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*
short
coaxial
cable.
The two auxilary comparator circuits are also
connected via
front panel BNC connectors and the threshold controls
are
in
line with them for ease
of identification and use.
The unit's power
switch and pilot
light are also on the
front panel,
but
the fuse
is
located
on the power supply tray in the
back.
The peripheral circuitry is mounted on
a
long, narrow strip
of vector perf-board and attached to
the back of
the panel near
the top
so that
the input and output connections
to the panel BNC connectors
are
direct.
The power supply tray
is attached to the rear of
the panel
at
one
end.
The ac
line
cord
is hard-wired to the power supply tray and
exits
at
the rear.
The unit
is mounted
in
a standard
19-inch rack directly below
the processor interface and
connects
to
it with short
coaxial
cable.
The
fiber optic
cables
are attached and routed
to
the noise units
as needed.
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Appendix
B
TECHNICAL DETAILS OF SPECIAL INTERFACE BOARD
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Appendix B
TECHNICAL DETAILS OF SPECIAL INTERFACE BOARD
.
Introdu ction
The special
interface board contains
several major functional
components
:
•
Command output
•
Real-time
clock
•
Input
data
to LSI-11
•
Output
data
from LSI- 11
•
B- decay channel
•
Noise
diode
channel
•
Pseudorandom shift
register
•
Counters
.
The DRV I I -P board from Digital Equipment Corporation contains
a
prewired section for address
decoding and interrupt handling.
The
description
of
these sections
as well
as
PIN assignments may be found in
the Digital Components
Group DRVII-P Module Users'
Manual.
All pin
references
on the schematic prints may be
found in this
manual.
We have
followed
a
chip placement procedure that differs slightly from the one
shown in the
manual.
Columns
are
labeled on the component
side
of the
board.
With
the
bus
contacts
facing
you we
label
the chip positions
A
through L starting on the
left.
Noticing that the hole positions
are
numbered on the board
0 through
64,
a chip may be positioned by specifying
its
column
letter and the hole position for
chip pin number
1.
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.
Functional Description
a
.
Command Output
The
special interface board functional commands
are completely
contained in
a
single byte
(74LS374).
All outputs
from the LSI-11 are
strobed per
the DLVII-P protocol
through
a
NOR decoding
gate
(74LS02).
The function of each
of
the
command bits
is
shown in Table
B-l
.
b
.
Real
Time
Clock
The time base
for
the real
time
block
is
derived from
a standard
crystal-controlled oscillator that
is
divided by
10^
in three stages with
74LS390 dividers.
Depending upon the tick-select
bit
in the
command byte,
either
a
10-kHz
or an
0,1 -Hz
clock is
gated into
a
16-bit
countdown counter
(4-74LS193
counters).
These
counters may
be preset
from
a
16-bit
register
that
is under software
control
(described below).
Two 74LS74 dc flip-flops
ensure
:
•
That
the
clock enable pulse
starts
the timing
countdown.
•
That
at
the
end
of
countdown,
the
clock
is reset to
initial
conditions
and restarted.
A 74LS123
one-shot
is used
to produce an interrput
signal
(called
real-time block pulse)
that
enables
the DRVII-P interrupt protocol and
is
presented
to the outside world through 74LS04 inverter/drivers
,
Depending upon the
clock select
bit, either the above process
is enabled
or the real-time block pulse
is
derived from an external source
through
a
74LS04.
c
.
Data
Input
to LSI- 11
The DRV11-P allows
for up to four different addresses
to be
decoded from the Q-bus
,
and thus
four different
16-bit
registers have
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*
%
Table
B-l
DEFINITION OF COMMAND-BYTE BITS
Number
Name
Function
Go
Start
clock when asserted;
stop clock when
not asserted
Tick select
Clock tick is
0.1
s when asserted;
clock
tick is
100 ps when not asserted
Clock select
Internal clock
is disabled and external
clock input
is accepted when asserted
Diode
data enable
Random byte from diode when asserted
Decay data enable
Random byte from P-decay when asserted
Pseudorandom data
Random byte from shift
register when
enable
asserted
Interrupt enable
Enable interrupt
from real-time
clock when
asserted
Not used
been provided for
data
input
to
the LSI-11.
The
two bytes
of word
contain the diode noise random data byte
(LOB)
and P-decay random data
byte
(HOB);
Word
contains
the input
count rate
for each source,
-3
respectively
(LOB is the number
of diode pulses per
s,
and the HOB
—2
is
the number
of electrons per 10
s);
Word
contains the diode tempera-
ture information and pseudorandom course data byte in the HOB and LOB,
respectively,
and Word
is unused.
To convert
the 8-bit temperature
data
to degrees
centigrade, use
the following relationship:
T = data byte/1280.0
The data in
a given word are strobed on to the Q-bus via the DRV11-P
protocol and the 74LS32 decode OR gate.
Data are clocked into
the output
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registers
either by the selected data source bit
in the command byte
or
from the strobes derived from the appropriate scalers,
d
•
Output
from the LSI-11
Two output words may be
latched into 74LS374 registers
from the
LSI-11 Q-bus,
The
LOB
of Word
is
the
command byte described above.
The HOB
of
this word
is an
8- bit
seed number for the pseudorandom shift
register.
Word
is
a 16-bit
integer representing the number
of ticks
that
must elapse
before the real-time
clock
causes
an interrupt.
The
strobe
logic from the 74LS02 NOR gate
is
determined by the DRVII-P protocol,
e *
B-Pecay Channel/Noise Diode Channel
Both random source channels
are handled identically.
A logic
pulse from the optical receiver
is
presented to
a
74LS123
one-shot with
a reset
time
of approximately 50
ns.
It
is also presented to a second
74LS123
one-shot
gated by
a symmetric
1-kHz
clock.
This
one-shot provides
a
50-ns
”dead zone”
centered about either transition of
a divide-by-two
74LS74.
This
ensures
that when
the 8-bit
shift register
(74LS164)
is
strobed by the
1-kHz
clock,
the register will
not
shift during
a divide-
by-two transition.
This added
logic feature eliminates
a small bias
in
favor
of
a binary one state
due
to differential rise and fall times
of
TTL logic.
The output
of the shift register
is
bits
of random data
toggling at
1 kHz.
These data are presented
to the appropriate
input
of
the 74LS374
latches.
Data from these
latches are strobed onto the
bus
at the
leading edge of
the RTCP derived from the real-time clock time
out.
f
.
Pseudorandom Shift
Register
According to the Kendall algorithm
a pseudorandom 8-bit
shift
register may be constructed by feeding back the Mod
2 summation of
a
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