dataesr/scientific-paragraphs-categorization huggingface dataset:
StreamFlow has been designed around two main principles: 1. Allowing the execution of tasks in multi-container environments, in order to support concurrent execution of multiple communicating tasks in a multi-agent ecosystem; 2. Relaxing the requirement of a single shared data space, in order to allow for hybrid workflow executions on top of multi-cloud or hybrid cloud/HPC infrastructures. StreamFlow source code is available on GitHub under the LGPLv3 license. A Python package is downloadable from PyPI and Docker containers can be found on Docker Hub. More details about the tool and its applications can be found in the StreamFlow website  11. Compiler Technology for Mixed-Precision Support. Many applications of HPC are error-tolerant, a characteristic that can be exploited -either in hardware or in software -to achieve important savings in system costs or power efficiency improvements  [69].
Hardware-based proposals take advantage of inherent sensor limitations, redundant data, and reduced precision input, or introduce additional uncertainty by adopting design features that produce approximate results. On the other hand, software-based approximate-computing approaches such as floating-point optimization or loop perforation allow to trade-off algorithm exactness for a more efficient implementation  [65]. To this end, high complexity of modern applications makes approximate compilers increasingly important. We aim to focus on mixed-precision compilers  [29] , which are a subset of approximate compilers. Recently, new data types specifically geared for mixed-precision are emerging, such as Posit  [49]  and BFloat16  [26]. Posit are a new compressed floating-point data format for which University of Pisa has developed a SW library called CppPosit  [34, 33].
From the first results of applying the CppPosit library to AI/DNN problems, Posit can lead to the same processing accuracy of single-precision floating-point but with a data compression from a factor 2 to 4  [34, 33]. This means that applying Posit to the application cases (HPC, HPDA and AI/CNN) has the potential to reduce data storage issues and allows for fast data movement. BFloat16 (Brain Floating Point) is used in upcoming Intel AI processors (NERVANA), XEON processors, Google Cloud TPU and ARMv8. 6-A, as well as in RISC-V extensions  [77]. In contrast to other standardized 16-bit floating point formats, BFloat16 offers a greater dynamic range and higher compatibility with the conventional single-precision floating-point format defined by the IEEE-754 standard. In TEXTAROSSA, we aim at exploiting and extending the tools for precision tuning developed as part of the H2020 FETHPC ANTAREX project  [64]  collected in the TAFFO framework  [30, 31].
The TAFFO framework is implemented as a set of plugins for the LLVM compiler. Based on programmer hints expressed as attributes, TAFFO performs value range analysis, data type and code conversion, and static estimation of the performance impact, automatically producing a mixed-precision application with statically-guaranteed error bounds. TAFFO is language-independent, supports data types ranging from fixed-point to standard floating-point formats, and allows the user to finely tune the performance-precision trade-off to their needs  [28]. The extensions to TAFFO will allow it to cover a wider range of target platforms, such as FPGAs through integration with the TEXTAROSSA High Level Synthesis (HLS) toolchain. Additionally, we aim to include support for emerging data types such as Posit and BFloat16, expanding the use of the tools to heterogeneous systems with reconfigurable components, and to improve the performance estimation by exploiting recent analysis techniques  [39]  as well as a deeper understanding of the target processor pipeline.
In general, given the reference hardware platform and the application use-cases, the TEXTAROSSA project would represent an extremely interesting testbench for exploring novel power and energy management strategies, by operating at both software and hardware level. At the hardware level, for example, we can provide a major contribution, by instrumenting the computing architecture with ad-hoc power monitors  [74]  and controllers  [71, 60] , in order to minimize the monitoring latencies, while increasing the effectiveness of the management policies. On the software side, we start from an already existing resource management framework  [17] , and aim at extend it with the support for the new target hardware, the integration of the precision tuning mechanisms and the introduction of new platform-specific resource management policies.
Calculations can be done even with simple bit manipulations on the Posit format without extraction, further decreasing the complexity of the operations. It is thus possible to enhance memory bandwidth, and lower level cache utilization, power footprint, and throughput of the arithmetic units. Within TEXTAROSSA, a RISC-V unit will be extended with support for alternative data representations, including fine-grained reduced precision floating point  [77]  and Posit arithmetic. To complement the hardware IP developments, the LLVM compiler, also adopted in EPI, will be extended for Posit and data compression support and real-world HPC applications and CNN kernels will be ported to leverage the IP. Fast software co-design will be enabled through software implementation of Posit in the CppPosit library  12.
Two approaches will be followed: the first called light PPU (Posit Processing Unit) will add Posit to/from float and Posit to/from integer converter to a RISC-V 64b 6 stages core with ALU and FPU. This way, with minimal circuit overhead, estimated in less than 1%, and exploiting the instruction customization of RISC-V, the support of Posit8 and Posit16 is also added. Since with the light PPU, Posit processing replies on ALU or FPU back-end the advantage is mainly in the compression properties of Posits that allows a compact storage of large CNNs, while the inference part will be done using the FPU with floats. In the second approach a full PPU will be added to the RISC-V 64b core, replacing the FPU. This version will be suited to use Posits for both storage and inference. Beside the implementation of accelerators for new data formats, other analysis will be carried out to provide basic blocks to implement novel cryptosystems onto FPGAs, like multipliers for large binary polynomials  [76]  and decoders for post-quantum cryptography  [75].
The integration of the two-phase cooling system with the TTC is currently underway (Figure  5 ). The collected experimental data will be used to improve and validate the thermal models as well as for the design of the control policies. For what concerns thermal control policies, in TEXTAROSSA the integration of two-phase cooling will be made by means of a multilevel thermal control strategy, aiming to overcome the complexity of controlling an HPC platform from node to system level. To reduce overhead, we will exploit and extend the use of event-based control policies (patent pending) developed at Politecnico di Milano to provide effective thermal control with minimal overhead. As the fastest temperature gradients occur at the silicon active layer, we will use fast event-based control loops  [53]  acting on DVFS to limit the maximum operating temperature of compute elements.
Low-latency Communication between FPGAs The usage of FPGAs as accelerators is getting so widespread that even big cloud providers are now installing reconfigurable devices in their instances (e. g. on Microsoft Azure and Amazon EC2). Interaction of hundreds to thousands of FPGAs require a scalable approach to hold them together, allowing a low latency connection among them, but a definitive approach has to be found to let users make the most of their flexibility and in the meanwhile easing the usage for software developers. As an example, the latest version of the Microsoft Catapult fabric, puts a Stratix 10 device between each NIC on the x86 servers and the ToR switch, enabling a fast path for accelerators to communicate among themselves with a few microseconds latency. The Brainwave project  [32]  leverages this architecture to provide a deep learning platform for real-time AI inference on the cloud.
While this framework offers a very friendly interface for users to deploy their models on top of this architecture, it loses the flexibility of delivering the cores as black boxes, and providing an implementation of only a few pre-trained models. Our approach, on the other hand, let users full control of the platform, allowing the implementation of custom processing tasks on FP-GAs, still maintaining ease of usage by supplying a set of interfaces to integrate with the HLS tools developed in the project. This will allow developers to define a scalable application using a streaming programming model (Kahn Process Network  [50] ) that can be efficiently deployed on a multi-FPGAs system. TEX-TAROSSA is developing a communication IP and its software stack, providing the implementation of a direct network that allows low-latency communication between processing tasks deployed on FPGAs, even hosted in different computing nodes.
In more details, we will provide new high-performance algorithms and software modules for some of the so-called Colella's dwarves, that classified numerical methods crucial for science and engineering. In particular, we will focus on algorithms and software for sparse linear algebra, where data sets include many zero-values and are usually stored in compressed data structures to reduce storage and memory bandwidth requirements. Those data structures are generally accessed with indexed loads and stores, and main computational kernels are communication bound. We intend to develop and benchmark a library of kernels optimized for hybrid nodes embedding NVDIA GPUs in order to pursue node-level performance further than multi-node scalability. Scalability will be improved by leveraging overlap between communication and computation.
g. CNN) in subsequent processing layers and studying reduced precision and/or compression techniques for input data. These concepts define the RAIDER software application and its reference hardware platform, whose combination yields a distinguishing feature that is the capability of performing this distributed inference scheme with realtime constraints. FPGA devices are the key architectural elements enabling the implementation of the general RAIDER architecture in application scenarios characterized by very low-latency classification requirements. In fact, these devices allow the implementation of data transport and processing stages characterized by a highly predictable and low latency. Wrapping up overview and studies concerning available low-latency communication IPs and frameworks for Neural Networks (NNs) deployment on FPGA to finalize a preliminary testbed for a distributed data-analytics system.
Henceforth having the possibility to evaluate pros and cons of a programming model focused on the realisation of a real-time AI-based data analytics heterogeneous distributed system. For this purpose, a distributed HLS development framework is required, hence we will work toward the extension of one of those frameworks, namely Xilinx Vitis, in order to be able to deploy in a straightforward manner multi-FPGA distributed low-latency applications, such as RAIDER. It shall be done integrating INFN set of Interconnection IPs (switch, low-latency data channels) in the Xilinx Vitis framework also through the definition and implementation of the full software stack supporting those IPs for the very low-latency data transfer between processing tasks deployed on the same FPGA (intra-node communication) and on different FPGAs (inter-node communication), in order to offer hardware support for the execution of applications developed according to the streaming programming models on a system made of multiple interconnected FPGAs.
The careful design and implementation of the HW/SW interface, through the Vitis HLS flow to define the communication protocol (HLS communication primitives) and to map the I/O ports of the Vitis HLS flow on those provided by the communication IPs will be of great importance to fully exploit the potential of the hardware. Brain Simulation (DPSNN). INFN started tackling neural simulations with its own engine, the Distributed and Plastic Spiking Neural Network (DPSNN), which is a scalable C++/MPI code for HPC platforms at extreme scales simulating the spiking dynamics of a brain cortex modeled as a grid of cortical columns populated with neurons and their interconnecting synapses. It has been used to first model brain cortex behaviour -with a special focus on sleeplike states  [58]  -and to gauge compute and power efficiency on different architectures  [12].
Coupled with the huge set of tools for analysis, visualization and data transformation available to the Python user, NEST allows for a compact yet expressive way to perform even very involved neural simulations. INFN has used NEST to implement a biologically-inspired thalamo-cortical model which is able to be trained in classification of handwritten digits from the MNIST dataset and then mimic the wake-sleep cycle, in order to test the enhancing effects of sleep on the quality of learning and recognition  [27] , even in noisy environments  [48]. Smart Cities video surveillance. Implementing distributed video surveillance systems in the context of smart cities provides a huge amount of data for processing, using also AI techniques for detection and classification. Possible applications are related to safety versus Covid-19, e.
The HEP community, and in particular the LHC experiments, have started an experimentation with a few products, like Alpaka  [70] , Kokkos  [59] , Intel OneApi and SYCL. In TEXTAROSSA, we plan to select a representative set of applications, mission critical in their scientific domains, and evaluate the porting to the frameworks. Whenever successful, a thorough benchmarking will follow on the main target platform, and auxiliary ones. A first target for migration is certainly the collection of high-level software libraries used by the LHC experiments for simulation and data analysis. They include Geant4  [4]  and Fluka  [45]  for particle-matter simulation, the use of high-level analysis tools like those in ROOT  [25] , and simulation packages of high-energy collisions. A design activity will be focused to optimize these software frameworks for the realization of code bases able to execute on multiple architectures, including the next generations of pre-Exascale and Exascale European HPC systems.
Heterogenous architecture based on GPU/FPGA is already used to reduce the huge processing time in MD simulations. Its programming model provides a top-level abstraction for low-level hardware routines as well as consistent memory and execution models for dealing with massively-parallel code execution. A standard programming model is OpenCL, which is composed of one CPU-based "Host" controlling multiple "Compute Devices" such as GPUs and FPGAs. Each of these coarse-grained compute devices consists of multiple "Compute Units", and within these are multiple "Processing Elements". At the lowest level, these processing elements all execute OpenCL "Kernel Functions". These kernel functions compute the forces by involving in an n-body interaction a particle system on which all coordinates are fixed during the force computation that can be parallelized for the different values of each particle.
In terms of streams and kernels, this can be expressed as the kernel function shown in the pseudo-code of Algorithm 1. Reverse Time Migration (RTM). The Reverse Time Migration application and mini-kernels are used within EPI to co-design the STX Accelerator and have been ported to FPGAs within the EuroEXA project. The respective kernels will be analysed to which extent they can leverage the new, energy-efficient, capabilities like Posit arithmetic and lossy compression to enhance performance and energy efficiency. The RTM kernels are stencil-based kernels. Hence, they provide conclusions on many stencil based applications. Reverse Time Migration by FHG for HPC applications to Oil & Gas and Geo-Services.
Objectives: Transcriptional regulatory modules are usually modelled via a network, in which nodes correspond to genes and edges correspond to regulatory associations between them. In the model yeast Saccharomyces cerevisiae, the topological properties of such a network are well-described (distribution of degrees, hierarchical levels, organization in network motifs, etc. ). To go further on this, our aim was to search for additional information resulting from the new combination of classical representations of transcriptional regulatory networks with more realistic models of the spatial organization of S. cerevisiae genome in the nucleus. Results: Taking advantage of independent studies with high-quality datasets, i. e. lists of target genes for specific transcription factors and chromosome positions in a three dimensional space representing the nucleus, particular spatial co-localizations of genes that shared common regulatory mechanisms were searched.
Introduction Normal cell functioning requires appropriate gene expression, which depends on multiple regulatory layers (see  [1]  for review). In this context, transcriptional regulatory modules (TRMs) were extensively studied (for instance  [2] [3] [4] [5] ). By definition, a TRM is a set of genes for which transcriptional activity is modulated by a specific transcription factor (TF)  [6]. In the model yeast Saccharomyces cerevisiae, TRMs are well described  [2] [3] [4] [5]  and public databases like YEASTRACT  [7]  or SGD  [8] , provide lists of target genes for any TF. All together TRMs were explored to better understand their individual organizations, but also their collective relationships  [4, 5, 9, 10]. In most studies, questions were addressed via a representation of TRMs as networks.
cerevisiae genome at interphase. The TRMs were explored from a new perspective, which integrates functional and spatial information presently available, and addressed the following question: are target genes associated to a common TF (TRM) randomly disseminated within the nucleus, or are they preferentially co-localized? In the literature, this question was only partially answered, focusing essentially on spatial distances between genes coding for TFs and associated targets  [15]. Our analysis represents an additional step in this context, reporting all distances between genes that belong to any TRM, as described in the latest release of the YEASTRACT database. Statistical parameters are provided, to quantify the intensity of potential bias observed in distributions of pairwise Euclidean distances calculated between lists of genes.
Main text This study extends on two previous analyses of transcriptional regulatory modules, recently presented in the literature. The first one is that of Monteiro et al. [2] , published in 2020. The authors assessed the regulatory features of the current transcriptional network of S. cerevisiae, taking advantage of the latest release of their YEASTRACT database, which comprised almost 200,000 interactions including 220 TFs and 6886 target genes. The second one is that of Sun et al. [15] , published in 2019. The authors used the 3D model of S. cerevisiae genome proposed by Duan et al. [12] , to study the spatial organization of the regulatory network of S. cerevisiae. We propose that the perspectives and the data from the two studies can be elegantly combined to increase the scope of the results presented in each of them.
cerevisiae. They concluded that "the transcriptional regulatory network of S. cerevisiae presents an optimized structure in space to adapt to functional requirements". Undoubtedly very promising, we think that this conclusion (i) suffers from the use of transcriptional regulations, which were only partially verified and (ii) lacks individual analyses of TRMs. The work presented in this article was performed in three steps. First, the TRMs were extracted from the study of Monteiro et al. [2]. The supplementary data provided all the YEASTRACT transcriptional regulations, annotated according to "binding evidence", "expression evidence" or "both". We decided to focus on regulatory associations which relied on "binding evidence" only. They represent 176 TFs with 6475 target genes, connected with 45,209 associations (23% of the full regulatory associations dataset).
e. highest deviation from the distribution of all targets) are shown in Fig. 2. An interesting situation, regarding the Upc2 transcriptional module, is detailed in file 6. Finally, an open-source tool was developed, for interactive visualization and exploration. Source code is available on GitHub https:// github. com/ data-fun/ 3d-scere and the tool is freely usable online at https:// 3d-scere. ijm. fr/. It allows the visualization of any list of genes in the context of the 3D model of S. cerevisiae genome (Additional file 5 for screenshots). Further information can easily be added, like functional annotations (GO terms) or gene expression measurements. Qualitative or quantitative functional properties are highlighted in the large-scale 3D context of the genome with only a few mouse clicks.
Availability of data and materials Source code written to generate figures is available on GitHub: https:// github. com/ data-fun/ 3d-scere-scrip ts. Source code written to develop the web tool (3d-Scere) is also available on GitHub: https:// github. com/ data-fun/ 3d-scere. Results are archived in the Zenodo repository: https:// zenodo. org/ record/ 58411 77.
Activated NSCs (i. e. aNSCs) were assigned by their expression of Egfr and Ascl1, but exclusion of Dlx1 and Dlx2, whereas transit-amplifying progenitors were defined by an elevated expression of these markers, but low expression of Sp8, Gad1 & Gad2. Finally, we used broad generic markers defining the neuroblast pools (NBs: Dcx, cd24a, and Nrxn3) as well as cells of the oligodendroglial lineage cells (OLglia, Pdgfra & Sox10), and concomitant high expression of S100b and Aqp4 for astrocytes (Astros) (Fig. 1C-D ). These initial analyses identified qNSCs as the prime cohorts of cells captured in our datasets (52% of all cells), followed by aNSCs and TAPs (17% each). Ependymal cells (6. 6%) and Astros (5. 4%) were lowly represented. The restricted proportion of oligodendroglia (1%) and NBs (0. 5%), underlined the accuracy of our dorsal V-SVZ microdissection.
, 2013) ; 2) the correlation of ribosomal transcripts with NSC activation (aNSCs); and 3) the rapid sequence of cell cycle initiation, mitosis and neuronal differentiation in TAPs and NBs (Fig. S3A-B ). Similar Biological Processes (BPs) were highlighted by an over-representation analysis performed on genes up-and down-regulated at transitions between these differentiation stages (Fig. S3C ). This analysis highlighted the gradual downregulation from qNSCs to TAPs/NBs of genes involved in pluripotency, gliogenesis, as well as glycolytic metabolism, and the inversely correlated upregulation of genes involved in ribosome biogenesis and mitosis (Fig. S3D ). We next assessed the cell lineage progression within our datasets by performing non-supervised RNA-velocity lineage trajectory reconstruction (La  Manno et al.
2C , Data S1). To gain further insights into this central aNSC3 population (569 cells), we performed additional sub clustering at higher resolution, producing 6 further clusters. Analysis of the differential expression of key transcription factors (TFs) among these clusters (Fig. 2D  & E, Data S2) supported that the aNSC3 cluster is composed of a mixture of cells primed for differentiation into different lineages, rather than a homogeneous population of multipotent NSCs. In particular clusters 1 and 2 expressed TFs associated with oligodendrogenesis (e. g. Olig1/2), while clusters 4 and 5 expressed TFs associated with neurogenesis (i. e. Dlx2 and Neurog2, respectively). Interestingly, TFs defining subpallial and pallial lineages segregated across clusters 3/4 and 5/6 respectively, demonstrating the coexistence of both lineages within our datasets (Fig.