dataesr/scientific-paragraphs-categorization huggingface dataset:
https://doi. org/10. 1371/journal. pone. 0180198. g006 except for the parameters, threshold and gap that varies (Fig  8 ). We also tried several mismatch values but they did not change substantially the results and corresponding graphs almost completely overlapped graphs with the same gap value in Fig 8 so we omitted them. Pre-processing genomes and collapsing clusters of tandem duplicates (still with tandemGapMax = 5), did not change significantly the results of Cyntenator. Figs 7 and 8 can be reproduced following the protocol dx. doi. org/10. 17504/protocols. io. idnca5e. The quality of the detection of conserved segments is estimated for each algorithm using three types of items: extremities of conserved segments, adjacencies of genes in conserved The refinement methods described in this manuscript are imr (Identify Micro-Rearrangements), imcs (Identify Mono-genic Conserved Segments) and t (Truncation).
Finally, it would be of great interest to simulate errors (assembly errors, annotation errors or even errors in gene trees) in addition to the main known events that alter genomes during evolution (S14 Fig). This could help us understand how these errors affect algorithms-given that some algorithms might be more robust to errors than others. However, relevant statistics on errors in genomic data (e. g. vertebrate genomes of the Ensembl database) are difficult to obtain. We hope that an increased consideration of micro-rearrangements will help detect such remaining errors. copies and copied genes: A. a is not the same gene as gene A even if they are both in the family of gene A. Furthermore if gene A was once more duplicated there would be an instantiated copy named A. b newly inserted in the genome and if the gene A.
(PDF) S10 Fig. Matrix of homologies calculated with i-ADHoRe 3. 0 where a segment of pre-processed human chromosome X is compared to a segment of pre-processed mouse chromosome X. Yellow dots represent homologies in a base_cluster and blue dots represent the "confidence intervals" around the base_cluster, see the documentation of i-ADHoRe 3. 0 [6]. Here also, after the pre-processing of i-ADHoRe 3. 0 (filter + collapse of clusters of tandem duplicates), artificial gaps remain within a diagonal of a conserved segment. (PDF) S11 Fig. Workflow for the detection of conserved segments. The scripts/ folder, in the LibsDyogen deposit, provides tools to prune. nhx gene trees and extract gene families from pruned gene trees. The new version of PhylDiag (from v2. 0. 0-alpha) includes the pre-processing and post-processing steps (https://github.
The work of  JMEXL  and  HRC  has been funded by  Centre National de la Recherche Scientifique (CNRS) , the program " Investissements d'Avenir " launched by the  French Government , the  Agence Nationale de la Recherche (ANR)  [Grant:  Ancestrome  Project  ANR-10-BINF-01-03 ] and received support from the  MemoLife  project [ ANR-10-LABX-54  MEMO LIFE]. The work of  HRC  has also been funded by  Paris Sciences et Lettres (PSL) Research University  [ ANR-11-IDEX-0001-02 PSL Ã Research University ]. The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript.
Multi-level annotation in the ANNODIS project: preliminaries The research presented here started with the ANNODIS annotation project, which can be described as a large-scale discourse-level annotation experiment calling upon different discourse models and different genres of written French language texts 1. The project comprised two distinct approaches, respectively labelled bottom-up and multi-level. Bottom-up and multi-level annotations were applied to different corpora, for reasons which are explained in 4. 2. 2, but a set of texts was annotated in both frameworks to allow a direct comparison of the approaches (ANNODIS duo, see 5. 3). The bottom-up annotation, conducted according to Segmented Discourse Representation Theory  (Asher, 1993) , focused on the identification of rhetorical relations.
The association of exhaustive NLP-generated linguistic information (pre-marked features) with human intuitions (manual annotation of structures and cues) produces rich data, opening the way for new investigations using corpus-linguistics or data driven methods. Two multi-level structures have been annotated according to this methodology within the ANNODIS project--topical chains and enumerative structures--, but the present paper deals solely with the latter. In line with the approach outlined in Section 2, the annotation project described here differs in several major ways from previous discourse annotation initiatives, such as the Penn Discourse Treebank (PDTB  Prasad et al. , 2008) , the RST (Rhetorical Structure Theory) Treebank  (Carlson et al. , 2003) , or the Discourse Graphbank  (Wolf et al.
Cue associations The examples make it clear that most ESs are signalled concurrently by several kinds of ES-cues. The previous section gave an insight into the frequencies of individual ES-cues without taking into account their co-occurrence. Yet our hunch, as stressed in Section 2, is that textual patterns are not just signalled by discrete clearly identifiable dedicated markers, but by configurations of ES-cues functioning as complex discourse markers. In such a perspective, a discourse function should not be attributed to a particular lexical expression--on the basis of a specific semantic or pragmatic value--but rather to this expression when it occurs in a particular context or configuration (cf. the pattern formed by the series of paragraph-initial adverbials in Example 1). The ANNODIS resource now provides us with data to investigate this hypothesis, and this is what we attempt below using the notion of cueset.
An embedded real-time indexing engine for live radio stations requires a high-speed parallel advanced audio coding (AAC) decoder architecture to decode hundreds of compressed audio streams broadcast in the digital radio mondiale band. Several AAC hardware core units must be integrated into a single chip and synchronized with a global controller to achieve such high performance. This paper proposes a new parallel AAC decoder architecture to address this challenge. The proposed architecture includes multiple AAC decoder core units, each of which achieves a speed-up by a factor of 2 compared with the existing AAC decoder core units while using optimal logic resources. The proposed architecture overcomes several challenges faced by existing architectures. The Huffman decoder module decodes one word per clock cycle regardless of word length, and a smaller lookup table size is achieved for the inverse quantization module.
I. INTRODUCTION Broadcast radio in Digital Audio Broadcasting (DAB and T-DMB) and Digital Radio Mondiale  [1] ,  [2]  (DRM30 and DRM+) are promising radios that contain various data, such as music, news, sports, weather services, traffic information, commentary, drama, advertising and an increasing amount of metadata to help identify and organize content. Broadcasting information will substantially enrich the diversity of available content and also open the way to index the content either via existing metadata tags or using original features extracted from the radio signals themselves. Just as it took web browsers to transform the Internet from a simple computer network into a searchable worldwide database, new types of navigators capable of searching and organizing the multimedia streams now available on broadcast radio will be developed.
Unfortunately, the conflicting needs of systems exploiting these streams have slowed the development of new products in this emerging market. Today, software-defined radio techniques based on FPGA devices allow hardware designers to imagine the power of such media monitoring systems on a single chip. This advancement opens the door to a wealth of exciting new consumer electronics applications. DRM30 is a broadcasting radio system that replaces the classical analog radio system. DRM30 introduces high-quality audio combined with rich information about the broadcasted program. Processing this type of data requires a new generation of radio receivers. Ideally, the DRM30 receiver should be able to demodulate more than 1,000 streams simultaneously to monitor all the broadcasted programs. Therefore, a new radio receiver architecture called SurfOnHertz  [3]  has been proposed.
II. RELATED WORK AAC decoders have been implemented and designed using many approaches in the past decade. Software (SW) decoders are used most often because of their high flexibility and short development time  [5] ,  [6]. A major development focus has been to accelerate SW decoders. Reduced instruction set computing (RISC) microprocessors have been widely used for this purpose. Takamizawa et al. [7]  developed a SW AAC decoder for an embedded RISC, but it lacks hardware utilization and non-optimum scheduling. Ryu et al. [8]  introduced the digital signal processor (DSP) as an alternative to the RISC approach. Mesarovic et al. [9]  presented an optimized and cost-effective implementation of the decoder on a dual DSP. Tsai and Chen  [10]  used a co-design approach. The bitstream parser was performed by software, and the highercomplexity portion was solved by hardware.
With this approach, over 91. 26% of the processor-based loading was substituted by hardware IP. Tao et al. [11]  introduced another co-design solution verified on Xilinx XUP FPGA. The Huffman and inverse modified discrete cosine transform (IMDCT) hardware accelerator modules were developed to accelerate the decoding process. The application-specific integrated circuit (ASIC) approach is considered the best solution in terms of power consumption and area costs. Zhanget al. [12]  implemented a low-power AAC decoder on ASIC, with a power consumption of 20 mW. Another ASIC implementation presented by Tsai and Liu  [13]  consumes considerably less power (2. 45 mW). An ASIC MPEG-4 targeting low-power systems was presented by Liu et al. [14] , and a very-lowpower audio decoder compatible with DAB/DAB+ was presented by Wang et al.
, with a power consumption of only 10. 4 mW  [15]. The FPGA is considered an alternative hardware approach to ASIC. Although it consumes more power, FPGA-based platforms are more flexible than ASIC-based platforms. Renner and Susin  [16]  presented a full implementation of an AAC decoder used for Brazilian Digital Television. The designed architecture is capable of decoding a lowcomplexity audio signal in real time with a clock frequency of 4 MHz. Another FPGA-based implementation was introduced by Sampaio et al. [17]. The design was implemented on an Altera Cyclone II FPGA with NIOS II/s as a processor and was able to decode up to six audio channels. Previously developed designs focused their approaches mainly on (i) satisfying the real-time constraint while decoding one compressed audio stream and (ii) minimizing the power consumption by performing an ASIC implementation.
The time samples are in pulse coded modulation (PCM) format. The proposed AAC decoder architecture includes only the essential required tools to run an LC profile to achieve a smaller area and shorter decoding time. It also supports the audio data transport stream (ADTS) format, whereas decoders in previous work supported the audio data interchange format (ADIF). The main difference between the two formats is that the ADIF stream has only one header, whereas the ADTS stream consists of multiple frames, each with its own header, which is a useful way to simplify radio broadcasting.
C. DATA DE-MULTIPLEXER AND HUFFMAN MODULE The DEMUX_HUFF block architecture is shown in Fig. 7. It receives the input bitstream and parses it to extract the side information. Then, it decodes the scale factors and   audio spectral data using the Huffman decoder. The decoded scale factor data are written to the scale factor (SF-RAM), whereas the decoded audio samples are written to the spectral data (SD-RAM). The key novelty of this design arises from the fact that we combine bitstream parsing and the decoding operations in the same module to save area and optimize the central controller.
The barrel shifter contains the Huffman encoded bits. All inputs of the codebooks' PLAs are tied to the barrel shifter output, which makes the search process more efficient and able to perform in parallel. Each HCB PLA has two outputs, the decoded word and its length, which is used to calculate the new shift amount of the barrel shifter. The scale factor data are decoded using the Huffman codebook (HCB_SF), and then,  the spectral data are decoded. Depending on the codebook dimension, the resulting decoded word is de-grouped into 2-tuple (W and X ) or 4-tuple (W , X , Y , and Z ) coefficients according to the standard  [4]. The Demux_Controller sends select signals for the MUXs, write enables and addresses for SD-RAM and SF-RAM. The Huffman decoder controller FSM is shown in Fig. 9. The state ''Huffman Decode'' indicates that the bitstream is decoded in one clock cycle due to the PLA approach.
D. INVERSE QUANTIZATION AND RESCALING MODULE The inverse quantization function is expressed as X inv_qunt = sign X qunt 4/3 , (1) where X qun is the quantized coefficients (spectral data) and X inv_qunt is the inverse quantized coefficients, which are rescaled by a gain value as described in (2) to obtain X rescale , as illustrated in  (3). gain = 2 0. 25×(sf -100) , ( 2 ) where sf is the scale factor. X rescale = X inv_qunt × gain. ( 3 ) The IQ_RESC module reads the spectral data and applies the inverse quantization to them. Then, it rescales the outputs using the rescaling factors and writes the result to the IQ_RAM. The IQ_RESC architecture is shown in Fig. 10. The operation of this module is divided into two stages:.
1) INVERSE QUANTIZATION STAGE The algorithm used in FAAD2, an open-source software AAC decoder, is translated into hardware. There are two probabilities for the IQ operation depending on the spectral coefficient value. If the value is less than 1,026, the IQ is calculated using a direct lookup table (LUT); otherwise, the spectral coefficient is rescaled by a factor of 8. The scaling operation is a shift to the right by 3 bits to generate the LUT address. Then, a direct linear interpolation method is applied to the LUT output.
2) RESCALING STAGE The output from the previous stage is passed to the rescaling module, as shown on the right side in Fig. 10. It calculates the exponential part of the rescaling gain and then multiplies the IQ data by the gain. The multiplication is performed by a logical shift right/left (LSL/LSR) operation. The exponent part of the gain (EXP) register content is shifted by the IQ data value. If the fraction part of the scale factor is not equal to zero, it will be multiplied by one of those values {0, 2 0. 25 , 2 0. 5 , 2 0. 75 }, which are pre-calculated and stored in the power ROM (POW ROM).
2) PRE-IFFT OPERATION The controller reads the inputs of the complex multiplier from the IQ RAM. Then, it latches them into real data and imaginary data registers (Reg_RE, Reg_IM). It performs the multiplication when the data are valid in those registers. At the same time, it fetches new data for the next multiplication operation and feeds the multiplication outputs to the IFFT module. This process is repeated 512 or 64 times according to the window sequence (window shape).
A. AAC DECODER VALIDATION PROCESS The design methodology and validation process are shown in Fig. 14. First, a single AAC core unit was simulated with EDA tools. The simulation results were compared to the bitstream decoded by a golden software. Next, a single AAC core unit was implemented on FPGA and tested by loading a test ADTS bitstream into ROM. A trigger signal was generated to start the acquisition of the decoded audio samples. The samples were stored in a text file saved on the local memory of a logical analyzer. The text file was compared to the one generated by the golden software. The final step of the verification process was to check the full parallel decoder architecture, including the global controller and stream buffers. An initial validation was performed by comparing the decompressed audio streams and the outputs of the golden software.
B. SIMULATION RESULTS The proposed architecture was simulated and compared to the reference model FAAD2 output. FAAD2 is a freeware opensource software AAC decoder, which has been explored, analyzed and then adopted to run in a fixed-point format. Fig. 15  shows a one-frame output from both the VHDL simulation of an AAC single core unit and the software reference model. The maximum absolute error is 0. 00002, and the root mean square error (RMSE) is 5. 61 × 10 -6. The consumed time in clock cycles for each block is shown in Table  1. These values are calculated for one frame, which takes 12,620 cycles to be decoded. The filter bank comprises 51. 35% of the total computation time. It is difficult to compare the simulation results with the related work because the number of implemented modules in each one is different.
D. PARALLEL DECODER PROTOTYPE FOR THE SurfOnHertz RECEIVER Fig. 16  shows the experimental setup of the designed DRM receiver. The prototype receives (0 -30) MHz DRM band signals from the signal generator via the front-end module and passes them to the channelizer. The outputs of the demodulators are decompressed using the proposed architecture. Next, the audio streams are indexed on the PC feeding a GUI, which allows users to search for the desired content extracted from the radio channels. In this first prototype, no extra cooling is added to the FPGA chip. However, it's advisable to install a heat sink on the final product since we use extensive physical resources of the FPGA. Table  4  shows the resource utilization results of the proposed decoder implemented on an Altera Stratix V GS FPGA platform.
We used various settings in the Quartus software to optimize resources utilization. The purpose is to be able to put as much AAC core units as possible. The decoder contains 25 AAC core units, which can decompress 50 parallel audio streams. The proposed decoder is scalable to a higher number of parallel streams. The full proposed decoder consumes 84% of the DSP blocks and 59% of the logic area due to the computation-intensive IFFT modules inside the filter bank. It requires a small amount of memory (20% of the available block memory). DSP blocks are considered the bottleneck to integrate more AAC decoder core units. The new FPGA platform generations contain more logic resources, more on-chip memory and more DSP blocks, thus meeting the scalability requirements to decode more audio streams.
VI. CONCLUSION This article presented a full-fixed-point AAC decoder architecture that allows for the rapid decompression of parallel audio streams and thus enables the indexing of DRM radio channels in real time. The global architecture consists of multi-AAC decoder core units, stream buffers, and a global controller. The core unit architecture includes the required tools to decode an ADTC bitstream with LC profile. It also supports a variety of sampling rate frequencies and operates in real time. Speed and area factors are considered in the design of the AAC core unit. An approach based on a PLA-like method has been implemented, making the search process for codebooks possible in parallel. The IMDCT architecture is fully pipelined and operates for two types of window size: short and long.
The proposed AAC decoder core unit can decode two frames faster than the best related work presented in the literature. Therefore, it enables a reduction in the number of required core units to decode N parallel streams by half and paves the way for the decoding of hundreds of compressed streams on a single chip. An initial prototype has been implemented on an Altera Stratix V GS FPGA platform. This prototype supports decompressing 50 parallel audio streams with an operating frequency of up to 50. 54 MHz.
LRR-RLKs Extraction, Phylogeny, and OGs On each of the 33 plant proteomes, the hmmsearch program was run to extract peptide sequences containing both LRR(s) and a KD  (Eddy, 2009). Sequences containing both LRRs and KD were classified into SGs using a global phylogenetic analysis  (Fischer et al. , 2016). First, the KD of all these sequences was aligned using MAFFT with a progressive strategy  (Katoh et al. , 2002). Then the alignment was cleaned with TrimAl configured to remove every sites with more than 20% of gaps or with a similarity score lower than 0. 001  (Capella-Gutierrez et al. , 2009). A similarity matrix was computed using ProtDist with a JTT model, and then a global distance phylogeny was inferred using FastME configured with default settings and SPR movements to optimize the tree topology  (Felsenstein, 1989; Desper and Gascuel, 2002).
SGs were defined manually in the global phylogeny using the Arabidopsis genes as reference  (Shiu et al. , 2004; Lehti-Shiu et al. , 2009; Fischer et al. , 2016). To extend this dataset to receptor kinases devoid of LRRs in their ECD (sequences annotated "No_LRR"), the BLASTP algorithm (default parameters) has been run SG per SG, using each of the 7,767 KD sequences to search a database composed of the 33 proteomes as query  (Altschul et al. , 1997). Blast outputs were parsed to keep only homolog sequences sharing more than 90% identity with the query sequence. The new "No_LRR" sequences retrieved by blast were assigned to the same SG as the query sequence. Then, phylogenies were inferred for each of the 20 SGs. Each group of sequences was aligned using MAFFT with an iterative strategy (maximum of 100 iterations)  (Katoh et al.
Structural Features Number of motifs and positions (LRRs (PF00560. 24) and KDs (PF00069. 16)) are outputs of the hmmsearch program (default parameters)  (Eddy, 2009). Island domains were determined based on predicted LRR positions in sequences. For SP and TM domains, the TMHMM and TOPPRED softwares have been used  (Claros and von Heijne, 1994; Krogh et al. , 2001). For the malectin domains in SG_I and SG_VIII-2, sequences of the domains were extracted in SMART and aligned to build hmm motifs with the hmmbuild program  (Eddy, 2009; Letunic et al. , 2009). For Cys-pairs, hmm motifs were built based on subsets of sequences known to possess these motifs  (Eddy, 2009).
Test of Positive Selection on Ancestral Branches Twelve sub-trees were considered: the OGs selected were those with a 'simple' organization, i. e. with a gene topology fitting approximately with the species tree. Three to four sequences among those that are the most closely related to the OG were selected from the whole SG tree as outgroup (Supplementary Figure  S4 ). The sequences were re-aligned and the alignment was cleaned as described previously  (Fischer et al. , 2014 (Fischer et al. , , 2016)). We ran codeml branch/site models implemented in the PAML4 software  (Yang, 2007). For each OG, the following branch partition was defined: all branches but one were tagged as 'background' branches and the branch between the duplication node and the node corresponding to the split between monocot and dicot tagged as 'foreground' branch.
, 2009; Fischer et al. , 2016). In our previous study  (Fischer et al. , 2016) , the LRR-RLK dataset contained 7,767 sequences possessing at least one LRR in their ECD. Since we focus on structural features of ECDs and presence/absence of the genes in LRR-RLK OGs in this present study, we included LRR-RLK homologues for which LRRs were completely lost or were degenerated in this new dataset. Thus, 593 sequences (prefixed "No_LRR") were added to the original set of 7,767 sequences which lead to a total of 8,360 sequences (Supplementary Table  S2 ). Within each of the 20 SGs, KDs were aligned and SG-specific trees were obtained using a likelihood-based method (PHYML) (Figure  1A  and Supplementary Material). Altogether, these LRR-RLK genes represent on average 0. 71 and 0. 66% of the monocot and dicot proteomes, respectively.