dataesr/scientific-paragraphs-categorization huggingface dataset:
In particular, in IUPAC encoding  [20] , specific symbols, referred to as degenerate, are employed to represent a sequence position that corresponds to a set of possible alternative nucleotides. Various algorithmic tools and software have been published to enable the study of IRs in genomes  [8, [21] [22] [23]. However, to the best of our knowledge, the only available tool that can meaningfully process IUPAC-encoded sequences is EMBOSS palindrome  [21]. In this paper, we develop an exact and efficient tool called IUPACpal as an alternative to EMBOSS palindrome (henceforth EMBOSS). We have implemented IUPACpal to mimic the workflow, parameters and output format of EMBOSS to better enable direct comparisons in performance as well as to minimise the learning curve of using our software. We show that IUPACpal compares favourably to EMBOSS.
The current palindrome application within the EMBOSS package uses a method by which every IUPAC symbol is assigned a single unique complement, by first taking complements of the underlying symbols of the represented subset of. For example, the complement of B = {C, G, T} is V = {G, C, A} , and therefore B ←→ V. We dub this scheme simple complement matching. However, if we choose to interpret IUPAC symbols as representing a set of possibilities, then this type of matching does not take into account all possible match scenarios. Consider for example the symbol R = {A, G} when compared with the symbol C = {C}. Under simple complement matching, the R and C do not match, despite the fact that R contains G, the complement of C. Because of this potential shortcoming, we define the degenerate complement matching scheme over the IUPAC alphabet.
Under this matching scheme, two IUPAC symbols I 1 and I 2 match if and only if there exists a pair of sym- bols σ 1 ∈ I 1 and σ 2 ∈ I 2 such that σ 1 ←→ σ 2. Note that the underlying algorithm of IUPACpal is independent of the matching scheme used. Though currently implemented to use degenerate complement matching, Fig. 1  Example of an IR. The sequence CT-CGC AGT CACCG-GA is an IR with a gap of 7 and a single mismatch towards the tail ends a modification of the matching matrix within the open source code permits other potential matching schemes to be defined. The matching scheme may therefore be chosen to fit the intended use case. We present a visualisation of both the simple and degenerate complement matching schemes in Fig. 2. Note that when considering sequences exclusively over the alphabet = {A, C, G, T} , there is no distinction between simple and degenerate complement matching.
Interface We have implemented IUPACpal in C++ under GNU/Linux. IUPACpal mimics the workflow, parameters and output format of EMBOSS to better enable direct comparisons in performance. By making the key features similar and output format identical, we also minimise the learning curve of using our software. Our application requests the following parameters: input file (0), sequence name (1), output file (2), minimum length (3), maximum length (4), maximum gap (  5 ), maximum mismatches  (6). IUPACpal is run with the following terminal command: Output is given in an identical format to that of EMBOSS, in which all the discovered IRs are identified by their index locations (1-based indexing) alongside their symbol representation. An example as applied to the IR from Fig. 1  is shown below:. /IUPACpal -f<0>-s<1> -o<2> -m<3> -M<4> -g<5> -x <6>.
However we see that IUPACpal completes execution significantly faster than EMBOSS. Consider for example the run-time with 9 permitted mismatches and a maximum gap of 500, where IUPACpal requires 10 1. 5 ≈ 30 s and EMBOSS requires 10 4 s to complete. Further to the comparisons with EMBOSS, an investigation was also made of the Inverted Repeats Finder (IRF) program  [8] , which targets a similar problem of identifying IRs. To enable a preliminary comparison, a test run of IRF was performed in accordance with the authors' example page  [28]. Using the same testing environment as previous tests on IUPACpal, IRF was able to process human chromosome 21 (approximately 46 million base pairs) within an average of 930 s. Equivalently a rate of 50,000 DNA symbols per second. Scaling the timing tests of IUPACpal results in a speed of 130,000 DNA symbols per second.
Accuracy of output The final testing performed verified that IUPACpal is capable of exhaustively identifying at least the same IRs as EMBOSS. In addition to ensuring the usefulness of our tool, this also serves to ensure that the increases in speed performance are a result of improved algorithmic efficiency and not the result of merely solving a simpler version of the problem. A Python script was written and included as part of the software package, to verify the commonalities of the output of both tools, in addition to identifying discrepancies between the two. It was found across numerous tests that IUPACpal does indeed identify at least the same IRs as identified by EMBOSS. In a small number of cases, it was found that EMBOSS did not identify certain instances of IRs, perhaps due to considering them equivalent to some smaller IR at the same centre.
The state-owned Enterprises (SEO) that manages businesses in the food sector, especially rice, is Perum Bulog. However, there were often reports from the public about the quality of Perum Bulog's rice. Such as the rice had contaminated with gravel or plastic and did not match with premium rice standards. Moreover, The distribution process of premium rice to outlet (RPK) found uncertainty over the arrival time of orders. It caused out of stock and lost sales at the outlet. This paper introduces a traceability system for the rice distribution process based on Android with QR Code technology. Furthermore, this paper discusses the system architecture and the development of traceability system design using the data flow diagram of the company's business process. The developed prototype system shows the system's functional requirements and can be used by stakeholders to monitor the production process and assist decision-making.
The technology used in the traceability system is an android system application and is connected to the internet network by integrating the 2D barcode system. According to Taibo Chen et al. (  2020 ), the traceability system with the 2D barcode system, especially the QR Code type, is relatively inexpensive and can record large amounts of data, besides being easy to adopt into companies. Meanwhile, Android provides an open platform for developers to create their applications for various needs. Aung and Chang (2014)  also suggest that smartphones and the internet will be the foundation for developing a traceability system where high-cost issues can be resolved. This paper aims to develop a traceability system using an Android-based QR Code to identify physical characteristics, specifications, and quality and maintain product image.
Data Flow Diagram The design of the Bulog QR Code Mobile application for integration information in every activity carried out by the company so that it can track and trace information accurately; steps are needed such as: designing a QR Code flow pattern system, designing a QR Code, designing a database and designing a user interface. (Figure  5 ) The design of the QR Code flow diagram system comes from the business process of Bulog Subdivre III Surakarta so that the QR Code can provide accurate information. QR Code Flow Pattern System 1, The supplier (Gapoktan, Task Force, Partners) sends lots of premium rice orders to the warehouse of Perum Bulog Subdivre III Surakarta. Quality inspectors check rice samples at Minilab. The quality standards of Bulog's Premium rice are water content max 14%, the minimum degree of foam 95%, broken grains max 20%, and groats grains max 2%.
After passing the quality test, the rice storage warehouse officer enters the data, containing the date of arrival of the rice, the supplier of origin of the rice, the quantity, and the location of the warehouse. This information is generated into QR code 1. QR Code Flow Pattern System 2, before the rebagging process (packing rice into 5 Kg packs). The scanning process is carried out on QR code 1. This process stores and identifies information about 5 kg packaged rice to the information system database. The packaging clerk performs the 5 Kg premium rice rebagging process in the warehouse. The 5 Kg premium rice packs rebagg depend on the marketing division's DO (Delivery Order). The shelf life of 5 kg packaged premium rice in the warehouse is 14 days. A QR code 2 will be generated and attached to each 5 Kg premium rice package in the rebagging process.
QR code 2 contains information regarding the rice production date and rice expiration date. (automatically filled, 6 months from the rice production date), packaging code, processing warehouse code, and rice mixture code. Premium Rice Order QR Code Flow Pattern System, Premium rice 5 Kg packs are sent and distributed to 9 warehouse complexes of Perum Bulog Subdivre III Surakarta. Distribution center officers enter information about the location of the storage warehouse. The data is stored in the information system database to be recorded and tracked quickly and accurately. The marketing division received requests for premium rice from RPK outlets. Premium rice with a shelf life of close to 14 days (based on QR Code 2 data) is sold automatically by the system. This system was designed to facilitate the delivery process, and the selection of premium rice sent to the RPK.
Database Design Database design using MySQL in its manufacture. The MySQL database will determine the relationships between existing entities. so that the application can run with the wishes that have been designed before. (Figure  6 ) The MySQL database system was chosen because it supports several features such as multithreaded, multi-user, and SQL database management systems (DBMS). This database was created for a database system that is fast, reliable, and easy to use (Budi Asmara, Septian, 2016).
Verification and Validation Verification and validation are done by testing using several brands of Android smartphones. Android smartphone brands that are tested on the BULOG Mobile application are Samsung A70 2018, Android 10, Samsung S20 2020, Android 10, Realme 5 Pro, Android 10, Xiaomi Mi 10, Android 10, Lenovo S5, Android 8, Redmi Note 7, 9, Vivo V20, android 10, Oppo Reno 4F, android 10, Xiaomi Redmi 5, android 9, Asus Zenfone 6, and android 10. (Figure  9 ). On Realme 5 Pro, Android 10, there are problems when scanning the QR Code because there are scratches on the rear camera. On the Lenovo S5, Android 8, there are problems when the application is run for a long time and has experienced a system crash due to the full smartphone memory.
IV. CONCLUSION Successfully designed a tracking system for the Distribution of premium 5 kg rice at Perum Bulog Sub Divre III Surakarta using a QR Code based on an android smartphone application. The design result is an application called "Mobile BULOG. " Testing the BULOG Mobile application obtained positive results and the benefits felt by Perum Bulog Sub Divre III Surakarta. Suggestions for further research are to improve the more attractive BULOG Mobile user interface. level of tracking should be done in more detail down to the farmer so that they can trace the problem down to the root.
I. INTRODUCTION M ODERN System-on-Chips (SoCs) are designed with heterogeneous architectures to support a variety of computationally intensive tasks in many application domains such as IoT systems, industrial automation, robotics, etc. These systems could consist of multi-core processors, or specialized hardware such as Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). The latter is used for accelerating complex operations and performing tasks concurrently compared to traditional processors. K-Nearest Neighbor is a supervised classification algorithm used in a variety of applications such as pattern recognition, computer vision and machine learning  [1]. However, kNN imposes significant computational workload since it has a linear scalability with the size of the dataset and the number of classes  [2].
g. image compression, encoding, etc. ). The latter one replaces computationally intensive blocks with approximate ones that implements the same mathematical operations. Data-oriented techniques target dataset modifications as "Dataset Reduction" and "Data Format Modification". Dataset Reduction aims at decreasing the number of processed samples through Downsampling and Downscaling. Downsampling includes adjusting the sampling frequency of a processing block or truncating the size of an acquired sample. Downscaling reduces the dimension of the data by adjusting the matrix or vector size for vector-based applications. As for Data Format Modification, it changes the data from floating-point to fixed-point representation to simplify the involved arithmetic operations. " Approximate computing can lead to significant improvements from algorithmic to circuit level.
1× speedup over a GPP based implementation is noticed. In  [14] , several architectures are presented, where each one adopt a single or multiple HLS optimization directives. Speedups between 3. 8× and 58× could be achieved while using the quick sort algorithm and the BCW 9 dataset. Both hardware and software designs using Xilinx MicroBlaze platform were used to verify the bubble sort based architecture of the kNN algorithm in  [15]. The hardware design achieved 127× speedup compared to its software counter counter-part. To reduce the impact of the memory-access constraint in kNN classification problems, an HLS based kernel is proposed in  [16]. The kernel employs two data access reduction methods: low precision data representation and principal component analysis based filtering (PCAF). The kernel performed to an equivalent 56-thread CPU server while greatly reducing external memory-accesses.
B. Selection-based kNN Architecture The block diagram of the proposed hardware architecture is shown in Figure  2. The "kNN Classifier" block has been designed in HLS (coded in C++), whereas the other blocks are existing IP blocks embedded in Vivado. The SDRAM memory is used to store the training set, which is more suitable than the Block RAM (BRAM) of the FPGA for platforms with limited number of BRAMs or applications with large datasets. The AXI Interconnect IP handles the read and write operations from and to the memory. It adopts an AXI smart connect IP to use one AXI port for 1) writing to the data acquisition block and 2) reading the classification result from the class determination block. The Zynq processing system IP is the main block of the design which uses a processor system reset IP to drive all blocks with a common clock and reset signals.
The advantage of this architecture compared to the one presented in  [14] , is that if V 2[i] is greater than minK, step 3 will not be executed. Thus, the K minimum distances are the output of step 2. This will result in a reduced selection time for hardware implementations. Moreover, the architecture in  [14]  selects the K minimum distances in a single step, which imposes hardware complexity and increased time latency for large datasets. While in the proposed architecture, the selection is performed in two smaller steps with a high probability that the third step will not be executed (V 2[i] > minK). Although the proposed selector finds the K-nearest neighbors without sorting the entire vector, a comparison with two sorters reported in the literature, i. e. QuickSort  [12]  and Bitonic Sorter   [21] , has been carried out.
D. Approximate kNN Blocks In  [23] , we have presented a complete assessment of using algorithmic level ACTs on a kNN classifier. The assessment included the degradation in accuracy to the gain in memory and execution time on Intel i7 CPU. In  [8] , the studied techniques have been formulated into a general approach that has been tested for the FPGA implementation of two machine learning classifiers. The reported approach has been adopted in this paper where a trade-off between the classifiers performance and quality has been considered. The trade-off resulted in our selection for the ACTs presented in the proposed approximate kNN architecture. All the adopted techniques belong to the data-oriented approximate computing category  [8]. The adopted ACTs are Dataset Reduction (Downsampling (DS) and Downscaling (DSc)), and Data Format Modification (DFM).
DS means varying the signal sampling frequency during signal acquisition. Since tactile data used in this work are from an already available dataset, the sampling frequency can't be changed. As a consequence, DS is applied offline on the dataset by reducing the number of samples. DSc is applied by adjusting the sample size as shown in subsection IV. A. DFM reduces the sample resolution. This can be achieved through the use of fixed-point or mixed precision instead of floating-point data representation. In this paper, fixed-point representation is adopted, and the precision is determined as a trade-off between resolution (32, 24, 16, and 8-bit) and classification accuracy. " The approximate kNN classifier starts operating once the Data Acquisition block receives the training samples (after DS/DSc has been applied offline) from the memory.
The dataset collected in  [30]  has been selected for the validation of the proposed kNN architecture. The experimental setup is shown in Figure  4  and can be described as follows: • Dataset: The dataset contains records for the two touch modalities performed by 70 participants. Each modality was recorded from a 4 × 4 tactile sensor for 10 seconds at 3 kHz sampling frequency. Thus, each raw data sample can be modeled in the form of a tensor of size 4×4×30,000. The touch modalities were performed on both the horizontal and vertical directions for two trials, resulting in a dataset of 840 samples. • Simulation Software: An open-source machine learning simulation tool called "Weka" has been used  [31]. Weka involves a collection of learning algorithms that can be applied to a pre-defined dataset or invoked from a Java code.
B. Hardware and Software Design Tools The Zynqberry TE0726-03M  [32]  was adopted for implementation. Zynqberry is a small-sized platform in the form of a Raspberry Pi compatible System-on-Chip (SoC) module integrating a Xilinx Zynq-7010 with a 512 MB SDRAM memory. The Zynq SoC has a hybrid structure of combining a dual-core ARM Cortex-A9 processor as a Processing System (PS) and an FPGA as Programmable Logic (PL) in a single SoC. Moreover, for comparison purposes, the architecture has As for the software tools, Vivado HLS 2018. 3 and Vivado 2018. 3 were used. Vivado HLS allows the design of an embedded system on FPGA using a high-level programming language such as C and C++ compared to traditional hardware description languages (HDL). The use of HLS decreases the FPGA development time and effort.
C. Implementation Methodology Once the whole design code is completed in HLS and design optimizations are applied, a co-simulation is performed. This simulation runs both the C++ and the RTL simulations together to verify a matching output. Then, the design is exported as an IP block. The latter is imported into Vivado 2018 and connected to the Zynq processor and other IP blocks as seen in Figure  2. First, a behavioral simulation is performed to verify the functionality of the design. Then, synthesis and place and route occur to finalize implementation. At this point, the generated report contains the occupied area percentage (BRAM, DSPs, etc. ) and the number of clock cycles passed to generate an output. Concerning power consumption estimation, Vivado offers two methods: Vector-based and Vector less.
e the power consumed by the simulated kNN architecture to compute a classification of an input sample (excluding the static power of the processing system (PS) as it is device dependent). For case (2), Exact kNN architecture has been coded using Python language running inside the CUDA computing platform. The GPU power estimation was obtained using NVIDIA System Managment Interface (NVSMI). The latter is a command utility that can be issued on any Python development environment with the CUDA libraries imported  [34]. Case 1: Exact versus Approximate kNN The implementation results on Zynqberry of the proposed Exact and Approximate kNN are shown in Table  II. Exact kNN occupies 12% of the hardware resources, consumes 0. 236 W, and classifies an input sample within 25. 7 µs. The obtained time latency verifies the real-time classification of a touch modality in less than 400 ms  [35].
6% is reported. The proposed approximate kNN provides real-time classification of touch modalities with a reduced time latency of 11. 2 µs. These results motivate the use of approximate computing techniques. Case 2: Exact kNN on FPGA versus GPU  Using the CUDA platform and NVSMI tool, the GPU implementation of Exact kNN provided a classification time of 80 ms while consuming 14. 12W for the touch modality classification problem. Table  III  shows a comparison between the FPGA and GPU implementations in terms of execution time and energy consumption. The results are significantly in favor of the FPGA, where the acceleration of the proposed kNN architecture on FPGA could be achieved with a fraction of the energy consumed using GPUs. This can be justified due to two possible reasons: • GPUs use DRAM for the communication between the different blocks of the kNN architecture (referred to as kernels)  [36] , which is slower than using a hybrid structure as proposed in Figure  2  where BRAMs are used to communicate between different blocks and DRAM is used only for dataset storage.
• The proposed kNN architecture exploits the parallelism capabilities of the FPGA. Thus, the "if-then-else" conditions are executed in parallel. On the other hand, the "then" and "else" parts are executed serially on GPUs resulting in a significant time latency increase. Such issue is known as "thread divergence"  [37]. Case 3: Comparison with similar works Comparing two kNN implementations is not a straight forward task due to the large number of differences such as: the number of nearest neighbors (K), dataset size (N ), number of features per sample (f ), development environment (HLS or HDL), hardware device used, etc. To achieve a fair comparison with Exact kNN, three similar architectures have been selected. These three architectures have been chosen such that they all have: • Used HLS for development since the comparison with an HDL implementation is not feasible.
Thus, for comparison reasons only, kNN-S 3 is implemented on the target device used in  [21]  i. e Vertix-7 knowing that implementing kNN on Zynqberry has achieved the real-time and low power consumption demands for the target touch modality application as reported in Table  II. kNN-S 3 offers a speedup of 1. 4× with 41. 5% and 12. 3% reduction in hardware resources and energy per classification respectively. Such results are justified with the lower number of FF and LUTs required by kNN-S 3. This is expected since the kNN in  [21]  uses the Bitonic sorter, which is outperformed by the proposed selector as shown in Table  I. Compared to kNN-S 1 and kNN-S 2 , the gain achieved by kNN-S 3 is relatively lower since the kNN in  [21]  exploits the high optimization capabilities of OpenCL for extensive computations and large datasets.
Such results pave the way towards embedding intelligence using a small-sized platform such as the Zynqberry for applications with low power and real- Calculated for the available resources only e. g. reduction in BRAM and DSP for kNN-S2 compared to  [15] , i. e. Reduction = (BRAM-Reduction + DSP-Reduction)/2, where BRAM-Reduction= 100(1-4/293) and DSP-Reduction= 100(1-5/47). time requirements. The implementation on different hardware platforms, under different settings, and operating on different dataset size, verifies the efficiency of the proposed selectionbased kNN architecture. Future work will involve the investigation of the use of circuit-level approximate computing techniques that are reported to permit noticeable gains in the performance of machine learning hardware implementations.