dataesr/scientific-paragraphs-categorization huggingface dataset:
We also used Blast to search for sequence similarities of such genomic region with (i) a database that contains all the individual TE copies identified in our genomes; and (ii) Flybase´s 'Transposons -all annotated elements (NT)'. If REPET identified a TE not annotated by TEMP/TIDAL we considered it as TEMP/TIDAL false negative. If a TE was annotated by REPET but we could not find sequence similarities with any of the TE databases by Blast, we considered it as a REPET false positive. Additional 50 TEs annotated by TEMP/ TIDAL but not by REPET were also manually curated following the same procedure. TE orthology identification. To identify orthologous TEs, we first transferred the TE coordinates from each strain to the ISO1 reference genome. Briefly, we used a similarity and synteny approach based on minimap2 (v.
All scripts used for the TE transfer are available at www. github. com/ sradiouy/deNovoTEsDmel. After determining the presence/absence of TEs, we classified them in three frequency classes: rare (TEs present in <10% genomes), fixed (TEs present in >95% of the genomes) and common (TEs present in ≥10% and ≤95%). We then calculated the number of TEs for each frequency class considering different number of genomes, starting from 5 up to 47. We estimated the mean and standard deviation of the number of TEs in each frequency class by randomly choosing genomes (30 iterations). Then, we intersected the different sets of common TEs considering 10, 20, 30, 40 and 47 strains using UpSetR (v. 1. 3)  100 and also established different sets of TEs based on the geographical origin of the genomes and compare them using VennDiagram (v.
1. 6)  101. For determining the location of the TE insertion regarding annotated genes, we used annotatr (R package version 1. 20. 0). TE eQTL analysis. In order to identify polymorphic TEs significantly associated with the expression levels of nearby genes, we analyzed available whole-body RNA-Seq data from 12 European 56,57 and 8 American strains  55  (Table  1 , Supplementary Data 2c). Briefly, RNA-Seq data was trimmed using the fastp package (v. 0. 20)  102  with default parameters. Expression levels were quantified by applying the salmon package (v. 1. 0. 0)  103  against the ENSEMBL (Dm. BDGP6. 22. 9) transcripts. Obtained transcripts per million (TPM) were summed up to gene level and rlog normalized using DESeq2 (v. 1. 28. 1)  104. eQTL analysis was performed using the QTLtools package (v.
1. 2) 105 taking into account the population structure (Supplementary Figs. 21  and 22 ). Putative cis-eQTL were searched within a 1 Kb window around each gene using the cis module in QTLtools. We used the nominal pass to evaluate the significance of the association of the gene expression level to TE insertions. The genotype table was created with a custom script. Finally, we performed a permutation pass (100,000 permutation) to adjust for multiple testing. Overall, we evaluated 12,281 eGenes-TE involving 4709 genes and 9676 TEs. We focused on TEs located in high recombination regions and we considered significant eGenes-TE associations when the nominal p-value and the associated adjusted p-value were significant (<0. 05). Manual inspection of the 15 TEs that were the top variant and the most significant associations (adjusted p-value <0.
From those, we also discarded TEs belonging to the INE-1 and the LARD families, since those represent very old TE families likely to have reach high frequencies neutrally, ending up with a set of 746 TEs. We considered TEs in this 746 dataset as likely to be enriched for candidate adaptive TEs  33. We then looked whether any of these 746 TEs was nearby a SNP showing significant values at some of the haplotype-based selection test. Finally, for each SNP-TE pair we established criteria of 'co-occurrence' by requesting certain number of the strains containing both the SNP allele undergoing a selective sweep and the nearby TE: for TEs present in 5-6 strains we request at least 4 of the strains to contain both the allele undergoing a selective sweep and the nearby TE and for TEs present in ≥7 strains we request the majority of strains to contain both the significant SNP and the nearby TE.
ncbi. nlm. nih. gov/gene/aboutgenerif). 2) Allele LoF Phenotypes from FlyBase: FlyBase's allele phenotypic dataset. Loss of function phenotypes and gene sets with alleles producing those phenotypes. 3) Putative Regulatory miRNAs from DroID: DroID's (http://www. droidb. org/) putative miRNA targets dataset and 4) Transcription Factors from DroID: DroID's (http://www. droidb. org/) transcription factor-gene interactions datasets. We report only terms with an adjusted p-value <0. 05.
Acknowledgements We would like to thank  DrosEU researchers  for sharing with us the strains sequenced in this manuscript (Supplementary Data 1). We also thank  Miriam Merenciano ,  Anna Ullastres , and  Lain Guio  for helping create the inbred strains. This project has received funding from the  European Research Council (ERC)  under the European Union's  Horizon 2020 research and innovation programme  ( H2020-ERC-2014-CoG-647900 ). S. R. was funded by the  MICINN/FSE/AEI  ( PRE2018-084755 ) and VH was funded by the  Generalitat de Catalunya  ( FI2017_B00468 ). DrosEU is funded by an  ESEB   Special Topic Network award.
Data availability All scaffolded assemblies and the raw data (long and short read sequencing) have been deposited in NCBI database under the BioProject accession PRJNA559813. The VCF file containing SNP callings for 46 D. melanogaster genomes used for testing positive selection evidences is available at DIGITAL. CSIC repository (https://doi. org/10. 20350/ digitalCSIC/13708) Fasta sequences for the D. melanogaster Manually Curated Transposable Elements (MCTE) library are available at DIGITAL. CSIC repository (https://doi. org/10. 20350/digitalCSIC/13765). The new consensus sequences are deposited in Dfam (Storer et al. 114 ). Recombination rates according to Fiston-Lavier et al. 98 and Comeron et al. 108 for D. melanogaster genome release 6 are available at DIGITAL. CSIC repository (https://doi.
The ultimate focus of this paper is to provide a hyperchaos-based reconfigurable platform for the real-time securing of communicating embedded systems interconnected in networks according to the Internet of Things (IoT) standards. The proposed platform's Register Transfer Level (RTL) architecture is entirely developed and designed from scratch using the VHSIC Hardware Description Language (VHDL). The original idea consists of exploiting the nonlinearity of a discretized and optimized 4D Lorenz hyperchaotic system as an encryption keystream generator in a symmetric cryptosystem to secure wireless communicating embedded systems and adapted to the UDP/IP protocol. It was necessary to go through three essential steps to achieve this goal. First, a lightweight and energy-efficient hyperchaos-based encryption IP core is designed, implemented on an FPGA circuit and dedicated to IoT device security, denoted Hyperchaotic-based IoT Device Security Core (HC-IoT-DSC).
Moreover, most proposed cryptosystems have been developed for academic purposes and are unused in practice or real-world applications. The present paper proposes a hyperchaos-based reconfigurable platform for real-time securing communicating embedded systems interconnected according to IoT standards. The designed platform is a modular RTL architecture fully developed and designed from scratch using the VHSIC Hardware Description Language (VHDL). The originality of the adopted encryption approach uses an optimized 4D hyperchaotic Lorenz system to construct a complex hyperchaotic pseudorandom number generator (HC-PRNG) for generating random data as encryption key matrices. In terms of design, the architectural study focuses on an adaptive layout using architectural optimization techniques to achieve a system embedded in an FPGA chip, which offers portability, easy adaptation, and reconfigurability with no technology constraints.
The IPv4 Core allows us to encapsulate (multiplex and demultiplex) the UDP datagram in the IP packets and vice versa to pass through the MAC layer of the FPGA platform. The Tx_arbitrator module allowed us to control and manage access to the MAC_TX channel when the ARP and IPv4 modules request a transmission simultaneously. The ARP module reads the MAC_RX data parallel to the IPV4_RX path. Subsequently, it manages the communication of ARP requests and the timeout if no response is received. The IPv4 module is developed to ignore every packet except the following: IPv4 packets, broadcast packets, and packets intended for our IP address. Once all these verifications are satisfied, the received header data are valid, and the module asserts the start of the reception. The MAC interface is relatively straightforward, with separate clocks for the receiver and the transmitter.
Each interface (RX and TX) has an 8-bit data bus. On the one hand, this interface is used to communicate with the ARP module using the AXI bus, and on the other hand, it is used to interface with the modules transmit engine and receive engine. In addition, the Xilinx MAC connects to the external ethernet PHY (copper) via a Gigabit Media Independent Interface (GMII). Note that the MAC wrapper is fundamentally provided with more subblocks, but to adapt it to our requirements and for optimization reasons, we have removed all modules that we do not need in our application. The UI shown in Figure  9  is used as a driver module for the UDP/IP core to control transmission and reception processes, the IP and MAC address configuration, and ensure the traffic routing path employing an internal private routing table.
In other words, this interface plays the role of an API in the application layer that allows communication with and controls the UDP stack. The first process is used for the static configuration of the FPGA's IP address. As a security measure, the MAC address of the platform changes randomly. The objective of this action is to avoid MAC spoofing attacks. In parallel with this process, an FSM is used to manage the transmission and reception of the data. First, we start UDP header capture and cannot send data. Second, if the reception is finished with validation, we pass it to user data transmission; otherwise, we must wait until the reception is completed. Finally, the transmitted data are routed according to a specific predefined routing table. The goals behind the static routing usage are from one side, to use less bandwidth and to minimize resource consumption (memory and computation).
These requirements could only be achieved with several tools and methods. In particular, the hardware-software codesign approach makes the overall architecture flexible and easily reconfigurable. Figure  10  represents the experimental setup of the wireless secure communication system, which is composed of: 1. A development ASUS workstation and TOSHIBA Laptop, containing the following tools: • ISE-DS 14. 7 software environment for VHDL programming and generation of configuration bitstreams; • iMPACT tool for FPGA configuration; • Eclipse IDE 2020-09 for Java development of the graphical interfaces to communicate between the PC and the FPGA board; • Wireshark software allows network packet analysis. This tool uses GTK+ software for its user interface implementation and pcap for packet capture  [96] ; 2.
C. HC-KG SIMULATION RESULTS Before the real-time measurement of our solution, we carried out two types of simulations. The first one is a MATLAB simulation, which aims to investigate and validate the chaotic aspect of the proposed HC-KG. To achieve this, the HC-KG is digitized by using the RK4 resolution method. Then, a bifurcation analysis is conducted to verify the behavior of the HC-KC and compare it to the original 4D Lorenz chaotic system. Moreover, the dynamical degradation effect is discussed through this simulation. The second simulates the hardware architecture with ModelSim-SE 10. 4 software (i. e. , functional simulation). In all cases, the simulations and real-time measurements are applied to the 4D Lorenz chaotic system described by the nonlinear dynamic equations (1) with an integration step h = 0.
001 and initial values x 0 = y 0 = z 0 = w 0 = -10. In addition, hyperchaotic signals were obtained such that the hyperchaotic signals (x, y, z, w) were represented with (10Q22) bits fixed-point arithmetic, 10 bits integer, and 22 bits decimal. The random signals (x r , y r , z r , w r ) are the fraction part (22 bits) of the hyperchaotic signals. The RK4 simulation results are given in Figure  13  and Figure  14 , while those of the functional simulations are depicted in Figure  15. The MATLAB simulation results are used to reference both the functional and real-time measurements. The results obtained by simulating the hardware are very similar to those obtained with MATLAB software.
4. 6 software  [96]. For reasons of organization of the paper and to avoid repetition, we only give Wireshark captures for a single transmission from Client 2 to Client 1. In this experiment, another station is used to intercept the UDP traffic between Client 1 and Client 2. To do this, one of the ports of the switch RG-ES224GC is configured as a mirroring port and connected to the interception station. On the one hand, this configuration allows a duplicate of all the network traffic between Client 1 and Client 2 to be obtained, and on the other hand, the same traffic can be captured and analyzed under the interception station by using Wireshark software. Figure  22  illustrates the packets captured during the communication between Client 2 and FPGA gateway 2 or between FPGA gateway 1 and Client 1.
F. CRYPTOSYSTEM SYNTHESIS RESULTS AND PERFORMANCE ANALYSIS This part mainly concerns the implementation results and performance analysis to demonstrate the robustness of the proposed security core. Several tools were used to carry out these results: MATLAB 2020b software, ISE-DS 14. 7 (Integrated Synthesis Environment-Design Suite), Eclipse IDE 2020-09 for Java developers, and ModelSim-SE 10. 4 of Mentor Graphics. A panoply of investigations has been performed to investigate the proposed design, according to the following: • The occupied FPGA area is estimated based on the used Flip Flops (FFs), Lookup Tables (LUTs), Block Random Access Memory (BRAM), and Digital Signal Processing unit (DSP). More precisely, every slice in Virtex-6 XC6VLX240T contains four (04) LUTs and eight (08) FFs, accordingly the AS (Area Size) in terms of the LS (Logic Slice) is equivalent to a quarter of (LUTs+FFs/2); • Maximum Post Place and Route operating Frequency (MPRF) and throughput, which is defined as the number of bits by a unit of time and can be formulated by TP = O_Size O_latency = (O_Size × GF) ( Gb s ), where O_sizeis the output size, O_latency is the delay to obtain a new • The power is evaluated for the register transfer abstraction level (RTAL) at the post place and route stage, considering all the hardware implementation details (physical constraints, placement and routing delays, device settings, ambient temperature, MPRF).
Statistical tests comprise three test suites: NIST SP 800-22, TESTU01, and AIS20/31. Moreover, for our sake and for the correct application of these tests, each of the seven test suites has been developed and implemented under the MATLAB 2020b environment. Figure  24  presents the implemented architecture and experimental setup for real-time data collection for statistical tests. Note that the data used for randomness quality evaluation and security analyses are not issued from simulation but represent the raw random sequences (without postprocessing) generated physically (real word data) after physically embedding the key generator on the XILINX ML605 FPGA target. This data acquisition is carried out by using the hardware architecture debugging tool ChipScope analyzer  [98]. The data are captured using a trigger and stored in an internal buffer.
90 GHz running Windows 10 Pro. In addition to the UDP socket configuration, the JAVA app executes the following operations: Implementing the UDP/IP architecture on the ML605 FPGA platforms has produced several results. The first result relates to the consumption of resources. As indicated in Table  6 , the proposed architecture consumes low physical resources, with only 653 logic slices (1%), two BRAM (1%), and no DSP blocks. This result also verifies the constraint of the open, flexible, and simple hardware architecture, allowing the addition of possible future hardware modules (ICMP, TCP, DHCP). The low number of BRAMs and DSP nonuse gives us high independence from the FPGA target. In other words, it offers good portability of the developed solution with no technology constraint. The second result corresponds to the critical operating frequencies and power consumption of the design.
The UDP/IP stack can operate at a maximum frequency of 123. 229 MHz (0. 986 Gb/s), almost very close to the theoretical frequency of 125 MHz (1 Gb/s). This time performance is more than sufficient for Ethernet-based communication at a maximum rate 1 Gbits/s. Additionally, it fulfills the constraint set at the start of the design. The low power consumption (40. 62 mW) can be explained by the low physical cost and confirmed by the obtained timing efficiency and the power efficiency values. The third result is the QoS metrics benchmarking. This test aims to study the behavior of UDP/IP for data packets with variable sizes. The obtained TR at the output is 116. 475 MB/s (114. 65 MB/s) with a TER of 99. 12% (98. 67%) for transmission and reception, respectively. Figure  25  illustrates a comparison between the predicted and measured values of the transfer ratio TRVS.
Moreover, the sampling distribution of the statistical test under H 0 should be found. Based on the previous steps, the rejection region is defined. Finally, the value of the statistical test using the sample data is computed. In our case, the hypothesis H 0 is that the studied or ''tested'' sequence is random, which induces H a : the tested sequence is not random. The appropriate choice of statistical tests for testing H 0 is the NIST SP800-22 test series. The significance level α of the test represents the probability that hypothesis H 0 is rejected when it should have been accepted. In practice, an upper limit of the first type for the level α, most often 5% (significant), 1% (very substantial) or 0. 1% (highly significant). More precisely, our approach evaluates the distribution of the P_Values for each test in NIST SP800-22 while calculating the P_ValueT.
b: TESTU01 TESTS Currently, TestU01 is the most complete and challenging test for RNGs, including eight (08) subbatteries with over 282 statistical tests. These subbatteries are SmallCrush, Crush, BigCrush, Alphabit, Rabbit, PseudoDIEHARD, FIPS 140-2, and NIST SP800-22. The SmallCrush is applied first. If the tested sequence passes, the crush tests are involved, and the more complex the BigCrush will be applied. Generally, if the tested sequence passes the previous battery, there is a high probability of succeeding in the remaining tests. Moreover, in these subbatteries, the tested sequences and the  In this subsection, the randomness quality of the proposed HC-GK is proved by using the AIS20/31 test suite that we developed under MATLAB software according to the requirements and the specifications of BSI.
V. CONCLUSION The present work comprised an FPGA design and realized embedded hyperchaotic communication for real-time and secure wireless data transmissions. The developed architectures are modular and comprise a UDP/IP stack and a chaotic security core. It was necessary to go through several stages to arrive at the final solution. The first step comprises the study, modeling, and implementation of FPGA technology of a UDP/IP interface, intending to control the network communications physically. To do this, we constructed an RTL architecture that relies on a VHDL description of UDP and IP network protocols. This stack has been developed to achieve, on the one hand, a flexible and reconfigurable architecture that gives the possibility of easy adaptation in the future without dependability to the hardware target technology.
MARTY-1. 4, is model independent and requires as input only the Lagrangian of the theory. Once the Lagrangian has been defined, tree-level and one-loop Wilson coefficients can be calculated symbolically by MARTY, from which flavor observables can be computed numerically by available software programs. We focus in particular on → and the recently updated → ℓ + ℓ - observables which are in tension with the SM, and present a general procedure to extract the relevant one-loop coefficients, such as 7 , ′ 7 , 9 and 10.
Introduction In the following we present a sample program using MARTY-1. 4 [1]  to calculate, in general BSM scenarios, one-loop Wilson coefficients for flavor physics such as (′)  7 and 9(10). These coefficients which are relevant to describe the → transitions are defined from the corresponding effective Hamiltonian  [2] , namely H eff ∋ - 4 √ 2 * 16 2 (′) ¯ ( ) + 2 16 2 9(10) ¯ ¯ ( 5 ) , (1) with , and the SM fermionic fields and the photon's field strength. The calculation of these coefficients using MARTY is model-independent and is not designed specifically for (′)  7 or 9(10). As presented in the next section, the procedure is very general and can be used to derive other coefficients, at the tree level or for other types of effective operators. Once these values are calculated by MARTY symbolically, numerical values of flavor observables can be obtained using SuperIso  [3]  for example.
Model definition This part is the only model-dependent part. It is possible to use built-in models in MARTY such as the SM or the MSSM, or define a custom Lagrangian. The program we present next only requires the model to have fermions named "b", "s" and "mu", and the photon "A". PMSSM_Model model; // built-in pMSSM in MARTY // SM_Model model; // built-in SM in MARTY Settings for the calculation In order to extract the Wilson coefficients, MARTY needs the conventiondependent global factor defined in the effective Hamiltonian (can be identified in equation 1) and the order of the external fermions in the operator because it is not uniquely defined. For the factor, it is first necessary to create its symbolic expression (using SM parameters in mty::sm_input::), namely: Expr factor = -pow_s(e_em, 4) * GetComplexConjugate(V_ts) * V_tb / (32 * CSL_PI*CSL_PI * M_W*M_W * s2_theta_W); Then, a FeynOptions object can be created to contain the factor and the fermion order: The fermions are defined from the order given to the computeWilsonCoefficients() method.
Conclusion We presented a general procedure to extract 7 , ′ 7 , 9 and 10 in any BSM model using MARTY-1. 4. Such a procedure is very useful to obtain, in a fully automated way, the loop-level predictions of flavor observables in general BSM scenarios that is a very long and difficult task by hand. Furthermore, MARTY is not limited to these Wilson coefficients and can also be used to extract coefficient of general ≤ 6 operators. Considering also the capability of MARTY to calculate squared amplitudes at tree-level or one-loop for general BSM, this software program allows us to automate theoretical predictions at the loop level for general BSM scenarios. http://arxiv. org/ps/2110. 14515v3.