dataesr/scientific-paragraphs-categorization huggingface dataset:
Model inputs PubMed was searched for publications relating to influenza in patients with diabetes. Articles were selected if they presented vaccine effectiveness in patients with diabetes, attack rates or complications of influenza in patients with diabetes (e. g. hospitalizations and deaths), VCR, or economic evaluations. Data unavailable through this search were identified by a search via Google and the websites for the WHO and International Diabetes Federation. Data from Turkey were preferred, but when unavailable, data from other countries were used. Data on population size, life expectancy, percentage of population working, and mean daily earning were obtained from the Turkish Statistical Institute, the OECD, or international economic survey data. When data specific to patients with diabetes were not available, data from the general population were used.
For DSA of inpatient cost, the lower bound was based on Turkish data  [41]  and the upperbound was based on data from WHO-CHOICE  [39]. For PSA, a lognormal distribution was used. Although there is no any gold standard to measure productivity loss due to an illness, the sources of lost productivity are assumed to include absence from paid work (absenteeism), decreased productivity at work (presentism), early retirement due to illness, early mortality for employee, and unpaid production. In this study, the only source of lost productivity was assumed to be absenteeism. Absenteeism costs due to influenza were calculated using the human capital approach. In this approach, the value of lost productivity is calculated as the product of the number of lost workdays and the cost of one workday from an employer's perspective.
Financial support for the study and for medical writing was provided by  Sanofi Pasteur. The funder participated in study design, data collection and analysis, the decision to publish, and preparation of the manuscript. Competing Interests: BM is an employee of  Sanofi Pasteur. SA was employed by  Sanofi Pasteur  when the study was conducted. IS previously received an unrestricted research grant from  Sanofi Pasteur  unrelated to this study.
MDE is nowadays applied in the context of software engineering for complex or cyber-physical systems, to build models of physical systems that can then be verified and simulated before they are built and deployed. This article focuses on DSMLs direct formal verification and simulation of their dynamic semantics. By "direct", we mean without transforming the DSML description into an automata-like one. This paper presents xviCore, a metamdeling language to create DSMLs equipped with an abstract syntax, a concrete syntax and a dynamic semantics. We exemplify xviCore by an integration of a metamodeling language and a formal behavioral modeling language, based on the blackboard design pattern. Formal verification techniques based on the Linear Temporal Logic (LTL) and the Temporal Boolean Difference can be then applied as demonstrated by the proposed approach.
In some works, e. g. ,  (Mayerhofer and al. , 2013) , the behavioral modeling language fUML is integrated into the M3 metamodeling layer. This overcomes transformation related problems, but formalverification related problems remain still a subject of a debate. Our global contribution presented in this paper is a new meta-modeling language, called xviCore, allowing meta-modelers to build DSMLs (called xviDSMLs), that along with their syntax and static semantics part also integrates a dynamic semantics part and providing solution for direct (without transformation) models verification and simulation. Our solution combines, two meta-languages, EMOF for the specification of the static part, and an original extension of the behavioral modeling formal language "Interpreted Sequential Machine" (ISM) called extended ISM (eISM) for the dynamic part.
Thanks to this key extension (that includes a blackboard-based communication model), dynamic semantics of an xviDSMLs can be designed, statically verified and used to simulate models written using them (called xviModels). xviCore is a tooled meta-language implemented as an Eclipse-EMF deployable plug-in. The remainder of this paper is structured as follows. Sections 2-3-4 describe our xviCore solution. Section 2 proposes an overview of the approach and the rationale for eISM and for its combination with EMOF. Section 3 presents eISM. Section 4 explains how the dynamic semantics of an xviDSML can be verified. A case study example demonstrating the approach's applicability is illustrated in Section 5. Section 6 presents related works on DSML dynamic semantics. Section 7 concludes and highlights our perspectives.
GLOBAL VIEW OF THE CONTRIBUTION (XVICORE) Our integrated meta-language xviCore (executable verifiable and interoperable core concepts and mechanisms) for creating verifiable DSML is illustrated in Fig. 1. XviCore combines two metalanguages, EMOF and our extension of the formal behavioral modeling language "Interpreted Sequential Machine" (ISM)  (Vandermeulen, 1996)  called extended ISM (eISM). Assuming other metalanguages could have been used, we thereafter justify this choice. An xviModel is created by an xviDSML itself created by EMOF for the static part and eISM for its dynamic semantics. The static part description of xviDSMLs is based on EMOF and does not require additional efforts  (Steinberg and al. , 2008). For what concerns the dynamic semantics, each domain concept has its own behavior, specified by a behavioral model.
RELATED WORK Specifying dynamic semantics in the field of MDE have been a topic of research for quite some time now, resulting with a wide diversity of approaches mainly based either on translational or operational semantics  (Combemale and al. 2009). The main benefit of translational semantics approaches is the reuse of appropriate formal toolsupported target space usually based on Automatalike formalisms. Among the most popular and currently used are: StateMate  (Harel and Politi, 1998) , Uppaal  (Larsen and al. , 1997) , the Finite State Machine (FSM) model of computation of Ptolemy II  (Lee and John, 1999) , the Stateflow module in the The MathWorks Simulink framework  (Boldt, 2007)  and the UML State Machines  (Schäfer and al. , 2001 -Harel, 1987). However, in comparison with the proposed approach, several drawbacks are hereafter highlighted.
CONCLUSION AND OUTLOOK The presented contribution illustrates an original, formal and tool-equipped approach named xviCore for verification and simulation purposes of DSML and models. xviCore provides the means for expressing dynamic semantics using formal behavioral modeling language, i. e. , an extended version of the interpreted sequential machine (ISM), named eISM. eISM is integrated with the metamodeling language EMOF, based on the blackboard design pattern. The resulting executable metamodeling language is promoted to the M3 layer. The approach also supports several formal verification techniques for dynamic semantics based on the Linear Temporal Logic (LTL) and the Temporal Boolean Difference. Other contributions remain still a subject of a debate. To prove the scalability of the approach, we are currently working on a more complex case study applied in the field of Systems Engineering.
neoformans. For instance, we previously reported that the first and last intron of the CAS3 gene are retained in some of the polyadenylated transcripts, whereas the others are mostly efficiently spliced  20. The present RNA-Seq-based analysis confirmed that in the wild-type strain, 5. 9% and 52. 9% of the CAS3 transcripts retained introns 1 and 12, respectively, whereas none of the other introns were retained at a significant level. However, these IR levels were not affected by the deletion of UPF1. Indeed, these levels remained very close to those measured in the wild-type strain (6. 1% and 53. 9% for introns 1 and 12, respectively). These results were confirmed using semi-quantitative RT-PCR assays as shown in Fig. 4A. We also tested additional loci (CNG00160, CNK02010, and CNA04020) using semi-quantitative RT-PCR assays and obtained similar results, suggesting that NMD has little role in the control of these intron-containing RNA molecules (Figure  S4 ).
Comparison of intron positions between C. neoformans var. neoformans and C. neoformans var. grubii. To analyze intron position conservation, the two genome sequences were aligned using Mauve 2. 3. 1 using default parameters (http://darlinglab. org/mauve/mauve. html). We then developed a script to use the position of each extremity of an intron in one variety to infer their theoretical positions in the other variety. We used this tool to classify introns of each strain in 1 of 4 categories: (1) conserved when both predicted positions correspond to intron extremities in the tested variety, (2) cross when the introns in each variety have at least 1 nucleotide overlap, (3) out when the predicted positions are out of the orthologous gene, and (4) lost when no intron is present at the predicted position (Figure  S7 ).
5-fold with a P value < 0. 05 as determined by Student t test analysis. RT-PCR analysis. Total RNA (5 μ g) was subjected to DNAse I treatment (Roche) to eliminate contaminating genomic DNA. A total of 1 μ g of the DNaseI-treated RNA was then used for reverse-transcription (RT) using the QuantiTect Reverse Transcription (Qiagen) kit. The resultant cDNAs were PCR-amplified in presence of dCTP (α 33 P) (Perkin Elmer) with the primers indicated in Table  S10. PCR products were resolved on 6% polyacrylamide gel and quantified using a Typhoon 9200 imager and ImageQuant 5. 2 software (Molecular dynamics). Wax moth killing assay. To determine the role of NMD in the virulence of C. neoformans, independent strains of the upf1Δ , upf2Δ , and upf3Δ single mutants and upf1Δ upf2Δ upf3Δ triple mutants were tested in a Galleria mellonella insect model of systemic cryptococcosis.
Acknowledgements This work was supported by  National Research Foundation of Korea  grants ( 2015R1A2A1A15055687 ) from  MEST , the  Strategic Initiative for Microbiomes in Agriculture and Food  funded by  Ministry of Agriculture, Food and Rural Affairs  ( 916006-2 ) (to Y. S. B). This work was supported by a grant from  ANR  ( 2010-BLAN-1620-01  program YeastIntrons) to GJ. We thank  Tae-Yup Kim  and  Anna Floyd  for their technical assistance. We thank  Cecelia Shertz Wall  for editing the manuscript.
In this paper, we present a new methodology that makes it possible to rapidly and efficiently compare several wireless applications in terms of performance and power consumption. The main contributions are as follows: • low-level components' implementation details are taken into account and efficiently fed back at high-level to build a complete wireless communication system • an environment, based on SystemC, makes it possible to model and simulate any wireless application that is built from the library modules. Although, simulations are performed at high level, provided results are very accurate. • the proposed approach enables faster estimation of power compared to classic approaches. This makes it possible to explore multiples configurations and facilitates design space exploration. The remainder of this paper is organized as follows: a review of the related works on FPGA power estimation is discussed in Section II with a focus on tools and methodologies performed at system level.
II. RELATED WORKS Today, as designers target at the implementation of a complete system into an FPGA device, they usually follow a generic top-down approach which is divided into several well-identified levels. Fig. 1  describes these levels for a hardware implementation, without any software considerations. At system level, the system is modelled using dedicated languages such as Matlab, which is widely used in the community, or programming languages such as C/C++. The system behaviour is usually validated using simulation tools such as Simulink. Then, FPGA design implementation is performed in three steps: first, system level synthesis enables the translation of system level architectures into a HDL description. Then, hardware synthesis takes this description as an input to generate a supported netlist compatible with FPGA vendors' implementation tools.
However, the accuracy of the estimation highly depends on the data input patterns that are provided  [3] ,  [4]. To circumvent this pattern-dependency, Monte-Carlo based approaches have been proposed to reduce the number of simulations  [5] ,  [6]. Random patterns are applied to the system and power is evaluated until a given criterion is satisfied. As compared to statistical models, probabilistic techniques only require one simulation to estimate power i. e. they only propagate the switching probabilities from the inputs to all nodes in the circuit. However, several considerations such as timing and spatial correlation, have to be taken into account in order to obtain more accurate results  [7] ,  [8]. In addition to providing a fast power estimation, simulation-based techniques generally have a better accuracy than probabilistic techniques.
Nevertheless, when designers work at this level, decisive choices are taken very late in the design flow, which imposes expensive redesign costs when constraints are not met. Simulations may also be very time-consuming due to the huge number of implementation details. To speed up power estimation, several techniques have been developed at the Register Transfer Level (RTL). At this level, systems are usually described using hardware description languages such as VHDL or Verilog, for example. The circuit is described using a set of signals and hardware sub-elements, also called macros. Macros can either refer to fine-grain components such as adders or multiplexers or much more complex elements such as Intellectual Property (IP) blocks. Macro-modelling techniques, that can be based on LUT tables or equations, have been developed to derive power according to input statistical parameters  [9] -  [11].
In all these works, power models are derived from data-sheet values, real measurements or are possibly based on other works presented in literature. The accuracy of power estimation is not the primary objective but rather used to draw general guidelines. Nevertheless, it is obvious that the accuracy of the power estimation is very poor because no implementation details are available. Several languages and tools are widely used to model the functionality of a system, such as the Matlab software environment from MathWorks  [17]. Other examples of tools and methodologies are listed in Table  1. Basically, such tools do not support power estimation. Designers have to integrate additional information in order to make it possible. As an example, Matlab allows users to develop and to test their algorithms in a user friendly environment and with a common language.
However, it requires additional tools to complete the design. For FPGA devices, System Generator  [18]  and DSP builder  [19] , respectively from Xilinx and Altera, are tools that have been integrated in the Matlab environment in order to enable HDL code generation, directly from a Simulink graphical description. The generated HDL code may be translated into a netlist or even a bitstream, according to the FPGA classic design flow. At this point, power consumption can be estimated by low-level simulations or by real on-board measurements. However, this approach can be really time consuming for large designs and design space exploration becomes limited due to the prohibitive number of required implementations. The flow has to be re-run from scratch, at each configuration of the system. To address the lack of information at high level, power and performance details can be fed back from lower levels to Matlab/Simulink.
This is typically the purpose of System Generator tool. In  [26] , the key points of the approach consists of Python-based modules that enable performance estimation (i. e. latency, resource utilization). These tools also provide a power analysis during system-level simulation. Although power estimations are relatively accurate, the time spent during the implementation steps is prohibitive and usually not convenient for design exploration. Furthermore, when dealing with streaming application modelling, authors of  [26]  assume that all hardware modules are active, which is not necessarily the case. FPGA vendors have also contributed to the development of power estimation tools at system level. These are called spreadsheets, such as XPE (Xilinx Power Estimator) from Xilinx  [27]  and Power Play Early Estimator from Altera  [28].
Moreover, it does not consider signals activity during the execution of the application. To bridge the gap between an algorithmic description and the corresponding RTL hardware description, Transaction-Level Modelling (TLM) has become a widely popular concept. This approach is generally based on the SystemC language since it has been standardized by the Open SystemC Initiative  [29]. SystemC consists of a C++ library and an associated simulation kernel. It allows designers to model a system by describing both hardware and software parts in a common language. It supports several degrees of refinement in which implementation details can be represented or omitted. SystemC modelling has the great advantage that all the objects communicate together using a generic interface call channel. The computational aspect of the system is thus separated from the communication path.
In the latter case, the IP requires an additional controller in order to configure and manage it. As depicted in Fig. 3 , each hardware IP, which corresponds to a specific configuration of its high-level model, is then fully characterized through the different steps of the design process. Design implementation is performed throughout the synthesis, mapping, place, and route steps. Note that these steps are performed for a specific FPGA device that has a given number of resources and specific timing properties. In this study, we make use of the Xilinx ISE 14. 4  [42]  tool. Implementation settings, that can have a significant impact regarding the power consumption, have been set to a standard-level and default values have been retained to limit software optimizations  [43]. All these remarks ensure the genericity of our approach.
A non-exhaustive list of the cores that are currently stored in the library is provided in Table  3. To reduce the number of configurations to analyse, a current work aims to extrapolate the results from specific IP configurations to build a more global model by studying the trend of the power consumption according to several criteria (data size, frequency, IP specific parameters, etc. ). Such approach is discussed in Section III-D. In this way, designers will have the possibility to explore a large design space based on a minimum set of tests. This first stage is quite tedious but has been relieved by the use of automated scripts that also spare time and reduce the number of errors. Designers can easily use the proposed scripts to characterize their own IPs. Note that a lot of works described in Section II are also based on a characterization process.
D. LIBRARY OPTIMIZATIONS The dedicated library already contains power consumption values, RTL codes and corresponding high-level models of various wireless communications hardware IPs. In fact, designers only have to use it in order to build a model of their systems. However, if hardware IPs or high-level models are not available in the library, designers have to perform the characterization step and the high-level modelling of their hardware IP in SystemC. Scripts have been developed in order to make the characterization process easier and to avoid error. Another limitation can be a huge number of possible parameters that can be set by designers to configure their IP. For example, both system parameters (e. g. IFFT size, choice of modulation) and technological parameters (e. g. clock frequency, FPGA device) can be different from the configurations that are already stored in the library.
A. SISO-OFDM SYSTEM The transmitter consists of a source which provides the binary data to send. These data can be sent to the channel encoder, if there is any, or immediately processed by the QAM modulator that delivers complex I/Q QAM symbols according to the input binary symbols. The modulator supports QPSK, 16QAM and 64QAM modulations. The Carrier Mapper module aims to allocate modulated symbols to the corresponding sub-carriers. Moreover, as in real systems, all sub-carriers may not be used. Some of them can be cancelled in order to avoid degradations at the border of the band. An OFDM modulation is then performed using an IFFT block and a cyclic prefix (CP) is added. OFDM symbols coming from the IFFT can be scaled by the DAC-Scaling module according to the Digital-to-Analogue converter resolution.
The last block of the transmitter realizes the time pilot insertion, which enables channel estimation at the receiver side. The receiver performs the dual operations, starting with removing the CP and ADC data scaling. Then, the FFT is computed and carrier un-mapping only keeps the useful sub-carriers. A channel estimation is performed on every dedicated OFDM pilot symbol. Finally, received signals are equalized according to the channel coefficients and a QAM demodulation is performed to retrieve the binary data. Turbo decoding is used for channel decoding. The global communication chain has been completely described in VHDL and some IP cores from Xilinx have been used. The architecture is highly configurable according to user-defined scenarios. Some parameters that can be chosen are: • data quantization (number of bits to represent the QAM complex symbols) of every module, • Fast Fourier transforms size [256:2048], • length of the cyclic prefix, • modulation orders [QPSK, 16QAM, 64QAM], • number of used sub-carriers, • frame structure i.
Semantic technologies have been used in the past to analyze the components of workflows, for example to extract common structural patterns  [8]. Recently more attention has been given to the elicitation of the activity of workflows in a knowledge principled way, for example searching for common motifs in scientific workflows  [10]  or labelling data artifacts to produce high level execution traces (provenance)  [1]. This research highlighted the need for adding semantics to the representation of workflows and the challenges associated with the problem of producing such annotations  [1]. Recently a number of repositories of scientific workflows have been published -Wings 8 , My experiments 9 , SHIWA 10 are the prominent examples. We selected the My experiments repository as data source for our study.
The ontology defines a unique type -Datanode -and 114 relations, starting from a single top property: relat-edWith, having the class Datanode as rdfs:domain and rdfs:range. Datanode relations can express meta-level aspects (e. g. describes/describedBy, hasAnnotation/isAnnotationOf ), containment (e. g. hasPart/isPartOf, hasSection/isSec-tionOf ) as well as a properties like derivation (e. g. hasCopy/isCopyOf, processed-Into/processedFrom), among others. Relations are organised by the means of the rdfs:subPropertyOf property. For example, processedInto is a subproperty of hasDerivation, as it is possible to derive a new data object from another also in other ways, for example generating an unprocessed copy -hasCopy. In the present work, a datanode is any data object that can be the input or output of a workflow processor.