page_title: Cache coherency protocols (examples)
section_title: Write-once (or write-first) protocol
hierarchical_section_title: Cache coherency protocols (examples) / Coherency protocols / Write-once (or write-first) protocol
context_page_description: Examples of coherency protocols for cache memory are listed here. For simplicity, all "miss" Read and Write status transactions which obviously come from state "I", in the diagrams are not shown. They are shown directly on the new state. Many of the following protocols have only historical value. At the moment the main protocols used are the R-MESI type / MESIF protocols and the HRT-ST-MESI or a subset or an extension of these.
context_section_description:   States D-R-V-I  (MESI) 
  – Characteristics:
  – No use of  "shared line"  (protocol for standard or unmodifiable bus)
  – Write Through on first  Write Hit in state V, then Copy Back
  Processor operations
  Read Miss
  – If there is a D copy in another cache, the data is supplied by this cache (intervention) and in the same time it is written also in MM (Copy-Back).
  – else the data is read from MM
  – all caches are set V
  Write Hit
  – If the cache is D or R (exclusiveness), the write can take place locally without any other action and the state is set (or remains) D
  – else V (first Write Hit) the data is written in cache and in MM (Write Through) invalidating all the other caches (Write-Invalidate). – The cache is set R
  Write Miss
  – Like a Read Miss but with "invalidate" command (RWITM) plus a Write Hit in D state (updating). The cache is set D and all the other caches are set "Invalid" (I)
  – Note – Write Through is performed only in "Write Miss". It is point out that in this case a bus transaction in any case is needed to invalidate the other caches and therefore it can be taken advantage of this fact to update also the MM. In "Write Hit" instead no more transaction is needed so a "Write Through" it would become a useless operation in case that the cache were updated again.
  Bus transactions
  Bus Read
  – If the cache is D the data is sent  to requesting cache (intervention) and to MM (copy-back). The cache is set V
  – else the state is changed or remains in V
  Bus Read – (RWITM)
  – If the cache is D the data is sent to the bus (Intervention)
  – The cache is set "Invalid" (I)
  Bus Invalidate Transaction
  – The cache is set "Invalid" (I)
  Operations
  - Write Allocate
  - Intervention: from D
  - Write Through: first write hit in V state
  - Write Invalidate
  - Copy-Back: D replacement
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caption: Bull HN ISI Protocol – State Transaction Diagram