page_title: Multiple patterning
section_title: Self-aligned contact/via patterning
hierarchical_section_title: Multiple patterning / Self-aligned contact/via patterning
caption_attribution_description: English: Self-aligned via patterning scheme. Left: Patterned unfilled trenches (blue). Center: Resist mask. Right: Vias patterned by etching through resist mask and hardmask (purple) surrounding trenches (blue).
context_page_description: Multiple patterning is a class of technologies for manufacturing integrated circuits, developed for photolithography to enhance the feature density. It is expected to be necessary for the 10 nm and 7 nm node semiconductor processes and beyond. The premise is that a single lithographic exposure may not be enough to provide sufficient resolution. Hence additional exposures would be needed, or else positioning patterns using etched feature sidewalls would be necessary.
  Even with single exposure having sufficient resolution, extra masks have been implemented for better patterning quality such as by Intel for line-cutting at its 45nm node or TSMC at its 28nm node.
  Even for electron-beam lithography, single exposure appears insufficient at ~10 nm half-pitch, hence requiring double patterning.
  Pitch double-patterning was pioneered by Gurtej Singh Sandhu of Micron Technology during the 2000s, leading to the development of 30-nm class NAND flash memory. Multi-patterning has since been widely adopted by NAND flash and RAM memory manufacturers worldwide.
context_section_description: Self-aligned contact and via patterning is an established method for patterning multiple contacts or vias from a single lithographic feature. It makes use of the intersection of an enlarged feature resist mask and underlying trenches which are surrounded by a pre-patterned hardmask layer. This technique is used in DRAM cells and is also used for advanced logic to avoid multiple exposures of pitch-splitting contacts and vias.
  Since 32 nm node, Intel has applied the above-mentioned self-aligned via approach, which allows two vias separated by a small enough pitch (112.5 nm for Intel 32 nm metal) to be patterned with one resist opening instead of two separate ones. If the vias were separated by less than the single exposure pitch resolution limit, the minimum required number of masks would be reduced, as two separate masks for the originally separated via pair can now be replaced by a single mask for the same pair.
caption: Self-aligned via dual-damascene patterning.
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