This is a sequential circuit. The circuit consists of combinational logic
and one bit of memory (i.e., one flip-flop). The output of the flip-flop
has been made observable through the output state.

  Read the simulation waveforms to determine what the circuit does, then implement it.

  time            clk             a               b               state           q
  0ns             0               1               x               x               x
  5ns             1               1               x               x               x
  10ns            0               0               0               x               x
  15ns            1               0               0               0               0
  20ns            0               0               0               0               0
  25ns            1               0               0               0               0
  30ns            0               0               0               0               0
  35ns            1               0               0               0               0
  40ns            0               0               0               0               0
  45ns            1               0               1               0               1
  50ns            0               0               1               0               1
  55ns            1               1               0               0               1
  60ns            0               1               0               0               1
  65ns            1               1               1               0               0
  70ns            0               1               1               0               0
  75ns            1               0               0               1               1
  80ns            0               0               0               1               1
  85ns            1               1               1               0               0
  90ns            0               1               1               0               0
  95ns            1               1               1               1               1
  100ns           0               1               1               1               1
  105ns           1               1               1               1               1
  110ns           0               1               1               1               1
  115ns           1               1               0               1               0
  120ns           0               1               0               1               0
  125ns           1               0               1               1               0
  130ns           0               0               1               1               0
  135ns           1               0               0               1               1
  140ns           0               0               0               1               1
  145ns           1               0               0               0               0
  150ns           0               0               0               0               0
  155ns           1               0               0               0               0
  160ns           0               0               0               0               0
  165ns           1               0               0               0               0
  170ns           0               0               0               0               0
  175ns           1               0               0               0               0
  180ns           0               0               0               0               0
  185ns           1               0               0               0               0
  190ns           0               0               0               0               0

module TopModule (
  input clk,
  input a,
  input b,
  output q,
  output state
);


Reference solution:

module RefModule (
  input clk,
  input a,
  input b,
  output q,
  output state
);

  reg c;
  always @(posedge clk)
    c <= a&b | a&c | b&c;

  assign q = a^b^c;
  assign state = c;

endmodule


Testbench:
`timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13


module stimulus_gen (
	input clk,
	output logic a,
	output logic b,
	output reg[511:0] wavedrom_title,
	output reg wavedrom_enable	
);


// Add two ports to module stimulus_gen:
//    output [511:0] wavedrom_title
//    output reg wavedrom_enable

	task wavedrom_start(input[511:0] title = "");
	endtask
	
	task wavedrom_stop;
		#1;
	endtask	



	initial begin
		a <= 1;
		@(negedge clk) {a,b} <= 0;
		@(negedge clk) wavedrom_start("Unknown circuit");
			repeat(3) @(posedge clk);
			{a,b} <= 1;
			@(posedge clk) {a,b} <= 2;
			@(posedge clk) {a,b} <= 3;
			@(posedge clk) {a,b} <= 0;
			@(posedge clk) {a,b} <= 3;
			@(posedge clk) {a,b} <= 3;
			@(posedge clk) {a,b} <= 3;
			@(posedge clk) {a,b} <= 2;
			@(posedge clk) {a,b} <= 1;
			@(posedge clk) {a,b} <= 0;
			@(posedge clk) {a,b} <= 0;
			@(posedge clk) {a,b} <= 0;
			@(negedge clk);
		wavedrom_stop();

		repeat(200) @(posedge clk, negedge clk)
			a <= &((5)'($urandom));
		$finish;
	end
	
endmodule

module tb();

	typedef struct packed {
		int errors;
		int errortime;
		int errors_q;
		int errortime_q;
		int errors_state;
		int errortime_state;

		int clocks;
	} stats;
	
	stats stats1;
	
	
	wire[511:0] wavedrom_title;
	wire wavedrom_enable;
	int wavedrom_hide_after_time;
	
	reg clk=0;
	initial forever
		#5 clk = ~clk;

	logic a;
	logic b;
	logic q_ref;
	logic q_dut;
	logic state_ref;
	logic state_dut;

	initial begin 
		$dumpfile("wave.vcd");
		$dumpvars(1, stim1.clk, tb_mismatch ,clk,a,b,q_ref,q_dut,state_ref,state_dut );
	end


	wire tb_match;		// Verification
	wire tb_mismatch = ~tb_match;
	
	stimulus_gen stim1 (
		.clk,
		.* ,
		.a,
		.b );
	RefModule good1 (
		.clk,
		.a,
		.b,
		.q(q_ref),
		.state(state_ref) );
		
	TopModule top_module1 (
		.clk,
		.a,
		.b,
		.q(q_dut),
		.state(state_dut) );

	
	bit strobe = 0;
	task wait_for_end_of_timestep;
		repeat(5) begin
			strobe <= !strobe;  // Try to delay until the very end of the time step.
			@(strobe);
		end
	endtask	

	
	final begin
		if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
		else $display("Hint: Output '%s' has no mismatches.", "q");
		if (stats1.errors_state) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "state", stats1.errors_state, stats1.errortime_state);
		else $display("Hint: Output '%s' has no mismatches.", "state");

		$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
		$display("Simulation finished at %0d ps", $time);
		$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
	end
	
	// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
	assign tb_match = ( { q_ref, state_ref } === ( { q_ref, state_ref } ^ { q_dut, state_dut } ^ { q_ref, state_ref } ) );
	// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
	// the sensitivity list of the @(strobe) process, which isn't implemented.
	always @(posedge clk, negedge clk) begin

		stats1.clocks++;
		if (!tb_match) begin
			if (stats1.errors == 0) stats1.errortime = $time;
			stats1.errors++;
		end
		if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
		begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
			stats1.errors_q = stats1.errors_q+1'b1; end
		if (state_ref !== ( state_ref ^ state_dut ^ state_ref ))
		begin if (stats1.errors_state == 0) stats1.errortime_state = $time;
			stats1.errors_state = stats1.errors_state+1'b1; end

	end

   // add timeout after 100K cycles
   initial begin
     #1000000
     $display("TIMEOUT");
     $finish();
   end

endmodule