dakies/OSS_Verilog huggingface dataset:
module hello_skylersaleh(
  input clk,
  input [6:0] dip_switch,
  output [6:0] segments,
  output decimal
);

wire slow_clock;
reg [15:0] clock_div;
reg [2:0] state; 
wire flash;
wire [2:0]selected_state;
reg [6:0] hello_seg_output;
reg [6:0] rpog_seg_output;

always@(posedge clk)clock_div+=1;
assign slow_clock = clock_div[dip_switch[3:0]];
always@(posedge slow_clock)state+=1;
assign selected_state = dip_switch[6]? state: dip_switch[2:0];
assign flash = (dip_switch[6]? slow_clock : dip_switch[3])|dip_switch[4];
assign decimal = !flash;

initial begin
  clock_div = 0; 
  state = 0;
end

always@(selected_state)begin
  case(selected_state)
    0: hello_seg_output= 7'b1110100; //H
    1: hello_seg_output= 7'b1111001; //E
    2: hello_seg_output= 7'b0111000; //L
    3: hello_seg_output= 7'b0111000; //L
    4: hello_seg_output= 7'b0111111; //O 
    default: hello_seg_output= 7'b0000000;  
  endcase
end

always@(selected_state)begin
  case(selected_state)
    0: rpog_seg_output= 7'b1010000; //R
    1: rpog_seg_output= 7'b1110011; //P
    2: rpog_seg_output= 7'b0111111; //O
    3: rpog_seg_output= 7'b1111101; //G 
    default: rpog_seg_output= 7'b0000000;  
  endcase
end
assign segments = flash?( dip_switch[5] ? rpog_seg_output : hello_seg_output): 7'b000000;

endmodule
module SPIController (
  // System Interfaces
  input wire clk,
  input wire rst,

  // SPI Bus Interfaces
  output reg CS0,
  output reg CS1,
  output reg SPICLK,
  output reg MOSI,
  input wire MISO,

  // Input Signals
  input wire Addr15, 		// Sampled on Phase 01
  input wire Read_notWrite,	// Sampled on Phase 16
  input wire Addr,		// Sampled on Phase 18[bit0/LSB], 20[bit1], ..., 44[bit13], 46[bit14/MSB], bit 15 not sampled (see Addr15)
  input wire Data,		// Sampled on Phase 50[bit0/LSB], 52[bit1], ..., 78[bit14], 80[bit15/MSB]


  // Timing Output Signals
  output reg ShiftAddr,		// Asserted when the Address should be shifted
  output reg ShiftDataRead,     // Asserted when the data register collecting data read from memory should be shifted
  output reg ShiftDataWrite,    // Asserted when the data regsiter providing data to be written to memory should be shifted
  output reg PresetCarry,       // Asserted the clock before data motion starts
  output reg EndOfPhase,        //
  output reg PrepOutput
);

  // SPI sequencer
  reg [6:0] SPIphase;
  always @(posedge clk) begin
    if (rst)
      SPIphase <= 0;
    else if (SPIphase == 83)
      SPIphase <= 0;
    else
      SPIphase <= SPIphase + 1;
  end

  // SPI bus signal generator
  always @(posedge clk) begin
    if (SPIphase <= 1) begin
      CS0 <= 1;
      CS1 <= 1;
      SPICLK <= 0;
      MOSI <= 0;
    end else begin
      CS0 <= CSreg;
      CS1 <= !CSreg;
      if (SPIphase <= 81)
        SPICLK <= SPIphase[0];
      else
        SPICLK <= 0;

      if (SPIphase <= 13)
        MOSI <= 0;
      else if (SPIphase <= 15)
        MOSI <= 1;
      else if (SPIphase <= 17) begin
        if (SPIphase[0] == 0)
          MOSI <= Read_notWrite;
      end else if (SPIphase <= 47) begin
        if (SPIphase[0] == 0)
          MOSI <= Addr;
      end else if (SPIphase <= 49)
        MOSI <= 0;
      else begin
        if (Read_notWrite)
          MOSI <= 0;
        else begin
          if (SPIphase[0] == 0)
            MOSI <= Data;
        end
      end
    end
  end

  // Generate Address Shift Enable Signals
  always @(posedge clk) begin
    ShiftAddr <= ((SPIphase >= 18) && (SPIphase <= 48) && (SPIphase[0] == 0));
    ShiftDataRead <= ((SPIphase >= 51) && (SPIphase <= 81) && (SPIphase[0] == 1) && Read_notWrite);
    ShiftDataWrite <= ((SPIphase >= 50) && (SPIphase <= 80) && (SPIphase[0] == 0) && !Read_notWrite);
    PresetCarry <= (SPIphase == 17);
    EndOfPhase <= (SPIphase == 83);
    PrepOutput <= (SPIphase == 49);
  end

  reg CSreg;
  always @(posedge clk) begin
    if (SPIphase == 1)
      CSreg <= Addr15;
  end

endmodule
module user_module_341571228858843732(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7 = io_in[6];
  wire net8 = io_in[7];
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13;
  wire net14;
  wire net15 = 1'b0;
  wire net16 = 1'b1;
  wire net17 = 1'b1;

  assign io_out[0] = net1;
  assign io_out[1] = net2;
  assign io_out[2] = net9;
  assign io_out[3] = net10;
  assign io_out[4] = net11;
  assign io_out[5] = net12;
  assign io_out[6] = net13;
  assign io_out[7] = net14;

  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (
    .d (net3),
    .clk (net1),
    .q (net9)
  );
  dff_cell flipflop2 (
    .d (net4),
    .clk (net1),
    .q (net10)
  );
  dff_cell flipflop3 (
    .d (net5),
    .clk (net1),
    .q (net11)
  );
  dff_cell flipflop4 (
    .d (net6),
    .clk (net1),
    .q (net12)
  );
  dff_cell flipflop5 (
    .d (net7),
    .clk (net1),
    .q (net13)
  );
  dff_cell flipflop6 (
    .d (net8),
    .clk (net1),
    .q (net14)
  );
endmodule
module tomkeddie_top_tto
  #(parameter CLOCK_RATE=1000)
  (
   input [7:0]  io_in,
   output [7:0] io_out
   );
  
  wire                      clk   = io_in[0];
  wire                      reset = io_in[1];
  wire                      hour_inc = io_in[6];
  wire                      min_inc  = io_in[7];
  wire                      lcd_en;
  wire                      lcd_rs;
  wire               [3:0]  lcd_data;

  assign io_out[0] = lcd_data[0];
  assign io_out[1] = lcd_data[1];
  assign io_out[2] = lcd_data[2];
  assign io_out[3] = lcd_data[3];
  assign io_out[4] = lcd_en;
  assign io_out[5] = lcd_rs;

  // instatiate lcd
  lcd lcd(.clk(clk), .reset(reset), .hour_inc(hour_inc), .min_inc(min_inc), .en(lcd_en), .rs(lcd_rs), .data(lcd_data));
  
endmodule
module hex_sr #( parameter LENGTH = 40 ) (
  input [7:0] io_in,
  output [7:0] io_out
);
    
   wire clk;
   wire recirc;
   wire [5:0] data_in;

   wire [5:0] data_out;

   assign clk = io_in[0];
   assign recirc = io_in[1];
   assign data_in = io_in[7:2];

   assign io_out[7:2] = data_out;
   assign io_out[1:0] = 2'b0;

   genvar i;
   generate
      for (i = 0; i < 6; i = i + 1)
	sr_recirc #(.LENGTH(LENGTH)) sr0(clk, recirc, data_in[i], data_out[i]);
   endgenerate

endmodule
module cpldcpu_TrainLED2top(
  input [7:0] io_in,
  output [7:0] io_out
);

// Instance 1
TrainLED2 TrainLED2_top1 (
  .clk(io_in[0]),
  .rst(io_in[1]),
  .din(io_in[2]),
  .dout(io_out[0]),
  .led1(io_out[1]),
  .led2(io_out[2]),
  .led3(io_out[3])
  );



endmodule
module xor_shift32_evango #( parameter MAX_COUNT = 1000 ) (
  input [7:0] io_in,
  output [7:0] io_out
);
    
    wire clk = io_in[0];
    wire reset = io_in[1];
    wire [6:0] led_out;
    assign io_out[6:0] = led_out;
    wire [5:0] seed_input = io_in[7:2];

    // external clock is 1000Hz, so need 10 bit counter
    reg [9:0] second_counter;
    reg [3:0] digit;
    reg unsigned [31:0] inital_state;

    always @(posedge clk) begin
        // Seed Setting
        if (reset) begin
            inital_state <= {26'b00000000000000000000000000, seed_input};
            second_counter <= 0;
            digit <= 0;
        end else begin
            // if up to 16e6
            if (second_counter == MAX_COUNT) begin
                // reset
                second_counter <= 0;
                
                inital_state = inital_state ^ (inital_state << 13);
                inital_state = inital_state ^ (inital_state >> 17);
                inital_state = inital_state ^ (inital_state << 5);

                // increment digit
                digit <= {1'b0, inital_state[2:0]};
            end else 
                // increment counter
                second_counter <= second_counter + 1'b1;
        end
    end

    // instantiate segment display
    seg7 seg7(.counter(digit), .segments(led_out));

endmodule
module xor_shift32_quantamhd #( parameter MAX_COUNT = 1000 ) (
  input [7:0] io_in,
  output [7:0] io_out
);
    
    wire clk = io_in[0];
    wire reset = io_in[1];
    wire [6:0] led_out;
    assign io_out[6:0] = led_out;
    wire [5:0] seed_input = io_in[7:2];

    // external clock is 1000Hz, so need 10 bit counter
    reg [9:0] second_counter;
    reg [3:0] digit;
    reg unsigned [31:0] inital_state;

    always @(posedge clk) begin
        // Seed Setting
        if (reset) begin
            inital_state <= {26'b00000000000000000000000000, seed_input};
            second_counter <= 0;
            digit <= 0;
        end else begin
            // if up to 16e6
            if (second_counter == MAX_COUNT) begin
                // reset
                second_counter <= 0;
                
                inital_state = inital_state ^ (inital_state << 13);
                inital_state = inital_state ^ (inital_state >> 17);
                inital_state = inital_state ^ (inital_state << 5);

                // increment digit
                digit <= {1'b0, inital_state[2:0]};
            end else 
                // increment counter
                second_counter <= second_counter + 1'b1;
        end
    end

    // instantiate segment display
    seg7 seg7(.counter(digit), .segments(led_out));

endmodule
module klei22_ra #(
    parameter RA_SIZE = 8,
    parameter BITS_PER_ELEM = 5
) (
    input  [7:0] io_in,
    output [7:0] io_out
);

  wire clk = io_in[0];
  wire rst = io_in[1];
  wire i_data_clk = io_in[2];
  wire start_calc;
  wire [4:0] i_value = io_in[7:3];

  wire [BITS_PER_ELEM - 1:0] ra_out;
  assign io_out[BITS_PER_ELEM-1:0] = {3'b000, ra_out[4:0]};


  parameter SRL_SIZE = RA_SIZE + 1;  // RA_SIZE valid inputs and one stale input
  parameter TOTAL_SRL_BITS = 5 * SRL_SIZE;
  wire [TOTAL_SRL_BITS - 1:0] taps;

  shift_register_line #(
      .TOTAL_TAPS(SRL_SIZE),
      .BITS_PER_ELEM(BITS_PER_ELEM),
      .TOTAL_BITS(TOTAL_SRL_BITS)
  ) srl_1 (
      .clk(clk),
      .rst(rst),
      .i_value(i_value[4:0]),
      .i_data_clk(i_data_clk),
      .o_start_calc(start_calc),
      .o_taps(taps[TOTAL_SRL_BITS-1:0])
  );

  // rolling sums RA_SIZE elements + 1 stale element
  parameter RA_NUM_ELEM = RA_SIZE;
  parameter MAX_BITS = 8;  // log_2(31 * 8) = 7.9 ~ 8; where 31 is largest valut for 5 bit elem
  rolling_average #(
      .BITS_PER_ELEM(BITS_PER_ELEM),
      .MAX_BITS(8)
  ) ra_1 (
      .clk(clk),
      .rst(rst),
      .i_new(taps[4:0]),
      .i_old(taps[(4 + 5 * 9):(0 + 5 * 8)]),
      .i_start_calc(start_calc),
      .o_ra(ra_out[BITS_PER_ELEM-1:0])
  );


endmodule
module meriac_tt02_play_tune #( parameter MAX_COUNT = 100 ) (
  input [7:0] io_in,
  output [7:0] io_out
);
    
    wire clk = io_in[0];
    wire reset = io_in[1];
    wire [10:0] db_entry;

    reg [6:0] note_address;
    reg [10:0] ticks;
    reg [6:0] freq, counter;
    reg speaker;

    assign io_out[0] = speaker;
    assign io_out[1] = ~speaker;

    always @(posedge clk) begin

        // if reset, set note_address to 0
        if (reset) begin
            note_address <= 0;
            ticks <= 0;
            freq <= 0;
            counter <= 0;
            speaker <= 0;
        end else begin

            if (!ticks) begin
                if (note_address<MAX_COUNT) begin
                    note_address <= note_address + 1'b1;
                end else begin
                    note_address <= 0;
                end
            end

            // tone frequency divider
            if (counter>0) begin
                counter <= counter - 1'b1;
                speaker <= counter >= (freq/2);
            end else begin
                counter <= freq;
                speaker <= 1'b0;
            end

        end
    end

    always @(negedge clk) begin

        if (!reset) begin

            if (ticks>0) begin
                ticks <= ticks - 1'b1;
            end else begin
                // update per-note delay
                ticks[10:7] <= db_entry[3:0];
                ticks[6:0] <= 0;

                // reset tone generator
                counter <= db_entry[10:4];
                freq <= db_entry[10:4];
            end

        end

    end

    // instantiate tune database
    meriac_tune_db meriac_tune_db(.address(note_address), .db_entry(db_entry));

endmodule
module chase_the_beat (
  input [7:0] io_in,
  output [7:0] io_out
);
    top top(.o(io_out), .clk(io_in[0]), .rst(io_in[1]), .tap(io_in[2]), .mode(io_in[3]));
endmodule
module shan1293_2bitalu(
           input [7:0] io_in,                  
           output [7:0] io_out 
    );
         alu alu(
            .A(io_in[7:6]), 
            .B(io_in[5:4]), 
            .opcode(io_in[3:0]), 
            .ALU_Out(io_out[7:0])
            );
endmodule
module alu(
	input [1:0] A,
	input [1:0] B,
	input [3:0] opcode,
	output [7:0] ALU_Out
);

    reg [7:0] ALU_Result;
    assign ALU_Out = ALU_Result; // ALU out
    always @(*)
    begin
        case(opcode)
        4'b0000: // Addition
           ALU_Result = A + B ; 
        4'b0001: // Subtraction
           ALU_Result = A - B ;
        4'b0010: // Multiplication
           ALU_Result = A * B;
        4'b0011: // Division
           ALU_Result = A/B;
        4'b0100: // Logical shift left one time
           ALU_Result = A<<1;
         4'b0101: // Logical shift right one time
           ALU_Result = A>>1;
         4'b0110: // Logical shift left B times
           ALU_Result = A<<B;
         4'b0111: // Logical shift right B times
           ALU_Result = A>>B;
          4'b1000: //  Logical and 
           ALU_Result = A & B;
          4'b1001: //  Logical or
           ALU_Result = A | B;
          4'b1010: //  Logical xor 
           ALU_Result = A ^ B;
          4'b1011: //  Logical nor
           ALU_Result = ~(A | B);
          4'b1100: // Logical nand 
           ALU_Result = ~(A & B);
          4'b1101: // Logical xnor
           ALU_Result = ~(A ^ B);
          4'b1110: // Greater comparison
           ALU_Result = (A>B)?4'd1:4'd0 ;
          4'b1111: // Equal comparison   
            ALU_Result = (A==B)?4'd1:4'd0 ;
          default: ALU_Result = A + B ; 
        endcase
    end
 endmodule
module tholin_avalonsemi_5401(
   input [7:0] io_in,
   output [7:0] io_out
);

   wire s_CLK = io_in[0];
   wire s_RST = io_in[1];
   wire s_D0 = io_in[2];
   wire s_D1 = io_in[3];
   wire s_D2 = io_in[4];
   wire s_D3 = io_in[5];
   wire s_EF0 = io_in[6];
   wire s_EF1 = io_in[7];
   
   wire s_O_D0_RR0;
   wire s_O_D1_RR1;
   wire s_O_D2_RR2;
   wire s_O_D3_RR3;
   wire s_O_4_MAR;
   wire s_O_5_WRITE;
   wire s_O_6_JMP;
   wire s_O_7_I;
   assign io_out[0] = s_O_D0_RR0;
   assign io_out[1] = s_O_D1_RR1;
   assign io_out[2] = s_O_D2_RR2;
   assign io_out[3] = s_O_D3_RR3;
   assign io_out[4] = s_O_4_MAR;
   assign io_out[5] = s_O_5_WRITE;
   assign io_out[6] = s_O_6_JMP;
   assign io_out[7] = s_O_7_I;
   
   CPU   CIRCUIT_0 (.CLK(s_CLK),
                    .D0(s_D0),
                    .D1(s_D1),
                    .D2(s_D2),
                    .D3(s_D3),
                    .EF0(s_EF0),
                    .EF1(s_EF1),
                    .O_4_MAR(s_O_4_MAR),
                    .O_5_WRITE(s_O_5_WRITE),
                    .O_6_JMP(s_O_6_JMP),
                    .O_7_I(s_O_7_I),
                    .O_D0_RR0(s_O_D0_RR0),
                    .O_D1_RR1(s_O_D1_RR1),
                    .O_D2_RR2(s_O_D2_RR2),
                    .O_D3_RR3(s_O_D3_RR3),
                    .RST(s_RST));
endmodule
module lms_ctr (
	clk_clk,
	exfifo_if_d_export,
	exfifo_if_rd_export,
	exfifo_if_rdempty_export,
	exfifo_of_d_export,
	exfifo_of_wr_export,
	exfifo_of_wrfull_export,
	exfifo_rst_export,
	leds_external_connection_export,
	lms_ctr_gpio_external_connection_export,
	scl_exp_export,
	sda_exp_export,
	spi_1_adf_external_MISO,
	spi_1_adf_external_MOSI,
	spi_1_adf_external_SCLK,
	spi_1_adf_external_SS_n,
	spi_1_dac_external_MISO,
	spi_1_dac_external_MOSI,
	spi_1_dac_external_SCLK,
	spi_1_dac_external_SS_n,
	spi_lms_external_MISO,
	spi_lms_external_MOSI,
	spi_lms_external_SCLK,
	spi_lms_external_SS_n,
	switch_external_connection_export);	

	input		clk_clk;
	input	[31:0]	exfifo_if_d_export;
	output		exfifo_if_rd_export;
	input		exfifo_if_rdempty_export;
	output	[31:0]	exfifo_of_d_export;
	output		exfifo_of_wr_export;
	input		exfifo_of_wrfull_export;
	output		exfifo_rst_export;
	output	[7:0]	leds_external_connection_export;
	output	[3:0]	lms_ctr_gpio_external_connection_export;
	inout		scl_exp_export;
	inout		sda_exp_export;
	input		spi_1_adf_external_MISO;
	output		spi_1_adf_external_MOSI;
	output		spi_1_adf_external_SCLK;
	output		spi_1_adf_external_SS_n;
	input		spi_1_dac_external_MISO;
	output		spi_1_dac_external_MOSI;
	output		spi_1_dac_external_SCLK;
	output		spi_1_dac_external_SS_n;
	input		spi_lms_external_MISO;
	output		spi_lms_external_MOSI;
	output		spi_lms_external_SCLK;
	output	[4:0]	spi_lms_external_SS_n;
	input	[7:0]	switch_external_connection_export;
endmodule
module lms_ctr_sysid_qsys_0 (
               // inputs:
                address,
                clock,
                reset_n,

               // outputs:
                readdata
             )
;

  output  [ 31: 0] readdata;
  input            address;
  input            clock;
  input            reset_n;

  wire    [ 31: 0] readdata;
  //control_slave, which is an e_avalon_slave
  assign readdata = address ? 1476792439 : 4920;

endmodule
module lms_ctr_oc_mem (
                        // inputs:
                         address,
                         byteenable,
                         chipselect,
                         clk,
                         clken,
                         reset,
                         reset_req,
                         write,
                         writedata,

                        // outputs:
                         readdata
                      )
;

  parameter INIT_FILE = "lms_ctr_oc_mem.hex";


  output  [ 31: 0] readdata;
  input   [ 12: 0] address;
  input   [  3: 0] byteenable;
  input            chipselect;
  input            clk;
  input            clken;
  input            reset;
  input            reset_req;
  input            write;
  input   [ 31: 0] writedata;

  wire             clocken0;
  wire    [ 31: 0] readdata;
  wire             wren;
  assign wren = chipselect & write;
  assign clocken0 = clken & ~reset_req;
  altsyncram the_altsyncram
    (
      .address_a (address),
      .byteena_a (byteenable),
      .clock0 (clk),
      .clocken0 (clocken0),
      .data_a (writedata),
      .q_a (readdata),
      .wren_a (wren)
    );

  defparam the_altsyncram.byte_size = 8,
           the_altsyncram.init_file = INIT_FILE,
           the_altsyncram.lpm_type = "altsyncram",
           the_altsyncram.maximum_depth = 8192,
           the_altsyncram.numwords_a = 8192,
           the_altsyncram.operation_mode = "SINGLE_PORT",
           the_altsyncram.outdata_reg_a = "UNREGISTERED",
           the_altsyncram.ram_block_type = "AUTO",
           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
           the_altsyncram.width_a = 32,
           the_altsyncram.width_byteena_a = 4,
           the_altsyncram.widthad_a = 13;

  //s1, which is an e_avalon_slave
  //s2, which is an e_avalon_slave

endmodule
module lms_ctr_uart_rx_stimulus_source (
                                         // inputs:
                                          baud_divisor,
                                          clk,
                                          clk_en,
                                          reset_n,
                                          rx_char_ready,
                                          rxd,

                                         // outputs:
                                          source_rxd
                                       )
;

  output           source_rxd;
  input   [  9: 0] baud_divisor;
  input            clk;
  input            clk_en;
  input            reset_n;
  input            rx_char_ready;
  input            rxd;

  reg     [  7: 0] d1_stim_data;
  reg              delayed_unxrx_char_readyxx0;
  wire             do_send_stim_data;
  wire             pickup_pulse;
  wire             source_rxd;
  wire    [  7: 0] stim_data;
  wire             unused_empty;
  wire             unused_overrun;
  wire             unused_ready;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //stimulus_transmitter, which is an e_instance
  lms_ctr_uart_tx stimulus_transmitter
    (
      .baud_divisor     (baud_divisor),
      .begintransfer    (do_send_stim_data),
      .clk              (clk),
      .clk_en           (clk_en),
      .do_force_break   (1'b0),
      .reset_n          (reset_n),
      .status_wr_strobe (1'b0),
      .tx_data          (d1_stim_data),
      .tx_overrun       (unused_overrun),
      .tx_ready         (unused_ready),
      .tx_shift_empty   (unused_empty),
      .tx_wr_strobe     (1'b1),
      .txd              (source_rxd)
    );

  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_stim_data <= 0;
      else if (do_send_stim_data)
          d1_stim_data <= stim_data;
    end


  assign stim_data = 8'b0;
  //delayed_unxrx_char_readyxx0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          delayed_unxrx_char_readyxx0 <= 0;
      else if (clk_en)
          delayed_unxrx_char_readyxx0 <= rx_char_ready;
    end


  assign pickup_pulse = ~(rx_char_ready) &  (delayed_unxrx_char_readyxx0);
  assign do_send_stim_data = (pickup_pulse || 1'b0) && 1'b0;

//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on
//synthesis read_comments_as_HDL on
//  assign source_rxd = rxd;
//synthesis read_comments_as_HDL off

endmodule
module Serial_flash_loader (
		input  wire  noe_in  // noe_in.noe
	);

	altera_serial_flash_loader #(
		.INTENDED_DEVICE_FAMILY  ("Cyclone IV E"),
		.ENHANCED_MODE           (1),
		.ENABLE_SHARED_ACCESS    ("OFF"),
		.ENABLE_QUAD_SPI_SUPPORT (0),
		.NCSO_WIDTH              (1)
	) serial_flash_loader_0 (
		.noe_in (noe_in)  // noe_in.noe
	);

endmodule
module altera_serial_flash_loader (

	asmi_access_granted,

	asdo_in,

	data_in,

	data_oe,

	dclk_in,

	ncso_in,

	noe_in,

	asmi_access_request,

	data0_out,

	data_out);



	parameter

		ENABLE_QUAD_SPI_SUPPORT = 1,

		ENABLE_SHARED_ACCESS = "ON",

		ENHANCED_MODE = 1,

		INTENDED_DEVICE_FAMILY = "Arria 10",

		NCSO_WIDTH = 3;

		

	input	asmi_access_granted;

	input	asdo_in;

	input	[3:0]  data_in;

	input	[3:0]  data_oe;

	input	dclk_in;

	input	[NCSO_WIDTH-1:0]  ncso_in;

	input	noe_in;

	output	asmi_access_request;

	output	data0_out;

	output	[3:0]  data_out;



	wire	sub_wire0;

	wire	sub_wire1;

	wire	[3:0] sub_wire2;

	wire	asmi_access_request = sub_wire0;

	wire	data0_out = sub_wire1;

	wire	[3:0] data_out = sub_wire2[3:0];



	altserial_flash_loader	altserial_flash_loader_component (

				.asmi_access_granted (asmi_access_granted),

				.data_in (data_in),

				.data_oe (data_oe),

				.dclkin (dclk_in),

				.noe (noe_in),

				.scein (ncso_in),

				.asmi_access_request (sub_wire0),

				.data_out (sub_wire2),

				.data0out (sub_wire1),

				.sdoin (asdo_in)

				);

	defparam

		altserial_flash_loader_component.enable_quad_spi_support = ENABLE_QUAD_SPI_SUPPORT,

		altserial_flash_loader_component.enable_shared_access = ENABLE_SHARED_ACCESS,

		altserial_flash_loader_component.enhanced_mode = ENHANCED_MODE,

		altserial_flash_loader_component.intended_device_family = INTENDED_DEVICE_FAMILY,

		altserial_flash_loader_component.ncso_width = NCSO_WIDTH;





endmodule
module ddr2_traffic_gen (
	clk,
	reset_n,
	pass,
	fail,
	test_complete,
	avl_ready,
	avl_addr,
	avl_size,
	avl_wdata,
	avl_rdata,
	avl_write_req,
	avl_read_req,
	avl_rdata_valid,
	avl_be,
	avl_burstbegin,
	pnf_per_bit,
	pnf_per_bit_persist);	

	input		clk;
	input		reset_n;
	output		pass;
	output		fail;
	output		test_complete;
	input		avl_ready;
	output	[24:0]	avl_addr;
	output	[1:0]	avl_size;
	output	[31:0]	avl_wdata;
	input	[31:0]	avl_rdata;
	output		avl_write_req;
	output		avl_read_req;
	input		avl_rdata_valid;
	output	[3:0]	avl_be;
	output		avl_burstbegin;
	output	[31:0]	pnf_per_bit;
	output	[31:0]	pnf_per_bit_persist;
endmodule
module reset_sync(
	reset_n,
	clk,
	reset_n_sync
);

parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;

input	reset_n;
input	clk;
output	[NUM_RESET_OUTPUT-1:0] reset_n_sync;




// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these resets are localized to the PHY alone, make them routed locally
// to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg	[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;

generate
genvar i;
	for (i=0; i<RESET_SYNC_STAGES+NUM_RESET_OUTPUT-1; i=i+1)
	begin: reset_stage
		always @(posedge clk or negedge reset_n)
		begin
			if (~reset_n)
				reset_reg[i] <= 1'b0;
			else
			begin
				if (i==0)
					reset_reg[i] <= 1'b1;
				else if (i < RESET_SYNC_STAGES)
					reset_reg[i] <= reset_reg[i-1];
				else
					reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
				
			end
		end
	end
endgenerate

	assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];

endmodule
module clkctrl (
	inclk,
	ena,
	outclk);	

	input		inclk;
	input		ena;
	output		outclk;
endmodule
module clkctrl (
		input  wire  inclk,  //  altclkctrl_input.inclk
		input  wire  ena,    //                  .ena
		output wire  outclk  // altclkctrl_output.outclk
	);

	clkctrl_altclkctrl_0 altclkctrl_0 (
		.inclk  (inclk),  //  altclkctrl_input.inclk
		.ena    (ena),    //                  .ena
		.outclk (outclk)  // altclkctrl_output.outclk
	);

endmodule
module  clkctrl_altclkctrl_0_sub
	( 
	ena,
	inclk,
	outclk) /* synthesis synthesis_clearbox=1 */;
	input   ena;
	input   [3:0]  inclk;
	output   outclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri1   ena;
	tri0   [3:0]  inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire  wire_clkctrl1_outclk;
	wire [1:0]  clkselect;
	wire  [1:0]  clkselect_wire;
	wire  [3:0]  inclk_wire;

	cycloneive_clkctrl   clkctrl1
	( 
	.clkselect(clkselect_wire),
	.ena(ena),
	.inclk(inclk_wire),
	.outclk(wire_clkctrl1_outclk)
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		clkctrl1.clock_type = "Global Clock",
		clkctrl1.ena_register_mode = "falling edge",
		clkctrl1.lpm_type = "cycloneive_clkctrl";
	assign
		clkselect = {2{1'b0}},
		clkselect_wire = {clkselect},
		inclk_wire = {inclk},
		outclk = wire_clkctrl1_outclk;
endmodule //clkctrl_altclkctrl_0_sub
module  mgqo8
	( 
	data,
	eq) /* synthesis synthesis_clearbox=1 */;
	input   [3:0]  data;
	output   [15:0]  eq;

	wire  [15:0]   wire_mgl_prim1_eq;

	lpm_decode   mgl_prim1
	( 
	.data(data),
	.eq(wire_mgl_prim1_eq));
	defparam
		mgl_prim1.lpm_decodes = 16,
		mgl_prim1.lpm_type = "LPM_DECODE",
		mgl_prim1.lpm_width = 4;
	assign
		eq = wire_mgl_prim1_eq;
endmodule //mgqo8
module  mg4h8
	( 
	data) /* synthesis synthesis_clearbox=1 */;
	input   [3:0]  data;


	lpm_decode   mgl_prim1
	( 
	.data(data));
	defparam
		mgl_prim1.lpm_decodes = 16,
		mgl_prim1.lpm_type = "LPM_DECODE",
		mgl_prim1.lpm_width = 4;
endmodule //mg4h8
module chirpGenerator(
input                                   chirpReset,
input                                   clk, 
input signed    [`PRECISION-1:0]	    basephase,
input           [`CHIRP_TYPE_SIZE-1:0] 	chirpType, 
input           [`PRECISION-1:0] 		BW_SR,
input           [`PRECISION-1:0] 		phaseInc_val,
input           [`PRECISION-1:0] 		symbol_size,
output wire     [`SinSize-1:0]          outcos, 
output wire     [`SinSize-1:0]          outsin, 
output reg                              done
);
	
reg signed  [`PRECISION-1:0] acc;
reg signed 	[`PRECISION-1:0] accNext;
reg signed  [`PRECISION-1:0] phase;
reg signed 	[`PRECISION-1:0] phaseNext;
reg 			[`PRECISION-1:0] chirp_count;

wire signed [`PRECISION-1:0] phaseNextOut;
wire signed [`PRECISION-1:0] accNextOut;

parameter const1 = 2'd1;
parameter const2 = 2'd2;
parameter const3 = 2'd3;

parameter VSS = 1'b0;

always @(*) begin
    if (chirpReset == VSS) begin
        accNext		=	`PRECISION'd0;
        phaseNext 	=	`PRECISION'd0;
    end else begin
        accNext		=	accNextOut;
        phaseNext	=	phaseNextOut;
    end
end

always @(posedge clk) begin
    if (chirpReset == VSS) begin
        chirp_count     <= `PRECISION'd0;
        acc 			<= `PRECISION'd0;
        phase			<=	`PRECISION'd0;
        done 			<= 1'b0;
    end else begin
        phase <= (chirp_count == `PRECISION'd0) ? basephase : phaseNext;
        acc 	<= accNext;
            
        if (chirpType == `TYPE_Q_DOWNCHIRP) begin
            //chirp_count <= (chirp_count == symbol_size/4-1) ? 0 : chirp_count + 1;
            if ((chirp_count + `PRECISION'd1) == symbol_size) begin
                chirp_count <= `PRECISION'd0;
                done <= 1'b1;
            end else begin
                chirp_count <= chirp_count + `PRECISION'd1;
                done <= 1'b0;
            end
        end else begin
            //chirp_count <= (chirp_count+1 == symbol_size) ? 0 : chirp_count + 1;
            if ((chirp_count + `PRECISION'd1) == symbol_size) begin
                chirp_count <= `PRECISION'd0;
                done <= 1'b1;
            end else begin
                chirp_count <= chirp_count + `PRECISION'd1;
                done <= 1'b0;
            end
        end
    end
end

phaseInc phase_u1(
    .phaseIn(phase),
    .chirpType(chirpType),
    .BW_SR(BW_SR),
    .phaseInc_val(phaseInc_val),
    .phaseOut(phaseNextOut)
);
    
accInc accInc_u1(
    .phaseIn(phase),
    .accIn(acc),
    .accOut(accNextOut)
);

//squareCos squareCos_u1(
    //.angle(acc),
    //.cosOut(outcos)
//);

//squareSin squareSin_u1(
    //.angle(acc),
    //.sinOut(outsin)
//);

cosIdeal cosIdeal_0(
    .angle(acc),
    .cosOut(outcos)
);

sinIdeal sinIdeal_0(
    .angle(acc),
    .sinOut(outsin)
);

endmodule
module DEDFF(
input           clk,
input           rst,
input           D0,
input           D1,
output          Q
);

parameter VSS = 1'b0;
parameter VCC = 1'b1;

reg pose_edge;
reg neg_edge;
wire Q1;
wire Q2;

assign Q1   = neg_edge ^ D0;
assign Q2   = pose_edge ^ D1;
assign Q    = neg_edge ^ pose_edge;

//Pose Edge
always @(posedge clk) begin
    if (rst == VSS) pose_edge   <= VSS;
    else            pose_edge   <= Q1;
end

//Neg Edge
always @(negedge clk) begin
    if (rst == VSS) neg_edge    <= VSS;
    else            neg_edge    <= Q2;
end

endmodule
module clockDivider(
input       clk,
input	    pll_lock,
output reg  clkOut,
output reg  clkLock
);

parameter [7:0] Freq = 4;
reg [7:0] maxWait;

always @(pll_lock) begin
    maxWait = (64/Freq)/2;
end

reg [7:0] lockCounter;
reg [7:0] counter;

always @(posedge clk) begin
    if (pll_lock == 1'b0) begin
        counter     <= 8'd0;
        clkOut      <= 1'b0;
        lockCounter <= 8'd0;
        clkLock     <= 1'b0;
    end else begin
        counter     <= counter + 8'd1;
        if (counter == (maxWait-1)) begin
            clkOut  <= ~clkOut;
            counter <= 8'd0;
        end else begin
            clkOut  <= clkOut;
        end

        lockCounter <= lockCounter + 8'd1;
        if (lockCounter >= 4*2*2*maxWait)
            clkLock <= 1'b1;
        else
            clkLock <= clkLock;
    end
end
endmodule
module counter(
input                       clk,
input	                    clkLock,
output reg                  countDone
);

reg [`WAIT_SIZE-1:0]  waitcount;

always @(posedge clk) begin
    if (clkLock == 1'b0) begin
        countDone 		<= 1'b0;
        waitcount 	    <= `WAIT_SIZE'd0;
    end else begin		
        waitcount       <= (waitcount < `maxWait) ? waitcount + `WAIT_SIZE'd1 : `WAIT_SIZE'd0;
        if (waitcount > `WAIT_SIZE'd50) begin
            countDone   <= 1'b1;
        end else begin
            countDone   <= 1'b0;
        end
    end
end
endmodule
module accInc(
	input signed        [`PRECISION-1:0] 	phaseIn,
	input signed        [`PRECISION-1:0] 	accIn,
	output reg signed   [`PRECISION-1:0]    accOut
);
	
//###################################################################################################
always @(*) begin
    accOut = $signed(accIn + phaseIn);

    // hangle negative
    if ($signed(accOut) < 0) begin
        accOut = $signed(accOut + `SCALE_2X);
    end

    // mod(accInc,2)
    if ($signed(accOut) >= $signed(`SCALE_2X)) begin
        accOut = $signed(accOut - `SCALE_2X);
    end		
end
	
endmodule
module initialPhase(
input                                       clk,
input               [`CHIRP_TYPE_SIZE-1:0]  chirp_type,
input               [`SYMBOL_PRECISION-1:0]	symbol,
input		        [`SIZE_8-1:0]			BW_shift_scale,
input		        [`SYMBOL_PRECISION-1:0] offset,
input 		        [`SYMBOL_PRECISION-1:0] chirp_size,
input		        [`SF_SIZE-1:0]			SF,
input 		        [`PRECISION-1:0] 		BW_SR,
(* syn_preserve = "TRUE" *) output reg signed   [`PRECISION-1:0] 		phaseOut
);

reg [`SYMBOL_PRECISION-1:0] phaseStart;
reg signed [`PRECISION-1:0] phaseOut0;

always @(*) begin
    //phaseStart = $signed(symbol - offset);
    //if ($signed(phaseStart) < 0) begin
        //phaseStart = $signed(phaseStart + chirp_size);
    //end
                
    phaseStart = $signed(symbol);
            
    //new version
    phaseOut0 = `BW_SCALE_SR_MIN >> (SF-1-BW_shift_scale);
    phaseOut0 = $signed(phaseOut0 * phaseStart);

    //phaseOut0 = dir ? $signed(phaseOut0 - BW_SR) : $signed(phaseOut0 + BW_SR);
    if (chirp_type == `TYPE_UPCHIRP)
        phaseOut0 = $signed(phaseOut0 - BW_SR);
    else
        phaseOut0 = $signed(phaseOut0 + BW_SR);
end

always @(posedge clk) begin
    phaseOut <= phaseOut0;
end

endmodule
module constant(
input		                            clk,
input           [`CHIRP_TYPE_SIZE-1:0]  chirp_type,
input			[`SF_SELECT_SIZE-1:0]	SF_select,
input		    [`SIZE_8-1:0]           BW_shift_scale,
(* syn_preserve = "TRUE" *) output reg	    [`PRECISION-1:0] 		BW_SR,
(* syn_preserve = "TRUE" *) output reg	    [`PRECISION-1:0] 		phaseInc_val,
(* syn_preserve = "TRUE" *) output reg	    [`PRECISION-1:0] 		symbol_size
);

reg [`SF_SIZE-1:0]	SF;

reg	[`PRECISION-1:0] 	phaseInc_val0;
reg	[`PRECISION-1:0] 	symbol_size0;
    
always @(*) begin
    case (SF_select)
        `SF_SELECT_12: begin
            SF	=	`SF_12;
        end
        `SF_SELECT_11: begin
            SF	=	`SF_11;
        end
        `SF_SELECT_10: begin
            SF	=	`SF_10;
        end
        `SF_SELECT_9: begin
            SF	=	`SF_9;
        end
        `SF_SELECT_8: begin
            SF	=	`SF_8;
        end
        `SF_SELECT_7: begin
            SF	=	`SF_7;
        end
        `SF_SELECT_6: begin
            SF	=	`SF_6;
        end
        default: begin
            SF	=	`SF_12;
        end
    endcase
end

always @(*) begin
    phaseInc_val0	= (`BW2_SCALE_SR2_MIN << (2*BW_shift_scale + 1));
    phaseInc_val0	= (phaseInc_val0 >> SF);
end

always @(*) begin
    symbol_size0	= (1 << (`minBW_SR_Ratio_Power - BW_shift_scale));
    symbol_size0	= (symbol_size0 << SF);
    ////commented this line, since SR is not 12M.
    //symbol_size0	= symbol_size0 * 3;
    if (chirp_type == `TYPE_Q_DOWNCHIRP)
        symbol_size0 = symbol_size0 >> 2;
end


always @(posedge clk) begin
    BW_SR           <= (`BW_SCALE_SR_MIN << BW_shift_scale);

    phaseInc_val    <= phaseInc_val0;
    
    symbol_size     <= symbol_size0;
end		
		
endmodule
module phaseInc(
input signed 		[`PRECISION-1:0]        phaseIn,
input 				[`CHIRP_TYPE_SIZE-1:0] 	chirpType, 
input 				[`PRECISION-1:0] 		BW_SR,
input 				[`PRECISION-1:0] 		phaseInc_val,
output reg signed	[`PRECISION-1:0] 	    phaseOut
);


reg 	[`PRECISION-1:0] BW_SR_2x;

always @(*) begin
    BW_SR_2x = $signed(BW_SR << 1);
    
    //if (chirpType == `TYPE_UPCHIRP) begin
        //phaseOut = $signed(phaseIn + phaseInc_val);
        //
        //////clip chirp symbol at sampling rate
        //if ($signed(phaseOut) > $signed(BW_SR)) begin
            //phaseOut = $signed(phaseOut - BW_SR_2x);
        //end
    //end else begin
        //phaseOut = $signed(phaseIn - phaseInc_val);
        //////clip chirp symbol at bandwidth
        //if ($signed(phaseOut) < $signed(-1*BW_SR)) begin
            //phaseOut = $signed(phaseOut + BW_SR_2x);
        //end else if ($signed(phaseOut) > $signed(BW_SR)) begin
            //phaseOut = $signed(phaseOut - BW_SR_2x);
        //end
    //end

    //new version
    if (chirpType == `TYPE_UPCHIRP) begin
        phaseOut = $signed(phaseIn + phaseInc_val);
    end else begin
        phaseOut = $signed(phaseIn - phaseInc_val);
    end

    
    ////clip chirp symbol at sampling rate
    if ($signed(phaseOut) > $signed(BW_SR)) begin
        phaseOut = $signed(phaseOut - BW_SR_2x);
    end else if ($signed(phaseOut) < $signed(-1*BW_SR)) begin
        phaseOut = $signed(phaseOut + BW_SR_2x);
    end
end

endmodule
module register8(input clk, input [7:0] D, input EI, output reg [7:0] Q);
wire CLK;
assign CLK=(clk & EI);
always @(posedge CLK)
begin
    Q <= D;
end
endmodule
module ALU(input op, input [7:0] A, input [7:0] B, output [8:0] res);
assign res[8:0] = op ? (A[7:0] - B[7:0]) : (A[7:0] + B[7:0]);
endmodule
module CPU(input clkin, output [7:0] OutPut, output [6:0] LED1, output [6:0] LED2);
wire [7:0] bus;
wire [3:0] MemAddr;
wire [7:0] Aout;
wire [7:0] Bout;
wire [7:0] Instout;
wire [3:0] Pcount;
wire [3:0] Addr_in;
wire [7:0] Dispout;
wire [7:0] aluOut;
wire HLT, MI, RI, RO, IO, II, AI, AO, SO, SU, BI, OI, CE, CO, J;
wire PCrst, flag;


assign clk = (clkin & ~HLT);


register8 A(.clk(clk), .D(bus), .Q(Aout), .EI(AI));
tristateBuff triA(.data(Aout), .dataOut(bus), .enable(AO));

register8 B(.clk(clk), .D(bus), .Q(Bout), .EI(BI));

register8 InstReg(.clk(clk), .D(bus), .Q(Instout), .EI(II));
triBuff4 triInstReg(.data(Instout[3:0]), .dataOut(bus[3:0]), .enable(IO));

ALU alu(.A(Aout), .B(Bout), .op(SU), .res({flag,aluOut}));
tristateBuff tri_alu(.data(aluOut), .enable(SO), .dataOut(bus));


PC pc(.clk(clk), .rst(1'b0), .enable(CE), .jmp(J), .jmploc(bus[3:0]), .count(Pcount));
triBuff4 tripc(.data(Pcount), .dataOut(bus[3:0]), .enable(CO));


register4 MemAdd(.clk(clk), .D(bus[3:0]), .Q(Addr_in), .EI(MI));

RAM ram(.clk(~clk), .address(Addr_in), .write_enable(RI), .read_enable(RO), .data(bus));


IC ic(.clk(clk), .enable(1'b1), .Instruction(Instout[7:4]), .ctrl_wrd({HLT, MI, RI, RO, IO, II, AI, AO, SO, SU, BI, OI, CE, CO, J}));


register8 O(.clk(clk), .D(bus), .Q(OutPut), .EI(OI));


bcd2sevenseg seg0(.bcd(OutPut[3:0]), .seg(LED1));
bcd2sevenseg seg1(.bcd(OutPut[7:4]), .seg(LED2));

endmodule
module CPUtb();
reg clk;
wire [7:0] outPut;
wire [6:0] LED1;
wire [6:0] LED2;

initial begin
    clk <= 0;
    forever begin
        #10;
        clk <= ~clk;
    end
end

CPU cpu(.clkin(clk), .OutPut(outPut), .LED1(LED1), .LED2(LED2));

initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0, CPUtb);
    #1000;
    $finish;
end

endmodule
module register4(input clk, input [3:0] D, input EI, output reg [3:0] Q);
wire CLK;
assign CLK=(clk & EI);
always @(posedge CLK)
begin
    Q <= D;
end
endmodule
module RAM(input clk, input [3:0] address, input write_enable, input read_enable, inout [7:0] data);
reg [7:0] Memory[15:0];
reg [7:0] buffer;

initial begin
    Memory[0] <= 8'b0001_1010;
    Memory[1] <= 8'b0010_1011;
    Memory[2] <= 8'b0100_0101;
    Memory[3] <= 8'b0011_1100;
    Memory[4] <= 8'b0010_1101;
    Memory[5] <= 8'b1110_0000;
    Memory[6] <= 8'b0001_1110;
    Memory[7] <= 8'b0010_1111;
    Memory[8] <= 8'b1110_0000;
    Memory[9] <= 8'b1111_0000;
    Memory[10] <= 8'b0000_0011;
    Memory[11] <= 8'b0000_0010;
    Memory[12] <= 8'b0000_0001;
    Memory[13] <= 8'b0000_0101;
    Memory[14] <= 8'b0000_1010;
    Memory[15] <= 8'b0000_1011;
end


always @(posedge clk)
begin
    if(write_enable & ~read_enable)
    begin
        Memory[address] <= data;
    end
    else
    begin
        buffer <= Memory[address];
    end
end

assign data = (read_enable & ~write_enable) ? buffer : 8'bzzzzzzzz;

endmodule
module tristateBuff(input [7:0] data, input enable, output [7:0] dataOut);
    assign dataOut = enable ? data : 8'bzzzzzzzz;
endmodule
module triBuff4(input [3:0] data, input enable, output [3:0] dataOut);
    assign dataOut = enable ? data : 4'bzzzz;
endmodule
module bcd2sevenseg(
    input [3:0] bcd,
    output reg [6:0] seg
    );
always @(bcd)
begin
    case (bcd)
        0 : seg <= 7'b1111110;
        1 : seg <= 7'b0110000;
        2 : seg <= 7'b1101101;
        3 : seg <= 7'b1111001;
        4 : seg <= 7'b0110011;
        5 : seg <= 7'b1011011;
        6 : seg <= 7'b1011111;
        7 : seg <= 7'b1110000;
        8 : seg <= 7'b1111111;
        9 : seg <= 7'b1111011;
        10 : seg <= 7'b1110111;
        11 : seg <= 7'b0011111;
        12 : seg <= 7'b1001110;
        13 : seg <= 7'b0111101;
        14 : seg <= 7'b1001111;
        15 : seg <= 7'b1000111;
        default : seg <= 7'b0000000; 
    endcase
end  
endmodule
module PC(input clk, input rst, input enable, input [3:0] jmploc, input jmp, output reg [3:0] count);
wire CLK;
assign CLK = (clk & enable);
initial begin
    count <= 4'b0000;
end
always @(posedge CLK)
begin
    if(rst)
    begin
        count <= 4'b0000;
    end
    else
    begin
        count <= count + 1;
    end
end

always @(posedge clk)
begin
    if(jmp)
    begin
        count <= jmploc;
    end
end
endmodule
module IC(input clk, input enable, input [3:0] Instruction, output reg [14:0] ctrl_wrd);
wire CLK;
//reg [3:0] Instruction;
assign CLK = (~clk & enable);
reg [2:0] Inst_count;
reg reset_in;

initial begin
    Inst_count <= 3'b111;
    reset_in <= 1'b0;
end
always @ (posedge CLK)
    begin
        Inst_count <= reset_in ? 3'b000 : Inst_count+1;
        reset_in <= 1'b0;
        case(Inst_count)//HLT, MI, RI, RO, IO, II, AI, AO, SO, SU, BI, OI, CE, CO, J;
            3'b000: ctrl_wrd <= 15'b010000000000010;
            3'b001: ctrl_wrd <= 15'b000101000000100;
            3'b010: begin
                    case(Instruction)
                    4'b0001: ctrl_wrd <= 15'b010010000000000; // LDA
                    4'b0010: ctrl_wrd <= 15'b010010000000000; //ADD
                    4'b0011: ctrl_wrd <= 15'b010010000000000;  //SUBT
                    4'b1110: ctrl_wrd <= 15'b000000010001000; // OUT
                    4'b0100: ctrl_wrd <= 15'b000010000000001; // JMP
                    4'b1111: ctrl_wrd <= 15'b100000000000000; // HLT
                    default: ctrl_wrd <= 15'b000000000000000;
                    endcase 
                    end      
            3'b011: begin
                    case(Instruction)
                    4'b0001: ctrl_wrd <= 15'b000100100000000; // LDA
                    4'b0010: ctrl_wrd <= 15'b000100000010000; //ADD
                    4'b0011: ctrl_wrd <= 15'b000100000010000; //SUBT
                    4'b1110: ctrl_wrd <= 15'b000000000000000; // OUT
                    4'b0100: ctrl_wrd <= 15'b000000000000000; // JMP
                    4'b1111: ctrl_wrd <= 15'b000000000000000; // HLT
                    default: ctrl_wrd <= 15'b000000000000000;
                    endcase             
                    end
            3'b100: begin
                    case(Instruction)
                    4'b0001: ctrl_wrd <= 15'b000000000000000; // LDA done
                    4'b0010: ctrl_wrd <= 15'b000000101000000; //ADD
                    4'b0011: ctrl_wrd <= 15'b000000101100000; //SUBT
                    4'b1110: ctrl_wrd <= 15'b000000000000000; // OUT
                    4'b0100: ctrl_wrd <= 15'b000000000000000; // JMP
                    4'b1111: ctrl_wrd <= 15'b000000000000000; // HLT
                    default: ctrl_wrd <= 15'b000000000000000;
                    endcase 
                    reset_in <= 1'b1; // Have some doubt here..... Maybe this part can go wrong .....
                    end                  
            default: ctrl_wrd <= 15'b000000000000000;
        endcase                          
    end


endmodule
module dff #(
  parameter gp_data_width = 8                  // Set input & output bit-width
) 
(
  input  wire                     i_rst_an,    // Asynchronous active low reset
  input  wire                     i_ena,       // Synchronous active high enable
  input  wire                     i_clk,       // Rising-edge clock
  input  wire [gp_data_width-1:0] i_data,      // Input data with gp_data_width bits MSB:LSB, signed or unsigned
  output wire [gp_data_width-1:0] o_data       // Output data with gp_data_width bits MSB:LSB, signed or unsigned
);
// -------------------------------------------------------------------
  reg [gp_data_width-1:0] r_data;
// -------------------------------------------------------------------  
  always @(posedge i_clk or negedge i_rst_an)
    begin: p_dff
      if (!i_rst_an)
        r_data <= 'd0;
      else if (i_ena)
        r_data <= i_data;  
    end
  
  assign o_data = r_data;
endmodule
module shift_register #(
  parameter gp_data_width = 8,                   // Input & output bit-width
  parameter gp_nr_stages  = 4                    // Number of shift registers
) (
  input  wire                     i_rst_an,      // Asynchronous active low reset
  input  wire                     i_ena,         // Synchronous active high enable
  input  wire                     i_clk,         // Rising-edge clock
  input  wire [gp_data_width-1:0] i_data,        // Input data with p_data_width bits MSB:LSB, signed
  output wire [gp_data_width-1:0] o_data,        // Output data with p_data_width bits MSB:LSB, signed
  output wire                     o_shift_done   // Flag indicates inital shift operation is done 
);
// -------------------------------------------------------------------
  // CONSTANT DECLARATION
  localparam c_cnt_width = $clog2(gp_nr_stages);
  // REGISTER DECLARATION
  reg [c_cnt_width-1:0]                 r_cnt;
  reg                                   r_shift_done; 
  // WIRE DECLARATION
  wire                                  w_shift_done;
  wire [gp_nr_stages*gp_data_width-1:0] w_data;
// -------------------------------------------------------------------  
  genvar i;  
  generate
    //begin: g_shift_register
      for (i=0; i<gp_nr_stages; i=i+1)
        begin: g_shift_register_loop
	  if (i==0)
	    begin: g_shift_register_0
	      dff #(
              .gp_data_width (gp_data_width)
              ) REG_COMMUTATOR_INP_DATA  (
              .i_rst_an (i_rst_an),
              .i_ena    (i_ena),
              .i_clk    (i_clk),
              .i_data   (i_data),
              .o_data   (w_data[(i+1)*gp_data_width-1 -: gp_data_width])
              );
	    end
	  else
	    begin: g_shift_register_1_n
	      dff #(
              .gp_data_width (gp_data_width)
              ) REG_COMMUTATOR_INP_DATA  (
              .i_rst_an (i_rst_an),
              .i_ena    (i_ena),
              .i_clk    (i_clk),
              .i_data   (w_data[(i)*gp_data_width-1 -: gp_data_width]),
              .o_data   (w_data[(i+1)*gp_data_width-1 -: gp_data_width])
              );	    
	    end
	  end
    //end
  endgenerate
  
  always @(posedge i_clk or negedge i_rst_an)
    begin: p_count_done
      if (!i_rst_an)
        begin
	  r_cnt        <= {c_cnt_width{1'b1}};
	  r_shift_done <= 1'b0;
	end
      else if (i_ena)
        begin
	  if (r_cnt<gp_nr_stages)
	    r_cnt <= r_cnt + 1'b1;
	  else
	      r_cnt <= 'd0;
	      
	  if (w_shift_done)
	    r_shift_done <= 1'b1;	    
	end
    end
    
assign w_shift_done = (r_cnt == (gp_nr_stages-1)) ? 1'b1 : r_shift_done;
assign o_shift_done = w_shift_done;
assign o_data       = w_data[gp_nr_stages*gp_data_width-1 -: gp_data_width];  

endmodule