module mig_7series_v4_2_axi_mc_b_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
                    // Width of ID signals.
                    // Range: >= 1.
  parameter integer C_ID_WIDTH                = 4 
                    
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations     
///////////////////////////////////////////////////////////////////////////////
  input  wire                                 clk,
  input  wire                                 reset,

  // AXI signals
  output wire [C_ID_WIDTH-1:0]                bid,
  output wire [1:0]                           bresp,
  output wire                                 bvalid,
  input  wire                                 bready,

  // Signals to/from the axi_mc_aw_channel modules
  input  wire                                 b_push,
  input  wire [C_ID_WIDTH-1:0]                b_awid,
  input  wire                                 b_resp_rdy,
  output wire                                 b_full

);

////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// FIFO settings
localparam P_WIDTH  = C_ID_WIDTH;
localparam P_DEPTH  = 8;
localparam P_AWIDTH = 3;
// AXI protocol responses:
localparam P_OKAY   = 2'b00;
localparam P_EXOKAY = 2'b01;
localparam P_SLVERR = 2'b10;
localparam P_DECERR = 2'b11;

localparam B_RESP_PERF = 1'b1; 	// Set to 1 to increase the write response performance for back to back single beats.
				// Set to 0 in case of timing issues, but performance degrades for back to back single beats.
wire                    empty;
wire                    bhandshake;
wire [C_ID_WIDTH-1:0]   bid_i;

reg                     b_pop;
reg                     bvalid_i;
reg  [C_ID_WIDTH-1:0]   bid_t;

assign bresp      = P_OKAY;

generate
  if (B_RESP_PERF == 1) begin
  
    assign bid        = bid_t;
    assign bvalid     = bvalid_i;
    assign bhandshake  = ~bvalid | bready;
    
    always @(*)
      b_pop = bhandshake & ~empty;
    
    always @(posedge clk) begin
      if(reset) begin
        bid_t <= 'b0;
        bvalid_i <= 1'b0;
      end else if(bhandshake) begin
        bid_t <= bid_i;
        bvalid_i <= ~empty;
      end
    end
  
  end else begin // B_RESP_PERF
  
    assign bid        = bid_i;
    assign bvalid     = bvalid_i;
    assign bhandshake = bvalid & bready;
    
    always @(posedge clk)
      b_pop <= bhandshake;
       
    always @(posedge clk) begin
      if (reset | bhandshake) begin
        bvalid_i <= 1'b0;
      end else if (~empty & (~b_pop)) begin
        bvalid_i <= 1'b1;
      end
    end
    
  end // B_RESP_PERF
endgenerate

mig_7series_v4_2_axi_mc_fifo #
  (
  .C_WIDTH                  (P_WIDTH),
  .C_AWIDTH                 (P_AWIDTH),
  .C_DEPTH                  (P_DEPTH)
)
bid_fifo_0
(
  .clk     ( clk        ) ,
  .rst     ( reset      ) ,
  .wr_en   ( b_push     ) ,
  .rd_en   ( b_pop      ) ,
  .din     ( b_awid     ) ,
  .dout    ( bid_i      ) ,
  .a_full  (            ) ,
  .full    ( b_full     ) ,
  .a_empty (            ) ,
  .empty   ( empty      ) 
);

endmodule