dakies/OSS_Verilog huggingface dataset:
module Posit_to_FP_tb_v;

function [31:0] log2;
input reg [31:0] value;
	begin
	value = value-1;
	for (log2=0; value>0; log2=log2+1)
        	value = value>>1;
      	end
endfunction

parameter N=32;
parameter E=8;
parameter Bs=log2(N);
parameter es = 3;

reg [N-1:0] in;
reg clk;

wire [N-1:0] out;

// Instantiate the Unit Under Test (UUT)
Posit_to_FP #(.N(N), .E(E), .es(es)) d1 (
	.in(in), 
	.out(out) 
	);


	initial begin
		// Initialize Inputs
		clk = 1;
		// Wait 100 ns for global reset to finish
		#101 in = 65535;

		#655360

		$fclose(outfile);
		$finish;
	end
	
always #5 clk=~clk;
always @(posedge clk) begin
	if (in < 32'hffffffff) 
		in <= in + 65535;
end

integer outfile;
initial outfile = $fopen("Posit_to_FP_out.txt", "wb");
  always @(negedge clk) begin
     $fwrite(outfile, "%h\t%h\n",in,out);
  end

endmodule
module data_extract(in, rc, regime, exp, mant, Lshift);

function [31:0] log2;
input reg [31:0] value;
	begin
	value = value-1;
	for (log2=0; value>0; log2=log2+1)
        	value = value>>1;
      	end
endfunction

parameter N=16;
parameter Bs=log2(N);
parameter es = 2;
input [N-1:0] in;
output rc;
output [Bs-1:0] regime, Lshift;
output [es-1:0] exp;
output [N-es-1:0] mant;

wire [N-1:0] xin = in;
assign rc = xin[N-2];
wire [Bs-1:0] k0, k1;
LOD_N #(.N(N)) xinst_k0(.in({xin[N-2:0],1'b0}), .out(k0));
LZD_N #(.N(N)) xinst_k1(.in({xin[N-3:0],2'b0}), .out(k1));

assign regime = xin[N-2] ? k1 : k0;
assign Lshift = xin[N-2] ? k1+1 : k0;

wire [N-1:0] xin_tmp;
DSR_left_N_S #(.N(N), .S(Bs)) ls (.a({xin[N-3:0],2'b0}),.b(Lshift),.c(xin_tmp));

assign exp= xin_tmp[N-1:N-es];
assign mant= xin_tmp[N-es-1:0];

endmodule
module FP_to_posit(in, out);

function [31:0] log2;
input reg [31:0] value;
	begin
	value = value-1;
	for (log2=0; value>0; log2=log2+1)
        	value = value>>1;
      	end
endfunction

parameter N = 16;
parameter E = 5;
parameter es = 2;	//ES_max = E-1
parameter M = N-E-1;
parameter BIAS = (2**(E-1))-1;

parameter Bs = log2(N);

input [N-1:0] in;
output [N-1:0] out;

wire s_in = in[N-1];
wire [E-1:0] exp_in = in[N-2:N-1-E];
wire [M-1:0] mant_in = in[M-1:0];
wire zero_in = ~|{exp_in,mant_in};
wire inf_in = &exp_in;

wire [M:0] mant = {|exp_in, mant_in};

wire [N-1:0] LOD_in = {mant,{E{1'b0}}};
wire[Bs-1:0] Lshift;
LOD_N #(.N(N)) uut (.in(LOD_in), .out(Lshift));

wire[N-1:0] mant_tmp;
DSR_left_N_S #(.N(N), .S(Bs)) ls (.a(LOD_in),.b(Lshift),.c(mant_tmp));

wire [E:0] exp = {exp_in[E-1:1], exp_in[0] | (~|exp_in)} - BIAS - Lshift;

//Exponent and Regime Computation
wire [E:0] exp_N = exp[E] ? -exp : exp;
wire [es-1:0] e_o = (exp[E] & |exp_N[es-1:0]) ? exp[es-1:0] : exp_N[es-1:0];
wire [E-es-1:0] r_o = (~exp[E] || (exp[E] & |exp_N[es-1:0])) ? {{Bs{1'b0}},exp_N[E-1:es]} + 1'b1 : {{Bs{1'b0}},exp_N[E-1:es]};

//Exponent and Mantissa Packing
wire [2*N-1:0]tmp_o = { {N{~exp[E]}}, exp[E], e_o, mant_tmp[N-2:es]};

//Including Regime bits in Exponent-Mantissa Packing
wire [2*N-1:0] tmp1_o;
wire [Bs-1:0] diff_b;
generate
	if(E-es > Bs) 	assign diff_b = |r_o[E-es-1:Bs] ? {{(Bs-2){1'b1}},2'b01} : r_o[Bs-1:0];
	else 		assign diff_b = r_o;
endgenerate
DSR_right_N_S #(.N(2*N), .S(Bs)) dsr2 (.a(tmp_o), .b(diff_b), .c(tmp1_o));

//Final Output
wire [N-1:0] tmp1_oN = s_in ? -tmp1_o[N-1:0] : tmp1_o[N-1:0];
assign out = inf_in|zero_in|(~mant_tmp[N-1]) ? {inf_in,{N-1{1'b0}}} : {s_in, tmp1_oN[N-1:1]};

endmodule
module FP_to_posit_tb_v;

function [31:0] log2;
input reg [31:0] value;
	begin
	value = value-1;
	for (log2=0; value>0; log2=log2+1)
        	value = value>>1;
      	end
endfunction

parameter N=32;
parameter E=8;
parameter Bs=log2(N);
parameter es = 4;

reg [N-1:0] in;
reg clk;

wire [N-1:0] out;

// Instantiate the Unit Under Test (UUT)
FP_to_posit #(.N(N), .E(E), .es(es)) d1 (
	.in(in), 
	.out(out) 
	);


	initial begin
		// Initialize Inputs
		clk = 1;
		// Wait 100 ns for global reset to finish
		#101 in = 32'h0080ffff;
		#325150 
		$fclose(outfile);
		$finish;
	end
	
always #5 clk=~clk;
always @(posedge clk) begin
	if (in < 32'h7f7fffff)
		in <= in + 65535;
end

integer outfile;
initial outfile = $fopen("FP_to_posit_out.txt", "wb");
  always @(negedge clk) begin
     $fwrite(outfile, "%h\t%h\n",in,out);
  end

endmodule
module add_mantovf (a,mant_ovf,c);
parameter N=10;
input [N:0] a;
input mant_ovf;
output [N:0] c;
assign c = a + mant_ovf;
endmodule
module sub_N (a,b,c);
parameter N=10;
input [N-1:0] a,b;
output [N:0] c;
assign c = {1'b0,a} - {1'b0,b};
endmodule
module add_N (a,b,c);
parameter N=10;
input [N-1:0] a,b;
output [N:0] c;
assign c = {1'b0,a} + {1'b0,b};
endmodule
module tri_mode_ethernet_mac_0_bram_tdp #(
    parameter DATA_WIDTH = 8,
    parameter ADDR_WIDTH = 12
) (
    // Port A
    input   wire                      a_clk,
    input   wire                      a_rst,
    input   wire                      a_wr,
    input   wire    [ADDR_WIDTH-1:0]  a_addr,
    input   wire    [DATA_WIDTH-1:0]  a_din,

    // Port B
    input   wire                      b_clk,
    input   wire                      b_en,
    input   wire                      b_rst,
    input   wire    [ADDR_WIDTH-1:0]  b_addr,
    output  reg     [DATA_WIDTH-1:0]  b_dout
);

// Shared memory
localparam RAM_DEPTH = 2 ** ADDR_WIDTH;
reg [DATA_WIDTH-1:0] mem [RAM_DEPTH-1:0];

// To write use port A
always @(posedge a_clk)
begin
    if(!a_rst && a_wr) begin
        mem[a_addr] <= a_din;
    end
end

// To read use Port B
always @(posedge b_clk)
begin
    if(b_rst)
       b_dout      <= {DATA_WIDTH{1'b0}};
    else if(b_en)
       b_dout      <= mem[b_addr];
end

endmodule
module tri_mode_ethernet_mac_0_reset_sync #(
  parameter INITIALISE = 1'b1,
  parameter DEPTH = 5
)
(
   input       reset_in,
   input       clk,
   input       enable,
   output      reset_out
);


  wire     reset_sync_reg0;
  wire     reset_sync_reg1;
  wire     reset_sync_reg2;
  wire     reset_sync_reg3;
  wire     reset_sync_reg4;

  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
  FDPE #(
   .INIT (INITIALISE[0])
  ) reset_sync0 (
  .C  (clk),
  .CE (enable),
  .PRE(reset_in),
  .D  (1'b0),
  .Q  (reset_sync_reg0)
  );

  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
  FDPE #(
   .INIT (INITIALISE[0])
  ) reset_sync1 (
  .C  (clk),
  .CE (enable),
  .PRE(reset_in),
  .D  (reset_sync_reg0),
  .Q  (reset_sync_reg1)
  );

  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
  FDPE #(
   .INIT (INITIALISE[0])
  ) reset_sync2 (
  .C  (clk),
  .CE (enable),
  .PRE(reset_in),
  .D  (reset_sync_reg1),
  .Q  (reset_sync_reg2)
  );

  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
  FDPE #(
   .INIT (INITIALISE[0])
  ) reset_sync3 (
  .C  (clk),
  .CE (enable),
  .PRE(reset_in),
  .D  (reset_sync_reg2),
  .Q  (reset_sync_reg3)
  );

  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
  FDPE #(
   .INIT (INITIALISE[0])
  ) reset_sync4 (
  .C  (clk),
  .CE (enable),
  .PRE(reset_in),
  .D  (reset_sync_reg3),
  .Q  (reset_sync_reg4)
  );


assign reset_out = reset_sync_reg4;


endmodule
module tri_mode_ethernet_mac_0_sync_block #(
  parameter INITIALISE = 1'b0,
  parameter DEPTH = 5
)
(
  input        clk,              // clock to be sync'ed to
  input        data_in,          // Data to be 'synced'
  output       data_out          // synced data
);

  // Internal Signals
  wire   data_sync0;
  wire   data_sync1;
  wire   data_sync2;
  wire   data_sync3;
  wire   data_sync4;


  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
  FDRE #(
    .INIT (INITIALISE[0])
  ) data_sync_reg0 (
    .C  (clk),
    .D  (data_in),
    .Q  (data_sync0),
	.CE (1'b1),
    .R  (1'b0)
  );

  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
  FDRE #(
   .INIT (INITIALISE[0])
  ) data_sync_reg1 (
  .C  (clk),
  .D  (data_sync0),
  .Q  (data_sync1),
  .CE (1'b1),
  .R  (1'b0)
  );

  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
  FDRE #(
   .INIT (INITIALISE[0])
  ) data_sync_reg2 (
  .C  (clk),
  .D  (data_sync1),
  .Q  (data_sync2),
  .CE (1'b1),
  .R  (1'b0)
  );

  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
  FDRE #(
   .INIT (INITIALISE[0])
  ) data_sync_reg3 (
  .C  (clk),
  .D  (data_sync2),
  .Q  (data_sync3),
  .CE (1'b1),
  .R  (1'b0)
  );

  (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
  FDRE #(
   .INIT (INITIALISE[0])
  ) data_sync_reg4 (
  .C  (clk),
  .D  (data_sync3),
  .Q  (data_sync4),
  .CE (1'b1),
  .R  (1'b0)
  );

  assign data_out = data_sync4;


endmodule
module tri_mode_ethernet_mac_0_syncer_level
#(
  parameter WIDTH       = 1,
  parameter RESET_VALUE = 1'b0
 )
(
  input  wire clk,
  input  wire reset,

  input  wire [WIDTH-1:0] datain,
  output wire [WIDTH-1:0] dataout
);

  (* ASYNC_REG = "TRUE" *) reg  [WIDTH-1:0] dataout_reg;
  reg  [WIDTH-1:0] meta_nxt;
  wire [WIDTH-1:0] dataout_nxt;

  (* ASYNC_REG = "TRUE" *) reg  [WIDTH-1:0] meta;
  (* ASYNC_REG = "TRUE" *) reg  [WIDTH-1:0] meta2;
  always @*
    begin
      meta_nxt = datain;
    end

  always @( posedge clk )
    begin
      if ( reset == 1'b1 )
        begin
          meta  <= {WIDTH{RESET_VALUE}};
          meta2 <= {WIDTH{RESET_VALUE}};
        end
      else
        begin
          meta  <= meta_nxt;
          meta2 <= meta;
        end
    end

  assign dataout_nxt = meta2;

  always @( posedge clk )
    begin
      if ( reset == 1'b1 )
        begin
          dataout_reg <= {WIDTH{RESET_VALUE}};
        end
      else
        begin
          dataout_reg <= dataout_nxt;
        end
    end

  assign dataout = dataout_reg;

endmodule // syncer_level
module tri_mode_ethernet_mac_0_axi_mux (
   input                   mux_select,

   // mux inputs
   input       [7:0]       tdata0,
   input                   tvalid0,
   input                   tlast0,
   output reg              tready0,
   
   input       [7:0]       tdata1,
   input                   tvalid1,
   input                   tlast1,
   output reg              tready1,
   
   // mux outputs
   output reg  [7:0]       tdata,
   output reg              tvalid,
   output reg              tlast,
   input                   tready
);

always @(mux_select or tdata0 or tvalid0 or tlast0 or tdata1 or 
         tvalid1 or tlast1)
begin
   if (mux_select) begin
      tdata    = tdata1;
      tvalid   = tvalid1;
      tlast    = tlast1;
   end
   else begin
      tdata    = tdata0;
      tvalid   = tvalid0;
      tlast    = tlast0;
   end
end

always @(mux_select or tready)
begin
   if (mux_select) begin
      tready0     = 1'b1;
   end
   else begin
      tready0     = tready;
   end
   tready1     = tready;
end

endmodule
module user_module_341608297106768466(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4;
  wire net5 = 1'b0;
  wire net6 = 1'b1;
  wire net7 = 1'b1;
  wire net8;

  assign io_out[0] = net4;

  and_cell gate1 (
    .a (net1),
    .b (net2),
    .out (net8)
  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  and_cell gate7 (
    .a (net8),
    .b (net3),
    .out (net4)
  );
endmodule
module user_module_341581732833657427(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[6];
  wire net3 = io_in[7];
  wire net4;
  wire net5;
  wire net6;
  wire net7 = 1'b0;
  wire net8 = 1'b1;
  wire net9 = 1'b1;
  wire net10;
  wire net11;
  wire net12 = 1'b1;
  wire net13;
  wire net14;
  wire net15;
  wire net16;
  wire net17;
  wire net18;
  wire net19;
  wire net20 = 1'b0;
  wire net21 = 1'b0;
  wire net22;
  wire net23;
  wire net24;

  assign io_out[0] = net4;
  assign io_out[3] = net5;
  assign io_out[6] = net6;

  and_cell gate1 (

  );
  or_cell gate2 (
    .a (net2),
    .b (net3),
    .out (net10)
  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  dff_cell flipflop2 (
    .d (net10),
    .clk (net1),
    .q (net11)
  );
  xor_cell gate7 (
    .a (net5),
    .b (net12),
    .out (net13)
  );
  and_cell gate8 (
    .a (net5),
    .b (net12),
    .out (net14)
  );
  dff_cell flipflop3 (
    .d (net11),
    .clk (net1),
    .q (net15)
  );
  not_cell gate9 (
    .in (net15),
    .out (net16)
  );
  and_cell gate10 (
    .a (net16),
    .b (net11),
    .out (net17)
  );
  dff_cell flipflop4 (
    .d (net13),
    .clk (net17),
    .q (net5)
  );
  dff_cell flipflop5 (
    .d (net18),
    .clk (net17),
    .q (net6)
  );
  xor_cell gate11 (
    .a (net14),
    .b (net19),
    .out (net18)
  );
  xor_cell gate12 (
    .a (net6),
    .b (net20),
    .out (net19)
  );
  and_cell gate13 (
    .a (net6),
    .b (net21),
    .out (net22)
  );
  and_cell gate14 (
    .a (net19),
    .b (net14),
    .out (net23)
  );
  or_cell gate15 (
    .a (net22),
    .b (net23),
    .out (net24)
  );
  dff_cell flipflop6 (
    .d (net24),
    .clk (net17),
    .q (net4)
  );
endmodule
module user_module_341497971083313748(
  input wire [7:0] io_in,
  output wire [7:0] out
);
  wire [1:0] add_347;
  wire [1:0] add_349;
  wire [1:0] add_351;
  wire [1:0] add_353;
  wire [2:0] add_359;
  wire [2:0] add_361;
  wire [3:0] add_365;
  assign add_347 = {1'h0, io_in[0]} + {1'h0, io_in[1]};
  assign add_349 = {1'h0, io_in[2]} + {1'h0, io_in[3]};
  assign add_351 = {1'h0, io_in[4]} + {1'h0, io_in[5]};
  assign add_353 = {1'h0, io_in[6]} + {1'h0, io_in[7]};
  assign add_359 = {1'h0, add_347} + {1'h0, add_349};
  assign add_361 = {1'h0, add_351} + {1'h0, add_353};
  assign add_365 = {1'h0, add_359} + {1'h0, add_361};
  assign out = {4'h0, add_365};
endmodule
module user_module_339688086163161683(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5;
  wire net6 = 1'b0;
  wire net7 = 1'b1;
  wire net8 = 1'b1;
  wire net9;
  wire net10;
  wire net11;
  wire net12;

  assign io_out[0] = net5;
  assign io_out[1] = net5;
  assign io_out[2] = net5;
  assign io_out[3] = net5;
  assign io_out[6] = net5;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  not_cell gate7 (
    .in (net9),
    .out (net5)
  );
  not_cell gate8 (
    .in (net10),
    .out (net9)
  );
  and_cell gate9 (
    .a (net1),
    .b (net2),
    .out (net11)
  );
  and_cell gate10 (
    .a (net3),
    .b (net4),
    .out (net12)
  );
  and_cell gate11 (
    .a (net11),
    .b (net12),
    .out (net10)
  );
endmodule
module user_module_341438392303616596(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7 = io_in[6];
  wire net8 = io_in[7];
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13 = 1'b0;
  wire net14 = 1'b1;
  wire net15 = 1'b1;

  assign io_out[0] = net9;
  assign io_out[1] = net10;
  assign io_out[2] = net11;
  assign io_out[3] = net12;
  assign io_out[4] = net5;
  assign io_out[5] = net6;
  assign io_out[6] = net7;
  assign io_out[7] = net8;

  not_cell not1 (
    .in (net1),
    .out (net9)
  );
  not_cell not2 (
    .in (net2),
    .out (net10)
  );
  not_cell not3 (
    .in (net3),
    .out (net11)
  );
  not_cell not4 (
    .in (net4),
    .out (net12)
  );
  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
endmodule
module user_module_341160201697624660(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7;
  wire net8;
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13;
  wire net14;
  wire net15 = 1'b1;
  wire net16 = 1'b1;
  wire net17;
  wire net18;
  wire net19;
  wire net20;
  wire net21;
  wire net22;
  wire net23;
  wire net24;
  wire net25;
  wire net26;
  wire net27;
  wire net28;
  wire net29;
  wire net30;
  wire net31;
  wire net32;
  wire net33;
  wire net34;
  wire net35 = 1'b0;
  wire net36 = 1'b0;

  assign io_out[0] = net7;
  assign io_out[1] = net8;
  assign io_out[2] = net9;
  assign io_out[3] = net10;
  assign io_out[4] = net11;
  assign io_out[5] = net12;
  assign io_out[6] = net13;
  assign io_out[7] = net14;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  dff_cell flipflop2 (
    .d (net17),
    .clk (net18),
    .q (net19),
    .notq (net17)
  );
  dff_cell flipflop3 (
    .d (net20),
    .clk (net19),
    .q (net21),
    .notq (net20)
  );
  dff_cell flipflop4 (
    .d (net22),
    .clk (net21),
    .q (net23),
    .notq (net22)
  );
  dff_cell flipflop5 (
    .d (net24),
    .clk (net23),
    .q (net25),
    .notq (net24)
  );
  mux_cell mux2 (
    .a (net1),
    .b (net2),
    .sel (net5),
    .out (net18)
  );
  mux_cell mux3 (
    .a (net3),
    .b (net4),
    .sel (net6),
    .out (net26)
  );
  dff_cell flipflop6 (
    .d (net27),
    .clk (net26),
    .q (net28),
    .notq (net27)
  );
  dff_cell flipflop7 (
    .d (net29),
    .clk (net28),
    .q (net30),
    .notq (net29)
  );
  dff_cell flipflop8 (
    .d (net31),
    .clk (net30),
    .q (net32),
    .notq (net31)
  );
  dff_cell flipflop9 (
    .d (net33),
    .clk (net32),
    .q (net34),
    .notq (net33)
  );
  buffer_cell gate7 (
    .in (net19),
    .out (net7)
  );
  buffer_cell gate9 (
    .in (net21),
    .out (net8)
  );
  buffer_cell gate10 (
    .in (net23),
    .out (net9)
  );
  buffer_cell gate11 (
    .in (net25),
    .out (net10)
  );
  buffer_cell gate12 (
    .in (net28),
    .out (net11)
  );
  buffer_cell gate13 (
    .in (net30),
    .out (net12)
  );
  buffer_cell gate14 (
    .in (net32),
    .out (net13)
  );
  buffer_cell gate15 (
    .in (net34),
    .out (net14)
  );
endmodule
module user_module_341136771628663380(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7 = io_in[6];
  wire net8 = io_in[7];
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13;
  wire net14;
  wire net15;
  wire net16;
  wire net17 = 1'b0;
  wire net18 = 1'b1;
  wire net19;
  wire net20;
  wire net21;
  wire net22;
  wire net23;
  wire net24 = 1'b0;
  wire net25;
  wire net26;

  assign io_out[0] = net9;
  assign io_out[1] = net10;
  assign io_out[2] = net11;
  assign io_out[3] = net12;
  assign io_out[4] = net13;
  assign io_out[5] = net14;
  assign io_out[6] = net15;
  assign io_out[7] = net16;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (
    .a (net6),
    .b (net5),
    .sel (net7),
    .out (net19)
  );
  dff_cell flipflop1 (

  );
  mux_cell mux2 (
    .a (net5),
    .b (net4),
    .sel (net7),
    .out (net20)
  );
  mux_cell mux3 (
    .a (net4),
    .b (net3),
    .sel (net7),
    .out (net21)
  );
  mux_cell mux4 (
    .a (net3),
    .b (net2),
    .sel (net7),
    .out (net22)
  );
  mux_cell mux5 (
    .a (net2),
    .b (net1),
    .sel (net7),
    .out (net23)
  );
  mux_cell mux6 (
    .a (net1),
    .b (net24),
    .sel (net7),
    .out (net25)
  );
  mux_cell mux7 (
    .a (net24),
    .b (net6),
    .sel (net7),
    .out (net26)
  );
  mux_cell mux8 (
    .a (net19),
    .b (net21),
    .sel (net8),
    .out (net14)
  );
  mux_cell mux9 (
    .a (net20),
    .b (net22),
    .sel (net8),
    .out (net13)
  );
  mux_cell mux10 (
    .a (net21),
    .b (net23),
    .sel (net8),
    .out (net12)
  );
  mux_cell mux11 (
    .a (net22),
    .b (net25),
    .sel (net8),
    .out (net11)
  );
  mux_cell mux12 (
    .a (net23),
    .b (net24),
    .sel (net8),
    .out (net10)
  );
  mux_cell mux13 (
    .a (net25),
    .b (net24),
    .sel (net8),
    .out (net9)
  );
  mux_cell mux14 (
    .a (net26),
    .b (net20),
    .sel (net8),
    .out (net15)
  );
  mux_cell mux15 (
    .a (net24),
    .b (net19),
    .sel (net8),
    .out (net16)
  );
endmodule
module user_module_341154068332282450(
  input [7:0] io_in, 
  output [7:0] io_out
);

  wire pdm_out;

  assign io_out[0] = pdm_out;
  assign io_out[1] = ~pdm_out;

  pdm_341154068332282450 pdm_core(
    .pdm_input(io_in[7:3]),
    .write_en(io_in[2]),
    .reset(io_in[1]),
    .clk(io_in[0]),    
    .pdm_out(pdm_out)
  );

endmodule
module pdm_341154068332282450(
    input [4:0] pdm_input,
    input       write_en,
    input       clk, reset,    
    output      pdm_out
);

reg [4:0] accumulator;
reg [4:0] input_reg;

wire [5:0] sum;

assign sum = input_reg + accumulator;
assign pdm_out = sum[5];

always @(posedge clk or posedge reset) begin
    if (reset) begin 
        input_reg <= 5'h00 ;
        accumulator <= 5'h00;
    end else begin
        accumulator <= sum[4:0];
        if (write_en) input_reg <= pdm_input ;
    end
end

endmodule
module user_module_341193419111006803(
  input [7:0] io_in,
  output [7:0] io_out
);

   // State
   reg [1:0]   code[7:0];
   reg [3:0]   data[7:0];
   reg [2:0]   pc;
   reg [3:0]   acc;

   wire [2:0]  npc = pc + 1;

   assign io_out = {1'd0, pc, acc};
   wire [3:0]  cmdarg = io_in[7:4];
   wire [3:0]  arg = data[pc];

   always @(posedge io_in[0])
      case (io_in[2:1])
        `Reset: begin
           $display("        Reset");
           pc <= cmdarg[2:0];
           acc <= 0;
        end
        `LoadCode: begin
           $display("        LoadCode %d: Insn %d", pc, cmdarg);
           code[pc] <= cmdarg;
           pc <= npc;
        end
        `LoadData: begin
           $display("        LoadData %d: Data %d", pc, cmdarg);
           data[pc] <= cmdarg;
           pc <= npc;
        end
        `Run: begin
           $display("        Running %d (insn %d, %d)", pc, code[pc], data[pc]);
           case (code[pc])
             `Load: begin acc <= arg; pc = npc; end
             `Store: begin data[arg[2:0]] <= acc; pc <= npc; end
             `Add: begin acc <= acc + arg; pc <= npc; end
             `Bz: begin pc <= acc == 0 ? arg : npc; end
           endcase
           end
      endcase
endmodule
module user_module_341624400621077076(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = 1'b0;
  wire net2;
  wire net3;
  wire net4;
  wire net5 = 1'b1;
  wire net6;
  wire net7 = 1'b1;
  wire net8;
  wire net9;

  assign io_out[0] = net1;
  assign io_out[1] = net2;
  assign io_out[2] = net3;
  assign io_out[3] = net4;
  assign io_out[4] = net3;
  assign io_out[5] = net5;
  assign io_out[6] = net5;
  assign io_out[7] = net6;

  and_cell gate1 (
    .a (net4),
    .b (net2),
    .out (net8)
  );
  dff_cell flipflop1 (
    .d (net6),
    .clk (net9),
    .q (net3),
    .notq (net4)
  );
  dff_cell flipflop2 (
    .d (net8),
    .clk (net9),
    .q (net6),
    .notq (net2)
  );
endmodule
module user_module_341419328215712339(
	input [7:0] io_in, 
	output [7:0] io_out
);
	wire clk25 = io_in[0];
	wire rst = io_in[1];

	wire sw_switch = io_in[7];

	// for funny
	wire [2:0]sw1 = io_in[4:2];

	// for counter
	wire [1:0]sw_outctrl = io_in[5:4];
	wire sw_pause = io_in[6];
	wire signal1 = io_in[2];
	wire signal2 = io_in[3];
	reg sig1r;
	reg sig2r;
	reg sig1rr;
	reg sig2rr;

	reg [13:0]cnt = 0;
	reg [13:0]cnt2 = 0;
	always @ (posedge clk25) begin
		sig1r <= signal1;
		sig2r <= signal2;
		sig1rr <= sig1r;
		sig2rr <= sig2r;
		if (sw_switch) begin
			if (rst) begin
				cnt <= 0;
				cnt2 <= 0;
			end else begin
				if (!sw_pause) begin
					if (sig1r != sig1rr) cnt <= cnt + 1;
					if (sig2r != sig2rr) cnt2 <= cnt2 + 1;
				end
			end
		end else begin
			cnt <= cnt + 1;
		end
	end
	wire clkslow = cnt[3 + sw1];
	reg [6:0]cntslow = 0;
	reg [2:0]cntf = 0;
	always @ (posedge clkslow) begin
		cntslow <= cntslow == 105 ? 0 : cntslow + 1;
		if (!cntslow[0]) begin
			if (cntslow >= 73) begin
				cntf <= cntf == 4 ? 0 : cntf + 1;
			end else
				cntf <= 0;
		end
	end
	reg	[2:0]finalpos;
	always @ (*) begin
		finalpos = 0;
		case (cntf)
			0: finalpos = 2;
			1: finalpos = 6;
			2: finalpos = 0;
			3: finalpos = 3;
			4: finalpos = 5;
		endcase
	end
	reg [7:0]io_out_funny;
	reg [7:0]io_out_cnter;
	always @ (*) begin
		io_out_funny = 0;
		if (cntslow >= 1 && cntslow <= 8) io_out_funny = 8'b11111111 << (8 - cntslow);
		else if (cntslow >= 9 && cntslow <= 17) io_out_funny = 8'b11111111 << (cntslow - 9);
		else if (cntslow >= 18 && cntslow <= 25) io_out_funny = 8'b10000000 >> (cntslow - 18);
		else if (cntslow >= 26 && cntslow <= 33) io_out_funny = 8'b00000001 << (cntslow - 26);
		else if (cntslow >= 35 && cntslow <= 55) io_out_funny = cntslow[0] ? 8'b00000000 : 8'b11111111;
		else if (cntslow >= 56 && cntslow <= 72) io_out_funny = cntslow[0] ? 8'b11110000 : 8'b00001111;
		else if (cntslow >= 73 && cntslow[0] == 0) io_out_funny = 8'b10000000 >> finalpos;

		io_out_cnter = 0;
		case (sw_outctrl)
			2'b00: io_out_cnter = cnt[7:0];
			2'b01: io_out_cnter = {2'b0, cnt[13:8]};
			2'b10: io_out_cnter = cnt2[7:0];
			2'b11: io_out_cnter = {2'b0, cnt2[13:8]};
		endcase
	end
	assign io_out = sw_switch ? io_out_cnter : io_out_funny;
endmodule
module user_module_341337976625693266(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7 = io_in[6];
  wire net8 = io_in[7];
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13;
  wire net14 = 1'b0;
  wire net15 = 1'b1;
  wire net16 = 1'b1;
  wire net17;
  wire net18;
  wire net19;
  wire net20;
  wire net21;
  wire net22;
  wire net23;
  wire net24;
  wire net25;
  wire net26;
  wire net27;
  wire net28;

  assign io_out[0] = net9;
  assign io_out[1] = net10;
  assign io_out[2] = net11;
  assign io_out[3] = net12;
  assign io_out[4] = net13;

  and_cell gate1 (
    .a (net1),
    .b (net5),
    .out (net17)
  );
  or_cell gate2 (

  );
  xor_cell gate3 (
    .a (net2),
    .b (net6),
    .out (net18)
  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (
    .a (net19),
    .b (net20),
    .sel (net17),
    .out (net21)
  );
  dff_cell flipflop1 (

  );
  xor_cell gate7 (
    .a (net1),
    .b (net5),
    .out (net9)
  );
  xor_cell gate8 (
    .a (net17),
    .b (net18),
    .out (net10)
  );
  xor_cell gate9 (

  );
  and_cell gate10 (

  );
  mux_cell mux2 (

  );
  and_cell gate11 (
    .a (net2),
    .b (net6),
    .out (net19)
  );
  or_cell gate12 (

  );
  or_cell gate13 (
    .a (net2),
    .b (net6),
    .out (net20)
  );
  xor_cell gate14 (
    .a (net3),
    .b (net7),
    .out (net22)
  );
  mux_cell mux3 (
    .a (net23),
    .b (net24),
    .sel (net21),
    .out (net25)
  );
  xor_cell gate15 (
    .a (net21),
    .b (net22),
    .out (net11)
  );
  and_cell gate16 (
    .a (net3),
    .b (net7),
    .out (net23)
  );
  or_cell gate17 (

  );
  or_cell gate18 (
    .a (net3),
    .b (net7),
    .out (net24)
  );
  xor_cell gate19 (
    .a (net4),
    .b (net8),
    .out (net26)
  );
  mux_cell mux4 (
    .a (net27),
    .b (net28),
    .sel (net25),
    .out (net13)
  );
  xor_cell gate20 (
    .a (net25),
    .b (net26),
    .out (net12)
  );
  and_cell gate21 (
    .a (net4),
    .b (net8),
    .out (net27)
  );
  or_cell gate22 (
    .a (net4),
    .b (net8),
    .out (net28)
  );
endmodule
module user_module_341364381657858642(
  input [7:0] io_in,
  output [7:0] io_out
);

mcpu6bit mcpu6bit_top (
  .clk(io_in[0]),
  .rst(io_in[1]),
  .datain(io_in[7:2]),

  .we(io_out[1]),
  .dataout(io_out[7:2])
);

endmodule
module mcpu6bit(datain,dataout,we,rst,clk);

input [5:0] datain;
output [5:0] dataout;
output we;
input rst;
input clk;

reg [6:0] accumulator; // accumulator(6) is carry !
reg [3:0] adreg;
reg [3:0] pc;
reg [2:0] states;

initial begin
end

	always @(posedge clk)
		if (~rst) begin
			adreg 	  <= 0;
			states	  <= 0;
			accumulator <= 0;	
			pc <= 0;
		end
		else begin
			// PC / Address path
			if (~|states) begin
				pc	 <= adreg + 1'b1;
				adreg <= datain[3:0];  // was adreg <=pc, aw fix.
			end
			else adreg <= pc;
		
			// ALU / Data Path
			case(states)
				3'b010 : accumulator 	 <= {1'b0, accumulator[5:0]} + {1'b0, datain}; // add
				3'b011 : accumulator[5:0] <= ~(accumulator[5:0]|datain); // nor
				3'b101 : accumulator[6]   <= 1'b0; // branch not taken, clear carry					   
			endcase							// default:  instruction fetch, jcc taken

			// State machine
			if (|states) states <= 0;
			else begin 
				if ( &datain[5:4] && accumulator[6] ) states <= 3'b101;
				else states <= {1'b0, ~datain[5:4]};
			end
		end

assign dataout   = clk ?  {1'b00,adreg} : accumulator[5:0]; 
assign we     =  ~rst | (states!=3'b001) ; 

endmodule
module user_module_341160271679586899(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3;
  wire net4;
  wire net5;
  wire net6;
  wire net7;
  wire net8;
  wire net9;
  wire net10;
  wire net11 = 1'b1;
  wire net12 = 1'b1;
  wire net13 = 1'b0;
  wire net14 = 1'b0;
  wire net15 = 1'b0;
  wire net16 = 1'b0;
  wire net17 = 1'b0;
  wire net18 = 1'b0;
  wire net19 = 1'b0;
  wire net20 = 1'b0;
  wire net21;
  wire net22;
  wire net23;

  assign io_out[0] = net3;
  assign io_out[1] = net4;
  assign io_out[2] = net5;
  assign io_out[3] = net6;
  assign io_out[4] = net7;
  assign io_out[5] = net8;
  assign io_out[6] = net9;
  assign io_out[7] = net10;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  xor_cell gate7 (
    .a (net10),
    .b (net2),
    .out (net21)
  );
  dff_cell flipflop2 (
    .d (net21),
    .clk (net1),
    .q (net3)
  );
  dff_cell flipflop3 (
    .d (net3),
    .clk (net1),
    .q (net4)
  );
  dff_cell flipflop4 (
    .d (net4),
    .clk (net1),
    .q (net5)
  );
  dff_cell flipflop5 (
    .d (net5),
    .clk (net1),
    .q (net6)
  );
  xor_cell gate8 (
    .a (net21),
    .b (net6),
    .out (net22)
  );
  dff_cell flipflop6 (
    .d (net22),
    .clk (net1),
    .q (net7)
  );
  xor_cell gate9 (
    .a (net21),
    .b (net7),
    .out (net23)
  );
  dff_cell flipflop7 (
    .d (net23),
    .clk (net1),
    .q (net8)
  );
  dff_cell flipflop8 (
    .d (net8),
    .clk (net1),
    .q (net9)
  );
  dff_cell flipflop9 (
    .d (net9),
    .clk (net1),
    .q (net10)
  );
endmodule
module user_module_341631485498884690(
  input [7:0] io_in,
  output [7:0] io_out
);

TrainLED LED1 (
    .clk(io_in[0]),
    .rst(io_in[1]),
    .din(io_in[2]),
    .dout(io_out[0]),
    .led1(io_out[1]),
    .led2(io_out[2]),
    .led3(io_out[3])
    );

endmodule
module TrainLED(clk,rst,din,dout,led1,led2,led3);

input clk,rst,din;
output dout;
output led1,led2,led3;

reg [3:0] finecount;
reg outdff;
reg [11:00] shiftregister;
reg [11:00] shiftlatch;
reg [3:0] bitcount;
reg [7:0] resetcount;
reg [3:0] pwmcounter;
reg [1:0] mode;  // 0=receive, 1=forward, 2=reset

PWMEngine PWM1 (.clk(clk),.rst(rst),.counter(pwmcounter),.PW_in(shiftlatch[3:0]),.led(led1));
PWMEngine PWM2 (.clk(clk),.rst(rst),.counter(pwmcounter),.PW_in(shiftlatch[7:4]),.led(led2));
PWMEngine PWM3 (.clk(clk),.rst(rst),.counter(pwmcounter),.PW_in(shiftlatch[11:8]),.led(led3));

    always @(posedge clk)
        if (rst) begin
            finecount <= 0;
            outdff <= 0;
            shiftregister <= 0;
            bitcount <= 0;
            mode <= 0;
            pwmcounter <=0;
            resetcount <=0;
        end
        else begin
            // PWM mastercounter
            pwmcounter <= pwmcounter + 1'b1;

            // data recovery
            if ((finecount < 4'b1011) && (finecount >= 4'b0010))
                    finecount <= finecount + 1'b1;
            else 
                if (din && (finecount < 4'b0010))
                    finecount <= finecount + 1'b1;
                else
                    if (~din)
                        finecount <= 0;

            // state machine
            if (mode == 2'b00) begin          
                // handle data store (mode=0, receive)
                if (finecount == 4'b0110) begin
                    shiftregister <= {shiftregister[10:0], din};
                    bitcount <= bitcount + 1'b1;
                    if (bitcount == 4'b1011)
                        mode <= 2'b01;        
                end
                outdff <= 1'b0;
            end
            else // mode reset
                if ((mode == 2'b10) && (finecount == 4'b0010)) begin
                    mode <= 2'b00;
                    bitcount <= 4'b0000;
                end 
                else begin    
                    // handle data out (forward)        
                    case(finecount)
                        4'b0010: outdff <= 1'b1; 
                        4'b0110: outdff <= din;
                        4'b1010: outdff <= 1'b0;
                    endcase;
                    end

            // Handle reset. 
            // Resetcounter is increased while no bits arrive
            if (finecount <= 4'b0010) begin
                resetcount <= resetcount + 1'b1;
                if (resetcount == 8'd96) begin  // reset after 8 bit times
                    mode <= 2'b10;
                end
            end 
            else 
                resetcount <= 0;
        end

    // Handle PWMlatch
    always@(*)
        if (clk && (pwmcounter == 4'b1111) && (bitcount == 4'b1100) && (mode == 2'b10) ) begin
            shiftlatch <= shiftregister;
        end 

assign dout = outdff;

endmodule
module PWMEngine(clk,rst,PW_in,counter,led);

input [3:0] PW_in;   // 
input [3:0] counter;   // 
input clk;
input rst;
output led;

reg LEDdff;

	always @(posedge clk)
		if (rst) begin
            LEDdff <= 0;
		end
		else begin

            if (counter == PW_in)
                LEDdff <= 1'b0;
            else if (counter == 0)
                LEDdff <= 1'b1;
        end

assign led = LEDdff;

endmodule
module user_module_341235973870322258(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3;
  wire net4;
  wire net5;
  wire net6;
  wire net7;
  wire net8;
  wire net9;
  wire net10 = 1'b0;
  wire net11 = 1'b1;
  wire net12 = 1'b1;
  wire net13;
  wire net14;

  assign io_out[0] = net3;
  assign io_out[1] = net4;
  assign io_out[2] = net5;
  assign io_out[3] = net6;
  assign io_out[4] = net7;
  assign io_out[5] = net8;
  assign io_out[6] = net9;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (
    .a (net9),
    .b (net12),
    .sel (net2),
    .out (net13)
  );
  dff_cell flipflop1 (

  );
  dff_cell flipflop2 (
    .d (net13),
    .clk (net1),
    .q (net3)
  );
  dff_cell flipflop3 (
    .d (net3),
    .clk (net1),
    .q (net4)
  );
  dff_cell flipflop4 (
    .d (net4),
    .clk (net1),
    .q (net5)
  );
  dff_cell flipflop5 (
    .d (net5),
    .clk (net1),
    .q (net6),
    .notq (net14)
  );
  dff_cell flipflop6 (
    .d (net14),
    .clk (net1),
    .q (net7)
  );
  dff_cell flipflop7 (
    .d (net7),
    .clk (net1),
    .q (net8)
  );
  dff_cell flipflop8 (
    .d (net8),
    .clk (net1),
    .q (net9)
  );
endmodule
module user_module_341353928049295956(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2;
  wire net3;
  wire net4;
  wire net5;
  wire net6;
  wire net7;
  wire net8;
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13;
  wire net14;
  wire net15;
  wire net16;
  wire net17;
  wire net18 = 1'b0;
  wire net19;
  wire net20;
  wire net21;
  wire net22;
  wire net23;
  wire net24;
  wire net25;
  wire net26;
  wire net27;
  wire net28;
  wire net29;
  wire net30;
  wire net31;
  wire net32;
  wire net33;
  wire net34;
  wire net35;
  wire net36;
  wire net37;
  wire net38;
  wire net39;
  wire net40;
  wire net41;

  assign io_out[0] = net2;
  assign io_out[1] = net3;
  assign io_out[2] = net4;
  assign io_out[3] = net5;
  assign io_out[4] = net6;
  assign io_out[5] = net7;
  assign io_out[6] = net8;
  assign io_out[7] = net9;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  dff_cell flipflop1 (
    .d (net10),
    .clk (net11),
    .q (net12),
    .notq (net10)
  );
  dff_cell flipflop2 (
    .d (net13),
    .clk (net12),
    .q (net14),
    .notq (net13)
  );
  dff_cell flipflop3 (
    .d (net15),
    .clk (net16),
    .q (net17),
    .notq (net15)
  );
  dff_cell flipflop4 (
    .d (net19),
    .clk (net20),
    .q (net21),
    .notq (net19)
  );
  dff_cell flipflop5 (
    .d (net22),
    .clk (net23),
    .q (net16),
    .notq (net22)
  );
  dff_cell flipflop6 (
    .d (net24),
    .clk (net25),
    .q (net23),
    .notq (net24)
  );
  dff_cell flipflop7 (
    .d (net26),
    .clk (net27),
    .q (net25),
    .notq (net26)
  );
  dff_cell flipflop8 (
    .d (net28),
    .clk (net14),
    .q (net29),
    .notq (net28)
  );
  dff_cell flipflop9 (
    .d (net30),
    .clk (net29),
    .q (net27),
    .notq (net30)
  );
  dff_cell flipflop10 (
    .d (net31),
    .clk (net21),
    .q (net32),
    .notq (net31)
  );
  dff_cell flipflop11 (
    .d (net33),
    .clk (net17),
    .q (net34),
    .notq (net33)
  );
  dff_cell flipflop12 (
    .d (net35),
    .clk (net34),
    .q (net36),
    .notq (net35)
  );
  dff_cell flipflop13 (
    .d (net37),
    .clk (net38),
    .q (net20),
    .notq (net37)
  );
  dff_cell flipflop14 (
    .d (net39),
    .clk (net36),
    .q (net40),
    .notq (net39)
  );
  dff_cell flipflop15 (
    .d (net41),
    .clk (net40),
    .q (net38),
    .notq (net41)
  );
  buffer_cell gate10 (
    .in (net1),
    .out (net11)
  );
  buffer_cell gate11 (
    .in (net32),
    .out (net9)
  );
  buffer_cell gate12 (
    .in (net23),
    .out (net6)
  );
  buffer_cell gate13 (
    .in (net29),
    .out (net3)
  );
  buffer_cell gate14 (
    .in (net14),
    .out (net2)
  );
  buffer_cell gate15 (
    .in (net27),
    .out (net4)
  );
  buffer_cell gate16 (
    .in (net25),
    .out (net5)
  );
  buffer_cell gate7 (
    .in (net16),
    .out (net7)
  );
  buffer_cell gate8 (
    .in (net17),
    .out (net8)
  );
endmodule
module user_module_341155178824598098(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7;
  wire net8;
  wire net9;
  wire net10 = 1'b0;
  wire net11 = 1'b1;
  wire net12 = 1'b1;
  wire net13;
  wire net14;
  wire net15;
  wire net16;
  wire net17;
  wire net18;
  wire net19;
  wire net20;
  wire net21;
  wire net22;
  wire net23;
  wire net24;
  wire net25;
  wire net26;
  wire net27;
  wire net28;
  wire net29;
  wire net30;
  wire net31;

  assign io_out[0] = net7;
  assign io_out[1] = net8;
  assign io_out[2] = net9;

  xor_cell gate3 (
    .a (net13),
    .b (net14),
    .out (net15)
  );
  and_cell gate100 (
    .a (net16),
    .b (net17),
    .out (net18)
  );
  mux_cell mux1 (
    .a (net15),
    .b (net2),
    .sel (net3),
    .out (net19)
  );
  dff_cell flipflop1 (
    .d (net19),
    .clk (net1),
    .q (net20)
  );
  xor_cell gate7 (
    .a (net16),
    .b (net17),
    .out (net21)
  );
  or_cell gate9 (
    .a (net22),
    .b (net18),
    .out (net23)
  );
  dff_cell flipflop2 (
    .d (net20),
    .clk (net1),
    .q (net24)
  );
  dff_cell flipflop3 (
    .d (net24),
    .clk (net1),
    .q (net13)
  );
  dff_cell flipflop4 (
    .d (net13),
    .clk (net1),
    .q (net25)
  );
  dff_cell flipflop5 (
    .d (net25),
    .clk (net1),
    .q (net26)
  );
  dff_cell flipflop6 (
    .d (net26),
    .clk (net1),
    .q (net27)
  );
  dff_cell flipflop7 (
    .d (net27),
    .clk (net1),
    .q (net28)
  );
  dff_cell flipflop8 (
    .d (net28),
    .clk (net1),
    .q (net7)
  );
  xor_cell gate10 (
    .a (net26),
    .b (net29),
    .out (net14)
  );
  xor_cell gate11 (
    .a (net27),
    .b (net7),
    .out (net29)
  );
  dff_cell flipflop9 (
    .d (net4),
    .clk (net1),
    .q (net16)
  );
  dff_cell flipflop10 (
    .d (net5),
    .clk (net1),
    .q (net17)
  );
  dff_cell flipflop11 (
    .d (net6),
    .clk (net1),
    .q (net30)
  );
  dff_cell flipflop12 (
    .d (net23),
    .clk (net1),
    .q (net9)
  );
  dff_cell flipflop13 (
    .d (net31),
    .clk (net1),
    .q (net8)
  );
  xor_cell gate1 (
    .a (net21),
    .b (net30),
    .out (net31)
  );
  and_cell gate2 (
    .a (net21),
    .b (net30),
    .out (net22)
  );
endmodule
module user_module_341176884318437971(
    input  wire [7:0] io_in,
    output wire [7:0] io_out
);
/*
 * Local signals
 */
    // Used as a clock.
    wire clk;

    // Used as a synchronous reset.
    wire rst;

    // Indicates that the first nibble is registered.
    reg int_nibble_stored;

    // The registered first nibble.
    reg [3:0] int_first_nibble;

    // The resistered output.
    reg [7:0] int_out;

    // The multiplied 8-bit output.
    wire [7:0] int_mult_result;
/*
 * Logic
 */
    // Using io_in[0] as clk.
    assign clk = io_in[0];

    // Using io_in[1] as rst.
    assign rst = io_in[1];

    // Assign the 
    assign io_out = int_out;

    always @(posedge clk) begin
        if (rst) begin
            int_nibble_stored <= 1'b0;
            int_first_nibble  <= 4'd0;
            int_out           <= 8'd0;
        end else begin
            // If we havent latched in the first nibble,
            // then do so first.
            if (!int_nibble_stored) begin
                int_first_nibble  <= io_in[7:4];
                int_nibble_stored <= 1'b1;
            end else begin
                // Register the multiplier result.
                int_out <= int_mult_result;

                // Reset the nibble registered flag.
                int_nibble_stored <= 1'b0;

                // Reset the nibble data.
                int_first_nibble <= 4'd0;
            end
        end
    end

/*
 * Instances
 */
    Mult_Wallace4 inst_mul (
        .a(int_first_nibble),
        .b(io_in[7:4]),
        .o(int_mult_result)
    );
endmodule
module Mult_Wallace4 # (
    parameter N = 4
)(
    input  wire [N-1:0] a,
    input  wire [N-1:0] b,
    output wire [2*N-1:0] o
);

    wire [N-1:0] ppts[N-1:0];

	assign ppts[0][0] = a[0] & b[0];
	assign ppts[0][1] = a[0] & b[1];
	assign ppts[0][2] = a[0] & b[2];
	assign ppts[0][3] = a[0] & b[3];
	assign ppts[1][0] = a[1] & b[0];
	assign ppts[1][1] = a[1] & b[1];
	assign ppts[1][2] = a[1] & b[2];
	assign ppts[1][3] = a[1] & b[3];
	assign ppts[2][0] = a[2] & b[0];
	assign ppts[2][1] = a[2] & b[1];
	assign ppts[2][2] = a[2] & b[2];
	assign ppts[2][3] = a[2] & b[3];
	assign ppts[3][0] = a[3] & b[0];
	assign ppts[3][1] = a[3] & b[1];
	assign ppts[3][2] = a[3] & b[2];
	assign ppts[3][3] = a[3] & b[3];

	wire [11:0] s;
	wire [11:0] cout;

	ha HA1 (.a(ppts[0][1]), .b(ppts[1][0]), .s(s[0]), .cout(cout[0]));
	fa FA2 (.a(ppts[0][2]), .b(ppts[1][1]), .cin(ppts[2][0]), .s(s[1]), .cout(cout[1]));
	fa FA3 (.a(ppts[0][3]), .b(ppts[1][2]), .cin(ppts[2][1]), .s(s[2]), .cout(cout[2]));
	ha HA4 (.a(ppts[1][3]), .b(ppts[2][2]), .s(s[3]), .cout(cout[3]));
	ha HA5 (.a(cout[0]), .b(s[1]), .s(s[4]), .cout(cout[4]));
	fa FA6 (.a(ppts[3][0]), .b(cout[1]), .cin(s[2]), .s(s[5]), .cout(cout[5]));
	fa FA7 (.a(ppts[3][1]), .b(cout[2]), .cin(s[3]), .s(s[6]), .cout(cout[6]));
	fa FA8 (.a(ppts[2][3]), .b(ppts[3][2]), .cin(cout[3]), .s(s[7]), .cout(cout[7]));
	ha HA9 (.a(cout[4]), .b(s[5]), .s(s[8]), .cout(cout[8]));
	fa FA10 (.a(cout[5]), .b(s[6]), .cin(cout[8]), .s(s[9]), .cout(cout[9]));
	fa FA11 (.a(cout[6]), .b(s[7]), .cin(cout[9]), .s(s[10]), .cout(cout[10]));
	fa FA12 (.a(ppts[3][3]), .b(cout[7]), .cin(cout[10]), .s(s[11]), .cout(cout[11]));

	assign o[7] = cout[11];
	assign o[6] = s[11];
	assign o[5] = s[10];
	assign o[4] = s[9];
	assign o[3] = s[8];
	assign o[2] = s[4];
	assign o[1] = s[0];
	assign o[0] = ppts[0][0];
endmodule
module fa (
    input  wire a,
    input  wire b,
    input  wire cin,
    output wire s,
    output wire cout
);

/*
 * Local signals
 */
    // wire int_a_xor_b;
    // wire int_a_and_b;
    // wire int_a_xor_b_and_cin;
/*
 * Logic
 */
 
    // Implement a full adder with individual gates.
    // assign int_a_xor_b         = a ^ b;
    // assign int_a_and_b         = a & b;
    // assign int_a_xor_b_and_cin = int_a_xor_b & cin;
    // assign s                   = int_a_xor_b ^ cin;
    // assign cout                = int_a_xor_b_and_cin | int_a_and_b;

    // Instantiate a full adder cell from the
    // standard cell library.
    // sky130_fd_sc_hd__fah inst_fa (
    //     .A   (a),
    //     .B   (b),
    //     .CI  (cin),
    //     .SUM (s),
    //     .COUT(cout)
    // );

    // Infer a full adder.
    assign {cout, s} = a + b + cin;
endmodule
module ha (
    input  wire a,
    input  wire b,
    output wire s,
    output wire cout
);

/*
 * Logic
 */

    // Implement a half adder with individual gates.
    // assign s    = a ^ b;
    // assign cout = a & b;

    // Instantiate a half adder cell from the
    // standard cell library.
    // sky130_fd_sc_hd__ha inst_ha (
    //     .A   (a),
    //     .B   (b),
    //     .SUM (s),
    //     .COUT(cout)
    // );

    // Infer a half adder.
    assign {cout, s} = a + b;
endmodule
module csa #(
    parameter NUM_BITS = 4
) (
    input  wire [NUM_BITS-1:0] a, // Input A
    input  wire [NUM_BITS-1:0] b, // Input B
    input  wire [NUM_BITS-1:0] c, // Input C
    output wire [NUM_BITS-1:0] p, // Output p (propagate)
    output wire [NUM_BITS-1:0] g  // Output g (generate)
);
    genvar i;

    generate
        for (i = 0; i < NUM_BITS; i = i + 1) begin
            fa fa_i (
                .a   (a[i]),
                .b   (b[i]),
                .cin (c[i]),
                .s   (p[i]),
                .cout(g[i])
            );
        end
    endgenerate
endmodule
module rca #(
    parameter NUM_BITS = 4
) (
    input  wire [NUM_BITS-1:0] a,
    input  wire [NUM_BITS-1:0] b,
    output wire [NUM_BITS-1:0] s,
    output wire                cout
);

/*
 * Local signals
 */
    // The carry out to carry in signals.
    wire [NUM_BITS:0] int_carry;

/*
 * Logic
 */
    genvar i;

    generate
        for (i = 0; i < NUM_BITS; i = i + 1) begin
            if (i == 0) begin
                // The first bits have no carry in,
                // so just generate a half adder.
                ha ha_0 (
                    .a   (a[i]),
                    .b   (b[i]),
                    .s   (s[i]),
                    .cout(int_carry[i])
                );
            end else begin
                fa fa_i (
                    .a   (a[i]),
                    .b   (b[i]),
                    .cin (int_carry[i-1]),
                    .s   (s[i]),
                    .cout(int_carry[i])
                );
            end
        end
    endgenerate

    assign cout = int_carry[NUM_BITS-1];
endmodule
module user_module_341444501414347346(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[1];
  wire net2 = io_in[2];
  wire net3 = io_in[3];
  wire net4 = io_in[6];
  wire net5 = io_in[7];
  wire net6;
  wire net7;
  wire net8;
  wire net9;
  wire net10;
  wire net11;
  wire net12 = 1'b1;
  wire net13 = 1'b1;
  wire net14 = 1'b0;
  wire net15;
  wire net16;

  assign io_out[0] = net6;
  assign io_out[1] = net7;
  assign io_out[4] = net8;
  assign io_out[5] = net9;
  assign io_out[6] = net10;
  assign io_out[7] = net11;

  or_cell gate7 (
    .a (net1),
    .b (net3),
    .out (net6)
  );
  or_cell gate8 (
    .a (net2),
    .b (net3),
    .out (net7)
  );
  not_cell gate9 (
    .in (net4),
    .out (net15)
  );
  not_cell gate10 (
    .in (net5),
    .out (net16)
  );
  and_cell gate11 (
    .a (net15),
    .b (net16),
    .out (net8)
  );
  and_cell gate12 (
    .a (net4),
    .b (net16),
    .out (net10)
  );
  and_cell gate13 (
    .a (net5),
    .b (net15),
    .out (net9)
  );
  and_cell gate14 (
    .a (net4),
    .b (net5),
    .out (net11)
  );
endmodule
module latch (GATE, D, Q);
   input  GATE, D;
   output Q;
   reg    Q;
   always @ (GATE or D)
      if (GATE)
         Q <= D;
endmodule
module scan_flop(CLK, D, SCD, SCE, Q);
    input CLK, D, SCD, SCE;
    output Q;
    reg Q;

    always @(posedge CLK)
        Q <= SCE ? SCD : D;
endmodule