dakies/OSS_Verilog huggingface dataset:
module rotary_encoder (
  input wire [7:0] io_in,
  output wire [7:0] io_out
);

    wire clk = io_in[0];
    wire reset = io_in[1];
    wire encA = io_in[2];
    wire encB = io_in[3];
    wire [6:0] led_out;
    assign io_out[6:0] = led_out;
    assign io_out[7] = 0;
    
    reg [7:0] delay_counter;
    reg [3:0] digit;
    reg old_value;

    always @(posedge clk) begin
        // if reset, set counter to 0
        if (reset) begin
            digit <= 0;
            old_value <= encA;
            delay_counter <= 0;
        end else begin
            if (delay_counter != 0) begin
                delay_counter <= delay_counter - 1'b1;
            end
            if (encA == 1 && old_value == 0 && delay_counter == 0) begin
                delay_counter = 125; //IOrefreshrate = 12.5Khz => clock = 6.25KHz => delay 20ms = 125 cycles
                //rising edge on A
                if(encB == 0) begin
                    // increment digit
                    digit <= digit + 1'b1;
    
                    // only count from 0 to 9
                    if (digit == 9) begin
                        digit <= 0;
                    end
                end else begin
                    // decrement digit
                    if (digit == 0) begin
                        digit <= 9;
                    end else begin    
                        digit <= digit - 1'b1;
                    end 
                end             
            end
            old_value = encA;
        end
    end 

    // instantiate segment display
    seg7 seg7(.counter(digit), .segments(led_out));

endmodule
module gregdavill_clock_top(
  input [7:0] io_in, 
  output [7:0] io_out
);

clock clock_top (
    .i_clk(io_in[0]),
    .i_rst(io_in[1]),
    .i_min_up(io_in[2]),
    .i_hour_up(io_in[3]),
    .o_clk(io_out[0]),
    .o_latch(io_out[1]),
    .o_bit(io_out[2])
);

endmodule
module cpldcpu_MCPU5plus(
  input [7:0] io_in,
  output [7:0] io_out
);

MCPU5plus MCPU5plus_top (
  .clk(io_in[0]),
  .rst(io_in[1]),
  .inst_in(io_in[7:2]),
  .cpu_out(io_out[7:0])
);

endmodule
module MCPU5plus(inst_in,cpu_out,rst,clk);

input [5:0] inst_in;
output [7:0] cpu_out;
input rst;
input clk;

localparam OP_BCC  = 2'b00;      //00IIII
localparam OP_STA  = 3'b101;     //101RRR
localparam OP_JMPA = 6'b111010;  //111010

reg [8:0] accu; // accu(6) is carry !
reg [7:0] pc;
reg [7:0] regfile [0:8];
reg iflag;
integer i;

    //handle register file writes (STA)
    always @(*)
        if ((inst_in[5:3] == OP_STA) && ~rst && ~clk)
            regfile[inst_in[2:0]] <= accu;

	always @(posedge clk)
		if (rst) begin
			accu <= 0;	
			pc <= 0;
            iflag <= 0;
		end
		else begin
            // PC
            if ((inst_in[5:4] == OP_BCC) && ~accu[8])            // conditional branch (BCC)            
                pc <= pc + (iflag ? { inst_in[3:0], accu[3:0]}: {{4{inst_in[3]}}, inst_in[3:0]});  
            else
                pc <= pc + 1'b1;
                       
            // ALU path + carry flag
            casex(inst_in)
                6'b00????: accu[8]   <= 1'b0;                                                                     // BCC #imm4
                6'b01????: accu[7:0] <= iflag ? { inst_in[3:0], accu[3:0]}: {{4{inst_in[3]}}, inst_in[3:0]}  ;    // LDI #simm4
                6'b100???: accu[8:0] <= {1'b0,regfile[inst_in[2:0]]} + {1'b0,accu[7:0]};                          // ADD reg8
                6'b101???: ;                                                                                      // STA reg8
                6'b110???: accu[7:0] <= regfile[inst_in[2:0]];                                                    // LDA reg8
                6'b11100?: accu[8:0] <= {~inst_in[0] & accu[8], ~accu[7:0]} + inst_in[0];                         // NEG / NOT
                6'b111010: ;                                                                                      // Free
                6'b111011: ;                                                                                      // OUT
                6'b1111??: ;                                                                                      // Free imm2
            endcase

            // Flags
            casex(inst_in)
                6'b01????: iflag <= 1'b1;           // LDI #simm4
                default:   iflag <= 1'b0;           // all others
            endcase		
        end

    assign cpu_out = clk ? {pc[7:0]} :  accu[7:0] ; 

endmodule
module pwm_gen (
  input [7:0] io_in,
  output [7:0] io_out
);
  
wire clk = io_in[0];
wire reset = io_in[1];
reg counter_state;
reg [5:0] pwm_counter;
reg [6:0] duty;
reg pwm;
assign io_out = {duty, pwm};

  //upcounter which determines pwm period 
always @(posedge clk) begin
    if (reset)
        pwm_counter <= 0;
    else
        pwm_counter <= pwm_counter + 1;
end
  //duty state machine to determine countup or countdown
always @(posedge clk) begin
    if (reset) begin
        counter_state = 0;
    end else begin
            case (counter_state)
                0:
                    if (duty == 8'b111110)
                        counter_state = 1;
                    else
                        counter_state = 0;
                1:
                    if (duty == 8'b000001)
                        counter_state = 0;
                    else
                        counter_state = 1;
            endcase
    end
end
  //generate duty
always @(posedge clk) begin
    if (reset) begin
        duty <= 0;
    end else begin
        if (pwm_counter == 6'b000000) begin
            if (counter_state == 0) begin
                duty <= duty + 1;
            end else if(counter_state == 1) begin
                duty <= duty - 1;
            end
        end
    end
end
  //generate pwm where duty determines it's duty cycle
always @(posedge clk) begin
    if(reset) begin
        pwm <= 0;
    end else begin
        if (pwm_counter == 6'b000000) begin
            pwm <= 1;
        end else if (pwm_counter == duty[6:0]) begin
            pwm <= 0;
        end
    end
end

endmodule
module yubex_egg_timer (
    input [7:0] io_in,
    output reg [7:0] io_out
    );
  
 wire clk;
 localparam clk_frequency = 14'd10000; // frequency in Hz
 wire rst;
 wire start;
  
  
 assign clk = io_in[0];
 assign rst = io_in[1];
 assign start = io_in[2];
 
 reg [1:0] state;
 localparam idle    = 2'b00;
 localparam waiting = 2'b01;
 localparam alarm   = 2'b10;
 
  reg [13:0] clk_cycle_cnt;
  reg [5:0]  second_cnt;
  reg [4:0]  minute_cnt;
  
  always @(posedge clk or posedge rst)
  begin
	if(rst) begin
        	state <= idle;
    	    end 
    else begin
        case(state)
            idle: 
                begin
                if (start == 1'b1)
                    state <= waiting;
                else
                    state <= idle;
                end
            waiting: 
                begin
                  if (second_cnt == 6'b0 && minute_cnt == 5'b0 && clk_cycle_cnt == 14'b0)
                    state <= alarm;
                else 
                    state <= waiting;
                end
            alarm: 
                begin
                if (start == 1'b0)
                    state <= idle;
                else
                    state <= alarm;
                end
            default: state <= idle;
        endcase
    end
  end  
  
  always @(posedge clk or posedge rst)
  begin
    if (rst) begin
      minute_cnt 	<= 5'b1;
      second_cnt    <= 6'd59;
      clk_cycle_cnt <= clk_frequency - 1;
    end
    else begin
        if (state == idle) begin
            //load wait time from io_in
            minute_cnt    <= io_in[7:3] - 1;
            second_cnt    <= 6'd59;
            clk_cycle_cnt <= clk_frequency - 1;
        end
        if (state == waiting) begin
            if (clk_cycle_cnt == 14'b0) begin
                clk_cycle_cnt <= clk_frequency - 1;
                if (second_cnt == 6'b0) begin
                    second_cnt <= 6'd59;
                  if (minute_cnt != 5'b0) begin
                        minute_cnt <= minute_cnt - 1;
                    end
                end
                else begin
                    second_cnt <= second_cnt - 1;
                end
            end
            else begin
                clk_cycle_cnt <= clk_cycle_cnt - 1;
            end
        end 
    end
  end
  
  // 7 segment display
  always @(posedge clk or posedge rst)
  begin
	if(rst) begin
        	io_out <= 8'b0;
    	end else begin
        case(state)
              idle: 
                  begin
                    io_out <= 8'b01000000;
                  end
              waiting: 
                  begin
                    io_out [6:0] <= 7'b0;
                    if (clk_cycle_cnt == 14'b0)
                    	io_out[7]<=~io_out[7];
                  end
              alarm: 
                  begin
	                io_out <= 8'b11110111;
                  end
              default:;
          endcase
        end
  end

endmodule
module voice(
    input clk,
    input addr,
    input write_data,
    input [5:0] data,
    output out
);

    reg [5:0] max_clk_div_counter;

    always @(posedge clk) begin
        if (write_data & ~addr)
            max_clk_div_counter <= data;
    end

    reg [5:0] clk_div_counter;
    wire tick = clk_div_counter >= max_clk_div_counter;

    always @(posedge clk) begin
        if (tick) begin
            clk_div_counter <= 6'h00;
        end
        else begin
            clk_div_counter <= clk_div_counter + 6'h01;
        end
    end

    reg [3:0] lfsr_tap_mask;

    always @(posedge clk) begin
        if (write_data & addr)
            lfsr_tap_mask <= data[3:0];
    end

    reg [9:0] lfsr;
    wire tap1 = lfsr[1] & lfsr_tap_mask[0];
    wire tap4 = lfsr[4] & lfsr_tap_mask[1];
    wire tap6 = lfsr[6] & lfsr_tap_mask[2];
    wire tap9 = lfsr[9] & lfsr_tap_mask[3];

    always @(posedge clk) begin
        if (tick) begin
            if (lfsr == 10'h00) begin
                lfsr <= 10'h01;
            end
            else begin
                lfsr <= {lfsr[8:0], tap1 ^ tap4 ^ tap6 ^ tap9};
            end
        end
    end

    assign out = lfsr[0];

endmodule
module mixer(
    input clk,
    input write_data,
    input [5:0] data,
    input voice0_out,
    input voice1_out,
    output [3:0] out
);

    reg [5:0] voice_volumes;

    always @(posedge clk) begin
        if (write_data)
            voice_volumes <= data;
    end

    wire [2:0] voice0_volume = voice_volumes[2:0];
    wire [2:0] voice1_volume = voice_volumes[5:3];

    wire [2:0] scaled_voice0_out = voice0_out ? voice0_volume : 3'h00;
    wire [2:0] scaled_voice1_out = voice1_out ? voice1_volume : 3'h00;

    assign out = scaled_voice0_out + scaled_voice1_out;

endmodule
module yupferris_bitslam(
    input [7:0] io_in,
    output [7:0] io_out
);

    wire clk = io_in[0];

    wire addr_data_sel = io_in[1];
    wire write_addr = ~addr_data_sel;
    wire write_data = addr_data_sel;
    wire [5:0] addr_data = io_in[7:2];
    wire [5:0] data = addr_data;

    reg [2:0] addr;

    always @(posedge clk) begin
        if (write_addr)
            addr <= addr_data[2:0];
    end

    wire voice_select = addr[1];
    wire mixer_select = addr[2];

    wire voice0_select = ~voice_select & ~mixer_select;
    wire voice1_select = voice_select & ~mixer_select;

    wire voice0_out;
    voice voice0(
        .clk(clk),
        .addr(addr[0]),
        .write_data(write_data & voice0_select),
        .data(data),
        .out(voice0_out)
    );

    wire voice1_out;
    voice voice1(
        .clk(clk),
        .addr(addr[0]),
        .write_data(write_data & voice1_select),
        .data(data),
        .out(voice1_out)
    );

    wire [3:0] mixer_out;
    mixer mixer(
        .clk(clk),
        .write_data(write_data & mixer_select),
        .data(data),
        .voice0_out(voice0_out),
        .voice1_out(voice1_out),
        .out(mixer_out)
    );

    assign io_out = {4'h00, mixer_out};

endmodule
module user_module_348195845106041428(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4;
  wire net5;
  wire net6 = 1'b1;
  wire net7;
  wire net8;
  wire net9;
  wire net10;
  wire net11 = 1'b0;
  wire net12 = 1'b0;
  wire net13;
  wire net14;
  wire net15;
  wire net16;
  wire net17;
  wire net18;
  wire net19;
  wire net20;
  wire net21;
  wire net22;
  wire net23;
  wire net24;
  wire net25;

  assign io_out[0] = net4;
  assign io_out[1] = net5;

  or_cell gate2 (

  );
  nand_cell gate4 (
    .a (net7),
    .b (net1),
    .out (net8)
  );
  not_cell gate5 (
    .in (net7),
    .out (net4)
  );
  buffer_cell gate6 (
    .in (net9),
    .out (net10)
  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  nand_cell nand1 (
    .a (net8),
    .b (net13),
    .out (net14)
  );
  nand_cell nand2 (
    .a (net14),
    .b (net10),
    .out (net13)
  );
  nand_cell nand3 (
    .a (net10),
    .b (net15),
    .out (net16)
  );
  nand_cell nand4 (
    .a (net16),
    .b (net17),
    .out (net15)
  );
  nand_cell nand5 (
    .a (net2),
    .b (net5),
    .out (net17)
  );
  and_cell and1 (
    .a (net8),
    .b (net14),
    .out (net18)
  );
  nand_cell nand6 (
    .a (net18),
    .b (net10),
    .out (net7)
  );
  nand_cell nand7 (
    .a (net14),
    .b (net8),
    .out (net19)
  );
  nand_cell nand8 (
    .a (net17),
    .b (net15),
    .out (net20)
  );
  nand_cell nand9 (
    .a (net19),
    .b (net19),
    .out (net21)
  );
  nand_cell nand10 (
    .a (net20),
    .b (net20),
    .out (net22)
  );
  nand_cell nand11 (
    .a (net21),
    .b (net22),
    .out (net23)
  );
  nand_cell nand12 (
    .a (net23),
    .b (net3),
    .out (net24)
  );
  not_cell not1 (
    .in (net24),
    .out (net9)
  );
  and_cell and2 (
    .a (net10),
    .b (net15),
    .out (net25)
  );
  nand_cell nand13 (
    .a (net25),
    .b (net17),
    .out (net5)
  );
endmodule
module tiny_fft (
  input [7:0] io_in,
  output [7:0] io_out
);

    wire clk = io_in[0];
    wire reset = io_in[1];
    wire wrEn = io_in[2];

    wire [3:0] data_in = io_in[7:4];

    reg [1:0] wrIdx;
    reg [2:0] rdIdx;

    reg signed [3:0] input_reg[0:3];

    assign io_out[0] = (rdIdx == 0) ? 1'b1 : 1'b0;
    // Signal high when output value is real
    assign io_out[1] = ~rdIdx[0];

    always @(posedge clk) begin
        if (reset) begin
            wrIdx <= 0;
        end else if(wrEn) begin
            input_reg[wrIdx] <= data_in;
            wrIdx <= wrIdx + 1;
        end
    end

    wire [5:0] stage0_0 = input_reg[0] + input_reg[2];
    wire [5:0] stage0_1 = input_reg[0] + ((~input_reg[2]) + 1);
    wire [5:0] stage0_2 = input_reg[1] + input_reg[3];
    wire [5:0] stage0_3 = input_reg[1] + ((~input_reg[3]) + 1);

    wire [5:0] stage1[0:7];

    // Freq bin 0 real + complex
    assign stage1[0] = stage0_0 + stage0_2;
    assign stage1[1] = 0;
    // Freq bin 1 real + complex
    assign stage1[2] = stage0_1;
    assign stage1[3] = ((~stage0_3) + 1);
    // Freq bin 2 real + complex
    assign stage1[4] = ((~stage0_2) + 1) + stage0_0;
    assign stage1[5] = 0;
    // Freq bin 3 real + complex
    assign stage1[6] = stage0_1;
    assign stage1[7] = stage0_3;

    assign io_out[7:2] = stage1[rdIdx];

    always @(posedge clk) begin
        if (reset) begin
            rdIdx <= 0;
        end else begin
            rdIdx <= rdIdx + 1;
        end
    end

endmodule
module tt2_tholin_multiplexed_counter(
   input [7:0] io_in,
   output [7:0] io_out
);
   wire s_A;
   wire s_B;
   wire s_C;
   wire s_CLK = io_in[0];
   wire s_D;
   wire s_E;
   wire s_F;
   wire s_G;
   wire s_RST = io_in[1];
   wire s_SEL;

   assign io_out[0] = s_A;
   assign io_out[1] = s_B;
   assign io_out[2] = s_C;
   assign io_out[3] = s_D;
   assign io_out[4] = s_E;
   assign io_out[5] = s_F;
   assign io_out[6] = s_G;
   assign io_out[7] = s_SEL;

   main   CIRCUIT_0 (.A(s_A),
                     .B(s_B),
                     .C(s_C),
                     .CLK(s_CLK),
                     .D(s_D),
                     .E(s_E),
                     .F(s_F),
                     .G(s_G),
                     .RST(s_RST),
                     .SEL(s_SEL));
endmodule
module msaghir_top_level 
  (
    input   [7:0] io_in, 
    output  [7:0] io_out
  );

  wire      w_clk = io_in[0];
  wire      w_rst = io_in[1];
  wire      [3:0] w_sel = io_in[5:2];
  wire      w_blink = io_in[6];
  wire      w_fx = io_in[7];
  wire      [6:0] w_segment;
  wire      w_clk2Hz;
  wire      [6:0] w_bus0;
  wire      [6:0] w_bus1;

  assign io_out = {1'b0, w_segment};

  digit_gen b0 (.i_digit(w_sel), .i_blink(w_blink), .i_clk2Hz(w_clk2Hz), .o_segment(w_bus0));
  fx_gen    b1 (.i_clk(w_clk), .i_rst(w_rst), .i_sel(w_sel), .o_clk2Hz(w_clk2Hz), .o_segment(w_bus1));
  mux2      b2 (.i_in0(w_bus0), .i_in1(w_bus1), .i_sel(w_fx), .o_out(w_segment));

endmodule
module logisim_demo(
  input [7:0] io_in,
  output [7:0] io_out
);

   wire s_CLK = io_in[0];
   wire s_A;
   wire s_B;
   wire s_C;
   wire s_D;
   wire s_E;
   wire s_F;
   wire s_G;
   wire s_DP;
   assign io_out[0] = s_A;
   assign io_out[1] = s_B;
   assign io_out[2] = s_C;
   assign io_out[3] = s_D;
   assign io_out[4] = s_E;
   assign io_out[5] = s_F;
   assign io_out[6] = s_G;
   assign io_out[7] = s_DP;
   wire s_RST = io_in[1];

  main   CIRCUIT_0 (.CLK(s_CLK),
                     .A(s_A),
                     .B(s_B),
                     .C(s_C),
                     .D(s_D),
                     .E(s_E),
                     .F(s_F),
                     .G(s_G),
                     .DP(s_DP),
                     .RST(s_RST));
endmodule
module tomkeddie_top_tto_a
  #(parameter CLOCK_RATE=1000)
  (
   input [7:0]  io_in,
   output [7:0] io_out
   );
  
  wire                      clk   = io_in[0];
  wire                      reset = io_in[1];
  wire                      uart_tx_pin0;
  wire                      uart_tx_pin1;
  wire                      uart_tx_pin2;

  assign io_out[0] = uart_tx_pin0;
  assign io_out[1] = uart_tx_pin1;
  assign io_out[2] = uart_tx_pin2;

  // instatiate lcd
  uart_tx uart_tx(.clk(clk), .reset(reset), .tx_pin0(uart_tx_pin0), .tx_pin1(uart_tx_pin1), .tx_pin2(uart_tx_pin2));
  
endmodule
module user_module_341678527574180436(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[1];
  wire net2 = io_in[2];
  wire net3;
  wire net4 = 1'b0;
  wire net5 = 1'b1;
  wire net6 = 1'b1;

  assign io_out[0] = net3;

  and_cell gate1 (
    .a (net1),
    .b (net2),
    .out (net3)
  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
endmodule
module option22 (
    input wire [7:0] io_in,
    output wire [7:0] io_out
);
parameter WORD_COUNT = 22;

wire clk = io_in[0];
wire reset = io_in[1];
wire write = io_in[2];
wire din = io_in[3];

assign io_out = buffer[7:0];

reg [2:0] count;
reg [8 * WORD_COUNT - 1:0] buffer;

wire [7:0] bh = (write & din) | (!write & buffer[15]);

always@(posedge clk or posedge reset) begin

    if(reset) begin
        count <= 3'd0;
    end else begin
        if(count == 3'b111) begin
            buffer <= {buffer[7:0], buffer[WORD_COUNT * 8 - 1:16], bh, buffer[15:9]};
        end else begin
            buffer[15:8] <= {bh, buffer[15:9]};
        end
        count <= count + 3'd1;
    end
end
endmodule
module user_module_349255310782759507(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7 = io_in[6];
  wire net8 = io_in[7];
  wire net9;
  wire net10;
  wire net11 = 1'b0;
  wire net12 = 1'b1;
  wire net13 = 1'b1;
  wire net14;
  wire net15;
  wire net16;
  wire net17;
  wire net18;
  wire net19 = 1'b1;
  wire net20;
  wire net21;
  wire net22;
  wire net23;
  wire net24;
  wire net25;
  wire net26;

  assign io_out[0] = net9;
  assign io_out[3] = net10;

  mux_cell mux1 (
    .a (net14),
    .b (net15),
    .sel (net16),
    .out (net17)
  );
  mux_cell mux2 (
    .a (net18),
    .b (net19),
    .sel (net16),
    .out (net20)
  );
  mux_cell mux3 (
    .a (net17),
    .b (net20),
    .sel (net21),
    .out (net9)
  );
  buffer_cell gate1 (
    .in (net1),
    .out (net16)
  );
  buffer_cell gate2 (
    .in (net2),
    .out (net21)
  );
  buffer_cell gate3 (
    .in (net3),
    .out (net14)
  );
  mux_cell mux4 (
    .a (net22),
    .b (net23),
    .sel (net16),
    .out (net24)
  );
  mux_cell mux5 (
    .a (net25),
    .b (net19),
    .sel (net16),
    .out (net26)
  );
  mux_cell mux6 (
    .a (net24),
    .b (net26),
    .sel (net21),
    .out (net10)
  );
  buffer_cell gate4 (
    .in (net4),
    .out (net22)
  );
  buffer_cell gate5 (
    .in (net5),
    .out (net15)
  );
  buffer_cell gate6 (
    .in (net6),
    .out (net23)
  );
  buffer_cell gate7 (
    .in (net7),
    .out (net18)
  );
  buffer_cell gate8 (
    .in (net8),
    .out (net25)
  );
endmodule
module afoote_w5s8_tt02_utm_core(
    input clock,
    input reset,
    input mode,
    input [2:0] encoded_state_in,
    input [2:0] sym_in,
    input sym_in_valid,
    output [2:0] new_sym,
    output direction,
    output [2:0] encoded_next_state
);

reg [7:0] stored_state;
reg [2:0] symbuf;
reg symbuf_valid;

wire [7:0] state_in;
wire [7:0] state;
wire [7:0] next_state;
wire [2:0] sym;

always @(posedge clock) begin
    if (reset) begin
        stored_state <= 8'h01;
    end
    else if (sym_in_valid && symbuf_valid) begin
        stored_state <= next_state;
    end
    else begin
        stored_state <= stored_state;
    end
end

always @(posedge clock) begin
    if (reset) begin
        symbuf <= 3'b0;
    end
    else if (sym_in_valid) begin
        symbuf <= sym_in;
    end
    else begin
        symbuf <= symbuf;
    end
end

always @(posedge clock) begin
    if (reset) begin
        symbuf_valid <= 0;
    end
    else if (sym_in_valid) begin
        symbuf_valid <= 1;
    end
    else begin
        symbuf_valid <= symbuf_valid;
    end
end

afoote_w5s8_tt02_decoder_3to8 decode_state_in(
    .in(encoded_state_in),
    .out(state_in)
);

assign state = (mode == 0) ? state_in : stored_state;
assign sym = (mode == 0) ? sym_in : symbuf;

afoote_w5s8_tt02_direction direction_block(
    .state(state),
    .s2(sym[2]),
    .s1(sym[1]),
    .s0(sym[0]),
    .direction(direction)
);

afoote_w5s8_tt02_next_state next_state_block(
    .state_in(state),
    .s2(sym[2]),
    .s1(sym[1]),
    .s0(sym[0]),
    .state_out(next_state));

afoote_w5s8_tt02_new_symbol new_sym_block(
    .state_in(state),
    .s2(sym[2]),
    .s1(sym[1]),
    .s0(sym[0]),
    .z2(new_sym[2]),
    .z1(new_sym[1]),
    .z0(new_sym[0])
);

afoote_w5s8_tt02_encoder_8to3 encode_state_out(
    .in(next_state),
    .out(encoded_next_state)
);

endmodule
module afoote_w5s8_tt02_direction(
    input [7:0] state,
    input s2,
    input s1,
    input s0,
    // 0 = left, 1 = right
    output direction
);

wire a,b,c,d,e,f,g,h;

assign a = state[0];
assign b = state[1];
assign c = state[2];
assign d = state[3];
assign e = state[4];
assign f = state[5];
assign g = state[6];
assign h = state[7];

assign direction = ((a | e | f) & s1)
                 | (((a & s0) | b | c | (e & s0) | f | g | h) & s2)
                 | ((d | (e & (~s1) & (~s0))) & (~s2))
                 | (g & (~s1));
endmodule
module afoote_w5s8_tt02_next_state(
    input [7:0] state_in,
    input s2,
    input s1,
    input s0,
    output [7:0] state_out
);

wire a,b,c,d,e,f,g,h;

assign a = state_in[0];
assign b = state_in[1];
assign c = state_in[2];
assign d = state_in[3];
assign e = state_in[4];
assign f = state_in[5];
assign g = state_in[6];
assign h = state_in[7];

wire sym_0;
assign sym_0 = (~s2) & (~s1) & (~s0);

// next H
assign state_out[7] = s2 & ((s0 & (b | c)) | h);

// next G
assign state_out[6] = (s2 & ( ((b | c) & (~s0)) | g)) | (f & s1);

// next F
assign state_out[5] = (e & (~s2) & s0) | (f & (~(s2 | s1))) | (s1 & (g | h));

// next E
assign state_out[4] = (a & s2 & (~s0)) | (d & (~s2) & s0) | (e & (s1 | (s2 & s0)));

// next D
assign state_out[3] = (b & s1) | (d & s2) | (e & (~s1) & (~s0));

// next C
assign state_out[2] = (a & (~s2) & s0) | (c & (~(s2 | s1))) | (d & sym_0);

// next B
assign state_out[1] = (a & sym_0) | (b & (~(s2 | s1))) | (c & s1) | (f & s2);

// next A
assign state_out[0] = (a & (s1 | (s2 & s0))) | (d & s1) | ((g | h) & (~(s2 | s1)));

endmodule
module afoote_w5s8_tt02_new_symbol(
    input [7:0] state_in,
    input s2,
    input s1,
    input s0,
    output z2,
    output z1,
    output z0
);

wire a,b,c,d,e,f,g,h;

assign a = state_in[0];
assign b = state_in[1];
assign c = state_in[2];
assign d = state_in[3];
assign e = state_in[4];
assign f = state_in[5];
assign g = state_in[6];
assign h = state_in[7];

assign z2 = ((~s2) & b) | (d & s0) | c | (e & (s0 | s1)) | (f & (~(s2 | s1)));
assign z1 = (a & (~s2)) | (d & (s2 | s1) & (~s0)) | (e & s2 & (~s0));
assign z0 = (s0 & ((a & s2) | (~a))) | (h & s1);

endmodule
module afoote_w5s8_tt02_decoder_3to8(
    input [2:0] in,
    output [7:0] out
);

assign out[0] = (~in[2]) & (~in[1]) & (~in[0]);
assign out[1] = (~in[2]) & (~in[1]) & ( in[0]);
assign out[2] = (~in[2]) & ( in[1]) & (~in[0]);
assign out[3] = (~in[2]) & ( in[1]) & ( in[0]);
assign out[4] = ( in[2]) & (~in[1]) & (~in[0]);
assign out[5] = ( in[2]) & (~in[1]) & ( in[0]);
assign out[6] = ( in[2]) & ( in[1]) & (~in[0]);
assign out[7] = ( in[2]) & ( in[1]) & ( in[0]);

endmodule
module afoote_w5s8_tt02_encoder_8to3(
    input [7:0] in,
    output [2:0] out
);

assign out[0] = in[1] | in[3] | in[5] | in[7];
assign out[1] = in[2] | in[3] | in[6] | in[7];
assign out[2] = in[4] | in[5] | in[6] | in[7];
endmodule
module afoote_w5s8_tt02_top(
  input [7:0] io_in,
  output [7:0] io_out
);

wire mode;
wire clock;
wire reset;

wire direction;

wire sym_valid;
wire [2:0] sym_in;
wire [2:0] new_sym;

// 1-hot state in & out
wire [7:0] state_in;
wire [7:0] state_out;

// 3-bit dense encoding of state in & out
wire [2:0] encoded_state_in;
wire [2:0] encoded_state_out;

assign mode = io_in[7];
assign clock = io_in[0];
assign reset = (mode == 0) ? 1'b1 : io_in[1];

assign encoded_state_in = (mode == 0) ? io_in[3:1] : 3'b0;
assign io_out[7:5] = encoded_state_out;

assign sym_valid = (mode == 0) ? 1'b0 : io_in[2];
assign sym_in = io_in[6:4];
assign io_out[4:2] = new_sym;

assign io_out[1] = direction;
assign io_out[0] = 1'b0;

afoote_w5s8_tt02_utm_core core(
    .clock(clock),
    .reset(reset),
    .mode(mode),
    .encoded_state_in(encoded_state_in),
    .sym_in(sym_in),
    .sym_in_valid(sym_valid),
    .new_sym(new_sym),
    .direction(direction),
    .encoded_next_state(encoded_state_out)
);

endmodule
module AidanMedcalf_pid_controller (
    input  [7:0] io_in,
    output [7:0] io_out
);

    wire clk;
    wire reset;
    //wire enable;
    wire cfg_clk;
    wire cfg_mosi;
    wire cfg_cs;
    wire pv_in_miso;

    assign clk        = io_in[0];
    assign reset      = io_in[1];
    // io_in[2] not used
    //assign enable     = io_in[2];
    assign cfg_clk    = io_in[3];
    assign cfg_mosi   = io_in[4];
    // io_in[5] not used
    assign cfg_cs     = io_in[6];
    assign pv_in_miso = io_in[7];

    wire pv_in_clk;
    wire pv_in_cs;
    reg  [1:0] pv_in_cs_hist;
    wire out_clk, out_cs, out_mosi;

    assign io_out[0] = pv_in_clk;
    assign io_out[1] = pv_in_cs;
    //assign io_out[2] = 1'b0; // io_out[2] not used
    //assign io_out[3] = pid_stb_d1;
    //assign io_out[7:4] = out;
    assign io_out[2] = out_clk;
    assign io_out[3] = out_mosi;
    assign io_out[4] = out_cs;
    assign io_out[7:5] = 1'b0; // not used

    // Configuration registers
    //reg  [7:0] cfg_buf[4];
    wire [7:0] sp;
    wire [7:0] kp;
    wire [7:0] ki;
    //wire [7:0] kd;

    //assign sp = cfg_buf[0][3:0];
    //assign kp = cfg_buf[0][7:4];
    //assign ki = cfg_buf[1][3:0];
    //assign kd = cfg_buf[1][7:4];
    //assign stb_level[7:0] = cfg_buf[2];
    //assign stb_level[15:8] = cfg_buf[3];

    assign sp = cfg_spi_buffer[7:0];
    assign kp = cfg_spi_buffer[15:8];
    assign ki = cfg_spi_buffer[23:16];
    //assign kd = cfg_spi_buffer[31:24];

    wire pv_stb;
    wire pid_stb;
    reg pid_stb_d1;

    wire pid_rst;
    assign pid_rst = reset || !cfg_cs;

    // I/O registers
    reg [7:0] in_pv;
    reg [7:0] out;

    // Slave SPI for configuration
    //wire cfg_spi_done;
    wire [23:0] cfg_spi_buffer;
    spi_slave_in #(.BITS(24)) cfg_spi(.reset(reset), .clk(clk), .cs(cfg_cs), .sck(cfg_clk), .mosi(cfg_mosi), .out_buf(cfg_spi_buffer));

    // Shift input in
    spi_master_in spi_in(.reset(pid_rst), .clk(clk),
                           .miso(pv_in_miso), .start(pv_stb),
                           .out_buf(in_pv), .sck(pv_in_clk), .cs(pv_in_cs));

    // Shift output out
    spi_master_out spi_out(.reset(pid_rst), .clk(clk), .in_buf(out),
                           .start(pid_stb_d1),
                           .sck(out_clk), .cs(out_cs), .mosi(out_mosi));

    // PID core
    pid pid (.reset(pid_rst), .clk(clk), .pv_stb(pid_stb),
             .sp(sp), .pv(in_pv),
             .kp(kp), .ki(ki),
             .stimulus(out));
    
    strobe #(.BITS(16)) pv_stb_gen(.reset(reset), .clk(clk), .out(pv_stb));

    assign pid_stb = pv_in_cs_hist[0] && !pv_in_cs_hist[1];

    always @(posedge clk) begin
        if (reset) begin
            pid_stb_d1 <= 'b0;
            pv_in_cs_hist <= 'b0;
        end else begin
            pv_in_cs_hist <= { pv_in_cs_hist[0], pv_in_cs };
            pid_stb_d1 <= pid_stb;
        end
    end

endmodule
module edge_detect (
    input  reset,
    input  clk,
    input  sig,
    input  pol,
    output out
);
    reg sigin;
    reg siglast;
    assign out = reset ? 1'b0 : (pol ? ((!siglast) && sigin) : (siglast && (!sigin)));
    always @(posedge clk) begin
        { siglast, sigin } <= { sigin, sig };
        //sigin <= sig;
        //siglast <= sigin;
    end
endmodule
module strobe #(
    parameter BITS=8
) (
    input reset,
    input clk,
    output out
);
    reg  [BITS-1:0] count;
    wire [BITS-1:0] next;
    assign next = count + 'b1;
    assign out = next == 'b0;
    always @(posedge clk) begin
        if (reset) begin
            count <= 'b0;
        end else begin
            count <= next;
        end
    end
endmodule
module rglenn_hex_to_7_seg (
  input [7:0] io_in,
  output [7:0] io_out
);
    
    wire latch = io_in[0];
    wire blank = io_in[1];
    wire [4:0] data = io_in[5:2];
    wire [6:0] led_out;
    assign io_out[6:0] = blank ? 7'b0000000 : led_out;
    assign io_out[7] = io_in[6]; // decimal point

    // external clock is 1000Hz, so need 10 bit counter
    reg [3:0] data_reg;

    always @(posedge latch) begin
        data_reg <= data;
    end

    // instantiate segment display
    hex2seg7 hex2seg7(.data(data_reg), .segments(led_out));

endmodule
module user_module_348540666182107731(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7 = io_in[6];
  wire net8 = io_in[7];
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13;
  wire net14;
  wire net15;
  wire net16;
  wire net17 = 1'b0;
  wire net18 = 1'b1;
  wire net19 = 1'b1;
  wire net20;
  wire net21;
  wire net22;

  assign io_out[0] = net9;
  assign io_out[1] = net10;
  assign io_out[2] = net11;
  assign io_out[3] = net12;
  assign io_out[4] = net13;
  assign io_out[5] = net14;
  assign io_out[6] = net15;
  assign io_out[7] = net16;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (
    .a (net6),
    .b (net14),
    .out (net13)
  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (
    .d (net2),
    .clk (net1),
    .q (net9),
    .notq (net10)
  );
  dff_cell flop1 (

  );
  dffsr_cell flipflop2 (
    .d (net2),
    .clk (net3),
    .s (net4),
    .r (net5),
    .q (net11),
    .notq (net12)
  );
  nand_cell gate7 (
    .a (net13),
    .b (net7),
    .out (net14)
  );
  and_cell gate8 (
    .a (net2),
    .b (net8),
    .out (net20)
  );
  or_cell gate9 (
    .a (net2),
    .b (net8),
    .out (net21)
  );
  and_cell gate10 (
    .a (net21),
    .b (net15),
    .out (net22)
  );
  or_cell gate11 (
    .a (net20),
    .b (net22),
    .out (net15)
  );
  not_cell gate12 (
    .in (net1),
    .out (net16)
  );
endmodule
module jleightcap_top( input wire  [7:0] io_in
                     , output wire [7:0] io_out
                     );

    top _top( .clk(io_in[0])
            , .rst(io_in[1])
            , .instr(io_in[7:2])
            , .io_out(io_out)
            );

endmodule
module user_module_346553315158393428(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6;
  wire net7 = 1'b0;
  wire net8 = 1'b1;
  wire net9;
  wire net10;

  assign io_out[0] = net6;

  xor_cell gate3 (
    .a (net9),
    .b (net4),
    .out (net10)
  );
  mux_cell mux1 (
    .a (net1),
    .b (net2),
    .sel (net3),
    .out (net9)
  );
  xor_cell gate1 (
    .a (net10),
    .b (net5),
    .out (net6)
  );
endmodule
module femto_top 
#(
    parameter OPSIZE = 3, //Number of opcodes, power of 2 (3 => 2**3 = 8 opcodes)
    parameter  NUMRF = 2,  //Number of registers in register file, power of 2 (2 => 2**2 = 4 registers)
    parameter   SIZE = 4 //Size of data in bits
)
(
    input  [7:0] io_in,
    output [7:0] io_out
);

wire clk=io_in[0];
reg[1:0] mode;

reg change_state;
reg[1:0] next_mode;

always @(*) begin
    if(io_in[3:1]==0&&io_in[7:6]==2'b10) 
    begin
        change_state=1'b1;
        next_mode=io_in[5:4];
    end
    else begin
        change_state=0;
        next_mode=0;
    end 
        
end

always @(posedge clk) begin
    if(change_state==1) begin
        mode<=next_mode;
    end
end

//Mode:
//00: No action
//01: Run (Read instruction buffer)
//10: Fill (Write instruction buffer)
//11: N/A

wire wren=mode[1]&&(io_in[3:1]!=0&&io_in[7:6]!=2'b10); //Don't write when changing state
wire rden=mode[0];
wire[6:0] instr_in=io_in[7:1];
wire[6:0] instr_out;

ibuffer 
#(
    .ENTRIES(6)
)
ibuf
(
    .clk(clk), .wren(wren), .rden(rden),
    .instr_in(instr_in),
    .instr_out(instr_out)
);

//Decode (from interface)
// wire[OPSIZE-1:0]     op=io_in[1+:OPSIZE];                        //opcode wire
// wire  [NUMRF-1:0] reg_0=io_in[1+OPSIZE+:NUMRF];                  //register address 0 (Dest)
// wire  [NUMRF-1:0] reg_1=io_in[1+OPSIZE+NUMRF+:NUMRF];            //register address 1 (Src)
wire[OPSIZE-1:0]                     op=instr_out[2:0];                        //opcode wire
wire  [NUMRF-1:0]                 reg_0=instr_out[4:3];                  //register address 0 (Dest)
wire  [NUMRF-1:0]                 reg_1=instr_out[6:5];            //register address 1 (Src)


wire valid=(op=={(OPSIZE){1'b1}})?1:0;
wire rd=(op!=3'h6&&op!=3'h0&&op!=3'h1);
wire wr=(op==3'h6);
reg[3:0] value;

wire [SIZE-1:0] data_0,data_1,data_out;

reg_file #( .NUMRF(NUMRF),  .SIZE(SIZE))  rf (.clk(clk), .rd(rd), .wr(wr), .reg_out(reg_1),.reg_in(reg_0),.data_in(data_0),.data_out(data_1));

//Execute
alu_gen  #(.OPSIZE(OPSIZE), .SIZE(SIZE)) alu (.clk(clk), .op(op),.inp(data_1),.outp(data_out));

//Output

assign data_0=data_out;

always @(posedge clk) begin
    if(valid==1) begin
        value<=data_out;
    end
end

seg7 seg(.value(value),.segments(io_out[6:0]));
endmodule
module krasin_3_bit_8_channel_pwm_driver (
  input [7:0] io_in,
  output [7:0] io_out
);
    
  wire clk = io_in[0];
  wire pset = io_in[1];
  wire [2:0] addr = io_in[4:2];
  wire [2:0] level = io_in[7:5];

  wire [7:0] pwm_out;
  assign io_out[7:0] = pwm_out;

  // This register is used to determine if the execution just started and we need to reset.
  // It's a bullshit implementation and will most likely not work. I am curious to test it anyway.
  // The idea is that initially this register has a somewhat random value. If it does not match what we expect,
  // we're in a reset mode and set this register to the expected state + reset all other registers.
  // This is not a great way, as it does not guarantee anything, but I already use all input pins and
  // like to live dangerously.
  reg[8:0] reset_canary = 0;

  // 3-bit PWM counter that goes from 0 to 7.
  reg [2:0] counter;

  function is_reset (input [8:0] a);
    begin
      is_reset = (a != 8'b01010101);
    end
  endfunction

  // PWM level for channel0.
  // 0 means always off.
  // 1 means that PWM will be on for just 1 clock cycle and then off for the other 6, giving 1/7 on average.
  // 6 means 6/7 on.
  // 7 means always on.
  reg [2:0] pwm0_level;
  // The rest of the channels.
  reg [2:0] pwm1_level;
  reg [2:0] pwm2_level;
  reg [2:0] pwm3_level;
  reg [2:0] pwm4_level;
  reg [2:0] pwm5_level;
  reg [2:0] pwm6_level;
  reg [2:0] pwm7_level;

  function is_on(input [3:0] level, input[3:0] counter);
    begin
      is_on = (counter < level);
    end
  endfunction // is_on

  assign pwm_out[0] = is_on(pwm0_level, counter);
  assign pwm_out[1] = is_on(pwm1_level, counter);
  assign pwm_out[2] = is_on(pwm2_level, counter);
  assign pwm_out[3] = is_on(pwm3_level, counter);
  assign pwm_out[4] = is_on(pwm4_level, counter);
  assign pwm_out[5] = is_on(pwm5_level, counter);
  assign pwm_out[6] = is_on(pwm6_level, counter);
  assign pwm_out[7] = is_on(pwm7_level, counter);

  // external clock is 1000Hz.
  always @(posedge clk) begin
    // if reset, set counter and pwm levels to 0
    if (is_reset(reset_canary)) begin
      reset_canary = 8'b01010101;
      counter <= 0;
      pwm0_level <= 0;
      pwm1_level <= 0;
      pwm2_level <= 0;
      pwm3_level <= 0;
      pwm4_level <= 0;
      pwm5_level <= 0;
      pwm6_level <= 0;
      pwm7_level <= 0;
    end else begin // if (is_reset(reset_canary))
      if (counter == 6) begin
        // Roll over.
        counter <= 0;
      end else begin
        // increment counter
        counter <= counter + 1'b1;
      end
      if (pset) begin
        case (addr)
          0: pwm0_level <= level;
          1: pwm1_level <= level;
          2: pwm2_level <= level;
          3: pwm3_level <= level;
          4: pwm4_level <= level;
          5: pwm5_level <= level;
          6: pwm6_level <= level;
          7: pwm7_level <= level;
        endcase
      end // if (set)
    end
  end // always @ (posedge clk)
endmodule
module regymm_mcpi(
	input [7:0] io_in, 
	output reg [7:0] io_out
);
	wire clk = io_in[0];
	wire rst = io_in[1];
	wire [5:0]sw1 = io_in[7:2];

	always @ (*) begin
		io_out = 0;
		case(sw1[1:0])
			0: io_out = cnt[7:0];
			1: io_out = cnt_in[7:0];
			2: io_out = {6'b0, cnt[0], cnt_in[0]};
		endcase
	end

	reg [8:0]breg;
	reg [7:0]breg2; // shouldn't exceed 7:0 because x^2<1 when 0<x<1
	reg [7:0]x;

	reg [3:0]mulin1;
	reg [3:0]mulin2;
	wire [7:0]mulout;
	mul4_341521390605697619 mul_inst(
		.a(mulin1),
		.b(mulin2),
		.c(mulout)
	);

	reg [7:0]addin1;
	reg [7:0]addin2;
	wire [8:0]addout;
	assign addout = addin1 + addin2;

	// not very random actually, should somehow 
	// receive seed from outside
	reg [7:0]random = 8'h01;
	always @ (posedge clk) begin
		random <= {random[6:0], (random[7] ^ random[5] ^ random[4] ^ random[3])};
	end

	reg [3:0]sts;
	reg [7:0]cnt;
	reg [7:0]cnt_in;
	always @ (posedge clk) begin
		if (rst) begin
			sts <= 0;
			cnt <= 0;
			cnt_in <= 0;
			//x <= 0;
		end else begin
			if (sw1[5] == 0) begin
				case (sts)
					0: begin
						breg <= 0;
						x <= random;
					end
					4: begin
						x <= random;
						breg2 <= breg_in;
					end
					9: begin
						cnt <= cnt + 1;
						if (addout[8]) cnt_in <= cnt_in + 1;
					end
				endcase
				sts <= sts == 10 ? 0 : sts + 1;
				breg <= breg_in;
			end
		end
	end

	reg [8:0]breg_in;
	always @ (*) begin
		mulin1 = 0;
		mulin2 = 0;
		addin1 = 0;
		addin2 = 0;
		breg_in = 0;
		if (sts == 9) begin
			addin1 = breg;
			addin2 = breg2;
		end else begin
			case(sts[1:0])
				2'b01: begin
					mulin1 = x[3:0];
					mulin2 = x[3:0];
					breg_in = {1'b0, mulout};
				end
				2'b10: begin
					mulin1 = x[7:4];
					mulin2 = x[3:0];
					addin1 = {4'b0, breg[7:4]};
					addin2 = mulout;
					breg_in = addout;
				end
				2'b11: begin
					mulin1 = x[3:0];
					mulin2 = x[7:4];
					addin1 = breg[7:0];
					addin2 = mulout;
					breg_in = addout;
				end
				2'b00: begin
					mulin1 = x[7:4];
					mulin2 = x[7:4];
					addin1 = {3'b0, breg[8:4]};
					addin2 = mulout;
					breg_in = addout;
				end
			endcase
		end
	end
endmodule
module mul4_341521390605697619
(
	input [3:0] a,
	input [3:0] b,
	output [7:0] c
);
wire [3:0]x = b[0] ? a : 0;
wire [3:0]y = b[1] ? a : 0;
wire [3:0]z = b[2] ? a : 0;
wire [3:0]t = b[3] ? a : 0;

assign c = {
	add3,
	add2[0],
	add1[0],
	x[0]
	};
wire [4:0]add1;
add_341521390605697619 #(.WIDTH(4)) add_1(
	.a({1'b0, x[3:1]}),
	.b(y),
	.c(add1)
);

wire [4:0]add2;
add_341521390605697619 #(.WIDTH(4)) add_2(
	.a(add1[4:1]),
	.b(z),
	.c(add2)
);

wire [4:0]add3;
add_341521390605697619 #(.WIDTH(4)) add_3(
	.a(add2[4:1]),
	.b(t),
	.c(add3)
);
endmodule
module tt2_tholin_diceroll(
	input [7:0] io_in,
	output [7:0] io_out
);
	wire CLK = io_in[0];
	wire RST = io_in[1];
	wire ROLL = io_in[2];
	wire [7:0] LEDS;
	assign io_out[7:0] = LEDS;
	
	dice dice (
		.CLK(CLK),
		.RST(RST),
		.ROLL(ROLL),
		.LEDS(LEDS)
	);

endmodule
module c_tt2_mrcs_test (
  input [7:0] io_in,
  output [7:0] io_out  
);

wire net_0 = io_in[0];
wire net_1 = net_0;
wire net_2 = net_0;
wire net_3 = net_0;
wire net_4 = net_0;
wire net_5 = io_in[1];
wire net_6 = net_5;
wire net_7 = net_5;
wire net_8 = net_5;

wire net_9;
wire net_10;
wire net_11;
wire net_12;
wire net_13;
wire net_14;
wire net_15;
wire net_16;
wire net_17;
wire net_18;

assign io_out[0] = net_9;
assign io_out[1] = net_10;
assign io_out[2] = net_11;
assign io_out[3] = net_12;
assign io_out[4] = net_13;
assign io_out[5] = net_14;
assign io_out[6] = net_15;
assign io_out[7] = net_16;

c_BIN_DFF SavedGate_0 (
.in_0(net_1),
.in_1(net_6),
.out_0(net_10),
.out_1(net_11),
.out_2(net_17),
.out_3(net_18)
);

c_BIN_ZOOK_DLATCH SavedGate_1 (
.in_0(net_0),
.in_1(net_5),
.out_0(net_9)
);

c_BIN_NAND_DLATCH SavedGate_2 (
.in_1(net_2),
.in_0(net_7),
.out_0(net_12),
.out_1(net_13)
);

c_BIN_EDGE_DETECTOR SavedGate_3 (
.in_0(net_4),
.out_0(net_16)
);

c_BIN_NAND_SR_LATCH SavedGate_4 (
.in_0(net_3),
.in_1(net_8),
.out_0(net_14),
.out_1(net_15)
);

endmodule
module c_BIN_DFF (
     input [0:0] in_0,
     input [0:0] in_1,
     output [0:0] out_0,
     output [0:0] out_1,
     output [0:0] out_2,
     output [0:0] out_3
);

wire net_0 = in_0;
wire net_1 = net_0;
wire net_2 = in_1;

wire net_3;
wire net_4;
wire net_5;
wire net_6 = net_4;
wire net_7;
wire net_8;

assign out_0 = net_5;
assign out_1 = net_6;
assign out_2 = net_7;
assign out_3 = net_8;

f_2 LogicGate_0 (
.in_0(net_0),
.out_0(net_3)
);

c_BIN_NAND_DLATCH SavedGate_0 (
.in_0(net_2),
.in_1(net_3),
.out_0(net_4),
.out_1(net_8)
);

c_BIN_NAND_DLATCH SavedGate_1 (
.in_1(net_1),
.in_0(net_4),
.out_0(net_5),
.out_1(net_7)
);

endmodule
module c_BIN_EDGE_DETECTOR (
     input [0:0] in_0,
     output [0:0] out_0
);

wire net_0 = in_0;
wire net_1 = net_0;

wire net_2;
wire net_3;
wire net_4;
wire net_5;

assign out_0 = net_5;

f_K00 LogicGate_0 (
.in_1(net_0),
.in_0(net_4),
.out_0(net_5)
);

f_2 LogicGate_1 (
.in_0(net_1),
.out_0(net_2)
);

f_2 LogicGate_2 (
.in_0(net_2),
.out_0(net_3)
);

f_2 LogicGate_3 (
.in_0(net_3),
.out_0(net_4)
);

endmodule
module c_BIN_NAND_DLATCH (
     input [0:0] in_0,
     input [0:0] in_1,
     output [0:0] out_0,
     output [0:0] out_1
);

wire net_0 = in_0;
wire net_1 = net_0;
wire net_2 = in_1;
wire net_3 = net_2;

wire net_4;
wire net_5;
wire net_6;
wire net_7;
wire net_8;

assign out_0 = net_7;
assign out_1 = net_8;

f_22Z LogicGate_0 (
.in_1(net_0),
.in_0(net_2),
.out_0(net_4)
);

f_22Z LogicGate_1 (
.in_1(net_3),
.in_0(net_6),
.out_0(net_5)
);

f_2 LogicGate_2 (
.in_0(net_1),
.out_0(net_6)
);

c_BIN_NAND_SR_LATCH SavedGate_0 (
.in_0(net_4),
.in_1(net_5),
.out_0(net_7),
.out_1(net_8)
);

endmodule
module c_BIN_NAND_SR_LATCH (
     input [0:0] in_0,
     input [0:0] in_1,
     output [0:0] out_0,
     output [0:0] out_1
);

wire net_0 = in_0;
wire net_1 = in_1;

wire net_2;
wire net_3;
wire net_4 = net_2;
wire net_5 = net_3;

assign out_0 = net_4;
assign out_1 = net_5;

f_22Z LogicGate_0 (
.in_1(net_0),
.in_0(net_3),
.out_0(net_2)
);

f_22Z LogicGate_1 (
.in_1(net_2),
.in_0(net_1),
.out_0(net_3)
);

endmodule
module c_BIN_ZOOK_DLATCH (
     input [0:0] in_0,
     input [0:0] in_1,
     output [0:0] out_0
);

wire net_0 = in_0;
wire net_1 = in_1;

wire net_2;
wire net_3 = net_2;

assign out_0 = net_3;

f_Z00K00KKK LogicGate_0 (
.in_2(net_0),
.in_0(net_2),
.in_1(net_1),
.out_0(net_2)
);

endmodule
module f_2 (
     input wire in_0,
     output wire out_0
     );

     assign out_0 = (in_0 == 0);
endmodule
module f_22Z (
     input wire in_0,
     input wire in_1,
     output wire out_0
     );

     assign out_0 = (in_0 == 0 & in_1 == 0) | (in_0 == 0 & in_1 == 1) | (in_0 == 1 & in_1 == 0);
endmodule
module f_K00 (
     input wire in_0,
     input wire in_1,
     output wire out_0
     );

     assign out_0 = (in_0 == 1 & in_1 == 1);
endmodule
module f_Z00K00KKK (
     input wire in_0,
     input wire in_1,
     input wire in_2,
     output wire out_0
     );

     assign out_0 = (in_0 == 0 & in_1 == 1 & in_2 == 0) | (in_0 == 1 & in_1 == 1 & in_2 == 0) | (in_0 == 1 & in_1 == 0 & in_2 == 1) | (in_0 == 1 & in_1 == 1 & in_2 == 1);
endmodule
module alu_top (
	input [7:0] io_in,
	output [7:0] io_out
);
	
	alu alu(.A(io_in[7:6]), .B(io_in[5:4]), .ALU_Sel(io_in[3:0]), 
		.ALU_Out(io_out[6:0]), .CarryOut(io_out[7])
  );
	
endmodule
module user_module_349803790984020562(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7 = 1'b1;
  wire net8;
  wire net9 = 1'b0;
  wire net10;
  wire net11;
  wire net12;
  wire net13;
  wire net14;
  wire net15;
  wire net16;
  wire net17;
  wire net18;
  wire net19;
  wire net20;
  wire net21 = 1'b0;

  xor_cell gate11 (
    .a (net2),
    .b (net5),
    .out (net8)
  );
  xor_cell gate7 (
    .a (net8),
    .b (net10),
    .out (net11)
  );
  and_cell gate8 (
    .a (net8),
    .b (net10),
    .out (net12)
  );
  and_cell gate9 (
    .a (net2),
    .b (net5),
    .out (net13)
  );
  or_cell gate10 (
    .a (net12),
    .b (net13),
    .out (net14)
  );
  xor_cell gate1 (
    .a (net3),
    .b (net6),
    .out (net15)
  );
  xor_cell gate2 (
    .a (net15),
    .b (net14),
    .out (net16)
  );
  and_cell gate3 (
    .a (net15),
    .b (net14),
    .out (net17)
  );
  and_cell gate4 (
    .a (net3),
    .b (net6),
    .out (net18)
  );
  or_cell gate5 (
    .a (net17),
    .b (net18),
    .out (net19)
  );
  and_cell gate6 (
    .a (net1),
    .b (net4),
    .out (net10)
  );
  xor_cell gate12 (
    .a (net1),
    .b (net4),
    .out (net20)
  );
endmodule
module zoechip #( parameter MAX_COUNT = 1000 ) (
  input [7:0] io_in,
  output [7:0] io_out
);

wire A,B,C,D,F,G,M;
assign io_out = { 1'b0, D,B,G,F,M,C,A };

wire Z = io_in[0];
wire O = io_in[1];
wire E = io_in[2];
wire f = io_in[3];

assign A = Z+O+E;
assign B =O+E+f;
assign C =Z+O+f;
assign D =Z+O+E+f; 
assign F = E+Z;
assign G =E+Z;
assign M = f;
      
endmodule
module user_module_skylersaleh(
  input [7:0] io_in, 
  output [7:0] io_out
);

  hello_skylersaleh hello_core(
    .clk(io_in[0]),
    .dip_switch(io_in[7:1]),
    .segments(io_out[6:0]),
    .decimal(io_out[7])
  );

endmodule