dakies/OSS_Verilog huggingface dataset:
module bp_be_dcache_wbuf_queue_width_p97
(
  clk_i,
  data_i,
  el0_en_i,
  el1_en_i,
  mux0_sel_i,
  mux1_sel_i,
  el0_snoop_o,
  el1_snoop_o,
  data_o
);

  input [96:0] data_i;
  output [96:0] el0_snoop_o;
  output [96:0] el1_snoop_o;
  output [96:0] data_o;
  input clk_i;
  input el0_en_i;
  input el1_en_i;
  input mux0_sel_i;
  input mux1_sel_i;
  wire [96:0] data_o;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
  N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
  N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
  N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
  N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
  N102;
  reg [96:0] el0_snoop_o,el1_snoop_o;
  assign { N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5 } = (N0)? el0_snoop_o : 
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                (N1)? data_i : 1'b0;
  assign N0 = mux0_sel_i;
  assign N1 = N4;
  assign data_o = (N2)? el1_snoop_o : 
                  (N3)? data_i : 1'b0;
  assign N2 = mux1_sel_i;
  assign N3 = N102;
  assign N4 = ~mux0_sel_i;
  assign N102 = ~mux1_sel_i;

  always @(posedge clk_i) begin
    if(el0_en_i) begin
      { el0_snoop_o[96:0] } <= { data_i[96:0] };
    end 
    if(el1_en_i) begin
      { el1_snoop_o[96:0] } <= { N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5 };
    end 
  end


endmodule
module bsg_dff_width_p640
(
  clk_i,
  data_i,
  data_o
);

  input [639:0] data_i;
  output [639:0] data_o;
  input clk_i;
  reg [639:0] data_o;

  always @(posedge clk_i) begin
    if(1'b1) begin
      { data_o[639:0] } <= { data_i[639:0] };
    end 
  end


endmodule
module bsg_dff_reset_en_width_p8
(
  clk_i,
  reset_i,
  en_i,
  data_i,
  data_o
);

  input [7:0] data_i;
  output [7:0] data_o;
  input clk_i;
  input reset_i;
  input en_i;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13;
  reg [7:0] data_o;
  assign N3 = (N0)? 1'b1 : 
              (N13)? 1'b1 : 
              (N2)? 1'b0 : 1'b0;
  assign N0 = reset_i;
  assign { N11, N10, N9, N8, N7, N6, N5, N4 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 
                                                (N13)? data_i : 1'b0;
  assign N1 = en_i | reset_i;
  assign N2 = ~N1;
  assign N12 = ~reset_i;
  assign N13 = en_i & N12;

  always @(posedge clk_i) begin
    if(N3) begin
      { data_o[7:0] } <= { N11, N10, N9, N8, N7, N6, N5, N4 };
    end 
  end


endmodule
module bsg_dff_reset_en_width_p1
(
  clk_i,
  reset_i,
  en_i,
  data_i,
  data_o
);

  input [0:0] data_i;
  output [0:0] data_o;
  input clk_i;
  input reset_i;
  input en_i;
  wire N0,N1,N2,N3,N4,N5,N6;
  reg [0:0] data_o;
  assign N3 = (N0)? 1'b1 : 
              (N6)? 1'b1 : 
              (N2)? 1'b0 : 1'b0;
  assign N0 = reset_i;
  assign N4 = (N0)? 1'b0 : 
              (N6)? data_i[0] : 1'b0;
  assign N1 = en_i | reset_i;
  assign N2 = ~N1;
  assign N5 = ~reset_i;
  assign N6 = en_i & N5;

  always @(posedge clk_i) begin
    if(N3) begin
      { data_o[0:0] } <= { N4 };
    end 
  end


endmodule
module bsg_dff_width_p1890
(
  clk_i,
  data_i,
  data_o
);

  input [1889:0] data_i;
  output [1889:0] data_o;
  input clk_i;
  reg [1889:0] data_o;

  always @(posedge clk_i) begin
    if(1'b1) begin
      { data_o[1889:0] } <= { data_i[1889:0] };
    end 
  end


endmodule
module bsg_dff_width_p35
(
  clk_i,
  data_i,
  data_o
);

  input [34:0] data_i;
  output [34:0] data_o;
  input clk_i;
  reg [34:0] data_o;

  always @(posedge clk_i) begin
    if(1'b1) begin
      { data_o[34:0] } <= { data_i[34:0] };
    end 
  end


endmodule
module bsg_dff_reset_en_64_80000124
(
  clk_i,
  reset_i,
  en_i,
  data_i,
  data_o
);

  input [63:0] data_i;
  output [63:0] data_o;
  input clk_i;
  input reset_i;
  input en_i;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
  N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
  N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
  N62,N63,N64,N65,N66,N67,N68,N69;
  reg [63:0] data_o;
  assign N3 = (N0)? 1'b1 : 
              (N69)? 1'b1 : 
              (N2)? 1'b0 : 1'b0;
  assign N0 = reset_i;
  assign { N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } : 
                                                                                                                                                                                                                                                                                                                                        (N69)? data_i : 1'b0;
  assign N1 = en_i | reset_i;
  assign N2 = ~N1;
  assign N68 = ~reset_i;
  assign N69 = en_i & N68;

  always @(posedge clk_i) begin
    if(N3) begin
      { data_o[63:0] } <= { N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4 };
    end 
  end


endmodule
module Element(
  input         clock,
  input  [63:0] io_ins_down,
  input  [63:0] io_ins_right,
  input  [63:0] io_ins_up,
  input  [63:0] io_ins_left,
  output [63:0] io_outs_down,
  output [63:0] io_outs_right,
  output [63:0] io_outs_up,
  output [63:0] io_outs_left,
  input         io_lsbIns_1,
  input         io_lsbIns_2,
  input         io_lsbIns_3,
  input         io_lsbIns_4,
  input         io_lsbIns_5,
  input         io_lsbIns_6,
  input         io_lsbIns_7,
  output        io_lsbOuts_0,
  output        io_lsbOuts_1,
  output        io_lsbOuts_2,
  output        io_lsbOuts_3,
  output        io_lsbOuts_4,
  output        io_lsbOuts_5,
  output        io_lsbOuts_6,
  output        io_lsbOuts_7
);
  reg [63:0] REG;
  reg [63:0] REG_1;
  reg [63:0] REG_2;
  reg [63:0] REG_3;
  assign io_outs_down = REG_3;
  assign io_outs_right = REG_2;
  assign io_outs_up = REG_1;
  assign io_outs_left = REG;
  assign io_lsbOuts_0 = io_lsbIns_1;
  assign io_lsbOuts_1 = io_lsbIns_2;
  assign io_lsbOuts_2 = io_lsbIns_3;
  assign io_lsbOuts_3 = io_lsbIns_4;
  assign io_lsbOuts_4 = io_lsbIns_5;
  assign io_lsbOuts_5 = io_lsbIns_6;
  assign io_lsbOuts_6 = io_lsbIns_7;
  assign io_lsbOuts_7 = io_outs_left[0];
  always @(posedge clock) begin
    REG <= io_ins_down;
    REG_1 <= io_ins_right;
    REG_2 <= io_ins_up;
    REG_3 <= io_ins_left;
  end
endmodule
module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);


input Clk;
input Reset;
input [3:0] Data;
input Enable;
input Initialize;

output [31:0] Crc;
output CrcError;

reg  [31:0] Crc;

wire [31:0] CrcNext;


assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]); 
assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]); 
assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]); 
assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]); 
assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0]; 
assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1]; 
assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2]; 
assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3]; 
assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4]; 
assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5]; 
assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6]; 
assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7]; 
assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8]; 
assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9]; 
assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10]; 
assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11]; 
assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12]; 
assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13]; 
assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14]; 
assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15]; 
assign CrcNext[20] = Crc[16]; 
assign CrcNext[21] = Crc[17]; 
assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18]; 
assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19]; 
assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20]; 
assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21]; 
assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22]; 
assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23]; 
assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24]; 
assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25]; 
assign CrcNext[30] = Crc[26]; 
assign CrcNext[31] = Crc[27]; 


always @ (posedge Clk or posedge Reset)
begin
  if (Reset)
    Crc <=  32'hffffffff;
  else
  if(Initialize)
    Crc <=  32'hffffffff;
  else
    Crc <=  CrcNext;
end

assign CrcError = Crc[31:0] != 32'hc704dd7b;  // CRC not equal to magic number

endmodule
module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt, 
                   RandomEq0, RandomEqByteCnt);

input MTxClk;
input Reset;
input StateJam;
input StateJam_q;
input [3:0] RetryCnt;
input [15:0] NibCnt;
input [9:0] ByteCnt;
output RandomEq0;
output RandomEqByteCnt;

wire Feedback;
reg [9:0] x;
wire [9:0] Random;
reg  [9:0] RandomLatched;


always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    x[9:0] <=  0;
  else
    x[9:0] <=  {x[8:0], Feedback};
end

assign Feedback = ~(x[2] ^ x[9]);

assign Random [0] = x[0];
assign Random [1] = (RetryCnt > 1) ? x[1] : 1'b0;
assign Random [2] = (RetryCnt > 2) ? x[2] : 1'b0;
assign Random [3] = (RetryCnt > 3) ? x[3] : 1'b0;
assign Random [4] = (RetryCnt > 4) ? x[4] : 1'b0;
assign Random [5] = (RetryCnt > 5) ? x[5] : 1'b0;
assign Random [6] = (RetryCnt > 6) ? x[6] : 1'b0;
assign Random [7] = (RetryCnt > 7) ? x[7] : 1'b0;
assign Random [8] = (RetryCnt > 8) ? x[8] : 1'b0;
assign Random [9] = (RetryCnt > 9) ? x[9] : 1'b0;


always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    RandomLatched <=  10'h000;
  else
    begin
      if(StateJam & StateJam_q)
        RandomLatched <=  Random;
    end
end

// Random Number == 0      IEEE 802.3 page 68. If 0 we go to defer and not to backoff.
assign RandomEq0 = RandomLatched == 10'h0; 

assign RandomEqByteCnt = ByteCnt[9:0] == RandomLatched & (&NibCnt[6:0]);

endmodule
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);

input       Clk;              // Input clock (Host clock)
input       Reset;            // Reset signal
input [7:0] Divider;          // Divider (input clock will be divided by the Divider[7:0])

output      Mdc;              // Output clock
output      MdcEn;            // Enable signal is asserted for one Clk period before Mdc rises.
output      MdcEn_n;          // Enable signal is asserted for one Clk period before Mdc falls.

reg         Mdc;
reg   [7:0] Counter;

wire        CountEq0;
wire  [7:0] CounterPreset;
wire  [7:0] TempDivider;


assign TempDivider[7:0]   = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1;           // We are counting half of period


// Counter counts half period
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    Counter[7:0] <=  8'h1;
  else
    begin
      if(CountEq0)
        begin
          Counter[7:0] <=  CounterPreset[7:0];
        end
      else
        Counter[7:0] <=  Counter - 8'h1;
    end
end


// Mdc is asserted every other half period
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    Mdc <=  1'b0;
  else
    begin
      if(CountEq0)
        Mdc <=  ~Mdc;
    end
end


assign CountEq0 = Counter == 8'h0;
assign MdcEn = CountEq0 & ~Mdc;
assign MdcEn_n = CountEq0 & Mdc;

endmodule
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect, 
                    LatchByte, ShiftedBit, Prsd, LinkFail);


input       Clk;              // Input clock (Host clock)
input       Reset;            // Reset signal
input       MdcEn_n;          // Enable signal is asserted for one Clk period before Mdc falls.
input       Mdi;              // MII input data
input [4:0] Fiad;             // PHY address
input [4:0] Rgad;             // Register address (within the selected PHY)
input [15:0]CtrlData;         // Control data (data to be written to the PHY)
input       WriteOp;          // The current operation is a PHY register write operation
input [3:0] ByteSelect;       // Byte select
input [1:0] LatchByte;        // Byte select for latching (read operation)

output      ShiftedBit;       // Bit shifted out of the shift register
output[15:0]Prsd;             // Read Status Data (data read from the PHY)
output      LinkFail;         // Link Integrity Signal

reg   [7:0] ShiftReg;         // Shift register for shifting the data in and out
reg   [15:0]Prsd;
reg         LinkFail;




// ShiftReg[7:0] :: Shift Register Data
always @ (posedge Clk or posedge Reset) 
begin
  if(Reset)
    begin
      ShiftReg[7:0] <=  8'h0;
      Prsd[15:0] <=  16'h0;
      LinkFail <=  1'b0;
    end
  else
    begin
      if(MdcEn_n)
        begin 
          if(|ByteSelect)
            begin
	       /* verilator lint_off CASEINCOMPLETE */
              /*case (ByteSelect[3:0])  // synopsys parallel_case full_case*/
              case (ByteSelect[3:0])  
                4'h1 :    ShiftReg[7:0] <=  {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
                4'h2 :    ShiftReg[7:0] <=  {Fiad[0], Rgad[4:0], 2'b10};
                4'h4 :    ShiftReg[7:0] <=  CtrlData[15:8];
                4'h8 :    ShiftReg[7:0] <=  CtrlData[7:0];
              endcase // case (ByteSelect[3:0])
	       /* verilator lint_on CASEINCOMPLETE */
            end 
          else
            begin
              ShiftReg[7:0] <=  {ShiftReg[6:0], Mdi};
              if(LatchByte[0])
                begin
                  Prsd[7:0] <=  {ShiftReg[6:0], Mdi};
                  if(Rgad == 5'h01)
                    LinkFail <=  ~ShiftReg[1];  // this is bit [2], because it is not shifted yet
                end
              else
                begin
                  if(LatchByte[1])
                    Prsd[15:8] <=  {ShiftReg[6:0], Mdi};
                end
            end
        end
    end
end


assign ShiftedBit = ShiftReg[7];


endmodule
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);

input         Clk;                // Host Clock
input         Reset;              // General Reset
input         WriteOp;            // Write Operation Latch (When asserted, write operation is in progress)
input         NoPre;              // No Preamble (no 32-bit preamble)
input         InProgress;         // Operation in progress
input         ShiftedBit;         // This bit is output of the shift register and is connected to the Mdo signal
input   [6:0] BitCounter;         // Bit Counter
input         MdcEn_n;            // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.

output        Mdo;                // MII Management Data Output
output        MdoEn;              // MII Management Data Output Enable

wire          SerialEn;

reg           MdoEn_2d;
reg           MdoEn_d;
reg           MdoEn;

reg           Mdo_2d;
reg           Mdo_d;
reg           Mdo;                // MII Management Data Output



// Generation of the Serial Enable signal (enables the serialization of the data)
assign SerialEn =  WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
                | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));


// Generation of the MdoEn signal
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    begin
      MdoEn_2d <=  1'b0;
      MdoEn_d <=  1'b0;
      MdoEn <=  1'b0;
    end
  else
    begin
      if(MdcEn_n)
        begin
          MdoEn_2d <=  SerialEn | InProgress & BitCounter<32;
          MdoEn_d <=  MdoEn_2d;
          MdoEn <=  MdoEn_d;
        end
    end
end


// Generation of the Mdo signal.
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    begin
      Mdo_2d <=  1'b0;
      Mdo_d <=  1'b0;
      Mdo <=  1'b0;
    end
  else
    begin
      if(MdcEn_n)
        begin
          Mdo_2d <=  ~SerialEn & BitCounter<32;
          Mdo_d <=  ShiftedBit | Mdo_2d;
          Mdo <=  Mdo_d;
        end
    end
end



endmodule
module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD, 
                     IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD, 
                     StateDrop
                    );

input         MRxClk;
input         Reset;
input         MRxDV;
input         ByteCntEq0;
input         ByteCntGreat2;
input         MRxDEq5;
input         Transmitting;
input         MRxDEqD;
input         IFGCounterEq24;
input         ByteCntMaxFrame;

output [1:0]  StateData;
output        StateIdle;
output        StateDrop;
output        StatePreamble;
output        StateSFD;

reg           StateData0;
reg           StateData1;
reg           StateIdle;
reg           StateDrop;
reg           StatePreamble;
reg           StateSFD;

wire          StartIdle;
wire          StartDrop;
wire          StartData0;
wire          StartData1;
wire          StartPreamble;
wire          StartSFD;


// Defining the next state
assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData));

assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);

assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble);

assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1);

assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame);

assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 &
                   MRxDEqD |  StateData0 &  ByteCntMaxFrame);

// Rx State Machine
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    begin
      StateIdle     <=  1'b0;
      StateDrop     <=  1'b1;
      StatePreamble <=  1'b0;
      StateSFD      <=  1'b0;
      StateData0    <=  1'b0;
      StateData1    <=  1'b0;
    end
  else
    begin
      if(StartPreamble | StartSFD | StartDrop)
        StateIdle <=  1'b0;
      else
      if(StartIdle)
        StateIdle <=  1'b1;

      if(StartIdle)
        StateDrop <=  1'b0;
      else
      if(StartDrop)
        StateDrop <=  1'b1;

      if(StartSFD | StartIdle | StartDrop)
        StatePreamble <=  1'b0;
      else
      if(StartPreamble)
        StatePreamble <=  1'b1;

      if(StartPreamble | StartIdle | StartData0 | StartDrop)
        StateSFD <=  1'b0;
      else
      if(StartSFD)
        StateSFD <=  1'b1;

      if(StartIdle | StartData1 | StartDrop)
        StateData0 <=  1'b0;
      else
      if(StartData0)
        StateData0 <=  1'b1;

      if(StartIdle | StartData0 | StartDrop)
        StateData1 <=  1'b0;
      else
      if(StartData1)
        StateData1 <=  1'b1;
    end
end

assign StateData[1:0] = {StateData1, StateData0};

endmodule
module ROM (clk, en, address, instr);

   input wire [30:0] address;   
   input wire         clk;
   input wire 	      en;

   output wire [31:0] instr;

   assign instr = (address == 31'h0000_0000) ? 32'h8000_0337 :
                  (address == 31'h0000_0004) ? 32'h0003_03E7 :
                  32'h0000_0000;
   
   //always_ff @(posedge clk)
   //always@(*)
   //  if (en)
   //    begin
   //   	  case (address)
   //   	    //{31'h0}: instr <= 32'h37030080;	    
   //   	    {31'h0}: instr <= 32'h80000337;	    
   //   	    //{31'h4}: instr <= 32'hE7030300;
   //   	    {31'h4}: instr <= 32'h000303E7;
   //   	    default: instr <= 32'h0;
   //   	  endcase // case (address)	  	    
   //    end

endmodule
module random(clk, data, raw, err);
  input clk;
  wire clk;
  output [63:0] data;
  wire [63:0] data;
  output err;
  wire err;
  output [63:0] raw;
  wire [63:0] raw;
  assign data = 64'hffffffffffffffff;
  assign raw = 64'hffffffffffffffff;
  assign err = 1'h1;
endmodule
module cr_file_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, \d_in.read , \w_in.write_cr_enable , \w_in.write_cr_mask , \w_in.write_cr_data , \w_in.write_xerc_enable , \w_in.write_xerc_data , sim_dump, \d_out.read_cr_data , \d_out.read_xerc_data , log_out);
  wire [3:0] _00_;
  wire [3:0] _01_;
  wire [3:0] _02_;
  wire [3:0] _03_;
  wire [3:0] _04_;
  wire [3:0] _05_;
  wire [3:0] _06_;
  wire [3:0] _07_;
  wire [4:0] _08_;
  wire [31:0] _09_;
  reg [31:0] _10_ = 32'd0;
  wire [4:0] _11_;
  reg [4:0] _12_ = 5'h00;
  input clk;
  wire clk;
  wire [31:0] crs;
  wire [31:0] crs_updated;
  input \d_in.read ;
  wire \d_in.read ;
  output [31:0] \d_out.read_cr_data ;
  wire [31:0] \d_out.read_cr_data ;
  output [4:0] \d_out.read_xerc_data ;
  wire [4:0] \d_out.read_xerc_data ;
  output [12:0] log_out;
  wire [12:0] log_out;
  input sim_dump;
  wire sim_dump;
  input [31:0] \w_in.write_cr_data ;
  wire [31:0] \w_in.write_cr_data ;
  input \w_in.write_cr_enable ;
  wire \w_in.write_cr_enable ;
  input [7:0] \w_in.write_cr_mask ;
  wire [7:0] \w_in.write_cr_mask ;
  input [4:0] \w_in.write_xerc_data ;
  wire [4:0] \w_in.write_xerc_data ;
  input \w_in.write_xerc_enable ;
  wire \w_in.write_xerc_enable ;
  wire [4:0] xerc;
  wire [4:0] xerc_updated;
  assign _00_ = \w_in.write_cr_mask [0] ? \w_in.write_cr_data [3:0] : crs[3:0];
  assign _01_ = \w_in.write_cr_mask [1] ? \w_in.write_cr_data [7:4] : crs[7:4];
  assign _02_ = \w_in.write_cr_mask [2] ? \w_in.write_cr_data [11:8] : crs[11:8];
  assign _03_ = \w_in.write_cr_mask [3] ? \w_in.write_cr_data [15:12] : crs[15:12];
  assign _04_ = \w_in.write_cr_mask [4] ? \w_in.write_cr_data [19:16] : crs[19:16];
  assign _05_ = \w_in.write_cr_mask [5] ? \w_in.write_cr_data [23:20] : crs[23:20];
  assign _06_ = \w_in.write_cr_mask [6] ? \w_in.write_cr_data [27:24] : crs[27:24];
  assign _07_ = \w_in.write_cr_mask [7] ? \w_in.write_cr_data [31:28] : crs[31:28];
  assign _08_ = \w_in.write_xerc_enable  ? \w_in.write_xerc_data  : xerc;
  assign _09_ = \w_in.write_cr_enable  ? crs_updated : crs;
  always @(posedge clk)
    _10_ <= _09_;
  assign _11_ = \w_in.write_xerc_enable  ? xerc_updated : xerc;
  always @(posedge clk)
    _12_ <= _11_;
  assign crs = _10_;
  assign crs_updated = { _07_, _06_, _05_, _04_, _03_, _02_, _01_, _00_ };
  assign xerc = _12_;
  assign xerc_updated = _08_;
  assign \d_out.read_cr_data  = crs_updated;
  assign \d_out.read_xerc_data  = xerc_updated;
  assign log_out = 13'hzzzz;
endmodule
module Arbiter_2
(
  io_in_3_ready,
  io_in_3_valid,
  io_in_3_bits_way_en,
  io_in_3_bits_addr,
  io_in_2_ready,
  io_in_2_valid,
  io_in_2_bits_way_en,
  io_in_2_bits_addr,
  io_in_1_ready,
  io_in_1_valid,
  io_in_1_bits_way_en,
  io_in_1_bits_addr,
  io_in_0_ready,
  io_in_0_valid,
  io_in_0_bits_way_en,
  io_in_0_bits_addr,
  io_out_ready,
  io_out_valid,
  io_out_bits_way_en,
  io_out_bits_addr,
  io_chosen
);

  input [3:0] io_in_3_bits_way_en;
  input [11:0] io_in_3_bits_addr;
  input [3:0] io_in_2_bits_way_en;
  input [11:0] io_in_2_bits_addr;
  input [3:0] io_in_1_bits_way_en;
  input [11:0] io_in_1_bits_addr;
  input [3:0] io_in_0_bits_way_en;
  input [11:0] io_in_0_bits_addr;
  output [3:0] io_out_bits_way_en;
  output [11:0] io_out_bits_addr;
  output [1:0] io_chosen;
  input io_in_3_valid;
  input io_in_2_valid;
  input io_in_1_valid;
  input io_in_0_valid;
  input io_out_ready;
  output io_in_3_ready;
  output io_in_2_ready;
  output io_in_1_ready;
  output io_in_0_ready;
  output io_out_valid;
  wire [3:0] io_out_bits_way_en,T12,T10;
  wire [11:0] io_out_bits_addr,T6,T3;
  wire [1:0] io_chosen,T0;
  wire io_in_3_ready,io_in_2_ready,io_in_1_ready,io_in_0_ready,io_out_valid,N0,N1,N2,
  N3,N4,N5,N6,N7,io_out_ready,N8,N9,N10,N11,N12,T18,T16,T22,T24,T25,T27,T28,T29;
  wire [0:0] T1;
  assign io_in_0_ready = io_out_ready;
  assign io_chosen = (N0)? { 1'b0, 1'b0 } : 
                     (N1)? T0 : 1'b0;
  assign N0 = io_in_0_valid;
  assign N1 = N8;
  assign T0[0] = (N2)? 1'b1 : 
                 (N3)? T1[0] : 1'b0;
  assign N2 = io_in_1_valid;
  assign N3 = T0[1];
  assign io_out_bits_addr = (N4)? T6 : 
                            (N5)? T3 : 1'b0;
  assign N4 = io_chosen[1];
  assign N5 = N11;
  assign T3 = (N6)? io_in_1_bits_addr : 
              (N7)? io_in_0_bits_addr : 1'b0;
  assign N6 = io_chosen[0];
  assign N7 = N12;
  assign T6 = (N6)? io_in_3_bits_addr : 
              (N7)? io_in_2_bits_addr : 1'b0;
  assign io_out_bits_way_en = (N4)? T12 : 
                              (N5)? T10 : 1'b0;
  assign T10 = (N6)? io_in_1_bits_way_en : 
               (N7)? io_in_0_bits_way_en : 1'b0;
  assign T12 = (N6)? io_in_3_bits_way_en : 
               (N7)? io_in_2_bits_way_en : 1'b0;
  assign io_out_valid = (N4)? T18 : 
                        (N5)? T16 : 1'b0;
  assign T16 = (N6)? io_in_1_valid : 
               (N7)? io_in_0_valid : 1'b0;
  assign T18 = (N6)? io_in_3_valid : 
               (N7)? io_in_2_valid : 1'b0;
  assign N8 = ~io_in_0_valid;
  assign N9 = ~io_in_1_valid;
  assign T0[1] = N9;
  assign N10 = ~io_in_2_valid;
  assign T1[0] = N10;
  assign N11 = ~io_chosen[1];
  assign N12 = ~io_chosen[0];
  assign io_in_1_ready = T22 & io_out_ready;
  assign T22 = ~io_in_0_valid;
  assign io_in_2_ready = T24 & io_out_ready;
  assign T24 = ~T25;
  assign T25 = io_in_0_valid | io_in_1_valid;
  assign io_in_3_ready = T27 & io_out_ready;
  assign T27 = ~T28;
  assign T28 = T29 | io_in_2_valid;
  assign T29 = io_in_0_valid | io_in_1_valid;

endmodule
module Arbiter_7
(
  io_in_1_ready,
  io_in_1_valid,
  io_in_1_bits_idx,
  io_in_1_bits_tag,
  io_in_0_ready,
  io_in_0_valid,
  io_in_0_bits_idx,
  io_in_0_bits_tag,
  io_out_ready,
  io_out_valid,
  io_out_bits_idx,
  io_out_bits_tag,
  io_chosen
);

  input [5:0] io_in_1_bits_idx;
  input [19:0] io_in_1_bits_tag;
  input [5:0] io_in_0_bits_idx;
  input [19:0] io_in_0_bits_tag;
  output [5:0] io_out_bits_idx;
  output [19:0] io_out_bits_tag;
  input io_in_1_valid;
  input io_in_0_valid;
  input io_out_ready;
  output io_in_1_ready;
  output io_in_0_ready;
  output io_out_valid;
  output io_chosen;
  wire [5:0] io_out_bits_idx;
  wire [19:0] io_out_bits_tag;
  wire io_in_1_ready,io_in_0_ready,io_out_valid,io_chosen,N0,N1,io_out_ready,T5;
  assign io_in_0_ready = io_out_ready;
  assign io_chosen = ~io_in_0_valid;
  assign io_out_bits_tag = (N0)? io_in_1_bits_tag : 
                           (N1)? io_in_0_bits_tag : 1'b0;
  assign N0 = io_chosen;
  assign N1 = io_in_0_valid;
  assign io_out_bits_idx = (N0)? io_in_1_bits_idx : 
                           (N1)? io_in_0_bits_idx : 1'b0;
  assign io_out_valid = (N0)? io_in_1_valid : 
                        (N1)? io_in_0_valid : 1'b0;
  assign io_in_1_ready = T5 & io_out_ready;
  assign T5 = ~io_in_0_valid;

endmodule
module CompareRecFN
(
  io_a,
  io_b,
  io_signaling,
  io_lt,
  io_eq,
  io_gt,
  io_exceptionFlags
);

  input [64:0] io_a;
  input [64:0] io_b;
  output [4:0] io_exceptionFlags;
  input io_signaling;
  output io_lt;
  output io_eq;
  output io_gt;
  wire [4:0] io_exceptionFlags;
  wire io_lt,io_eq,io_gt,N0,T15,T1,T2,ordered,T9,T3,rawB_isNaN,rawA_isNaN,T22,T16,T17,
  T23,T50,T29,ordered_eq,bothZeros,T30,T43,T31,bothInfs,common_eqMags,eqExps,T32,
  rawA_isInf,rawB_isInf,T38,T41,T51,ordered_lt,T67,T52,T65,T53,T64,T54,T60,T55,T59,
  common_ltMags,T58,T56,T57,T62,T61,T63,T66,N1,N2,N3,N4,N5,N6,N7,N8;
  assign io_exceptionFlags[0] = 1'b0;
  assign io_exceptionFlags[1] = 1'b0;
  assign io_exceptionFlags[2] = 1'b0;
  assign io_exceptionFlags[3] = 1'b0;
  assign T32 = { 1'b0, 1'b1, io_a[51:0], 1'b0, 1'b0 } == { 1'b0, 1'b1, io_b[51:0], 1'b0, 1'b0 };
  assign eqExps = { 1'b0, io_a[63:52] } == { 1'b0, io_b[63:52] };
  assign N0 = io_a[64] ^ io_b[64];
  assign T43 = ~N0;
  assign T57 = { 1'b0, 1'b1, io_a[51:0], 1'b0, 1'b0 } < { 1'b0, 1'b1, io_b[51:0], 1'b0, 1'b0 };
  assign T58 = $signed({ 1'b0, io_a[63:52] }) < $signed({ 1'b0, io_b[63:52] });
  assign N1 = io_a[62] | io_a[63];
  assign N2 = io_a[61] | N1;
  assign N3 = ~N2;
  assign N4 = io_b[62] | io_b[63];
  assign N5 = io_b[61] | N4;
  assign N6 = ~N5;
  assign N7 = io_a[62] & io_a[63];
  assign N8 = io_b[62] & io_b[63];
  assign io_exceptionFlags[4] = T15 | T1;
  assign T1 = io_signaling & T2;
  assign T2 = ~ordered;
  assign ordered = T9 & T3;
  assign T3 = ~rawB_isNaN;
  assign rawB_isNaN = N8 & io_b[61];
  assign T9 = ~rawA_isNaN;
  assign rawA_isNaN = N7 & io_a[61];
  assign T15 = T22 | T16;
  assign T16 = rawB_isNaN & T17;
  assign T17 = ~io_b[51];
  assign T22 = rawA_isNaN & T23;
  assign T23 = ~io_a[51];
  assign io_gt = T50 & T29;
  assign T29 = ~ordered_eq;
  assign ordered_eq = bothZeros | T30;
  assign T30 = T43 & T31;
  assign T31 = bothInfs | common_eqMags;
  assign common_eqMags = eqExps & T32;
  assign bothInfs = rawA_isInf & rawB_isInf;
  assign rawB_isInf = N8 & T38;
  assign T38 = ~io_b[61];
  assign rawA_isInf = N7 & T41;
  assign T41 = ~io_a[61];
  assign bothZeros = N3 & N6;
  assign T50 = ordered & T51;
  assign T51 = ~ordered_lt;
  assign ordered_lt = T67 & T52;
  assign T52 = T65 | T53;
  assign T53 = T64 & T54;
  assign T54 = T60 | T55;
  assign T55 = T59 & common_ltMags;
  assign common_ltMags = T58 | T56;
  assign T56 = eqExps & T57;
  assign T59 = ~io_b[64];
  assign T60 = T62 & T61;
  assign T61 = ~common_eqMags;
  assign T62 = io_a[64] & T63;
  assign T63 = ~common_ltMags;
  assign T64 = ~bothInfs;
  assign T65 = io_a[64] & T66;
  assign T66 = ~io_b[64];
  assign T67 = ~bothZeros;
  assign io_eq = ordered & ordered_eq;
  assign io_lt = ordered & ordered_lt;

endmodule
module Arbiter_8
(
  io_in_1_ready,
  io_in_1_valid,
  io_in_1_bits_addr,
  io_in_1_bits_tag,
  io_in_1_bits_cmd,
  io_in_1_bits_typ,
  io_in_1_bits_kill,
  io_in_1_bits_phys,
  io_in_1_bits_sdq_id,
  io_in_0_ready,
  io_in_0_valid,
  io_in_0_bits_addr,
  io_in_0_bits_tag,
  io_in_0_bits_cmd,
  io_in_0_bits_typ,
  io_in_0_bits_kill,
  io_in_0_bits_phys,
  io_in_0_bits_sdq_id,
  io_out_ready,
  io_out_valid,
  io_out_bits_addr,
  io_out_bits_tag,
  io_out_bits_cmd,
  io_out_bits_typ,
  io_out_bits_kill,
  io_out_bits_phys,
  io_out_bits_sdq_id,
  io_chosen
);

  input [39:0] io_in_1_bits_addr;
  input [9:0] io_in_1_bits_tag;
  input [4:0] io_in_1_bits_cmd;
  input [2:0] io_in_1_bits_typ;
  input [4:0] io_in_1_bits_sdq_id;
  input [39:0] io_in_0_bits_addr;
  input [9:0] io_in_0_bits_tag;
  input [4:0] io_in_0_bits_cmd;
  input [2:0] io_in_0_bits_typ;
  input [4:0] io_in_0_bits_sdq_id;
  output [39:0] io_out_bits_addr;
  output [9:0] io_out_bits_tag;
  output [4:0] io_out_bits_cmd;
  output [2:0] io_out_bits_typ;
  output [4:0] io_out_bits_sdq_id;
  input io_in_1_valid;
  input io_in_1_bits_kill;
  input io_in_1_bits_phys;
  input io_in_0_valid;
  input io_in_0_bits_kill;
  input io_in_0_bits_phys;
  input io_out_ready;
  output io_in_1_ready;
  output io_in_0_ready;
  output io_out_valid;
  output io_out_bits_kill;
  output io_out_bits_phys;
  output io_chosen;
  wire [39:0] io_out_bits_addr;
  wire [9:0] io_out_bits_tag;
  wire [4:0] io_out_bits_cmd,io_out_bits_sdq_id;
  wire [2:0] io_out_bits_typ;
  wire io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_kill,io_out_bits_phys,
  io_chosen,N0,N1,io_out_ready,T10;
  assign io_in_0_ready = io_out_ready;
  assign io_chosen = ~io_in_0_valid;
  assign io_out_bits_sdq_id = (N0)? io_in_1_bits_sdq_id : 
                              (N1)? io_in_0_bits_sdq_id : 1'b0;
  assign N0 = io_chosen;
  assign N1 = io_in_0_valid;
  assign io_out_bits_phys = (N0)? io_in_1_bits_phys : 
                            (N1)? io_in_0_bits_phys : 1'b0;
  assign io_out_bits_kill = (N0)? io_in_1_bits_kill : 
                            (N1)? io_in_0_bits_kill : 1'b0;
  assign io_out_bits_typ = (N0)? io_in_1_bits_typ : 
                           (N1)? io_in_0_bits_typ : 1'b0;
  assign io_out_bits_cmd = (N0)? io_in_1_bits_cmd : 
                           (N1)? io_in_0_bits_cmd : 1'b0;
  assign io_out_bits_tag = (N0)? io_in_1_bits_tag : 
                           (N1)? io_in_0_bits_tag : 1'b0;
  assign io_out_bits_addr = (N0)? io_in_1_bits_addr : 
                            (N1)? io_in_0_bits_addr : 1'b0;
  assign io_out_valid = (N0)? io_in_1_valid : 
                        (N1)? io_in_0_valid : 1'b0;
  assign io_in_1_ready = T10 & io_out_ready;
  assign T10 = ~io_in_0_valid;

endmodule
module RRArbiter_1
(
  clk,
  reset,
  io_in_1_ready,
  io_in_1_valid,
  io_in_1_bits_rw,
  io_in_1_bits_addr,
  io_in_1_bits_data,
  io_in_0_ready,
  io_in_0_valid,
  io_in_0_bits_rw,
  io_in_0_bits_addr,
  io_in_0_bits_data,
  io_out_ready,
  io_out_valid,
  io_out_bits_rw,
  io_out_bits_addr,
  io_out_bits_data,
  io_chosen
);

  input [11:0] io_in_1_bits_addr;
  input [63:0] io_in_1_bits_data;
  input [11:0] io_in_0_bits_addr;
  input [63:0] io_in_0_bits_data;
  output [11:0] io_out_bits_addr;
  output [63:0] io_out_bits_data;
  input clk;
  input reset;
  input io_in_1_valid;
  input io_in_1_bits_rw;
  input io_in_0_valid;
  input io_in_0_bits_rw;
  input io_out_ready;
  output io_in_1_ready;
  output io_in_0_ready;
  output io_out_valid;
  output io_out_bits_rw;
  output io_chosen;
  wire [11:0] io_out_bits_addr;
  wire [63:0] io_out_bits_data;
  wire io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_rw,io_chosen,N0,N1,N2,N3,
  N4,N5,N6,T1,N7,T2,T4,N8,T11,T18,T12,T13,T16,T14,T15,T17,T20,T24,T21,T22,T23,T26,
  T25,N9,N10,N11,N12,N13,N14,N15;
  reg last_grant;
  assign T17 = N0 & 1'b0;
  assign N0 = ~last_grant;
  assign T18 = N1 & 1'b0;
  assign N1 = ~last_grant;

  always @(posedge clk) begin
    if(N11) begin
      last_grant <= N12;
    end 
  end

  assign N15 = ~io_in_0_valid;
  assign io_chosen = (N2)? 1'b1 : 
                     (N3)? N15 : 1'b0;
  assign N2 = T1;
  assign N3 = N7;
  assign io_out_bits_data = (N4)? io_in_1_bits_data : 
                            (N5)? io_in_0_bits_data : 1'b0;
  assign N4 = io_chosen;
  assign N5 = N8;
  assign io_out_bits_addr = (N4)? io_in_1_bits_addr : 
                            (N5)? io_in_0_bits_addr : 1'b0;
  assign io_out_bits_rw = (N4)? io_in_1_bits_rw : 
                          (N5)? io_in_0_bits_rw : 1'b0;
  assign io_out_valid = (N4)? io_in_1_valid : 
                        (N5)? io_in_0_valid : 1'b0;
  assign N11 = (N6)? 1'b1 : 
               (N14)? 1'b1 : 
               (N10)? 1'b0 : 1'b0;
  assign N6 = reset;
  assign N12 = (N6)? 1'b0 : 
               (N14)? io_chosen : 1'b0;
  assign N7 = ~T1;
  assign T1 = io_in_1_valid & T2;
  assign T2 = ~last_grant;
  assign T4 = io_out_ready & io_out_valid;
  assign N8 = ~io_chosen;
  assign io_in_0_ready = T11 & io_out_ready;
  assign T11 = T18 | T12;
  assign T12 = ~T13;
  assign T13 = T16 | T14;
  assign T14 = io_in_1_valid & T15;
  assign T15 = ~last_grant;
  assign T16 = io_in_0_valid & T17;
  assign io_in_1_ready = T20 & io_out_ready;
  assign T20 = T24 | T21;
  assign T21 = ~T22;
  assign T22 = T23 | io_in_0_valid;
  assign T23 = T16 | T14;
  assign T24 = T26 & T25;
  assign T25 = ~last_grant;
  assign T26 = ~T16;
  assign N9 = T4 | reset;
  assign N10 = ~N9;
  assign N13 = ~reset;
  assign N14 = T4 & N13;

endmodule
module Arbiter_4
(
  io_in_1_ready,
  io_in_1_valid,
  io_in_1_bits_addr_beat,
  io_in_1_bits_addr_block,
  io_in_1_bits_client_xact_id,
  io_in_1_bits_voluntary,
  io_in_1_bits_r_type,
  io_in_1_bits_data,
  io_in_1_bits_way_en,
  io_in_0_ready,
  io_in_0_valid,
  io_in_0_bits_addr_beat,
  io_in_0_bits_addr_block,
  io_in_0_bits_client_xact_id,
  io_in_0_bits_voluntary,
  io_in_0_bits_r_type,
  io_in_0_bits_data,
  io_in_0_bits_way_en,
  io_out_ready,
  io_out_valid,
  io_out_bits_addr_beat,
  io_out_bits_addr_block,
  io_out_bits_client_xact_id,
  io_out_bits_voluntary,
  io_out_bits_r_type,
  io_out_bits_data,
  io_out_bits_way_en,
  io_chosen
);

  input [1:0] io_in_1_bits_addr_beat;
  input [25:0] io_in_1_bits_addr_block;
  input [5:0] io_in_1_bits_client_xact_id;
  input [2:0] io_in_1_bits_r_type;
  input [127:0] io_in_1_bits_data;
  input [3:0] io_in_1_bits_way_en;
  input [1:0] io_in_0_bits_addr_beat;
  input [25:0] io_in_0_bits_addr_block;
  input [5:0] io_in_0_bits_client_xact_id;
  input [2:0] io_in_0_bits_r_type;
  input [127:0] io_in_0_bits_data;
  input [3:0] io_in_0_bits_way_en;
  output [1:0] io_out_bits_addr_beat;
  output [25:0] io_out_bits_addr_block;
  output [5:0] io_out_bits_client_xact_id;
  output [2:0] io_out_bits_r_type;
  output [127:0] io_out_bits_data;
  output [3:0] io_out_bits_way_en;
  input io_in_1_valid;
  input io_in_1_bits_voluntary;
  input io_in_0_valid;
  input io_in_0_bits_voluntary;
  input io_out_ready;
  output io_in_1_ready;
  output io_in_0_ready;
  output io_out_valid;
  output io_out_bits_voluntary;
  output io_chosen;
  wire [1:0] io_out_bits_addr_beat;
  wire [25:0] io_out_bits_addr_block;
  wire [5:0] io_out_bits_client_xact_id;
  wire [2:0] io_out_bits_r_type;
  wire [127:0] io_out_bits_data;
  wire [3:0] io_out_bits_way_en;
  wire io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_voluntary,io_chosen,N0,N1,
  io_out_ready,T10;
  assign io_in_0_ready = io_out_ready;
  assign io_chosen = ~io_in_0_valid;
  assign io_out_bits_way_en = (N0)? io_in_1_bits_way_en : 
                              (N1)? io_in_0_bits_way_en : 1'b0;
  assign N0 = io_chosen;
  assign N1 = io_in_0_valid;
  assign io_out_bits_data = (N0)? io_in_1_bits_data : 
                            (N1)? io_in_0_bits_data : 1'b0;
  assign io_out_bits_r_type = (N0)? io_in_1_bits_r_type : 
                              (N1)? io_in_0_bits_r_type : 1'b0;
  assign io_out_bits_voluntary = (N0)? io_in_1_bits_voluntary : 
                                 (N1)? io_in_0_bits_voluntary : 1'b0;
  assign io_out_bits_client_xact_id = (N0)? io_in_1_bits_client_xact_id : 
                                      (N1)? io_in_0_bits_client_xact_id : 1'b0;
  assign io_out_bits_addr_block = (N0)? io_in_1_bits_addr_block : 
                                  (N1)? io_in_0_bits_addr_block : 1'b0;
  assign io_out_bits_addr_beat = (N0)? io_in_1_bits_addr_beat : 
                                 (N1)? io_in_0_bits_addr_beat : 1'b0;
  assign io_out_valid = (N0)? io_in_1_valid : 
                        (N1)? io_in_0_valid : 1'b0;
  assign io_in_1_ready = T10 & io_out_ready;
  assign T10 = ~io_in_0_valid;

endmodule
module Arbiter_10
(
  io_in_0_ready,
  io_in_0_valid,
  io_in_0_bits,
  io_out_ready,
  io_out_valid,
  io_out_bits,
  io_chosen
);

  input io_in_0_valid;
  input io_in_0_bits;
  input io_out_ready;
  output io_in_0_ready;
  output io_out_valid;
  output io_out_bits;
  output io_chosen;
  wire io_in_0_ready,io_out_valid,io_out_bits,io_chosen,io_out_ready,io_in_0_valid,
  io_in_0_bits;
  assign io_chosen = 1'b0;
  assign io_in_0_ready = io_out_ready;
  assign io_out_valid = io_in_0_valid;
  assign io_out_bits = io_in_0_bits;

endmodule
module Arbiter_9
(
  io_in_1_ready,
  io_in_1_valid,
  io_in_1_bits,
  io_in_0_ready,
  io_in_0_valid,
  io_in_0_bits,
  io_out_ready,
  io_out_valid,
  io_out_bits,
  io_chosen
);

  input io_in_1_valid;
  input io_in_1_bits;
  input io_in_0_valid;
  input io_in_0_bits;
  input io_out_ready;
  output io_in_1_ready;
  output io_in_0_ready;
  output io_out_valid;
  output io_out_bits;
  output io_chosen;
  wire io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits,io_chosen,N0,N1,
  io_out_ready,T4;
  assign io_in_0_ready = io_out_ready;
  assign io_chosen = ~io_in_0_valid;
  assign io_out_bits = (N0)? io_in_1_bits : 
                       (N1)? io_in_0_bits : 1'b0;
  assign N0 = io_chosen;
  assign N1 = io_in_0_valid;
  assign io_out_valid = (N0)? io_in_1_valid : 
                        (N1)? io_in_0_valid : 1'b0;
  assign io_in_1_ready = T4 & io_out_ready;
  assign T4 = ~io_in_0_valid;

endmodule
module Arbiter_0
(
  io_in_4_ready,
  io_in_4_valid,
  io_in_4_bits_idx,
  io_in_3_ready,
  io_in_3_valid,
  io_in_3_bits_idx,
  io_in_2_ready,
  io_in_2_valid,
  io_in_2_bits_idx,
  io_in_1_ready,
  io_in_1_valid,
  io_in_1_bits_idx,
  io_in_0_ready,
  io_in_0_valid,
  io_in_0_bits_idx,
  io_out_ready,
  io_out_valid,
  io_out_bits_idx,
  io_chosen
);

  input [5:0] io_in_4_bits_idx;
  input [5:0] io_in_3_bits_idx;
  input [5:0] io_in_2_bits_idx;
  input [5:0] io_in_1_bits_idx;
  input [5:0] io_in_0_bits_idx;
  output [5:0] io_out_bits_idx;
  output [2:0] io_chosen;
  input io_in_4_valid;
  input io_in_3_valid;
  input io_in_2_valid;
  input io_in_1_valid;
  input io_in_0_valid;
  input io_out_ready;
  output io_in_4_ready;
  output io_in_3_ready;
  output io_in_2_ready;
  output io_in_1_ready;
  output io_in_0_ready;
  output io_out_valid;
  wire [5:0] io_out_bits_idx,T4,T8,T5;
  wire [2:0] io_chosen,T0,T1;
  wire io_in_4_ready,io_in_3_ready,io_in_2_ready,io_in_1_ready,io_in_0_ready,
  io_out_valid,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,io_out_ready,N12,N13,N14,N15,N16,N17,
  N18,T13,T16,T14,T21,T23,T24,T26,T27,T28,T30,T31,T32,T33;
  wire [2:1] T2;
  assign io_in_0_ready = io_out_ready;
  assign io_chosen = (N0)? { 1'b0, 1'b0, 1'b0 } : 
                     (N1)? T0 : 1'b0;
  assign N0 = io_in_0_valid;
  assign N1 = N12;
  assign T0 = (N2)? { 1'b0, 1'b0, 1'b1 } : 
              (N3)? T1 : 1'b0;
  assign N2 = io_in_1_valid;
  assign N3 = N13;
  assign T1 = (N4)? { 1'b0, 1'b1, 1'b0 } : 
              (N5)? { T2, T2[1:1] } : 1'b0;
  assign N4 = io_in_2_valid;
  assign N5 = N14;
  assign io_out_bits_idx = (N6)? io_in_4_bits_idx : 
                           (N7)? T4 : 1'b0;
  assign N6 = io_chosen[2];
  assign N7 = N16;
  assign T4 = (N8)? T8 : 
              (N9)? T5 : 1'b0;
  assign N8 = io_chosen[1];
  assign N9 = N17;
  assign T5 = (N10)? io_in_1_bits_idx : 
              (N11)? io_in_0_bits_idx : 1'b0;
  assign N10 = io_chosen[0];
  assign N11 = N18;
  assign T8 = (N10)? io_in_3_bits_idx : 
              (N11)? io_in_2_bits_idx : 1'b0;
  assign io_out_valid = (N6)? io_in_4_valid : 
                        (N7)? T13 : 1'b0;
  assign T13 = (N8)? T16 : 
               (N9)? T14 : 1'b0;
  assign T14 = (N10)? io_in_1_valid : 
               (N11)? io_in_0_valid : 1'b0;
  assign T16 = (N10)? io_in_3_valid : 
               (N11)? io_in_2_valid : 1'b0;
  assign N12 = ~io_in_0_valid;
  assign N13 = ~io_in_1_valid;
  assign N14 = ~io_in_2_valid;
  assign N15 = ~io_in_3_valid;
  assign T2[1] = io_in_3_valid;
  assign T2[2] = N15;
  assign N16 = ~io_chosen[2];
  assign N17 = ~io_chosen[1];
  assign N18 = ~io_chosen[0];
  assign io_in_1_ready = T21 & io_out_ready;
  assign T21 = ~io_in_0_valid;
  assign io_in_2_ready = T23 & io_out_ready;
  assign T23 = ~T24;
  assign T24 = io_in_0_valid | io_in_1_valid;
  assign io_in_3_ready = T26 & io_out_ready;
  assign T26 = ~T27;
  assign T27 = T28 | io_in_2_valid;
  assign T28 = io_in_0_valid | io_in_1_valid;
  assign io_in_4_ready = T30 & io_out_ready;
  assign T30 = ~T31;
  assign T31 = T32 | io_in_3_valid;
  assign T32 = T33 | io_in_2_valid;
  assign T33 = io_in_0_valid | io_in_1_valid;

endmodule
module Arbiter_1
(
  io_in_1_ready,
  io_in_1_valid,
  io_in_1_bits_idx,
  io_in_1_bits_way_en,
  io_in_1_bits_data_tag,
  io_in_1_bits_data_coh_state,
  io_in_0_ready,
  io_in_0_valid,
  io_in_0_bits_idx,
  io_in_0_bits_way_en,
  io_in_0_bits_data_tag,
  io_in_0_bits_data_coh_state,
  io_out_ready,
  io_out_valid,
  io_out_bits_idx,
  io_out_bits_way_en,
  io_out_bits_data_tag,
  io_out_bits_data_coh_state,
  io_chosen
);

  input [5:0] io_in_1_bits_idx;
  input [3:0] io_in_1_bits_way_en;
  input [19:0] io_in_1_bits_data_tag;
  input [1:0] io_in_1_bits_data_coh_state;
  input [5:0] io_in_0_bits_idx;
  input [3:0] io_in_0_bits_way_en;
  input [19:0] io_in_0_bits_data_tag;
  input [1:0] io_in_0_bits_data_coh_state;
  output [5:0] io_out_bits_idx;
  output [3:0] io_out_bits_way_en;
  output [19:0] io_out_bits_data_tag;
  output [1:0] io_out_bits_data_coh_state;
  input io_in_1_valid;
  input io_in_0_valid;
  input io_out_ready;
  output io_in_1_ready;
  output io_in_0_ready;
  output io_out_valid;
  output io_chosen;
  wire [5:0] io_out_bits_idx;
  wire [3:0] io_out_bits_way_en;
  wire [19:0] io_out_bits_data_tag;
  wire [1:0] io_out_bits_data_coh_state;
  wire io_in_1_ready,io_in_0_ready,io_out_valid,io_chosen,N0,N1,io_out_ready,T7;
  assign io_in_0_ready = io_out_ready;
  assign io_chosen = ~io_in_0_valid;
  assign io_out_bits_data_coh_state = (N0)? io_in_1_bits_data_coh_state : 
                                      (N1)? io_in_0_bits_data_coh_state : 1'b0;
  assign N0 = io_chosen;
  assign N1 = io_in_0_valid;
  assign io_out_bits_data_tag = (N0)? io_in_1_bits_data_tag : 
                                (N1)? io_in_0_bits_data_tag : 1'b0;
  assign io_out_bits_way_en = (N0)? io_in_1_bits_way_en : 
                              (N1)? io_in_0_bits_way_en : 1'b0;
  assign io_out_bits_idx = (N0)? io_in_1_bits_idx : 
                           (N1)? io_in_0_bits_idx : 1'b0;
  assign io_out_valid = (N0)? io_in_1_valid : 
                        (N1)? io_in_0_valid : 1'b0;
  assign io_in_1_ready = T7 & io_out_ready;
  assign T7 = ~io_in_0_valid;

endmodule
module bsg_circular_ptr_slots_p128_max_add_p1
(
  clk,
  reset_i,
  add_i,
  o
);

  input [0:0] add_i;
  output [6:0] o;
  input clk;
  input reset_i;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12;
  wire [6:0] genblk1_genblk1_ptr_r_p1;
  reg [6:0] o;

  always @(posedge clk) begin
    if(N12) begin
      o[6] <= N9;
    end 
  end


  always @(posedge clk) begin
    if(N12) begin
      o[5] <= N8;
    end 
  end


  always @(posedge clk) begin
    if(N12) begin
      o[4] <= N7;
    end 
  end


  always @(posedge clk) begin
    if(N12) begin
      o[3] <= N6;
    end 
  end


  always @(posedge clk) begin
    if(N12) begin
      o[2] <= N5;
    end 
  end


  always @(posedge clk) begin
    if(N12) begin
      o[1] <= N4;
    end 
  end


  always @(posedge clk) begin
    if(N12) begin
      o[0] <= N3;
    end 
  end

  assign genblk1_genblk1_ptr_r_p1 = o + 1'b1;
  assign { N9, N8, N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 
                                          (N1)? genblk1_genblk1_ptr_r_p1 : 1'b0;
  assign N0 = reset_i;
  assign N1 = N2;
  assign N2 = ~reset_i;
  assign N10 = ~add_i[0];
  assign N11 = N10 & N2;
  assign N12 = ~N11;

endmodule