dakies/OSS_Verilog huggingface dataset:
module aibio_decoder2x4
	(
	//----------Supply pins------------//
	input vddcq,
	input vss,
	//----------Input pins------------//
	input [1:0] i,
	//----------Output pins----------//
	output reg [3:0] o
	);

always @(i)
	case(i)
   	2'b00 : o = 4'b0001;
      2'b01 : o = 4'b0010;
		2'b10 : o = 4'b0100;
      2'b11 : o = 4'b1000;
      default : o = 4'b0000;
	endcase


endmodule
module aibio_outclk_mux16x1
		(
		//--------Supply pins----------//
		input vddcq,
		input vss,
		//--------Input pins-----------//
		input [15:0]i_clkph,
		input [3:0]i_clksel,
		//--------Output pins---------//
		output o_clk
		);

wire [3:0] clk_sel_stg1;
wire [3:0] clk_sel_stg2;
wire [3:0] clkphsel_stg2;

aibio_decoder2x4 I4
		(
		.vddcq(vddcq),
		.vss(vss),
		.i(i_clksel[1:0]),
		.o(clk_sel_stg1)
		);

aibio_decoder2x4 I3
		(
		.vddcq(vddcq),
		.vss(vss),
		.i(i_clksel[3:2]),
		.o(clk_sel_stg2)
		);

aibio_pimux4x1 MUX0
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(i_clkph[3:0]),
		.i_clkph_sel(clk_sel_stg1),
		.o_clkph(clkphsel_stg2[0])
		);

aibio_pimux4x1 I0
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(i_clkph[7:4]),
		.i_clkph_sel(clk_sel_stg1),
		.o_clkph(clkphsel_stg2[1])
		);

aibio_pimux4x1 I2
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(i_clkph[11:8]),
		.i_clkph_sel(clk_sel_stg1),
		.o_clkph(clkphsel_stg2[2])
		);

aibio_pimux4x1 I1
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(i_clkph[15:12]),
		.i_clkph_sel(clk_sel_stg1),
		.o_clkph(clkphsel_stg2[3])
		);

aibio_pimux4x1 I5
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(clkphsel_stg2),
		.i_clkph_sel(clk_sel_stg2),
		.o_clkph(o_clk)
		);

endmodule
module aibio_pimux4x1
	(
	//----------Supply pins----------//
	input vddcq,
	input vss,
	//---------Input pins-----------//
	input [3:0]i_clkph,
	input [3:0]i_clkph_sel,
	//---------Output pins----------//
	output o_clkph
	);

assign o_clkph =  (i_clkph_sel == 4'b0001) ? i_clkph[0] :
						(i_clkph_sel == 4'b0010) ? i_clkph[1] :
						(i_clkph_sel == 4'b0100) ? i_clkph[2] :
						(i_clkph_sel == 4'b1000) ? i_clkph[3] :
						1'b0;

endmodule
module aibio_clock_dist
		(
		//---------Supply pins------------//
		input vddcq,
		input vss,
		//---------Input pins------------//
		input i_piclk_even_in,
		input i_piclk_odd_in,
		input i_loopback_en,
		//---------Output pins----------//
		output o_piclk_even_loopback,
		output o_piclk_odd_loopback
		);

assign o_piclk_even_loopback = i_loopback_en ? i_piclk_even_in : 1'b0;
assign o_piclk_odd_loopback = i_loopback_en ? i_piclk_odd_in : 1'b0;

endmodule
module aibio_outclk_select
		(
		//----------Supply pins-----------//
		input vddcq,
		input vss,
		//----------Input pins-----------//
		input [3:0] i_adapter_code,
		input [3:0] i_soc_code,
		input [15:0] i_clkphb,
		//----------Output pins-----------//
		output o_clk_adapter,
		output o_clk_soc
		);

wire clk_adapter_b;
wire clk_soc_b;

aibio_outclk_mux16x1 Adapater_MUX
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(i_clkphb),
		.i_clksel(i_adapter_code),
		.o_clk(clk_adapter_b)
		);

aibio_outclk_mux16x1 SOC_MUX
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(i_clkphb),
		.i_clksel(i_soc_code),
		.o_clk(clk_soc_b)
		);


assign o_clk_adapter = ~clk_adapter_b;
assign o_clk_soc = ~clk_soc_b;

endmodule
module aibio_se_to_diff
	(
	input vddcq,
	input vss,
	input i,
	output o,
	output o_b
	);

assign o = i;
assign o_b = ~i;

endmodule
module aibio_auxch_Schmit_trigger
		(
		//-------Supply pins----------//
		input vddc,
		input vss,
		//-------Input pin-----------//
		input vin,
		//-------Output pin---------//
		output vout
		);

assign vout=vin;

endmodule
module aibio_auxch_cbb
		(
		//----supply pins----//
		input vddc,
		input vss,
		//-----input pins-------------//
		input dual_mode_sel,
		input i_m_power_on_reset,
		input m_por_ovrd,
		input m_device_detect_ovrd,
		input [2:0]rxbuf_cfg,
		input powergood,
		input gen1mode_en,
		//-----inout pins-----------------//
		inout xx_power_on_reset,
		inout xx_device_detect,
		//-------output pins--------------//
		output o_m_power_on_reset,
		output m_device_detect,
		//--------spare pins---------------//
		input [3:0]i_aux_spare,
		output [3:0]o_aux_spare
		);


wire net016;
wire net017;
wire net09;
wire net028;
wire net023;
wire net013;

wire vin1;
wire vin2;


assign net013 = ~i_m_power_on_reset;
assign net09 = ~ dual_mode_sel;
assign net028 = ~net09;
assign net023 = ~vddc;

assign o_m_power_on_reset = (m_por_ovrd & net016);
assign m_device_detect = (net017 | m_device_detect_ovrd);

assign xx_power_on_reset = (net09)? ~net013 : 1'hz;
assign xx_device_detect = (net028) ? ~net023 :1'hz;

assign vin1 = xx_power_on_reset;
assign vin2 = xx_device_detect;

aibio_auxch_Schmit_trigger schmit_trigger1
		(
		.vddc(vddc),
		.vss(vss),
		.vin(vin1),
		.vout(net016)
		);


aibio_auxch_Schmit_trigger schmit_trigger2
		(
		.vddc(vddc),
		.vss(vss),
		.vin(vin2),
		.vout(net017)
		);

endmodule
module aibio_pulsegen_phsel_halfside
		(
		//---------Supply pins----------//
		input vddcq,
		input vss,
		//--------Input pins-----------//
		input [7:0]i_clkph,
		input [2:0]i_ph1sel,
		input [2:0]i_ph2sel,
		//--------Output pins---------//
		output o_clkph1,
		output o_clkph2
		);

aibio_pulsegen_mux8x1 I0
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(i_clkph),
		.i_clksel(i_ph1sel),
		.o_clkph(o_clkph1)
		);

aibio_pulsegen_mux8x1 I1
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(i_clkph),
		.i_clksel(i_ph2sel),
		.o_clkph(o_clkph2)
		);

endmodule
module aibio_inpclk_select_txdll
		(
		//--------Supply pins----------//
		input vddcq,
		input vss,
		//--------Input pins-----------//
		input i_clk_in,
		input i_clk_loopback,
		input i_clk_sys,
		input i_clk_jtag,
		input [1:0] i_clksel,
		//--------Output pins-----------//
		output o_clkp,
		output o_clkn
		);
/*
wire i_clk_inp;
wire i_clk_inn;
wire i_clk_loopbackp;
wire i_clk_loopbackn;
wire i_clk_sysp;
wire i_clk_sysn;
wire i_clk_jtagp;
wire i_clk_jtagn;

assign i_clk_loopbackp = i_clk_loopback;
assign i_clk_loopbackn = ~i_clk_loopback;

assign i_clk_sysp = i_clk_sys;
assign i_clk_sysn = ~i_clk_sys;

assign i_clk_inp = i_clk_in;
assign i_clk_inn = ~i_clk_in;

assign i_clk_jtagp = i_clk_jtag;
assign i_clk_jtagn = ~i_clk_jtag;


assign o_clkp = (i_clksel == 2'b00) ? i_clk_inp :
					 (i_clksel == 2'b01) ? i_clk_loopbackp :
					 (i_clksel == 2'b10) ? i_clk_sysp :
					 (i_clksel == 2'b11) ? i_clk_jtagp :
					 1'b0;

assign o_clkn = (i_clksel == 2'b00) ? i_clk_inn :
					 (i_clksel == 2'b01) ? i_clk_loopbackn :
					 (i_clksel == 2'b10) ? i_clk_sysn :
					 (i_clksel == 2'b11) ? i_clk_jtagn :
					 1'b0;
*/
wire o_clk;
wire [3:0]clksel_decoded;

aibio_decoder2x4 I5
	(
	.vddcq(vddcq),
	.vss(vss),
	.i(i_clksel),
	.o(clksel_decoded)
	);

aibio_pimux4x1 MUX_clkp
	(
	.vddcq(vddcq),
	.vss(vss),
	.i_clkph_sel(clksel_decoded),
	.i_clkph({i_clk_jtag,i_clk_sys,i_clk_loopback,i_clk_in}),
	.o_clkph(o_clk)
	);


aibio_se_to_diff se_diff_1
	(
	.vddcq(vddcq),
	.vss(vss),
	.i(o_clk),
	.o(o_clkp),
	.o_b(o_clkn)
	);


endmodule
module aibio_pulsegen_muxfinal
		(
		//-------Supply pins--------//
		input vddcq,
		input vss,
		//-------Input pins--------//
		input [1:0]i_clkph1_even,
		input [1:0]i_clkph1_odd,
		input [1:0]i_clkph1_sel_even,
		input [1:0]i_clkph1_sel_odd,
		input [1:0]i_clkph2_even,
		input [1:0]i_clkph2_odd,
		input [1:0]i_clkph2_sel_even,
		input [1:0]i_clkph2_sel_odd,
		//-------Output pins---------//
		output clk_out_even,
		output clk_out_odd,
		output pulse_out_even,
		output pulse_out_odd
		);

wire clkph1b_even;
wire clkph2b_even;
wire clkph1b_odd;
wire clkph2b_odd;

wire clkph2_odd;
wire clkph2_even;

aibio_pulsegen_mux2x1 I0
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(i_clkph1_even),
		.i_clkph_sel(i_clkph1_sel_even),
		.o_clkph(clkph1b_even)
		);

aibio_pulsegen_mux2x1 I1
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(i_clkph2_even),
		.i_clkph_sel(i_clkph2_sel_even),
		.o_clkph(clkph2b_even)
		);

aibio_pulsegen_mux2x1 I3
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(i_clkph2_odd),
		.i_clkph_sel(i_clkph2_sel_odd),
		.o_clkph(clkph2b_odd)
		);

aibio_pulsegen_mux2x1 I4
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(i_clkph1_odd),
		.i_clkph_sel(i_clkph1_sel_odd),
		.o_clkph(clkph1b_odd)
		);

assign clk_out_even = ~clkph1b_even;
assign clk_out_odd = ~clkph1b_odd;
assign clkph2_odd = ~clkph2b_odd;
assign clkph2_even = ~clkph2b_even;

assign pulse_out_even = clk_out_even && clkph2_even; 
assign pulse_out_odd = clk_out_odd && clkph2_odd;

endmodule
module aibio_pulsegen_oddevn_halfside
		(
		//---------Supply pins----------//
		input vddcq,
		input vss,
		//---------Input pins----------//
		input [7:0]i_clkph,
		input [2:0]i_evn_ph1_sel,
		input [2:0]i_evn_ph2_sel,
		input [2:0]i_odd_ph1_sel,
		input [2:0]i_odd_ph2_sel,
		//--------Output pins-----------//
		output o_clkph1_evn,
		output o_clkph1_odd,
		output o_clkph2_evn,
		output o_clkph2_odd
		);

aibio_pulsegen_phsel_halfside odd_ph1ph2
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(i_clkph),
		.i_ph1sel(i_odd_ph1_sel),
		.i_ph2sel(i_odd_ph2_sel),
		.o_clkph1(o_clkph1_odd),
		.o_clkph2(o_clkph2_odd)
		);

aibio_pulsegen_phsel_halfside evn_ph1ph2
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(i_clkph),
		.i_ph1sel(i_evn_ph1_sel),
		.i_ph2sel(i_evn_ph2_sel),
		.o_clkph1(o_clkph1_evn),
		.o_clkph2(o_clkph2_evn)
		);

endmodule
module aibio_pulsegen_mux8x1
		(
		//-------Supply pins---------//
		input vddcq,
		input vss,
		//-------Input pins----------//
		input [7:0] i_clkph,
		input [2:0] i_clksel,
		//-------Output pins---------//
		output wor o_clkph
//		output o_clkph 		//For LEC comment above line and uncomment this line
		);

wire [7:0] clk_sel;
//wor o_clkph;			//For LEC comment this line

aibio_decoder3x8 I1
		(
		.vddcq(vddcq),
		.vss(vss),
		.i(i_clksel),
		.o(clk_sel)
		);

aibio_pimux4x1 MUX0
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph({i_clkph[3],i_clkph[2],i_clkph[1],i_clkph[0]}),
		.i_clkph_sel({clk_sel[3],clk_sel[2],clk_sel[1],clk_sel[0]}),
		.o_clkph(o_clkph)
		);

aibio_pimux4x1 I0
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph({i_clkph[7],i_clkph[6],i_clkph[5],i_clkph[4]}),
		.i_clkph_sel({clk_sel[7],clk_sel[6],clk_sel[5],clk_sel[4]}),
		.o_clkph(o_clkph)
		);

//assign o_clkph = o_clkph_int1 || o_clkph_int2 ;

endmodule
module aibio_pulsegen_mux2x1
		(
		//-------Supply pins---------//
		input vddcq,
		input vss,
		//-------Input pins----------//
		input [1:0] i_clkph,
		input [1:0] i_clkph_sel,
		//-------Output pins--------//
		output o_clkph
		);

assign o_clkph = (i_clkph_sel == 2'b01) ? i_clkph[0] :
					  (i_clkph_sel == 2'b10) ? i_clkph[1] :
					1'b0;

endmodule
module aibio_pulsegen_top
		(
		//---------Supply pins----------//
		input vddcq,
		input vss,
		//---------Input pins----------//
		input [15:0] i_clkphb,
		input [3:0] i_dll_even_phase1_sel,
		input [3:0] i_dll_odd_phase1_sel,
		input [3:0] i_dll_even_phase2_sel,
		input [3:0] i_dll_odd_phase2_sel,
		//--------Output pins-----------//
		output o_clk_even,
		output o_clk_odd,
		output o_pulseclk_even,
		output o_pulseclk_odd
		);

wire [1:0]clkph1_even;
wire [1:0]clkph2_even;
wire [1:0]clkph1_odd;
wire [1:0]clkph2_odd;

wire i_dll_odd_phase1_selb_3;
wire i_dll_even_phase1_selb_3;
wire i_dll_odd_phase2_selb_3;
wire i_dll_even_phase2_selb_3;

assign i_dll_odd_phase2_selb_3 = ~i_dll_odd_phase2_sel[3];
assign i_dll_even_phase2_selb_3 = ~i_dll_even_phase2_sel[3];
assign i_dll_odd_phase1_selb_3 = ~i_dll_odd_phase1_sel[3];
assign i_dll_even_phase1_selb_3 = ~i_dll_even_phase1_sel[3];

aibio_pulsegen_oddevn_halfside phsel_LSB
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(i_clkphb[7:0]),
		.i_evn_ph1_sel(i_dll_even_phase1_sel[2:0]),
		.i_evn_ph2_sel(i_dll_even_phase2_sel[2:0]),
		.i_odd_ph1_sel(i_dll_odd_phase1_sel[2:0]),
		.i_odd_ph2_sel(i_dll_odd_phase2_sel[2:0]),
		.o_clkph1_evn(clkph1_even[0]),
		.o_clkph1_odd(clkph1_odd[0]),
		.o_clkph2_evn(clkph2_even[0]),
		.o_clkph2_odd(clkph2_odd[0])
		);

aibio_pulsegen_oddevn_halfside phsel_MSB
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(i_clkphb[15:8]),
		.i_evn_ph1_sel(i_dll_even_phase1_sel[2:0]),
		.i_evn_ph2_sel(i_dll_even_phase2_sel[2:0]),
		.i_odd_ph1_sel(i_dll_odd_phase1_sel[2:0]),
		.i_odd_ph2_sel(i_dll_odd_phase2_sel[2:0]),
		.o_clkph1_evn(clkph1_even[1]),
		.o_clkph1_odd(clkph1_odd[1]),
		.o_clkph2_evn(clkph2_even[1]),
		.o_clkph2_odd(clkph2_odd[1])
		);

aibio_pulsegen_muxfinal muxfinal
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph1_even(clkph1_even),
		.i_clkph1_odd(clkph1_odd),
		.i_clkph1_sel_even({i_dll_even_phase1_sel[3],i_dll_even_phase1_selb_3}),
		.i_clkph1_sel_odd({i_dll_odd_phase1_sel[3],i_dll_odd_phase1_selb_3}),
		.i_clkph2_even(clkph2_even),
		.i_clkph2_odd(clkph2_odd),
		.i_clkph2_sel_even({i_dll_even_phase2_selb_3,i_dll_even_phase2_sel[3]}),
		.i_clkph2_sel_odd({i_dll_odd_phase2_selb_3,i_dll_odd_phase2_sel[3]}),
		.clk_out_even(o_clk_even),
		.clk_out_odd(o_clk_odd),
		.pulse_out_even(o_pulseclk_even),
		.pulse_out_odd(o_pulseclk_odd)
		);

endmodule
module aibio_pi_decode_sync
		(
		//---------Supply pins--------//
		input vddcq,
		input vss,
		//---------Input pins----------//
		input i_clk_en,
		input i_clk_sync,
		input [7:0] i_picode,
		input i_reset,
		input i_update,
		//---------Output pins---------//
		output [7:0] o_clkphsel_stg1_synced,
		output [1:0] o_clkphsel_stg2_synced,
		output [7:0] o_pimixer_synced
		);

wire [7:0] clkphsel_stg1;
wire [1:0] clkphsel_stg2;
wire [7:0] pimixer;

aibio_pi_decode I1
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_picode(i_picode),
		.o_clkphsel_stg1(clkphsel_stg1),
		.o_clkphsel_stg2(clkphsel_stg2),
		.o_pimixer(pimixer)
		);

aibio_pi_codeupdate I2
		(
 		.vddcq(vddcq),
		.vss(vss),
 		.i_clk(i_clk_sync),
 		.i_clk_en(i_clk_en),
		.i_clkphsel_stg1(clkphsel_stg1),
		.i_clkphsel_stg2(clkphsel_stg2),
		.i_pimixer(pimixer),
		.i_update(i_update),
		.i_reset(i_reset),
		.o_clkphsel_stg1(o_clkphsel_stg1_synced),
		.o_clkphsel_stg2(o_clkphsel_stg2_synced),
		.o_pimixer(o_pimixer_synced)
		);

endmodule
module aibio_pi_decode
		(
		//--------Supply pins----------//
		input vddcq,
		input vss,
		//--------Input pins-----------//
		input [7:0] i_picode,
		//--------Output pins----------//
		output [7:0]o_clkphsel_stg1,
		output [1:0]o_clkphsel_stg2,
		output [7:0]o_pimixer
		);

wire [3:0] picode_plus1;
wire mix_on;
wire [7:0] curr_code;
wire [7:0] next_code;

wire [7:1] therm;
wire [7:1] therm_b;
wire next_odd_en;
wire next_evn_en;
wire i_picode_b_3;


aibio_decoder3x8 I7
		(
		.vddcq(vddcq),
		.vss(vss),
		.i(i_picode[5:3]),
		.o(curr_code)
		);

aibio_decoder3x8 I6
		(
		.vddcq(vddcq),
		.vss(vss),
		.i(picode_plus1[2:0]),
		.o(next_code)
		);

aibio_3bit_bin_to_therm I3
		(
		.vddcq(vddcq),
		.vss(vss),
		.b(i_picode[2:0]),
		.t(therm)
		);

aibio_4bit_plus1 I4
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_code(i_picode[6:3]),
		.o_code(picode_plus1)
		);


assign therm_b[7] = ~therm[7];
assign therm_b[6] = ~therm[6];
assign therm_b[5] = ~therm[5];
assign therm_b[4] = ~therm[4];
assign therm_b[3] = ~therm[3];
assign therm_b[2] = ~therm[2];
assign therm_b[1] = ~therm[1];

//assign mix_on = i_picode[2] || i_picode[1] || i_picode[0];
//assign next_evn_en = i_picode[3] && mix_on ;
assign next_evn_en = i_picode[3];
assign i_picode_b_3 = ~i_picode[3];
//assign next_odd_en = i_picode_b_3 && mix_on;
assign next_odd_en = i_picode_b_3;

assign o_clkphsel_stg2[0] = next_evn_en ? picode_plus1[3] : i_picode[6];
assign o_clkphsel_stg2[1] = next_odd_en ? picode_plus1[3] : i_picode[6];

assign o_clkphsel_stg1[6] = next_evn_en ? next_code[6] : curr_code[6];
assign o_clkphsel_stg1[4] = next_evn_en ? next_code[4] : curr_code[4];
assign o_clkphsel_stg1[2] = next_evn_en ? next_code[2] : curr_code[2];
assign o_clkphsel_stg1[0] = next_evn_en ? next_code[0] : curr_code[0];

assign o_clkphsel_stg1[7] = next_odd_en ? next_code[7] : curr_code[7];
assign o_clkphsel_stg1[5] = next_odd_en ? next_code[5] : curr_code[5];
assign o_clkphsel_stg1[3] = next_odd_en ? next_code[3] : curr_code[3];
assign o_clkphsel_stg1[1] = next_odd_en ? next_code[1] : curr_code[1];

assign o_pimixer[7] = i_picode[3] ? therm_b[7] : therm[7];
assign o_pimixer[6] = i_picode[3] ? therm_b[6] : therm[6];
assign o_pimixer[5] = i_picode[3] ? therm_b[5] : therm[5];
assign o_pimixer[4] = i_picode[3] ? therm_b[4] : therm[4];
assign o_pimixer[3] = i_picode[3] ? therm_b[3] : therm[3];
assign o_pimixer[2] = i_picode[3] ? therm_b[2] : therm[2];
assign o_pimixer[1] = i_picode[3] ? therm_b[1] : therm[1];

assign o_pimixer[0] = i_picode[3];

endmodule
module aibio_pioddevn_mixer_top
		(
		//--------Supply pins--------//
		input vddcq,
		input vss,
		//--------Input pins---------//
		input i_clkevn_evn,
		input i_clkevn_odd,
		input i_clkodd_evn,
		input i_clkodd_odd,
		input i_pien,
		input [7:0]i_pimixer_evn,
		input [7:0]i_pimixer_odd,
		input [15:0]i_clkph,
		input [7:0]i_pievn_code,
		input [7:0]i_piodd_code,
		input real ph_diff,
		//--------Output pins---------//
		output o_clk_evn,
		output o_clk_odd
		);

wire odd_clk_mixer;
wire evn_clk_mixer;

wire odd_clk_mixerb;
wire evn_clk_mixerb;

wire out_ph_0_flag_evn;
wire out_ph_0_flag_odd;
wire out_ph_0_flag;

wire odd_clk_mixer_int;
wire evn_clk_mixer_int;

aibio_pi_mixer_top mixer_odd
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph_evn(i_clkevn_odd),
		.i_clkph_odd(i_clkodd_odd),
		.i_oddph_en(i_pimixer_odd),
		.i_pien(i_pien),
		.i_clkph(i_clkph),
		.i_picode(i_piodd_code),
		.ph_diff(ph_diff),
		.o_clkmix_out(odd_clk_mixer)
		);

aibio_pi_mixer_top mixer_evn
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph_evn(i_clkevn_evn),
		.i_clkph_odd(i_clkodd_evn),
		.i_oddph_en(i_pimixer_evn),
		.i_pien(i_pien),
		.i_clkph(i_clkph),
		.i_picode(i_pievn_code),
		.ph_diff(ph_diff),
		.o_clkmix_out(evn_clk_mixer)
		);


assign evn_clk_mixerb = ~evn_clk_mixer;
assign o_clk_evn = ~evn_clk_mixerb;

assign odd_clk_mixerb = ~odd_clk_mixer;
assign o_clk_odd = ~odd_clk_mixerb;

endmodule
module aibio_half_adder
		(
		//-------Supply pins---------//
		input vddcq,
		input vss,
		//-------Input pins----------//
		input a,
		input b,
		//------Output pins---------//
		output c,
		output s
		);

assign s = a^b;
assign c = a&&b;

endmodule
module aibio_pi_phsel_halfside
		(
		//---------Supply pins--------//
		input vddcq,
		input vss,
		//--------Input pins---------//
		input [1:0]i_cap_sel,
		input [1:0]i_cap_selb,
		input [3:0]i_clk_evnph,
		input [3:0]i_clk_evnphsel_stg1,
		input i_clk_evnphsel_stg2,
		input [3:0]i_clk_oddph,
		input [3:0]i_clk_oddphsel_stg1,
		input i_clk_oddphsel_stg2,
		input i_nbias,
		input [2:0]i_nbias_trim,
		input i_pbias,
		input [2:0]i_pbias_trim,
		//--------Output pins----------//
		output o_clk_evnph,
		output o_clk_oddph
		);

aibio_pi_phsel_quarter phsel_mux_odd
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(i_clk_oddph),
		.i_clkphsel_stg1(i_clk_oddphsel_stg1),
		.i_clkphsel_stg2(i_clk_oddphsel_stg2),
		.i_pbias(i_pbias),
		.i_pbias_trim(i_pbias_trim),
		.i_nbias(i_nbias),
		.i_nbias_trim(i_nbias_trim),
		.i_cap_sel(i_cap_sel),
		.i_cap_selb(i_cap_selb),
		.o_clkph(o_clk_oddph)
		);

aibio_pi_phsel_quarter phsel_mux_evn
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(i_clk_evnph),
		.i_clkphsel_stg1(i_clk_evnphsel_stg1),
		.i_clkphsel_stg2(i_clk_evnphsel_stg2),
		.i_pbias(i_pbias),
		.i_pbias_trim(i_pbias_trim),
		.i_nbias(i_nbias),
		.i_nbias_trim(i_nbias_trim),
		.i_cap_sel(i_cap_sel),
		.i_cap_selb(i_cap_selb),
		.o_clkph(o_clk_evnph)
		);

endmodule
module aibio_4bit_plus1
		(
		//-------Supply pins------//
		input vddcq,
		input vss,
		//-------Input pins--------//
		input [3:0] i_code,
		//-------Output pins-------//
		output [3:0] o_code
		);

wire net13;
wire net14;
wire net15;
wire net27;

aibio_half_adder I0
		(
		.vddcq(vddcq),
		.vss(vss),
		.a(i_code[0]),
		.b(1'b1),
		.c(net13),
		.s(o_code[0])
		);

aibio_half_adder I1
		(
		.vddcq(vddcq),
		.vss(vss),
		.a(i_code[1]),
		.b(net13),
		.c(net14),
		.s(o_code[1])
		);

aibio_half_adder I2
		(
		.vddcq(vddcq),
		.vss(vss),
		.a(i_code[2]),
		.b(net14),
		.c(net15),
		.s(o_code[2])
		);

aibio_half_adder I3
		(
		.vddcq(vddcq),
		.vss(vss),
		.a(i_code[3]),
		.b(net15),
		.c(net27),
		.s(o_code[3])
		);

endmodule
module aibio_inpclk_select
		(
		//--------Supply pins----------//
		input vddcq,
		input vss,
		//--------Input pins-----------//
		input i_clk_inp,
		input i_clk_inn,
		input i_clk_loopback,
		input i_clk_sys,
		input i_clk_jtag,
		input i_clk_cdr_inp,
		input i_clk_cdr_inn,
		input [1:0] i_clksel,
		//--------Output pins-----------//
		output o_clkp,
		output o_clkn,
		output o_cdr_clkp,
		output o_cdr_clkn
		);

wire i_clk_loopbackp;
wire i_clk_loopbackn;
wire i_clk_sysp;
wire i_clk_sysn;
wire i_clk_jtagp;
wire i_clk_jtagn;

wire [3:0] clksel_decoded;

wire net016,net017,net018,net019;


aibio_se_to_diff se_diff_1
	(
	.vddcq(vddcq),
	.vss(vss),
	.i(i_clk_loopback),
	.o(i_clk_loopbackp),
	.o_b(i_clk_loopbackn)
	);

aibio_se_to_diff I7
	(
	.vddcq(vddcq),
	.vss(vss),
	.i(i_clk_jtag),
	.o(i_clk_jtagp),
	.o_b(i_clk_jtagn)
	);

aibio_se_to_diff se_diff_2
	(
	.vddcq(vddcq),
	.vss(vss),
	.i(i_clk_sys),
	.o(i_clk_sysp),
	.o_b(i_clk_sysn)
	);


aibio_pimux4x1 MUX_dummy_p
	(
	.vddcq(vddcq),
	.vss(vss),
	.i_clkph_sel({1'b0,1'b0,1'b0,1'b1}), //TBD
	.i_clkph({1'b0,1'b0,1'b0,i_clk_cdr_inp}),
	.o_clkph(net017)
	);


aibio_pimux4x1 MUX_dummy_n
	(
	.vddcq(vddcq),
	.vss(vss),
	.i_clkph_sel({1'b0,1'b0,1'b0,1'b1}),
	.i_clkph({1'b0,1'b0,1'b0,i_clk_cdr_inn}),
	.o_clkph(net016)
	);


aibio_decoder2x4 I5
	(
	.vddcq(vddcq),
	.vss(vss),
	.i(i_clksel),
	.o(clksel_decoded)
	);

aibio_pimux4x1 MUX_clkp
	(
	.vddcq(vddcq),
	.vss(vss),
	.i_clkph_sel(clksel_decoded),
	.i_clkph({i_clk_jtagp,i_clk_sysp,i_clk_loopbackp,i_clk_inp}),
	.o_clkph(net019)
	);

aibio_pimux4x1 MUX_clkn
	(
	.vddcq(vddcq),
	.vss(vss),
	.i_clkph_sel(clksel_decoded),
	.i_clkph({i_clk_jtagn,i_clk_sysn,i_clk_loopbackn,i_clk_inn}),
	.o_clkph(net018)
	);


/*
assign o_cdr_clkp = ~net017;
assign o_cdr_clkn = ~net016;
assign o_clkp = ~net019;
assign o_clkn = ~net018;
*/

assign o_cdr_clkp = net017;
assign o_cdr_clkn = net016;
assign o_clkp = net019;
assign o_clkn = net018;

endmodule
module aibio_pi_phsel_quarter
		(
		//--------Supply pins-------------//
		input vddcq,
		input vss,
		//--------Input pins-------------//
		input [3:0] i_clkph,
		input [3:0] i_clkphsel_stg1,
		input i_clkphsel_stg2,
		input i_pbias,
		input [2:0] i_pbias_trim,
		input i_nbias,
		input [2:0] i_nbias_trim,
		input [1:0] i_cap_sel,
		input [1:0] i_cap_selb,
		//---------Output pins------------//
		output o_clkph
		);

wire ph_MUX_out;

aibio_pimux4x1 MUX0
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph_sel(i_clkphsel_stg1),
		.i_clkph(i_clkph),
		.o_clkph(ph_MUX_out)
		);

assign o_clkph = (i_clkphsel_stg2 == 1'b1) ? ph_MUX_out : 1'bz;

endmodule
module aibio_pioddevn_phsel_half
		(
		//--------Supply pins---------//
		input vddcq,
		input vss,
		//--------Input pins----------//
		input [1:0]i_cap_sel,
		input [1:0]i_cap_selb,
		input [3:0]i_clk_evnph,
		input [3:0]i_clk_evnphsel_stg1_evn,
		input [3:0]i_clk_evnphsel_stg1_odd,
		input i_clk_evnphsel_stg2_evn,
		input i_clk_evnphsel_stg2_odd,
		input [3:0]i_clk_oddph,
		input [3:0]i_clk_oddphsel_stg1_evn,
		input [3:0]i_clk_oddphsel_stg1_odd,
		input i_clk_oddphsel_stg2_evn,
		input i_clk_oddphsel_stg2_odd,
		input i_nbias,
		input [2:0] i_nbias_trim,
		input i_pbias,
		input [2:0]i_pbias_trim,
		//---------Output pins-----------//
		output o_clk_evnph_evn,
		output o_clk_evnph_odd,
		output o_clk_oddph_evn,
		output o_clk_oddph_odd
		);

aibio_pi_phsel_halfside oddclk_phselhalf
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_cap_sel(i_cap_sel),
		.i_cap_selb(i_cap_selb),
		.i_clk_evnph(i_clk_evnph),
		.i_clk_evnphsel_stg1(i_clk_evnphsel_stg1_odd),
		.i_clk_evnphsel_stg2(i_clk_evnphsel_stg2_odd),
		.i_clk_oddph(i_clk_oddph),
		.i_clk_oddphsel_stg1(i_clk_oddphsel_stg1_odd),
		.i_clk_oddphsel_stg2(i_clk_oddphsel_stg2_odd),
		.i_nbias(i_nbias),
		.i_nbias_trim(i_nbias_trim),
		.i_pbias(i_pbias),
		.i_pbias_trim(i_pbias_trim),
		.o_clk_evnph(o_clk_evnph_odd),
		.o_clk_oddph(o_clk_oddph_odd)
		);

aibio_pi_phsel_halfside evnclk_phselhalf
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_cap_sel(i_cap_sel),
		.i_cap_selb(i_cap_selb),
		.i_clk_evnph(i_clk_evnph),
		.i_clk_evnphsel_stg1(i_clk_evnphsel_stg1_evn),
		.i_clk_evnphsel_stg2(i_clk_evnphsel_stg2_evn),
		.i_clk_oddph(i_clk_oddph),
		.i_clk_oddphsel_stg1(i_clk_oddphsel_stg1_evn),
		.i_clk_oddphsel_stg2(i_clk_oddphsel_stg2_evn),
		.i_nbias(i_nbias),
		.i_nbias_trim(i_nbias_trim),
		.i_pbias(i_pbias),
		.i_pbias_trim(i_pbias_trim),
		.o_clk_evnph(o_clk_evnph_evn),
		.o_clk_oddph(o_clk_oddph_evn)
		);

endmodule
module aibio_cdr_detect
		(
		//----------Supply pins------------//
		input vddcq,
		input vss,
		//---------Input pins--------------//
		input i_cdr_clk,
		input i_piclk_90,
		input i_piclk_180,
		input i_sdr_mode,
		input i_reset,
		//---------Output pins-------------//
		output reg o_cdr_phdet
		);

wire clk_int;
wire rstb;

assign rstb = ~i_reset;

assign clk_int = (i_sdr_mode) ? i_piclk_180 : i_piclk_90;

`ifdef POST_WORST
	localparam t_setup = 0.0;
	localparam t_hold = 0.0;
	localparam t_clk2q = 0.0;
`else
	localparam t_setup = 0.0;
	localparam t_hold = 0.0;
	localparam t_clk2q = 0.0;
`endif

sampler #(t_setup,t_hold,t_clk2q)
			i_cdr_phdet
			(
			.data_in(i_cdr_clk),
			.clk(clk_int),
			.rst(rstb),
			.data_out(o_cdr_phdet)
			);
/*
always @(posedge clk_int or negedge rstb)
begin
	if(!rstb)
	begin
		o_cdr_phdet <= 1'b0;
	end
	else
	begin
		o_cdr_phdet <= i_cdr_clk;
	end
end
*/

endmodule
module aibio_3bit_bin_to_therm
		(
		//--------Supply pins---------//
		input vddcq,
		input vss,
		//-------Input pins----------//
		input [2:0] b,
		//-------Outptu pins---------//
		output reg [6:0] t
		);

always @(b)
	case(b)
   	3'b000 : t = 7'b000_0000;
      3'b001 : t = 7'b000_0001;
		3'b010 : t = 7'b000_0011;
      3'b011 : t = 7'b000_0111;
   	3'b100 : t = 7'b000_1111;
      3'b101 : t = 7'b001_1111;
		3'b110 : t = 7'b011_1111;
      3'b111 : t = 7'b111_1111;
      default : t = 8'b0000_0000;
	endcase

endmodule
module aibio_bias_trim
		(
		//-------Supply pins---------//
		input vddcq,
		input vss,
		//-------Input pins---------//
		input [2:0]i_bias_trim,
		input i_pbias,
		input i_nbias,
		//--------Output pins----------//
		output [2:0]o_pbias_trim,
		output [2:0]o_nbias_trim
			);

//assign o_pbias_trim = ~(i_bias_trim);
//assign o_nbias_trim = i_bias_trim;

assign o_pbias_trim[0] = i_bias_trim[0] ? i_pbias : vddcq;
assign o_pbias_trim[1] = i_bias_trim[1] ? i_pbias : vddcq;
assign o_pbias_trim[2] = i_bias_trim[2] ? i_pbias : vddcq;

assign o_nbias_trim[0] = i_bias_trim[0] ? i_nbias : vss;
assign o_nbias_trim[1] = i_bias_trim[1] ? i_pbias : vss;
assign o_nbias_trim[2] = i_bias_trim[2] ? i_pbias : vss;

//assign o_pbias_trim = 3'b000;
//assign o_nbias_trim = 3'b000;

endmodule
module aib_fifo_rdata_ored #(
parameter DWIDTH  = 80,  // FIFO Input data width
parameter DEPTH    = 3   // FIFO Depth
)
(
// Output
output reg [DWIDTH-1:0] fifo_rdata, 
// Input
input [DEPTH-1:0][DWIDTH-1:0] fifo_out_sel
);

integer n;

always @(*) 
  begin
    fifo_rdata = {DWIDTH{1'b0}};
    for(n = 0; n < DEPTH; n = n + 1)
      begin
        fifo_rdata = fifo_rdata | fifo_out_sel[n];
      end
  end

endmodule // aib_fifo_rdata_ored
module aib_rxfifo_rd_dpath #(
parameter DWIDTH  = 320,
parameter DEPTH   = 16,
parameter DEPTH4  = DEPTH*4
)
(
output  [DWIDTH-1:0] rdata_sync_ff, // Read data synchronized
input   [DEPTH4-1:0] fifo_rd_en,    // FIFO element selector
input   [1:0]        r_fifo_mode,   // FIFO mode
input                m_gen2_mode,   // Gen2 mode
input   [DEPTH-1 :0][DWIDTH-1:0] fifo_data_async, // FIFO data
input                rd_clk,        // FIFO read clock
input                rd_rst_n       // FIFO read asynchronous reset
);

wire [DEPTH4-1:0][79:0] fifo_out_sel;
wire [DEPTH4-1 :0][79:0]   fifo_dword_async;
wire [DWIDTH-1:0] fifo_rdata;



genvar k;
generate
  for(k=0; k < DEPTH; k = k+1)
    begin: fifo_dword_async_gen
      assign fifo_dword_async[(4*k)]    = fifo_data_async[k][79:0];
      assign fifo_dword_async[(4*k)+1]  = fifo_data_async[k][159:80];
      assign fifo_dword_async[(4*k)+2]  = fifo_data_async[k][239:160];
      assign fifo_dword_async[(4*k)+3]  = fifo_data_async[k][319:240];
    end // block: fifo_dword_async_gen
endgenerate

generate 
  for(k=0; k < DEPTH4; k = k+1)
    begin: fifo_and_sel
      aib_fifo_and_sel #(.DWIDTH (80))
      aib_fifo_and_sel(
      // Outputs
      .fifo_out_sel (fifo_out_sel[k]),
      // Inputs
      .fifo_rd_en   (fifo_rd_en[k]),
      .fifo_rd_in   (fifo_dword_async[k][80-1:0])
      );
    end // fifo_and_sel
endgenerate

aib_rxfifo_rdata_sel #(
.DEPTH (DEPTH),
.DWIDTH (DWIDTH)
)
aib_rxfifo_rdata_sel(
// Output
.fifo_rdata (fifo_rdata[DWIDTH-1:0]),
//Input
.r_fifo_mode  (r_fifo_mode[1:0]),       // FIFO mode
.m_gen2_mode  (m_gen2_mode),            // GEN2 mode
.fifo_out_sel (fifo_out_sel)
);

aib_fifo_rdata_buf #(
.DWIDTH (DWIDTH)
)
aib_fifo_rdata_buf(
// outputs
.fifo_rdata_ff (rdata_sync_ff[DWIDTH-1:0]),
// Inputs
.fifo_rdata    (fifo_rdata[DWIDTH-1:0]),
.rd_clk        (rd_clk),
.rd_rst_n      (rd_rst_n)
);

endmodule // aib_rxfifo_rd_dpath
module aib_txfifo_rd_dpath #(
parameter DINW   = 320,
parameter DOUTW  = 80,
parameter DEPTH  = 16,
parameter DEPTH4 = DEPTH * 4
)
(
output  [DOUTW-1:0]           rdata_sync_ff,   // Read data synchronized
input   [DEPTH4-1:0]          fifo_rd_en,      // FIFO element selector
input   [DEPTH-1:0][DINW-1:0] fifo_data_async, // FIFO data
input                         rd_clk,          // FIFO read clock
input                         rd_rst_n         // FIFO read asynchronous reset
);

wire [DEPTH4-1:0][DOUTW-1:0] fifo_out_sel;
wire [DOUTW-1:0]            fifo_rdata;
wire [DEPTH4-1 :0][79:0]    fifo_dword_async;

genvar k;
generate
  for(k=0; k < DEPTH; k = k+1)
    begin: fifo_dword_async_gen
      assign fifo_dword_async[(4*k)]    = fifo_data_async[k][79:0];
      assign fifo_dword_async[(4*k)+1]  = fifo_data_async[k][159:80];
      assign fifo_dword_async[(4*k)+2]  = fifo_data_async[k][239:160];
      assign fifo_dword_async[(4*k)+3]  = fifo_data_async[k][319:240];
    end // block: fifo_dword_async_gen
endgenerate

generate 
  for(k=0; k < DEPTH4; k = k+1)
    begin: fifo_and_sel
      aib_fifo_and_sel #(.DWIDTH (DOUTW))
      aib_fifo_and_sel(
      // Outputs
      .fifo_out_sel (fifo_out_sel[k]),
      // Inputs
      .fifo_rd_en   (fifo_rd_en[k]),
      .fifo_rd_in   (fifo_dword_async[k][DOUTW-1:0])
      );
    end // fifo_and_sel
endgenerate


aib_fifo_rdata_ored #(
.DEPTH (DEPTH4),
.DWIDTH (DOUTW)
)
aib_fifo_rdata_ored(
// Output
.fifo_rdata (fifo_rdata[DOUTW-1:0]),
//Input
.fifo_out_sel (fifo_out_sel)
);

aib_fifo_rdata_buf #(
.DWIDTH (DOUTW)
)
aib_fifo_rdata_buf(
// outputs
.fifo_rdata_ff (rdata_sync_ff[DOUTW-1:0]),
// Inputs
.fifo_rdata    (fifo_rdata[DOUTW-1:0]),
.rd_clk        (rd_clk),
.rd_rst_n      (rd_rst_n)
);

endmodule // aib_txfifo_rd_dpath
module emib_ch_m2s2 (
	inout [101:0] s_aib,
	inout [101:0] m_aib

	);

genvar i;

generate
  for (i=0; i<102; i=i+1) begin: aib_io_conn
  aliasv xaliasv95 (
	.PLUS(m_aib[i]),
	.MINUS(s_aib[101-i])
  );
  end
endgenerate

endmodule