module ghrd_10as066n2_axi_bridge_0 #(
		parameter USE_PIPELINE          = 1,
		parameter USE_M0_AWID           = 1,
		parameter USE_M0_AWREGION       = 1,
		parameter USE_M0_AWLEN          = 1,
		parameter USE_M0_AWSIZE         = 1,
		parameter USE_M0_AWBURST        = 1,
		parameter USE_M0_AWLOCK         = 1,
		parameter USE_M0_AWCACHE        = 1,
		parameter USE_M0_AWQOS          = 1,
		parameter USE_S0_AWREGION       = 1,
		parameter USE_S0_AWLOCK         = 1,
		parameter USE_S0_AWCACHE        = 1,
		parameter USE_S0_AWQOS          = 1,
		parameter USE_S0_AWPROT         = 1,
		parameter USE_M0_WSTRB          = 1,
		parameter USE_S0_WLAST          = 1,
		parameter USE_M0_BID            = 1,
		parameter USE_M0_BRESP          = 1,
		parameter USE_S0_BRESP          = 1,
		parameter USE_M0_ARID           = 1,
		parameter USE_M0_ARREGION       = 1,
		parameter USE_M0_ARLEN          = 1,
		parameter USE_M0_ARSIZE         = 1,
		parameter USE_M0_ARBURST        = 1,
		parameter USE_M0_ARLOCK         = 1,
		parameter USE_M0_ARCACHE        = 1,
		parameter USE_M0_ARQOS          = 1,
		parameter USE_S0_ARREGION       = 1,
		parameter USE_S0_ARLOCK         = 1,
		parameter USE_S0_ARCACHE        = 1,
		parameter USE_S0_ARQOS          = 1,
		parameter USE_S0_ARPROT         = 1,
		parameter USE_M0_RID            = 1,
		parameter USE_M0_RRESP          = 1,
		parameter USE_M0_RLAST          = 1,
		parameter USE_S0_RRESP          = 1,
		parameter M0_ID_WIDTH           = 3,
		parameter S0_ID_WIDTH           = 6,
		parameter DATA_WIDTH            = 512,
		parameter WRITE_ADDR_USER_WIDTH = 32,
		parameter READ_ADDR_USER_WIDTH  = 32,
		parameter WRITE_DATA_USER_WIDTH = 32,
		parameter WRITE_RESP_USER_WIDTH = 32,
		parameter READ_DATA_USER_WIDTH  = 32,
		parameter ADDR_WIDTH            = 32,
		parameter USE_S0_AWUSER         = 0,
		parameter USE_S0_ARUSER         = 0,
		parameter USE_S0_WUSER          = 0,
		parameter USE_S0_RUSER          = 0,
		parameter USE_S0_BUSER          = 0,
		parameter USE_M0_AWUSER         = 0,
		parameter USE_M0_ARUSER         = 0,
		parameter USE_M0_WUSER          = 0,
		parameter USE_M0_RUSER          = 0,
		parameter USE_M0_BUSER          = 0,
		parameter AXI_VERSION           = "AXI4"
	) (
		input  wire         aclk,        //       clk.clk
		input  wire         aresetn,     // clk_reset.reset_n
		output wire [2:0]   m0_awid,     //        m0.awid
		output wire [31:0]  m0_awaddr,   //          .awaddr
		output wire [7:0]   m0_awlen,    //          .awlen
		output wire [2:0]   m0_awsize,   //          .awsize
		output wire [1:0]   m0_awburst,  //          .awburst
		output wire [0:0]   m0_awlock,   //          .awlock
		output wire [3:0]   m0_awcache,  //          .awcache
		output wire [2:0]   m0_awprot,   //          .awprot
		output wire [3:0]   m0_awqos,    //          .awqos
		output wire [3:0]   m0_awregion, //          .awregion
		output wire         m0_awvalid,  //          .awvalid
		input  wire         m0_awready,  //          .awready
		output wire [511:0] m0_wdata,    //          .wdata
		output wire [63:0]  m0_wstrb,    //          .wstrb
		output wire         m0_wlast,    //          .wlast
		output wire         m0_wvalid,   //          .wvalid
		input  wire         m0_wready,   //          .wready
		input  wire [2:0]   m0_bid,      //          .bid
		input  wire [1:0]   m0_bresp,    //          .bresp
		input  wire         m0_bvalid,   //          .bvalid
		output wire         m0_bready,   //          .bready
		output wire [2:0]   m0_arid,     //          .arid
		output wire [31:0]  m0_araddr,   //          .araddr
		output wire [7:0]   m0_arlen,    //          .arlen
		output wire [2:0]   m0_arsize,   //          .arsize
		output wire [1:0]   m0_arburst,  //          .arburst
		output wire [0:0]   m0_arlock,   //          .arlock
		output wire [3:0]   m0_arcache,  //          .arcache
		output wire [2:0]   m0_arprot,   //          .arprot
		output wire [3:0]   m0_arqos,    //          .arqos
		output wire [3:0]   m0_arregion, //          .arregion
		output wire         m0_arvalid,  //          .arvalid
		input  wire         m0_arready,  //          .arready
		input  wire [2:0]   m0_rid,      //          .rid
		input  wire [511:0] m0_rdata,    //          .rdata
		input  wire [1:0]   m0_rresp,    //          .rresp
		input  wire         m0_rlast,    //          .rlast
		input  wire         m0_rvalid,   //          .rvalid
		output wire         m0_rready,   //          .rready
		input  wire [5:0]   s0_awid,     //        s0.awid
		input  wire [31:0]  s0_awaddr,   //          .awaddr
		input  wire [7:0]   s0_awlen,    //          .awlen
		input  wire [2:0]   s0_awsize,   //          .awsize
		input  wire [1:0]   s0_awburst,  //          .awburst
		input  wire [0:0]   s0_awlock,   //          .awlock
		input  wire [3:0]   s0_awcache,  //          .awcache
		input  wire [2:0]   s0_awprot,   //          .awprot
		input  wire [3:0]   s0_awqos,    //          .awqos
		input  wire [3:0]   s0_awregion, //          .awregion
		input  wire         s0_awvalid,  //          .awvalid
		output wire         s0_awready,  //          .awready
		input  wire [511:0] s0_wdata,    //          .wdata
		input  wire [63:0]  s0_wstrb,    //          .wstrb
		input  wire         s0_wlast,    //          .wlast
		input  wire         s0_wvalid,   //          .wvalid
		output wire         s0_wready,   //          .wready
		output wire [5:0]   s0_bid,      //          .bid
		output wire [1:0]   s0_bresp,    //          .bresp
		output wire         s0_bvalid,   //          .bvalid
		input  wire         s0_bready,   //          .bready
		input  wire [5:0]   s0_arid,     //          .arid
		input  wire [31:0]  s0_araddr,   //          .araddr
		input  wire [7:0]   s0_arlen,    //          .arlen
		input  wire [2:0]   s0_arsize,   //          .arsize
		input  wire [1:0]   s0_arburst,  //          .arburst
		input  wire [0:0]   s0_arlock,   //          .arlock
		input  wire [3:0]   s0_arcache,  //          .arcache
		input  wire [2:0]   s0_arprot,   //          .arprot
		input  wire [3:0]   s0_arqos,    //          .arqos
		input  wire [3:0]   s0_arregion, //          .arregion
		input  wire         s0_arvalid,  //          .arvalid
		output wire         s0_arready,  //          .arready
		output wire [5:0]   s0_rid,      //          .rid
		output wire [511:0] s0_rdata,    //          .rdata
		output wire [1:0]   s0_rresp,    //          .rresp
		output wire         s0_rlast,    //          .rlast
		output wire         s0_rvalid,   //          .rvalid
		input  wire         s0_rready    //          .rready
	);

	altera_axi_bridge #(
		.USE_PIPELINE          (USE_PIPELINE),
		.USE_M0_AWID           (USE_M0_AWID),
		.USE_M0_AWREGION       (USE_M0_AWREGION),
		.USE_M0_AWLEN          (USE_M0_AWLEN),
		.USE_M0_AWSIZE         (USE_M0_AWSIZE),
		.USE_M0_AWBURST        (USE_M0_AWBURST),
		.USE_M0_AWLOCK         (USE_M0_AWLOCK),
		.USE_M0_AWCACHE        (USE_M0_AWCACHE),
		.USE_M0_AWQOS          (USE_M0_AWQOS),
		.USE_S0_AWREGION       (USE_S0_AWREGION),
		.USE_S0_AWLOCK         (USE_S0_AWLOCK),
		.USE_S0_AWCACHE        (USE_S0_AWCACHE),
		.USE_S0_AWQOS          (USE_S0_AWQOS),
		.USE_S0_AWPROT         (USE_S0_AWPROT),
		.USE_M0_WSTRB          (USE_M0_WSTRB),
		.USE_S0_WLAST          (USE_S0_WLAST),
		.USE_M0_BID            (USE_M0_BID),
		.USE_M0_BRESP          (USE_M0_BRESP),
		.USE_S0_BRESP          (USE_S0_BRESP),
		.USE_M0_ARID           (USE_M0_ARID),
		.USE_M0_ARREGION       (USE_M0_ARREGION),
		.USE_M0_ARLEN          (USE_M0_ARLEN),
		.USE_M0_ARSIZE         (USE_M0_ARSIZE),
		.USE_M0_ARBURST        (USE_M0_ARBURST),
		.USE_M0_ARLOCK         (USE_M0_ARLOCK),
		.USE_M0_ARCACHE        (USE_M0_ARCACHE),
		.USE_M0_ARQOS          (USE_M0_ARQOS),
		.USE_S0_ARREGION       (USE_S0_ARREGION),
		.USE_S0_ARLOCK         (USE_S0_ARLOCK),
		.USE_S0_ARCACHE        (USE_S0_ARCACHE),
		.USE_S0_ARQOS          (USE_S0_ARQOS),
		.USE_S0_ARPROT         (USE_S0_ARPROT),
		.USE_M0_RID            (USE_M0_RID),
		.USE_M0_RRESP          (USE_M0_RRESP),
		.USE_M0_RLAST          (USE_M0_RLAST),
		.USE_S0_RRESP          (USE_S0_RRESP),
		.M0_ID_WIDTH           (M0_ID_WIDTH),
		.S0_ID_WIDTH           (S0_ID_WIDTH),
		.DATA_WIDTH            (DATA_WIDTH),
		.WRITE_ADDR_USER_WIDTH (WRITE_ADDR_USER_WIDTH),
		.READ_ADDR_USER_WIDTH  (READ_ADDR_USER_WIDTH),
		.WRITE_DATA_USER_WIDTH (WRITE_DATA_USER_WIDTH),
		.WRITE_RESP_USER_WIDTH (WRITE_RESP_USER_WIDTH),
		.READ_DATA_USER_WIDTH  (READ_DATA_USER_WIDTH),
		.ADDR_WIDTH            (ADDR_WIDTH),
		.USE_S0_AWUSER         (USE_S0_AWUSER),
		.USE_S0_ARUSER         (USE_S0_ARUSER),
		.USE_S0_WUSER          (USE_S0_WUSER),
		.USE_S0_RUSER          (USE_S0_RUSER),
		.USE_S0_BUSER          (USE_S0_BUSER),
		.USE_M0_AWUSER         (USE_M0_AWUSER),
		.USE_M0_ARUSER         (USE_M0_ARUSER),
		.USE_M0_WUSER          (USE_M0_WUSER),
		.USE_M0_RUSER          (USE_M0_RUSER),
		.USE_M0_BUSER          (USE_M0_BUSER),
		.AXI_VERSION           (AXI_VERSION),
		.BURST_LENGTH_WIDTH    (8),
		.LOCK_WIDTH            (1)
	) axi_bridge_0 (
		.aclk        (aclk),                                 //   input,    width = 1,       clk.clk
		.aresetn     (aresetn),                              //   input,    width = 1, clk_reset.reset_n
		.s0_awid     (s0_awid),                              //   input,    width = 6,        s0.awid
		.s0_awaddr   (s0_awaddr),                            //   input,   width = 32,          .awaddr
		.s0_awlen    (s0_awlen),                             //   input,    width = 8,          .awlen
		.s0_awsize   (s0_awsize),                            //   input,    width = 3,          .awsize
		.s0_awburst  (s0_awburst),                           //   input,    width = 2,          .awburst
		.s0_awlock   (s0_awlock),                            //   input,    width = 1,          .awlock
		.s0_awcache  (s0_awcache),                           //   input,    width = 4,          .awcache
		.s0_awprot   (s0_awprot),                            //   input,    width = 3,          .awprot
		.s0_awqos    (s0_awqos),                             //   input,    width = 4,          .awqos
		.s0_awregion (s0_awregion),                          //   input,    width = 4,          .awregion
		.s0_awvalid  (s0_awvalid),                           //   input,    width = 1,          .awvalid
		.s0_awready  (s0_awready),                           //  output,    width = 1,          .awready
		.s0_wdata    (s0_wdata),                             //   input,  width = 512,          .wdata
		.s0_wstrb    (s0_wstrb),                             //   input,   width = 64,          .wstrb
		.s0_wlast    (s0_wlast),                             //   input,    width = 1,          .wlast
		.s0_wvalid   (s0_wvalid),                            //   input,    width = 1,          .wvalid
		.s0_wready   (s0_wready),                            //  output,    width = 1,          .wready
		.s0_bid      (s0_bid),                               //  output,    width = 6,          .bid
		.s0_bresp    (s0_bresp),                             //  output,    width = 2,          .bresp
		.s0_bvalid   (s0_bvalid),                            //  output,    width = 1,          .bvalid
		.s0_bready   (s0_bready),                            //   input,    width = 1,          .bready
		.s0_arid     (s0_arid),                              //   input,    width = 6,          .arid
		.s0_araddr   (s0_araddr),                            //   input,   width = 32,          .araddr
		.s0_arlen    (s0_arlen),                             //   input,    width = 8,          .arlen
		.s0_arsize   (s0_arsize),                            //   input,    width = 3,          .arsize
		.s0_arburst  (s0_arburst),                           //   input,    width = 2,          .arburst
		.s0_arlock   (s0_arlock),                            //   input,    width = 1,          .arlock
		.s0_arcache  (s0_arcache),                           //   input,    width = 4,          .arcache
		.s0_arprot   (s0_arprot),                            //   input,    width = 3,          .arprot
		.s0_arqos    (s0_arqos),                             //   input,    width = 4,          .arqos
		.s0_arregion (s0_arregion),                          //   input,    width = 4,          .arregion
		.s0_arvalid  (s0_arvalid),                           //   input,    width = 1,          .arvalid
		.s0_arready  (s0_arready),                           //  output,    width = 1,          .arready
		.s0_rid      (s0_rid),                               //  output,    width = 6,          .rid
		.s0_rdata    (s0_rdata),                             //  output,  width = 512,          .rdata
		.s0_rresp    (s0_rresp),                             //  output,    width = 2,          .rresp
		.s0_rlast    (s0_rlast),                             //  output,    width = 1,          .rlast
		.s0_rvalid   (s0_rvalid),                            //  output,    width = 1,          .rvalid
		.s0_rready   (s0_rready),                            //   input,    width = 1,          .rready
		.m0_awid     (m0_awid),                              //  output,    width = 3,        m0.awid
		.m0_awaddr   (m0_awaddr),                            //  output,   width = 32,          .awaddr
		.m0_awlen    (m0_awlen),                             //  output,    width = 8,          .awlen
		.m0_awsize   (m0_awsize),                            //  output,    width = 3,          .awsize
		.m0_awburst  (m0_awburst),                           //  output,    width = 2,          .awburst
		.m0_awlock   (m0_awlock),                            //  output,    width = 1,          .awlock
		.m0_awcache  (m0_awcache),                           //  output,    width = 4,          .awcache
		.m0_awprot   (m0_awprot),                            //  output,    width = 3,          .awprot
		.m0_awqos    (m0_awqos),                             //  output,    width = 4,          .awqos
		.m0_awregion (m0_awregion),                          //  output,    width = 4,          .awregion
		.m0_awvalid  (m0_awvalid),                           //  output,    width = 1,          .awvalid
		.m0_awready  (m0_awready),                           //   input,    width = 1,          .awready
		.m0_wdata    (m0_wdata),                             //  output,  width = 512,          .wdata
		.m0_wstrb    (m0_wstrb),                             //  output,   width = 64,          .wstrb
		.m0_wlast    (m0_wlast),                             //  output,    width = 1,          .wlast
		.m0_wvalid   (m0_wvalid),                            //  output,    width = 1,          .wvalid
		.m0_wready   (m0_wready),                            //   input,    width = 1,          .wready
		.m0_bid      (m0_bid),                               //   input,    width = 3,          .bid
		.m0_bresp    (m0_bresp),                             //   input,    width = 2,          .bresp
		.m0_bvalid   (m0_bvalid),                            //   input,    width = 1,          .bvalid
		.m0_bready   (m0_bready),                            //  output,    width = 1,          .bready
		.m0_arid     (m0_arid),                              //  output,    width = 3,          .arid
		.m0_araddr   (m0_araddr),                            //  output,   width = 32,          .araddr
		.m0_arlen    (m0_arlen),                             //  output,    width = 8,          .arlen
		.m0_arsize   (m0_arsize),                            //  output,    width = 3,          .arsize
		.m0_arburst  (m0_arburst),                           //  output,    width = 2,          .arburst
		.m0_arlock   (m0_arlock),                            //  output,    width = 1,          .arlock
		.m0_arcache  (m0_arcache),                           //  output,    width = 4,          .arcache
		.m0_arprot   (m0_arprot),                            //  output,    width = 3,          .arprot
		.m0_arqos    (m0_arqos),                             //  output,    width = 4,          .arqos
		.m0_arregion (m0_arregion),                          //  output,    width = 4,          .arregion
		.m0_arvalid  (m0_arvalid),                           //  output,    width = 1,          .arvalid
		.m0_arready  (m0_arready),                           //   input,    width = 1,          .arready
		.m0_rid      (m0_rid),                               //   input,    width = 3,          .rid
		.m0_rdata    (m0_rdata),                             //   input,  width = 512,          .rdata
		.m0_rresp    (m0_rresp),                             //   input,    width = 2,          .rresp
		.m0_rlast    (m0_rlast),                             //   input,    width = 1,          .rlast
		.m0_rvalid   (m0_rvalid),                            //   input,    width = 1,          .rvalid
		.m0_rready   (m0_rready),                            //  output,    width = 1,          .rready
		.s0_awuser   (32'b00000000000000000000000000000000), // (terminated),                         
		.s0_wuser    (32'b00000000000000000000000000000000), // (terminated),                         
		.s0_buser    (),                                     // (terminated),                         
		.s0_aruser   (32'b00000000000000000000000000000000), // (terminated),                         
		.s0_ruser    (),                                     // (terminated),                         
		.m0_awuser   (),                                     // (terminated),                         
		.m0_wuser    (),                                     // (terminated),                         
		.m0_buser    (32'b00000000000000000000000000000000), // (terminated),                         
		.m0_aruser   (),                                     // (terminated),                         
		.m0_ruser    (32'b00000000000000000000000000000000), // (terminated),                         
		.m0_wid      (),                                     // (terminated),                         
		.s0_wid      (6'b000000)                             // (terminated),                         
	);

endmodule