dakies/OSS_Verilog huggingface dataset:
module lms_ctr_irq_mapper
(
    // -------------------
    // Clock & Reset
    // -------------------
    input clk,
    input reset,

    // -------------------
    // IRQ Receivers
    // -------------------
    input                receiver0_irq,
    input                receiver1_irq,
    input                receiver2_irq,
    input                receiver3_irq,
    input                receiver4_irq,

    // -------------------
    // Command Source (Output)
    // -------------------
    output reg [31 : 0] sender_irq
);


    always @* begin
	sender_irq = 0;

        sender_irq[0] = receiver0_irq;
        sender_irq[1] = receiver1_irq;
        sender_irq[2] = receiver2_irq;
        sender_irq[3] = receiver3_irq;
        sender_irq[4] = receiver4_irq;
    end

endmodule
module lms_ctr_mm_interconnect_0_cmd_demux_001
(
    // -------------------
    // Sink
    // -------------------
    input  [1-1      : 0]   sink_valid,
    input  [103-1    : 0]   sink_data, // ST_DATA_W=103
    input  [15-1 : 0]   sink_channel, // ST_CHANNEL_W=15
    input                         sink_startofpacket,
    input                         sink_endofpacket,
    output                        sink_ready,

    // -------------------
    // Sources 
    // -------------------
    output reg                      src0_valid,
    output reg [103-1    : 0] src0_data, // ST_DATA_W=103
    output reg [15-1 : 0] src0_channel, // ST_CHANNEL_W=15
    output reg                      src0_startofpacket,
    output reg                      src0_endofpacket,
    input                           src0_ready,

    output reg                      src1_valid,
    output reg [103-1    : 0] src1_data, // ST_DATA_W=103
    output reg [15-1 : 0] src1_channel, // ST_CHANNEL_W=15
    output reg                      src1_startofpacket,
    output reg                      src1_endofpacket,
    input                           src1_ready,


    // -------------------
    // Clock & Reset
    // -------------------
    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
    input clk,
    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
    input reset

);

    localparam NUM_OUTPUTS = 2;
    wire [NUM_OUTPUTS - 1 : 0] ready_vector;

    // -------------------
    // Demux
    // -------------------
    always @* begin
        src0_data          = sink_data;
        src0_startofpacket = sink_startofpacket;
        src0_endofpacket   = sink_endofpacket;
        src0_channel       = sink_channel >> NUM_OUTPUTS;

        src0_valid         = sink_channel[0] && sink_valid;

        src1_data          = sink_data;
        src1_startofpacket = sink_startofpacket;
        src1_endofpacket   = sink_endofpacket;
        src1_channel       = sink_channel >> NUM_OUTPUTS;

        src1_valid         = sink_channel[1] && sink_valid;

    end

    // -------------------
    // Backpressure
    // -------------------
    assign ready_vector[0] = src0_ready;
    assign ready_vector[1] = src1_ready;

    assign sink_ready = |(sink_channel & {{13{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});

endmodule
module lms_ctr_nios2_cpu_custom_instruction_master_comb_xconnect
(
    // -------------------
    // Custom instruction masters
    // -------------------
    output [31 : 0] ci_master0_dataa,
    output [31 : 0] ci_master0_datab,
    input  [31 : 0] ci_master0_result,
    output [ 7 : 0] ci_master0_n,
    output          ci_master0_readra,
    output          ci_master0_readrb,
    output          ci_master0_writerc,
    output [ 4 : 0] ci_master0_a,
    output [ 4 : 0] ci_master0_b,
    output [ 4 : 0] ci_master0_c,
    output [31 : 0] ci_master0_ipending,
    output          ci_master0_estatus,


    // -------------------
    // Custom instruction slave
    // -------------------
    input  [31 : 0] ci_slave_dataa,
    input  [31 : 0] ci_slave_datab,
    output [31 : 0] ci_slave_result,
    input  [ 7 : 0] ci_slave_n,
    input           ci_slave_readra,
    input           ci_slave_readrb,
    input           ci_slave_writerc,
    input  [ 4 : 0] ci_slave_a,
    input  [ 4 : 0] ci_slave_b,
    input  [ 4 : 0] ci_slave_c,
    input  [31 : 0] ci_slave_ipending,
    input           ci_slave_estatus

);

    wire select0;

    // -------------------------------------------------------
    // Wire non-control signals through to each master
    // -------------------------------------------------------
    assign  ci_master0_dataa    = ci_slave_dataa;
    assign  ci_master0_datab    = ci_slave_datab;
    assign  ci_master0_n        = ci_slave_n;
    assign  ci_master0_a        = ci_slave_a;
    assign  ci_master0_b        = ci_slave_b;
    assign  ci_master0_c        = ci_slave_c;
    assign  ci_master0_ipending = ci_slave_ipending;
    assign  ci_master0_estatus  = ci_slave_estatus;


    // -------------------------------------------------------
    // Figure out which output is selected, and use that to
    // gate control signals
    // -------------------------------------------------------
    assign select0 = ci_slave_n >= 0 && ci_slave_n < 1;

    assign ci_master0_readra  = (select0 && ci_slave_readra);
    assign ci_master0_readrb  = (select0 && ci_slave_readrb);
    assign ci_master0_writerc = (select0 && ci_slave_writerc);


    // -------------------------------------------------------
    // Use the select signal to figure out which result to mux
    // back
    // -------------------------------------------------------
    assign ci_slave_result = {32{ select0 }} & ci_master0_result
    ;


endmodule
module factory_mm_interconnect_0_cmd_mux
(
    // ----------------------
    // Sinks
    // ----------------------
    input                       sink0_valid,
    input [98-1   : 0]  sink0_data,
    input [6-1: 0]  sink0_channel,
    input                       sink0_startofpacket,
    input                       sink0_endofpacket,
    output                      sink0_ready,


    // ----------------------
    // Source
    // ----------------------
    output                      src_valid,
    output [98-1    : 0] src_data,
    output [6-1 : 0] src_channel,
    output                      src_startofpacket,
    output                      src_endofpacket,
    input                       src_ready,

    // ----------------------
    // Clock & Reset
    // ----------------------
    input clk,
    input reset
);
    localparam PAYLOAD_W        = 98 + 6 + 2;
    localparam NUM_INPUTS       = 1;
    localparam SHARE_COUNTER_W  = 1;
    localparam PIPELINE_ARB     = 1;
    localparam ST_DATA_W        = 98;
    localparam ST_CHANNEL_W     = 6;
    localparam PKT_TRANS_LOCK   = 61;

    assign	src_valid			=  sink0_valid;
    assign	src_data			=  sink0_data;
    assign	src_channel			=  sink0_channel;
    assign	src_startofpacket  	        =  sink0_startofpacket;
    assign	src_endofpacket		        =  sink0_endofpacket;
    assign	sink0_ready			=  src_ready;
endmodule
module factory_mm_interconnect_0_rsp_demux
(
    // -------------------
    // Sink
    // -------------------
    input  [1-1      : 0]   sink_valid,
    input  [98-1    : 0]   sink_data, // ST_DATA_W=98
    input  [6-1 : 0]   sink_channel, // ST_CHANNEL_W=6
    input                         sink_startofpacket,
    input                         sink_endofpacket,
    output                        sink_ready,

    // -------------------
    // Sources 
    // -------------------
    output reg                      src0_valid,
    output reg [98-1    : 0] src0_data, // ST_DATA_W=98
    output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
    output reg                      src0_startofpacket,
    output reg                      src0_endofpacket,
    input                           src0_ready,


    // -------------------
    // Clock & Reset
    // -------------------
    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
    input clk,
    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
    input reset

);

    localparam NUM_OUTPUTS = 1;
    wire [NUM_OUTPUTS - 1 : 0] ready_vector;

    // -------------------
    // Demux
    // -------------------
    always @* begin
        src0_data          = sink_data;
        src0_startofpacket = sink_startofpacket;
        src0_endofpacket   = sink_endofpacket;
        src0_channel       = sink_channel >> NUM_OUTPUTS;

        src0_valid         = sink_channel[0] && sink_valid;

    end

    // -------------------
    // Backpressure
    // -------------------
    assign ready_vector[0] = src0_ready;

    assign sink_ready = |(sink_channel & {{5{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});

endmodule
module factory_mm_interconnect_0_router_default_decode
  #(
     parameter DEFAULT_CHANNEL = 4,
               DEFAULT_WR_CHANNEL = -1,
               DEFAULT_RD_CHANNEL = -1,
               DEFAULT_DESTID = 4 
   )
  (output [84 - 82 : 0] default_destination_id,
   output [6-1 : 0] default_wr_channel,
   output [6-1 : 0] default_rd_channel,
   output [6-1 : 0] default_src_channel
  );

  assign default_destination_id = 
    DEFAULT_DESTID[84 - 82 : 0];

  generate
    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
      assign default_src_channel = '0;
    end
    else begin : default_channel_assignment
      assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
    end
  endgenerate

  generate
    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
      assign default_wr_channel = '0;
      assign default_rd_channel = '0;
    end
    else begin : default_rw_channel_assignment
      assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
      assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
    end
  endgenerate

endmodule
module factory_mm_interconnect_0_router_001_default_decode
  #(
     parameter DEFAULT_CHANNEL = 0,
               DEFAULT_WR_CHANNEL = -1,
               DEFAULT_RD_CHANNEL = -1,
               DEFAULT_DESTID = 0 
   )
  (output [84 - 82 : 0] default_destination_id,
   output [6-1 : 0] default_wr_channel,
   output [6-1 : 0] default_rd_channel,
   output [6-1 : 0] default_src_channel
  );

  assign default_destination_id = 
    DEFAULT_DESTID[84 - 82 : 0];

  generate
    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
      assign default_src_channel = '0;
    end
    else begin : default_channel_assignment
      assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
    end
  endgenerate

  generate
    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
      assign default_wr_channel = '0;
      assign default_rd_channel = '0;
    end
    else begin : default_rw_channel_assignment
      assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
      assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
    end
  endgenerate

endmodule
module AXILITE #
	(
		parameter C_S00_BASEADDR        = 0,
		// Parameters of Axi Slave Bus Interface S00_AXI
		parameter C_S00_AXI_DATA_WIDTH	= 32,
		parameter C_S00_AXI_ADDR_WIDTH	= 32
	)
	(
		// Ports of Axi Slave Bus Interface S00_AXI
		input wire  s00_axi_aclk,
		input wire  s00_axi_aresetn,
		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
		input wire  s00_axi_awvalid,
		output wire  s00_axi_awready,
		input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
		input wire  s00_axi_wvalid,
		output wire  s00_axi_wready,
		output wire [1 : 0] s00_axi_bresp,
		output wire  s00_axi_bvalid,
		input wire  s00_axi_bready,
		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
		input wire  s00_axi_arvalid,
		output wire  s00_axi_arready,
		output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
		output wire [1 : 0] s00_axi_rresp,
		output wire  s00_axi_rvalid,
		input wire  s00_axi_rready
	);
// Instantiation of Axi Bus Interface S00_AXI
	AXILITE_S00 # ( 
		.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
		.C_S_AXI_BASEADDR(C_S00_BASEADDR),
		.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
	) AXILITE_S00_inst (
		.S_AXI_ACLK(s00_axi_aclk),
		.S_AXI_ARESETN(s00_axi_aresetn),
		.S_AXI_AWADDR(s00_axi_awaddr),
		.S_AXI_AWVALID(s00_axi_awvalid),
		.S_AXI_AWREADY(s00_axi_awready),
		.S_AXI_WDATA(s00_axi_wdata),
		.S_AXI_WVALID(s00_axi_wvalid),
		.S_AXI_WREADY(s00_axi_wready),
		.S_AXI_BRESP(s00_axi_bresp),
		.S_AXI_BVALID(s00_axi_bvalid),
		.S_AXI_BREADY(s00_axi_bready),
		.S_AXI_ARADDR(s00_axi_araddr),
		.S_AXI_ARVALID(s00_axi_arvalid),
		.S_AXI_ARREADY(s00_axi_arready),
		.S_AXI_RDATA(s00_axi_rdata),
		.S_AXI_RRESP(s00_axi_rresp),
		.S_AXI_RVALID(s00_axi_rvalid),
		.S_AXI_RREADY(s00_axi_rready)
	);
	endmodule
module button_debouncer
#(parameter CNT_WIDTH = 16)
(   input       clk,
    input       reset,
    input       key,  
 
    output reg  key_state_o,  
    output reg  key_down_o,  
    output reg  key_up_o   
);
 
// Синхронизируем вход с текущим тактовым доменом.
reg  [1:0] key_reg;
always @ (posedge clk)
begin
    if (reset)
        key_reg <= 2'b00;
    else
        key_reg <= {key_reg[0], ~key};
end
 
reg [CNT_WIDTH - 1:0] key_count;

wire key_change_f = (key_state_o != key_reg[1]);
wire key_cnt_max = &key_count;    
 
always @(posedge clk)
begin
    if (reset)
    begin
        key_count <= 0;
        key_state_o <= 0;
    end 
    else if(key_change_f)    
        begin
            key_count <= key_count + 'd1;  
            if(key_cnt_max) 
                key_state_o <= ~key_state_o;  
        end
        else  
            key_count <= 0;
end
 
always @(posedge clk)
begin
    key_down_o <= key_change_f & key_cnt_max & ~key_state_o;
    key_up_o   <= key_change_f & key_cnt_max &  key_state_o;
end
 
endmodule
module sys_array_cell
#(parameter DATA_WIDTH = 8)
(   input                                     clk,
    input                                     reset_n,
    input                                     param_load,
    input      signed [DATA_WIDTH - 1:0]      input_data,
    input      signed [2 * DATA_WIDTH - 1:0]  prop_data,
    input      signed [DATA_WIDTH - 1:0]      param_data,
     
    output reg signed [2 * DATA_WIDTH - 1:0]  out_data,
    output reg signed [DATA_WIDTH - 1:0]      prop_param
);

reg signed [DATA_WIDTH - 1:0] par;

always @(posedge clk)
begin
    if (~reset_n) begin // Сброс
        out_data <= {2 * DATA_WIDTH{1'b0}};
        par <= {DATA_WIDTH{1'b0}};
    end
    else if (param_load) begin // Загрузка параметра
        par <= param_data;
    end
    else begin // Вычисление данных
        // Задание 1. Реализуйте основные вычисления модуля.        
    end
end
    
endmodule
module seven_segment_4_digits
(
    input             clock,
    input             reset,
    input      [15:0] number,

    output reg [ 7:0] abcdefgh,
    output reg [ 3:0] digit
);

function [7:0] bcd_to_seg (input [3:0] bcd);
    case (bcd)
        'h0: bcd_to_seg = 'b11000000;
        'h1: bcd_to_seg = 'b11111001;
        'h2: bcd_to_seg = 'b10100100;
        'h3: bcd_to_seg = 'b10110000;
        'h4: bcd_to_seg = 'b10011001;
        'h5: bcd_to_seg = 'b10010010;
        'h6: bcd_to_seg = 'b10000010;
        'h7: bcd_to_seg = 'b11111000;
        'h8: bcd_to_seg = 'b10000000;
        'h9: bcd_to_seg = 'b10010000;
        'ha: bcd_to_seg = 'b10001000;
        'hb: bcd_to_seg = 'b10000011;
        'hc: bcd_to_seg = 'b11000110;
        'hd: bcd_to_seg = 'b10100001;
        'he: bcd_to_seg = 'b10000110;
        'hf: bcd_to_seg = 'b10001110;
    endcase
endfunction

reg [15:0] cnt;

always @ (posedge clock)
    if (reset)
        cnt <= 16'd0;
    else
        cnt <= cnt + 16'd1;

reg [1:0] i;

always @ (posedge clock)
begin
    if (reset)
    begin
        abcdefgh <=   bcd_to_seg(0);
        digit    <= ~ 4'b1;

        i <= 0;
    end
    else if (cnt == 16'b0)
    begin
        abcdefgh <=   bcd_to_seg(number [i * 4 +: 4]);
        digit    <= ~ (4'b1 << i);

        i <= i + 1;
    end
end

endmodule
module read_data 
#(parameter DATA_WIDTH=8)(
    input                       clk,
    input                       reset_n,
    input                       change,

    output [2:0]                code,

    output [DATA_WIDTH-1:0]     inp,
    output [DATA_WIDTH-1:0]     par,
    output [2*DATA_WIDTH-1:0]   prop,
    output [2*DATA_WIDTH-1:0]   result    
 );


reg [0:7] [DATA_WIDTH-1:0]   data_inp;
reg [0:7] [DATA_WIDTH-1:0]   data_param;
reg [0:7] [2*DATA_WIDTH-1:0] data_prop;
reg [0:7] [2*DATA_WIDTH-1:0] data_result;

reg [2:0] code_b;

always @(posedge clk)
begin
    if (~reset_n)
    begin
        code_b = 'd0;
        // Индексация    0      1      2      3      4      5      6      7
        data_inp    = {8'hf1, 8'hf7, 8'hc8, 8'h4c, 8'h50, 8'hd9, 8'h32, 8'h85};
        data_param  = {8'hc8, 8'h6d, 8'h83, 8'hd1, 8'hd7, 8'h4b, 8'h17, 8'h82};
        // Индексация      0         1         2         3         4         5         6         7
        data_prop   = {16'h001b, 16'h0031, 16'h00de, 16'h0032, 16'h00b9, 16'h0057, 16'h00d7, 16'h00e6};
        data_result = {16'hbc63, 16'h695c, 16'h6736, 16'h3e3e, 16'h43e9, 16'h3fea, 16'h0555, 16'h4470};
    end
    else
        if (change)
            code_b = code_b + 1;
end

assign inp    = data_inp[code_b];
assign par    = data_param[code_b];
assign prop   = data_prop[code_b];
assign result = data_result[code_b];


// Для RZRD
assign code = ~{code_b[0], code_b[1], code_b[2]};
// Для omdazz
//assign code = ~code_b;
 
endmodule
module shift_reg
#(parameter DATA_WIDTH=8,
parameter LENGTH=4)
(
    input                                    clk,
    input                                    reset_n,
    input                   [1:0]            ctrl_code,
    input      [0:LENGTH-1] [DATA_WIDTH-1:0] data_in,
    input                   [DATA_WIDTH-1:0] data_write,

    output reg              [DATA_WIDTH-1:0] data_read,
    output reg [0:LENGTH-1] [DATA_WIDTH-1:0] data_out
);

localparam REG_UPLOAD = 0,
           REG_LOAD   = 1,
           REG_WRITE  = 2,
           REG_READ   = 3;

reg en;

reg [0:LENGTH - 1] [DATA_WIDTH - 1:0] contents;

integer i;
always @(posedge clk)
begin
    if (~reset_n)
    begin
        for(i = 0; i < LENGTH; i = i + 1) begin : for_reset_n
            contents[i] <= {DATA_WIDTH{1'b0}};
        end 
        en <= 1'b1;
    end
    else
    begin
        if (en)
        begin
            case (ctrl_code)
                REG_UPLOAD: data_out <= contents;
                REG_LOAD: contents <= data_in;
                REG_READ: 
                begin 
                    data_read <= contents[0]; 
                    for (i = 0; i < LENGTH - 1; i = i + 1) begin : for_REG_READ
                        contents[i] <= contents[i+1];
                    end
                    contents[LENGTH-1] <= contents[0];        
                end
                REG_WRITE: 
                begin
                    for (i = 0; i < LENGTH - 1; i = i + 1) begin : for_REG_WRITE
                        contents[i] <= contents[i+1];
                    end
                    contents[LENGTH-1] <= data_write;   
                end
            endcase
        end
    end
end

endmodule
module sys_array_basic
#(
    parameter DATA_WIDTH = 8,
    parameter ARRAY_W_W  = 4, //Строк в массиве весов
    parameter ARRAY_W_L  = 4, //Столбцов в массиве весов
    parameter ARRAY_A_W  = 4, //Строк в массиве данных
    parameter ARRAY_A_L  = 4) //Столбцов в массиве данных
(   input                                                           clk,
    input                                                           reset_n,
    input                                                           weights_load,
    input                   [0:ARRAY_A_W-1]     [DATA_WIDTH-1:0]    input_data,
    input [0:ARRAY_W_W-1]   [0:ARRAY_W_L-1]     [DATA_WIDTH-1:0]    weight_data,

    output                  [0:ARRAY_W_W-1]     [2*DATA_WIDTH-1:0]  output_data
);

wire [0:ARRAY_W_W-1] [0:ARRAY_W_L-1] [2*DATA_WIDTH-1:0] temp_output_data;
wire [0:ARRAY_W_W-1] [0:ARRAY_W_L-1] [DATA_WIDTH-1:0] propagate_module;

genvar i;
genvar j;
genvar t;
// Генерация массива вычислительных ячеек
// Задание 2. Допишите необходимые входные и выходные сигналы.
generate
    for(i = 0; i < ARRAY_W_W; i = i + 1) begin : generate_array_proc
         for (j = 0; j < ARRAY_W_L; j = j + 1) begin : generate_array_proc2
         if ((i == 0) && (j == 0)) // i - строка, j - столбец
         begin
              sys_array_cell #(.DATA_WIDTH(DATA_WIDTH)) cell_inst ( 
              .clk(clk),
              .reset_n(reset_n),
              .param_load(weights_load),
              .input_data(input_data[0]),
              .prop_data({2*DATA_WIDTH{1'b0}}),
              .param_data(weight_data[0][0]),
              .out_data(temp_output_data[0][0]),
              .prop_param(propagate_module[0][0])
              );
         end
         else if (i == 0) // Первая строка
         begin
              sys_array_cell #(.DATA_WIDTH(DATA_WIDTH)) cell_inst (
              .clk(),
              .reset_n(),
              .param_load(),
              .input_data(),
              .prop_data(),
              .param_data(),
              .out_data(),
              .prop_param()
              );
         end
         else if (j == 0) // Первый столбец
         begin
              sys_array_cell #(.DATA_WIDTH(DATA_WIDTH)) cell_inst (
              .clk(),
              .reset_n(),
              .param_load(),
              .input_data(),
              .prop_data(),
              .param_data(),
              .out_data(),
              .prop_param()
              );
         end
         else
         begin // Остальные элементы
              sys_array_cell #(.DATA_WIDTH(DATA_WIDTH)) cell_inst (
              .clk(),
              .reset_n(),
              .param_load(),
              .input_data(),
              .prop_data(),
              .param_data(),
              .out_data(),
              .prop_param()
              );
         end
         end
    end
endgenerate

// Генерация связей для выходных данных
generate
    for (t=0;t<ARRAY_W_W;t=t+1) begin: output_prop
        assign output_data[t] = temp_output_data[t][ARRAY_W_L-1];
    end
endgenerate

endmodule
module upsizing
# (
  parameter n = 5, nb = n * 8
)
(
  input  wire             aclk,
  input  wire             aresetn,

  input  wire [nb - 1:0]  in_tdata,
  input  wire             in_tvalid,
  output wire             in_tready,

  output wire [nb*2- 1:0] out_tdata,
  output wire             out_tvalid,
  input  wire             out_tready
);

logic             flag_hf;
logic [nb-1:0]    reg_hf;

always @(posedge aclk)
  if( ~aresetn )
    flag_hf <= #1 '0;
  else if( in_tvalid & in_tready )
    flag_hf <= #1 ~flag_hf;

always  @(posedge aclk) 
  if( in_tvalid & in_tready & ~flag_hf )
    reg_hf <= #1 in_tdata;

assign out_tdata = { reg_hf, in_tdata };

assign in_tready = ~flag_hf | out_tready;

assign out_tvalid = flag_hf & in_tvalid;





endmodule
module downsizing
# (
  parameter n = 5, nb = n * 8
)
(
  input  wire             aclk,
  input  wire             aresetn,

  input  wire [nb*2 - 1:0]  in_tdata,
  input  wire             in_tvalid,
  output wire             in_tready,

  output wire [nb - 1:0] out_tdata,
  output wire             out_tvalid,
  input  wire             out_tready
);

logic             flag_hf;


always @(posedge aclk)
  if( ~aresetn )
    flag_hf <= #1 '0;
  else if( out_tvalid & out_tready )
    flag_hf <= #1 ~flag_hf;



assign   out_tdata = (flag_hf) ?  in_tdata[0+:nb] : in_tdata[nb+:nb];

assign in_tready = flag_hf & out_tready;

assign out_tvalid = in_tvalid;

  


endmodule
module fifo_w8
#(
    parameter               WIDTH = 16
)    
(
    input   wire                    reset_p,    //! 1 - reset
    input   wire                    clk,        //! clock

    input   wire    [WIDTH-1:0]     data_i,
    input   wire                    data_we,

    output  wire    [WIDTH-1:0]     data_o,
    input   wire                    data_rd,

    output  wire                    full,
    output  wire                    empty

);

logic   [WIDTH-1:0]         mem[8];

logic   [3:0]               cnt_wr;
logic   [3:0]               cnt_rd;
logic                       rstp;

always @(posedge clk) begin

    rstp <= #1 reset_p;

    if( ~full & data_we ) begin
        mem[cnt_wr[2:0]] <= #1 data_i;
        cnt_wr <= #1 cnt_wr + 1;
    end

    if( ~empty & data_rd ) begin
        cnt_rd <= #1 cnt_rd + 1;
    end

    if( rstp ) begin
        cnt_wr      <= # 2'b0000;
        cnt_rd      <= # 2'b0000;
    end 

end

//assign  full    = (cnt_wr_next==cnt_rd) ? 1 : 0;
assign  full    = (cnt_rd[2:0]==cnt_wr[2:0] && cnt_rd[3]!=cnt_wr[3]) ? 1 : 0;
assign  empty   = (cnt_wr==cnt_rd) ? 1 : 0;

assign  data_o  = mem[cnt_rd[2:0]];

endmodule
module user_axis
# (
  parameter                 n = 5,          //! Number of bytes
  parameter                 nb = n * 8      //! Number of bits
)
(
  input  wire               clk,            //! clok
  input  wire               reset_n,        //! 0 - reset

  input  wire [nb*2 - 1:0]  in_tdata,       //! input data
  input  wire               in_tvalid,      //! 1 - input data is valid
  output wire               in_tready,      //! 1 - ready for get data

  output wire [nb - 1:0]    out_tdata,      //! output data
  output wire               out_tvalid,     //! 1 - output data is valid
  input  wire               out_tready      //! 1 - ready for get data
);

assign out_tdata    = in_tdata;
assign out_tvalid   = in_tvalid  & reset_n;
assign in_tready    = out_tready & reset_n;

endmodule
module other_single_port_ram21
#( parameter  RAMLENGTH=800, //RAMLENGTH*DATAWIDTH = 4800 = 80x60 RAM RESOLUTION
				  RAM_INITIAL_VALUE=6'b111111, //default value for memreset
				  DATA_WIDTH=6,
				  ADDR_WIDTH=10
 )
(
	input [DATA_WIDTH-1:0]data,		//RAM words' write input			
	input [ADDR_WIDTH-1:0] addr,				 //ln(RAMLENGTH)/ln(2)
	input we, clk, memenable,
	input [ADDR_WIDTH:0] resetcnt,
	output [DATA_WIDTH-1:0]q	//RAM words' read input
);

	//memreset variable
	//integer i;

	// Declare the RAM variable
	
	(* ramstyle = "M9K" *) reg  [DATA_WIDTH-1:0]ramblock[3*RAMLENGTH-1:0] ;
	//(* ramstyle = "M9K" *) - synthesis attribute for making ramblocks of Altera M9K memory blocks
	// !!! Not sure in its usefullness
	
	// Variable to hold the registered read address, write data, and we
	reg [ADDR_WIDTH-1:0] addr_reg;
	reg [DATA_WIDTH-1:0] data_reg;
	reg we_reg;

    wire [ADDR_WIDTH-1:0] addr_x;
    wire [DATA_WIDTH-1:0] data_x;
    wire                  we_x;

    
	
	// always @ (posedge clk)begin
	// //memory reset
	// if(memreset) counter<='d800;
	// else if(counter!=0) 
	// 	begin 
	// 	counter<=counter-1;
	// 	ramblock[counter-1]<=RAM_INITIAL_VALUE;
	// 	end
	// //R/W operations 
	// else if(enable) begin
	// 		addr_reg <= addr;
	// 		data_reg <= data;
	// 		we_reg<=we;
	// 	// Write
	// 		if (we_reg) begin
	// 			ramblock[addr_reg]<=data_reg;
	// 		end
	// end
    // end

    assign addr_x = (memenable) ? addr : resetcnt;
    assign data_x = (memenable) ? data : '0;
    assign we_x   = (memenable) ? we   : 1;
	 
	always @ (posedge clk)begin
	addr_reg <= addr_x;
	we_reg<=we_x;
	data_reg <= data_x;
	if (we_reg) begin ramblock[addr_reg]<=data_reg;
					end
	end
	
	// Continuous assignment implies read returns NEW data.
	// This is the natural behavior of the TriMatrix memory
	// blocks in Single Port mode.  
	assign q = ramblock[addr_reg];
	
endmodule
module TestBench();
parameter RAMLENGTH  = 800,
		  DATA_WIDTH=6,
		  ADDR_WIDTH=10,
		  V_BOTTOM = 1,
          V_SYNC   = 3,
          V_TOP    = 30,
		  H_FRONT  =  80,
          H_SYNC   =  136,
          H_BACK   =  216,
		  RESOLUTION_H = 640,
		  RESOLUTION_V = 480,
		  X_WIRE_WIDTH = $clog2 (RESOLUTION_H+H_FRONT+H_SYNC+H_BACK),
		  Y_WIRE_WIDTH = $clog2 (RESOLUTION_V+V_BOTTOM+V_SYNC+V_TOP);

reg display_on, clk, memreset,reset_n,fifoempty;
reg [ADDR_WIDTH-1:0] resetcnt;
reg [X_WIRE_WIDTH-1:0] hpos;
reg [Y_WIRE_WIDTH-1:0] vpos;
reg [2:0] RGBin,RGB;

int hpos_check[10];
int vpos_check[10];
int RGB_check[10];

RGBMemory_top
	 #(
		.RAMLENGTH(RAMLENGTH), //RAMLENGTH*DATAWIDTH = 4800 = 80x60 RAM RESOLUTION
		.DATA_WIDTH(DATA_WIDTH),
		.X_WIRE_WIDTH(X_WIRE_WIDTH),
		.Y_WIRE_WIDTH(Y_WIRE_WIDTH),
		.ADDR_WIDTH(ADDR_WIDTH),
		.RESOLUTION_H(RESOLUTION_H),
		.RESOLUTION_V(RESOLUTION_V)
	 )
	 FrameBuffer
	 (
		.display_on(display_on),
		.clk(clk),
		.memreset(memreset),
		.reset_n(~reset_n),
		.resetcnt(resetcnt),
		.RGBin(RGBin),
		.hpos(hpos),
		.vpos(vpos),
		.RGB(RGB),
		.fifoempty(fifoempty)
	 );

always #5 clk=~clk;

initial begin
fifoempty=0;
clk=0;
display_on=1;
RGBin=0;
resetcnt=0;
memreset=0;
hpos=0;
vpos=0;
RGB=0;
reset_n=0;
#20;
reset_n=1;
for(integer i=0; i<800; i++) begin
resetcnt<=i;
#10;
end
#15;
memreset=1;
#100
display_on=0;
vpos=0;
for(integer i=0; i<5; i++) begin
hpos=i;
if((i%2)==0) RGBin=3'b111;
else RGBin=3'b000;
#50;
end
#120;
display_on=1;
RGBin=0;
vpos=0;
for(integer i=0;i<31;i++) begin
hpos=i; #10;
end
#120
display_on=0;
vpos=1;
for(integer i=0; i<5; i++) begin
hpos=i;
if((i%2)==0) RGBin=3'b111;
else RGBin=3'b000;
#50;
end
#120
display_on=1;
RGBin=0;
vpos=0;
for(integer i=0;i<31;i++) begin
hpos=i; #10;
end
#120
display_on=0;
vpos=2;
for(integer i=0; i<5; i++) begin
hpos=i;
if((i%2)==0) RGBin=3'b111;
else RGBin=3'b000;
#50;
end
#120
display_on=1;
RGBin=0;
vpos=0;
for(integer i=0;i<31;i++) begin
hpos=i; #10;
end
#120
hpos=0;
vpos=0;



/*#100
display_on=0;
for(integer i=0; i<10; i++)begin
	hpos=$urandom_range(0,79);
	vpos=$urandom_range(0,59);
	RGBin=$urandom_range(0,7);
	hpos_check[i]=hpos;
	vpos_check[i]=vpos;
	RGB_check[i]=RGBin;
	#50;
end
#10
display_on=1;
for(integer i=0; i<10; i++)begin
hpos=hpos_check[i]*8;
vpos=vpos_check[i]*8;
#10;
if(RGB!=RGB_check[i]) $display("Wrong data on the coordinates hpos=%d, vpos=%d. Supposed to be %d ",hpos,vpos, RGB_check[i]);
end
#10*/
$stop;

end

endmodule
module Top_FB_TestBench();

reg clk, reset_n;

top DUT (
.clk(clk),
.reset_n(reset_n)
);

always #5 clk=~clk;

initial begin
clk=1;
reset_n=0;
#20;
reset_n=1;

end

endmodule
module FIFOTestBench();
parameter RESOLUTION_H = 1280,
		  RESOLUTION_V = 960,
		  V_BOTTOM = 1,
          V_SYNC   = 3,
          V_TOP    = 30,
		  H_FRONT  =  80,
          H_SYNC   =  136,
          H_BACK   =  216,
          X_WIRE_WIDTH = $clog2 (RESOLUTION_H+H_FRONT+H_SYNC+H_BACK),
		  Y_WIRE_WIDTH = $clog2 (RESOLUTION_V+V_BOTTOM+V_SYNC+V_TOP),
		  FIFODEPTH=10;

reg clk,reset_n,push,pop,empty,full;
reg [X_WIRE_WIDTH-1:0] hpos,hpos_read;
reg [Y_WIRE_WIDTH-1:0] vpos,vpos_read;
reg [2:0] RGBin,RGB;

//int hpos_check[10];
//int vpos_check[10];
//int RGB_check[10];

FIFO_top
#(
	.RESOLUTION_H(RESOLUTION_H),
	.RESOLUTION_V(RESOLUTION_V),
	.V_BOTTOM(V_BOTTOM),
    .V_SYNC(V_SYNC),
    .V_TOP(V_TOP),
	.H_FRONT(H_FRONT),
    .H_SYNC(H_SYNC),
    .H_BACK(H_BACK),
	.FIFODEPTH(FIFODEPTH)
)
DUT (
  .clk(clk),
  .rst(~reset_n),
  .push(push),
  .toppop(pop),
  .hpos_write(hpos),
  .vpos_write(vpos),
  .RGB_write(RGBin),
  .hpos_read(hpos_read),
  .vpos_read(vpos_read),
  .RGB_read(RGB),
  .empty(empty),
  .full(full)
);

always #5 clk=~clk;

initial begin
clk=0;
push=0;
pop=0;
hpos=0;
vpos=0;
hpos_read=0;
vpos_read=0;
RGBin=0;
reset_n=0;
#20;
reset_n=1;
#10
push=1;
for(integer i=0; i<10; i++) begin
hpos=$urandom_range(0,1279);
vpos=$urandom_range(0,959);
RGBin=$urandom_range(0,7);
#10;
end
push=0;
#10;
pop=1;
#550;
pop=0;
push=1;
for(integer i=0; i<7; i++) begin
hpos=$urandom_range(0,1279);
vpos=$urandom_range(0,959);
RGBin=$urandom_range(0,7);
#10;
end
push=0;
#10;
pop=1;
#120;
$stop;

end

endmodule
module Top_FB_TestBench();

reg clk, reset_n;
reg [3:0] key_sw;

top DUT (
.clk(clk),
.reset_n(reset_n),
.key_sw(key_sw)
);

always #5 clk=~clk;

initial begin
clk=1;
reset_n=0;
key_sw=0;
#20;
reset_n=1;

end

endmodule
module sm_rom_p1
#(
    parameter SIZE = 64
)
(
    input  [31:0] a,
    output [31:0] rd
);
    reg [31:0] rom [SIZE - 1:0];
    assign rd = rom [a];

    initial begin
        $readmemh ("p1_program.hex", rom);
    end

endmodule
module sm_rom_p0
#(
    parameter SIZE = 64
)
(
    input  [31:0] a,
    output [31:0] rd
);
    reg [31:0] rom [SIZE - 1:0];
    assign rd = rom [a];

    initial begin
        $readmemh ("p0_program.hex", rom);
    end

endmodule
module arbiter
  #(
    parameter N = 5 // Number of requesters
  )(
    input wire		    rst,
    input wire			clk,
    input wire  [N-1:0] req,
    output wire [N-1:0]	grant
  );

  reg  [N-1:0] pointer_req;
  //reg  [N-1:0] next_grant;

  wire [2*N-1:0] double_req = {req,req};
  wire [2*N-1:0] double_grant = double_req & ~(double_req - pointer_req);
  
  //Asynchronous grant update
//   assign grant = (rst)? {N{1'b0}} : double_grant[N-1:0] | double_grant[2*N-1:N];
  assign grant = double_grant[N-1:0] | double_grant[2*N-1:N];

  //Update the rotate pointer 
  wire [N-1:0]   new_req = req ^ grant;
  wire [2*N-1:0] new_double_req = {new_req,new_req};
  wire [2*N-1:0] new_double_grant  = new_double_req & ~(new_double_req - pointer_req);
  wire [N-1:0]	 async_pointer_req =  new_double_grant[N-1:0] | new_double_grant[2*N-1:N];
  
  always @ (posedge clk)
    if (rst || async_pointer_req == 0)
      pointer_req <= #1 1;
    else	 
      pointer_req <= #1 async_pointer_req;


endmodule
module mfp_uart_receiver (
    input clock,
    input reset_n,
    input rx,

    output reg [7:0] byte_data,
    output           byte_ready
);
  parameter clock_frequency = 50000000;
  parameter baud_rate       = 9600;
  parameter clock_cycles_in_symbol = clock_frequency / baud_rate;

  // Synchronize rx input to clock

  reg rx_sync1, rx_sync;

  always @(posedge clock or negedge reset_n) begin
    if (!reset_n) begin
      rx_sync1 <= 1'b1;
      rx_sync  <= 1'b1;
    end else begin
      rx_sync1 <= rx;
      rx_sync  <= rx_sync1;
    end
  end

  // Finding edge for start bit

  reg prev_rx_sync;

  always @(posedge clock or negedge reset_n) begin
    if (!reset_n) prev_rx_sync <= 1'b1;
    else prev_rx_sync <= rx_sync;
  end

  wire start_bit_edge = prev_rx_sync & !rx_sync;

  // Counter to measure distance between symbols

  reg [31:0] counter;
  reg load_counter;
  reg [31:0] load_counter_value;

  always @(posedge clock or negedge reset_n) begin
    if (!reset_n) counter <= 32'b0;
    else if (load_counter) counter <= load_counter_value;
    else if (counter != 0) counter <= counter - 1;
  end

  wire counter_done = counter == 1;

  // Shift register to accumulate data

  reg shift;
  reg [7:0] shifted_1;
  assign byte_ready = shifted_1[0];

  always @(posedge clock or negedge reset_n) begin
    if (!reset_n) begin
      shifted_1 <= 8'b0;
    end else if (shift) begin
      if (shifted_1 == 0) shifted_1 <= 8'b10000000;
      else shifted_1 <= shifted_1 >> 1;

      byte_data <= {rx, byte_data[7:1]};
    end else if (byte_ready) begin
      shifted_1 <= 8'b0;
    end
  end

  reg idle, idle_r;

  always @* begin
    idle = idle_r;
    shift = 1'b0;

    load_counter = 32'b0;
    load_counter_value = 32'b0;

    if (idle) begin
      if (start_bit_edge) begin
        load_counter = 1;
        load_counter_value = clock_cycles_in_symbol * 3 / 2;

        idle = 1'b0;
      end
    end else if (counter_done) begin
      shift = 1'b1;
      
      load_counter = 1;
      load_counter_value = clock_cycles_in_symbol;
    end else if (byte_ready) begin
      idle = 1'b1;
    end
  end

  always @(posedge clock or negedge reset_n) begin
    if (!reset_n) idle_r <= 1'b1;
    else idle_r <= idle;
  end

endmodule
module data_aggregator (
    input       clock,
    input       reset,
    input       enter,
    input       add,
    input       multiply,
    input       separator,
    input [3:0] data,

    output reg [7:0] number,
    output reg enter_occured
);

  always @(posedge clock) begin
    if (reset) begin
      number <= 8'b0;
      enter_occured <= 1'b0;
    end else if (enter) begin
      number <= {number[3:0], data};
      enter_occured <= 1'b1;
    end else if (add || multiply) begin
      enter_occured <= 1'b0;
    end else if (separator) begin
      number <= 8'b0;
    end
  end

endmodule
module two_bytes_uart_tx (
    input        clock,
    input        start,
    input        reset,
    input [15:0] data,

    output reg q,
    output     busy
);

  reg [12:0] cnt;
  reg [3:0]  bit_num;

  wire bit_start = (cnt == 5208);
  wire idle = (bit_num == 4'hF);
  assign busy = ~idle;

  reg byte_state;
  wire [7:0] word = byte_state ? data[7:0] : data[15:8];

  always @(posedge clock) begin
    if (reset) cnt <= 13'b0;
    else if (start && idle) cnt <= 13'b0;
    else if (bit_start) cnt <= 13'b0;
    else cnt <= cnt + 13'b1;
  end

  always @(posedge clock) begin
    if (reset) begin
      bit_num    <= 4'hf;
      byte_state <= 1'b0;
      q <= 1'b1;
    end else if (start && idle) begin
      bit_num    <= 4'h0;
      byte_state <= 1'b0;
      q <= 1'b1;
    end else if (bit_start) begin
      case (bit_num)
        4'h0: begin bit_num <= 4'h1; q <= 1'b0;    end // start
        4'h1: begin bit_num <= 4'h2; q <= word[0]; end
        4'h2: begin bit_num <= 4'h3; q <= word[1]; end
        4'h3: begin bit_num <= 4'h4; q <= word[2]; end
        4'h4: begin bit_num <= 4'h5; q <= word[3]; end
        4'h5: begin bit_num <= 4'h6; q <= word[4]; end
        4'h6: begin bit_num <= 4'h7; q <= word[5]; end
        4'h7: begin bit_num <= 4'h8; q <= word[6]; end
        4'h8: begin bit_num <= 4'h9; q <= word[7]; end
        4'h9: begin bit_num <= 4'ha; q <= 1'b1;        // finish
            if (!byte_state) begin
                byte_state <= 1'b1;
                bit_num <= 4'h0; 
            end
        end
        default: begin bit_num <= 4'hF; end            // Stop
      endcase
    end
  end

endmodule
module uart_transmitter (
    input        clock,
    input        start,
    input        reset,
    input [15:0] data,

    output reg q,
    output     busy
);

  parameter clock_frequency = 50000000;
  parameter baud_rate       = 9600;
  parameter clock_cycles_in_bit = clock_frequency / baud_rate;
  
  reg [12:0] cnt;
  reg [3:0]  bit_num;

  wire bit_start = (cnt == clock_cycles_in_bit);
  wire idle = (bit_num == 4'hF);
  assign busy = ~idle;

  reg byte_state;
  wire [7:0] word = byte_state ? data[7:0] : data[15:8];

  always @(posedge clock) begin
    if (reset) cnt <= 13'b0;
    else if (start && idle) cnt <= 13'b0;
    else if (bit_start) cnt <= 13'b0;
    else cnt <= cnt + 13'b1;
  end

  always @(posedge clock) begin
    if (reset) begin
      bit_num    <= 4'hF;
      byte_state <= 1'b0;
      q <= 1'b1;
    end else if (start && idle) begin
      bit_num    <= 4'h0;
      byte_state <= 1'b0;
      q <= 1'b1;
    end else if (bit_start) begin
      case (bit_num)
        4'h0: begin bit_num <= 4'h1; q <= 1'b0;    end // start
        4'h1: begin bit_num <= 4'h2; q <= word[0]; end
        4'h2: begin bit_num <= 4'h3; q <= word[1]; end
        4'h3: begin bit_num <= 4'h4; q <= word[2]; end
        4'h4: begin bit_num <= 4'h5; q <= word[3]; end
        4'h5: begin bit_num <= 4'h6; q <= word[4]; end
        4'h6: begin bit_num <= 4'h7; q <= word[5]; end
        4'h7: begin bit_num <= 4'h8; q <= word[6]; end
        4'h8: begin bit_num <= 4'h9; q <= word[7]; end
        4'h9: begin bit_num <= 4'ha; q <= 1'b1;        // finish
            if (!byte_state) begin
                byte_state <= 1'b1;
                bit_num <= 4'h0; 
            end
        end
        default: begin bit_num <= 4'hF; end            // Stop
      endcase
    end
  end

endmodule
module seven_segment_4_digits (
    input        clock,
    input        reset,
    input [15:0] number,

    output reg [7:0] abcdefgh,
    output reg [3:0] digit
);

  function [7:0] bcd_to_seg(input [3:0] bcd);

    case (bcd)

      'h0: bcd_to_seg = 'b00000011;  // a b c d e f g h
      'h1: bcd_to_seg = 'b10011111;
      'h2: bcd_to_seg = 'b00100101;  //   --a--
      'h3: bcd_to_seg = 'b00001101;  //  |     |
      'h4: bcd_to_seg = 'b10011001;  //  f     b
      'h5: bcd_to_seg = 'b01001001;  //  |     |
      'h6: bcd_to_seg = 'b01000001;  //   --g--
      'h7: bcd_to_seg = 'b00011111;  //  |     |
      'h8: bcd_to_seg = 'b00000001;  //  e     c
      'h9: bcd_to_seg = 'b00011001;  //  |     |
      'ha: bcd_to_seg = 'b00010001;  //   --d--  h
      'hb: bcd_to_seg = 'b11000001;
      'hc: bcd_to_seg = 'b01100011;
      'hd: bcd_to_seg = 'b10000101;
      'he: bcd_to_seg = 'b01100001;
      'hf: bcd_to_seg = 'b01110001;

    endcase

  endfunction

  reg [15:0] cnt;

  always @(posedge clock)
    if (reset) cnt <= 16'd0;
    else cnt <= cnt + 16'd1;

  reg [1:0] i;

  always @(posedge clock) begin
    if (reset) begin
      abcdefgh <= bcd_to_seg(0);
      digit <= ~4'b1;

      i <= 2'b0;
    end else if (cnt == 16'b0) begin
      abcdefgh <= bcd_to_seg(number[i * 4 +: 4]);
      digit <= ~(4'b1 << i);

      i <= i + 1;
    end
  end

endmodule
module top (
    input clock,
    input reset_n,
    input rx,

    output reg       tx,
    output reg [7:0] abcdefgh,
    output reg [3:0] nx_digit
);

  wire byte_ready;
  wire [7:0] ascii_data;

  uart_receiver listener (
      .clock  (clock),
      .reset_n(reset_n),
      .rx     (rx),

      .byte_data (ascii_data),
      .byte_ready(byte_ready)
  );

  wire separator, add, multiply, enter, clear, error_ascii;
  wire [3:0] digit;

  ascii_to_action translator (
      .clock(clock),
      .start(byte_ready),
      .reset(~reset_n),
      .data (ascii_data),

      .separator(separator),
      .add      (add),
      .multiply (multiply),
      .digit    (digit),
      .enter    (enter),
      .clear    (clear),
      .error    (error_ascii)
  );


  // Prepare and accumulate data 

  logic [7:0] number;
  logic enter_occured;

  data_aggregator aggregator (
      .clock    (clock),
      .reset    (~reset_n),
      .enter    (enter),
      .add      (add),
      .multiply (multiply),
      .separator(separator),
      .data     (digit),

      .number       (number),
      .enter_occured(enter_occured)
  );

  // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~

  wire [15:0] result;
  wire overflow, newresult;
  wire [3:0] error_calculator;
  wire is_tx_busy;

  calculator calculator (
      .clock   (clock),
      .reset   (~reset_n || clear),
      .enter   (separator & enter_occured),
      .add     (add),
      .multiply(multiply),
      .data    (number),

      .newresult(newresult),
      .result   (result),
      .overflow (overflow),
      .error    (error_calculator)
  );

  seven_segment_4_digits display (
      .clock (clock),
      .reset (~reset_n),
      .number(result),

      .digit   (nx_digit),
      .abcdefgh(abcdefgh)
  );

  uart_transmitter loader (
      .clock(clock),
      .reset(~reset_n),
      .start(newresult),
      .data (result),

      .q   (tx),
      .busy(is_tx_busy)
  );


endmodule
module DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_demux
(
    // -------------------
    // Sink
    // -------------------
    input  [1-1      : 0]   sink_valid,
    input  [96-1    : 0]   sink_data, // ST_DATA_W=96
    input  [6-1 : 0]   sink_channel, // ST_CHANNEL_W=6
    input                         sink_startofpacket,
    input                         sink_endofpacket,
    output                        sink_ready,

    // -------------------
    // Sources 
    // -------------------
    output reg                      src0_valid,
    output reg [96-1    : 0] src0_data, // ST_DATA_W=96
    output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
    output reg                      src0_startofpacket,
    output reg                      src0_endofpacket,
    input                           src0_ready,

    output reg                      src1_valid,
    output reg [96-1    : 0] src1_data, // ST_DATA_W=96
    output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6
    output reg                      src1_startofpacket,
    output reg                      src1_endofpacket,
    input                           src1_ready,


    // -------------------
    // Clock & Reset
    // -------------------
    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
    input clk,
    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
    input reset

);

    localparam NUM_OUTPUTS = 2;
    wire [NUM_OUTPUTS - 1 : 0] ready_vector;

    // -------------------
    // Demux
    // -------------------
    always @* begin
        src0_data          = sink_data;
        src0_startofpacket = sink_startofpacket;
        src0_endofpacket   = sink_endofpacket;
        src0_channel       = sink_channel >> NUM_OUTPUTS;

        src0_valid         = sink_channel[0] && sink_valid;

        src1_data          = sink_data;
        src1_startofpacket = sink_startofpacket;
        src1_endofpacket   = sink_endofpacket;
        src1_channel       = sink_channel >> NUM_OUTPUTS;

        src1_valid         = sink_channel[1] && sink_valid;

    end

    // -------------------
    // Backpressure
    // -------------------
    assign ready_vector[0] = src0_ready;
    assign ready_vector[1] = src1_ready;

    assign sink_ready = |(sink_channel & {{4{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});

endmodule
module DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_demux
(
    // -------------------
    // Sink
    // -------------------
    input  [6-1      : 0]   sink_valid,
    input  [96-1    : 0]   sink_data, // ST_DATA_W=96
    input  [6-1 : 0]   sink_channel, // ST_CHANNEL_W=6
    input                         sink_startofpacket,
    input                         sink_endofpacket,
    output                        sink_ready,

    // -------------------
    // Sources 
    // -------------------
    output reg                      src0_valid,
    output reg [96-1    : 0] src0_data, // ST_DATA_W=96
    output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
    output reg                      src0_startofpacket,
    output reg                      src0_endofpacket,
    input                           src0_ready,

    output reg                      src1_valid,
    output reg [96-1    : 0] src1_data, // ST_DATA_W=96
    output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6
    output reg                      src1_startofpacket,
    output reg                      src1_endofpacket,
    input                           src1_ready,


    // -------------------
    // Clock & Reset
    // -------------------
    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
    input clk,
    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
    input reset

);

    localparam NUM_OUTPUTS = 2;
    wire [NUM_OUTPUTS - 1 : 0] ready_vector;

    // -------------------
    // Demux
    // -------------------
    always @* begin
        src0_data          = sink_data;
        src0_startofpacket = sink_startofpacket;
        src0_endofpacket   = sink_endofpacket;
        src0_channel       = sink_channel >> NUM_OUTPUTS;

        src0_valid         = sink_channel[0] && sink_valid[0];

        src1_data          = sink_data;
        src1_startofpacket = sink_startofpacket;
        src1_endofpacket   = sink_endofpacket;
        src1_channel       = sink_channel >> NUM_OUTPUTS;

        src1_valid         = sink_channel[1] && sink_valid[1];

    end

    // -------------------
    // Backpressure
    // -------------------
    assign ready_vector[0] = src0_ready;
    assign ready_vector[1] = src1_ready;

    assign sink_ready = |(sink_channel & {{4{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});

endmodule
module DE0_NANO_SOC_QSYS_irq_mapper
(
    // -------------------
    // Clock & Reset
    // -------------------
    input clk,
    input reset,

    // -------------------
    // IRQ Receivers
    // -------------------
    input                receiver0_irq,
    input                receiver1_irq,

    // -------------------
    // Command Source (Output)
    // -------------------
    output reg [31 : 0] sender_irq
);


    always @* begin
	sender_irq = 0;

        sender_irq[0] = receiver0_irq;
        sender_irq[1] = receiver1_irq;
    end

endmodule