dakies/OSS_Verilog huggingface dataset:
module testbench;

    reg  clk, rst_n, d;
    wire q;

    dff_sync_rst_n dff_sync_rst_n (clk, rst_n, d, q);
    
    initial $dumpvars;

    initial
    begin
        rst_n = 0;
        
        $monitor ("%0d clk %b d %b q %b", $time, clk, d, q);

        # 20;   clk = 0; d = 0; 
        # 20;   clk = 1; d = 0; 
        # 20;   clk = 0; d = 1;
        # 20;   clk = 1; d = 1;
        # 20;   clk = 0; d = 1; rst_n = 1;
        # 20;   clk = 1; d = 1;
        # 20;   clk = 0; d = 0;
        # 20;   clk = 1; d = 0; 
        # 10;   clk = 1; d = 0; 
        # 10;   clk = 0; d = 0;
        # 10;   clk = 0; d = 1; 
        # 10;   clk = 1; d = 1; 
        # 10;   clk = 1; d = 1; rst_n = 0;
        # 10;   clk = 0; d = 1;
        # 10;   clk = 0; d = 1;
        # 10;   clk = 1; d = 1;
        # 10;   clk = 1; d = 0;
        # 20;

        $finish;
    end

endmodule
module de10_lite
(
    input         ADC_CLK_10,
    input         MAX10_CLK1_50,
    input         MAX10_CLK2_50,

    input  [ 1:0] KEY,
    input  [ 9:0] SW,
    output [ 9:0] LEDR
);

    assign LEDR[9:1] = 8'b0;

    dff_sync_rst_n dff_sync_rst_n
    (
        .clk   ( ~KEY [0] ),
        .rst_n (  SW  [0] ),
        .d     ( ~KEY [1] ),
        .q     (  LEDR[0] )
    );

endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    dff_async_rst_n_param dff_async_rst_n_param (KEY[0], KEY[2], SW, LEDR);
 
endmodule
module testbench;

    reg  clk, rst_n;
    reg  [3:0] d;
    wire [3:0] q;

    dff_async_rst_n_param #(.WIDTH(4), .RESET(4'ha)) dff_async_rst_n_param (clk, rst_n, d, q);
    
    initial $dumpvars;

    initial
    begin
        rst_n = 1;
        clk   = 1;
        
        $monitor ("%0d clk %b d %b q %b", $time, clk, d, q);

        # 20;   clk = 0; d = 4'h0; rst_n = 0;
        # 20;   clk = 1; d = 4'h1; 
        # 20;   clk = 0; d = 4'h2;
        # 20;   clk = 1; d = 4'h3;
        # 20;   clk = 0; d = 4'h4; rst_n = 1;
        # 20;   clk = 1; d = 4'h5;
        # 20;   clk = 0; d = 4'h6;
        # 20;   clk = 1; d = 4'h7; 
        # 10;   clk = 1; d = 4'h8; 
        # 10;   clk = 0; d = 4'h9;
        # 10;   clk = 0; d = 4'ha; 
        # 10;   clk = 1; d = 4'hb; 
        # 10;   clk = 1; d = 4'hc; rst_n = 0;
        # 10;   clk = 0; d = 4'hd;
        # 10;   clk = 0; d = 4'he;
        # 10;   clk = 1; d = 4'hf;
        # 10;   clk = 1; d = 4'h0;
        # 20;

        $finish;
    end

endmodule
module de10_lite
(
    input         ADC_CLK_10,
    input         MAX10_CLK1_50,
    input         MAX10_CLK2_50,

    input  [ 1:0] KEY,
    input  [ 9:0] SW,
    output [ 9:0] LEDR
);
    assign LEDR[0] = 1'b0;

    dff_async_rst_n_param 
    #(
        .WIDTH ( 8     ), 
        .RESET ( 8'hf0 )
    ) 
    dff_async_rst_n_param
    (
        .clk   ( ~KEY  [0]   ),
        .rst_n (  SW   [0]   ),
        .d     (  SW   [9:1] ),
        .q     (  LEDR [9:1] )
    );

endmodule
module tb();

    reg CLOCK_50 = 0;               // DE-series 50 MHz clock
    reg [9:0] SW = 0;               // DE-series SW switches
    reg [3:0] KEY = 0;              // DE-series pushbutton keys
    wire [(8*6) -1:0] HEX;          // HEX displays (six ports)
    wire [9:0] LEDR;                // DE-series LEDs

    reg key_action = 0;
    reg [7:0] scan_code = 0;
    wire [2:0] ps2_lock_control;

    wire [7:0] VGA_X;               // "VGA" column
    wire [6:0] VGA_Y;               // "VGA" row
    wire [2:0] VGA_COLOR;           // "VGA pixel" colour (0-7)
    wire plot;                      // "Pixel" is drawn when this is pulsed
    wire [31:0] GPIO;               // DE-series GPIO port

    initial $sim_fpga(CLOCK_50, SW, KEY, LEDR, HEX, key_action, scan_code, 
                      ps2_lock_control, VGA_X, VGA_Y, VGA_COLOR, plot, GPIO);


    // create the 50 MHz clock signal
    always #10
        CLOCK_50 <= ~CLOCK_50;
       
    top DUT (.SW(SW), .LEDR(LEDR));

endmodule
module top (SW, LEDR);

    input wire [9:0] SW;        // DE-series switches
	 
    output wire [9:0] LEDR;     // DE-series LEDs   

    sr_latch sr_latch (SW[1], SW[0], LEDR[1], LEDR[0]);

endmodule
module testbench;

    reg  s, r;
    wire q, q_n;

    sr_latch sr_latch (s, r, q, q_n);
    
    initial $dumpvars;

    initial
    begin
        
        
        $monitor ("%0d s %b r %b q %b q_n %b", $time, s, r, q, q_n);

        # 10;   s = 0; r = 0; 
        # 10;   s = 1; r = 0;
        # 10;   s = 0; r = 0;
        # 10;   s = 0; r = 1;
        # 10;   s = 0; r = 0;
        # 10;   s = 1; r = 1;
        # 10;   s = 0; r = 0;
        # 10;   s = 0; r = 0;
        # 10;

        $finish;
    end

endmodule
module de10_lite
(
    input         ADC_CLK_10,
    input         MAX10_CLK1_50,
    input         MAX10_CLK2_50,

    input  [ 1:0] KEY,
    input  [ 9:0] SW,
    output [ 9:0] LEDR
);

    assign LEDR[9:2] = 7'b0;

    sr_latch sr_latch
    (
        .s   ( ~KEY [0] ),
        .r   ( ~KEY [1] ),
        .q   (  LEDR[0] ),
        .q_n (  LEDR[1] )
    );

endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    dff_with_en dff_with_en (KEY[0], KEY[2], SW[0], LEDR[1]);
 
endmodule
module testbench;

    reg  clk, en, d;
    wire q;

    dff_with_en dff_with_en (clk, en, d, q);
    
    initial $dumpvars;

    initial
    begin
        en = 0;
        
        $monitor ("%0d clk %b d %b q %b", $time, clk, d, q);

        # 20;   clk = 0; d = 0; 
        # 20;   clk = 1; d = 0; 
        # 20;   clk = 0; d = 1;
        # 20;   clk = 1; d = 1;
        # 20;   clk = 0; d = 1; en = 1;
        # 20;   clk = 1; d = 1;
        # 20;   clk = 0; d = 0;
        # 20;   clk = 1; d = 0; 
        # 10;   clk = 1; d = 0; 
        # 10;   clk = 0; d = 0;
        # 10;   clk = 0; d = 1; 
        # 10;   clk = 1; d = 1; 
        # 10;   clk = 1; d = 1; en = 0;
        # 10;   clk = 0; d = 1;
        # 10;   clk = 0; d = 1;
        # 10;   clk = 1; d = 1;
        # 10;   clk = 1; d = 0;
        # 20;

        $finish;
    end

endmodule
module de10_lite
(
    input         ADC_CLK_10,
    input         MAX10_CLK1_50,
    input         MAX10_CLK2_50,

    input  [ 1:0] KEY,
    input  [ 9:0] SW,
    output [ 9:0] LEDR
);

    assign LEDR[9:1] = 8'b0;

    dff_with_en dff_with_en
    (
        .clk   ( ~KEY [0] ),
        .en    (  SW  [0] ),
        .d     ( ~KEY [1] ),
        .q     (  LEDR[0] )
    );

endmodule
module tb();

    reg CLOCK_50 = 0;               // DE-series 50 MHz clock
    reg [9:0] SW = 0;               // DE-series SW switches
    reg [3:0] KEY = 0;              // DE-series pushbutton keys
    wire [(8*6) -1:0] HEX;          // HEX displays (six ports)
    wire [9:0] LEDR;                // DE-series LEDs

    reg key_action = 0;
    reg [7:0] scan_code = 0;
    wire [2:0] ps2_lock_control;

    wire [7:0] VGA_X;               // "VGA" column
    wire [6:0] VGA_Y;               // "VGA" row
    wire [2:0] VGA_COLOR;           // "VGA pixel" colour (0-7)
    wire plot;                      // "Pixel" is drawn when this is pulsed
    wire [31:0] GPIO;               // DE-series GPIO port

    initial $sim_fpga(CLOCK_50, SW, KEY, LEDR, HEX, key_action, scan_code, 
                      ps2_lock_control, VGA_X, VGA_Y, VGA_COLOR, plot, GPIO);

    
    // create the 50 MHz clock signal
    always #10
        CLOCK_50 <= ~CLOCK_50;
		  
    
    top DUT (.SW(SW), .KEY(KEY), .LEDR(LEDR));

endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    d_flip_flop d_flip_flop (KEY[0], SW[0], LEDR[1], LEDR[0]);

endmodule
module testbench;

    reg  clk, d;
    wire q, q_n;

    d_flip_flop d_flip_flop (clk, d, q, q_n);
    
    initial $dumpvars;

    initial
    begin
        
        
        $monitor ("%0d clk %b d %b q %b q_n %b", $time, clk, d, q, q_n);

        # 20;   clk = 0; d = 0; 
        # 20;   clk = 1; d = 0;
        # 20;   clk = 0; d = 1;
        # 20;   clk = 1; d = 1;
        # 20;   clk = 0; d = 0;
        # 20;   clk = 1; d = 0;
        # 20;   clk = 0; d = 1;
        # 20;   clk = 1; d = 1;
        # 10;   clk = 1; d = 0; 
        # 10;   clk = 0; d = 0;
        # 10;   clk = 0; d = 0;
        # 10;   clk = 1; d = 0;
        # 10;   clk = 1; d = 1;
        # 10;   clk = 0; d = 1;
        # 10;   clk = 0; d = 1;
        # 10;   clk = 1; d = 1;
        # 10;   clk = 1; d = 0;
        # 20;

        $finish;
    end

endmodule
module de10_lite
(
    input         ADC_CLK_10,
    input         MAX10_CLK1_50,
    input         MAX10_CLK2_50,

    input  [ 1:0] KEY,
    input  [ 9:0] SW,
    output [ 9:0] LEDR
);

    assign LEDR[9:2] = 7'b0;

    d_flip_flop d_flip_flop
    (
        .clk ( ~KEY [0] ),
        .d   ( ~KEY [1] ),
        .q   (  LEDR[0] ),
        .q_n (  LEDR[1] )
    );

endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    d_flip_flop d_flip_flop (KEY[0], SW[0], LEDR[1]);
 
endmodule
module testbench;

    reg  clk, d;
    wire q;

    d_flip_flop d_flip_flop (clk, d, q);
    
    initial $dumpvars;

    initial
    begin
        
        
        $monitor ("%0d clk %b d %b q %b", $time, clk, d, q);

        # 20;   clk = 0; d = 0; 
        # 20;   clk = 1; d = 0;
        # 20;   clk = 0; d = 1;
        # 20;   clk = 1; d = 1;
        # 20;   clk = 0; d = 0;
        # 20;   clk = 1; d = 0;
        # 20;   clk = 0; d = 1;
        # 20;   clk = 1; d = 1;
        # 10;   clk = 1; d = 0; 
        # 10;   clk = 0; d = 0;
        # 10;   clk = 0; d = 0;
        # 10;   clk = 1; d = 0;
        # 10;   clk = 1; d = 1;
        # 10;   clk = 0; d = 1;
        # 10;   clk = 0; d = 1;
        # 10;   clk = 1; d = 1;
        # 10;   clk = 1; d = 0;
        # 20;

        $finish;
    end

endmodule
module de10_lite
(
    input         ADC_CLK_10,
    input         MAX10_CLK1_50,
    input         MAX10_CLK2_50,

    input  [ 1:0] KEY,
    input  [ 9:0] SW,
    output [ 9:0] LEDR
);

    assign LEDR[9:1] = 8'b0;

    d_flip_flop d_flip_flop
    (
        .clk ( ~KEY [0] ),
        .d   ( ~KEY [1] ),
        .q   (  LEDR[0] )
    );

endmodule
module tb();

    reg CLOCK_50 = 0;               // DE-series 50 MHz clock
    reg [9:0] SW = 0;               // DE-series SW switches
    reg [3:0] KEY = 0;              // DE-series pushbutton keys
    wire [(8*6) -1:0] HEX;          // HEX displays (six ports)
    wire [9:0] LEDR;                // DE-series LEDs

    reg key_action = 0;
    reg [7:0] scan_code = 0;
    wire [2:0] ps2_lock_control;

    wire [7:0] VGA_X;               // "VGA" column
    wire [6:0] VGA_Y;               // "VGA" row
    wire [2:0] VGA_COLOR;           // "VGA pixel" colour (0-7)
    wire plot;                      // "Pixel" is drawn when this is pulsed
    wire [31:0] GPIO;               // DE-series GPIO port

    initial $sim_fpga(CLOCK_50, SW, KEY, LEDR, HEX, key_action, scan_code, 
                      ps2_lock_control, VGA_X, VGA_Y, VGA_COLOR, plot, GPIO);

 
    // create the 50 MHz clock signal
    always #10
        CLOCK_50 <= ~CLOCK_50;
		  
    
    top DUT (.SW(SW), .KEY(KEY), .LEDR(LEDR));

endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    d_latch d_latch (KEY[0], SW[0], LEDR[0]);

endmodule
module testbench;

    reg  clk, d;
    wire q;

    d_latch d_latch (clk, d, q);
    
    initial $dumpvars;

    initial
    begin
        
        
        $monitor ("%0d clk %b d %b q %b", $time, clk, d, q);

        # 20;   clk = 0; d = 0; 
        # 20;   clk = 1; d = 0;
        # 20;   clk = 0; d = 1;
        # 20;   clk = 1; d = 1;
        # 20;   clk = 0; d = 0;
        # 20;   clk = 1; d = 0;
        # 20;   clk = 0; d = 1;
        # 20;   clk = 1; d = 1;
        # 10;   clk = 1; d = 0; 
        # 10;   clk = 0; d = 0;
        # 10;   clk = 0; d = 0;
        # 10;   clk = 1; d = 0;
        # 10;   clk = 1; d = 1;
        # 10;   clk = 0; d = 1;
        # 10;   clk = 0; d = 1;
        # 10;   clk = 1; d = 1;
        # 10;   clk = 1; d = 0;
        # 20;

        $finish;
    end

endmodule
module de10_lite
(
    input         ADC_CLK_10,
    input         MAX10_CLK1_50,
    input         MAX10_CLK2_50,

    input  [ 1:0] KEY,
    input  [ 9:0] SW,
    output [ 9:0] LEDR
);

    assign LEDR[9:1] = 8'b0;

    d_latch d_latch
    (
        .clk ( ~KEY [0] ),
        .d   ( ~KEY [1] ),
        .q   (  LEDR[0] )
    );

endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    dff_async_rst_n dff_async_rst_n (KEY[0], KEY[3], SW[0], LEDR[1]);
 
endmodule
module testbench;

    reg  clk, rst_n, d;
    wire q;

    dff_async_rst_n dff_async_rst_n (clk, rst_n, d, q);
    
    initial $dumpvars;

    initial
    begin
        rst_n = 1;
        clk   = 1;
        
        $monitor ("%0d clk %b d %b q %b", $time, clk, d, q);

        # 20;   clk = 0; d = 0; rst_n = 0;
        # 20;   clk = 1; d = 0; 
        # 20;   clk = 0; d = 1;
        # 20;   clk = 1; d = 1;
        # 20;   clk = 0; d = 1; rst_n = 1;
        # 20;   clk = 1; d = 1;
        # 20;   clk = 0; d = 0;
        # 20;   clk = 1; d = 0; 
        # 10;   clk = 1; d = 0; 
        # 10;   clk = 0; d = 0;
        # 10;   clk = 0; d = 1; 
        # 10;   clk = 1; d = 1; 
        # 10;   clk = 1; d = 1; rst_n = 0;
        # 10;   clk = 0; d = 1;
        # 10;   clk = 0; d = 1;
        # 10;   clk = 1; d = 1;
        # 10;   clk = 1; d = 0;
        # 20;

        $finish;
    end

endmodule
module de10_lite
(
    input         ADC_CLK_10,
    input         MAX10_CLK1_50,
    input         MAX10_CLK2_50,

    input  [ 1:0] KEY,
    input  [ 9:0] SW,
    output [ 9:0] LEDR
);

    assign LEDR[9:1] = 8'b0;

    dff_async_rst_n dff_async_rst_n
    (
        .clk   ( ~KEY [0] ),
        .rst_n (  SW  [0] ),
        .d     ( ~KEY [1] ),
        .q     (  LEDR[0] )
    );

endmodule
module tb();

    reg CLOCK_50 = 0;               // DE-series 50 MHz clock
    reg [9:0] SW = 0;               // DE-series SW switches
    reg [3:0] KEY = 0;              // DE-series pushbutton keys
    wire [(8*6) -1:0] HEX;          // HEX displays (six ports)
    wire [9:0] LEDR;                // DE-series LEDs

    reg key_action = 0;
    reg [7:0] scan_code = 0;
    wire [2:0] ps2_lock_control;

    wire [7:0] VGA_X;               // "VGA" column
    wire [6:0] VGA_Y;               // "VGA" row
    wire [2:0] VGA_COLOR;           // "VGA pixel" colour (0-7)
    wire plot;                      // "Pixel" is drawn when this is pulsed
    wire [31:0] GPIO;               // DE-series GPIO port

    initial $sim_fpga(CLOCK_50, SW, KEY, LEDR, HEX, key_action, scan_code, 
                      ps2_lock_control, VGA_X, VGA_Y, VGA_COLOR, plot, GPIO);


    // create the 50 MHz clock signal
    always #10
        CLOCK_50 <= ~CLOCK_50;

    
    top DUT (.SW(SW), .KEY(KEY), .LEDR(LEDR));

endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    d_latch d_latch (KEY[0], SW[0], LEDR[1], LEDR[0]);

endmodule
module testbench;

    reg  clk, d;
    wire q, q_n;

    d_latch d_latch (clk, d, q, q_n);
    
    initial $dumpvars;

    initial
    begin
        
        
        $monitor ("%0d clk %b d %b q %b q_n %b", $time, clk, d, q, q_n);

        # 20;   clk = 0; d = 0; 
        # 20;   clk = 1; d = 0;
        # 20;   clk = 0; d = 1;
        # 20;   clk = 1; d = 1;
        # 20;   clk = 0; d = 0;
        # 20;   clk = 1; d = 0;
        # 20;   clk = 0; d = 1;
        # 20;   clk = 1; d = 1;
        # 10;   clk = 1; d = 0; 
        # 10;   clk = 0; d = 0;
        # 10;   clk = 0; d = 0;
        # 10;   clk = 1; d = 0;
        # 10;   clk = 1; d = 1;
        # 10;   clk = 0; d = 1;
        # 10;   clk = 0; d = 1;
        # 10;   clk = 1; d = 1;
        # 10;   clk = 1; d = 0;
        # 20;

        $finish;
    end

endmodule
module de10_lite
(
    input         ADC_CLK_10,
    input         MAX10_CLK1_50,
    input         MAX10_CLK2_50,

    input  [ 1:0] KEY,
    input  [ 9:0] SW,
    output [ 9:0] LEDR
);

    assign LEDR[9:2] = 7'b0;

    d_latch d_latch
    (
        .clk ( ~KEY [0] ),
        .d   ( ~KEY [1] ),
        .q   (  LEDR[0] ),
        .q_n (  LEDR[1] )
    );

endmodule
module lab8_3
(
    input  clock,
    input  reset_n,
    input  enable,
    input  a,
    output reg    y
);

    parameter [1:0] S0 = 0, S1 = 1, S2 = 2;

    reg [1:0] state, next_state;

    // State register

    always @ (posedge clock or negedge reset_n)
        if (! reset_n)
            state <= S0;
        else if (enable)
            state <= next_state;

    // Next state logic

    always @*
        case (state)
        
        S0:
            if (a)
                next_state = S1;
            else
                next_state = S0;

        S1:
            if (a)
                next_state = S2;
            else
                next_state = S1;

        S2:
            if (a)
                next_state = S0;
            else
                next_state = S2;

        default:

            next_state = S0;

        endcase

    // Output logic based on current state

    always @ (posedge clock or negedge reset_n)
    begin
        if (! reset_n)
            y <= 0;
        else if (enable)
        begin
            y <= 1;
            case (state)
            S0:
                if (!a) 
                    y <= 0;
            S2:
                if (a)
                    y <= 0;
            endcase
        end
    end
endmodule
module lab8_4
(
    input  clock,
    input  reset_n,
    input  enable,
    input  a,
    output y
);

    parameter [1:0] S0 = 2'b00, S1 = 2'b01, S2 = 2'b11, S3 = 2'b10;

    reg [1:0] state, next_state;

    // State register

    always @ (posedge clock or negedge reset_n)
        if (! reset_n)
            state <= S0;
        else if (enable)
            state <= next_state;

    // Next state logic

    always @*
        case (state)
        
        S0:
            if (a)
                next_state = S0;
            else
                next_state = S1;

        S1:
            if (a)
                next_state = S1;
            else
                next_state = S2;

        S2:
            if (a)
                next_state = S0;
            else
                next_state = S3;

        S3:
            if (a)
                next_state = S2;
            else
                next_state = S0;

        default:

            next_state = S0;

        endcase

    // Output logic based on current state

    assign y = (a & state == S1);

endmodule
module lab8_2
(
    input  clock,
    input  reset_n,
    input  enable,
    input  a,
    output reg    y
);

    parameter [1:0] S0 = 0, S1 = 1, S2 = 2;

    reg [1:0] state, next_state;

    // State register

    always @ (posedge clock or negedge reset_n)
        if (! reset_n)
            state <= S0;
        else if (enable)
            state <= next_state;

    // Next state logic

    always @*
        case (state)
        
        S0:
            if (a)
                next_state = S1;
            else
                next_state = S0;

        S1:
            if (a)
                next_state = S2;
            else
                next_state = S1;

        S2:
            if (a)
                next_state = S0;
            else
                next_state = S2;

        default:

            next_state = S0;

        endcase

    // Output logic based on current state

    always @ (posedge clock)
        case (state)
			S0: y <= 0;
			S1: y <= 1;
			S2: y <= 1;
			default: y <= 0;
        endcase

endmodule
module lab8_1
(
    input  clock,
    input  reset_n,
    input  enable,
    input  a,
    output y
);

    parameter [1:0] S0 = 0, S1 = 1, S2 = 2;

    reg [1:0] state, next_state;

    // State register

    always @ (posedge clock or negedge reset_n)
        if (! reset_n)
            state <= S0;
        else if (enable)
            state <= next_state;

    // Next state logic

    always @*
        case (state)
        
        S0:
            if (a)
                next_state = S1;
            else
                next_state = S0;

        S1:
            if (a)
                next_state = S2;
            else
                next_state = S1;

        S2:
            if (a)
                next_state = S0;
            else
                next_state = S2;

        default:

            next_state = S0;

        endcase

    // Output logic based on current state

    assign y = (state == S2 || state == S1);

endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    lab8_3 Moore_FSM_reg_next_output (KEY[0], KEY[2], KEY[3], SW[0], LEDR[0]);

endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    lab8_4 Mealy_FSM (KEY[0], KEY[2], KEY[3], SW[0], LEDR[0]);

endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    lab8_2 Moore_FSM_reg_output (KEY[0], KEY[2], KEY[3], SW[0], LEDR[0]);

endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    lab8_1 Moore_FSM (KEY[0], KEY[2], KEY[3], SW[0], LEDR[0]);

endmodule
module lab1
(
    input  [1:0] KEY,  // KEYs
    output [9:0] LED   // LEDs
);

    wire a = ~ KEY [0];
    wire b = ~ KEY [1];

    // Basic gates AND, OR and NOT
    assign LED [0] = a & b;
    assign LED [1] = a | b;
    assign LED [2] = ~ a;
    
    // XOR gates (useful for adders, comparisons,
    // parity and control sum calculation)
    assign LED [3] = a ^ b;

    // Building XOR only using AND, OR and NOT
    assign LED [4] = (a | b) & ~ (a & b);

    // Building NOT by XORing with 1
    assign LED [5] = a ^ 1'b1;

    // De Morgan law illustration
    assign LED [6] = ~ ( a &   b ) ;
    assign LED [7] = ~   a | ~ b   ;
    assign LED [8] = ~ ( a |   b ) ;
    assign LED [9] = ~   a & ~ b   ;
    
endmodule
module tb();

    reg CLOCK_50 = 0;               // DE-series 50 MHz clock
    reg [9:0] SW = 0;               // DE-series SW switches
    reg [3:0] KEY = 0;              // DE-series pushbutton keys
    wire [(8*6) -1:0] HEX;          // HEX displays (six ports)
    wire [9:0] LEDR;                // DE-series LEDs

    reg key_action = 0;
    reg [7:0] scan_code = 0;
    wire [2:0] ps2_lock_control;

    wire [7:0] VGA_X;               // "VGA" column
    wire [6:0] VGA_Y;               // "VGA" row
    wire [2:0] VGA_COLOR;           // "VGA pixel" colour (0-7)
    wire plot;                      // "Pixel" is drawn when this is pulsed
    wire [31:0] GPIO;               // DE-series GPIO port

    initial $sim_fpga(CLOCK_50, SW, KEY, LEDR, HEX, key_action, scan_code, 
                      ps2_lock_control, VGA_X, VGA_Y, VGA_COLOR, plot, GPIO);


    // create the 50 MHz clock signal
    always #10
        CLOCK_50 <= ~CLOCK_50;
   
    
    top DUT (.KEY(KEY), .LEDR(LEDR));

endmodule
module top (KEY, LEDR);

    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    lab1 lab1 (KEY[1:0], LEDR[9:0]);

endmodule
module testbench;

    // input and output test signals
    reg  [1:0] key;
    wire [9:0] led;

    // creating the instance of the module we want to test
    //  lab1 - module name
    //  dut  - instance name ('dut' means 'device under test')
    lab1 dut ( key, led );

    // do at the beginning of the simulation
    initial 
        begin
            key = 2'b00;    // set test signals value
            #10;            // pause
            key = 2'b01;    // set test signals value
            #10;            // pause
            key = 2'b10;    // set test signals value
            #10;            // pause
            key = 2'b11;    // set test signals value
            #10;            // pause
        end

    // do at the beginning of the simulation
    //  print signal values on every change
    initial 
        $monitor("key=%b led=%b", key, led);

    // do at the beginning of the simulation
    initial 
        $dumpvars;  //iverilog dump init

endmodule
module gray_cnt
#(
  parameter WIDTH = 4
  )
 (
  input                      clk,
  input                      rst_n,
  input                      enable,
  output reg [WIDTH - 1 : 0] gray 
 );

  reg [WIDTH - 1 : 0]       bin;
  wire [WIDTH - 1 : 0]      bin_inc;
  wire [WIDTH - 1 : 0]      bin_to_gray;
  
  always@(posedge clk or negedge rst_n)
    if(!rst_n)begin
      bin  <= 0;
      gray <= 0;
    end
    else if(enable)begin
      bin  <= bin_inc;
      gray <= bin_to_gray;
    end
  

  assign bin_inc     = bin + 1'b1;
  assign bin_to_gray = bin_inc ^ (bin_inc >> 1);
  
  
endmodule // gray_cnt
module bin2gray
#(
  parameter WIDTH = 4
 )
 (
  input  [WIDTH - 1 : 0] bin,
  output [WIDTH - 1 : 0] gray  
 );

  assign gray = bin ^ (bin>>1);
  

endmodule // bin2gray
module gray2bin
#(
  parameter WIDTH = 4
 )
 (
  input [WIDTH - 1 : 0]  gray,
  output [WIDTH - 1 : 0] bin
 );

  genvar                  i;

  generate
    for(i=0; i<WIDTH; i=i+1)begin:wrap
      assign bin[i] = ^(gray>>i);
    end
  endgenerate
  
  
endmodule // gray2bin
module timer
#(
  // Reference clock value in Hz
  parameter ref_clock = 50000000 
 )

(
 input            clk,
 input            rst_n,
 output reg [7:0] seconds,
 output reg [7:0] minuts
 );

  localparam 
    sec_tick = ref_clock,
    period   = 60;
  
  reg [31:0]      tick_cnt;
  wire            tick_en;
  wire            sec_en;
  
  //System time
  always@(posedge clk or negedge rst_n)
    if(!rst_n)
      tick_cnt <= 0;
    else if(tick_cnt == sec_tick - 1)
      tick_cnt <= 0;
    else
      tick_cnt <= tick_cnt + 1'b1;
  
  //Seconds
  always@(posedge clk or negedge rst_n)
    if(!rst_n)
      seconds <= 0;
    else if(tick_cnt == sec_tick - 1)
      if(seconds == period -1)
        seconds <= 0;
      else
        seconds <= seconds + 1'b1;
  
  // Minuts
  always@(posedge clk or negedge rst_n)
    if(!rst_n)
      minuts <= 0;
    else if(seconds == period - 1 && tick_cnt == sec_tick -1)
      if(minuts == period -1)
        minuts <= 0;
      else
        minuts <= minuts + 1'b1;
    
  
endmodule // timer
module crc_ser
(
 input            data,
 input            clk,
 input            rst_n,
 input            crc_en, 
 output reg [4:0] crc5
);
  reg [4:0]       crc5_s;
  
  always@(posedge clk or negedge rst_n)
    begin
      if(!rst_n)
        crc5 <= 5'h1f;
      else
        crc5 <= crc_en ? crc5_s : crc5;
    end

  always@*
    begin
      crc5_s[0] = crc5[4] ^ data ;
      crc5_s[1] = crc5[0] ;
      crc5_s[2] = crc5[4] ^ crc5[1] ^ data;
      crc5_s[3] = crc5[2];
      crc5_s[4] = crc5[3];
    end

  
endmodule // crc_serial
module lfsr
(
 input            clk,
 input            rst_n,
 output reg [7:0] prg_out 
 );

   wire           linear_feedback;
   
   assign linear_feedback = {((prg_out[7]^prg_out[5])^prg_out[4])^prg_out[3]};
   
   always@(posedge clk or negedge rst_n)
     begin
        if(!rst_n)
	        prg_out <= 8'hFC;
        else
          prg_out <= {prg_out[6:0],linear_feedback};
     end
   
endmodule
module cnt_updown 
#( 
  parameter WIDTH=16
)
(
 input                  clk,
 input                  rst_n,
 input                  up_down, 
 output reg [WIDTH-1:0] cnt
 );
   
   always@(posedge clk or negedge rst_n)
     begin
        if(!rst_n)
          cnt <= {WIDTH{1'b0}};
        else if(up_down)
          cnt <= cnt + 1'b1;
        else
          cnt <= cnt - 1'b1;
     end
   
endmodule // cnt_updown
module cnt_div
#(
  parameter DIV_CNT=10,
  parameter WIDTH = $clog2(DIV_CNT)
)
(
 input  clk_in,
 input  rst_n,
 output clk_out
);

   
   reg [WIDTH-1:0] cnt;

   always@(posedge clk_in or negedge rst_n)
     begin
        if(!rst_n)
          cnt <= {WIDTH{1'b0}};
        else if(cnt == DIV_CNT-1)
          cnt <= {WIDTH{1'b0}};
        else
          cnt <= cnt + 1'b1;
     end
   
   assign clk_out = (cnt == 0) ? 1'b1 : 1'b0;
   
endmodule // cnt_div
module led7 #(
    parameter COUNT = 1        //Quantity of used 7-segs leds
)(
    input  [4*COUNT-1:0] data,
    output [8*COUNT-1:0] leds
);

wire [3:0] in  [0:COUNT-1];
reg  [7:0] out [0:COUNT-1];

genvar i;
generate 
    for (i=0; i<=COUNT-1; i=i+1)
    begin : groups
        assign in[i] = data[4*i +: 4];
        assign leds[8*i +: 8] = out[i];

        always@ (in[i])
        case (in[i])        //6543201
            4'h0: out[i] = 8'b11000000;
            4'h1: out[i] = 8'b11111001;
            4'h2: out[i] = 8'b10100100;
            4'h3: out[i] = 8'b10110000;
            4'h4: out[i] = 8'b10011001;
            4'h5: out[i] = 8'b10010010;
            4'h6: out[i] = 8'b10000010;
            4'h7: out[i] = 8'b11111000;
            4'h8: out[i] = 8'b10000000;
            4'h9: out[i] = 8'b10010000;
            4'ha: out[i] = 8'b10001000;
            4'hb: out[i] = 8'b10000011;
            4'hc: out[i] = 8'b11000110;
            4'hd: out[i] = 8'b10100001;
            4'he: out[i] = 8'b10000110;
            4'hf: out[i] = 8'b10001110;
            default: out[i] = 8'h7f;
        endcase       
    end
endgenerate

endmodule
module clk_divider
#(
  parameter WIDTH = 24    
)
(
 input  clk_in,
 input  rst_n,
 output clk_out
);

  reg [WIDTH-1:0] cnt_div;
  
  always@(posedge clk_in or negedge rst_n)
  begin
    if(!rst_n)
      cnt_div <= {WIDTH{1'b0}};
    else
      cnt_div <= cnt_div + 1'b1;
  end
   
    assign clk_out = cnt_div[WIDTH-1];
   
endmodule
module strobe_gen
#( parameter div=24 )
(
 input  clk,
 input  rst_n,
 output strobe
);
  
  reg [div-1:0] cnt;
  
  always@(posedge clk or negedge rst_n)
    if(!rst_n)
      cnt <= {div{1'b0}};
    else
      cnt <= cnt + {{(div-1){1'b0}},1'b1};

    assign strobe = (cnt[div-1:0] == {div{1'b1}});
    
endmodule // strobe_gen
module bin2bcd 
#(  parameter IN_WIDTH = 10,
              DIGITS   = 4
)
(
 input [IN_WIDTH - 1:0]      bin,
 output reg [DIGITS*4 - 1:0] bcd
);

integer i, j;
//BIN to BCD
always@*
begin
  bcd = 0;
  for (i=IN_WIDTH-1; i>=0; i=i-1) 
  begin  
    for (j=DIGITS-1; j >= 0; j = j - 1)
      if (bcd[4*j +: 4] >= 5) 
        bcd[4*j +: 4] = bcd[4*j +: 4] + 3;
    bcd = bcd << 1;
    bcd[0] = bin[i];
  end
end

endmodule
module tone_gen
#( 
   parameter ref_clock     = 50000000,
   parameter out_freq_x100 = 26163
)
  
(
 input      clk,
 input      rst_n,
 output reg tone_freq
);
  
  localparam samp_rate = ref_clock*100/out_freq_x100;
  
  reg [31:0] cnt;
  
  always@(posedge clk or negedge rst_n)
    if(!rst_n)
      begin
        cnt       <= 16'b0;
        tone_freq <= 0;
      end
    else if(cnt == samp_rate / 2 - 1 )
      begin
        cnt       <= 16'b0;
        tone_freq <= !tone_freq;
      end
    else
      begin
        cnt       <= cnt + 16'b1;
        tone_freq <= tone_freq;
      end
     
        
  
endmodule // tone_gen
module simple_counter
#(
  parameter WIDTH=8
)
(
 input                  clk,
 input                  rst_n,
 output reg [WIDTH-1:0] cnt
 );
          
   always@(posedge clk or negedge rst_n)
     begin
        if(!rst_n)
          cnt <= {WIDTH{1'b0}};
        else
          cnt <= cnt + 1'b1;
     end
   
endmodule // simple_counter
module cnt_load
#(
  parameter WIDTH=16
  )
(
 input                  clk,
 input                  rst_n,
 input                  load,
 input [WIDTH-1:0]      data_load,
 output reg [WIDTH-1:0] cnt
 );

   always@(posedge clk or negedge rst_n)
     begin:cnt_with_load
        if(!rst_n)
          cnt <= {WIDTH{1'b0}};
        else if(load)
          cnt <= data_load;
        else
          cnt <= cnt + 1'b1;
     end
   
endmodule // cnt_load
module shift_reg
#(
  parameter WIDTH=8
)
(
 input                  clk,
 input                  rst_n,
 input                  data_in,
 input                  shift_en,
 
 output reg [WIDTH-1:0] data_out,
 output                 serial_out      
 );

      
   always@(posedge clk or negedge rst_n)
     begin
        if(!rst_n)
          data_out <= {WIDTH{1'b0}};
        else if(shift_en)
          data_out <= {data_in,data_out[WIDTH-1:1]};
     end
   
   assign serial_out = data_out[0];
   
endmodule // shift_reg
module pwm
#(
  parameter PWM_WIDTH=16
)
(
 input                 clk,
 input                 rst_n,
 input [PWM_WIDTH-1:0] imp_width,
 output                pwm_out
 );

   reg [PWM_WIDTH-1:0] cnt;
   
   
   always@(posedge clk or negedge rst_n)
     begin
        if(!rst_n)
          cnt <= {PWM_WIDTH{1'b0}};
        else
          cnt <= cnt + 1'b1;
     end
  
   assign pwm_out = (imp_width > cnt) ? 1'b1 : 1'b0;
   
endmodule // pwm
module hcsr04
#(
  parameter clk_freq = 50000000,
            width    = 8
)
(
 input                    clk,
 input                    rst_n,
 input                    echo,
 output reg               trig,
 output reg [width - 1:0] distance
);

  localparam 
    max_distance_cm        = 400,
                          
    trigger_in_us          = 10,
                          
    measurment_cycle_ms    = 200,
                          
    vel_of_sound_m_per_s   = 340,
                          
    measurment_cycle_tick  = ( clk_freq/1000 * measurment_cycle_ms ),
                          
    trigger_in_tick        = ( trigger_in_us*clk_freq/1000000),
                          
    max_echo_tick          = ( clk_freq/vel_of_sound_m_per_s/100) * max_distance_cm * 2, 
      
                          
    trig_cnt_width         = $clog2(measurment_cycle_tick),
    echo_cnt_width         = $clog2(max_echo_tick+1);

 
  reg [trig_cnt_width - 1 : 0] trig_cnt;
  reg [echo_cnt_width - 1 : 0] echo_cnt;
  reg                          echo_buff;
  wire                         echo_rise;
  wire                         echo_fall;
  
  
  always@(posedge clk or negedge rst_n)
    if(!rst_n)
      trig_cnt <= 0;
    else if(trig_cnt == measurment_cycle_tick -1)
      trig_cnt <= 0;
    else
      trig_cnt <= trig_cnt + 1'b1;

  always@(posedge clk or negedge rst_n)
    if(!rst_n)
      trig <= 1'b0;
    else if(trig_cnt == measurment_cycle_tick - trigger_in_tick -1)
      trig <= 1'b1;
    else if(trig_cnt == measurment_cycle_tick - 1)
      trig <= 1'b0;

 
                     
  always@(posedge clk or negedge rst_n)
    if(!rst_n)
      echo_buff <= 0;
    else
      echo_buff <= echo;
  
  assign echo_rise = echo  & !echo_buff;
  assign echo_fall = !echo & echo_buff;
  
  
  always@(posedge clk or negedge rst_n)
    if(!rst_n)begin
      echo_cnt <= 0;
      distance <= 0;
    end
    else if(echo_rise)
      echo_cnt <= 0;
    else if(echo_fall)
      distance <= echo_cnt[echo_cnt_width - 1 : echo_cnt_width - width];
    else
      echo_cnt <= echo_cnt + 1'b1;
  
  
endmodule // hcsr04
module crc32
(
 input             clk,
 input             rst_n,
 input [7:0]       data,
 input             crc_en,
 output reg [31:0] crc32
);
  always@(posedge clk or negedge rst_n)
    if(!rst_n)
      crc32 <= 32'hFFFFFFFF;
    else begin
      crc32 <= crc_en ? crc32_byte(crc32,data) : crc32;
      
    end
  function [31:0] crc32_bit;
    input [31:0]   crc;
    input          data;
    begin
      crc32_bit      = crc << 1;
      crc32_bit[0]   = crc[31] ^ data;
      crc32_bit[1]   = crc[31] ^ data ^ crc[0];
      crc32_bit[2]   = crc[31] ^ data ^ crc[1];
      crc32_bit[4]   = crc[31] ^ data ^ crc[3];
      crc32_bit[5]   = crc[31] ^ data ^ crc[4];
      crc32_bit[7]   = crc[31] ^ data ^ crc[6];
      crc32_bit[8]   = crc[31] ^ data ^ crc[7];
      crc32_bit[10]  = crc[31] ^ data ^ crc[9];
      crc32_bit[11]  = crc[31] ^ data ^ crc[10];
      crc32_bit[12]  = crc[31] ^ data ^ crc[11];
      crc32_bit[16]  = crc[31] ^ data ^ crc[15];
      crc32_bit[22]  = crc[31] ^ data ^ crc[21];
      crc32_bit[23]  = crc[31] ^ data ^ crc[22];
      crc32_bit[26]  = crc[31] ^ data ^ crc[25];
    end
  endfunction // crc32_bit

  function [31:0] crc32_byte;
    input [31:0] crc;
    input [7:0]  data;
    integer      i;
    begin
      crc32_byte = crc;
      for(i=0;i<8;i=i+1)begin
        crc32_byte = crc32_bit(crc32_byte,data[7-i]);
      end
    end
  endfunction // crc32_byte
  
endmodule // crc32
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    gray_cnt lab6 (KEY[0], SW[0], KEY[2], LEDR[3:0]);
 
endmodule
module de10_lite
(
 input        CLOCK_50,
 input [1:0]  KEY,
 output [3:0] LEDR,
 output [7:0] HEX0
);
  
  localparam cnt_size = 4;
  
  wire                  strobe;
  wire                  next_cnt;
  wire [cnt_size - 1:0] bin_to_led;
  wire [cnt_size - 1:0] gray_data;
  
  strobe_gen #(.div(24))
  strobe_en
    (
     .clk    ( CLOCK_50 ),
     .rst_n  ( KEY[0]   ),
     .strobe ( strobe   )
    );

  assign next_cnt = (!KEY[1]) ? strobe : 1'b0;
  
  // Gray counter on ledr
  gray_cnt #(.WIDTH(cnt_size))
  gcnt
    (
     .clk    ( CLOCK_50  ),
     .rst_n  ( KEY[0]    ),
     .enable ( next_cnt  ),
     .gray   ( gray_data )
    );

  assign LEDR = gray_data;
  
  // Binary representation

  gray2bin #(.WIDTH(cnt_size))
  hex_cnt
    (
     .gray ( gray_data  ),
     .bin  ( bin_to_led )
    );

  led7 #(.COUNT(1)) led7_inst
   (
    .data ( bin_to_led ),
    .leds ( HEX0       )
   );

  
endmodule // de10_lite
module testbench;

  localparam W = 4;
  
  reg              clk;
  reg              rst_n;
  reg              enable;
  wire [W - 1 : 0] gray;
  integer          en_time;
  
  gray_cnt #(.WIDTH(W))
  g_cnt
    (
     // Outputs
     .gray   (gray[W - 1:0]  ),
     // Inputs
     .clk    ( clk           ),
     .rst_n  ( rst_n         ),
     .enable ( enable        )
     );

  initial begin
    clk = 1'b0;
    forever
      #5 clk = !clk;
  end


  initial begin
    $dumpvars();
    
    rst_n  = 1'b1;
    enable = 1'b0;
    //-----Reset----- 
    #13 rst_n = 1'b0;
    #10 rst_n = 1'b1;
    //---------------

    repeat(5) begin
      en_time = $urandom%(30)+10;
      begin
        #11 enable        = 1'b1;
        #(en_time) enable = 1'b0;
      end
    end
    #30 $finish;
  end

endmodule // testbench
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    timer lab6 (KEY[0], SW[0], LEDR[7:0], LEDR[9:8]);
 
endmodule
module de10_lite
(
 input        CLOCK_50,
 input [0:0]  KEY0,
 output [7:0] HEX3,
 output [7:0] HEX2,
 output [7:0] HEX1,
 output [7:0] HEX0
);

  wire [7:0]  sec_bin;
  wire [7:0]  sec_dec;
  wire [7:0]  min_bin;
  wire [7:0]  min_dec;
  
  
  timer #(.ref_clock(50000000))
  my_clock
    (
     .clk     ( CLOCK_50  ),
     .rst_n   ( KEY0    ),
     .seconds ( sec_bin   ),
     .minuts  ( min_bin   )
    );

  // Conversion time to decimal system
  bin2bcd 
    #( .IN_WIDTH (8),
       .DIGITS    (2)
     )
  sec_inst
    (
     .bin(sec_bin),
     .bcd(sec_dec)
     );

  bin2bcd 
    #( .IN_WIDTH (8),
       .DIGITS    (2)
     )
  min_inst
    (
     .bin(min_bin),
     .bcd(min_dec)
     );
  
  // Time on 7segment display
  led7 #(.COUNT(2)) sec_led
    (
     .data ( sec_dec     ),
     .leds ( {HEX1,HEX0} )
    );
  
  led7 #(.COUNT(2)) min_led
    (
     .data ( min_dec     ),
     .leds ( {HEX3,HEX2} )
    );
  
endmodule // de10_lite
module testbench;
  
  reg        clk;
  reg        rst_n;
  wire [7:0] seconds;
  wire [7:0] minuts;

  // Select slow 
  localparam clk_sim = 50;
  
  timer #(.ref_clock(clk_sim)) t1
   (
    .clk     ( clk     ),
    .rst_n   ( rst_n   ),
    .seconds ( seconds ),
    .minuts  ( minuts  )
    );
  
  initial begin
    clk = 1'b0;
    forever #5 clk = ~clk;
  end

  
  initial begin
    $dumpvars();
    
    rst_n = 1'b1;
    #14 rst_n = 1'b0;
    #23 rst_n = 1'b1;
    wait(minuts == 8'd59)
     #4000
    $finish;
  end
  
  endmodule // testbench
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    crc_ser lab6 (SW[2], KEY[0], SW[0], KEY[2], LEDR[4:0]);
 
endmodule
module testbench;
  reg         clk;
  reg         rst_n;
  reg         data;
  wire [4:0]  crc5;
  reg         crc_en;
  
  reg [7:0]   buff;
  //integer     i;    
  
  crc_ser crc (/*AUTOINST*/
               // Outputs
               .crc5                    (crc5),
               // Inputs
               .data                    (data),
               .clk                     (clk),
               .rst_n                   (rst_n),
               .crc_en                  (crc_en));
  initial begin
    clk=1'b0;
    forever #5 clk = !clk;
  end

  task async_rst;
    begin
      $display("@%0t_########## Reset start! ##########",$time);
      #11 rst_n = 1'b0;
      #11 rst_n = 1'b1;
      $display("@%0t_########## Reset finish! ##########",$time);
    end
  endtask // async_rst
   
  task send_byte;
    integer i;
    begin
      buff = $urandom%(255);
      
      for(i=0;i<8;i=i+1) begin
        @(negedge clk)begin
          crc_en  = 1'b1;
          data    = buff[7-i];
        end
      end
      @(negedge clk);
      crc_en = 1'b0;
      i = 0;
    end
  endtask // send_byte

  task push_byte(input [7:0] d_byte);
    integer k;
    begin
      buff = d_byte;
      for(k=0;k<=7;k=k+1)begin
        @(negedge clk)begin
          crc_en = 1'b1;
          data = d_byte[7-k];
        end
      end
      @(negedge clk);
      crc_en = 1'b0;
      k=0;
    end

  endtask // testbench
  
  
  initial begin
    $dumpvars(0);
    data    = 1'b0;
    rst_n   = 1'b1;
    crc_en  = 1'b0;
     
    repeat(10)begin
      async_rst();
      push_byte($urandom%(255));
    end
       
    #20
      $finish;
    
    
  end
  
endmodule // crc_ser_tb
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    lfsr lab6 (KEY[0], SW[0], LEDR[7:0]);
 
endmodule
module testbench;

   reg        clk;
   reg        rst_n;
   wire [7:0] prg_out;
   integer    seq_len;
   
   lfsr l_inst
   (
         // Outputs
         .prg_out ( prg_out ),
         // Inputs
         .clk     ( clk     ),
         .rst_n   ( rst_n   )
   );
   
   initial begin
      clk = 0;
      forever #2 clk = ~clk;
   end

   task async_rst;
      begin
         $display("---------- Start async_reset at %0t ns ----------\n",$time);
         #13 rst_n  = 1'b0;
         #14 rst_n  = 1'b1;
         $display("---------- Finish async_reset at %0t ns ----------\n",$time);
      end
   endtask // async_rst
 
   initial begin
      $dumpvars();
      $monitor("Time=%0t ns\t LFSR=0x%h",$time,prg_out);
      rst_n    = 1'b1;
      seq_len  = 0;
      async_rst();
      #20
      //Max len sequence detect
      forever 
      begin
        @(negedge clk)
          begin
             seq_len = seq_len+1;
             if(prg_out == 8'hfc)begin
                $display("---------- Sequence lenght =%0d ----------\n",seq_len);        
                $finish;
             end
          end
      end
   end
   
endmodule // testbench
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    cnt_updown lab6 (KEY[0], SW[0], KEY[2], LEDR);
 
endmodule
module testbench;
   
   localparam NEW_WIDTH = 32;
   
   reg                  clk;
   reg                  rst_n;
   reg                  up_down;
   wire [NEW_WIDTH-1:0] cnt;
   integer              rst_time;
   integer              i;
   integer              up_time;
   integer              down_time;
   

   cnt_updown #(.WIDTH(NEW_WIDTH)) cnt_dut (
      .clk     ( clk     ),
      .rst_n   ( rst_n   ),
      .up_down ( up_down ),
      .cnt     ( cnt     )
      );
   
  // Clock generator
   initial begin
      clk = 0;
      forever #10 clk = !clk ;
   end

   
   task reset(input integer  rst_time);
      begin
         $display("########## Reset start ##########");
         rst_n      = 1'b0;
         #(rst_time) rst_n  = 1'b1;
         $display("########## Reset finish ##########\n");
      end
   endtask // reset  

   initial begin
      //Init variable for gtkwave
      $dumpvars();

      $monitor("time=%0t\t up_down=%b\t cnt=0x%h",$time,up_down,cnt);
      rst_n    = 1'b1;
      up_down  = 1'b0;

      reset(24);
      
      for(i=0;i<10;i=i+1)begin
         up_time               = $urandom%(1000)+20;
         down_time             = $urandom%(1000)+20;
         #(up_time) up_down    = 1'b0;
         #(down_time) up_down  = 1'b1;
      end

      #100 $finish;
      
   end
endmodule // testbench
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    cnt_div lab6 (KEY[0], SW[0], LEDR[0]);
 
endmodule
module testbench;

   localparam DIV_CNT = 10;
   
   reg  clk_in;
   reg  rst_n;
   wire clk_out;
   
   

   cnt_div #(.DIV_CNT(DIV_CNT)) 
   cnt_dut(
	         .clk_in  ( clk_in  ),
	         .rst_n   ( rst_n   ),
	         .clk_out ( clk_out )
	 );
   
   //Clock generation
   initial begin
      clk_in = 0;
      forever #10 clk_in = !clk_in;
   end

      
   initial begin
      $dumpvars();
      rst_n      = 1'b1;
      #13 rst_n  = 1'b0;
      #25 rst_n  = 1'b1;
      repeat(5)
        @(posedge clk_out);
      #20 $finish;
      
   end

endmodule // testbench
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    tone_gen lab6 (KEY[0], SW[0], LEDR[0]);
 
endmodule
module testbench;

  reg clk;
  reg rst_n;
  wire tone_freq;

  time start,stop;
  initial begin
    clk = 1'b0;
    forever
      #1 clk = !clk;
  end
  
  tone_gen
    #(
      .ref_clock     ( 50000000 ),
      .out_freq_x100 ( 50000    )
     )
  tone_dut
    (
     .clk       ( clk       ),
     .rst_n     ( rst_n     ),
     .tone_freq ( tone_freq )
    );

  task info;
    begin
      @(posedge tone_freq);
      start = $time;
      $display("@%0t\ttone_freq activate",$time);
      @(negedge tone_freq);
      stop = $time;
      $display("@%0t\ttone_freq deactive",$time);
      $display("----------Pulse duration = %0t----------\n",stop-start);
    end
  endtask // info
  


  initial begin
    $dumpvars();
    
    rst_n     = 1'b1;
   
    #11 rst_n = 1'b0;
    #11 rst_n = 1'b1;

    repeat(4)begin
      info;
    end
      
    #100 $finish;
   
  end
  
endmodule // testbench
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    simple_counter lab6 (KEY[0], SW[0], LEDR);
 
endmodule
module testbench;

   localparam W = 8;

   reg          clk;
   reg          rst_n;
   wire [W-1:0] cnt;

 
   simple_counter #(.WIDTH(W))
   cnt1(
 // Outputs
        .cnt    ( cnt   ),
 // Inputs
        .clk    ( clk   ),
        .rst_n  ( rst_n ));
   
   //Clock generation
   initial begin
      clk = 0;
      forever #10 clk = !clk;
   end

   initial begin
      $dumpvars;
      
      $monitor("@time=%0t\t cnt=0x%h\n",$time,cnt);
      rst_n      = 1;
      #15 rst_n  = 0;
      #25 rst_n  = 1;
      #350 $finish;
   end
endmodule // testbench