module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);

parameter INT_ROM_WID= 10;

input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg ea_int;
reg [4:0] addr01;
reg [7:0] data1, data2, data3;

wire ea;
wire [15:0] addr_rst;
wire [7:0] int_data0, int_data1, int_data2, int_data3, int_data4, int_data5, int_data6, int_data7, int_data8, int_data9, int_data10, int_data11, int_data12, int_data13, int_data14, int_data15, int_data16, int_data17, int_data18, int_data19, int_data20, int_data21, int_data22, int_data23, int_data24, int_data25, int_data26, int_data27, int_data28, int_data29, int_data30, int_data31;

assign ea = | addr[15:INT_ROM_WID];

assign addr_rst = rst ? 16'h0000 : addr;

  rom0 rom_0 (.a(addr01), .o(int_data0));
  rom1 rom_1 (.a(addr01), .o(int_data1));
  rom2 rom_2 (.a(addr_rst[9:5]), .o(int_data2));
  rom3 rom_3 (.a(addr_rst[9:5]), .o(int_data3));
  rom4 rom_4 (.a(addr_rst[9:5]), .o(int_data4));
  rom5 rom_5 (.a(addr_rst[9:5]), .o(int_data5));
  rom6 rom_6 (.a(addr_rst[9:5]), .o(int_data6));
  rom7 rom_7 (.a(addr_rst[9:5]), .o(int_data7));
  rom8 rom_8 (.a(addr_rst[9:5]), .o(int_data8));
  rom9 rom_9 (.a(addr_rst[9:5]), .o(int_data9));
  rom10 rom_10 (.a(addr_rst[9:5]), .o(int_data10));
  rom11 rom_11 (.a(addr_rst[9:5]), .o(int_data11));
  rom12 rom_12 (.a(addr_rst[9:5]), .o(int_data12));
  rom13 rom_13 (.a(addr_rst[9:5]), .o(int_data13));
  rom14 rom_14 (.a(addr_rst[9:5]), .o(int_data14));
  rom15 rom_15 (.a(addr_rst[9:5]), .o(int_data15));
  rom16 rom_16 (.a(addr_rst[9:5]), .o(int_data16));
  rom17 rom_17 (.a(addr_rst[9:5]), .o(int_data17));
  rom18 rom_18 (.a(addr_rst[9:5]), .o(int_data18));
  rom19 rom_19 (.a(addr_rst[9:5]), .o(int_data19));
  rom20 rom_20 (.a(addr_rst[9:5]), .o(int_data20));
  rom21 rom_21 (.a(addr_rst[9:5]), .o(int_data21));
  rom22 rom_22 (.a(addr_rst[9:5]), .o(int_data22));
  rom23 rom_23 (.a(addr_rst[9:5]), .o(int_data23));
  rom24 rom_24 (.a(addr_rst[9:5]), .o(int_data24));
  rom25 rom_25 (.a(addr_rst[9:5]), .o(int_data25));
  rom26 rom_26 (.a(addr_rst[9:5]), .o(int_data26));
  rom27 rom_27 (.a(addr_rst[9:5]), .o(int_data27));
  rom28 rom_28 (.a(addr_rst[9:5]), .o(int_data28));
  rom29 rom_29 (.a(addr_rst[9:5]), .o(int_data29));
  rom30 rom_30 (.a(addr_rst[9:5]), .o(int_data30));
  rom31 rom_31 (.a(addr_rst[9:5]), .o(int_data31));

always @(addr_rst)
begin
  if (addr_rst[1])
    addr01= addr_rst[9:5]+ 5'h1;
  else
    addr01= addr_rst[9:5];
end

//
// always read tree bits in row
always @(posedge clk)
begin
  case(addr[4:0])
    5'd0: begin
      data1 <= #1 int_data0;
      data2 <= #1 int_data1;
      data3 <= #1 int_data2;
	end
    5'd1: begin
      data1 <= #1 int_data1;
      data2 <= #1 int_data2;
      data3 <= #1 int_data3;
	end
    5'd2: begin
      data1 <= #1 int_data2;
      data2 <= #1 int_data3;
      data3 <= #1 int_data4;
	end
    5'd3: begin
      data1 <= #1 int_data3;
      data2 <= #1 int_data4;
      data3 <= #1 int_data5;
	end
    5'd4: begin
      data1 <= #1 int_data4;
      data2 <= #1 int_data5;
      data3 <= #1 int_data6;
	end
    5'd5: begin
      data1 <= #1 int_data5;
      data2 <= #1 int_data6;
      data3 <= #1 int_data7;
	end
    5'd6: begin
      data1 <= #1 int_data6;
      data2 <= #1 int_data7;
      data3 <= #1 int_data8;
	end
    5'd7: begin
      data1 <= #1 int_data7;
      data2 <= #1 int_data8;
      data3 <= #1 int_data9;
	end
    5'd8: begin
      data1 <= #1 int_data8;
      data2 <= #1 int_data9;
      data3 <= #1 int_data10;
	end
    5'd9: begin
      data1 <= #1 int_data9;
      data2 <= #1 int_data10;
      data3 <= #1 int_data11;
	end
    5'd10: begin
      data1 <= #1 int_data10;
      data2 <= #1 int_data11;
      data3 <= #1 int_data12;
	end
    5'd11: begin
      data1 <= #1 int_data11;
      data2 <= #1 int_data12;
      data3 <= #1 int_data13;
	end
    5'd12: begin
      data1 <= #1 int_data12;
      data2 <= #1 int_data13;
      data3 <= #1 int_data14;
	end
    5'd13: begin
      data1 <= #1 int_data13;
      data2 <= #1 int_data14;
      data3 <= #1 int_data15;
	end
    5'd14: begin
      data1 <= #1 int_data14;
      data2 <= #1 int_data15;
      data3 <= #1 int_data16;
	end
    5'd15: begin
      data1 <= #1 int_data15;
      data2 <= #1 int_data16;
      data3 <= #1 int_data17;
	end
    5'd16: begin
      data1 <= #1 int_data16;
      data2 <= #1 int_data17;
      data3 <= #1 int_data18;
	end
    5'd17: begin
      data1 <= #1 int_data17;
      data2 <= #1 int_data18;
      data3 <= #1 int_data19;
	end
    5'd18: begin
      data1 <= #1 int_data18;
      data2 <= #1 int_data19;
      data3 <= #1 int_data20;
	end
    5'd19: begin
      data1 <= #1 int_data19;
      data2 <= #1 int_data20;
      data3 <= #1 int_data21;
	end
    5'd20: begin
      data1 <= #1 int_data20;
      data2 <= #1 int_data21;
      data3 <= #1 int_data22;
	end
    5'd21: begin
      data1 <= #1 int_data21;
      data2 <= #1 int_data22;
      data3 <= #1 int_data23;
	end
    5'd22: begin
      data1 <= #1 int_data22;
      data2 <= #1 int_data23;
      data3 <= #1 int_data24;
	end
    5'd23: begin
      data1 <= #1 int_data23;
      data2 <= #1 int_data24;
      data3 <= #1 int_data25;
	end
    5'd24: begin
      data1 <= #1 int_data24;
      data2 <= #1 int_data25;
      data3 <= #1 int_data26;
	end
    5'd25: begin
      data1 <= #1 int_data25;
      data2 <= #1 int_data26;
      data3 <= #1 int_data27;
	end
    5'd26: begin
      data1 <= #1 int_data26;
      data2 <= #1 int_data27;
      data3 <= #1 int_data28;
	end
    5'd27: begin
      data1 <= #1 int_data27;
      data2 <= #1 int_data28;
      data3 <= #1 int_data29;
	end
    5'd28: begin
      data1 <= #1 int_data28;
      data2 <= #1 int_data29;
      data3 <= #1 int_data30;
	end
    5'd29: begin
      data1 <= #1 int_data29;
      data2 <= #1 int_data30;
      data3 <= #1 int_data31;
	end
    5'd30: begin
      data1 <= #1 int_data30;
      data2 <= #1 int_data31;
      data3 <= #1 int_data0;
	end
    5'd31: begin
      data1 <= #1 int_data31;
      data2 <= #1 int_data0;
      data3 <= #1 int_data1;
	end
    default: begin
      data1 <= #1 8'h00;
      data2 <= #1 8'h00;
      data3 <= #1 8'h00;
	end
  endcase
end

always @(posedge clk or posedge rst)
 if (rst)
   ea_int <= #1 1'b1;
  else ea_int <= #1 !ea;

endmodule