dakies/OSS_Verilog huggingface dataset:
module axi_serializer_intf #(
  /// AXI4+ATOP ID width.
  parameter int unsigned AXI_ID_WIDTH   = 32'd0,
  /// AXI4+ATOP address width.
  parameter int unsigned AXI_ADDR_WIDTH = 32'd0,
  /// AXI4+ATOP data width.
  parameter int unsigned AXI_DATA_WIDTH = 32'd0,
  /// AXI4+ATOP user width.
  parameter int unsigned AXI_USER_WIDTH = 32'd0,
  /// Maximum number of in flight read transactions.
  parameter int unsigned MAX_READ_TXNS  = 32'd0,
  /// Maximum number of in flight write transactions.
  parameter int unsigned MAX_WRITE_TXNS = 32'd0
) (
  /// Clock
  input  logic    clk_i,
  /// Asynchronous reset, active low
  input  logic    rst_ni,
  /// AXI4+ATOP Slave modport
  AXI_BUS.Slave   slv,
  /// AXI4+ATOP Master modport
  AXI_BUS.Master  mst
);

  typedef logic [AXI_ID_WIDTH    -1:0] id_t;
  typedef logic [AXI_ADDR_WIDTH  -1:0] addr_t;
  typedef logic [AXI_DATA_WIDTH  -1:0] data_t;
  typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
  typedef logic [AXI_USER_WIDTH  -1:0] user_t;
  `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
  `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
  `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
  `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
  `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
  `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
  `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
  req_t  slv_req,  mst_req;
  resp_t slv_resp, mst_resp;
  `AXI_ASSIGN_TO_REQ(slv_req, slv)
  `AXI_ASSIGN_FROM_RESP(slv, slv_resp)
  `AXI_ASSIGN_FROM_REQ(mst, mst_req)
  `AXI_ASSIGN_TO_RESP(mst_resp, mst)

  axi_serializer #(
    .MaxReadTxns  ( MAX_READ_TXNS  ),
    .MaxWriteTxns ( MAX_WRITE_TXNS ),
    .AxiIdWidth   ( AXI_ID_WIDTH   ),
    .req_t        ( req_t          ),
    .resp_t       ( resp_t         )
  ) i_axi_serializer (
    .clk_i,
    .rst_ni,
    .slv_req_i  ( slv_req  ),
    .slv_resp_o ( slv_resp ),
    .mst_req_o  ( mst_req  ),
    .mst_resp_i ( mst_resp )
  );

// pragma translate_off
`ifndef VERILATOR
  initial begin: p_assertions
    assert (AXI_ADDR_WIDTH  >= 1) else $fatal(1, "AXI address width must be at least 1!");
    assert (AXI_DATA_WIDTH  >= 1) else $fatal(1, "AXI data width must be at least 1!");
    assert (AXI_ID_WIDTH    >= 1) else $fatal(1, "AXI ID width must be at least 1!");
    assert (AXI_USER_WIDTH  >= 1) else $fatal(1, "AXI user width must be at least 1!");
    assert (MAX_READ_TXNS   >= 1)
      else $fatal(1, "Maximum number of read transactions must be >= 1!");
    assert (MAX_WRITE_TXNS  >= 1)
      else $fatal(1, "Maximum number of write transactions must be >= 1!");
  end
`endif
// pragma translate_on
endmodule
module axi_cdc_intf #(
  parameter int unsigned AXI_ID_WIDTH   = 0,
  parameter int unsigned AXI_ADDR_WIDTH = 0,
  parameter int unsigned AXI_DATA_WIDTH = 0,
  parameter int unsigned AXI_USER_WIDTH = 0,
  /// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
  parameter int unsigned LOG_DEPTH = 1
) (
   // slave side - clocked by `src_clk_i`
  input  logic      src_clk_i,
  input  logic      src_rst_ni,
  AXI_BUS.Slave     src,
  // master side - clocked by `dst_clk_i`
  input  logic      dst_clk_i,
  input  logic      dst_rst_ni,
  AXI_BUS.Master    dst
);

  typedef logic [AXI_ID_WIDTH-1:0]     id_t;
  typedef logic [AXI_ADDR_WIDTH-1:0]   addr_t;
  typedef logic [AXI_DATA_WIDTH-1:0]   data_t;
  typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
  typedef logic [AXI_USER_WIDTH-1:0]   user_t;
  `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
  `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
  `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
  `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
  `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
  `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
  `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)

  req_t  src_req,  dst_req;
  resp_t src_resp, dst_resp;

  `AXI_ASSIGN_TO_REQ(src_req, src)
  `AXI_ASSIGN_FROM_RESP(src, src_resp)

  `AXI_ASSIGN_FROM_REQ(dst, dst_req)
  `AXI_ASSIGN_TO_RESP(dst_resp, dst)

  axi_cdc #(
    .aw_chan_t  ( aw_chan_t ),
    .w_chan_t   ( w_chan_t  ),
    .b_chan_t   ( b_chan_t  ),
    .ar_chan_t  ( ar_chan_t ),
    .r_chan_t   ( r_chan_t  ),
    .axi_req_t  ( req_t     ),
    .axi_resp_t ( resp_t    ),
    .LogDepth   ( LOG_DEPTH )
  ) i_axi_cdc (
    .src_clk_i,
    .src_rst_ni,
    .src_req_i  ( src_req  ),
    .src_resp_o ( src_resp ),
    .dst_clk_i,
    .dst_rst_ni,
    .dst_req_o  ( dst_req  ),
    .dst_resp_i ( dst_resp )
  );

endmodule
module axi_lite_cdc_intf #(
  parameter int unsigned AXI_ADDR_WIDTH = 0,
  parameter int unsigned AXI_DATA_WIDTH = 0,
  /// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
  parameter int unsigned LOG_DEPTH = 1
) (
   // slave side - clocked by `src_clk_i`
  input  logic      src_clk_i,
  input  logic      src_rst_ni,
  AXI_LITE.Slave    src,
  // master side - clocked by `dst_clk_i`
  input  logic      dst_clk_i,
  input  logic      dst_rst_ni,
  AXI_LITE.Master   dst
);

  typedef logic [AXI_ADDR_WIDTH-1:0]   addr_t;
  typedef logic [AXI_DATA_WIDTH-1:0]   data_t;
  typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
  `AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)
  `AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t)
  `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)
  `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)
  `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)
  `AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
  `AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)

  req_t  src_req,  dst_req;
  resp_t src_resp, dst_resp;

  `AXI_LITE_ASSIGN_TO_REQ(src_req, src)
  `AXI_LITE_ASSIGN_FROM_RESP(src, src_resp)

  `AXI_LITE_ASSIGN_FROM_REQ(dst, dst_req)
  `AXI_LITE_ASSIGN_TO_RESP(dst_resp, dst)

  axi_cdc #(
    .aw_chan_t  ( aw_chan_t ),
    .w_chan_t   ( w_chan_t  ),
    .b_chan_t   ( b_chan_t  ),
    .ar_chan_t  ( ar_chan_t ),
    .r_chan_t   ( r_chan_t  ),
    .axi_req_t  ( req_t     ),
    .axi_resp_t ( resp_t    ),
    .LogDepth   ( LOG_DEPTH )
  ) i_axi_cdc (
    .src_clk_i,
    .src_rst_ni,
    .src_req_i  ( src_req  ),
    .src_resp_o ( src_resp ),
    .dst_clk_i,
    .dst_rst_ni,
    .dst_req_o  ( dst_req  ),
    .dst_resp_i ( dst_resp )
  );

endmodule
module axi_lite_regs_intf #(
  parameter type byte_t = logic [7:0],
  parameter int unsigned                REG_NUM_BYTES  = 32'd0,
  parameter int unsigned                AXI_ADDR_WIDTH = 32'd0,
  parameter int unsigned                AXI_DATA_WIDTH = 32'd0,
  parameter bit                         PRIV_PROT_ONLY = 1'd0,
  parameter bit                         SECU_PROT_ONLY = 1'd0,
  parameter logic  [REG_NUM_BYTES-1:0]  AXI_READ_ONLY = {REG_NUM_BYTES{1'b0}},
  parameter byte_t [REG_NUM_BYTES-1:0]  REG_RST_VAL = {REG_NUM_BYTES{8'h00}}
) (
  input  logic                      clk_i,
  input  logic                      rst_ni,
  AXI_LITE.Slave                    slv,
  output logic  [REG_NUM_BYTES-1:0] wr_active_o,
  output logic  [REG_NUM_BYTES-1:0] rd_active_o,
  input  byte_t [REG_NUM_BYTES-1:0] reg_d_i,
  input  logic  [REG_NUM_BYTES-1:0] reg_load_i,
  output byte_t [REG_NUM_BYTES-1:0] reg_q_o
);

  typedef logic [AXI_ADDR_WIDTH-1:0]   addr_t;
  typedef logic [AXI_DATA_WIDTH-1:0]   data_t;
  typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
  `AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_lite_t, addr_t)
  `AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_lite_t, data_t, strb_t)
  `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_lite_t)
  `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_lite_t, addr_t)
  `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_lite_t, data_t)
  `AXI_LITE_TYPEDEF_REQ_T(req_lite_t, aw_chan_lite_t, w_chan_lite_t, ar_chan_lite_t)
  `AXI_LITE_TYPEDEF_RESP_T(resp_lite_t, b_chan_lite_t, r_chan_lite_t)

  req_lite_t  axi_lite_req;
  resp_lite_t axi_lite_resp;

  `AXI_LITE_ASSIGN_TO_REQ(axi_lite_req, slv)
  `AXI_LITE_ASSIGN_FROM_RESP(slv, axi_lite_resp)

  axi_lite_regs #(
    .RegNumBytes  ( REG_NUM_BYTES  ),
    .AxiAddrWidth ( AXI_ADDR_WIDTH ),
    .AxiDataWidth ( AXI_DATA_WIDTH ),
    .PrivProtOnly ( PRIV_PROT_ONLY ),
    .SecuProtOnly ( SECU_PROT_ONLY ),
    .AxiReadOnly  ( AXI_READ_ONLY  ),
    .RegRstVal    ( REG_RST_VAL    ),
    .req_lite_t   ( req_lite_t     ),
    .resp_lite_t  ( resp_lite_t    )
  ) i_axi_lite_regs (
    .clk_i,
    .rst_ni,
    .axi_req_i   ( axi_lite_req  ),
    .axi_resp_o  ( axi_lite_resp ),
    .wr_active_o,
    .rd_active_o,
    .reg_d_i,
    .reg_load_i,
    .reg_q_o
  );

  // Validate parameters.
  // pragma translate_off
  `ifndef VERILATOR
    initial begin: p_assertions
      assert (AXI_ADDR_WIDTH == $bits(slv.aw_addr))
          else $fatal(1, "AXI_ADDR_WIDTH does not match slv interface!");
      assert (AXI_DATA_WIDTH == $bits(slv.w_data))
          else $fatal(1, "AXI_DATA_WIDTH does not match slv interface!");
    end
  `endif
  // pragma translate_on
endmodule
module TestBench ();
  parameter CLOCK_FREQ = 100_000_000;
  parameter CLOCK_PERIOD = 1_000_000_000 / CLOCK_FREQ;

  // setup clock and reset
  reg clk, rst;
  initial clk = 'b0;
  always #(CLOCK_PERIOD/2) clk = ~clk;
  


  Tile dut (
    .clock(clk),
    .reset(rst),
    .io_led()
);

  reg clock;


  initial begin
    
    // set up logging
    // $dumpfile("out.vcd");
    // $dumpvars(0, top);
    $fsdbDumpfile("out.fsdb");
    $fsdbDumpvars("+all");

    
    #0;
    rst = 1;
    $display("[TEST]\tRESET pulled HIGH.");
    repeat(2) @(posedge clk);
    
    @(negedge clk);
    rst = 0;
    $display("[TEST]\tRESET pulled LOW.");
    @(posedge clk);

   repeat(100) @(posedge clk);

    $display("[TEST]\tDONE.");

    $finish;
  end

endmodule
module TB_Tile();
  parameter CLOCK_FREQ = 100_000_000;
  parameter CLOCK_PERIOD = 1_000_000_000 / CLOCK_FREQ;

  // setup clock and reset
  reg clk, rst;
  initial clk = 'b0;
  always #(CLOCK_PERIOD/2) clk = ~clk;
  
  Tile dut (
    .clk(clk),
    .rst(rst),

    .led()
  );

  initial begin
    #0;
    rst = 1;
    $display("[TEST]\tRESET pulled HIGH.");
    repeat(2) @(posedge clk);
    
    @(negedge clk);
    rst = 0;
    $display("[TEST]\tRESET pulled LOW.");
    @(posedge clk);
    
    
   repeat(10000) @(posedge clk);
    
    


   $finish();
  end

endmodule
module nvme_buffer_ram
  #(
    parameter ADDR_BITS = 8,
    parameter DEPTH = 2**8
  ) (
    input wire                    wclk,
    input wire [3:0]              we,
    input wire [ADDR_BITS-1:0]    waddr,
    input wire [127:0]            din,
    input wire                    rclk,
    input wire                    re,
    input wire [ADDR_BITS-1:0]    raddr,
    output logic [127:0]          dout
  );

  reg [31:0] ram0 [0:DEPTH-1];
  reg [31:0] ram1 [0:DEPTH-1];
  reg [31:0] ram2 [0:DEPTH-1];
  reg [31:0] ram3 [0:DEPTH-1];

  always @(posedge rclk)
  begin : READ_P
    if (re) begin
      dout <= {ram3[raddr], ram2[raddr], ram1[raddr], ram0[raddr]};
    end
  end

  always @(posedge wclk)
  begin : WRITE_P
    if (we[0]) begin
      ram0[waddr] <= din[31:0];
    end
    if (we[1]) begin
      ram1[waddr] <= din[63:32];
    end
    if (we[2]) begin
      ram2[waddr] <= din[95:64];
    end
    if (we[3]) begin
      ram3[waddr] <= din[127:96];
    end
  end

endmodule
module rvfi_bus_util_fifo_stage #(
	parameter WIDTH = 8
) (
	input clock,
	input reset,

	input              in_valid,
	output             in_ready,
	input  [WIDTH-1:0] in_data,

	output             out_valid,
	input              out_ready,
	output [WIDTH-1:0] out_data
);

	reg [WIDTH-1:0] buffered;
	reg buffer_valid;

	wire in_txn = in_valid && in_ready;
	wire out_txn = out_valid && out_ready;

	assign out_data = buffer_valid ? buffered : in_data;
	assign in_ready = out_ready || !buffer_valid;
	assign out_valid = in_valid || buffer_valid;

	always @(posedge clock) begin
		if (reset) begin
			buffer_valid <= 0;
		end else begin
			if (in_txn != out_txn)
				buffer_valid <= in_txn;
		end
		if (in_txn)
			buffered <= in_data;
	end

endmodule
module rvfi_bus_util_fifo #(
	parameter WIDTH = 8,
	parameter DEPTH = 3
) (
	input clock,
	input reset,

	input              in_valid,
	output             in_ready,
	input  [WIDTH-1:0] in_data,

	output             out_valid,
	input              out_ready,
	output [WIDTH-1:0] out_data
);

	wire [WIDTH-1:0] stage_data [0:DEPTH];
	wire [DEPTH:0] stage_valid;
	wire [DEPTH:0] stage_ready;

	genvar i;
	generate for (i = 0; i < DEPTH; i = i + 1) begin
		rvfi_bus_util_fifo_stage #(.WIDTH(WIDTH)) stage (
			.clock(clock),
			.reset(reset),
			.in_data(stage_data[i]),
			.out_data(stage_data[i+1]),
			.in_valid(stage_valid[i]),
			.out_valid(stage_valid[i+1]),
			.in_ready(stage_ready[i]),
			.out_ready(stage_ready[i+1])
		);
	end endgenerate

	assign stage_valid[0] = in_valid;
	assign stage_data[0] = in_data;
	assign in_ready = stage_ready[0];

	assign out_valid = stage_valid[DEPTH];
	assign stage_ready[DEPTH] = out_ready;
	assign out_data = stage_data[DEPTH];
endmodule
module testbench (
	input clk
);
	reg reset = 1;

	always @(posedge clk)
		reset <= 0;




	(* keep *) wire        iBus_cmd_valid;
	(* keep *) wire [31:0] iBus_cmd_payload_pc;
	(* keep *) `rvformal_rand_reg iBus_cmd_ready;
	(* keep *) `rvformal_rand_reg iBus_rsp_ready;
	(* keep *) `rvformal_rand_reg [31:0] iBus_rsp_inst;


	(* keep *) wire  dBus_cmd_valid;
	(* keep *) wire  dBus_cmd_payload_wr;
	(* keep *) wire [31:0] dBus_cmd_payload_address;
	(* keep *) wire [31:0] dBus_cmd_payload_data;
	(* keep *) wire [1:0] dBus_cmd_payload_size;
	(* keep *) `rvformal_rand_reg dBus_cmd_ready;
	(* keep *) `rvformal_rand_reg    dBus_rsp_ready;
	(* keep *) `rvformal_rand_reg   [31:0] dBus_rsp_data;


	`RVFI_WIRES

	(* keep *) wire [31:0] dmem_addr;
	(* keep *) reg [31:0] dmem_data;

	rvfi_dmem_check checker_inst (
		.clock     (clk      ),
		.reset     (reset  ),
		.enable    (1'b1     ),
		.dmem_addr (dmem_addr),
		`RVFI_CONN
	);

	(* keep *) reg dmem_last_valid;
	(* keep *) wire [3:0] dBus_cmd_payload_mask;

	assign dBus_cmd_payload_mask = ((1 << (1 << dBus_cmd_payload_size))-1) << dBus_cmd_payload_address[1:0];

	


	always @(posedge clk) begin
		if (reset) begin
			dmem_last_valid <= 0;
		end else begin
			if(dmem_last_valid) begin
				assume(dBus_rsp_data == dmem_data);
			end
			if(dBus_rsp_ready) begin
				dmem_last_valid <= 0;
			end
			if(dBus_cmd_valid && dBus_cmd_ready) begin
				if((dBus_cmd_payload_address >> 2) == (dmem_addr >> 2)) begin
					if(!dBus_cmd_payload_wr) begin
						dmem_last_valid <= 1;
					end else begin
						if (dBus_cmd_payload_mask[0]) dmem_data[ 7: 0] <= dBus_cmd_payload_data[ 7: 0];
						if (dBus_cmd_payload_mask[1]) dmem_data[15: 8] <= dBus_cmd_payload_data[15: 8];
						if (dBus_cmd_payload_mask[2]) dmem_data[23:16] <= dBus_cmd_payload_data[23:16];
						if (dBus_cmd_payload_mask[3]) dmem_data[31:24] <= dBus_cmd_payload_data[31:24];
					end
				end
			end
			
		end
		
	end





	VexRiscv uut (
		.clk       (clk    ),
		.reset    (reset   ),

		.iBus_cmd_valid (iBus_cmd_valid),
		.iBus_cmd_ready (iBus_cmd_ready),
		.iBus_cmd_payload_pc  (iBus_cmd_payload_pc ),
		.iBus_rsp_ready(iBus_rsp_ready),
		.iBus_rsp_inst (iBus_rsp_inst),
		.iBus_rsp_error(1'b0),

		.dBus_cmd_valid(dBus_cmd_valid),
		.dBus_cmd_payload_wr(dBus_cmd_payload_wr),
		.dBus_cmd_payload_address(dBus_cmd_payload_address),
		.dBus_cmd_payload_data(dBus_cmd_payload_data),
		.dBus_cmd_payload_size(dBus_cmd_payload_size),
		.dBus_cmd_ready(dBus_cmd_ready),
		.dBus_rsp_ready(dBus_rsp_ready),
		.dBus_rsp_data(dBus_rsp_data),
		.dBus_rsp_error(1'b0),

		`RVFI_CONN
	);

endmodule
module testbench (
	input clk
);
	reg reset = 1;

	always @(posedge clk)
		reset <= 0;




	(* keep *) wire        iBus_cmd_valid;
	(* keep *) wire [31:0] iBus_cmd_payload_pc;
	(* keep *) `rvformal_rand_reg iBus_cmd_ready;
	(* keep *) `rvformal_rand_reg iBus_rsp_ready;
	(* keep *) `rvformal_rand_reg [31:0] iBus_rsp_inst;


	(* keep *) wire  dBus_cmd_valid;
	(* keep *) wire  dBus_cmd_payload_wr;
	(* keep *) wire [31:0] dBus_cmd_payload_address;
	(* keep *) wire [31:0] dBus_cmd_payload_data;
	(* keep *) wire [1:0] dBus_cmd_payload_size;
	(* keep *) `rvformal_rand_reg dBus_cmd_ready;
	(* keep *) `rvformal_rand_reg    dBus_rsp_ready;
	(* keep *) `rvformal_rand_reg   [31:0] dBus_rsp_data;



	`RVFI_WIRES

	(* keep *) wire [31:0] imem_addr;
	(* keep *) wire [15:0] imem_data;

	rvfi_imem_check checker_inst (
		.clock     (clk      ),
		.reset     (reset  ),
		.enable    (1'b1     ),
		.imem_addr (imem_addr),
		.imem_data (imem_data),
		`RVFI_CONN
	);

	(* keep *) wire imem_last_valid;
	(* keep *) wire [31:0] imem_last_addr;

	always @(posedge clk) begin
		if (reset) begin
			imem_last_valid <= 0;
		end else begin
			if(imem_last_valid) begin
				if (imem_last_addr == imem_addr)
					assume(iBus_rsp_inst[15:0] == imem_data);
				if (imem_last_addr+2 == imem_addr)
					assume(iBus_rsp_inst[31:16] == imem_data);
			end
			if(iBus_rsp_ready) begin
				imem_last_valid <= 0;
			end
			if(iBus_cmd_valid && iBus_cmd_ready) begin
				imem_last_valid <= 1;
				imem_last_addr <= iBus_cmd_payload_pc;
			end
		end
		
	end





	VexRiscv uut (
		.clk       (clk    ),
		.reset    (reset   ),

		.iBus_cmd_valid (iBus_cmd_valid),
		.iBus_cmd_ready (iBus_cmd_ready),
		.iBus_cmd_payload_pc  (iBus_cmd_payload_pc ),
		.iBus_rsp_ready(iBus_rsp_ready),
		.iBus_rsp_inst (iBus_rsp_inst),
		.iBus_rsp_error(1'b0),

		.dBus_cmd_valid(dBus_cmd_valid),
		.dBus_cmd_payload_wr(dBus_cmd_payload_wr),
		.dBus_cmd_payload_address(dBus_cmd_payload_address),
		.dBus_cmd_payload_data(dBus_cmd_payload_data),
		.dBus_cmd_payload_size(dBus_cmd_payload_size),
		.dBus_cmd_ready(dBus_cmd_ready),
		.dBus_rsp_ready(dBus_rsp_ready),
		.dBus_rsp_data(dBus_rsp_data),
		.dBus_rsp_error(1'b0),

		`RVFI_CONN
	);

endmodule
module SB_RAM40_4KNR (
	output [15:0] RDATA,
	input         RCLKN, RCLKE, RE,
	input  [10:0] RADDR,
	input         WCLK, WCLKE, WE,
	input  [10:0] WADDR,
	input  [15:0] MASK, WDATA
);
	parameter WRITE_MODE = 0;
	parameter READ_MODE = 0;

	parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;

	SB_RAM40_4K #(
		.WRITE_MODE(WRITE_MODE),
		.READ_MODE (READ_MODE ),
		.INIT_0    (INIT_0    ),
		.INIT_1    (INIT_1    ),
		.INIT_2    (INIT_2    ),
		.INIT_3    (INIT_3    ),
		.INIT_4    (INIT_4    ),
		.INIT_5    (INIT_5    ),
		.INIT_6    (INIT_6    ),
		.INIT_7    (INIT_7    ),
		.INIT_8    (INIT_8    ),
		.INIT_9    (INIT_9    ),
		.INIT_A    (INIT_A    ),
		.INIT_B    (INIT_B    ),
		.INIT_C    (INIT_C    ),
		.INIT_D    (INIT_D    ),
		.INIT_E    (INIT_E    ),
		.INIT_F    (INIT_F    )
	) RAM (
		.RDATA(RDATA),
		.RCLK (~RCLKN),
		.RCLKE(RCLKE),
		.RE   (RE   ),
		.RADDR(RADDR),
		.WCLK (WCLK ),
		.WCLKE(WCLKE),
		.WE   (WE   ),
		.WADDR(WADDR),
		.MASK (MASK ),
		.WDATA(WDATA)
	);
endmodule
module SB_RAM40_4KNW (
	output [15:0] RDATA,
	input         RCLK, RCLKE, RE,
	input  [10:0] RADDR,
	input         WCLKN, WCLKE, WE,
	input  [10:0] WADDR,
	input  [15:0] MASK, WDATA
);
	parameter WRITE_MODE = 0;
	parameter READ_MODE = 0;

	parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;

	SB_RAM40_4K #(
		.WRITE_MODE(WRITE_MODE),
		.READ_MODE (READ_MODE ),
		.INIT_0    (INIT_0    ),
		.INIT_1    (INIT_1    ),
		.INIT_2    (INIT_2    ),
		.INIT_3    (INIT_3    ),
		.INIT_4    (INIT_4    ),
		.INIT_5    (INIT_5    ),
		.INIT_6    (INIT_6    ),
		.INIT_7    (INIT_7    ),
		.INIT_8    (INIT_8    ),
		.INIT_9    (INIT_9    ),
		.INIT_A    (INIT_A    ),
		.INIT_B    (INIT_B    ),
		.INIT_C    (INIT_C    ),
		.INIT_D    (INIT_D    ),
		.INIT_E    (INIT_E    ),
		.INIT_F    (INIT_F    )
	) RAM (
		.RDATA(RDATA),
		.RCLK (RCLK ),
		.RCLKE(RCLKE),
		.RE   (RE   ),
		.RADDR(RADDR),
		.WCLK (~WCLKN),
		.WCLKE(WCLKE),
		.WE   (WE   ),
		.WADDR(WADDR),
		.MASK (MASK ),
		.WDATA(WDATA)
	);
endmodule
module SB_RAM40_4KNRNW (
	output [15:0] RDATA,
	input         RCLKN, RCLKE, RE,
	input  [10:0] RADDR,
	input         WCLKN, WCLKE, WE,
	input  [10:0] WADDR,
	input  [15:0] MASK, WDATA
);
	parameter WRITE_MODE = 0;
	parameter READ_MODE = 0;

	parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;

	SB_RAM40_4K #(
		.WRITE_MODE(WRITE_MODE),
		.READ_MODE (READ_MODE ),
		.INIT_0    (INIT_0    ),
		.INIT_1    (INIT_1    ),
		.INIT_2    (INIT_2    ),
		.INIT_3    (INIT_3    ),
		.INIT_4    (INIT_4    ),
		.INIT_5    (INIT_5    ),
		.INIT_6    (INIT_6    ),
		.INIT_7    (INIT_7    ),
		.INIT_8    (INIT_8    ),
		.INIT_9    (INIT_9    ),
		.INIT_A    (INIT_A    ),
		.INIT_B    (INIT_B    ),
		.INIT_C    (INIT_C    ),
		.INIT_D    (INIT_D    ),
		.INIT_E    (INIT_E    ),
		.INIT_F    (INIT_F    )
	) RAM (
		.RDATA(RDATA),
		.RCLK (~RCLKN),
		.RCLKE(RCLKE),
		.RE   (RE   ),
		.RADDR(RADDR),
		.WCLK (~WCLKN),
		.WCLKE(WCLKE),
		.WE   (WE   ),
		.WADDR(WADDR),
		.MASK (MASK ),
		.WDATA(WDATA)
	);
endmodule
module nervsoc (
	input clock,
	input reset,
	output reg [31:0] leds
);
	reg [31:0] imem [0:1023];
	reg [31:0] dmem [0:1023];

	wire stall = 0;
	wire trap;

	wire [31:0] imem_addr;
	reg  [31:0] imem_data;

	wire        dmem_valid;
	wire [31:0] dmem_addr;
	wire [3:0]  dmem_wstrb;
	wire [31:0] dmem_wdata;
	reg  [31:0] dmem_rdata;

	initial begin
		$readmemh("firmware.hex", imem);
	end

	always @(posedge clock)
		imem_data <= imem[imem_addr[31:2]];

	always @(posedge clock) begin
		if (dmem_valid) begin
			if (dmem_addr == 32'h 0100_0000) begin
				if (dmem_wstrb[0]) leds[ 7: 0] <= dmem_wdata[ 7: 0];
				if (dmem_wstrb[1]) leds[15: 8] <= dmem_wdata[15: 8];
				if (dmem_wstrb[2]) leds[23:16] <= dmem_wdata[23:16];
				if (dmem_wstrb[3]) leds[31:24] <= dmem_wdata[31:24];
			end else begin
				if (dmem_wstrb[0]) dmem[dmem_addr[31:2]][ 7: 0] <= dmem_wdata[ 7: 0];
				if (dmem_wstrb[1]) dmem[dmem_addr[31:2]][15: 8] <= dmem_wdata[15: 8];
				if (dmem_wstrb[2]) dmem[dmem_addr[31:2]][23:16] <= dmem_wdata[23:16];
				if (dmem_wstrb[3]) dmem[dmem_addr[31:2]][31:24] <= dmem_wdata[31:24];
			end
			dmem_rdata <= dmem[dmem_addr[31:2]];
		end
	end

	nerv cpu (
		.clock     (clock     ),
		.reset     (reset     ),
		.stall     (stall     ),
		.trap      (trap      ),

		.imem_addr (imem_addr ),
		.imem_data (imem_data ),

		.dmem_valid(dmem_valid),
		.dmem_addr (dmem_addr ),
		.dmem_wstrb(dmem_wstrb),
		.dmem_wdata(dmem_wdata),
		.dmem_rdata(dmem_rdata)
	);
endmodule
module testbench;

localparam MEM_ADDR_WIDTH = 16;
localparam TIMEOUT = (1<<10);

reg clock;
reg reset = 1'b1;
reg stall = 1'b0;
wire trap;

wire [31:0] imem_addr;
reg  [31:0] imem_data;

wire        dmem_valid;
wire [31:0] dmem_addr;
wire [ 3:0] dmem_wstrb;
wire [31:0] dmem_wdata;
reg  [31:0] dmem_rdata;

reg  [31:0] irq = 'b0;

always #5 clock = clock === 1'b0;
always @(posedge clock) reset <= 0;

reg [7:0] mem [0:(1<<MEM_ADDR_WIDTH)-1];

wire wr_in_mem_range = (dmem_addr[31:2] < (1<<MEM_ADDR_WIDTH));
wire wr_in_output = (dmem_addr == 32'h 02000000);

reg [31:0] out;
reg out_valid;
always @(posedge clock) begin
	if (out_valid) begin
		$write("%c", out[7:0]);
`ifndef VERILATOR
		$fflush();
`endif
	end
end

`ifdef STALL
always @(posedge clock) begin
	stall <= $random;
end
`endif

always @(posedge clock) begin
	if (imem_addr >= (1<<MEM_ADDR_WIDTH)) begin
		$display("Memory access out of range: imem_addr = 0x%08x", imem_addr);
	end
	if (dmem_valid && !(wr_in_mem_range || wr_in_output)) begin
		$display("Memory access out of range: dmem_addr = 0x%08x", dmem_addr);
	end
end

integer i;
always @(posedge clock) begin
	out <= 32'h 0;
	out_valid <= 1'b0;
	if (!stall && !reset) begin
		imem_data <= {
			mem[{imem_addr[MEM_ADDR_WIDTH-1:2], 2'b11}],
			mem[{imem_addr[MEM_ADDR_WIDTH-1:2], 2'b10}],
			mem[{imem_addr[MEM_ADDR_WIDTH-1:2], 2'b01}],
			mem[{imem_addr[MEM_ADDR_WIDTH-1:2], 2'b00}]
		};

		if (dmem_valid) begin
			dmem_rdata <= {
				mem[{dmem_addr[MEM_ADDR_WIDTH-1:2], 2'b11}],
				mem[{dmem_addr[MEM_ADDR_WIDTH-1:2], 2'b10}],
				mem[{dmem_addr[MEM_ADDR_WIDTH-1:2], 2'b01}],
				mem[{dmem_addr[MEM_ADDR_WIDTH-1:2], 2'b00}]
			};
			for (i=0;i<4;i=i+1) begin
				if (dmem_wstrb[i]) begin
					if (wr_in_mem_range) begin
						mem[{dmem_addr[MEM_ADDR_WIDTH-1:2], i[1:0]}] <= dmem_wdata[(i*8)+: 8];
					end
					if (wr_in_output) begin
						out[(i*8)+: 8] <= dmem_wdata[(i*8)+: 8];
						out_valid <= 1'b1;
					end
					dmem_rdata <= 'hx;
				end
			end
		end else begin
			dmem_rdata <= 32'h XXXX_XXXX;
		end
	end
end

initial begin
	$readmemh("firmware.hex", mem);
	if ($test$plusargs("vcd")) begin
		$dumpfile("testbench.vcd");
		$dumpvars(0, testbench);
	end
end

nerv dut (
	.clock(clock),
	.reset(reset),
	.stall(stall),
	.trap(trap),

	.imem_addr(imem_addr),
	.imem_data(stall ? 32'bx : imem_data),

	.dmem_valid(dmem_valid),
	.dmem_addr(dmem_addr),
	.dmem_wstrb(dmem_wstrb),
	.dmem_wdata(dmem_wdata),
	.dmem_rdata(stall ? 32'bx : dmem_rdata),

`ifdef NERV_FAULT
	.imem_fault(1'b0),
	.dmem_fault(1'b0),
`endif

	.irq(irq)
);

reg [31:0] cycles = 0;

always @(posedge clock) begin
	cycles <= cycles + 32'h1;
	if (trap || (cycles >= TIMEOUT)) begin
		$display("Simulated %0d cycles", cycles);
		$finish;
	end
end



endmodule
module testbench;

localparam TIMEOUT = (1<<10);
reg clock;

wire LEDR_N, LEDG_N, LED1, LED2, LED3, LED4, LED5;

always #5 clock = clock === 1'b0;

top dut (
	.CLK(clock),
	.LEDR_N(LEDR_N),
	.LEDG_N(LEDG_N),
	.LED1(LED1),
	.LED2(LED2),
	.LED3(LED3),
	.LED4(LED4),
	.LED5(LED5)
);

initial begin
	if ($test$plusargs("vcd")) begin
		$dumpfile("testbench.vcd");
		$dumpvars(0, testbench);
	end
end

reg [31:0] cycles = 0;

always @(posedge clock) begin
	cycles <= cycles + 32'h1;
	if (cycles >= TIMEOUT) begin
		$display("Simulated %0d cycles", cycles);
		$finish;
	end
end

endmodule
module aliasv ( .PLUS(w), .MINUS(w) );

   inout   w;
   wire    w;

 endmodule
module aliasv_16 ( .PLUS(w), .MINUS(w) );

   inout [15:0]  w;
   wire  [15:0]  w;

 endmodule
module  c3lib_sync3_reset_ulvt_gate( 

  clk, 
  rst_n, 
  data_in,
  data_out

  ); 

input	clk; 
input	rst_n; 
input	data_in;
output	data_out;

//  c3lib_sync_metastable_behav_gate #(
//
//    .RESET_VAL	( 0 ),
//    .SYNC_STAGES( 3 )
//
//  ) u_c3lib_sync2_reset_lvt_gate ( 
//
//    .clk	( clk      ),
//    .rst_n	( rst_n    ),
//    .data_in	( data_in  ),
//    .data_out	( data_out )
//
//  );
data_sync_for_aib # (
    .ActiveLow(1),
    .ResetVal(1'b0),
    .SyncRegWidth(3)
) u_c3lib_sync2_reset_lvt_gate (
    .clk    ( clk      ),
    .rst_in (rst_n ),
    .data_in(data_in),
    .data_out   ( data_out )
);

endmodule
module c3lib_sync2_set_lvt_gate( 

  clk, 
  rst_n, 
  data_in,
  data_out

  ); 

input		clk; 
input		rst_n; 
input		data_in;
output		data_out;

//  c3lib_sync_metastable_behav_gate #(
//
//    .RESET_VAL	( 1 ),
//    .SYNC_STAGES( 2 )
//
//  ) u_c3lib_sync2_reset_lvt_gate ( 
//
//    .clk	( clk      ),
//    .rst_n	( rst_n    ),
//    .data_in	( data_in  ),
//    .data_out	( data_out )
//
//  );
  data_sync_for_aib # (
      .ActiveLow    (1),
      .ResetVal     (1'b1),
      .SyncRegWidth (2)
  ) u_c3lib_sync2_reset_ulvt_gate (
      .clk          ( clk      ),
      .rst_in       ( rst_n ),
      .data_in      (data_in),
      .data_out     ( data_out )
  );


endmodule
module c3lib_sync2_set_ulvt_gate( 

  clk, 
  rst_n, 
  data_in,
  data_out

  ); 

input		clk; 
input		rst_n; 
input		data_in;
output		data_out;

//  c3lib_sync_metastable_behav_gate #(
//
//    .RESET_VAL	( 1 ),
//    .SYNC_STAGES( 2 )
//
//  ) u_c3lib_sync2_reset_lvt_gate ( 
//
//    .clk	( clk      ),
//    .rst_n	( rst_n    ),
//    .data_in	( data_in  ),
//    .data_out	( data_out )
//
//  );

  data_sync_for_aib # (
      .ActiveLow(1),
      .ResetVal(1'b1),
      .SyncRegWidth(2)
  ) u_c3lib_sync2_reset_lvt_gate (
      .clk    ( clk      ),
      .rst_in ( rst_n ),
      .data_in(data_in),
      .data_out   ( data_out )
  );

endmodule
module c3lib_sync2_reset_lvt_gate( 

  clk, 
  rst_n, 
  data_in,
  data_out

  ); 

input		clk; 
input		rst_n; 
input		data_in;
output		data_out;
// AYAR RESET SYNC VERSION WITH 2 deep synchronizer to mimic the behavioral model below Chandru Ramamurthy!!
//  c3lib_sync_metastable_behav_gate #(
//
//    .RESET_VAL	( 0 ),
//    .SYNC_STAGES( 2 )
//
//  ) u_c3lib_sync2_reset_lvt_gate ( 
//
//    .clk	( clk      ),
//    .rst_n	( rst_n    ),
//    .data_in	( data_in  ),
//    .data_out	( data_out )
//
//  );

data_sync_for_aib # ( 
    .ActiveLow(1),
    .ResetVal(1'b0),
    .SyncRegWidth(2)
) u_c3lib_sync2_reset_lvt_gate ( 
    .clk    ( clk      ),
    .rst_in (rst_n ),
    .data_in(data_in),
    .data_out   ( data_out )
);


endmodule
module c3lib_sync2_reset_ulvt_gate( 

  clk, 
  rst_n, 
  data_in,
  data_out

  ); 

input		clk; 
input		rst_n; 
input		data_in;
output		data_out;
// AYAR RESET SYNC VERSION WITH 2 deep synchronizer to mimic the behavioral model below Chandru Ramamurthy!!
//  c3lib_sync_metastable_behav_gate #(
//
//    .RESET_VAL	( 0 ),
//    .SYNC_STAGES( 2 )
//
//  ) u_c3lib_sync2_reset_lvt_gate ( 
//
//    .clk	( clk      ),
//    .rst_n	( rst_n    ),
//    .data_in	( data_in  ),
//    .data_out	( data_out )
//
//);
  data_sync_for_aib # (
      .ActiveLow(1),
      .ResetVal(1'b0),
      .SyncRegWidth(2)
  ) u_c3lib_sync2_reset_ulvt_gate (
      .clk    ( clk      ),
      .rst_in ( rst_n ),
      .data_in(data_in),
      .data_out   ( data_out )
  );

endmodule
module  c3lib_sync3_set_ulvt_gate ( 

  clk, 
  rst_n, 
  data_in,
  data_out

  ); 

input	clk; 
input	rst_n; 
input 	data_in;
output	data_out;

//  c3lib_sync_metastable_behav_gate #(
//
//    .RESET_VAL	( 1 ),
//    .SYNC_STAGES( 3 )
//
//  ) u_c3lib_sync2_reset_lvt_gate ( 
//
//    .clk	( clk      ),
//    .rst_n	( rst_n    ),
//    .data_in	( data_in  ),
//    .data_out	( data_out )
data_sync_for_aib # (
    .ActiveLow(1),
    .ResetVal(1'b1),
    .SyncRegWidth(3)
) u_c3lib_sync2_reset_lvt_gate (
    .clk    ( clk      ),
    .rst_in (rst_n ),
    .data_in(data_in),
    .data_out   ( data_out )
);

endmodule
module c3lib_ckg_lvt_8x(

  tst_en,
  clk_en,
  clk,
  gated_clk

);

    input wire tst_en;
    input wire clk_en;
    input wire clk;
    output wire gated_clk;

`ifdef BEHAVIORAL
    var logic latch_d;
    var logic latch_q;

    // Formulate control signal
    assign latch_d = clk_en | tst_en;

    // Latch control signal
    always_latch if (~clk) latch_q <= latch_d;

    // Actual clk gating gate
    assign gated_clk = clk & latch_q;
`else
    b15cilb01ah1n08x5 icg_cell (.clkout(gated_clk), .en(clk_en), .te(tst_en), .clk(clk));
`endif


endmodule
module c3lib_ckinv_svt_8x( 

  in,
  out

  ); 

input		in;
output		out;

`ifdef BEHAVIORAL
  assign out = ~in;
`else
  clock_inv u_clock_inv (.out(out), .in(in));
`endif

endmodule
module aibio_clkdist_inv1_cbb
(
	//------Supply pins------//
	input vddcq,
	input vss,
	//------Input pins------//
	input clkp,
	input clkn,
	//------Output pins------//
	output clkp_b,
	output clkn_b
);

wire clkp_b_1;
wire clkp_b_2;
wire clkn_b_1;
wire clkn_b_2;

`ifdef POST_WORST
	localparam delay_1 = 100;
	localparam delay_2 = 49.55;
`else
	localparam delay_1 = 0.0;
	localparam delay_2 = 0.0;
`endif

assign #(delay_1) clkp_b_1 = ~clkp;
assign #(delay_2) clkp_b_2 = ~clkp_b_1;
assign #(delay_2) clkp_b = ~clkp_b_2;

assign #(delay_1) clkn_b_1 = ~clkn;
assign #(delay_2) clkn_b_2 = ~clkn_b_1;
assign #(delay_2) clkn_b = ~clkn_b_2;
/*
assign #(delay_clkp_b)clkp_b = ~clkp;
assign #(delay_clkn_b)clkn_b = ~clkn;
*/

endmodule
module aibio_rxclk_cbb
(
	//------Supply pins------//
	input vddcq,
	input vss,
	//------Input pins------//
	input [4:0] dcc_p_pdsel,
	input [4:0] dcc_p_pusel,
	input [4:0] dcc_n_pdsel,
	input [4:0] dcc_n_pusel,
	input rxclkp,
	input rxclkn,
	input rxclk_en,
	input rxclk_localbias_en,
	input ipbias,
	input [2:0] ibias_ctrl,
	input gen1mode_en,
	//------Output pins------//
	output rxclkp_out,
	output rxclkn_out,
	//------Spare pins------//
	input [3:0] i_rxclk_spare,
	output [3:0] o_rxclk_spare
);

wire rxclkp_out_1;
wire rxclkp_out_2;
wire rxclkp_out_3;
wire rxclkn_out_1;
wire rxclkn_out_2;
wire rxclkn_out_3;

`ifdef POST_WORST
	localparam delay_rxclkp_out_1 = 150;
	localparam delay_rxclkp_out_2 = 5;
	localparam delay_rxclkn_out_1 = 150;
	localparam delay_rxclkn_out_2 = 3;
`else
	localparam delay_rxclkp_out_1 = 0.0;
	localparam delay_rxclkp_out_2 = 0.0;
	localparam delay_rxclkn_out_1 = 0.0;
	localparam delay_rxclkn_out_2 = 0.0;
`endif

assign #(delay_rxclkp_out_1)rxclkp_out_1 = rxclk_en ? rxclkp : 1'b0;
assign #(delay_rxclkp_out_1)rxclkp_out_2 = rxclk_en ? rxclkp_out_1 : 1'b0;
assign #(delay_rxclkp_out_1)rxclkp_out_3 = rxclk_en ? rxclkp_out_2 : 1'b0;
assign #(delay_rxclkp_out_2)rxclkp_out = rxclk_en ? rxclkp_out_3 : 1'b0;
assign #(delay_rxclkn_out_1)rxclkn_out_1 = rxclk_en ? rxclkn : 1'b0;
assign #(delay_rxclkn_out_1)rxclkn_out_2 = rxclk_en ? rxclkn_out_1 : 1'b0;
assign #(delay_rxclkn_out_1)rxclkn_out_3 = rxclk_en ? rxclkn_out_2 : 1'b0;
assign #(delay_rxclkn_out_2)rxclkn_out = rxclk_en ? rxclkn_out_3 : 1'b0;

endmodule
module aibio_clkdist_inv2_cbb
(
	//------Supply pins------//
	input vddcq,
  	input vss,
	//------Input pins------//
  	input clkp,
  	input clkn,
	//------Output pins------//
  	output clkp_b,
  	output clkn_b
);

wire clkp_b_1;
wire clkp_b_2;
wire clkn_b_1;
wire clkn_b_2;

`ifdef POST_WORST
	localparam delay_1 = 100;
	localparam delay_2 = 16.5;
`else
	localparam delay_1 = 0.0;
	localparam delay_2 = 0.0;
`endif

assign #(delay_1) clkp_b_1 = ~clkp;
assign #(delay_2) clkp_b_2 = ~clkp_b_1;
assign #(delay_2) clkp_b = ~clkp_b_2;

assign #(delay_1) clkn_b_1 = ~clkn;
assign #(delay_2) clkn_b_2 = ~clkn_b_1;
assign #(delay_2) clkn_b = ~clkn_b_2;

/*
assign #(delay_clkp_b)clkp_b = ~clkp;
assign #(delay_clkn_b)clkn_b = ~clkn;
*/

endmodule
module aibio_outclk_select
		(
		//--------Supply pins----------//
		input vddcq,
		input vss,
		//--------Input pins-----------//
		input [15:0]i_clkphb,
		input [3:0]i_adapter_code,
		input [3:0]i_soc_code,
		//--------Output pins---------//
		output o_clk_adapter,
		output o_clk_soc
		);



assign o_clk_adapter = ~ i_clkphb[i_adapter_code];
assign o_clk_soc = ~ i_clkphb[i_soc_code];

endmodule
module aibio_txdll_cbb
(
	//------Supply pins------//
	input vddcq,
	input vddc,
	input vss,
	//------Input pins------//
	input ck_in,
	input ck_loopback,
	input ck_sys,
	input ck_jtag,
	input [1:0] inp_clksel,
	input dll_en,
	input dll_reset,
	input [3:0] dll_biasctrl,
	input [4:0] dll_capctrl,
	input [3:0] dll_cksoc_code,
	input [3:0] dll_ckadapter_code,
	input [3:0] dll_even_phase1_sel,
	input [3:0] dll_odd_phase1_sel,
	input [3:0] dll_even_phase2_sel,
	input [3:0] dll_odd_phase2_sel,
	input [3:0] dll_lockthresh,
	input [1:0] dll_lockctrl,
	input pwrgood_in,
	input dll_dfx_en,
	input [4:0] dll_digview_sel,
	input [4:0] dll_anaview_sel,
	//------Output pins------//
	output dll_lock,
	output clk_odd,
	output clk_even,
	output clk_soc,
	output clk_adapter,
	output pulseclk_odd,
	output pulseclk_even,
	output inbias,
	output ipbias,
	output [1:0] dll_digviewout,
	output dll_anaviewout,
	//------Spare pins------//
	input [7:0] i_dll_spare,
	output [7:0] o_dll_spare
);

wire clkp,clkn;
wire up,dn,upb,dnb;
wire [15:0]clkphb;

wire dll_enb;

assign dll_enb= ~dll_en;

aibio_inpclk_select_txdll inpclk_select
		(
 		.vddcq(vddcq),
		.vss(vss),
		.i_clk_in(ck_in),
		.i_clk_loopback(ck_loopback),
		.i_clk_sys(ck_sys),
		.i_clk_jtag(ck_jtag),
		.i_clksel(inp_clksel),
		.o_clkp(clkp),
		.o_clkn(clkn)
		);

aibio_dll_top dll_top
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkp(clkp),
		.i_clkn(clkn),
		.i_clkp_cdr(),
		.i_clkn_cdr(),
		.i_dll_biasctrl(dll_biasctrl),
		.i_dll_capctrl(dll_capctrl),
		.i_dll_en(dll_en),
		.i_dll_enb(dll_enb),
		.o_up(up),
		.o_dn(dn),
		.o_upb(upb),
		.o_dnb(dnb),
		.o_dll_clkphb(clkphb),
		.o_piclk_180(),
		.o_piclk_90(),
		.o_cdr_clk(),
		.o_pbias(),
		.o_nbias()
		);

aibio_lock_detector lock_detector
		(
		.vddcq(vddcq),
  		.vss(vss),
		.i_clkin(ck_sys),
		.i_en(dll_en),
		.i_up(up),
		.i_dn(dn),
		.i_upb(upb),
		.i_dnb(dnb),
		.i_lockthresh(dll_lockthresh[1:0]),
		.i_lockctrl(dll_lockctrl),
		.lock(dll_lock)
		);

aibio_pulsegen_top pulsegen
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkph(clkphb),
		.i_dll_even_phase1_sel(dll_even_phase1_sel),
		.i_dll_odd_phase1_sel(dll_odd_phase1_sel),
		.i_dll_even_phase2_sel(dll_even_phase2_sel),
		.i_dll_odd_phase2_sel(dll_odd_phase2_sel),
		.o_clk_even(clk_even),
		.o_clk_odd(clk_odd),
		.o_pulseclk_even(pulseclk_even),
		.o_pulseclk_odd(pulseclk_odd)
		);

aibio_outclk_select outclk_select
		(
		.vddcq(vddcq),
		.vss(vss),
		.i_clkphb(clkphb),
		.i_adapter_code(dll_ckadapter_code),
		.i_soc_code(dll_cksoc_code),
		.o_clk_adapter(clk_adapter),
		.o_clk_soc(clk_soc)
		);


endmodule
module aibio_inpclk_select_txdll
		(
		//--------Supply pins----------//
		input vddcq,
		input vss,
		//--------Input pins-----------//
		input i_clk_in,
		input i_clk_loopback,
		input i_clk_sys,
		input i_clk_jtag,
		input [1:0] i_clksel,
		//--------Output pins-----------//
		output o_clkp,
		output o_clkn
		);

wire i_clk_inp;
wire i_clk_inn;
wire i_clk_loopbackp;
wire i_clk_loopbackn;
wire i_clk_sysp;
wire i_clk_sysn;
wire i_clk_jtagp;
wire i_clk_jtagn;

assign i_clk_loopbackp = i_clk_loopback;
assign i_clk_loopbackn = ~i_clk_loopback;

assign i_clk_sysp = i_clk_sys;
assign i_clk_sysn = ~i_clk_sys;

assign i_clk_inp = i_clk_in;
assign i_clk_inn = ~i_clk_in;

assign i_clk_jtagp = i_clk_jtag;
assign i_clk_jtagn = ~i_clk_jtag;


assign o_clkp = (i_clksel == 2'b00) ? i_clk_inp :
					 (i_clksel == 2'b01) ? i_clk_loopbackp :
					 (i_clksel == 2'b10) ? i_clk_sysp :
					 (i_clksel == 2'b11) ? i_clk_jtagp :
					 1'b0;

assign o_clkn = (i_clksel == 2'b00) ? i_clk_inn :
					 (i_clksel == 2'b01) ? i_clk_loopbackn :
					 (i_clksel == 2'b10) ? i_clk_sysn :
					 (i_clksel == 2'b11) ? i_clk_jtagn :
					 1'b0;

endmodule
module aibio_pulsegen_top
		(
		//---------Supply pins----------//
		input vddcq,
		input vss,
		//---------Input pins----------//
		input [15:0] i_clkph,
		input [3:0] i_dll_even_phase1_sel,
		input [3:0] i_dll_odd_phase1_sel,
		input [3:0] i_dll_even_phase2_sel,
		input [3:0] i_dll_odd_phase2_sel,
		//--------Output pins-----------//
		output o_clk_even,
		output o_clk_odd,
		output o_pulseclk_even,
		output o_pulseclk_odd
		);

wire [3:0]dll_even_phase2_sel_int;
wire [3:0]dll_odd_phase2_sel_int;

wire dll_even_phase2_selb_3;
wire dll_odd_phase2_selb_3;

assign dll_even_phase2_selb_3 = ~i_dll_even_phase2_sel[3];
assign dll_odd_phase2_selb_3 = ~i_dll_odd_phase2_sel[3];
assign dll_even_phase2_sel_int = {dll_even_phase2_selb_3,i_dll_even_phase2_sel[2:0]};
assign dll_odd_phase2_sel_int = {dll_odd_phase2_selb_3,i_dll_odd_phase2_sel[2:0]};

assign o_clk_even = ~i_clkph[i_dll_even_phase1_sel];
assign o_clk_odd = ~i_clkph[i_dll_odd_phase1_sel];
assign o_pulseclk_even = o_clk_even && (i_clkph[dll_even_phase2_sel_int]);
assign o_pulseclk_odd = o_clk_odd && (i_clkph[dll_odd_phase2_sel_int]);

endmodule
module aibio_vref_cbb
(
	//------Supply pins------//
	input vddc,
	input vddtx,
	inout vss,
	//------Input pins------//
	input vref_en,
	input calvref_en,
	input [6:0] vref_bin_0,
	input [6:0] vref_bin_1,
	input [6:0] vref_bin_2,
	input [6:0] vref_bin_3,
	input [4:0] calvref_bin,
	input gen1mode_en,
	input pwrgood_in,
	//------Output pins------//
	output [3:0] vref,
	output calvref,
	//------Spare pins------//
	input [3:0] i_vref_spare,
	output [3:0] o_vref_spare
);

endmodule
module en_logic_xxpad
		(
		input data,
		input pwrgoodtx,
		input pwrgood,
		input rst_strap,
		input wk_pu_en,
		input wk_pd_en,
		input compen_n,
		input compen_p,
		input tx_en,
		input sdr_mode_en,
		input tx_async_en,
		input gen1_en,
		output reg pu_en_gen1,
		output reg pd_en_gen1,
		output reg pu_en_gen2,
		output reg pd_en_gen2,
		output reg wkpd_en,
		output reg wkpu_en
		);

wire pg;
wire compen;
wire wk_en;

assign pg = (pwrgoodtx && pwrgood);
assign compen = (compen_p ^ compen_n);
assign wk_en = (wk_pu_en ^ wk_pd_en);

always @(rst_strap,pg,wk_en,compen,tx_en,sdr_mode_en,tx_async_en,gen1_en,data)
begin
	if(rst_strap) 								//reset
	begin
		pu_en_gen1 = 1'b0;
		pd_en_gen1 = 1'b0;
		pu_en_gen2 = 1'b0;
		pd_en_gen2 = 1'b1;
		wkpd_en = 1'b0;
		wkpu_en = 1'b0;
	end
	else if(!pg) 								//pwrgoodtx and pwrgood invalid
	begin
		pu_en_gen1 = 1'b0;
		pd_en_gen1 = 1'b0;
		pu_en_gen2 = 1'b0;
		pd_en_gen2 = 1'b0;
		wkpd_en = 1'b0;
		wkpu_en = 1'b0;
	end
	else if(wk_en)
	begin
		if(wk_pu_en) 							//Weak PULL-UP
		begin
			pu_en_gen1 = 1'b0;
			pd_en_gen1 = 1'b0;
			pu_en_gen2 = 1'b0;
			pd_en_gen2 = 1'b0;
			wkpd_en = 1'b0;
			wkpu_en = 1'b1;
		end
		else if(wk_pd_en) 					//Weak PULL-DOWN
		begin
			pu_en_gen1 = 1'b0;
			pd_en_gen1 = 1'b0;
			pu_en_gen2 = 1'b0;
			pd_en_gen2 = 1'b0;
			wkpd_en = 1'b1;
			wkpu_en = 1'b0;
		end
	end
	else if(compen)
	begin
		if(compen_n) 							//rcomp_n
		begin
			pu_en_gen1 = 1'b0;
			pd_en_gen1 = 1'b0;
			pu_en_gen2 = 1'b1;
			pd_en_gen2 = 1'b1;
			wkpd_en = 1'b0;
			wkpu_en = 1'b0;
		end
		else if(compen_p) 					//rcomp_p
		begin
			pu_en_gen1 = 1'b1;
			pd_en_gen1 = 1'b1;
			pu_en_gen2 = 1'b0;
			pd_en_gen2 = 1'b0;
			wkpd_en = 1'b0;
			wkpu_en = 1'b0;
		end
	end
	else if(tx_async_en) 					//Async mode(Assumption ---> gen1_en is high): data here is async data
	begin
		pu_en_gen1 = (data == 1'b1) ? 1'b1 : 1'b0;
		pd_en_gen1 = (data == 1'b0) ? 1'b1 : 1'b0;
		pu_en_gen2 = 1'b0;
		pd_en_gen2 = 1'b0;
		wkpd_en = 1'b0;
		wkpu_en = 1'b0;
	end
	else if(!tx_en) 							//No Mode: Both tx_async_en & tx_en is low
	begin
		pu_en_gen1 = 1'b0;
		pd_en_gen1 = 1'b0;
		pu_en_gen2 = 1'b0;
		pd_en_gen2 = 1'b0;
		wkpd_en = 1'b0;
		wkpu_en = 1'b0;
	end
	else if(tx_en)								//tx_en : high
	begin
		if(sdr_mode_en)						//SDR Mode(Assumption ---> gen1_en is high) : Here data is even data
		begin
			pu_en_gen1 = (data == 1'b1) ? 1'b1 : 1'b0;
			pd_en_gen1 = (data == 1'b0) ? 1'b1 : 1'b0;
			pu_en_gen2 = 1'b0;
			pd_en_gen2 = 1'b0;
			wkpd_en = 1'b0;
			wkpu_en = 1'b0;
		end
		else
		begin
			if(gen1_en) 						//GEN1 Mode : Here data is serialised data
			begin
				pu_en_gen1 = (data == 1'b1) ? 1'b1 : 1'b0;
				pd_en_gen1 = (data == 1'b0) ? 1'b1 : 1'b0;
				pu_en_gen2 = 1'b0;
				pd_en_gen2 = 1'b0;
				wkpd_en = 1'b0;
				wkpu_en = 1'b0;
			end
			else 									//GEN2 Mode : Here data is serialised data
			begin
				pu_en_gen1 = 1'b0;
				pd_en_gen1 = 1'b0;
				pu_en_gen2 = (data == 1'b1) ? 1'b1 : 1'b0;
				pd_en_gen2 = (data == 1'b0) ? 1'b1 : 1'b0;
				wkpd_en = 1'b0;
				wkpu_en = 1'b0;
			end
		end
	end
end

endmodule
module pad_out_logic
		(
		input rst,
		input pu_gen1,
		input pd_gen1,
		input pu_gen2,
		input pd_gen2,
		input wkpu,
		input wkpd,
		output reg data_out
		);

always @(rst,wkpu,wkpd,pu_gen1,pd_gen1,pu_gen2,pd_gen2)
begin
	if(rst)
	begin
		data_out = 1'b0;
	end
	else if(wkpu)
	begin
		data_out = 1'b1;
	end
	else if(wkpd)
	begin
		data_out = 1'b0;
	end
	else if(pu_gen1 && pd_gen1)
	begin
		data_out = 1'bx;
	end
	else if(pu_gen2 && pd_gen2)
	begin
		data_out = 1'bx;
	end
	else if(pu_gen1 ^ pd_gen1)
	begin
		data_out = pu_gen1;
	end
	else if(pu_gen2 ^ pd_gen2)
	begin
		data_out = pu_gen2;
	end
	else
	begin
		data_out = 1'bz;
	end
end

endmodule
module aibio_pvtmon_3to8dec(
				//-----Supply Pins---//
				input logic vdd,
				input logic vss,
				
				//-----Input Pins---//
				input logic [2:0]sel,
				
				//----Output pins----//
				output logic [7:0]out
				);
always @(sel)
	begin
		case(sel)
		3'b000 : out=8'b0000_0001;
		3'b001 : out=8'b0000_0010;
		3'b010 : out=8'b0000_0100;
		3'b011 : out=8'b0000_1000;
		3'b100 : out=8'b0001_0000;
		3'b101 : out=8'b0010_0000;
		3'b110 : out=8'b0100_0000;
		3'b111 : out=8'b1000_0000;
		default : out = 8'b0000_0000;
		endcase
	end
				
endmodule
module mux2x1 (
		//-----Supply Pins---//
		input logic vdd,
		input logic vss,
		
		//-----Input Pins---//
		input logic [1:0]in,
		input logic s,
		
		//----Output pins----//
		output logic out
		);
		

always @(in or s)
begin

	if(s) 
	out= in[1];
	else
	out=in[0];

end

endmodule
module DFF(
		//-----Supply Pins---//
		input logic vdd,
		input logic vss,
		
		//-----Input Pins---//
		input logic clk,
		input logic rb,
		input logic d,
		
		//----Output pins----//
		output logic o
		);
initial o <= 0;		
always @(posedge clk or negedge rb )
begin
	if(rb == 1'b0)
	begin
		o = 'd0;
	end
	else
	begin
		o = d;
	end

end

endmodule
module aibio_decoder3x8
		(
		//---------Supply pins---------//
		input vddcq,
		input vss,
		//--------Input pins----------//
		input [2:0] i,
		//--------Output pins---------//
		output reg [7:0] o
		);

always @(i)
	case(i)
   	3'b000 : o = 8'b0000_0001;
      3'b001 : o = 8'b0000_0010;
		3'b010 : o = 8'b0000_0100;
      3'b011 : o = 8'b0000_1000;
   	3'b100 : o = 8'b0001_0000;
      3'b101 : o = 8'b0010_0000;
		3'b110 : o = 8'b0100_0000;
      3'b111 : o = 8'b1000_0000;
      default : o = 8'b0000_0000;
	endcase

endmodule