dakies/OSS_Verilog huggingface dataset:
module word_mixcolum(in,outx,outy);
input [31:0] in;
output [31:0] outx;
output [31:0] outy;

reg [31:0] outx;
reg [31:0] outy;

reg [7:0] a;
reg [7:0] b;
reg [7:0] c;
reg [7:0] d;
wire [7:0] x1;

wire [7:0] x2;

wire [7:0] x3;

wire [7:0] x4;

wire [7:0] y1;

wire [7:0] y2;

wire [7:0] y3;

wire [7:0] y4;


byte_mixcolum bm1 (.a(a), .b(b), .c(c), .d(d), .outx(x1), .outy(y1));
byte_mixcolum bm2 (.a(b), .b(c), .c(d), .d(a), .outx(x2), .outy(y2));
byte_mixcolum bm3 (.a(c), .b(d), .c(a), .d(b), .outx(x3), .outy(y3));
byte_mixcolum bm4 (.a(d), .b(a), .c(b), .d(c), .outx(x4), .outy(y4));


		reg[31:0] in_var;
		reg[31:0] outx_var,outy_var;
//split:
always @(  in)

begin


		
		in_var=in;
		a = (in_var[31:24]);
		b = (in_var[23:16]);
	c = (in_var[15:8]);
		d = (in_var[7:0]);
	
end
//mix:
always @(  x1 or   x2 or   x3 or   x4 or   y1 or   y2 or   y3 or   y4)

begin

		
		
		outx_var[31:24]=x1;
		outx_var[23:16]=x2;
		outx_var[15:8]=x3;
		outx_var[7:0]=x4;
		outy_var[31:24]=y1;
		outy_var[23:16]=y2;
		outy_var[15:8]=y3;
		outy_var[7:0]=y4;
		
		outx = (outx_var);
		outy = (outy_var);
	
end

endmodule
module s4(stage1_input,stage1_output);
input [5:0] stage1_input;
output [3:0] stage1_output;

reg [3:0] stage1_output;



always @(  stage1_input)

begin

   case(stage1_input)

        0: stage1_output = (7); 
        1: stage1_output = (13); 
        2: stage1_output = (13); 
        3: stage1_output = (8); 
        4: stage1_output = (14); 
        5: stage1_output = (11); 
        6: stage1_output = (3); 
        7: stage1_output = (5); 
        8: stage1_output = (0); 
        9: stage1_output = (6); 
        10: stage1_output = (6); 
        11: stage1_output = (15); 
        12: stage1_output = (9); 
        13: stage1_output = (0); 
        14: stage1_output = (10); 
        15: stage1_output = (3); 
        16: stage1_output = (1); 
        17: stage1_output = (4); 
        18: stage1_output = (2); 
        19: stage1_output = (7); 
        20: stage1_output = (8); 
        21: stage1_output = (2); 
        22: stage1_output = (5); 
        23: stage1_output = (12); 
        24: stage1_output = (11); 
        25: stage1_output = (1); 
        26: stage1_output = (12); 
        27: stage1_output = (10); 
        28: stage1_output = (4); 
        29: stage1_output = (14); 
        30: stage1_output = (15); 
        31: stage1_output = (9); 
        32: stage1_output = (10); 
        33: stage1_output = (3); 
        34: stage1_output = (6); 
        35: stage1_output = (15); 
        36: stage1_output = (9); 
        37: stage1_output = (0); 
        38: stage1_output = (0); 
        39: stage1_output = (6); 
        40: stage1_output = (12); 
        41: stage1_output = (10); 
        42: stage1_output = (11); 
        43: stage1_output = (1); 
        44: stage1_output = (7); 
        45: stage1_output = (13); 
        46: stage1_output = (13); 
        47: stage1_output = (8); 
        48: stage1_output = (15); 
        49: stage1_output = (9); 
        50: stage1_output = (1); 
        51: stage1_output = (4); 
        52: stage1_output = (3); 
        53: stage1_output = (5); 
        54: stage1_output = (14); 
        55: stage1_output = (11); 
        56: stage1_output = (5); 
        57: stage1_output = (12); 
        58: stage1_output = (2); 
        59: stage1_output = (7); 
        60: stage1_output = (8); 
        61: stage1_output = (2); 
        62: stage1_output = (4); 
        63: stage1_output = (14); 

endcase

	

end

endmodule
module s6(stage1_input,stage1_output);
input [5:0] stage1_input;
output [3:0] stage1_output;

reg [3:0] stage1_output;



always @(  stage1_input)

begin

   case(stage1_input)

        0: stage1_output = (12); 
        1: stage1_output = (10); 
        2: stage1_output = (1); 
        3: stage1_output = (15); 
        4: stage1_output = (10); 
        5: stage1_output = (4); 
        6: stage1_output = (15); 
        7: stage1_output = (2); 
        8: stage1_output = (9); 
        9: stage1_output = (7); 
        10: stage1_output = (2); 
        11: stage1_output = (12); 
        12: stage1_output = (6); 
        13: stage1_output = (9); 
        14: stage1_output = (8); 
        15: stage1_output = (5); 
        16: stage1_output = (0); 
        17: stage1_output = (6); 
        18: stage1_output = (13); 
        19: stage1_output = (1); 
        20: stage1_output = (3); 
        21: stage1_output = (13); 
        22: stage1_output = (4); 
        23: stage1_output = (14); 
        24: stage1_output = (14); 
        25: stage1_output = (0); 
        26: stage1_output = (7); 
        27: stage1_output = (11); 
        28: stage1_output = (5); 
        29: stage1_output = (3); 
        30: stage1_output = (11); 
        31: stage1_output = (8); 
        32: stage1_output = (9); 
        33: stage1_output = (4); 
        34: stage1_output = (14); 
        35: stage1_output = (3); 
        36: stage1_output = (15); 
        37: stage1_output = (2); 
        38: stage1_output = (5); 
        39: stage1_output = (12); 
        40: stage1_output = (2); 
        41: stage1_output = (9); 
        42: stage1_output = (8); 
        43: stage1_output = (5); 
        44: stage1_output = (12); 
        45: stage1_output = (15); 
        46: stage1_output = (3); 
        47: stage1_output = (10); 
        48: stage1_output = (7); 
        49: stage1_output = (11); 
        50: stage1_output = (0); 
        51: stage1_output = (14); 
        52: stage1_output = (4); 
        53: stage1_output = (1); 
        54: stage1_output = (10); 
        55: stage1_output = (7); 
        56: stage1_output = (1); 
        57: stage1_output = (6); 
        58: stage1_output = (13); 
        59: stage1_output = (0); 
        60: stage1_output = (11); 
        61: stage1_output = (8); 
        62: stage1_output = (6); 
        63: stage1_output = (13); 

endcase


	

end

endmodule
module s2(stage1_input,stage1_output);
input [5:0] stage1_input;
output [3:0] stage1_output;

reg [3:0] stage1_output;



always @(  stage1_input)

begin


   case(stage1_input)
        0: stage1_output = (15); 
        1: stage1_output = (3); 
        2: stage1_output = (1); 
        3: stage1_output = (13); 
        4: stage1_output = (8); 
        5: stage1_output = (4); 
        6: stage1_output = (14); 
        7: stage1_output = (7); 
        8: stage1_output = (6); 
        9: stage1_output = (15); 
        10: stage1_output = (11); 
        11: stage1_output = (2); 
        12: stage1_output = (3); 
        13: stage1_output = (8); 
        14: stage1_output = (4); 
        15: stage1_output = (14); 
        16: stage1_output = (9); 
        17: stage1_output = (12); 
        18: stage1_output = (7); 
        19: stage1_output = (0); 
        20: stage1_output = (2); 
        21: stage1_output = (1); 
        22: stage1_output = (13); 
        23: stage1_output = (10); 
        24: stage1_output = (12); 
        25: stage1_output = (6); 
        26: stage1_output = (0); 
        27: stage1_output = (9); 
        28: stage1_output = (5); 
        29: stage1_output = (11); 
        30: stage1_output = (10); 
        31: stage1_output = (5); 
        32: stage1_output = (0); 
        33: stage1_output = (13); 
        34: stage1_output = (14); 
        35: stage1_output = (8); 
        36: stage1_output = (7); 
        37: stage1_output = (10); 
        38: stage1_output = (11); 
        39: stage1_output = (1); 
        40: stage1_output = (10); 
        41: stage1_output = (3); 
        42: stage1_output = (4); 
        43: stage1_output = (15); 
        44: stage1_output = (13); 
        45: stage1_output = (4); 
        46: stage1_output = (1); 
        47: stage1_output = (2); 
        48: stage1_output = (5); 
        49: stage1_output = (11); 
        50: stage1_output = (8); 
        51: stage1_output = (6); 
        52: stage1_output = (12); 
        53: stage1_output = (7); 
        54: stage1_output = (6); 
        55: stage1_output = (12); 
        56: stage1_output = (9); 
        57: stage1_output = (0); 
        58: stage1_output = (3); 
        59: stage1_output = (5); 
        60: stage1_output = (2); 
        61: stage1_output = (14); 
        62: stage1_output = (15); 
        63: stage1_output = (9); 
   
endcase


end

endmodule
module s7(stage1_input,stage1_output);
input [5:0] stage1_input;
output [3:0] stage1_output;

reg [3:0] stage1_output;



always @(  stage1_input)

begin

   case(stage1_input)

        0: stage1_output = (4); 
        1: stage1_output = (13); 
        2: stage1_output = (11); 
        3: stage1_output = (0); 
        4: stage1_output = (2); 
        5: stage1_output = (11); 
        6: stage1_output = (14); 
        7: stage1_output = (7); 
        8: stage1_output = (15); 
        9: stage1_output = (4); 
        10: stage1_output = (0); 
        11: stage1_output = (9); 
        12: stage1_output = (8); 
        13: stage1_output = (1); 
        14: stage1_output = (13); 
        15: stage1_output = (10); 
        16: stage1_output = (3); 
        17: stage1_output = (14); 
        18: stage1_output = (12); 
        19: stage1_output = (3); 
        20: stage1_output = (9); 
        21: stage1_output = (5); 
        22: stage1_output = (7); 
        23: stage1_output = (12); 
        24: stage1_output = (5); 
        25: stage1_output = (2); 
        26: stage1_output = (10); 
        27: stage1_output = (15); 
        28: stage1_output = (6); 
        29: stage1_output = (8); 
        30: stage1_output = (1); 
        31: stage1_output = (6); 
        32: stage1_output = (1); 
        33: stage1_output = (6); 
        34: stage1_output = (4); 
        35: stage1_output = (11); 
        36: stage1_output = (11); 
        37: stage1_output = (13); 
        38: stage1_output = (13); 
        39: stage1_output = (8); 
        40: stage1_output = (12); 
        41: stage1_output = (1); 
        42: stage1_output = (3); 
        43: stage1_output = (4); 
        44: stage1_output = (7); 
        45: stage1_output = (10); 
        46: stage1_output = (14); 
        47: stage1_output = (7); 
        48: stage1_output = (10); 
        49: stage1_output = (9); 
        50: stage1_output = (15); 
        51: stage1_output = (5); 
        52: stage1_output = (6); 
        53: stage1_output = (0); 
        54: stage1_output = (8); 
        55: stage1_output = (15); 
        56: stage1_output = (0); 
        57: stage1_output = (14); 
        58: stage1_output = (5); 
        59: stage1_output = (2); 
        60: stage1_output = (9); 
        61: stage1_output = (3); 
        62: stage1_output = (2); 
        63: stage1_output = (12); 

endcase


	

end

endmodule
module s8(stage1_input,stage1_output);
input [5:0] stage1_input;
output [3:0] stage1_output;

reg [3:0] stage1_output;



always @(stage1_input)

begin

   case(stage1_input)

        0: stage1_output = (13); 
        1: stage1_output = (1); 
        2: stage1_output = (2); 
        3: stage1_output = (15); 
        4: stage1_output = (8); 
        5: stage1_output = (13); 
        6: stage1_output = (4); 
        7: stage1_output = (8); 
        8: stage1_output = (6); 
        9: stage1_output = (10); 
        10: stage1_output = (15); 
        11: stage1_output = (3); 
        12: stage1_output = (11); 
        13: stage1_output = (7); 
        14: stage1_output = (1); 
        15: stage1_output = (4); 
        16: stage1_output = (10); 
        17: stage1_output = (12); 
        18: stage1_output = (9); 
        19: stage1_output = (5); 
        20: stage1_output = (3); 
        21: stage1_output = (6); 
        22: stage1_output = (14); 
        23: stage1_output = (11); 
        24: stage1_output = (5); 
        25: stage1_output = (0); 
        26: stage1_output = (0); 
        27: stage1_output = (14); 
        28: stage1_output = (12); 
        29: stage1_output = (9); 
        30: stage1_output = (7); 
        31: stage1_output = (2); 
        32: stage1_output = (7); 
        33: stage1_output = (2); 
        34: stage1_output = (11); 
        35: stage1_output = (1); 
        36: stage1_output = (4); 
        37: stage1_output = (14); 
        38: stage1_output = (1); 
        39: stage1_output = (7); 
        40: stage1_output = (9); 
        41: stage1_output = (4); 
        42: stage1_output = (12); 
        43: stage1_output = (10); 
        44: stage1_output = (14); 
        45: stage1_output = (8); 
        46: stage1_output = (2); 
        47: stage1_output = (13); 
        48: stage1_output = (0); 
        49: stage1_output = (15); 
        50: stage1_output = (6); 
        51: stage1_output = (12); 
        52: stage1_output = (10); 
        53: stage1_output = (9); 
        54: stage1_output = (13); 
        55: stage1_output = (0); 
        56: stage1_output = (15); 
        57: stage1_output = (3); 
        58: stage1_output = (3); 
        59: stage1_output = (5); 
        60: stage1_output = (5); 
        61: stage1_output = (6); 
        62: stage1_output = (8); 
        63: stage1_output = (11); 

endcase

	

end

endmodule
module s1(stage1_input,stage1_output);
input [5:0] stage1_input;
output [3:0] stage1_output;

reg [3:0] stage1_output;



always @(  stage1_input)

begin

	
   case(stage1_input)
	    0: stage1_output = (14); 
        1: stage1_output = (0); 
        2: stage1_output = (4); 
        3: stage1_output = (15); 
        4: stage1_output = (13); 
        5: stage1_output = (7); 
        6: stage1_output = (1); 
        7: stage1_output = (4); 
        8: stage1_output = (2); 
        9: stage1_output = (14); 
        10: stage1_output = (15); 
        11: stage1_output = (2); 
        12: stage1_output = (11); 
        13: stage1_output = (13); 
        14: stage1_output = (8); 
        15: stage1_output = (1); 
        16: stage1_output = (3); 
        17: stage1_output = (10); 
        18: stage1_output = (10); 
        19: stage1_output = (6); 
        20: stage1_output = (6); 
        21: stage1_output = (12); 
        22: stage1_output = (12); 
        23: stage1_output = (11); 
        24: stage1_output = (5); 
        25: stage1_output = (9); 
        26: stage1_output = (9); 
        27: stage1_output = (5); 
        28: stage1_output = (0); 
        29: stage1_output = (3); 
        30: stage1_output = (7); 
        31: stage1_output = (8); 
        32: stage1_output = (4); 
        33: stage1_output = (15); 
        34: stage1_output = (1); 
        35: stage1_output = (12); 
        36: stage1_output = (14); 
        37: stage1_output = (8); 
        38: stage1_output = (8); 
        39: stage1_output = (2); 
        40: stage1_output = (13); 
        41: stage1_output = (4); 
        42: stage1_output = (6); 
        43: stage1_output = (9); 
        44: stage1_output = (2); 
        45: stage1_output = (1); 
        46: stage1_output = (11); 
        47: stage1_output = (7); 
        48: stage1_output = (15); 
        49: stage1_output = (5); 
        50: stage1_output = (12); 
        51: stage1_output = (11); 
        52: stage1_output = (9); 
        53: stage1_output = (3); 
        54: stage1_output = (7); 
        55: stage1_output = (14); 
        56: stage1_output = (3); 
        57: stage1_output = (10); 
        58: stage1_output = (10); 
        59: stage1_output = (0); 
        60: stage1_output = (5); 
        61: stage1_output = (6); 
        62: stage1_output = (0); 
        63: stage1_output = (13); 
    
endcase


end

endmodule
module s3(stage1_input,stage1_output);
input [5:0] stage1_input;
output [3:0] stage1_output;

reg [3:0] stage1_output;



always @(  stage1_input)

begin

   case(stage1_input)

        0: stage1_output = (10); 
        1: stage1_output = (13); 
        2: stage1_output = (0); 
        3: stage1_output = (7); 
        4: stage1_output = (9); 
        5: stage1_output = (0); 
        6: stage1_output = (14); 
        7: stage1_output = (9); 
        8: stage1_output = (6); 
        9: stage1_output = (3); 
        10: stage1_output = (3); 
        11: stage1_output = (4); 
        12: stage1_output = (15); 
        13: stage1_output = (6); 
        14: stage1_output = (5); 
        15: stage1_output = (10); 
        16: stage1_output = (1); 
        17: stage1_output = (2); 
        18: stage1_output = (13); 
        19: stage1_output = (8); 
        20: stage1_output = (12); 
        21: stage1_output = (5); 
        22: stage1_output = (7); 
        23: stage1_output = (14); 
        24: stage1_output = (11); 
        25: stage1_output = (12); 
        26: stage1_output = (4); 
        27: stage1_output = (11); 
        28: stage1_output = (2); 
        29: stage1_output = (15); 
        30: stage1_output = (8); 
        31: stage1_output = (1); 
        32: stage1_output = (13); 
        33: stage1_output = (1); 
        34: stage1_output = (6); 
        35: stage1_output = (10); 
        36: stage1_output = (4); 
        37: stage1_output = (13); 
        38: stage1_output = (9); 
        39: stage1_output = (0); 
        40: stage1_output = (8); 
        41: stage1_output = (6); 
        42: stage1_output = (15); 
        43: stage1_output = (9); 
        44: stage1_output = (3); 
        45: stage1_output = (8); 
        46: stage1_output = (0); 
        47: stage1_output = (7); 
        48: stage1_output = (11); 
        49: stage1_output = (4); 
        50: stage1_output = (1); 
        51: stage1_output = (15); 
        52: stage1_output = (2); 
        53: stage1_output = (14); 
        54: stage1_output = (12); 
        55: stage1_output = (3); 
        56: stage1_output = (5); 
        57: stage1_output = (11); 
        58: stage1_output = (10); 
        59: stage1_output = (5); 
        60: stage1_output = (14); 
        61: stage1_output = (2); 
        62: stage1_output = (7); 
        63: stage1_output = (12); 
  
endcase



end

endmodule
module s5(stage1_input,stage1_output);
input [5:0] stage1_input;
output [3:0] stage1_output;

reg [3:0] stage1_output;



always @(  stage1_input)

begin

   case(stage1_input)

        0: stage1_output = (2); 
        1: stage1_output = (14); 
        2: stage1_output = (12); 
        3: stage1_output = (11); 
        4: stage1_output = (4); 
        5: stage1_output = (2); 
        6: stage1_output = (1); 
        7: stage1_output = (12); 
        8: stage1_output = (7); 
        9: stage1_output = (4); 
        10: stage1_output = (10); 
        11: stage1_output = (7); 
        12: stage1_output = (11); 
        13: stage1_output = (13); 
        14: stage1_output = (6); 
        15: stage1_output = (1); 
        16: stage1_output = (8); 
        17: stage1_output = (5); 
        18: stage1_output = (5); 
        19: stage1_output = (0); 
        20: stage1_output = (3); 
        21: stage1_output = (15); 
        22: stage1_output = (15); 
        23: stage1_output = (10); 
        24: stage1_output = (13); 
        25: stage1_output = (3); 
        26: stage1_output = (0); 
        27: stage1_output = (9); 
        28: stage1_output = (14); 
        29: stage1_output = (8); 
        30: stage1_output = (9); 
        31: stage1_output = (6); 
        32: stage1_output = (4); 
        33: stage1_output = (11); 
        34: stage1_output = (2); 
        35: stage1_output = (8); 
        36: stage1_output = (1); 
        37: stage1_output = (12); 
        38: stage1_output = (11); 
        39: stage1_output = (7); 
        40: stage1_output = (10); 
        41: stage1_output = (1); 
        42: stage1_output = (13); 
        43: stage1_output = (14); 
        44: stage1_output = (7); 
        45: stage1_output = (2); 
        46: stage1_output = (8); 
        47: stage1_output = (13); 
        48: stage1_output = (15); 
        49: stage1_output = (6); 
        50: stage1_output = (9); 
        51: stage1_output = (15); 
        52: stage1_output = (12); 
        53: stage1_output = (0); 
        54: stage1_output = (5); 
        55: stage1_output = (9); 
        56: stage1_output = (6); 
        57: stage1_output = (10); 
        58: stage1_output = (3); 
        59: stage1_output = (4); 
        60: stage1_output = (0); 
        61: stage1_output = (5); 
        62: stage1_output = (14); 
        63: stage1_output = (3); 

endcase


	

end

endmodule
module clk_on_lut(a, b, q, out, clk);

input wire clk;
input wire a;
input wire b;
output reg q;
output wire out;

always @(posedge clk) begin
  q <= a;
end

assign out = b & clk;

endmodule
module rst_on_lut_8bit(a, b0, b1, b2, b3, b4, b5, b6, b7, q, out0, out1, out2, out3, out4, out5, out6, out7,  clk, rst);

input wire rst;
input wire clk;
input wire a;
input wire b0;
input wire b1;
input wire b2;
input wire b3;
input wire b4;
input wire b5;
input wire b6;
input wire b7;
output reg q;
output wire out0;
output wire out1;
output wire out2;
output wire out3;
output wire out4;
output wire out5;
output wire out6;
output wire out7;

always @(posedge rst or posedge clk) begin
  if (rst) begin
    q <= 0;
  end else begin
    q <= a;
  end
end

assign out0 = b0 & ~rst;
assign out1 = b1 & ~rst;
assign out2 = b2 & ~rst;
assign out3 = b3 & ~rst;
assign out4 = b4 & ~rst;
assign out5 = b5 & ~rst;
assign out6 = b6 & ~rst;
assign out7 = b7 & ~rst;

endmodule
module rst_on_lut_4bit(a, b0, b1, b2, b3, q, out0, out1, out2, out3, clk, rst);

input wire rst;
input wire clk;
input wire a;
input wire b0;
input wire b1;
input wire b2;
input wire b3;
output reg q;
output wire out0;
output wire out1;
output wire out2;
output wire out3;

always @(posedge rst or posedge clk) begin
  if (rst) begin
    q <= 0;
  end else begin
    q <= a;
  end
end

assign out0 = b0 & ~rst;
assign out1 = b1 & ~rst;
assign out2 = b2 & ~rst;
assign out3 = b3 & ~rst;

endmodule
module and4(
  a,
  b,
  c,
  d,
  e);

input wire a;
input wire b;
input wire c;
input wire d;
output wire e;

assign e = a & b & c & d;

endmodule
module pipelined_8bit_adder(
    input clk,
    input ren,
    input wen,
    input raddr_0_,
    input raddr_1_,
    input raddr_2_,
    input raddr_3_,
    input raddr_4_,
    input raddr_5_,
    input waddr_0_,
    input waddr_1_,
    input waddr_2_,
    input waddr_3_,
    input waddr_4_,
    input waddr_5_,
    input a_0_,
    input a_1_,
    input a_2_,
    input a_3_,
    input a_4_,
    input a_5_,
    input a_6_,
    input b_0_,
    input b_1_,
    input b_2_,
    input b_3_,
    input b_4_,
    input b_5_,
    input b_6_,
    output q_0_,
    output q_1_,
    output q_2_,
    output q_3_,
    output q_4_,
    output q_5_,
    output q_6_,
    output q_7_);

	wire [5:0] raddr;
	wire [5:0] waddr;
	wire [6:0] a;
	wire [6:0] b;
	wire [7:0] q;


	assign raddr = { raddr_5_, raddr_4_, raddr_3_, raddr_2_, raddr_1_, raddr_0_ };
	assign waddr = { waddr_5_, waddr_4_, waddr_3_, waddr_2_, waddr_1_, waddr_0_ };
	assign a = { a_6_, a_5_, a_4_, a_3_, a_2_, a_1_, a_0_ };
	assign b = { b_6_, b_5_, b_4_, b_3_, b_2_, b_1_, b_0_ };
    assign q_7_ = q[7];
    assign q_6_ = q[6];
    assign q_5_ = q[5];
    assign q_4_ = q[4];
    assign q_3_ = q[3];
    assign q_2_ = q[2];
    assign q_1_ = q[1];
    assign q_0_ = q[0];

	reg[7:0] ram[63:0];
	reg[6:0] a_st0;
	reg[6:0] a_st1;
	reg[6:0] b_st0;
	reg[6:0] b_st1;
	reg[8:0] waddr_st0;
	reg[8:0] waddr_st1;
	reg wen_st0;
	reg wen_st1;
	reg[7:0] q_int;

	wire[7:0] AplusB;

	assign AplusB = a_st1 + b_st1;
	assign q = q_int;

	always@(posedge clk) begin
		waddr_st0 <= waddr;
		waddr_st1 <= waddr_st0;
		a_st0 <= a;
		a_st1 <= a_st0;
		b_st0 <= b;
		b_st1 <= b_st0;
		wen_st0 <= wen;
		wen_st1 <= wen_st0;
		if(wen_st1) begin
			ram[waddr_st1] <= AplusB;
		end
		if(ren) begin
			q_int <= ram[raddr];
		end
	end

endmodule
module rst_and_clk_on_lut(a, b, c, q, out0, out1, clk, rst);

input wire rst;
input wire clk;
input wire a;
input wire b;
input wire c;
output reg q;
output wire out0;
output wire out1;

always @(posedge rst or posedge clk) begin
  if (rst) begin
    q <= 0;
  end else begin
    q <= a;
  end
end

assign out0 = b & ~rst;
assign out1 = c & ~clk;

endmodule
module clk_cond(clk_i, clk_cond_i, d_i, q_o);

input wire clk_cond_i;
input wire clk_i;
input wire d_i;
output reg q_o;

wire int_clk;
assign int_clk = clk_cond_i & clk_i;

always @(posedge int_clk) begin
  q_o <= d_i;
end

endmodule
module dual_port_ram_16k (
  input clk,
  input wen,
  input ren,
  input [10:0] waddr,
  input [10:0] raddr,
  input [7:0] din,
  output [7:0] dout
);

    dual_port_sram_16kb memory_0 (
      .wclk    (clk),
      .wen    (wen),
      .waddr    (waddr),
      .data_in  (din),
      .rclk    (clk),
      .ren    (ren),
      .raddr    (raddr),
      .data_out    (dout) );

endmodule
module dual_port_sram_16kb (
  input wclk,
  input wen,
  input [10:0] waddr,
  input [7:0] data_in,
  input rclk,
  input ren,
  input [10:0] raddr,
  output [7:0] data_out
);

  reg [7:0] ram[2047:0];
  reg [7:0] internal;

  assign data_out = internal;

  always @(posedge wclk) begin
    if(wen) begin
      ram[waddr] <= data_in;
    end
  end

  always @(posedge rclk) begin
    if(ren) begin
      internal <= ram[raddr];
    end
  end

endmodule
module asyn_spram_4x1(
  clk,
  addr_0,
  addr_1,
  d_in,
  wr_en,
  d_out );

  input wire  clk;
  input wire  addr_0;
  input wire  addr_1;
  input wire  d_in;
  input wire  wr_en;
  output wire d_out;

  wire[1:0]   addr;
  reg [3:0]   mem;

  assign addr = {addr_1, addr_0};
  assign d_out = (addr == 2'd0)? mem[0]:
                 (addr == 2'd1)? mem[1]:
                 (addr == 2'd2)? mem[2]: mem[3];

  always@(posedge clk) begin
    if(wr_en) begin
      mem[addr] <= d_in;
    end
  end

endmodule
module discrete_dffn(
  clk_ni,
  d_i,
  d_o);
input wire clk_ni;
input wire d_i;
output reg d_o;

wire int_clk;

assign int_clk = ~clk_ni;

always @(posedge int_clk) begin
  d_o <= d_i;
end

endmodule
module configuration_manager(
    input clk_in,
    output prog_reset,
    output prog_clk,
    output ccff_head,
    output configuration_done
    );
    
    parameter START_CYCLE=3; // Start configuration on cycle 3 of prog_clk
    parameter CONFIGURATION_CLK_DIV_SIZE=12; // Divide clk_in (50MHz) by 4096 (2^12) times
    
    wire prog_clk_out; // prog_clk signal from clk_divider
    wire ccff_head_out;
    
    assign ccff_head = ccff_head_out & ~prog_reset;
    assign prog_clk = prog_clk_out & ~configuration_done; // prog_clk will stop when configuration done
    
    // PRESET
    // Programming reset will be enabled until START_CYCLE
    reset_generator #(
      .INITIAL_VALUE(1),
      .ACTIVE_CYCLES(START_CYCLE)
    ) prog_reset_generator(
      .clk(~prog_clk),
      .pulse(prog_reset)
    );
    
    
    // PROG_CLK
    // Divide pl_clk (50MHz) by 4096 (2^12) times
    clock_divider #(
      .CLK_DIVIDER_SIZE(CONFIGURATION_CLK_DIV_SIZE)
      ) prog_clk_divider (
        .clk_in(clk_in),
        .clk_out(prog_clk_out)
      ); 
      
      
    // Instantiate bitstream loader
    bitstream_loader loader (
      .prog_clk(prog_clk),
      .config_chain_head(ccff_head_out),
      .start(~prog_reset),
      .done(configuration_done)
    );
    
endmodule
module test_mode_low (
	a,
	b,
	clk,
	reset,
	out );

	input wire a;
	input wire b;
	input wire clk;
	input wire reset;
	output wire[3:0] out;

	reg[1:0] pipe_a;
	reg[1:0] pipe_b;
	reg[3:0] pipe_sum;
	wire[7:0] sum;

	assign sum[1:0] = pipe_a[1] + pipe_b[1] + pipe_sum[3];
	assign sum[3:2] = pipe_sum[0] + sum[1] + pipe_sum[2];
	assign sum[5:4] = pipe_sum[1] + sum[3] + pipe_sum[3];
	assign sum[7:6] = pipe_sum[2] + sum[5] + pipe_sum[0];
	assign out = pipe_sum;

	initial begin
		pipe_a <= 2'b00;
		pipe_b <= 2'b00;
		pipe_sum <= 4'b0000;
	end

	always @(posedge clk or posedge reset) begin
		if(reset) begin
			pipe_a <= 2'b00;
			pipe_b <= 2'b00;
			pipe_sum <= 4'b0000;
		end else begin
			pipe_a[0] <= a;
			pipe_a[1] <= pipe_a[0];
			pipe_b[0] <= b;
			pipe_b[1] <= pipe_b[0];
			pipe_sum <= {sum[6], sum[4], sum[2], sum[0]};
		end	
	end

endmodule
module clk_divider(clk_i, clk_o);

input wire clk_i;
output reg clk_o;

reg int_clk;

initial begin
  clk_o <= 0;
  int_clk <= 0;
end

always @(posedge clk_i) begin
  int_clk <= ~int_clk;
end

always @(posedge int_clk) begin
  clk_o <= ~clk_o;
end

endmodule
module syn_spram_4x1(
  clk,
  addr_0,
  addr_1,
  d_in,
  wr_en,
  d_out );

  input wire  clk;
  input wire  addr_0;
  input wire  addr_1;
  input wire  d_in;
  input wire  wr_en;
  output reg  d_out;

  wire[1:0]   addr;
  wire        tmp;
  reg [3:0]   mem;

  assign addr = {addr_1, addr_0};
  assign tmp  = (addr == 2'd0)? mem[0]:
                (addr == 2'd1)? mem[1]:
                (addr == 2'd2)? mem[2]: mem[3];

  always@(posedge clk) begin
    if(wr_en) begin
      mem[addr] <= d_in;
    end
    d_out <= tmp;
  end

endmodule
module dual_port_ram_1k (
  input clk,
  input wen,
  input ren,
  input [6:0] waddr,
  input [6:0] raddr,
  input [7:0] din,
  output [7:0] dout
);

    dual_port_sram_1kb memory_0 (
      .wclk    (clk),
      .wen    (wen),
      .waddr    (waddr),
      .data_in  (din),
      .rclk    (clk),
      .ren    (ren),
      .raddr    (raddr),
      .data_out    (dout) );

endmodule
module dual_port_sram_1kb (
  input wclk,
  input wen,
  input [6:0] waddr,
  input [7:0] data_in,
  input rclk,
  input ren,
  input [6:0] raddr,
  output [7:0] data_out
);

  reg [7:0] ram[127:0];
  reg [7:0] internal;

  assign data_out = internal;

  always @(posedge wclk) begin
    if(wen) begin
      ram[waddr] <= data_in;
    end
  end

  always @(posedge rclk) begin
    if(ren) begin
      internal <= ram[raddr];
    end
  end

endmodule
module clk_gate(
  rst_i,
  clk_i,
  data_i,
  data_o);
input wire rst_i;
input wire clk_i;
input wire data_i;
output wire data_o;
reg q;

always @(posedge clk_i) begin
  if (rst_i) begin
    q <= 0;
  end else begin
    q <= 1;
  end
end
assign data_o = data_i & q;

endmodule
module FSM_minute(
	input wire rst,
	input wire clk,
	input wire [5:0] min_in,
	input wire min_in_load,
	input wire [5:0] sec_count,
	output reg [5:0] min_out);
	
	reg  [2:0] ps, ns;
	wire [5:0] min_data_add;
	reg  [5:0] min_data;
	reg  [5:0] min_ps, min_ns;
	reg  [1:0] min_sel;
	wire min_count;
	
	always@(posedge clk)
	begin
		if(rst) ps <= 3'd0;
		else ps <= ns;
	end
	
	always@(posedge clk)
	begin
		if(rst) min_ps <= 6'd0;
		else min_ps <= min_ns;
	end
	
	always@(*)
	begin
		min_sel = 2'd0;
		case(ps)
			3'd0: begin
				ns = 3'd1;
			end
			3'd1: begin
				if(min_in_load) begin
					min_sel = 2'd1;
					min_out = min_data;
					ns = 3'd2;
					min_ns = min_data;
				end
				else ns = 3'd1;
			end
			3'd2: begin
				if(min_count == 1'd1) begin
					if(min_data == 6'd59) begin
						min_out = min_data;
						ns = 3'd2;
						min_ns = 6'd0;
					end
					else begin
						min_out = min_data;
						ns = 3'd2;
						min_ns = min_data_add;
					end
				end
				else begin
					min_out = min_data;
					min_ns = min_data;
					ns = 3'd2;
				end
			end
			default: begin
				ns = 3'd0;
			end
		endcase
	end
	
	assign min_data_add = min_data + 1;
	assign min_count = (sec_count == 6'd59) ? 1'd1 : 1'd0;
	
	always@(*)
	begin
		case(min_sel)
			2'd0: min_data = min_ps;
			2'd1: min_data = min_in;
		endcase
	end

endmodule
module FSM_top(
	input wire rst,
	input wire clk,
	input wire load_in,
	input wire [5:0] sec_in,
	input wire [5:0] min_in,
	input wire [5:0] hour_in,
	output wire [5:0] sec_out,
	output wire [5:0] min_out,
	output wire [5:0] hour_out
	);

	FSM_second FSM_sec(
		.rst(rst),
		.clk(clk),
		.sec_in(sec_in),
		.sec_in_load(load_in),
		.sec_out(sec_out));

	FSM_minute FSM_min(
		.rst(rst),
		.clk(clk),
		.min_in(min_in),
		.min_in_load(load_in),
		.sec_count(sec_out),
		.min_out(min_out));
		
	FSM_hour FSM_hr(
		.rst(rst),
		.clk(clk),
		.hour_in(hour_in),
		.hour_in_load(load_in),
		.min_count(min_out),
		.hour_out(hour_out),
		.sec_count(sec_out));

endmodule
module FSM_hour(
	input wire rst,
	input wire clk,
	input wire [5:0] hour_in,
	input wire hour_in_load,
	input wire [5:0] min_count,
	input wire [5:0] sec_count,
	output reg [5:0] hour_out);
	
	reg  [2:0] ps, ns;
	wire [5:0] hour_data_add;
	reg  [5:0] hour_data;
	reg  [5:0] hour_ps, hour_ns;
	reg  [1:0] hour_sel;
	wire hour_count;
	
	always@(posedge clk)
	begin
		if(rst) ps <= 3'd0;
		else ps <= ns;
	end
	
	always@(posedge clk)
	begin
		if(rst) hour_ps <= 6'd0;
		else hour_ps <= hour_ns;
	end
	
	always@(*)
	begin
		hour_sel = 2'd0;
		case(ps)
			3'd0: begin
				ns = 3'd1;
			end
			3'd1: begin
				if(hour_in_load) begin
					hour_sel = 2'd1;
					hour_out = hour_data;
					ns = 3'd2;
					hour_ns = hour_data;
				end
				else ns = 3'd1;
			end
			3'd2: begin
				if(hour_count == 1'd1) begin
					if(hour_data == 6'd59) begin
						hour_out = hour_data;
						ns = 3'd2;
						hour_ns = 6'd0;
					end
					else begin
						hour_out = hour_data;
						ns = 3'd2;
						hour_ns = hour_data_add;
					end
				end
				else begin
					hour_out = hour_data;
					hour_ns = hour_data;
					ns = 3'd2;
				end
			end
			default: begin
				ns = 3'd0;
			end
		endcase
	end
	
	assign hour_data_add = hour_data + 1;
	assign hour_count = ((sec_count == 6'd59)&&(min_count == 6'd59)) ? 1'd1 : 1'd0;
	
	always@(*)
	begin
		case(hour_sel)
			2'd0: hour_data = hour_ps;
			2'd1: hour_data = hour_in;
		endcase
	end

endmodule
module FSM_second(
	input wire rst,
	input wire clk,
	input wire [5:0] sec_in,
	input wire sec_in_load,
	output reg [5:0] sec_out);
	
	reg  [2:0] ps, ns;
	wire [5:0] sec_data_add;
	reg  [5:0] sec_data;
	reg  [5:0] sec_ps, sec_ns;
	reg  [1:0] sec_sel;
	
	always@(posedge clk)
	begin
		if(rst) ps <= 3'd0;
		else ps <= ns;
	end
	
	always@(posedge clk)
	begin
		if(rst) sec_ps <= 6'd0;
		else sec_ps <= sec_ns;
	end
	
	always@(*)
	begin
		sec_sel = 2'd0;
		case(ps)
			3'd0: begin
				ns = 3'd1;
			end
			3'd1: begin
				if(sec_in_load) begin
					sec_sel = 2'd1;
					sec_out = sec_data;
					ns = 3'd2;
					sec_ns = sec_data_add;
				end
				else ns = 3'd1;
			end
			3'd2: begin
				if(sec_data == 6'd59) begin
					sec_out = sec_data;
					ns = 3'd2;
					sec_ns = 6'd0;
				end
				else begin
					sec_out = sec_data;
					ns = 3'd2;
					sec_ns = sec_data_add;
				end
			end
			default: begin
				ns = 3'd0;
			end
		endcase
	end
	
	assign sec_data_add = sec_data + 1;
	
	always@(*)
	begin
		case(sec_sel)
			2'd0: sec_data = sec_ps;
			2'd1: sec_data = sec_in;
		endcase
	end

endmodule
module FSM_three_tb;

	reg rst;
	reg clk;
	reg [5:0] sec_in, min_in, hour_in;
	reg load_in;
	wire [5:0] sec_out, min_out, hour_out;

	FSM_top FSM_1(
		.rst(rst),
		.clk(clk),
		.sec_in(sec_in),
		.load_in(load_in),
		.sec_out(sec_out),
		.min_in(min_in),
		.min_out(min_out),
		.hour_in(hour_in),
		.hour_out(hour_out));
		
	initial begin
		#0 rst = 1'd1; clk = 1'd0; load_in = 1'd1; sec_in = 6'd33; min_in = 6'd14; hour_in = 6'd5;
		#100 rst = 1'd0;
		#50 load_in = 1'd0;
	end
	
	always begin
		#10 clk = ~clk;
	end
	
	initial begin
		#100000 $stop;
	end

endmodule
module rst_cond(rst_i, rst_cond_i, clk_i, d_i, q_o);

input wire rst_cond_i;
input wire rst_i;
input wire clk_i;
input wire d_i;
output reg q_o;

wire int_rst;
assign int_rst = rst_cond_i & rst_i;

always @(posedge int_rst or posedge clk_i) begin
  if (int_rst) begin
    q_o <= 0;
  end else begin
    q_o <= d_i;
  end
end

endmodule
module and2_pipelined(
  clk,
  a,
  b,
  c);

input wire clk;
input wire a;
input wire b;
output wire c;

reg a_reg;
reg b_reg;
reg c_reg;

always @(posedge clk) begin
  a_reg <= a;
  b_reg <= b;
end

always @(posedge clk) begin
  c_reg <= a_reg & b_reg;
end

assign c = c_reg;

endmodule
module or2(
  a,
  b,
  c);

input wire a;
input wire b;
output wire c;

assign c = a | b;

endmodule
module and2_latch_2clock(
  a0,
  b0,
  clk0,
  a1,
  b1,
  clk1,
  c0,
  d0,
  c1,
  d1);

input wire clk0;

input wire a0;
input wire b0;
output wire c0;
output reg d0;

input wire clk1;

input wire a1;
input wire b1;
output wire c1;
output reg d1;


assign c0 = a0 & b0;

always @(posedge clk0) begin
  d0 <= c0;
end

assign c1 = a1 & b1;

always @(posedge clk1) begin
  d1 <= c1;
end

endmodule
module rst_on_lut(a, b, q, out, clk, rst);

input wire rst;
input wire clk;
input wire a;
input wire b;
output reg q;
output wire out;

always @(posedge rst or posedge clk) begin
  if (rst) begin
    q <= 0;
  end else begin
    q <= a;
  end
end

assign out = b & ~rst;

endmodule
module pulse_generator(
  input clk_in,
  input repeated, // Specify if the pulse should be generated repeatedly
  output reg pulse
  );
    
    
  parameter INITIAL_VALUE=0; // Define the initial value for the pulse, either 0 or 1; The pulse logic level will be a flip over the initial value
  parameter WAIT_CYCLES=0; // Define the number of clock cycles to wait before the pulse is applied
  parameter PULSE_WIDTH=1; // Define the length of the pulse width 
  parameter PULSE_COUNTER_SIZE=10; // Define the size of the pulse width counter
  
  reg [WAIT_CYCLES<=2 ? 2 : $clog2(WAIT_CYCLES) : 0] wait_cycle_counter; // Size of wait counter is determined by WAIT_CYCLES
  reg [PULSE_COUNTER_SIZE - 1 : 0] pulse_width_counter;
  reg pulse_start;
  reg pulse_end;

`ifdef VIVADO_SYNTHESIS
  initial begin
    pulse <= INITIAL_VALUE;
    pulse_start <= 1'b0;
    pulse_end <= 1'b0;
    wait_cycle_counter <= 0;
    pulse_width_counter <= 0;
  end
`endif
  
  // Wait a number of clock cycles, hold the initial value
  always @(posedge clk_in) begin
    if (wait_cycle_counter == WAIT_CYCLES) begin
      pulse_start <= 1'b1;
    end
    if (~pulse_start) begin
      wait_cycle_counter <= wait_cycle_counter + 1;
    end
  end
  
  // Wait a number of clock cycles, hold the initial value
  always @(posedge clk_in) begin
    pulse <= INITIAL_VALUE;
    if (pulse_start && ~pulse_end) begin
      // Reach the pulse width limit, stop counting
      if (pulse_width_counter < PULSE_WIDTH) begin
        pulse <= ~INITIAL_VALUE;
        if (~repeated) begin
          pulse_end = 1'b1;
        end
      end
      // When pulse ends, flip to initial value
      if (pulse_end) begin
        pulse <= INITIAL_VALUE;
      end
      pulse_width_counter <= pulse_width_counter + 1;
    end
  end
  
endmodule
module reset_generator(
	input clk,
	output reg pulse
	);

	parameter INITIAL_VALUE=0; // Define the initial value for the pulse, either 0 or 1; The pulse logic level will be a flip over the initial value
	parameter ACTIVE_CYCLES=0; // Define the number of clock cycles to wait before the pulse is applied

	reg [ACTIVE_CYCLES<=2 ? 2 : $clog2(ACTIVE_CYCLES) - 1 : 0] active_cycle_counter;

`ifdef VIVADO_SYNTHESIS
	initial begin
		clkdiv_counter <= 0;
		active_cycle_counter <= 0;
		pulse <= INITIAL_VALUE;
	end
`endif

	// Wait a number of clock cycles, hold the initial value
	always @(posedge clk) begin
		if (active_cycle_counter == ACTIVE_CYCLES) begin
			pulse <= ~pulse;
		end else begin 
			active_cycle_counter <= active_cycle_counter + 1;
		end
	end

endmodule
module clock_divider (
    input clk_in,
    output reg clk_out
    );
    
    parameter CLK_DIVIDER_SIZE=8;
    
    reg [CLK_DIVIDER_SIZE - 1:0] clkdiv_counter;
    
`ifdef VIVADO_SYNTHESIS
    initial begin
      clkdiv_counter <= 0;
      clk_out <= 0;
    end
`endif
    
    // Divide pl_clk (50MHz) to 1MHz
    always @(posedge clk_in) begin
        if (clkdiv_counter == 1 << CLK_DIVIDER_SIZE - 1) begin
            clk_out <= ~clk_out;
        end
        clkdiv_counter <= clkdiv_counter +1;
    end
    
endmodule
module test_modes(
	clk,
	a_0,
	a_1,
	a_2,
	a_3,
	b_0,
	b_1,
	b_2,
	b_3,
	cin,
	e,
	f,
	g,
	sum_0,
	sum_1,
	sum_2,
	sum_3,
	cout,
	x,
	y,
	z );

	input wire clk, a_0, a_1, a_2, a_3, b_0, b_1, b_2, b_3, cin, e, f, g;
	output reg sum_0, sum_1, sum_2, sum_3, cout;
	output wire x, y, z;

	wire d0;
	wire [4:0] n0;
	wire [3:0] a, b;
	reg reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9, reg10, reg11, reg_a_0, reg_a_1, reg_a_2, reg_a_3, reg_b_0, reg_b_1, reg_b_2, reg_b_3, reg_cin;

	assign a = {reg_a_3, reg_a_2, reg_a_1, reg_a_0};
	assign b = {reg_b_3, reg_b_2, reg_b_1, reg_b_0};
	assign d0 = (e && g) || !f;
	assign n0 = a + b + reg_cin;
	assign x = reg3;
	assign y = reg7;
	assign z = reg11;

	always @(posedge clk) begin
		reg0 <= d0;
		reg1 <= reg0;
		reg2 <= reg1;
		reg3 <= reg2;
		reg4 <= reg3;
		reg5 <= reg4;
		reg6 <= reg5;
		reg7 <= reg6;
		reg8 <= reg7;
		reg9 <= reg8;
		reg10 <= reg9;
		reg11 <= reg10;
		reg_a_0 <= a_0;
		reg_a_1 <= a_1;
		reg_a_2 <= a_2;
		reg_a_3 <= a_3;
		reg_b_0 <= b_0;
		reg_b_1 <= b_1;
		reg_b_2 <= b_2;
		reg_b_3 <= b_3;
		reg_cin <= cin;
		sum_0 <= n0[0];
		sum_1 <= n0[1];
		sum_2 <= n0[2];
		sum_3 <= n0[3];
		cout <= n0[4];
	end

endmodule
module K4n4_test (
	clk,
	a,
	b,
	c,
	XOR,
	XNOR,
	AND,
	NAND,
	OR,
	NOR,
	XOR_sync,
	XNOR_sync,
	AND_sync,
	NAND_sync,
	OR_sync,
	NOR_sync );

	input  wire clk;
	input  wire a;
	input  wire b;
	input  wire c;
	output wire XOR;
	output wire XNOR;
	output wire AND;
	output wire NAND;
	output wire OR;
	output wire NOR;
	output reg  XOR_sync;
	output reg  XNOR_sync;
	output reg  AND_sync;
	output reg  NAND_sync;
	output reg  OR_sync;
	output reg  NOR_sync;

	assign XOR = a ^ b ^ c;
	assign XNOR = !XOR;
	assign OR = a || b || c;
	assign NOR = !( a || b || c);
	assign AND = a && b && c;
	assign NAND = !(a && b && c);

	always @(posedge clk) begin
		XOR_sync = XOR;
		XNOR_sync = XNOR;
		OR_sync = OR;
		NOR_sync = NOR;
		AND_sync = AND;
		NAND_sync = NAND;
	end

endmodule
module RISC_testbench;
   
wire	[7:0]bus_1_out;
reg	clk,rst;
wire	[7:0]Reg_R0_out;
wire	[7:0]Reg_R1_out;
wire	[7:0]Reg_R2_out;
wire	[7:0]Reg_R3_out;

/* wire	[7:0]MEMAddress;
wire	[7:0]MEMdataout;
wire  	MEMwrite; */

/* assign MEMAddress = top.MEMAddress;
assign MEMdataout = top.MEMdataout;
assign MEMwrite   = top.MEMwrite; */

RISC_core_mem_top top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst);

 always#20 clk=~clk;
   
 initial
    begin
      clk=0;rst=1;
      #30 rst=0;
      #6000 $stop;       
      end

/* //----------

	integer fp;
	initial
	begin
		fp = $fopen("RISC_xa.vec");
		
		$fdisplay(fp, "radix		1	  1	44	44	44	44	44	1	44	44");
		$fdisplay(fp, "vname	  clk	rst		Reg_R0_out[[7:0]]	Reg_R1_out[[7:0]]	Reg_R2_out[[7:0]]	Reg_R3_out[[7:0]]	bus_1_out[[7:0]]	MEMwrite	MEMAddress	MEMdataout");
		$fdisplay(fp, "   io		i	  i	oo	oo	oo	oo	oo	o	oo	ii");
		$fdisplay(fp, "slope		0.3");
		$fdisplay(fp, "  vih		3.3");
		$fdisplay(fp, "  vil		0");
		$fdisplay(fp, "tunit		ns");
	end
	always@(clk)
	begin
		$fdisplay(fp, "%t %b %b %h %h %h %h %h %b %h %h", $time, clk, rst, Reg_R0_out, Reg_R1_out, Reg_R2_out, Reg_R3_out, bus_1_out, MEMwrite, MEMAddress, MEMdataout);
	end

//---------- */
   
endmodule
module ALU(zero_flag_out,alu_out,Reg_Y_in,Bus_1_in,IR_code);

output	zero_flag_out;
output	reg	[7:0]alu_out;
input	[7:0]Reg_Y_in,Bus_1_in;
input	[7:0]IR_code;

wire	[3:0]opcode=IR_code[7:4];



always@(*)
	begin
		case(opcode)
		1:	alu_out=Reg_Y_in+Bus_1_in;
		2:	alu_out=Bus_1_in+~(Reg_Y_in)+1;
		3:	alu_out=Reg_Y_in&(Bus_1_in);
		4:  alu_out=~(Bus_1_in);
		default:alu_out=8'b0;
		endcase
	end

assign zero_flag_out=~|alu_out;

endmodule
module Memory(Data_out,Address);

	output	[7:0]Data_out;
	input	[7:0]Address;
	
	reg	[7:0]mem[255:0];
	assign	Data_out=mem[Address];
	
	always@(Address)
	begin
		case(Address)
							//opcode_src_dest
		//NOP
		0:	mem[Address]=8'b0000_00_00;
		
		//rd 00 10		//Read MEM[130] to R2
		1:	mem[Address]=8'b0101_00_10; //Instruction 
		2:	mem[Address]=130;	//Address
		
		//rd 00 11		//Read MEM[131] to R3
		3:	mem[Address]=8'b0101_00_11; //Instruction 
		4:	mem[Address]=131; //Address
		
		//rd 00 01		//Read MEM[128] to R1
		5:	mem[Address]=8'b0101_00_01; //Instruction
		6:	mem[Address]=128; //Address

		//rd 00 00		//Read MEM[129] to R0		
		7:	mem[Address]=8'b0101_00_00; //Instruction
		8:	mem[Address]=129; //Address
		
		//Sub 00 01		//Sub R1-R0 to R1
		9:	mem[Address]=8'b0010_00_01; //Instruction
		
		//BRZ 00 00    
		10:	mem[Address]=8'b1000_00_00; //Instruction
		11:	mem[Address]=134; //Address
		
		//Add 10 11		//Add R2+R3 to R3
		12:	mem[Address]=8'b00011011;
		
		//BR
		13:	mem[Address]=8'b01110011; //Instruction
		14:	mem[Address]=140; //Address
		
		128:mem[Address]=6;
		129:mem[Address]=1;
		130:mem[Address]=2;
		131:mem[Address]=0;
		134:mem[Address]=139; //Address
		135:mem[Address]=0;
		//HAL
		139:mem[Address]=8'b1111_00_00; //Instruction
		140:mem[Address]=9; //Address
		default mem[Address]=8'bx;
    endcase
  end
	
endmodule
module RISC_core_top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst,MEMdataout,MEMAddress);

output	[7:0]bus_1_out,MEMAddress;
input	clk,rst;
input	[7:0]MEMdataout;
output	[7:0]Reg_R0_out;
output	[7:0]Reg_R1_out;
output	[7:0]Reg_R2_out;
output	[7:0]Reg_R3_out;

wire	[7:0]BUS_2,BUS_1,MEMAddress;
wire	[7:0]alu_out;
wire	[7:0]MEMdataout;
wire	[7:0]Reg_Y_out,Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,PC_out;
wire	[7:0]IR_out;
wire	zero_flag_out;
wire	[2:0]Sel_Bus1;
wire	[1:0]Sel_Bus2;
wire	L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,L_IR,L_ADD_R,L_R_Y,L_R_Z,MEMwrite,zero;

assign	bus_1_out=BUS_1;
assign	bus_2_out=BUS_2;

Controller CON(L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,Sel_Bus1,L_IR,L_ADD_R,L_R_Y,L_R_Z,Sel_Bus2,MEMwrite,zero,IR_out,clk,rst);
//module PC(PC_out,PC_in,load,inc,clk,rst);
PC Program_Counter(PC_out,BUS_2,L_PC,Inc_PC,clk,rst);
//module ALU(zero_flag_out,alu_out,Reg_Y_in,Bus_1_in,IR_code);
ALU	 Arithmetic_Logic_Unit(zero_flag_out,alu_out,Reg_Y_out,BUS_1,IR_out);
//module Memory(Data_out,Data_in,MEMAddress,clk,MEMwrite);
//Memory MEM(MEMdataout,BUS_1,MEMAddress,clk,MEMwrite);
//module Mux_31(Y,A0,A1,A2,sel);
Mux_31	 Mux31(BUS_2,alu_out,BUS_1,MEMdataout,Sel_Bus2);
//module Reg_1bit(Q,D,load,clk,rst);
Reg_1bit Reg_Z(zero,zero_flag_out,L_R_Z,clk,rst);
//module Reg_8bit(Q,D,load,clk,rst);
Reg_8bit Reg_Y(Reg_Y_out,BUS_2,L_R_Y,clk,rst);
Reg_8bit Add_R(MEMAddress,BUS_2,L_ADD_R,clk,rst);
//R0~R3
Reg_8bit Reg_R0(Reg_R0_out,BUS_2,L_R0,clk,rst);
Reg_8bit Reg_R1(Reg_R1_out,BUS_2,L_R1,clk,rst);
Reg_8bit Reg_R2(Reg_R2_out,BUS_2,L_R2,clk,rst);
Reg_8bit Reg_R3(Reg_R3_out,BUS_2,L_R3,clk,rst);
//module Mux_51(Y,A0,A1,A2,A3,A4,sel);
Mux_51	Mux51(BUS_1,Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,PC_out,Sel_Bus1);
//module IR(IR_out,IR_in,load,clk,rst);
IR	Instruction_Register(IR_out,BUS_2,L_IR,clk,rst);

endmodule
module Mux_31(Y,A0,A1,A2,sel);

output	[7:0]Y;
input	[7:0]A2,A1,A0;
input	[1:0]sel;

reg		[7:0]Y;

always@(*)
	begin
		case(sel)
			0:	Y=A0;
			1:	Y=A1;
			2:	Y=A2;
			default:Y=8'bz;
		endcase
	end

endmodule
module RISC_core_mem_top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst);

output	[7:0]bus_1_out;
input	clk,rst;
output	[7:0]Reg_R0_out;
output	[7:0]Reg_R1_out;
output	[7:0]Reg_R2_out;
output	[7:0]Reg_R3_out;

wire	[7:0]bus_1_out,MEMAddress;
wire	clk,rst;
wire	[7:0]MEMdataout;
wire	[7:0]Reg_R0_out;
wire	[7:0]Reg_R1_out;
wire	[7:0]Reg_R2_out;
wire	[7:0]Reg_R3_out;


RISC_core_top core(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst,MEMdataout,MEMAddress);

Memory MEM(MEMdataout,MEMAddress);

endmodule
module IR(IR_out,IR_in,load,clk,rst);

output reg	[7:0]IR_out;
input	[7:0]IR_in;
input	load,clk,rst;

always@(posedge clk)
	begin
		if(rst==1)IR_out<=8'b0;
		else if(load==1)IR_out<=IR_in;		
	end

endmodule
module Mux_51(Y,A0,A1,A2,A3,A4,sel);

output	[7:0]Y;
input	[7:0]A4,A3,A2,A1,A0;
input	[2:0]sel;

reg		[7:0]Y;

always@(*)
	begin
		case(sel)
			0:	Y=A0;
			1:	Y=A1;
			2:	Y=A2;
			3:	Y=A3;
			4:	Y=A4;
			default:Y=8'bx;
		endcase
	end

endmodule
module Reg_1bit(Q,D,load,clk,rst);

output	Q;
input	D;
input	load,clk,rst;

reg 	Q;

always@(posedge clk)
	begin
		if(rst==1)Q<=0;
		else if(load==1)Q<=D;
	end

endmodule
module Reg_8bit(Q,D,load,clk,rst);

output	[7:0]Q;
input	[7:0]D;
input	load,clk,rst;

reg [7:0]Q;

always@(posedge clk)
	begin
		if(rst==1)Q<=8'b0;
		else if(load==1)Q<=D;
	end

endmodule
module PC(PC_out,PC_in,load,inc,clk,rst);

output	[7:0]PC_out;
input	[7:0]PC_in;
input	load,inc,clk,rst;

reg	[7:0]PC_out;

always@(posedge clk)
	begin
		if(rst==1)PC_out<=8'b0;
		else if(load==1)PC_out<=PC_in;
		else if(inc==1)PC_out<=PC_out+8'b00000001;		
	end
	
endmodule
module testSAPone;

	wire [7:0] SAP_out;
	wire [11:0] con;
	wire [7:0] bus;
//	wire clk_out, clr_out;
	reg clk, clr_;

	always #5 clk = ~clk;
	
	SAPone sapone1(
		.SAP_out(SAP_out),
		.con(con),
		.bus(bus),
//		.clk_out(clk_out),
//		.clr_out(clr_out),
		.clk(clk),
		.clr_(clr_)
		);
		
//	PC pc1(bus[3:0], clk, clr_, cp, ep);
//	MAR mar1(mar, clk, lm_, bus[3:0]);

	initial
	begin
		clk = 0; clr_ = 0;
		#10 clr_ = 1;
		
		
		
		#990 $stop;	
	end

endmodule
module OutputRegister(
	output reg [7:0] OutputRegister_out,
	input [7:0] OutputRegister_in,
	input lo_,
	input clk,
	input clr_
	);

	always @(posedge clk)
		if(~clr_) OutputRegister_out <= 8'b0;
		else if(~lo_) OutputRegister_out <= OutputRegister_in;

endmodule