dakies/OSS_Verilog huggingface dataset:
module clkdll_maximum_period_check (clock, rst);
parameter clock_name = "";
parameter maximum_period = 0;
input clock;
input rst;

time clock_edge;
time clock_period;

initial begin
    clock_edge = 0;
    clock_period = 0;
end

always @(posedge clock) begin
    clock_edge <= $time;
    clock_period <= $time - clock_edge;
    if (clock_period > maximum_period && rst == 0) begin
	$display("Warning : Input clock period of, %1.3f ns, on the %s port of instance %m exceeds allotted value of %1.3f ns at simulation time %1.3f ns.", clock_period/1000.0, clock_name, maximum_period/1000.0, $time/1000.0);
    end
end
endmodule
module IBUFG_SSTL18_I (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module KEEPER (O);

    inout O;
    reg   in;

    always @(O)
	if (O)
	    in <= 1;
	else
	    in <= 0;

    buf (pull1, pull0) B1 (O, in);

endmodule
module IBUFG_SSTL3_I (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module IBUF_PCIX (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module OR4B3 (O, I0, I1, I2, I3);

    output O;

    input  I0, I1, I2, I3;

    wire i0_inv;
    wire i1_inv;
    wire i2_inv;

    not N2 (i2_inv, I2);
    not N1 (i1_inv, I1);
    not N0 (i0_inv, I0);
    or O1 (O, i0_inv, i1_inv, i2_inv, I3);


endmodule
module IBUF_AGP (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module IBUF_PCI66_3 (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module AND3B2 (O, I0, I1, I2);

    output O;

    input  I0, I1, I2;

    wire i0_inv;
    wire i1_inv;

    not N1 (i1_inv, I1);
    not N0 (i0_inv, I0);
    and A1 (O, i0_inv, i1_inv, I2);


endmodule
module PULLDOWN (O);

    output O;

    wire A;

	pulldown (A);
	buf (weak0,weak1) #(100,100) (O,A);

endmodule
module RAM32M (DOA, DOB, DOC, DOD, ADDRA, ADDRB, ADDRC, ADDRD, DIA, DIB, DIC, DID, WCLK, WE);

  parameter  INIT_A = 64'h0000000000000000;
  parameter  INIT_B = 64'h0000000000000000;
  parameter  INIT_C = 64'h0000000000000000;
  parameter  INIT_D = 64'h0000000000000000;

  output [1:0] DOA;
  output [1:0] DOB;
  output [1:0] DOC;
  output [1:0] DOD;
  input [4:0] ADDRA;
  input [4:0] ADDRB;
  input [4:0] ADDRC;
  input [4:0] ADDRD;
  input [1:0] DIA;
  input [1:0] DIB;
  input [1:0] DIC;
  input [1:0] DID;
  input WCLK;
  input WE;

  reg [63:0] mem_a, mem_b, mem_c, mem_d;

  initial begin
    mem_a = INIT_A;
    mem_b = INIT_B;
    mem_c = INIT_C;
    mem_d = INIT_D;
  end

  always @(posedge WCLK)
    if (WE) begin
      mem_a[2*ADDRD] <= #100 DIA[0];
      mem_a[2*ADDRD + 1] <= #100 DIA[1];
      mem_b[2*ADDRD] <= #100 DIB[0];
      mem_b[2*ADDRD + 1] <= #100 DIB[1];
      mem_c[2*ADDRD] <= #100 DIC[0];
      mem_c[2*ADDRD + 1] <= #100 DIC[1];
      mem_d[2*ADDRD] <= #100 DID[0];
      mem_d[2*ADDRD + 1] <= #100 DID[1];
  end

   assign  DOA[0] = mem_a[2*ADDRA];
   assign  DOA[1] = mem_a[2*ADDRA + 1];
   assign  DOB[0] = mem_b[2*ADDRB];
   assign  DOB[1] = mem_b[2*ADDRB + 1];
   assign  DOC[0] = mem_c[2*ADDRC];
   assign  DOC[1] = mem_c[2*ADDRC + 1];
   assign  DOD[0] = mem_d[2*ADDRD];
   assign  DOD[1] = mem_d[2*ADDRD + 1];

endmodule
module MULT_AND (LO, I0, I1);

    output LO;

    input  I0, I1;

    and A1 (LO, I0, I1);

    specify
	(I0 *> LO) = (0, 0);
	(I1 *> LO) = (0, 0);
    endspecify

endmodule
module NAND4B2 (O, I0, I1, I2, I3);

    output O;

    input  I0, I1, I2, I3;

    wire i0_inv;
    wire i1_inv;

    not N1 (i1_inv, I1);
    not N0 (i0_inv, I0);
    nand A1 (O, i0_inv, i1_inv, I2, I3);


endmodule
module BUFT (O, I, T);

    output O;

    input  I, T;

	bufif0 T1 (O, I, T);


endmodule
module IBUF_LVDS (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module RAM16X1D (DPO, SPO, A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE);

    parameter INIT = 16'h0000;

    output DPO, SPO;

    input  A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE;

    reg  [15:0] mem;
    wire [3:0] adr;

    assign adr = {A3, A2, A1, A0};
    assign SPO = mem[adr];
    assign DPO = mem[{DPRA3, DPRA2, DPRA1, DPRA0}];

    initial 
        mem = INIT;

    always @(posedge WCLK) 
        if (WE == 1'b1)
            mem[adr] <= #100 D;

endmodule
module IBUFG_HSTL_II_18 (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module MUXCY_D (LO, O, CI, DI, S);

    output LO, O;
    reg    O, LO;

    input  CI, DI, S;

	always @(CI or DI or S) 
	    if (S) begin
		O = CI;
                LO = CI;
            end
	    else begin
		O = DI;
                LO = DI;
            end

endmodule
module IBUFG_SSTL2_II_DCI (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module IBUF_GTL (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module NOR2B2 (O, I0, I1);

    output O;

    input  I0, I1;

    wire i0_inv;
    wire i1_inv;

    not N1 (i1_inv, I1);
    not N0 (i0_inv, I0);
    nor O1 (O, i0_inv, i1_inv);


endmodule
module NOR3B2 (O, I0, I1, I2);

    output O;

    input  I0, I1, I2;

    wire i0_inv;
    wire i1_inv;

    not N1 (i1_inv, I1);
    not N0 (i0_inv, I0);
    nor O1 (O, i0_inv, i1_inv, I2);


endmodule
module clkdllhf_maximum_period_check (clock, rst);
parameter clock_name = "";
parameter maximum_period = 0;
input clock;
input rst;

time clock_edge;
time clock_period;

initial begin
    clock_edge <= 0;
    clock_period <= 0;
end

always @(posedge clock) begin
    clock_edge <= $time;
    clock_period <= $time - clock_edge;
    if (clock_period > maximum_period && rst == 0) begin
	$display("Warning : Input clock period of, %1.3f ns, on the %s port of instance %m exceeds allotted value of %1.3f ns at simulation time %1.3f ns.", clock_period/1000.0, clock_name, maximum_period/1000.0, $time/1000.0);
    end
end
endmodule
module IBUF_SSTL18_II (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module IBUFGDS_LVDSEXT_33 (O, I, IB);

    output O;

    input  I, IB;

    reg o_out;

    buf b_0 (O, o_out);

    always @(I or IB) begin
	if (I == 1'b1 && IB == 1'b0)
	    o_out <= I;
	else if (I == 1'b0 && IB == 1'b1)
	    o_out <= I;
    end


endmodule
module RAM16X1S_1 (O, A0, A1, A2, A3, D, WCLK, WE);

    parameter INIT = 16'h0000;

    output O;

    input  A0, A1, A2, A3, D, WCLK, WE;

    reg  [15:0] mem;
    wire [3:0] adr;

    assign adr = {A3, A2, A1, A0};
    assign O = mem[adr];

    initial
        mem = INIT;

    always @(negedge WCLK)
        if (WE == 1'b1)
            mem[adr] <= #100 D;

endmodule
module IBUF_HSTL_I_18 (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module MUXF5_D (LO, O, I0, I1, S);

    output LO, O;
    reg    O, LO;

    input  I0, I1, S;

	always @(I0 or I1 or S) 
	    if (S) begin
		O = I1;
		LO = I1;
            end
	    else begin
		O = I0;
		LO = I0;
	    end
endmodule
module RAM16X2S (O0, O1, A0, A1, A2, A3, D0, D1, WCLK, WE);

    parameter INIT_00 = 16'h0000;
    parameter INIT_01 = 16'h0000;

    output O0, O1;

    input  A0, A1, A2, A3, D0, D1, WCLK, WE;

    reg  [15:0] mem1;
    reg  [15:0] mem2;

    wire [3:0] adr;

    assign adr = {A3, A2, A1, A0};
    assign O0 = mem1[adr];
    assign O1 = mem2[adr];

    initial  begin
        mem1 = INIT_00;
        mem2 = INIT_01;
    end

    always @(posedge WCLK) 
        if (WE == 1'b1) begin
            mem1[adr] <= #100 D0;
            mem2[adr] <= #100 D1;
        end

endmodule
module IBUFG_PCI33_5 (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module IBUFG_LVDS (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module XOR5 (O, I0, I1, I2, I3, I4);

    output O;

    input  I0, I1, I2, I3, I4;

	xor X1 (O, I0, I1, I2, I3, I4);


endmodule
module ICAP_SPARTAN3A (BUSY, O, CE, CLK, I, WRITE);

    output BUSY;
    output [7:0] O;

    input  CE, CLK, WRITE;
    input  [7:0] I; 
    
endmodule
module NOR4B2 (O, I0, I1, I2, I3);

    output O;

    input  I0, I1, I2, I3;

    wire i0_inv;
    wire i1_inv;

    not N1 (i1_inv, I1);
    not N0 (i0_inv, I0);
    nor O1 (O, i0_inv, i1_inv, I2, I3);


endmodule
module NAND3 (O, I0, I1, I2);

    output O;

    input  I0, I1, I2;

    nand A1 (O, I0, I1, I2);


endmodule
module INV (O, I);

    output O;

    input  I;

	not N1 (O, I);

endmodule
module MUXF6 (O, I0, I1, S);

    output O;
    reg    O;

    input  I0, I1, S;

	always @(I0 or I1 or S)
	    if (S)
		O = I1;
	    else
		O = I0;
endmodule
module NOR5B5 (O, I0, I1, I2, I3, I4);

    output O;

    input  I0, I1, I2, I3, I4;

    wire i0_inv;
    wire i1_inv;
    wire i2_inv;
    wire i3_inv;
    wire i4_inv;

    not N4 (i4_inv, I4);
    not N3 (i3_inv, I3);
    not N2 (i2_inv, I2);
    not N1 (i1_inv, I1);
    not N0 (i0_inv, I0);
    nor O1 (O, i0_inv, i1_inv, i2_inv, i3_inv, i4_inv);


endmodule
module ROM256X1 (O, A0, A1, A2, A3, A4, A5, A6, A7);

    parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;

    output O;

    input  A0, A1, A2, A3, A4, A5, A6, A7;

    reg [255:0] mem;

    initial
	    mem = INIT;

    assign O = mem[{A7, A6, A5, A4, A3, A2, A1, A0}];


endmodule
module MUXF7_D (LO, O, I0, I1, S);

    output LO, O;
    reg    O, LO;

    input  I0, I1, S;

	always @(I0 or I1 or S)
            if (S) begin
		O = I1;
		LO = I1;
            end
	    else begin
		O = I0;
		LO = I0;
	    end
endmodule
module IBUFG_LVCMOS15 (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module IBUFG_SSTL3_I_DCI (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module OR4 (O, I0, I1, I2, I3);

    output O;

    input  I0, I1, I2, I3;

    or O1 (O, I0, I1, I2, I3);


endmodule
module JTAGPPC (TCK, TDIPPC, TMS, TDOPPC, TDOTSPPC);

output TCK;
output TDIPPC;
output TMS;

input TDOPPC;
input TDOTSPPC;

	assign TCK = 1'b1;
	assign TDIPPC = 1'b1;
	assign TMS = 1'b1;
endmodule
module IBUFGDS_DIFF_OUT (O, OB, I, IB);

    parameter DIFF_TERM = "FALSE";
    parameter IBUF_LOW_PWR = "TRUE";
    parameter IOSTANDARD = "LVDS_25";

    output O, OB;

    input  I, IB;

    reg  o_out;

    buf B0 (O, o_out);
    not B1 (OB, o_out);

    initial begin
        case (DIFF_TERM)

            "TRUE", "FALSE" : ;
            default : begin
                          $display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFGDS_DIFF_OUT instance %m is set to %s.  Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
                          $finish;
                      end

        endcase // case(DIFF_TERM)

        case (IBUF_LOW_PWR)

            "FALSE", "TRUE" : ;
            default : begin
                          $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUFGDS_DIFF_OUT instance %m is set to %s.  Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
                          $finish;
                      end

        endcase

    end

    always @(I or IB) begin
	if (I == 1'b1 && IB == 1'b0)
	    o_out <= I;
	else if (I == 1'b0 && IB == 1'b1)
	    o_out <= I;
    end


endmodule
module IBUFGDS_LVDS_33_DCI (O, I, IB);

    output O;

    input  I, IB;

    reg o_out;

    buf b_0 (O, o_out);

    always @(I or IB) begin
	if (I == 1'b1 && IB == 1'b0)
	    o_out <= I;
	else if (I == 1'b0 && IB == 1'b1)
	    o_out <= I;
    end


endmodule
module AND2 (O, I0, I1);

    output O;

    input  I0, I1;

    and A1 (O, I0, I1);

endmodule
module IDELAYCTRL (RDY, REFCLK, RST);

    output RDY;

    input REFCLK;
    input RST;

    wire refclk_in;
    wire rst_in;

    time clock_edge;
    reg [63:0] period;
    reg clock_low, clock_high;
    reg clock_posedge, clock_negedge;
    reg lost, rdy_out = 0;

    buf b_rdy (RDY, rdy_out);
    buf b_refclk (refclk_in, REFCLK);
    buf b_rst (rst_in, RST);
    

    always @(rst_in, lost) begin

	if ((rst_in == 1'b1) || (lost == 1))
	    
	    rdy_out <= 1'b0;

	else if (rst_in == 1'b0 && lost == 0)

	    rdy_out <= 1'b1;

    end

    
/*
   always @(posedge lost) begin

	rdy_out <= 1'b0;

    end
*/    
	
    initial begin
	clock_edge <= 0;
	clock_high <= 0;
	clock_low <= 0;
	lost <= 1;
	period <= 0;
    end


    always @(posedge refclk_in) begin
      if(rst_in == 1'b0) begin
	clock_edge <= $time;
	if (period != 0 && (($time - clock_edge) <= (1.5 * period)))
	    period <= $time - clock_edge;
	else if (period != 0 && (($time - clock_edge) > (1.5 * period)))
	    period <= 0;
	else if ((period == 0) && (clock_edge != 0))
	    period <= $time - clock_edge;
      end 
    end
    
    always @(posedge refclk_in) begin
	clock_low <= 1'b0;
	clock_high <= 1'b1;
	if (period != 0)
	    lost <= 1'b0;
	clock_posedge <= 1'b0;
	#((period * 9.1) / 10)
	if ((clock_low != 1'b1) && (clock_posedge != 1'b1))
	    lost <= 1;
    end
    
    always @(posedge refclk_in) begin
	clock_negedge <= 1'b1;
    end
    
    always @(negedge refclk_in) begin
	clock_posedge <= 1'b1;
    end
    
    always @(negedge refclk_in) begin
	clock_high  <= 1'b0;
	clock_low   <= 1'b1;
	if (period != 0)
	    lost <= 1'b0;
	clock_negedge <= 1'b0;
	#((period * 9.1) / 10)
	if ((clock_high != 1'b1) && (clock_negedge != 1'b1))
	    lost <= 1;
    end

    specify

	(REFCLK => RDY) = (100, 100);
	specparam PATHPULSE$ = 0;
    
    endspecify

endmodule // IDELAYCTRL
module BUFGMUX_VIRTEX4 (O, I0, I1, S);

    output O;
    
    input  I0;
    input  I1;
    input  S;

    BUFGCTRL bufgctrl_inst (.O(O), .CE0(1'b1), .CE1(1'b1), .I0(I0), .I1(I1), .IGNORE0(1'b0), .IGNORE1(1'b0), .S0(~S), .S1(S));
    
    defparam bufgctrl_inst.INIT_OUT = 1'b0;
    defparam bufgctrl_inst.PRESELECT_I0 = "TRUE";
    defparam bufgctrl_inst.PRESELECT_I1 = "FALSE";
    
endmodule
module AND2B1 (O, I0, I1);

    output O;

    input  I0, I1;

    wire i0_inv;

    not N0 (i0_inv, I0);
    and A1 (O, i0_inv, I1);


endmodule
module NOR5B4 (O, I0, I1, I2, I3, I4);

    output O;

    input  I0, I1, I2, I3, I4;

    wire i0_inv;
    wire i1_inv;
    wire i2_inv;
    wire i3_inv;

    not N3 (i3_inv, I3);
    not N2 (i2_inv, I2);
    not N1 (i1_inv, I1);
    not N0 (i0_inv, I0);
    nor O1 (O, i0_inv, i1_inv, i2_inv, i3_inv, I4);


endmodule
module IBUF_LVPECL (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module AUTOBUF (O, I);

    parameter BUFFER_TYPE = "AUTO";

    output O;

    input  I;

    initial begin
    case (BUFFER_TYPE)
      "AUTO" : ;
      "BUF" : ;
      "BUFG" : ;
      "BUFGP" : ;
      "BUFH" : ;
      "BUFIO" : ;
      "BUFIO2" : ;
      "BUFIO2FB" : ;
      "BUFR" : ;
      "IBUF" : ;
      "IBUFG" : ;
      "NONE" : ;
      "OBUF" : ;
      default : begin
        $display("Attribute Syntax Error : The Attribute BUFFER_TYPE on AUTOBUF instance %m is set to %s.  Legal values for this attribute are AUTO, BUF, BUFG, BUFGP, BUFH, BUFIO, BUFIO2, BUFIO2FB, BUFR, IBUF, IBUFG, NONE, and OBUF.", BUFFER_TYPE);
      end
    endcase
    end

	buf B1 (O, I);


endmodule
module NOR2 (O, I0, I1);

    output O;

    input  I0, I1;

    nor O1 (O, I0, I1);


endmodule
module IBUFG_HSTL_II_DCI (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module IBUF_SSTL2_II (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module IBUF_HSTL_II (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module OR2B2 (O, I0, I1);

    output O;

    input  I0, I1;

    wire i0_inv;
    wire i1_inv;

    not N1 (i1_inv, I1);
    not N0 (i0_inv, I0);
    or O1 (O, i0_inv, i1_inv);


endmodule
module RAM128X1S (O, A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE);

    parameter INIT = 128'h00000000000000000000000000000000;

    output O;

    input  A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE;

    reg  [127:0] mem;
    wire [6:0] adr;

    assign adr = {A6, A5, A4, A3, A2, A1, A0};
    assign O = mem[adr];

    initial 
        mem = INIT;

    always @(posedge WCLK) 
        if (WE == 1'b1)
            mem[adr] <= #100 D;

endmodule
module IBUFG_LVCMOS2 (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module XOR2 (O, I0, I1);

    output O;

    input  I0, I1;

	xor X1 (O, I0, I1);


endmodule
module SRLC32E (Q, Q31, A, CE, CLK, D);

    parameter INIT = 32'h00000000;

    output Q;
    output Q31;

    input  [4:0] A;
    input  CE, CLK, D;

    reg  [31:0] data;


    assign  Q = data[A];
    assign  Q31 = data[31];

    initial
    begin
          assign  data = INIT;
          while (CLK === 1'b1 || CLK===1'bX) 
            #10; 
          deassign data;
    end

    always @(posedge CLK)
	if (CE == 1'b1) 
	    data <= #100 {data[30:0], D};


endmodule
module IBUFG_AGP (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module IBUF_SSTL3_I (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module AND5B4 (O, I0, I1, I2, I3, I4);

    output O;

    input  I0, I1, I2, I3, I4;

    wire i0_inv;
    wire i1_inv;
    wire i2_inv;
    wire i3_inv;

    not N3 (i3_inv, I3);
    not N2 (i2_inv, I2);
    not N1 (i1_inv, I1);
    not N0 (i0_inv, I0);
    and A1 (O, i0_inv, i1_inv, i2_inv, i3_inv, I4);


endmodule
module IBUF_HSTL_IV_DCI_18 (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module LUT4_D (LO, O, I0, I1, I2, I3);

  parameter INIT = 16'h0000;

  input I0, I1, I2, I3;

  output O, LO;

  reg O;
  reg tmp;
  wire LO;

  assign LO = O;

  always @(  I3 or  I2 or  I1 or  I0 )  begin
 
    tmp =  I0 ^ I1  ^ I2 ^ I3;

    if ( tmp == 0 || tmp == 1)

        O = INIT[{I3, I2, I1, I0}];

    else 
    
      O =  lut4_mux4 ( {lut4_mux4 ( INIT[15:12], {I1, I0}),
                          lut4_mux4 ( INIT[11:8], {I1, I0}),
                          lut4_mux4 ( INIT[7:4], {I1, I0}),
                          lut4_mux4 ( INIT[3:0], {I1, I0}) }, {I3, I2});
  end

  function lut4_mux4;
  input [3:0] d;
  input [1:0] s;
   
  begin

       if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
           
           lut4_mux4 = d[s];

         else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2])) 
           lut4_mux4 = d[0];
         else if ((s[1] == 0) && (d[0] === d[1]))
           lut4_mux4 = d[0];
         else if ((s[1] == 1) && (d[2] === d[3])) 
           lut4_mux4 = d[2];
         else if ((s[0] == 0) && (d[0] === d[2])) 
           lut4_mux4 = d[0];
         else if ((s[0] == 1) && (d[1] === d[3]))
           lut4_mux4 = d[1];
         else
           lut4_mux4 = 1'bx;
   end
  endfunction

endmodule
module OR4B1 (O, I0, I1, I2, I3);

    output O;

    input  I0, I1, I2, I3;

    wire i0_inv;

    not N0 (i0_inv, I0);
    or O1 (O, i0_inv, I1, I2, I3);


endmodule
module NAND3B2 (O, I0, I1, I2);

    output O;

    input  I0, I1, I2;

    wire i0_inv;
    wire i1_inv;

    not N1 (i1_inv, I1);
    not N0 (i0_inv, I0);
    nand A1 (O, i0_inv, i1_inv, I2);


endmodule
module clkdlle_maximum_period_check (clock, rst);
parameter clock_name = "";
parameter maximum_period = 0;
input clock;
input rst;

time clock_edge;
time clock_period;

initial begin
    clock_edge <= 0;
    clock_period <= 0;
end

always @(posedge clock) begin
    clock_edge <= $time;
    clock_period <= $time - clock_edge;
    if (clock_period > maximum_period && rst == 0) begin
	$display("Warning : Input clock period of, %1.3f ns, on the %s port of instance %m exceeds allotted value of %1.3f ns at simulation time %1.3f ns.", clock_period/1000.0, clock_name, maximum_period/1000.0, $time/1000.0);
    end
end
endmodule
module VCC(P);

    output P;

	assign P = 1'b1;

endmodule
module AND4B4 (O, I0, I1, I2, I3);

    output O;

    input  I0, I1, I2, I3;

    wire i0_inv;
    wire i1_inv;
    wire i2_inv;
    wire i3_inv;

    not N3 (i3_inv, I3);
    not N2 (i2_inv, I2);
    not N1 (i1_inv, I1);
    not N0 (i0_inv, I0);
    and A1 (O, i0_inv, i1_inv, i2_inv, i3_inv);


endmodule
module CAPTURE_FPGACORE (CAP, CLK);

    input  CAP, CLK;

    parameter ONESHOT = "FALSE";

endmodule
module NAND5B3 (O, I0, I1, I2, I3, I4);

    output O;

    input  I0, I1, I2, I3, I4;

    wire i0_inv;
    wire i1_inv;
    wire i2_inv;

    not N2 (i2_inv, I2);
    not N1 (i1_inv, I1);
    not N0 (i0_inv, I0);
    nand A1 (O, i0_inv, i1_inv, i2_inv, I3, I4);


endmodule
module ROM128X1 (O, A0, A1, A2, A3, A4, A5, A6);

    parameter INIT = 128'h00000000000000000000000000000000;

    output O;

    input  A0, A1, A2, A3, A4, A5, A6;

    reg [127:0] mem;

    initial 
            mem = INIT;

    assign O = mem[{A6, A5, A4, A3, A2, A1, A0}];


endmodule
module IBUFG_HSTL_IV_18 (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module CAPTURE_VIRTEX4 (CAP, CLK);

    input  CAP, CLK;

    parameter ONESHOT = "TRUE";
    
endmodule
module NAND5B2 (O, I0, I1, I2, I3, I4);

    output O;

    input  I0, I1, I2, I3, I4;

    wire i0_inv;
    wire i1_inv;

    not N1 (i1_inv, I1);
    not N0 (i0_inv, I0);
    nand A1 (O, i0_inv, i1_inv, I2, I3, I4);


endmodule
module NOR5B2 (O, I0, I1, I2, I3, I4);

    output O;

    input  I0, I1, I2, I3, I4;

    wire i0_inv;
    wire i1_inv;

    not N1 (i1_inv, I1);
    not N0 (i0_inv, I0);
    nor O1 (O, i0_inv, i1_inv, I2, I3, I4);


endmodule
module IBUFG_GTLP_DCI (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module ROM16X1 (O, A0, A1, A2, A3);

    parameter INIT = 16'h0000;

    output O;

    input  A0, A1, A2, A3;

    reg [15:0] mem;

    initial 
            mem = INIT;

    assign O = mem[{A3, A2, A1, A0}];


endmodule
module BUFGMUX_CTRL (O, I0, I1, S);

    output O;
    
    input  I0;
    input  I1;
    input  S;

    BUFGCTRL bufgctrl_inst (.O(O), .CE0(1'b1), .CE1(1'b1), .I0(I0), .I1(I1), .IGNORE0(1'b0), .IGNORE1(1'b0), .S0(~S), .S1(S));
    
    defparam bufgctrl_inst.INIT_OUT = 1'b0;
    defparam bufgctrl_inst.PRESELECT_I0 = "TRUE";
    defparam bufgctrl_inst.PRESELECT_I1 = "FALSE";
    
endmodule
module IBUFGDS_BLVDS_25 (O, I, IB);

    output O;

    input  I, IB;

    reg o_out;

    buf b_0 (O, o_out);

    always @(I or IB) begin
	if (I == 1'b1 && IB == 1'b0)
	    o_out <= I;
	else if (I == 1'b0 && IB == 1'b1)
	    o_out <= I;
    end


endmodule
module IBUFGDS_LVDS_33 (O, I, IB);

    output O;

    input  I, IB;

    reg o_out;

    buf b_0 (O, o_out);

    always @(I or IB) begin
	if (I == 1'b1 && IB == 1'b0)
	    o_out <= I;
	else if (I == 1'b0 && IB == 1'b1)
	    o_out <= I;
    end


endmodule
module IBUFG_PCIX (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module XORCY (O, CI, LI);

    output O;

    input  CI, LI;

	xor X1 (O, CI, LI);


endmodule
module IBUFDS_ULVDS_25 (O, I, IB);

    output O;

    input  I, IB;

    reg o_out;

    buf b_0 (O, o_out);

    always @(I or IB) begin
	if (I == 1'b1 && IB == 1'b0)
	    o_out <= I;
	else if (I == 1'b0 && IB == 1'b1)
	    o_out <= I;
        else if (I == 1'bx || IB == 1'bx)
            o_out <= 1'bx;
    end


endmodule
module IBUF_SSTL2_I_DCI (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module CFGLUT5 (CDO, O5, O6, CDI, CE, CLK, I0, I1, I2, I3, I4);

    parameter INIT = 32'h00000000;

    output CDO;
    output O5;
    output O6;

    input  I4, I3, I2, I1, I0;
    input  CDI, CE, CLK;

    reg  [31:0] data;


    assign  O6 = data[{I4, I3, I2, I1, I0}];
    assign  O5 = data[{I3, I2, I1, I0}];
    assign  CDO = data[31];

    initial
    begin
          assign  data = INIT;
          while (CLK === 1'b1 || CLK===1'bX) 
            #10; 
          deassign data;
    end

    always @(posedge CLK)
	if (CE == 1'b1) begin
	    data <= #100 {data[30:0], CDI};
        end


endmodule
module ROM32X1 (O, A0, A1, A2, A3, A4);

    parameter INIT = 32'h00000000;

    output O;

    input  A0, A1, A2, A3, A4;

    reg [31:0] mem;

    initial 
            mem = INIT;

    assign O = mem[{A4, A3, A2, A1, A0}];


endmodule
module MUXF8 (O, I0, I1, S);

    output O;
    reg    O;

    input  I0, I1, S;

	always @(I0 or I1 or S) 
            if (S)
		O = I1;
	    else
		O = I0;
endmodule
module IBUFG_HSTL_II (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module OR4B2 (O, I0, I1, I2, I3);

    output O;

    input  I0, I1, I2, I3;

    wire i0_inv;
    wire i1_inv;

    not N1 (i1_inv, I1);
    not N0 (i0_inv, I0);
    or O1 (O, i0_inv, i1_inv, I2, I3);


endmodule
module BSCAN_FPGACORE (CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE, TDO1, TDO2);

    input TDO1, TDO2;

    output CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE;

    pulldown (DRCK1);
    pulldown (DRCK2);
    pulldown (RESET);
    pulldown (SEL1);
    pulldown (SEL2);
    pulldown (SHIFT);
    pulldown (TDI);
    pulldown (UPDATE);


endmodule
module IBUFG_LVDCI_25 (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module SUSPEND_SYNC (
  SREQ,
  CLK,
  SACK
);

  output SREQ;

  input CLK;
  input SACK;

endmodule
module MUXF8_D (LO, O, I0, I1, S);

    output LO, O;
    reg    O, LO;

    input  I0, I1, S;

	always @(I0 or I1 or S)
            if (S) begin
		O = I1;
		LO = I1;
            end
	    else begin
		O = I0;
		LO = I0;
	    end
endmodule
module IBUF_SSTL2_II_DCI (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module RAM32X8S (O, A0, A1, A2, A3, A4, D, WCLK, WE);

    parameter INIT_00 = 32'h00000000;
    parameter INIT_01 = 32'h00000000;
    parameter INIT_02 = 32'h00000000;
    parameter INIT_03 = 32'h00000000;
    parameter INIT_04 = 32'h00000000;
    parameter INIT_05 = 32'h00000000;
    parameter INIT_06 = 32'h00000000;
    parameter INIT_07 = 32'h00000000;

    output [7:0] O;

    input  A0, A1, A2, A3, A4, WCLK, WE;
    input [7:0] D;

    reg   [7:0] mem [31:0];
    integer i;

    wire [4:0] adr;

    assign adr = {A4, A3, A2, A1, A0};
    assign O = mem[adr];

    initial 
        for (i = 0; i < 32; i=i+1)
            mem[i] = {INIT_07[i], INIT_06[i], INIT_05[i], INIT_04[i], INIT_03[i], INIT_02[i],
                      INIT_01[i], INIT_00[i]};

    always @(posedge WCLK) 
        if (WE == 1'b1) 
            mem[adr] <= #100 D;

endmodule
module IBUF_LVTTL (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module KEY_CLEAR (
	KEYCLEARB
);

input KEYCLEARB;

specify
	specparam PATHPULSE$ = 0;
endspecify

endmodule
module IBUFDS_LVPECL_33 (O, I, IB);

    output O;

    input  I, IB;

    reg o_out;

    buf b_0 (O, o_out);

    always @(I or IB) begin
	if (I == 1'b1 && IB == 1'b0)
	    o_out <= I;
	else if (I == 1'b0 && IB == 1'b1)
	    o_out <= I;
        else if (I == 1'bx || IB == 1'bx)
            o_out <= 1'bx;
    end


endmodule
module BUFCF (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module PULLUP (O);

    output O;

    wire A;

	pullup (A);
	buf (weak0,weak1) #(100,100) (O,A);

endmodule
module IBUFGDS_LVPECL_33 (O, I, IB);

    output O;

    input  I, IB;

    reg o_out;

    buf b_0 (O, o_out);

    always @(I or IB) begin
	if (I == 1'b1 && IB == 1'b0)
	    o_out <= I;
	else if (I == 1'b0 && IB == 1'b1)
	    o_out <= I;
    end


endmodule
module IBUFG_SSTL2_I (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module IBUF_CTT (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module BUFHCE (O, CE, I);

    parameter integer INIT_OUT = 0;

    output O;

    input  CE;
    input  I;

    wire   NCE, o_bufg_o, o_bufg1_o;
                                                                                  
    BUFGMUX B1 (.I0(I),
        .I1(1'b0),
        .O(o_bufg_o),
        .S(NCE));
                                                                                  
    INV I1 (.I(CE),
        .O(NCE));

    BUFGMUX_1 B2 (.I0(I),
        .I1(1'b1),
        .O(o_bufg1_o),
        .S(NCE));

    assign O = (INIT_OUT == 1) ? o_bufg1_o : o_bufg_o;

endmodule
module IBUF_SSTL18_I_DCI (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module LUT3 (O, I0, I1, I2);

    parameter INIT = 8'h00;

    input I0, I1, I2;

    output O;

    reg O;
    reg tmp;
  
    always @(  I2 or  I1 or  I0 )  begin
      tmp =  I0 ^ I1  ^ I2;
      if ( tmp == 0 || tmp == 1)
           O = INIT[{I2, I1, I0}];
      else
           O = lut3_mux4 ( {1'b0, 1'b0, lut3_mux4 (INIT[7:4], {I1, I0}),
                          lut3_mux4 (INIT[3:0], {I1, I0}) }, {1'b0, I2});
    end

  function lut3_mux4;
  input [3:0] d;
  input [1:0] s;

  begin
       if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
           lut3_mux4 = d[s];
         else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2]))
           lut3_mux4 = d[0];
         else if ((s[1] == 0) && (d[0] === d[1]))
           lut3_mux4 = d[0];
         else if ((s[1] == 1) && (d[2] === d[3]))
           lut3_mux4 = d[2];
         else if ((s[0] == 0) && (d[0] === d[2]))
           lut3_mux4 = d[0];
         else if ((s[0] == 1) && (d[1] === d[3]))
           lut3_mux4 = d[1];
         else
           lut3_mux4 = 1'bx;
   end
   endfunction

endmodule
module LUT1_D (LO, O, I0);

    parameter INIT = 2'h0;

    input I0;

    output LO, O;
    
    wire LO, O;

    assign O = (INIT[0] == INIT[1]) ? INIT[0] : INIT[I0];
    assign LO = O;

endmodule
module OFDDRCPE (Q, C0, C1, CE, CLR, D0, D1, PRE);

    output Q;

    input  C0, C1, CE, CLR, D0, D1, PRE;

    wire   q_out;

    FDDRCPE F0 (.C0(C0),
	.C1(C1),
	.CE(CE),
	.CLR(CLR),
	.D0(D0),
	.D1(D1),
	.PRE(PRE),
	.Q(q_out));
    defparam F0.INIT = 1'b0;

    OBUF O1 (.I(q_out),
	.O(Q));

endmodule
module LUT6_L (LO, I0, I1, I2, I3, I4, I5);

  parameter INIT = 64'h0000000000000000;

  input I0, I1, I2, I3, I4, I5;

  output LO;

  reg LO;
  reg tmp;

  always @( I5 or I4 or I3 or  I2 or  I1 or  I0 )  begin
 
    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4 ^ I5;

    if ( tmp == 0 || tmp == 1)

        LO = INIT[{I5, I4, I3, I2, I1, I0}];

    else 
    
      LO =  lut6_mux8 ( {lut6_mux8 ( INIT[63:56], {I2, I1, I0}),
                          lut6_mux8 ( INIT[55:48], {I2, I1, I0}),
                          lut6_mux8 ( INIT[47:40], {I2, I1, I0}),
                          lut6_mux8 ( INIT[39:32], {I2, I1, I0}),
                          lut6_mux8 ( INIT[31:24], {I2, I1, I0}),
                          lut6_mux8 ( INIT[23:16], {I2, I1, I0}),
                          lut6_mux8 ( INIT[15:8], {I2, I1, I0}),
                          lut6_mux8 ( INIT[7:0], {I2, I1, I0}) }, {I5, I4, I3});
  end

  function lut6_mux8;
  input [7:0] d;
  input [2:0] s;
   
  begin

   if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0))
           
       lut6_mux8 = d[s];

     else
       if ( ~(|d))
             lut6_mux8 = 1'b0;
       else if ((&d))
             lut6_mux8 = 1'b1;
       else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]==d[{1'b1,s[1:0]}]))
             lut6_mux8 = d[{1'b0,s[1:0]}];
       else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]==d[{s[2],1'b1,s[0]}]))
             lut6_mux8 = d[{s[2],1'b0,s[0]}];
       else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]==d[{s[2],s[1],1'b1}]))
             lut6_mux8 = d[{s[2],s[1],1'b0}];
       else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]==d[{1'b0,1'b1,s[0]}]) &&
          (d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b1,s[0]}]))
             lut6_mux8 = d[{1'b0,1'b0,s[0]}];
       else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]==d[{1'b0,s[1],1'b1}]) &&
          (d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b1}]))
             lut6_mux8 = d[{1'b0,s[1],1'b0}];
       else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b0,1'b1}]) &&
          (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b1}]))
             lut6_mux8 = d[{s[2],1'b0,1'b0}];
       else
             lut6_mux8 = 1'bx;
   end
  endfunction

endmodule
module CAPTURE_SPARTAN3A (CAP, CLK);

    input  CAP, CLK;
    
    parameter ONESHOT = "TRUE";

endmodule
module LUT5 (O, I0, I1, I2, I3, I4);

  parameter INIT = 32'h00000000;

  input I0, I1, I2, I3, I4;

  output O;

  reg O;
  reg tmp;

  always @( I4 or I3 or  I2 or  I1 or  I0 )  begin
 
    tmp =  I0 ^ I1  ^ I2 ^ I3 ^ I4;

    if ( tmp == 0 || tmp == 1)

        O = INIT[{I4, I3, I2, I1, I0}];

    else 
    
      O =  lut4_mux4 ( 
                        { lut6_mux8 ( INIT[31:24], {I2, I1, I0}),
                          lut6_mux8 ( INIT[23:16], {I2, I1, I0}),
                          lut6_mux8 ( INIT[15:8], {I2, I1, I0}),
                          lut6_mux8 ( INIT[7:0], {I2, I1, I0}) }, { I4, I3});
  end

  function lut6_mux8;
  input [7:0] d;
  input [2:0] s;
   
  begin

       if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0))
           
           lut6_mux8 = d[s];

         else
           if ( ~(|d))
                 lut6_mux8 = 1'b0;
           else if ((&d))
                 lut6_mux8 = 1'b1;
           else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]===d[{1'b1,s[1:0]}]))
                 lut6_mux8 = d[{1'b0,s[1:0]}];
           else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]===d[{s[2],1'b1,s[0]}]))
                 lut6_mux8 = d[{s[2],1'b0,s[0]}];
           else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]===d[{s[2],s[1],1'b1}]))
                 lut6_mux8 = d[{s[2],s[1],1'b0}];
           else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]===d[{1'b0,1'b1,s[0]}]) &&
              (d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b1,s[0]}]))
                 lut6_mux8 = d[{1'b0,1'b0,s[0]}];
           else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]===d[{1'b0,s[1],1'b1}]) &&
              (d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b1}]))
                 lut6_mux8 = d[{1'b0,s[1],1'b0}];
           else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b0,1'b1}]) &&
              (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b1}]))
                 lut6_mux8 = d[{s[2],1'b0,1'b0}];
           else
                 lut6_mux8 = 1'bx;
   end
  endfunction


  function lut4_mux4;
  input [3:0] d;
  input [1:0] s;
   
  begin

       if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))

           lut4_mux4 = d[s];

         else if ((d[0] === d[1]) && (d[2] === d[3])  && (d[0] === d[2]) )
           lut4_mux4 = d[0];
         else if ((s[1] == 0) && (d[0] === d[1]))
           lut4_mux4 = d[0];
         else if ((s[1] == 1) && (d[2] === d[3]))
           lut4_mux4 = d[2];
         else if ((s[0] == 0) && (d[0] === d[2]))
           lut4_mux4 = d[0];
         else if ((s[0] == 1) && (d[1] === d[3]))
           lut4_mux4 = d[1];
         else
           lut4_mux4 = 1'bx;

   end
  endfunction

endmodule
module IBUFG_HSTL_III_18 (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module MUXF6_L (LO, I0, I1, S);

    output LO;
    reg    LO;

    input  I0, I1, S;

	always @(I0 or I1 or S) 
	    if (S)
		LO = I1;
	    else
		LO = I0;
endmodule
module FRAME_ECC_VIRTEX5 (
	CRCERROR,
	ECCERROR,
	SYNDROME,
	SYNDROMEVALID
);

output CRCERROR;
output ECCERROR;
output SYNDROMEVALID;
output [11:0] SYNDROME;

specify
	specparam PATHPULSE$ = 0;
endspecify

endmodule
module RAM64X2S (O0, O1, A0, A1, A2, A3, A4, A5, D0, D1, WCLK, WE);

    parameter INIT_00 = 64'h0000000000000000;
    parameter INIT_01 = 64'h0000000000000000;

    output O0, O1;

    input  A0, A1, A2, A3, A4, A5, D0, D1, WCLK, WE;

    reg  [63:0] mem1;
    reg  [63:0] mem2;

    wire [5:0] adr;

    assign adr = {A5, A4, A3, A2, A1, A0};
    assign O0 = mem1[adr];
    assign O1 = mem2[adr];

    initial  begin
        mem1 = INIT_00;
        mem2 = INIT_01;
    end

    always @(posedge WCLK) 
        if (WE == 1'b1) begin
            mem1[adr] <= #100 D0;
            mem2[adr] <= #100 D1;
        end

endmodule
module CAPTURE_VIRTEX6 (
  CAP,
  CLK
);
  parameter ONESHOT = "TRUE";


  input CAP;
  input CLK;

endmodule
module RAM64X1D_1 (DPO, SPO, A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE);

    parameter INIT = 64'h0000000000000000;

    output DPO, SPO;

    input  A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE;

    reg  [63:0] mem;
    wire [5:0] adr;

    assign adr = {A5, A4, A3, A2, A1, A0};
    assign SPO = mem[adr];
    assign DPO = mem[{DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}];

    initial 
        mem = INIT;

    always @(negedge WCLK) 
        if (WE == 1'b1)
            mem[adr] <= #100 D;

endmodule
module IBUFGDS_ULVDS_25 (O, I, IB);

    output O;

    input  I, IB;

    reg o_out;

    buf b_0 (O, o_out);

    always @(I or IB) begin
	if (I == 1'b1 && IB == 1'b0)
	    o_out <= I;
	else if (I == 1'b0 && IB == 1'b1)
	    o_out <= I;
    end


endmodule
module OR3B2 (O, I0, I1, I2);

    output O;

    input  I0, I1, I2;

    wire i0_inv;
    wire i1_inv;

    not N1 (i1_inv, I1);
    not N0 (i0_inv, I0);
    or O1 (O, i0_inv, i1_inv, I2);


endmodule
module OFDDRTCPE (O, C0, C1, CE, CLR, D0, D1, PRE, T);

    output O;

    input  C0, C1, CE, CLR, D0, D1, PRE, T;

    wire   q_out;

    FDDRCPE F0 (.C0(C0),
	.C1(C1),
	.CE(CE),
	.CLR(CLR),
	.D0(D0),
	.D1(D1),
	.PRE(PRE),
	.Q(q_out));
    defparam F0.INIT = 1'b0;

    OBUFT O1 (.I(q_out),
	.T(T),
	.O(O));

endmodule
module AND4B2 (O, I0, I1, I2, I3);

    output O;

    input  I0, I1, I2, I3;

    wire i0_inv;
    wire i1_inv;

    not N1 (i1_inv, I1);
    not N0 (i0_inv, I0);
    and A1 (O, i0_inv, i1_inv, I2, I3);


endmodule
module BUF (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module IBUF_LVCMOS15 (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module LUT3_L (LO, I0, I1, I2);

    parameter INIT = 8'h00;

    input I0, I1, I2;

    output LO;
    reg LO;
    reg tmp;
  
    always @(  I2 or  I1 or  I0 )  begin
      tmp =  I0 ^ I1  ^ I2;
      if ( tmp == 0 || tmp == 1)
           LO = INIT[{I2, I1, I0}];
      else
           LO = lut3_mux4 ( {1'b0, 1'b0, lut3_mux4 (INIT[7:4], {I1, I0}),
                          lut3_mux4 (INIT[3:0], {I1, I0}) }, {1'b0, I2});
    end

  function lut3_mux4;
  input [3:0] d;
  input [1:0] s;

  begin
       if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
           lut3_mux4 = d[s];
         else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2]))
           lut3_mux4 = d[0];
         else if ((s[1] == 0) && (d[0] === d[1]))
           lut3_mux4 = d[0];
         else if ((s[1] == 1) && (d[2] === d[3]))
           lut3_mux4 = d[2];
         else if ((s[0] == 0) && (d[0] === d[2]))
           lut3_mux4 = d[0];
         else if ((s[0] == 1) && (d[1] === d[3]))
           lut3_mux4 = d[1];
         else
           lut3_mux4 = 1'bx;
   end
   endfunction

endmodule
module GT11CLK (
	SYNCLK1OUT,
	SYNCLK2OUT,
	MGTCLKN,
	MGTCLKP,
	REFCLK,
	RXBCLK,
	SYNCLK1IN,
	SYNCLK2IN
);

parameter REFCLKSEL = "MGTCLK";
parameter SYNCLK1OUTEN = "ENABLE";
parameter SYNCLK2OUTEN = "DISABLE";


output SYNCLK1OUT;
output SYNCLK2OUT;

input MGTCLKN;
input MGTCLKP;
input REFCLK;
input RXBCLK;
input SYNCLK1IN;
input SYNCLK2IN;

reg [0:0] SYNCLK1OUTEN_BINARY;
reg [0:0] SYNCLK2OUTEN_BINARY;
reg [3:0] REFCLKSEL_BINARY;

reg notifier;

reg mgtclk_out;
reg mux_out;	


initial begin
	case (REFCLKSEL)
		"MGTCLK" : REFCLKSEL_BINARY <= 4'b1111;
		"SYNCLK1IN" : REFCLKSEL_BINARY <= 4'b0010;
		"SYNCLK2IN" : REFCLKSEL_BINARY <= 4'b0100;
		"REFCLK" : REFCLKSEL_BINARY <= 4'b0110;
		"RXBCLK" : REFCLKSEL_BINARY <= 4'b0000;
		default : begin
			$display("Attribute Syntax Error : The Attribute REFCLKSEL on GT11CLK instance %m is set to %s.  Legal values for this attribute are MGTCLK, SYNCLK1IN, SYNCLK2IN, REFCLK or RXBCLK.", REFCLKSEL);
			$finish;
		end
	endcase

	case (SYNCLK1OUTEN)
		"ENABLE" : SYNCLK1OUTEN_BINARY <= 1'b1;
		"DISABLE" : SYNCLK1OUTEN_BINARY <= 1'b0;
		default : begin
			$display("Attribute Syntax Error : The Attribute SYNCLK1OUTEN on GT11CLK instance %m is set to %s.  Legal values for this attribute are ENABLE or DISABLE.", SYNCLK1OUTEN);
			$finish;
		end
	endcase

	case (SYNCLK2OUTEN)
		"ENABLE" : SYNCLK2OUTEN_BINARY <= 1'b1;
		"DISABLE" : SYNCLK2OUTEN_BINARY <= 1'b0;
		default : begin
			$display("Attribute Syntax Error : The Attribute SYNCLK2OUTEN on GT11CLK instance %m is set to %s.  Legal values for this attribute are ENABLE or DISABLE.", SYNCLK2OUTEN);
			$finish;
		end
	endcase

end

    always @(MGTCLKN or MGTCLKP) begin
	if (MGTCLKP == 1'b1 && MGTCLKN == 1'b0)
	    mgtclk_out <= MGTCLKP;
	else if (MGTCLKP == 1'b0 && MGTCLKN == 1'b1)
	    mgtclk_out <= MGTCLKP;	
    end

    always @(REFCLK) begin
    	if (REFCLKSEL == "REFCLK")
            mux_out <= REFCLK;
    end

    always @(mgtclk_out) begin
    	if (REFCLKSEL == "MGTCLK") 
      	    mux_out <= mgtclk_out;
    end

    always @(RXBCLK) begin
        if (REFCLKSEL == "RXBCLK")
            mux_out <= RXBCLK;
    end

    always @(SYNCLK1IN) begin
    	if (REFCLKSEL == "SYNCLK1IN") 
	    mux_out <= SYNCLK1IN;
    end

    always @(SYNCLK2IN) begin
    	if (REFCLKSEL == "SYNCLK2IN") 
	    mux_out <= SYNCLK2IN;
    end


  bufif1 (SYNCLK1OUT, mux_out, SYNCLK1OUTEN_BINARY);
  bufif1 (SYNCLK2OUT, mux_out, SYNCLK2OUTEN_BINARY);

endmodule
module IBUF_SSTL18_I (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module AND5B3 (O, I0, I1, I2, I3, I4);

    output O;

    input  I0, I1, I2, I3, I4;

    wire i0_inv;
    wire i1_inv;
    wire i2_inv;

    not N2 (i2_inv, I2);
    not N1 (i1_inv, I1);
    not N0 (i0_inv, I0);
    and A1 (O, i0_inv, i1_inv, i2_inv, I3, I4);


endmodule
module IBUF_HSTL_III_DCI (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module IBUFGDS_LVPECL_25 (O, I, IB);

    output O;

    input  I, IB;

    reg o_out;

    buf b_0 (O, o_out);

    always @(I or IB) begin
	if (I == 1'b1 && IB == 1'b0)
	    o_out <= I;
	else if (I == 1'b0 && IB == 1'b1)
	    o_out <= I;
    end


endmodule
module IBUF_SSTL2_I (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module IBUFGDS_LVDS_25_DCI (O, I, IB);

    output O;

    input  I, IB;

    reg o_out;

    buf b_0 (O, o_out);

    always @(I or IB) begin
	if (I == 1'b1 && IB == 1'b0)
	    o_out <= I;
	else if (I == 1'b0 && IB == 1'b1)
	    o_out <= I;
    end


endmodule
module IBUFDS (O, I, IB);

    parameter CAPACITANCE = "DONT_CARE";
    parameter DIFF_TERM = "FALSE";
    parameter IBUF_DELAY_VALUE = "0";
    parameter IBUF_LOW_PWR = "TRUE";
    parameter IFD_DELAY_VALUE = "AUTO";
    parameter IOSTANDARD = "DEFAULT";
   
    output O;
    input  I, IB;

    reg o_out;

    buf b_0 (O, o_out);

    initial begin
	
        case (CAPACITANCE)

            "LOW", "NORMAL", "DONT_CARE" : ;
            default : begin
                          $display("Attribute Syntax Error : The attribute CAPACITANCE on IBUFDS instance %m is set to %s.  Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
                          $finish;
                      end

        endcase

	case (DIFF_TERM)

            "TRUE", "FALSE" : ;
            default : begin
                          $display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFDS instance %m is set to %s.  Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
                          $finish;
                      end

	endcase // case(DIFF_TERM)


	case (IBUF_DELAY_VALUE)

            "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
            default : begin
                          $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUFDS instance %m is set to %s.  Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
                          $finish;
                      end

        endcase

        case (IBUF_LOW_PWR)

            "FALSE", "TRUE" : ;
            default : begin
                          $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s.  Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
                          $finish;
                      end

        endcase

	case (IFD_DELAY_VALUE)

            "AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ;
            default : begin
                          $display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IBUFDS instance %m is set to %s.  Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE);
                          $finish;
                      end

	endcase

    end

    always @(I or IB) 
	if (I == 1'b1 && IB == 1'b0)
	    o_out = I;
	else if (I == 1'b0 && IB == 1'b1)
	    o_out = I;
        else if (I == 1'bx || I == 1'bz || IB == 1'bx || IB == 1'bz)
            o_out = 1'bx;
    

endmodule
module IBUFG_LVDCI_DV2_18 (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module IBUFG_SSTL2_I_DCI (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module USR_ACCESS_VIRTEX5 (
        CFGCLK,
	DATA,
	DATAVALID
);

output CFGCLK;
output DATAVALID;
output [31:0] DATA;

specify
	specparam PATHPULSE$ = 0;
endspecify

endmodule
module IBUF_HSTL_IV_DCI (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module IBUF_PCIX66_3 (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module IBUFG_HSTL_II_DCI_18 (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module IBUF_LVDCI_DV2_15 (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module SRL16E (Q, A0, A1, A2, A3, CE, CLK, D);

    parameter INIT = 16'h0000;

    output Q;

    input  A0, A1, A2, A3, CE, CLK, D;

    reg  [15:0] data;


    assign Q = data[{A3, A2, A1, A0}];

    initial
    begin
          assign  data = INIT;
          while (CLK === 1'b1 || CLK===1'bX) 
            #10; 
          deassign data;
    end

    always @(posedge CLK)
    begin
	if (CE == 1'b1) begin
	    {data[15:0]} <= #100 {data[14:0], D};
	end
    end


endmodule
module LUT2_L (LO, I0, I1);

    parameter INIT = 4'h0;

    input I0, I1;

    output LO;

    reg  LO;
    wire [1:0] s;

    assign s = {I1, I0};

    always @(s)
       if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
           LO = INIT[s];
         else if ((INIT[0] == INIT[1]) && (INIT[2] == INIT[3]) && (INIT[0] == INIT[2])) 
           LO = INIT[0];
         else if ((s[1] == 0) && (INIT[0] == INIT[1]))
           LO = INIT[0];
         else if ((s[1] == 1) && (INIT[2] == INIT[3])) 
           LO = INIT[2];
         else if ((s[0] == 0) && (INIT[0] == INIT[2])) 
           LO = INIT[0];
         else if ((s[0] == 1) && (INIT[1] == INIT[3]))
           LO = INIT[1];
         else
           LO = 1'bx;

endmodule
module OR2 (O, I0, I1);

    output O;

    input  I0, I1;

    or O1 (O, I0, I1);


endmodule
module IBUFG_HSTL_IV_DCI_18 (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule
module CAPTURE_VIRTEX5 (
	CAP,
	CLK
);

input CAP;
input CLK;

parameter ONESHOT = "TRUE";

specify
	specparam PATHPULSE$ = 0;
endspecify

endmodule
module NAND4B1 (O, I0, I1, I2, I3);

    output O;

    input  I0, I1, I2, I3;

    wire i0_inv;

    not N0 (i0_inv, I0);
    nand A1 (O, i0_inv, I1, I2, I3);


endmodule
module IBUFG_LVDCI_18 (O, I);

    output O;

    input  I;

	buf B1 (O, I);


endmodule