dakies/OSS_Verilog huggingface dataset:
module spi_shift #(
  parameter SPI_CHAR_LEN_BITS = 10
)(

  input                           clk,          // system clock
  input                           rst,          // reset
  input       [31:0]              len,          // data len in bits (minus one)
  input                           lsb,          // lbs first on the line
  input                           go,           // start stansfer
  input                           pos_edge,     // recognize posedge of sclk
  input                           neg_edge,     // recognize negedge of sclk
  input                           rx_negedge,   // s_in is sampled on negative edge
  input                           tx_negedge,   // s_out is driven on negative edge
  output  reg                     tip,          // transfer in progress
  output                          last,         // last bit
  input                           s_clk,        // serial clock
  input                           s_in,         // serial in
  output  reg                     s_out,        // serial out
  output  reg [SPI_MAX_CHAR-1:0]  miso_data,    // parallel out
  input       [SPI_MAX_CHAR-1:0]  mosi_data     // parallel out
);

localparam  SPI_MAX_CHAR        = 2 ** SPI_CHAR_LEN_BITS;


//Local Parameters

//Registers/Wires
reg     [31:0]                  cnt;          // data bit count
reg     [SPI_MAX_CHAR-1:0]      data;         // shift register
wire                            rx_clk;       // rx clock enable
wire                            tx_clk;       // tx clock enable


//Submodules

//Asynchronous Logic
assign last = !(|cnt);

assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;

//Synchronous Logic

// Character bit counter
always @(posedge clk) begin
  if(rst) begin
    cnt <=  0;
  end
  else begin
    if(tip) begin
      cnt <=  pos_edge ? (cnt - 1) : cnt;
    end
    else begin
      //if len is zero then we put in the max
      //else put in the number specified
      cnt <=  !(|len) ? {1'b1, {SPI_CHAR_LEN_BITS{1'b0}}} : len;
    end
  end
end

// Transfer in progress
always @(posedge clk) begin
  if(rst) begin
    tip <=  1'b0;
  end
  else begin
    if(go && ~tip) begin
      tip <=  1'b1;
    end
    else if(tip && last && pos_edge) begin
      tip <=  1'b0;
    end
  end
end

// Sending bits to the line
always @(posedge clk) begin
  if (rst) begin
    s_out   <=  1'b0;
    data    <=  0;
  end
  else begin
    if (tx_clk && tip) begin
      if (!lsb) begin
        s_out         <=  data[(SPI_MAX_CHAR - 1)];
        data     <=  {data[(SPI_MAX_CHAR - 2):0], 1'b1};
      end
      else begin
        s_out         <=  data[0];
        data     <=  {1'b1, data[(SPI_MAX_CHAR - 1):1]};
      end
    end
    if (!tip) begin
      data            <=  mosi_data;
    end
  end
end

// Receiving bits from the line
always @(posedge clk) begin
  if (rst) begin
    miso_data     <=  0;
  end
  else begin
    if (rx_clk) begin
      //Clock data in on the receive clock
      miso_data <=  {miso_data[(SPI_MAX_CHAR - 2):0], s_in};
    end
  end
end

endmodule
module spi_clkgen (

  input                           clk_in,   // input clock (system clock)
  input                           rst,      // reset
  input                           enable,   // clock enable
  input                           go,       // start transfer
  input                           last_clk, // last clock
  input     [31:0]                divider,  // clock divider (output clock is divided by this value)
  output  reg                     clk_out,  // output clock
  output  reg                     pos_edge, // pulse marking positive edge of clk_out
  output  reg                     neg_edge  // pulse marking negative edge of clk_out
);


//Local Parameters
//Registers/Wires
reg       [311:0]               cnt;      // clock counter
wire                            cnt_zero; // conter is equal to zero
wire                            cnt_one;  // conter is equal to one


//Submodules
//Asynchronous Logic
assign cnt_zero         = (cnt == 32'h0);
assign cnt_one          = (cnt == 32'h00000001);

//Synchronous Logic
// Counter counts half period
always @(posedge clk_in or posedge rst)
begin
  if(rst) begin
    cnt <= 32'h00000001;
  end
  else begin
    if(!enable || cnt_zero) begin
      cnt <= divider;
    end
    else begin
      cnt <=  cnt - 32'h00000001;
    end
  end
end

// clk_out is asserted every other half period
always @(posedge clk_in or posedge rst)
begin
  if(rst) begin
    clk_out <=  1'b0;
  end
  else begin
    clk_out <=  (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
  end
end

// Pos and neg edge signals
always @(posedge clk_in or posedge rst)
begin
  if(rst) begin
    pos_edge  <=  1'b0;
    neg_edge  <=  1'b0;
  end
  else begin
    pos_edge  <=  (enable && !clk_out && cnt_one) || (!(|divider) &&  clk_out) || (!(|divider) && go && !enable);
    neg_edge  <=  (enable &&  clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
  end
end

endmodule
module nh_lcd_command (
  input               rst,
  input               clk,

  output      [31:0]  debug,

  //Control Signals
  input               i_cmd_write_stb,
  input               i_cmd_read_stb,
  input       [7:0]   i_cmd_data,
  output  reg [7:0]   o_cmd_data,
  input               i_enable,
  input               i_cmd_parameter,
  output  reg         o_cmd_finished,

  //Physical Signals
  output              o_cmd_mode,
  output  reg         o_write,
  output  reg         o_read,
  output  reg [7:0]   o_data_out,
  input       [7:0]   i_data_in,
  output  reg         o_data_out_en
);

//Local Parameters
localparam  IDLE      = 4'h0;
localparam  FINISHED  = 4'h1;

//Registers/Wires
reg           [3:0]   state;
//Submodules
//Asynchronous Logic
assign  o_cmd_mode    = i_cmd_parameter;

//Synchronous Logic
always @ (posedge clk) begin
  if (rst) begin
    state                   <=  IDLE;
    o_data_out_en           <=  0;
    o_data_out              <=  0;
    o_cmd_finished          <=  0;
    o_cmd_data              <=  0;

    o_write                 <=  0;
    o_read                  <=  0;
  end
  else begin
    //Strobes
    o_cmd_finished          <=  0;

    //State Machine
    case (state)
      IDLE: begin
        o_write             <=  0;
        o_read              <=  0;

        o_data_out_en      <=  0;
        if (i_cmd_write_stb) begin
          //Change the bus to an output
          o_data_out_en    <=  1;
          //Put the data on the bus
          o_data_out        <=  i_cmd_data;
          o_write           <=  1;
          state             <=  FINISHED;
        end
        else if (i_cmd_read_stb) begin
          //Change the bus to an input
          o_data_out_en    <=  0;
          o_read            <=  1;
          state             <=  FINISHED;
        end
      end
      FINISHED: begin
        o_write             <=  0;
        o_read              <=  0;
        if (!o_data_out_en) begin
          //XXX: The appliction note doesn't describe how to explicitly read
          //and the protocol is different from the 8080 MCU interface
          o_cmd_data        <=  i_data_in;
        end
        o_cmd_finished      <=  1;
        state               <=  IDLE;
      end
    endcase
  end
end

endmodule
module ppfifo_data_generator (
  input               clk,
  input               rst,
  input               i_enable,

  //Ping Pong FIFO Interface
  input       [1:0]   i_wr_rdy,
  output  reg [1:0]   o_wr_act,
  input       [23:0]  i_wr_size,
  output  reg         o_wr_stb,
  output  reg [31:0]  o_wr_data
);

//Local Parameters
//Registers/Wires
reg   [23:0]          r_count;
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
  if (rst) begin
    o_wr_act        <=  0;
    o_wr_stb        <=  0;
    o_wr_data       <=  0;
    r_count         <=  0;
  end
  else begin
    //Reset strobe signals
    o_wr_stb        <= 0;
    if (i_enable) begin
      if ((i_wr_rdy > 0) && (o_wr_act == 0))begin
        r_count     <=  0;
        if (i_wr_rdy[0]) begin
          //Channel 0 is open
          o_wr_act[0]  <=  1;
        end
        else begin
          //Channel 1 is open
          o_wr_act[1]  <=  1;
        end
      end
      else if (o_wr_act > 0) begin
        if (r_count < i_wr_size) begin
          //More room left in the buffer
          r_count   <=  r_count + 1;
          o_wr_stb  <=  1;
          //put the count in the data
          o_wr_data <=  r_count;
        end
        else begin
          //Filled up the buffer, release it
          o_wr_act  <=  0;
        end
      end
    end
  end
end

endmodule
module seeed_tft_command (
  input               rst,
  input               clk,

  output      [31:0]  debug,

  //Control Signals
  input               i_cmd_write_stb,
  input               i_cmd_read_stb,
  input       [7:0]   i_cmd_data,
  output  reg [7:0]   o_cmd_data,
  input               i_enable,
  input               i_cmd_rs,
  output  reg         o_cmd_finished,

  //Physical Signals
  output              o_cmd_mode,
  output  reg         o_write,
  output  reg         o_read,
  output  reg [7:0]   o_data_out,
  input       [7:0]   i_data_in,
  output  reg         o_data_out_en
);

//Local Parameters
localparam  IDLE      = 4'h0;
localparam  DELAY     = 4'h1;
localparam  FINISHED  = 4'h2;

//Registers/Wires
reg           [3:0]   state;
reg           [7:0]   count;
//Submodules
//Asynchronous Logic
assign  o_cmd_mode    = i_cmd_rs;

//Synchronous Logic
always @ (posedge clk) begin
  if (rst) begin
    state                   <=  IDLE;
    o_data_out_en           <=  0;
    o_data_out              <=  0;
    o_cmd_finished          <=  0;
    o_cmd_data              <=  0;

    o_write                 <=  0;
    o_read                  <=  0;
    count                   <=  0;
  end
  else begin
    //Strobes
    o_cmd_finished          <=  0;
    if (count < `DELAY_COUNT) begin
        count               <= count + 1;
    end

    //State Machine
    case (state)
      IDLE: begin
        o_write             <=  0;
        o_read              <=  0;
        count               <=  `DELAY_COUNT;

        o_data_out_en      <=  0;
        if (i_cmd_write_stb) begin
          //Change the bus to an output
          o_data_out_en    <=  1;
          //Put the data on the bus
          o_data_out        <=  i_cmd_data;
          o_write           <=  1;
          state             <=  DELAY;
          count             <=  0;
        end
        else if (i_cmd_read_stb) begin
          //Change the bus to an input
          o_data_out_en     <=  0;
          o_read            <=  1;
          state             <=  DELAY;
          count             <=  0;
        end
      end
      DELAY: begin
        if (count >= `DELAY_COUNT) begin
            state           <=  FINISHED;
        end
      end
      FINISHED: begin
        o_write             <=  0;
        o_read              <=  0;
        if (!o_data_out_en) begin
          //XXX: The appliction note doesn't describe how to explicitly read
          //and the protocol is different from the 8080 MCU interface
          o_cmd_data        <=  i_data_in;
        end
        o_cmd_finished      <=  1;
        state               <=  IDLE;
      end
    endcase
  end
end

endmodule
module i2s_reader_phy (
  input               rst,
  /*This signal is connected to the i2s clock (driven either internally or
  externally)*/
  input               clk,

  output      [31:0]  debug,
  input               i_enable,
  input       [23:0]  i_min_read_size,

  //memory interface
  input       [23:0]  i_wfifo_size,
  input       [1:0]   i_wfifo_ready,
  output  reg [1:0]   o_wfifo_activate  = 2'b0,
  output  reg         o_wfifo_strobe    = 1'b0,
  output  reg [31:0]  o_wfifo_data      = 32'h0,

  //These signals are connected to the phy signals
  input               i_i2s_lr,
  input               i_i2s_data
);

//Local Parameters
localparam            IDLE          = 4'h0;
localparam            READ          = 4'h1;

//Registers/Wires
reg           [3:0]   state         = IDLE;
reg           [31:0]  read_word     = 32'h0;
reg           [23:0]  r_count       = 24'h0;
reg                   r_prev_i2s_lr = 1'b0;

//Submodules

//Asynchronous Logic
assign  debug[0]      = i_i2s_lr;
assign  debug[1]      = i_i2s_data;
assign  debug[2]      = i_enable;
assign  debug[4:3]    = i_wfifo_ready;
assign  debug[6:5]    = o_wfifo_activate;
assign  debug[7]      = o_wfifo_strobe;
assign  debug[11:8]   = state;

//Synchronous Logic
always @ (posedge clk) begin
  if (rst) begin
    state                     <=  IDLE;
    o_wfifo_activate          <=  2'b0;
    o_wfifo_strobe            <=  1'b0;
    o_wfifo_data              <=  32'h0;
    r_count                   <=  0;
    r_prev_i2s_lr             <=  0;
  end
  else begin
    o_wfifo_strobe            <=  0;
    if ((state == READ) && ((i_wfifo_ready > 0) && (o_wfifo_activate == 0))) begin
      r_count                 <=  0;
      if (i_wfifo_ready[0]) begin
        o_wfifo_activate[0]   <=  1;
      end                     
      else begin              
        o_wfifo_activate[1]   <=  1;
      end                     
    end                       
    case (state)              
      IDLE: begin             
        if (i_enable) begin  
          state               <=  READ;
          o_wfifo_activate    <=  0;
        end
      end
      READ: begin
        if (!i_enable) begin
          state               <=  IDLE;
        end
        else begin
          if (r_count < i_wfifo_size) begin
            if (i_i2s_lr != r_prev_i2s_lr) begin
              //A word is ready to write to memory
              o_wfifo_data    <=  {r_prev_i2s_lr, 7'h0, read_word[23:0]};
              o_wfifo_strobe  <=  1;
              r_count         <=  r_count + 1;
            end
          end
          else begin
            o_wfifo_activate  <=  0;
          end
          read_word           <=  {read_word[30:0] << 1, i_i2s_data};
        end
      end
      default: begin
        state                 <=  IDLE;
      end
    endcase
  end
  r_prev_i2s_lr               <=  i_i2s_lr;
end

endmodule
module sim_interface (
  //boilerplate
  input               rst,
  input               clk,

  //Sim Interface

  output              o_sim_master_ready,
  input               i_sim_in_reset,
  input               i_sim_in_ready,

  input   [31:0]      i_sim_in_command,
  input   [31:0]      i_sim_in_address,
  input   [31:0]      i_sim_in_data,
  input   [31:0]      i_sim_in_data_count,

  input               i_sim_out_ready,
  output              o_sim_out_en,

  output  [31:0]      o_sim_out_status,
  output  [31:0]      o_sim_out_address,
  output  [31:0]      o_sim_out_data,
  output  [27:0]      o_sim_out_data_count,


  //master interface
  input               i_master_ready,
  output  reg         o_ih_reset,
  output  reg         o_ih_ready,

  output  reg [31:0]  o_in_command,
  output  reg [31:0]  o_in_address,
  output  reg [31:0]  o_in_data,
  output  reg [27:0]  o_in_data_count,

  output  reg         o_oh_ready,
  input               i_oh_en,

  input   [31:0]      i_out_status,
  input   [31:0]      i_out_address,
  input   [31:0]      i_out_data,
  input   [27:0]      i_out_data_count
);

//Local Parameters
//Registers/Wires
//Submodules
//Asynchronous Logic
assign  o_sim_master_ready    = i_master_ready;
assign  o_sim_out_en          = i_oh_en;
assign  o_sim_out_status      = i_out_status;
assign  o_sim_out_address     = i_out_address;
assign  o_sim_out_data        = i_out_data;
assign  o_sim_out_data_count  = i_out_data_count;



//Synchronous Logic
always @ (i_sim_in_reset) begin
    o_ih_reset            = i_sim_in_reset;
end
always @ (i_sim_in_ready) begin
    o_ih_ready            =  i_sim_in_ready;
end
always @ (i_sim_in_command) begin
    o_in_command          = i_sim_in_command;
end
always @ (i_sim_in_address) begin
    o_in_address          = i_sim_in_address;
end
always @ (i_sim_in_data) begin
    o_in_data             = i_sim_in_data;
end
always @ (i_sim_in_data_count) begin
    o_in_data_count       = i_sim_in_data_count;
end
always @ (i_sim_out_ready) begin
    o_oh_ready            = i_sim_out_ready;
end

endmodule
module pf_hi_tester (
  input               clk,
  input               rst,

  //Add signals to control your device here

  //Wishbone Bus Signals
  input               i_wbs_we,
  input               i_wbs_cyc,
  input       [3:0]   i_wbs_sel,
  input       [31:0]  i_wbs_dat,
  input               i_wbs_stb,
  output  reg         o_wbs_ack,
  output  reg [31:0]  o_wbs_dat,
  input       [31:0]  i_wbs_adr,

  //This interrupt can be controlled from this module or a submodule
  output  reg         o_wbs_int
  //output              o_wbs_int
);

//Local Parameters
localparam     ADDR_0  = 32'h00000000;
localparam     ADDR_1  = 32'h00000001;
localparam     ADDR_2  = 32'h00000002;

//Local Registers/Wires
//Submodules
//Asynchronous Logic
//Synchronous Logic

always @ (posedge clk) begin
  if (rst) begin
    o_wbs_dat <= 32'h0;
    o_wbs_ack <= 0;
    o_wbs_int <= 0;
  end

  else begin
    //when the master acks our ack, then put our ack down
    if (o_wbs_ack && ~i_wbs_stb)begin
      o_wbs_ack <= 0;
    end

    if (i_wbs_stb && i_wbs_cyc) begin
      //master is requesting somethign
      if (!o_wbs_ack) begin
        if (i_wbs_we) begin
          //write request
          case (i_wbs_adr)
            24'h0000FF: begin
              o_wbs_int     <=  0;
            end
            24'h001000: begin
              o_wbs_int     <=  i_wbs_dat[0];
            end
            default: begin
            end
          endcase
        end
        else begin
          //read request
          o_wbs_dat <=  i_wbs_adr;
        end
      o_wbs_ack <= 1;
    end
    end
  end
end

endmodule
module tb_cocotb #(
  parameter ADDR_WIDTH          = 32,
  parameter DATA_WIDTH          = 32,
  parameter STROBE_WIDTH        = (DATA_WIDTH / 8)
)(

input                               clk,
input                               rst,

//Write Address Channel
input                               AXIML_AWVALID,
input       [ADDR_WIDTH - 1: 0]     AXIML_AWADDR,
output                              AXIML_AWREADY,

//Write Data Channel
input                               AXIML_WVALID,
output                              AXIML_WREADY,
input       [STROBE_WIDTH - 1:0]    AXIML_WSTRB,
input       [DATA_WIDTH - 1: 0]     AXIML_WDATA,

//Write Response Channel
output                              AXIML_BVALID,
input                               AXIML_BREADY,
output      [1:0]                   AXIML_BRESP,

//Read Address Channel
input                               AXIML_ARVALID,
output                              AXIML_ARREADY,
input       [ADDR_WIDTH - 1: 0]     AXIML_ARADDR,

//Read Data Channel
output                              AXIML_RVALID,
input                               AXIML_RREADY,
output      [1:0]                   AXIML_RRESP,
output      [DATA_WIDTH - 1: 0]     AXIML_RDATA

);


//Parameters
//Registers

reg               r_rst;
always @ (*)      r_rst           = rst;
reg   [3:0]       test_id         = 0;

//submodules

axi_lite_demo #(
  .ADDR_WIDTH       (ADDR_WIDTH     ),
  .DATA_WIDTH       (DATA_WIDTH     ),
  .INVERT_AXI_RESET (0              )
) dut (
  .clk              (clk            ),
  .rst              (r_rst          ),
                               
                               
  .i_awvalid        (AXIML_AWVALID  ),
  .i_awaddr         (AXIML_AWADDR   ),
  .o_awready        (AXIML_AWREADY  ),
                               
                               
  .i_wvalid         (AXIML_WVALID   ),
  .o_wready         (AXIML_WREADY   ),
  .i_wdata          (AXIML_WDATA    ),
                               
                               
  .o_bvalid         (AXIML_BVALID   ),
  .i_bready         (AXIML_BREADY   ),
  .o_bresp          (AXIML_BRESP    ),
                               
                               
  .i_arvalid        (AXIML_ARVALID  ),
  .o_arready        (AXIML_ARREADY  ),
  .i_araddr         (AXIML_ARADDR   ),
                               
                               
  .o_rvalid         (AXIML_RVALID   ),
  .i_rready         (AXIML_RREADY   ),
  .o_rresp          (AXIML_RRESP    ),
  .o_rdata          (AXIML_RDATA    )

);


//asynchronus logic
//synchronous logic

initial begin
  $dumpfile ("design.vcd");
  $dumpvars(0, tb_cocotb);
end


endmodule
module adapter_rgb_2_ppfifo #(
  parameter                 DATA_WIDTH = 24
)(
  input                             clk,
  input                             rst,

  input         [23:0]              i_rgb,
  input                             i_h_sync,
  input                             i_h_blank,
  input                             i_v_sync,
  input                             i_v_blank,
  input                             i_data_en,

  //Ping Pong FIFO Write Controller
  output                            o_ppfifo_clk,
  input       [1:0]                 i_ppfifo_rdy,
  output  reg [1:0]                 o_ppfifo_act,
  input       [23:0]                i_ppfifo_size,
  output  reg                       o_ppfifo_stb,
  output  reg [DATA_WIDTH - 1:0]    o_ppfifo_data


);
//local parameters
localparam      IDLE        = 0;
localparam      READY       = 1;
localparam      RELEASE     = 2;

//registes/wires

reg           [23:0]        r_count;
reg           [2:0]         state;
//submodules
//asynchronous logic
assign  o_ppfifo_clk    = clk;
//synchronous logic
always @ (posedge clk) begin
  o_ppfifo_stb          <=  0;
  if (rst) begin
    r_count             <=  0;
    o_ppfifo_act        <=  0;
    o_ppfifo_data       <=  0;
    state               <=  IDLE;
  end
  else begin
    case (state)
      IDLE: begin
        o_ppfifo_act    <=  0;
        if ((i_ppfifo_rdy > 0) && (o_ppfifo_act == 0)) begin
          r_count           <=  0;
          if (i_ppfifo_rdy[0]) begin
            o_ppfifo_act[0] <=  1;
          end
          else begin
            o_ppfifo_act[1] <=  1;
          end
          state             <=  READY;
        end
      end
      READY: begin
        if (r_count < i_ppfifo_size) begin
          if (!i_h_blank) begin
            o_ppfifo_stb    <=  1;
            o_ppfifo_data   <=  i_rgb;

            r_count         <=  r_count + 1;
          end
        end
        //Conditions to release the FIFO or stop a transaction
        else begin
          state             <=  RELEASE;
        end
        if (r_count > 0 && i_h_blank) begin
          state             <=  RELEASE;
        end
      end
      RELEASE: begin
        o_ppfifo_act        <=  0;
        state               <=  IDLE;
      end
      default: begin
      end
    endcase
  end
end



endmodule
module nh_lcd_command (
  input               rst,
  input               clk,

  output      [31:0]  debug,

  //Control Signals
  input               i_cmd_write_stb,
  input               i_cmd_read_stb,
  input       [7:0]   i_cmd_data,
  output  reg [7:0]   o_cmd_data,
  input               i_enable,
  input               i_cmd_parameter,
  output  reg         o_cmd_finished,

  //Physical Signals
  output              o_cmd_mode,
  output  reg         o_write,
  output  reg         o_read,
  output  reg [7:0]   o_data_out,
  input       [7:0]   i_data_in,
  output  reg         o_data_out_en
);

//Local Parameters
localparam  IDLE      = 4'h0;
localparam  READ_WAIT = 4'h1;
localparam  FINISHED  = 4'h2;

//Registers/Wires
reg           [3:0]   state;
//Submodules
//Asynchronous Logic
assign  o_cmd_mode    = i_cmd_parameter;

//Synchronous Logic
always @ (posedge clk) begin
  if (rst) begin
    state                   <=  IDLE;
    o_data_out_en           <=  0;
    o_data_out              <=  0;
    o_cmd_finished          <=  0;
    o_cmd_data              <=  0;

    o_write                 <=  0;
    o_read                  <=  0;
  end
  else begin
    //Strobes
    o_cmd_finished          <=  0;

    //State Machine
    case (state)
      IDLE: begin
        o_write             <=  0;
        o_read              <=  0;

        o_data_out_en       <=  0;
        if (i_cmd_write_stb) begin
          //Change the bus to an output
          o_data_out_en     <=  1;
          //Put the data on the bus
          o_data_out        <=  i_cmd_data;
          o_write           <=  1;
          state             <=  FINISHED;
        end
        else if (i_cmd_read_stb) begin
          //Change the bus to an input
          o_data_out_en     <=  0;
          o_read            <=  1;
          state             <=  READ_WAIT;
        end
      end
      READ_WAIT: begin
        state               <=  FINISHED;
      end
      FINISHED: begin
        o_write             <=  0;
        o_read              <=  0;
        if (!o_data_out_en) begin
          //XXX: The appliction note doesn't describe how to explicitly read
          //and the protocol is different from the 8080 MCU interface
          o_cmd_data        <=  i_data_in;
        end
        o_cmd_finished      <=  1;
        state               <=  IDLE;
      end
    endcase
  end
end

endmodule
module pixel_reader (
  input                     clk,
  input                     rst,

  //FIFO interface
  input                     i_read_rdy,
  output  reg               o_read_act,
  input           [23:0]    i_read_size,
  input           [24:0]    i_read_data,
  output  reg               o_read_stb,

  //Output Pixels
  output  reg     [7:0]     o_red,
  output  reg     [7:0]     o_green,
  output  reg     [7:0]     o_blue,

  output  reg               o_pixel_rdy,
  input                     i_pixel_stb,

  //Test Generator
  input                     i_tp_red,
  input                     i_tp_blue,
  input                     i_tp_green,

  output  reg               o_last
);
//local parameters
//registes/wires

reg               [7:0]     r_next_red;
reg               [7:0]     r_next_green;
reg               [7:0]     r_next_blue;
reg               [31:0]    r_read_count;
reg                         r_tp_green;
reg                         r_tp_blue;
//submodules
//asynchronous logic
//synchronous logic

always @ (posedge clk) begin
  o_read_stb                <=  0;
  o_pixel_rdy               <=  0;
  if (rst) begin
    o_read_act              <=  0;

    o_red                   <=  0;
    o_green                 <=  0;
    o_blue                  <=  0;

    r_next_red              <=  0;
    r_next_green            <=  0;
    r_next_blue             <=  0;

    o_last                  <=  0;
  end
  else begin

    //If a FIFO is available activate it
    if (i_read_rdy && !o_read_act) begin
      r_read_count              <=  0;
      o_read_act                <=  1;
    end

    if (o_pixel_rdy) begin
      if (i_pixel_stb) begin
        o_pixel_rdy             <=  0;
        o_red                   <=  i_read_data[23:16];
        o_green                 <=  i_read_data[15:8];
        o_blue                  <=  i_read_data[7:0];
        o_last                  <=  i_read_data[24];
      end
    end

    if (o_read_act) begin
      o_pixel_rdy               <=  1;
      if (r_read_count < i_read_size) begin
        if (i_pixel_stb) begin
          r_read_count          <=  r_read_count + 1;
          o_read_stb            <=  1;
        end
      end
      else begin
        o_read_act              <=  0;
      end
    end
  end
end



endmodule
module image_to_ppfifo #(
    parameter BUFFER_SIZE = 9
)(
input               clk,
input               rst,

input               axis_clk,
input               w_axis_rst,

input               i_enable,

input               i_video_hsync,
input               i_sof_stb,
input       [2:0]   i_red,
input       [2:0]   i_green,
input       [1:0]   i_blue,

//Memory FIFO Interface
output              o_rfifo_ready,
input               i_rfifo_activate,
input               i_rfifo_strobe,
output      [24:0]  o_rfifo_data,
output      [23:0]  o_rfifo_size
);

//Local Parameters
//Registers/Wires
wire                w_write_ready;
reg                 r_write_activate;
wire  [23:0]        w_write_fifo_size;
reg                 r_write_stb;
reg   [24:0]        r_write_data;

//Submodules
block_fifo #(
  .DATA_WIDTH       (25                 ),
  .ADDRESS_WIDTH    (BUFFER_SIZE        )
) bf (
  .reset            (rst | w_axis_rst   ),

  //write side
  .write_clock      (clk                ),
  .write_ready      (w_write_ready      ),
  .write_activate   (w_write_activate   ),
  .write_fifo_size  (w_write_fifo_size  ),
  .write_strobe     (r_write_stb        ),
  .write_data       (r_write_data       ),

  //read size
  .read_clock       (axis_clk           ),
  .read_strobe      (i_rfifo_strobe     ),
  .read_ready       (o_rfifo_ready      ),
  .read_activate    (i_rfifo_activate   ),
  .read_count       (o_rfifo_size       ),
  .read_data        (o_rfifo_data       )
);

//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
  r_write_stb                       <=  0;
  if (rst) begin
    r_write_activate                <=  0;
    r_write_stb                     <=  0;
    r_write_data                    <=  0;
  end
  else begin
    if (i_enable && !r_write_activate && w_write_ready) begin
      r_write_activate              <=  1;
    end
    if (r_write_activate) begin
      if (i_video_hsync) begin
        r_write_data                <=  {i_sof_stb, i_red, i_green, i_blue};
        r_write_stb                 <=  1;
      end
      else begin
        r_write_activate            <=  0;
      end
    end
  end
end
endmodule
module tb_cocotb #(
  parameter ADDR_WIDTH          = 32,
  parameter DATA_WIDTH          = 32,
  parameter STROBE_WIDTH        = (DATA_WIDTH / 8)
)(

input                               clk,
input                               rst,

//Write Address Channel
input                               AXIMS_TVALID,
input       [ADDR_WIDTH - 1: 0]     AXIMS_TDATA,
output                              AXIMS_TREADY,

input                               AXIMS_TLAST,
input       [STROBE_WIDTH - 1: 0]   AXIMS_TKEEP,
input       [STROBE_WIDTH - 1: 0]   AXIMS_TSTRB,
input       [3:0]                   AXIMS_TID,
input       [31:0]                  AXIMS_TDEST,
input       [3:0]                   AXIMS_TUSER
);


//Parameters
//Registers

reg               r_rst;
always @ (*)      r_rst           = rst;

//submodules

axi_stream_ingress_demo #(
  .ADDR_WIDTH   (ADDR_WIDTH     ),
  .DATA_WIDTH   (DATA_WIDTH     )
) dut (
  .clk          (clk            ),
  .rst          (r_rst          ),


  .i_tvalid     (AXIMS_TVALID   ),
  .i_tdata      (AXIMS_TDATA    ),
  .o_tready     (AXIMS_TREADY   ),

  .i_tlast      (AXIMS_TLAST    ),
  .i_tkeep      (AXIMS_TKEEP    ),
  .i_tstrb      (AXIMS_TSTRB    ),
  .i_tid        (AXIMS_TID      ),
  .i_tdest      (AXIMS_TDEST    ),
  .i_tuser      (AXIMS_TUSER    )
);


//asynchronus logic
//synchronous logic

initial begin
  $dumpfile ("design.vcd");
  $dumpvars(0, tb_cocotb);
end


endmodule
module axi_stream_ingress_demo #(
  parameter ADDR_WIDTH          = 32,
  parameter DATA_WIDTH          = 32,
  parameter STROBE_WIDTH        = (DATA_WIDTH / 8)
)(
  input                               clk,
  input                               rst,

  //Write Data Channel
  input                               i_tvalid,
  output  reg                         o_tready,
  input       [DATA_WIDTH - 1: 0]     i_tdata,

  input       [STROBE_WIDTH - 1:0]    i_tstrb,
  input       [STROBE_WIDTH - 1:0]    i_tkeep,
  input                               i_tlast,
  input       [3:0]                   i_tuser,
  input       [3:0]                   i_tid,
  input       [31:0]                  i_tdest

);
//local parameters

localparam      IDLE                = 4'h0;
localparam      RECEIVE_WRITE_DATA  = 4'h1;

//Address Map
localparam      ADDR_CONTROL        = 0;
localparam      ADDR_STATUS         = 1;

//registes/wires
reg           [3:0]                  state;
reg           [ADDR_WIDTH - 1: 0]    address;

reg           [DATA_WIDTH - 1: 0]    control;
reg           [DATA_WIDTH - 1: 0]    status;

//submodules
//asynchronous logic
//synchronous logic

always @ (posedge clk) begin
  //Deassert Strobes
  if (rst) begin
    o_tready            <=  0;

    //Demo values
    control             <=  0;
    status              <=  0;
    state               <= IDLE;
  end
  else begin
    case (state)
      IDLE: begin
        o_tready        <= 1;

        //Only handle read or write at one time, not both
        if (i_tvalid) begin
          state         <=  RECEIVE_WRITE_DATA;
          $display("Dest: %h", i_tdest);
          $display("User: %h", i_tuser);
          $display("ID:   %h", i_tid);
          $display("Data: 0x%08X", i_tdata);
        end
      end
      RECEIVE_WRITE_DATA: begin
        if (!i_tvalid) begin
          state         <=  IDLE;
          o_tready      <=  0;
        end
        else begin
          $display ("Data: 0x%08X", i_tdata);
        end
      end
      default: begin
        $display("Shouldn't have gotten here!");
      end
    endcase

    if (i_tlast) begin
      $display("Last Signal Strobed");
    end
  end
end

endmodule
module tb_cocotb #(
  parameter DATA_WIDTH          = 32,
  parameter FIFO_WIDTH          = 8
)(

  input                             rst,
  input       [31:0]                test_id,

  //write side
  input                             WR_CLK,
  output                            WR_RDY,
  input                             WR_ACT,
  output      [23:0]                WR_SIZE,
  input                             WR_STB,
  input       [DATA_WIDTH - 1: 0]   WR_DATA,
  output                            WR_STARVED,

  //read side
  input                             RD_CLK,
  input                             RD_STB,
  output                            RD_RDY,
  input                             RD_ACT,
  output      [23:0]                RD_SIZE,
  output      [DATA_WIDTH - 1: 0]   RD_DATA,

  output                            RD_INACTIVE
);

//Local Parameters

//Registers/Wires
reg                                 r_rst;

//Submodules
block_fifo#(
  .DATA_WIDTH      (DATA_WIDTH      ),
  .ADDRESS_WIDTH   (FIFO_WIDTH      )
)pp(
  //universal input
  .reset           (r_rst           ),

  //Write Path
  .write_clock     (WR_CLK          ),
  .write_ready     (WR_RDY          ),
  .write_activate  (WR_ACT          ),
  .write_fifo_size (WR_SIZE         ),
  .write_strobe    (WR_STB          ),
  .write_data      (WR_DATA         ),
  .starved         (WR_STARVED      ),

  //Read Path
  .read_clock      (RD_CLK          ),
  .read_strobe     (RD_STB          ),
  .read_ready      (RD_RDY          ),
  .read_activate   (RD_ACT          ),
  .read_count      (RD_SIZE         ),
  .read_data       (RD_DATA         ),

  .inactive        (RD_INACTIVE     )
);

//There is a timing thing in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst          = rst;

//Submodules
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
  $dumpfile ("design.vcd");
  $dumpvars(0, tb_cocotb);
end

endmodule
module tb_cocotb #(
  parameter DATA_WIDTH          = 32,
  parameter FIFO_WIDTH          = 8
)(

  input                             rst,
  input       [31:0]                test_id,

  //write side
  input                             WR_CLK,
  output      [1:0]                 WR_RDY,
  input       [1:0]                 WR_ACT,
  output      [23:0]                WR_SIZE,
  input                             WR_STB,
  input       [DATA_WIDTH - 1: 0]   WR_DATA,
  output                            WR_STARVED,

  //read side
  input                             RD_CLK,
  input                             RD_STB,
  output                            RD_RDY,
  input                             RD_ACT,
  output      [23:0]                RD_SIZE,
  output      [DATA_WIDTH - 1: 0]   RD_DATA,

  output                            RD_INACTIVE
);

//Local Parameters

//Registers/Wires
reg                                 r_rst;

//Submodules
ppfifo#(
  .DATA_WIDTH      (DATA_WIDTH      ),
  .ADDRESS_WIDTH   (FIFO_WIDTH      )
)pp(
  //universal input
  .reset           (r_rst           ),

  //Write Path
  .write_clock     (WR_CLK          ),
  .write_ready     (WR_RDY          ),
  .write_activate  (WR_ACT          ),
  .write_fifo_size (WR_SIZE         ),
  .write_strobe    (WR_STB          ),
  .write_data      (WR_DATA         ),
  .starved         (WR_STARVED      ),

  //Read Path
  .read_clock      (RD_CLK          ),
  .read_strobe     (RD_STB          ),
  .read_ready      (RD_RDY          ),
  .read_activate   (RD_ACT          ),
  .read_count      (RD_SIZE         ),
  .read_data       (RD_DATA         ),

  .inactive        (RD_INACTIVE     )
);

//There is a timing thing in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst          = rst;

//Submodules
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
  $dumpfile ("design.vcd");
  $dumpvars(0, tb_cocotb);
end

endmodule
module wishbone_mem_interconnect (
	clk,
	rst,

	i_m_we,
	i_m_cyc,
	i_m_stb,
	i_m_sel,
	o_m_ack,
	i_m_dat,
	o_m_dat,
	i_m_adr,
	o_m_int,

	o_s0_we,
	o_s0_cyc,
	o_s0_stb,
	o_s0_sel,
	i_s0_ack,
	o_s0_dat,
	i_s0_dat,
	o_s0_adr,
	i_s0_int


);


localparam MEM_SEL_0    = 0;
localparam MEM_OFFSET_0 = 0;
localparam MEM_SIZE_0   = 4096;


//state

//control signals
input 				      clk;
input 				      rst;

//wishbone master signals
input               i_m_we;
input               i_m_stb;
input               i_m_cyc;
input		    [3:0]   i_m_sel;
input		    [31:0]  i_m_adr;
input  		  [31:0]  i_m_dat;
output reg	[31:0]  o_m_dat;
output reg          o_m_ack;
output reg          o_m_int;


//wishbone mem signals
output              o_s0_we;
output              o_s0_cyc;
output              o_s0_stb;
output	  [3:0]     o_s0_sel;
output	  [31:0]    o_s0_adr;
output	  [31:0]    o_s0_dat;
input	    [31:0]		i_s0_dat;
input			          i_s0_ack;
input               i_s0_int;




reg [31:0] mem_select;

always @(rst or i_m_adr or mem_select) begin
	if (rst) begin
		//nothing selected
		mem_select <= 32'hFFFFFFFF;
	end
	else begin
		if ((i_m_adr >= MEM_OFFSET_0) && (i_m_adr < (MEM_OFFSET_0 + MEM_SIZE_0))) begin
			mem_select <= MEM_SEL_0;
		end
		else begin
			mem_select <= 32'hFFFFFFFF;
		end
	end
end


//data in from slave
always @ (mem_select or i_s0_dat) begin
	case (mem_select)
		MEM_SEL_0: begin
			o_m_dat <= i_s0_dat;
		end
		default: begin
			o_m_dat <= 32'h0000;
		end
	endcase
end



//ack in from slave

always @ (mem_select or i_s0_ack) begin
	case (mem_select)
		MEM_SEL_0: begin
			o_m_ack <= i_s0_ack;
		end
		default: begin
			o_m_ack <= 1'h1;
		end
	endcase
end



//int in from slave

always @ (mem_select or i_s0_int) begin
	case (mem_select)
		MEM_SEL_0: begin
			o_m_int <= i_s0_int;
		end
		default: begin
			o_m_int <= 1'h0;
		end
	endcase
end



assign o_s0_we	=	(mem_select == MEM_SEL_0) ? i_m_we: 0;
assign o_s0_stb	=	(mem_select == MEM_SEL_0) ? i_m_stb: 0;
assign o_s0_sel	=	(mem_select == MEM_SEL_0) ? i_m_sel: 0;
assign o_s0_cyc	=	(mem_select == MEM_SEL_0) ? i_m_cyc: 0;
assign o_s0_adr	=	(mem_select == MEM_SEL_0) ? i_m_adr: 0;
assign o_s0_dat	=	(mem_select == MEM_SEL_0) ? i_m_dat: 0;



endmodule
module add8u_0FP(A, B, O);
  input [7:0] A, B;
  output [8:0] O;
  wire n_198, n_36, n_189, n_195, n_42, n_192, n_23, n_21, n_20, n_27;
  wire n_40, n_24, n_48, n_147, n_66, n_60, n_201, n_108, n_129, n_39;
  wire n_207, n_204, n_120, n_8, n_9, n_4, n_5, n_6, n_7, n_0;
  wire n_1, n_2, n_3, n_33, n_34, n_18, n_19, n_16, n_17, n_14;
  wire n_15, n_12, n_13, n_10, n_11, n_114, n_45, n_78, n_93, n_111;
  wire n_150, n_75, n_51, n_57, n_54, n_46, n_213, n_210, n_132;
  assign n_0 = A[0];
  assign n_1 = A[1];
  assign n_2 = A[2];
  assign n_3 = A[3];
  assign n_4 = A[4];
  assign n_5 = A[5];
  assign n_6 = A[6];
  assign n_7 = A[7];
  assign n_8 = B[0];
  assign n_9 = B[1];
  assign n_10 = B[2];
  assign n_11 = B[3];
  assign n_12 = B[4];
  assign n_13 = B[5];
  assign n_14 = B[6];
  assign n_15 = B[7];
  assign n_16 = n_2 | n_10;
  assign n_17 = n_9 | n_1;
  assign n_18 = n_0 & n_8;
  assign n_19 = n_13 | n_5;
  assign n_20 = n_2 & n_10;
  assign n_21 = n_1 ^ n_9;
  assign n_23 = n_18 & n_17;
  assign n_24 = n_1 & n_9;
  assign n_27 = n_10 ^ n_2;
  assign n_33 = n_3 ^ n_11;
  assign n_34 = n_14 | n_6;
  assign n_36 = n_3 & n_11;
  assign n_39 = n_4 ^ n_12;
  assign n_40 = n_11 | n_3;
  assign n_42 = n_4 & n_12;
  assign n_45 = n_5 ^ n_13;
  assign n_46 = n_0 ^ n_8;
  assign n_48 = n_5 & n_13;
  assign n_51 = n_6 ^ n_14;
  assign n_54 = n_6 & n_14;
  assign n_57 = n_7 ^ n_15;
  assign n_60 = n_7 & n_15;
  assign n_66 = n_23 | n_24;
  assign n_75 = n_66 & n_16;
  assign n_78 = n_20 | n_75;
  assign n_93 = n_78 & n_40;
  assign n_108 = n_93 | n_36;
  assign n_111 = n_108 & n_39;
  assign n_114 = ~(n_111 | n_42);
  assign n_120 = ~n_114;
  assign n_129 = n_120 & n_19;
  assign n_132 = n_129 | n_48;
  assign n_147 = n_132 & n_34;
  assign n_150 = n_147 | n_54;
  assign n_189 = n_21 ^ n_18;
  assign n_192 = n_27 ^ n_66;
  assign n_195 = n_33 ^ n_78;
  assign n_198 = n_39 ^ n_108;
  assign n_201 = n_45 ^ n_120;
  assign n_204 = n_51 ^ n_132;
  assign n_207 = n_57 ^ n_150;
  assign n_210 = n_57 & n_150;
  assign n_213 = n_60 | n_210;
  assign O[0] = n_46;
  assign O[1] = n_189;
  assign O[2] = n_192;
  assign O[3] = n_195;
  assign O[4] = n_198;
  assign O[5] = n_201;
  assign O[6] = n_204;
  assign O[7] = n_207;
  assign O[8] = n_213;
endmodule
module c17(G1,G2,G3,G4,G5,G16,G17);
input G1,G2,G3,G4,G5;
output G16,G17;

  wire G8,G9,G12,G15;

  nand NAND2_0(G8,G1,G3);
  nand NAND2_1(G9,G3,G4);
  nand NAND2_2(G12,G2,G9);
  nand NAND2_3(G15,G9,G5);
  nand NAND2_4(G16,G8,G12);
  nand NAND2_5(G17,G12,G15);

endmodule
module spi_slave(SCK, SDI, CSB, SDO, sdoenb, idata, odata, oaddr, rdstb, wrstb);
    input SCK;
    input SDI;
    input CSB;
    output SDO;
    output sdoenb;
    input [7:0] idata;
    output [7:0] odata;
    output [7:0] oaddr;
    output rdstb;
    output wrstb; 

    reg  [7:0]  addr;
    reg		wrstb;
    reg		rdstb;
    reg		sdoenb;
    reg  [1:0]  state;
    reg  [2:0]  count;
    reg		writemode;
    reg		readmode;
    reg  [2:0]	fixed;
    wire [7:0]  odata;
    reg  [6:0]  predata;
    wire [7:0]  oaddr;
    reg  [7:0]  ldata;

    assign odata = {predata, SDI};
    assign oaddr = (state == `ADDRESS) ? {addr[6:0], SDI} : addr;
    assign SDO = ldata[7];

    // Readback data is captured on the falling edge of SCK so that
    // it is guaranteed valid at the next rising edge.
    always @(negedge SCK or posedge CSB) begin
	if (CSB == 1'b1) begin
	    wrstb <= 1'b0;
	    ldata  <= 8'b00000000;
	    sdoenb <= 1'b1;
        end else begin

	    // After CSB low, 1st SCK starts command

	    if (state == `DATA) begin
		if (readmode == 1'b1) begin
		    sdoenb <= 1'b0;
		    if (count == 3'b000) begin
			ldata <= idata;
		    end else begin
			ldata <= {ldata[6:0], 1'b0};	// Shift out
		    end
		end else begin
		    sdoenb <= 1'b1;
		end

		// Apply write strobe on SCK negative edge on the next-to-last
		// data bit so that it updates data on the rising edge of SCK
		// on the last data bit.
 
		if (count == 3'b111) begin
		    if (writemode == 1'b1) begin
			wrstb <= 1'b1;
 		    end
		end else begin
		    wrstb <= 1'b0;
		end
	    end else begin
		wrstb <= 1'b0;
		sdoenb <= 1'b1;
	    end		// ! state `DATA
	end		// ! CSB
    end			// always @ ~SCK

    always @(posedge SCK or posedge CSB) begin
	if (CSB == 1'b1) begin
	    // Default state on reset
	    addr <= 8'h00;
	    rdstb <= 1'b0;
	    predata <= 7'b0000000;
	    state  <= `COMMAND;
	    count  <= 3'b000;
	    readmode <= 1'b0;
	    writemode <= 1'b0;
	    fixed <= 3'b000;
        end else begin
	    // After CSB low, 1st SCK starts command
	    if (state == `COMMAND) begin
		rdstb <= 1'b0;
		count <= count + 1;
		if (count == 3'b000) begin
		    writemode <= SDI;
		end else if (count == 3'b001) begin
		    readmode <= SDI;
		end else if (count < 3'b101) begin
		    fixed <= {fixed[1:0], SDI}; 
		end else if (count == 3'b111) begin
		    state <= `ADDRESS;
		end
	    end else if (state == `ADDRESS) begin
		count <= count + 1;
		addr <= {addr[6:0], SDI};
		if (count == 3'b111) begin
		    if (readmode == 1'b1) begin
			rdstb <= 1'b1;
		    end
		    state <= `DATA;
		end else begin
		    rdstb <= 1'b0;
		end
	    end else if (state == `DATA) begin
		predata <= {predata[6:0], SDI};
		count <= count + 1;
		if (count == 3'b111) begin
		    if (fixed == 3'b001) begin
			state <= `COMMAND;
		    end else if (fixed != 3'b000) begin
			fixed <= fixed - 1;
			addr <= addr + 1;	// Auto increment address (fixed)
		    end else begin	
			addr <= addr + 1;	// Auto increment address (streaming)
		    end
		end else begin
		    rdstb <= 1'b0;
		end
	    end		// ! state `DATA
	end		// ! CSB
    end			// always @ SCK

endmodule // spi_slave
module ClockGen(CLK_OUT);

   parameter v1Width = 5;
   parameter v2Width  = 5;
   parameter initDelay = 5;
   parameter initValue = 1'b0;
   parameter otherValue = 1'b1 ;

   output    CLK_OUT ;
   reg       CLK_OUT ;

   // synopsys translate_off

   // Clock is set to initValue for initDelay, and
   // then repeats set to value1 for value1Width
   initial
      begin : clock_loop
         #0 ;
         CLK_OUT = initValue ;
         # initDelay ;
         forever
            begin
               CLK_OUT = otherValue ;
               # v1Width ;
               CLK_OUT = initValue ;
               # v2Width ;

            end // forever begin
      end // initial begin

   // Some assertions about parameter values
   initial
     begin : parameter_assertions
        integer ok ;
        ok = 1 ;

        if (! ( (( initValue == 1'b0 ) && ( otherValue == 1'b1 )) ||
             (( initValue == 1'b1 ) && ( otherValue == 1'b0 )) ) )
          begin
             ok = 0;
             $display ( "ERROR ClockGen.v: clock values must be complements" ) ;
          end // if ( (( initValue != 0 ) && ( otherValue != 1 )) ||...

        if ( ( v1Width <= 0 ) || ( v2Width <= 0 ))
          begin
             ok = 0;
             $display( "ERROR ClockGen.v: duty cycle must be greater then 0") ;
          end // if ( ( v1Width <= 0 ) || ( v2Width <= 0 ))

        if ( ok == 0 ) $finish ;

      end // initial begin
      // synopsys translate_on

endmodule // ClockGen
module testClockGen1() ;

   wire clkout ;

   ClockGen#(8,24,16,1'b1,1'b0)  u1( clkout );

   initial
     begin
        $dumpfile("ClockGen.dump");
        $dumpvars(5) ;
        $dumpon ;
        #10000 $finish ;
     end

endmodule // testClockGen
module SyncWire( DIN, DOUT );

   parameter width = 1;
            
   input [width - 1 : 0]    DIN;
   output [width - 1 : 0]   DOUT;

   assign                   DOUT = DIN ;
   

endmodule
module ASSIGN1(IN, OUT);
   output OUT;
   input IN;
   assign OUT = IN;
endmodule
module SyncSpRamBeNx64_00000008_00000100_0_2
  (
   Clk_CI,
   Rst_RBI,
   CSel_SI,
   WrEn_SI,
   BEn_SI,
   WrData_DI,
   Addr_DI,
   RdData_DO
   );

   input [7:0]   BEn_SI; // byte-enable: ignore or use as needed
   input [63:0]  WrData_DI;
   input [7:0] 	 Addr_DI;
   output [63:0] RdData_DO;
   input 	 Clk_CI;
   input 	 Rst_RBI; // reset: ignore or use as needed
   input 	 CSel_SI;
   input 	 WrEn_SI;
   wire [63:0] 	 RdData_DO;
   wire 	 csel_b,wren_b;
   wire [15:0] WMaskIn, NotWMaskIn;

   assign NotWMaskIn = 16'b0;
   assign WMaskIn = ~NotWMaskIn;
   assign wren_b = ~WrEn_SI; // active-low global-write-enable
   assign csel_b = ~CSel_SI; // active-low chip-select-enable

   fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
   fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
   fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[47:32]));
   fakeram45_256x16 macro_mem_3 (.clk(Clk_CI),.rd_out(RdData_DO[63:48]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[63:48]));

endmodule // SyncSpRamBeNx64_00000008_00000100_0_2