dakies/OSS_Verilog huggingface dataset:
module testbench;

    reg        clk;
    reg  [3:0] key;
    reg  [7:0] sw;

    top
    # (
        .debounce_depth             ( 1 ),
        .shift_strobe_width         ( 1 ),
        .seven_segment_strobe_width ( 1 )
    )
    i_top
    (
        .clk ( clk ),
        .key ( key ),
        .sw  ( sw  )
    );

    initial
    begin
        clk = 0;

        forever
            # 10 clk = ! clk;
    end

    reg reset;
    
    always @*
        key [3] = ~ reset;

    initial
    begin
        reset <= 'bx;
        repeat (2) @ (posedge clk);
        reset <= 1;
        repeat (2) @ (posedge clk);
        reset <= 0;
    end

    initial
    begin
        #0
        $dumpvars;

        key [2:0] <= 'b0;
        sw        <= 'b0;

        @ (negedge reset);

        repeat (1000)
        begin
            @ (posedge clk);

            key [2:0] <= $random;
            sw        <= $random;
        end

        `ifdef MODEL_TECH  // Mentor ModelSim and Questa
            $stop;
        `else
            $finish;
        `endif
    end

endmodule
module testbench;

    reg [3:0] key;
    reg [7:0] sw;

    top i_top (.key (key), .sw (sw));

    initial
    begin
        #0
        $dumpvars;

        repeat (8) #10 { key, sw } <= $random;

        `ifdef MODEL_TECH  // Mentor ModelSim and Questa
            $stop;
        `else
            $finish;
        `endif
    end

endmodule
module top
(
    input         clk,
    input  [ 3:0] key,
    input  [ 7:0] sw,
    output [11:0] led,

    output [ 7:0] abcdefgh,
    output [ 7:0] digit,

    output        vsync,
    output        hsync,
    output [ 2:0] rgb,

    inout  [18:0] gpio
);

    assign abcdefgh = 8'hff;
    assign digit    = 8'b0;
    assign hsync    = 1'b1;
    assign vsync    = 1'b1;
    assign rgb      = 3'b0;

    wire a = ~ key [0];
    wire b = ~ key [1];
    
    wire result = a ^ b;

    assign led [0] = ~ result;
    
    assign led [1] = ~ (~ key [0] ^ ~ key [1]);

    // Exercise 1: Change the code below.
    // Write the same for AND and OR operations
    
    assign led [2] = 1'b1;
    assign led [3] = 1'b1;

    // Exercise 2: Change the code below.
    // Assign to led [4] the result of XOR operation
    // without using "^" operation.
    // Use only operations "&", "|", "~" and parenthesis, "(" and ")".

    assign led [4] = 1'b1;

    assign led [11:5] = 7'h7f;

endmodule
module top
(
    input         clk,
    input  [ 3:0] key,
    input  [ 7:0] sw,
    output [11:0] led,

    output [ 7:0] abcdefgh,
    output [ 7:0] digit,

    output        vsync,
    output        hsync,
    output [ 2:0] rgb,

    inout  [18:0] gpio
);

    wire reset = ~ key [3];

    assign led    = 12'hfff;
    assign hsync  = 1'b1;
    assign vsync  = 1'b1;
    assign rgb    = 3'b0;

    //   --a--
    //  |     |
    //  f     b
    //  |     |
    //   --g--
    //  |     |
    //  e     c
    //  |     |
    //   --d--  h
    //
    //  0 means light

    parameter [7:0] C = 8'b01100011,
                    E = 8'b01100001,
                    h = 8'b11010001,
                    I = 8'b11110011,
                    P = 8'b00110001;

    assign abcdefgh = key [0] ? C : E;
    assign digit    = key [1] ? 8'b1111_1110 : 8'b1111_1101;

    // Exercise 1: Display the first letters
    // of your first name and last name instead.

    // assign abcdefgh = ...
    // assign digit    = ...

    // Exercise 2: Display letters of a 4-character word
    // using this code to display letter of ChIP as an example

    /*
    reg [7:0] letter;
    
    always @*
      case (key)
      4'b0111: letter = C;
      4'b1011: letter = h;
      4'b1101: letter = I;
      4'b1110: letter = P;
      default: letter = E;
      endcase
      
    assign abcdefgh = letter;
    assign digit    = key == 4'b1111 ? 8'h00 : { key, key };
    */

endmodule
module top
(
    input         clk,
    input  [ 3:0] key,
    input  [ 7:0] sw,
    output [11:0] led,

    output [ 7:0] abcdefgh,
    output [ 7:0] digit,

    output        vsync,
    output        hsync,
    output [ 2:0] rgb,

    inout  [18:0] gpio
);

    wire   reset  = ~ key [3];

    assign led    = 12'hfff;
    assign hsync  = 1'b1;
    assign vsync  = 1'b1;
    assign rgb    = 3'b0;

    //------------------------------------------------------------------------

    reg [31:0] cnt;
    
    always @ (posedge clk or posedge reset)
      if (reset)
        cnt <= 32'b0;
      else
        cnt <= cnt + 32'b1;
        
    wire enable = (cnt [22:0] == 23'b0);

    //------------------------------------------------------------------------

    reg [7:0] shift_reg;
    
    always @ (posedge clk or posedge reset)
      if (reset)
        shift_reg <= 8'b0000_0001;
      else if (enable)
        shift_reg <= { shift_reg [0], shift_reg [7:1] };

    //------------------------------------------------------------------------

    //   --a--
    //  |     |
    //  f     b
    //  |     |
    //   --g--
    //  |     |
    //  e     c
    //  |     |
    //   --d--  h
    //
    //  0 means light

    parameter [7:0] C = 8'b01100011,
                    E = 8'b01100001,
                    h = 8'b11010001,
                    I = 8'b11110011,
                    O = 8'b00000011,
                    P = 8'b00110001,
                    X = 8'b10010001;

    reg [7:0] letter;
    
    always @*
      case (shift_reg)
      8'b1000_0000: letter = C;
      8'b0100_0000: letter = h;
      8'b0010_0000: letter = I;
      8'b0001_0000: letter = P;

      8'b0000_1000: letter = E;
      8'b0000_0100: letter = X;
      8'b0000_0010: letter = P;
      8'b0000_0001: letter = O;
      default:      letter = E;
      endcase

    assign abcdefgh = letter;
    assign digit    = ~ shift_reg;

    // Exercise 1: Increase the frequency of enable signal
    // to the level your eyes see the letters as a solid word
    // without any blinking. What is the threshold of such frequency?

    // Exercise 2: Put your name or another word to the display.

    // Exercise 3: Comment out the "default" clause from the "case" statement
    // in the "always" block,and re-synthesize the example.
    // Are you getting any warnings or errors? Try to explain why.

endmodule
module top
(
    input         clk,
    input  [ 3:0] key,
    input  [ 7:0] sw,
    output [11:0] led,

    output [ 7:0] abcdefgh,
    output [ 7:0] digit,

    output        vsync,
    output        hsync,
    output [ 2:0] rgb,

    inout  [18:0] gpio
);

    wire reset = ~ key [3];

    assign abcdefgh = 8'hff;
    assign digit    = 8'hff;
    assign hsync    = 1'b1;
    assign vsync    = 1'b1;
    assign rgb      = 3'b0;

    // Exercise 1: Free running counter.
    // How do you change the speed of LED blinking?
    // Try different bit slices to display.

    reg [31:0] cnt;
    
    always @ (posedge clk or posedge reset)
      if (reset)
        cnt <= 32'b0;
      else
        cnt <= cnt + 32'b1;
        
    assign led = ~ cnt [31:20];

    // Exercise 2: Key-controlled counter.
    // Comment out the code above.
    // Uncomment and synthesize the code below.
    // Press the key to see the counter incrementing.
    //
    // Change the design, for example:
    //
    // 1. One key is used to increment, another to decrement.
    //
    // 2. Two counters controlled by different keys
    // displayed in different groups of LEDs.

    /*

    reg key_r;
    
    always @ (posedge clk or posedge reset)
      if (reset)
        key_r <= 1'b0;
      else
        key_r <= key [0];
        
    wire key_pressed = ~ key [0] & key_r;

    reg [11:0] cnt;

    always @ (posedge clk or posedge reset)
      if (reset)
        cnt <= 12'b0;
      else if (key_pressed)
        cnt <= cnt + 12'b1;
        
    assign led = ~ cnt;
    
    */

endmodule
module top
(
    input btnc,
    input btnu,
    input btnl,
    input btnr,
    input btnd,

    output [15:0] led
);

    assign led [0] = btnl ^ btnr;

    // Exercise: Change the code below.
    // Write the same for led [1] - logic operation AND 
    // Write the same for led [2] - logic operation OR

    assign led [1] = 1'b0;
    assign led [2] = 1'b1;

endmodule
module top
(
    input  [3:0] key_sw,
    output [3:0] led,

    output       buzzer
);

    wire a = ~ key_sw [0];
    wire b = ~ key_sw [1];
    
    wire result = a ^ b;

    assign led [0] = ~ result;

    assign led [1] = ~ (~ key_sw [0] ^ ~ key_sw [1]);

    // Exercise 1: Change the code below.
    // Write the same for led [2] - logic operation AND 
    // Write the same for led [3] - logic operation OR
    
    assign led [2] = 1'b0;
    assign led [3] = 1'b1;

    // Exercise 2: Change the code below.
    // Turn on and off buzzer on the board using key.
    // Listen to the click sound.

    assign buzzer = 1'b0;
    
endmodule
module top
(
    input         btnc,
    input         btnu,
    input         btnl,
    input         btnr,
    input         btnd,

    output [15:0] led,

    output        led16_r,
    output        led16_g,
    output        led16_b,

    output        led17_r,
    output        led17_g,
    output        led17_b
);

    assign led [0] = btnl ^ btnr;

    // Exercise 1: Change the code below.
    // Write the same for led [1] - logic operation AND 
    // Write the same for led [2] - logic operation OR

    assign led [1] = 1'b0;
    assign led [2] = 1'b1;

    // Exercise 2: RGB leds allow to make different colors.
    // Explore them.

    assign led16_r = 1'b0;
    assign led16_g = 1'b0;
    assign led16_b = 1'b0;

    assign led17_r = 1'b0;
    assign led17_g = 1'b0;
    assign led17_b = 1'b0;

endmodule
module top
(
    input  [3:0] key,
    input  [3:0] sw,
    output [7:0] led,

    output       buzzer
);

    wire a = ~ key [0];
    wire b = ~ key [1];
    
    wire result = a ^ b;

    assign led [0] = ~ result;

    assign led [1] = ~ (~ key [0] ^ ~ key [1]);

    // Exercise 1: Change the code below.
    // Write the same for led [2] - logic operation AND 
    // Write the same for led [3] - logic operation OR
    
    assign led [2] = 1'b0;
    assign led [3] = 1'b1;

    // Exercise 2: Change the code below.
    // Turn on and off buzzer on the board using key.
    // Listen to the click sound.

    assign buzzer = 1'b0;
    
endmodule
module top
(
    input  [1:0] key,
    output [9:0] led
);

    wire a = ~ key [0];
    wire b = ~ key [1];
    
    assign led [0] = a ^ b;
    assign led [1] = ~ key [0] ^ ~ key [1];

    // Exercise: Change the code below.
    // Write the same for led [2] - logic operation AND 
    // Write the same for led [3] - logic operation OR
    
    assign led [2] = 1'b0;
    assign led [3] = 1'b1;

endmodule
module top
(
    input  [ 3:0] key,
    output [11:0] led,
    output        buzzer
);

    wire a = ~ key [0];
    wire b = ~ key [1];
    
    wire result = a ^ b;

    assign led [0] = ~ result;
    
    assign led [1] = ~ (~ key [0] ^ ~ key [1]);

    // Exercise 1: Change the code below.
    // Write the same for AND and OR operations
    
    assign led [11:2] = 10'h3ff;

    // Exercise 2: Change the code below.
    // Turn on and off buzzer on the board using key.
    // Listen to the click sound.

    assign buzzer = 1'b1;

endmodule
module rotary_encoder
(
    input             clk,
    input             reset,
    input             a,
    input             b,
    output reg [15:0] value
);

    reg prev_a;

    always @ (posedge clk or posedge reset)
        if (reset)
            prev_a <= 1'b1;
        else
            prev_a <= a;

    always @ (posedge clk or posedge reset)
        if (reset)
        begin
            value <= - 16'd1;  // To do: figure out why we have to start with -1 and not 0
        end
        else if (a && ! prev_a)
        begin
            if (b)
                value <= value + 16'd1;
            else
                value <= value - 16'd1;
        end

endmodule
module calculator (
    input       clock,
    input       reset,
    input       enter,
    input       add,
    input       multiply,
    input [7:0] data,

    output        newresult,
    output [15:0] result,
    output        overflow,
    output [ 3:0] error
);
  assign error = 0;

  reg  [15:0] alu_a;
  reg  [15:0] alu_b;
  reg         alu_multiply;
  wire [15:0] alu_result;
  wire        alu_overflow;

  alu alu (
      .a       (alu_a),
      .b       (alu_b),
      .multiply(alu_multiply),
      .result  (alu_result),
      .overflow(alu_overflow)
  );

  reg r_overflow;
  assign overflow = r_overflow;

  always @(posedge clock) begin
    if (reset) r_overflow <= 0;
    else       r_overflow <= alu_overflow;
  end

  reg         stack_push;
  reg         stack_pop;
  reg [15:0]  stack_write_data;
  wire [15:0] stack_read_data;

  stack stack (
      .clock     (clock),
      .reset     (reset),
      .push      (stack_push),
      .pop       (stack_pop),
      .write_data(stack_write_data),
      .read_data (stack_read_data)
  );


  reg [15:0] r_alu_a;
  reg [15:0] r_alu_b;
  reg        r_alu_multiply;
  reg [1:0]  state;

  reg [1:0] next_state;

  reg [15:0] oldresult = 0;
  assign result    = stack_read_data;
  assign newresult = (result != oldresult) && state == 0;

  always @(*) begin
    alu_a = r_alu_a;
    alu_b = r_alu_b;
    alu_multiply = r_alu_multiply;
    stack_push = 0;
    stack_pop  = 0;
    stack_write_data = data;
    next_state = state;

    case (state)
      0:
      if (enter) begin
        stack_push = 1;
        stack_write_data = data;
      end else if (add | multiply) begin
        alu_a = stack_read_data;
        alu_multiply = multiply;

        stack_pop  = 1;
        next_state = 1;
      end

      1: begin
        alu_b = stack_read_data;
        stack_pop  = 1;
        next_state = 2;
      end

      2: begin
        stack_push = 1;
        stack_write_data = alu_result;
        next_state = 0;
      end

    endcase
  end

  always @(posedge clock) begin
    if (reset) begin
      r_alu_a <= 0;
      r_alu_b <= 0;
      r_alu_multiply <= 0;
      state   <= 0;
      oldresult <= 0;
    end else begin
      r_alu_a <= alu_a;
      r_alu_b <= alu_b;
      r_alu_multiply <= alu_multiply;
      state <= next_state;
      oldresult <= result;
    end
  end

endmodule
module stack (
    input clock,
    input reset,
    input push,
    input pop,

    input  [`word_width - 1:0] write_data,
    output [`word_width - 1:0] read_data
);

  reg [`word_width - 1:0] stack[0:`stack_size - 1];

  reg [`stack_pointer_size - 1:0] stack_pointer;

  assign read_data = stack[stack_pointer];

  integer i;

  always @(posedge clock) begin
    if (reset) begin
      stack_pointer <= 0;
      for (i = 0; i < `stack_size; i = i + 1) stack[i] <= 0;
    end else if (push) begin
      if (stack_pointer == `stack_size - 1) begin
        stack[0]      <= write_data;
        stack_pointer <= 0;
      end else begin
        stack[stack_pointer + 1] <= write_data;
        stack_pointer            <= stack_pointer + 1;
      end
    end else if (pop) begin
      stack[stack_pointer] <= 0;
      if (stack_pointer == 0) stack_pointer <= `stack_size - 1;
      else                    stack_pointer <= stack_pointer - 1;
    end
  end

endmodule
module alu (
    input [15:0] a,
    input [15:0] b,
    input        multiply,

    output [15:0] result,
    output        overflow
);

  wire [16:0] result_add = a + b;
  wire [31:0] result_mul = a * b;

  assign result   = multiply ?  result_mul[15: 0] : result_add[15:0];
  assign overflow = multiply ? |result_mul[31:16] : result_add[16];

endmodule
module sm_top
(
    input           clkIn,
    input           rst_n,
    input   [ 3:0 ] clkDevide,
    input           clkEnable,
    output          clk,
    input   [ 4:0 ] regAddr,
    output  [31:0 ] regData
);
    //metastability input filters
    wire    [ 3:0 ] devide;
    wire            enable;
    wire    [ 4:0 ] addr;

    sm_debouncer #(.SIZE(4)) f0(clkIn, clkDevide, devide);
    sm_debouncer #(.SIZE(1)) f1(clkIn, clkEnable, enable);
    sm_debouncer #(.SIZE(5)) f2(clkIn, regAddr,   addr  );

    //cores
    //clock devider
    sm_clk_divider sm_clk_divider
    (
        .clkIn      ( clkIn     ),
        .rst_n      ( rst_n     ),
        .devide     ( devide    ),
        .enable     ( enable    ),
        .clkOut     ( clk       )
    );

    //instruction memory
    wire    [31:0]  imAddr;
    wire    [31:0]  imData;
    sm_rom reset_rom(imAddr, imData);

    sr_cpu sm_cpu
    (
        .clk        ( clk       ),
        .rst_n      ( rst_n     ),
        .regAddr    ( addr      ),
        .regData    ( regData   ),
        .imAddr     ( imAddr    ),
        .imData     ( imData    )
    );

endmodule
module sm_hex_display_8
(
    input             clock,
    input             resetn,
    input      [31:0] number,

    output reg [ 6:0] seven_segments,
    output reg        dot,
    output reg [ 7:0] anodes
);

    function [6:0] bcd_to_seg (input [3:0] bcd);

        case (bcd)
        'h0: bcd_to_seg = 'b1000000;  // g f e d c b a
        'h1: bcd_to_seg = 'b1111001;
        'h2: bcd_to_seg = 'b0100100;  //   --a--
        'h3: bcd_to_seg = 'b0110000;  //  |     |
        'h4: bcd_to_seg = 'b0011001;  //  f     b
        'h5: bcd_to_seg = 'b0010010;  //  |     |
        'h6: bcd_to_seg = 'b0000010;  //   --g--
        'h7: bcd_to_seg = 'b1111000;  //  |     |
        'h8: bcd_to_seg = 'b0000000;  //  e     c
        'h9: bcd_to_seg = 'b0011000;  //  |     |
        'ha: bcd_to_seg = 'b0001000;  //   --d-- 
        'hb: bcd_to_seg = 'b0000011;
        'hc: bcd_to_seg = 'b1000110;
        'hd: bcd_to_seg = 'b0100001;
        'he: bcd_to_seg = 'b0000110;
        'hf: bcd_to_seg = 'b0001110;
        endcase

    endfunction

    reg [2:0] i;

    always @ (posedge clock or negedge resetn)
    begin
        if (! resetn)
        begin
            seven_segments <=   bcd_to_seg (0);
            dot            <= ~ 1'b0;
            anodes         <= ~ 8'b00000001;

            i <= 0;
        end
        else
        begin
            seven_segments <=   bcd_to_seg (number [i * 4 +: 4]);
            dot            <= ~ 1'b00;
            anodes         <= ~ (1 << i);

            i <= i + 1;
        end
    end

endmodule
module testbench;

    reg       clk;
    reg       reset_n;
    reg [3:0] key_sw;

    top
    # (
        .clk_mhz (50),
        .strobe_to_update_xy_counter_width (1)
    )
    i_top
    (
        .clk     ( clk     ),
        .reset_n ( reset_n ),
        .key_sw  ( key_sw  )
    );

    initial
    begin
        clk = 1'b0;

        forever
            # 10 clk = ! clk;
    end

    initial
    begin
        reset_n <= 1'bx;
        repeat (2) @ (posedge clk);
        reset_n <= 1'b0;
        repeat (2) @ (posedge clk);
        reset_n <= 1'b1;
    end

    initial
    begin
        #0
        $dumpvars(6);

        key_sw <= 4'b0;

        @ (posedge reset_n);

        // repeat (1000)
        // begin
        //     @ (posedge clk);

        //     key_sw <= $random;
        // end

        #120000000

        `ifdef MODEL_TECH  // Mentor ModelSim and Questa
            $stop;
        `else
            $finish;
        `endif
    end

endmodule
module top
# (
    parameter clk_mhz = 50,
              strobe_to_update_xy_counter_width = 20
)
(
    input        clk,
    input        reset_n,
    
    input  [3:0] key_sw,
    output [3:0] led,

    output [7:0] abcdefgh,
    output [3:0] digit,

    output       buzzer,

    output       hsync,
    output       vsync,
    output [2:0] rgb
);

    assign led       = key_sw;
    assign abcdefgh  = { key_sw, key_sw };
    assign digit     = 4'b0;
    assign buzzer    = 1'b0;

    wire launch_key = key_sw != 4'b1111;  // Any key is pressed
    
    // Either of two leftmost keys is pressed
    wire left_key   = key_sw [3:2] != 2'b11;

    // Either of two rightmost keys is pressed
    wire right_key  = key_sw [1:0] != 2'b11;

    risk_game_top
    # (
        .clk_mhz (clk_mhz),

        .strobe_to_update_xy_counter_width
        (strobe_to_update_xy_counter_width)
    )
    i_game_top
    (
        .clk              (   clk                   ),
        .reset            ( ~ reset_n               ),

        .launch_key       (   launch_key            ),
        .left_right_keys  ( { left_key, right_key } ),

        .hsync            (   hsync                 ),
        .vsync            (   vsync                 ),
        .rgb              (   rgb                   )
    );

endmodule
module top
# (
    parameter clk_mhz = 50,
              strobe_to_update_xy_counter_width = 20
)
(
    input        clk,
    input        reset_n,
    
    input  [3:0] key_sw,
    output [3:0] led,

    output [7:0] abcdefgh,
    output [3:0] digit,

    output       buzzer,

    output       hsync,
    output       vsync,
    output [2:0] rgb
);

    assign led       = key_sw;
    assign abcdefgh  = { key_sw, key_sw };
    assign digit     = 4'b0;
    assign buzzer    = 1'b0;

    wire launch_key = key_sw != 4'b1111;  // Any key is pressed
    
    // Either of two leftmost keys is pressed
    wire left_key   = key_sw [3:2] != 2'b11;

    // Either of two rightmost keys is pressed
    wire right_key  = key_sw [1:0] != 2'b11;

    wire [3:0] key_sw_p  = ~ key_sw;

    risk_game_top
    # (
        .clk_mhz (clk_mhz),

        .strobe_to_update_xy_counter_width
        (strobe_to_update_xy_counter_width)
    )
    i_game_top
    (
        .clk              (   clk                   ),
        .reset            ( ~ reset_n               ),

        .launch_key       (   launch_key            ),
        .left_right_keys  ( { left_key, right_key } ),
        .key_sw           (   key_sw_p              ),

        .hsync            (   hsync                 ),
        .vsync            (   vsync                 ),
        .rgb              (   rgb                   )
    );

endmodule
module raven_spi(RST, SCK, SDI, CSB, SDO, sdo_enb,
	xtal_ena, reg_ena, pll_vco_ena, pll_cp_ena, pll_bias_ena,
	pll_trim, pll_bypass, irq, reset, trap,
	mfgr_id, prod_id, mask_rev_in, mask_rev);

    input RST;
    input SCK;
    input SDI;
    input CSB;
    output SDO;
    output sdo_enb;
    output xtal_ena;
    output reg_ena;
    output pll_vco_ena;
    output pll_cp_ena;
    output pll_bias_ena;
    output [3:0] pll_trim;
    output pll_bypass;
    output irq;
    output reset;
    input  trap;
    input [3:0] mask_rev_in;	// metal programmed
    output [11:0] mfgr_id;
    output [7:0] prod_id;
    output [3:0] mask_rev;

    reg xtal_ena;
    reg reg_ena;
    reg [3:0] pll_trim;
    reg pll_vco_ena;
    reg pll_cp_ena;
    reg pll_bias_ena;
    reg pll_bypass;
    reg irq;
    reg reset;

    wire [7:0] odata;
    wire [7:0] idata;
    wire [7:0] iaddr;

    wire trap;
    wire rdstb;
    wire wrstb;

    // Instantiate the SPI slave module

    spi_slave U1 (
	.SCK(SCK),
	.SDI(SDI),
	.CSB(CSB),
	.SDO(SDO),
	.sdoenb(sdo_enb),
	.idata(odata),
	.odata(idata),
	.oaddr(iaddr),
	.rdstb(rdstb),
	.wrstb(wrstb)
    );

    wire [11:0] mfgr_id;
    wire [7:0] prod_id;
    wire [3:0] mask_rev;

    assign mfgr_id = 12'h456;		// Hard-coded
    assign prod_id = 8'h02;		// Hard-coded
    assign mask_rev = mask_rev_in;	// Copy in to out.

    // Send register contents to odata on SPI read command
    // All values are 1-4 bits and no shadow registers are required.

    assign odata = 
	(iaddr == 8'h00) ? 8'h00 :	// SPI status (fixed)
	(iaddr == 8'h01) ? {mask_rev, mfgr_id[11:8]} : 	// Mask rev (metal programmed)
	(iaddr == 8'h02) ? mfgr_id[7:0] :	// Manufacturer ID (fixed)
	(iaddr == 8'h03) ? prod_id :	// Product ID (fixed)
	(iaddr == 8'h04) ? {xtal_ena, reg_ena, pll_vco_ena, pll_cp_ena, pll_trim} :
	(iaddr == 8'h05) ? {7'b0000000, pll_bypass} :
	(iaddr == 8'h06) ? {7'b0000000, irq} :
	(iaddr == 8'h07) ? {7'b0000000, reset} :
	(iaddr == 8'h08) ? {7'b0000000, trap} :
			   8'h00;	// Default

    // Register mapping and I/O to slave module

    always @(posedge SCK or posedge RST) begin
	if (RST == 1'b1) begin
	    pll_trim <= 4'b0000;
	    xtal_ena <= 1'b1;
	    reg_ena <= 1'b1;
	    pll_vco_ena <= 1'b1;
	    pll_cp_ena <= 1'b1;
	    pll_bias_ena <= 1'b1;
	    pll_bypass <= 1'b0;
	    irq <= 1'b0;
	    reset <= 1'b0;
	end else if (wrstb == 1'b1) begin
	    case (iaddr)
		8'h04: begin
			 pll_trim    <= idata[7:4];
			 pll_cp_ena  <= idata[3];
			 pll_vco_ena <= idata[2];
			 reg_ena     <= idata[1];
			 xtal_ena    <= idata[0];
		       end
		8'h05: begin
			 pll_bypass <= idata[0];
		       end
		8'h06: begin
			 irq <= idata[0];
		       end
		8'h07: begin
			 reset <= idata[0];
		       end
		// Register 8 is read-only
	    endcase	// (iaddr)
	end
    end
endmodule	// raven_spi
module design_mux (
   	output out,
   	input select,
   	input RST,
    	input SCK,
    	input SDI,
    	input CSB,
    	input  trap,
    	input [3:0] mask_rev_in
);
	wire I0;
	wire I1;
	wire sdo_enb;
	wire xtal_ena;
	wire reg_ena;
	wire pll_vco_ena;
	wire pll_cp_ena;
	wire pll_bias_ena;
	wire [3:0] pll_trim;
	wire pll_bypass;
	wire irq;
	wire [11:0] mfgr_id;
	wire [7:0] prod_id;
	wire [3:0] mask_rev;
   AMUX2_3V AMUX2_3V (
		//.VDD (VDD),
		//.VSS (VSS),
		.I0 (IO),
		.I1 (I1),
		.out (out),
		.select (select)
	);
  raven_spi raven_spi(
  		.RST (RST), 
  		.SCK (SCK), 
  		.SDI (SDI), 
  		.CSB (CSB), 
  		.SDO (I0), 
  		.sdo_enb (sdo_enb),
		.xtal_ena (xtal_ena), 
		.reg_ena (reg_ena), 
		.pll_vco_ena (pll_vco_ena), 
		.pll_cp_ena (pll_cp_ena), 
		.pll_bias_ena (pll_bias_ena),
	        .pll_trim (pll_trim), 
	        .pll_bypass (pll_bypass), 
	        .irq (irq), 
	        .reset (I1), 
	        .trap (trap),
		.mfgr_id (mfgr_id), 
		.prod_id (prod_id), 
		.mask_rev_in (mask_rev_in), 
		.mask_rev (mask_rev)
		);

endmodule
module ram16x512 (
	address,
	byteena,
	clken,
	clock,
	data,
	wren,
	q);

	input	[8:0]  address;
	input	[1:0]  byteena;
	input	  clken;
	input	  clock;
	input	[15:0]  data;
	input	  wren;
	output	[15:0]  q;

	wire [15:0] sub_wire0;
	wire [15:0] q = sub_wire0[15:0];

	altsyncram	altsyncram_component (
				.clocken0 (clken),
				.wren_a (wren),
				.clock0 (clock),
				.byteena_a (byteena),
				.address_a (address),
				.data_a (data),
				.q_a (sub_wire0),
				.aclr0 (1'b0),
				.aclr1 (1'b0),
				.address_b (1'b1),
				.addressstall_a (1'b0),
				.addressstall_b (1'b0),
				.byteena_b (1'b1),
				.clock1 (1'b1),
				.clocken1 (1'b1),
				.clocken2 (1'b1),
				.clocken3 (1'b1),
				.data_b (1'b1),
				.eccstatus (),
				.q_b (),
				.rden_a (1'b1),
				.rden_b (1'b1),
				.wren_b (1'b0));
	defparam
		altsyncram_component.byte_size = 8,
		altsyncram_component.clock_enable_input_a = "NORMAL",
		altsyncram_component.clock_enable_output_a = "BYPASS",
		altsyncram_component.intended_device_family = "Cyclone II",
		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
		altsyncram_component.lpm_type = "altsyncram",
		altsyncram_component.numwords_a = 512,
		altsyncram_component.operation_mode = "SINGLE_PORT",
		altsyncram_component.outdata_aclr_a = "NONE",
		altsyncram_component.outdata_reg_a = "UNREGISTERED",
		altsyncram_component.power_up_uninitialized = "FALSE",
		altsyncram_component.widthad_a = 9,
		altsyncram_component.width_a = 16,
		altsyncram_component.width_byteena_a = 2;


endmodule
module bit_reverse(
	input [7:0] in,
	output [7:0] out
);

	assign out[7:0] = { in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7] };

endmodule
module rom16x2048 (
	address,
	clken,
	clock,
	q);

	input	[10:0]  address;
	input	  clken;
	input	  clock;
	output	[15:0]  q;

	wire [15:0] sub_wire0;
	wire [15:0] q = sub_wire0[15:0];

	altsyncram	altsyncram_component (
				.clocken0 (clken),
				.clock0 (clock),
				.address_a (address),
				.q_a (sub_wire0),
				.aclr0 (1'b0),
				.aclr1 (1'b0),
				.address_b (1'b1),
				.addressstall_a (1'b0),
				.addressstall_b (1'b0),
				.byteena_a (1'b1),
				.byteena_b (1'b1),
				.clock1 (1'b1),
				.clocken1 (1'b1),
				.clocken2 (1'b1),
				.clocken3 (1'b1),
				.data_a ({16{1'b1}}),
				.data_b (1'b1),
				.eccstatus (),
				.q_b (),
				.rden_a (1'b1),
				.rden_b (1'b1),
				.wren_a (1'b0),
				.wren_b (1'b0));
	defparam
		altsyncram_component.clock_enable_input_a = "NORMAL",
		altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef OPENMSP430_SIMULATION
		altsyncram_component.init_file = "./pmem.mif",
`else
		altsyncram_component.init_file = "../../software/memledtest/memledtest.mif",
`endif
		altsyncram_component.intended_device_family = "Cyclone II",
		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=ROM",
		altsyncram_component.lpm_type = "altsyncram",
		altsyncram_component.numwords_a = 2048,
		altsyncram_component.operation_mode = "ROM",
		altsyncram_component.outdata_aclr_a = "NONE",
		altsyncram_component.outdata_reg_a = "UNREGISTERED",
		altsyncram_component.ram_block_type = "M4K",
		altsyncram_component.widthad_a = 11,
		altsyncram_component.width_a = 16,
		altsyncram_component.width_byteena_a = 1;


endmodule
module  io_mux (

// Function A (typically GPIO)
    a_din,
    a_dout,
    a_dout_en,

// Function B (Timer A, ...)
    b_din,
    b_dout,
    b_dout_en,

// IO Cell
    io_din,
    io_dout,
    io_dout_en,

// Function selection (0=A, 1=B)
    sel
);

// PARAMETERs
//============
parameter          WIDTH = 8;
   
// Function A (typically GPIO)
//===============================
output [WIDTH-1:0] a_din;
input  [WIDTH-1:0] a_dout;
input  [WIDTH-1:0] a_dout_en;

// Function B (Timer A, ...)
//===============================
output [WIDTH-1:0] b_din;
input  [WIDTH-1:0] b_dout;
input  [WIDTH-1:0] b_dout_en;

// IO Cell
//===============================
input  [WIDTH-1:0] io_din;
output [WIDTH-1:0] io_dout;
output [WIDTH-1:0] io_dout_en;

// Function selection (0=A, 1=B)
//===============================
input  [WIDTH-1:0] sel;


//=============================================================================
// 1)  I/O FUNCTION SELECTION MUX
//=============================================================================

function [WIDTH-1:0] mux (
   input [WIDTH-1:0] A,
   input [WIDTH-1:0] B,
   input [WIDTH-1:0] SEL
);
   integer i;   
   begin
      mux = {WIDTH{1'b0}};
      for (i = 0; i < WIDTH; i = i + 1)
	mux[i] = sel[i] ? B[i] : A[i];
   end
endfunction


assign a_din      = mux(       io_din, {WIDTH{1'b0}}, sel);
assign b_din      = mux({WIDTH{1'b0}},        io_din, sel);
assign io_dout    = mux(       a_dout,        b_dout, sel);
assign io_dout_en = mux(    a_dout_en,     b_dout_en, sel);

	   
endmodule // io_mux
module  omsp_clock_gate (

// OUTPUTs
    gclk,                      // Gated clock

// INPUTs
    clk,                       // Clock
    enable,                    // Clock enable
    scan_enable                // Scan enable (active during scan shifting)
);

// OUTPUTs
//=========
output         gclk;           // Gated clock

// INPUTs
//=========
input          clk;            // Clock
input          enable;         // Clock enable
input          scan_enable;    // Scan enable (active during scan shifting)


//=============================================================================
// CLOCK GATE: LATCH + AND
//=============================================================================

// Enable clock gate during scan shift
// (the gate itself is checked with the scan capture cycle)
wire    enable_in =   (enable | scan_enable);

// LATCH the enable signal
reg     enable_latch;
always @(clk or enable_in)
  if (~clk)
    enable_latch <= enable_in;

// AND gate
assign  gclk      =  (clk & enable_latch);


endmodule // omsp_clock_gate
module  omsp_wakeup_cell (

// OUTPUTs
    wkup_out,                  // Wakup signal (asynchronous)

// INPUTs
    scan_clk,                  // Scan clock
    scan_mode,                 // Scan mode
    scan_rst,                  // Scan reset
    wkup_clear,                // Glitch free wakeup event clear
    wkup_event                 // Glitch free asynchronous wakeup event
);

// OUTPUTs
//=========
output         wkup_out;       // Wakup signal (asynchronous)

// INPUTs
//=========
input          scan_clk;       // Scan clock
input          scan_mode;      // Scan mode
input          scan_rst;       // Scan reset
input          wkup_clear;     // Glitch free wakeup event clear
input          wkup_event;     // Glitch free asynchronous wakeup event


//=============================================================================
// 1)  AND GATE
//=============================================================================

// Scan stuff for the ASIC mode
`ifdef ASIC
   wire wkup_rst;
   omsp_scan_mux scan_mux_rst (
                               .scan_mode    (scan_mode),
                               .data_in_scan (scan_rst),
                               .data_in_func (wkup_clear),
                               .data_out     (wkup_rst)
   );

   wire wkup_clk;
   omsp_scan_mux scan_mux_clk (
                               .scan_mode    (scan_mode),
                               .data_in_scan (scan_clk),
                               .data_in_func (wkup_event),
                               .data_out     (wkup_clk)
   );

`else
   wire wkup_rst  =  wkup_clear;
   wire wkup_clk  =  wkup_event;
`endif

// Wakeup capture
reg    wkup_out;
always @(posedge wkup_clk or posedge wkup_rst)
  if (wkup_rst) wkup_out <= 1'b0;
  else          wkup_out <= 1'b1;


endmodule // omsp_wakeup_cell
module  omsp_and_gate (

// OUTPUTs
    y,                         // AND gate output

// INPUTs
    a,                         // AND gate input A
    b                          // AND gate input B
);

// OUTPUTs
//=========
output         y;              // AND gate output

// INPUTs
//=========
input          a;              // AND gate input A
input          b;              // AND gate input B


//=============================================================================
// 1)  SOME COMMENTS ON THIS MODULE
//=============================================================================
//
//    In its ASIC version, some combinatorial pathes of the openMSP430 are
// sensitive to glitches, in particular the ones generating the wakeup
// signals.
//    To prevent synthesis from optmizing combinatorial clouds into glitchy
// logic, this AND gate module has been instanciated in the critical places.
//
//    Make sure that synthesis doesn't ungroup this module. As an alternative,
// a standard cell from the library could also be directly instanciated here
// (don't forget the "dont_touch" attribute)
//
//
//=============================================================================
// 2)  AND GATE
//=============================================================================

assign  y  =  a & b;


endmodule // omsp_and_gate
module  omsp_sync_reset (

// OUTPUTs
    rst_s,                        // Synchronized reset

// INPUTs
    clk,                          // Receiving clock
    rst_a                         // Asynchronous reset
);

// OUTPUTs
//=========
output              rst_s;        // Synchronized reset

// INPUTs
//=========
input               clk;          // Receiving clock
input               rst_a;        // Asynchronous reset


//=============================================================================
// 1)  SYNCHRONIZER
//=============================================================================

reg    [1:0] data_sync;

always @(posedge clk or posedge rst_a)
  if (rst_a) data_sync <=  2'b11;
  else       data_sync <=  {data_sync[0], 1'b0};

assign       rst_s      =   data_sync[1];


endmodule // omsp_sync_reset
module  omsp_scan_mux (

// OUTPUTs
    data_out,                      // Scan mux data output

// INPUTs
    data_in_scan,                  // Selected data input for scan mode
    data_in_func,                  // Selected data input for functional mode
    scan_mode                      // Scan mode
);

// OUTPUTs
//=========
output              data_out;      // Scan mux data output

// INPUTs
//=========
input               data_in_scan;  // Selected data input for scan mode
input               data_in_func;  // Selected data input for functional mode
input               scan_mode;     // Scan mode


//=============================================================================
// 1)  SCAN MUX
//=============================================================================

assign  data_out  =  scan_mode ? data_in_scan : data_in_func;


endmodule // omsp_scan_mux
module  omsp_sync_cell (

// OUTPUTs
    data_out,                      // Synchronized data output

// INPUTs
    clk,                           // Receiving clock
    data_in,                       // Asynchronous data input
    rst                            // Receiving reset (active high)
);

// OUTPUTs
//=========
output              data_out;      // Synchronized data output

// INPUTs
//=========
input               clk;          // Receiving clock
input               data_in;      // Asynchronous data input
input               rst;          // Receiving reset (active high)


//=============================================================================
// 1)  SYNCHRONIZER
//=============================================================================

reg  [1:0] data_sync;

always @(posedge clk or posedge rst)
  if (rst) data_sync <=  2'b00;
  else     data_sync <=  {data_sync[0], data_in};

assign     data_out   =   data_sync[1];


endmodule // omsp_sync_cell
module dmem_128B(WD,RD,WEN,REN,WADDR,RADDR,RWCLK,RESET);
input [7:0] WD;
output [7:0] RD;
input  WEN, REN;
input [6:0] WADDR, RADDR;
input RWCLK;
input RESET;

    wire VCC, GND;
    
    VCC VCC_1_net(.Y(VCC));
    GND GND_1_net(.Y(GND));
    RAM4K9 dmem_128B_R0C0(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9(
        GND), .ADDRA8(GND), .ADDRA7(GND), .ADDRA6(WADDR[6]), 
        .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), .ADDRA3(WADDR[3]), 
        .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), .ADDRA0(WADDR[0]), 
        .ADDRB11(GND), .ADDRB10(GND), .ADDRB9(GND), .ADDRB8(GND), 
        .ADDRB7(GND), .ADDRB6(RADDR[6]), .ADDRB5(RADDR[5]), 
        .ADDRB4(RADDR[4]), .ADDRB3(RADDR[3]), .ADDRB2(RADDR[2]), 
        .ADDRB1(RADDR[1]), .ADDRB0(RADDR[0]), .DINA8(GND), .DINA7(
        WD[7]), .DINA6(WD[6]), .DINA5(WD[5]), .DINA4(WD[4]), 
        .DINA3(WD[3]), .DINA2(WD[2]), .DINA1(WD[1]), .DINA0(WD[0])
        , .DINB8(GND), .DINB7(GND), .DINB6(GND), .DINB5(GND), 
        .DINB4(GND), .DINB3(GND), .DINB2(GND), .DINB1(GND), 
        .DINB0(GND), .WIDTHA0(VCC), .WIDTHA1(VCC), .WIDTHB0(VCC), 
        .WIDTHB1(VCC), .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), 
        .WMODEB(GND), .BLKA(WEN), .BLKB(REN), .WENA(GND), .WENB(
        VCC), .CLKA(RWCLK), .CLKB(RWCLK), .RESET(RESET), .DOUTA8(), 
        .DOUTA7(), .DOUTA6(), .DOUTA5(), .DOUTA4(), .DOUTA3(), 
        .DOUTA2(), .DOUTA1(), .DOUTA0(), .DOUTB8(), .DOUTB7(RD[7])
        , .DOUTB6(RD[6]), .DOUTB5(RD[5]), .DOUTB4(RD[4]), .DOUTB3(
        RD[3]), .DOUTB2(RD[2]), .DOUTB1(RD[1]), .DOUTB0(RD[0]));
    
endmodule
module  DAC121S101 (
 
// OUTPUTs
    vout,                           // Peripheral data output
 
// INPUTs
    din,                            // SPI Serial Data
    sclk,                           // SPI Serial Clock
    sync_n                          // SPI Frame synchronization signal (low active)
);

// OUTPUTs
//=========
output       [11:0] vout;           // Peripheral data output
 
// INPUTs
//=========
input               din;            // SPI Serial Data
input               sclk;           // SPI Serial Clock
input               sync_n;         // SPI Frame synchronization signal (low active)
 

//============================================================================
// 1) SPI INTERFACE
//============================================================================

// SPI Transfer Start detection
reg  sync_dly_n;
always @ (negedge sclk)
  sync_dly_n <= sync_n;

wire spi_tfx_start = ~sync_n & sync_dly_n;
   

// Data counter
reg [3:0] spi_cnt;
wire      spi_cnt_done = (spi_cnt==4'hf);
always @ (negedge sclk)
  if (sync_n)              spi_cnt <=  4'hf;
  else if (spi_tfx_start)  spi_cnt <=  4'he;
  else if (~spi_cnt_done)  spi_cnt <=  spi_cnt-1;

wire spi_tfx_done = sync_n & ~sync_dly_n & spi_cnt_done;

   
// Value to be shifted in
reg  [15:0] dac_shifter;
always @ (negedge sclk)
  dac_shifter <=  {dac_shifter[14:0], din};


// DAC Output value
reg  [11:0] vout;
always @ (negedge sclk)
  if (spi_tfx_done)
    vout <=  dac_shifter[11:0];


endmodule // DAC121S101
module rom_8x2k_lo(
	addr,
	clk,
	din,
	dout,
	en,
	we);


input [10 : 0] addr;
input clk;
input [7 : 0] din;
output [7 : 0] dout;
input en;
input we;

// synthesis translate_off

      BLKMEMSP_V6_2 #(
		.c_addr_width(11),
		.c_default_data("0"),
		.c_depth(2048),
		.c_enable_rlocs(0),
		.c_has_default_data(1),
		.c_has_din(1),
		.c_has_en(1),
		.c_has_limit_data_pitch(0),
		.c_has_nd(0),
		.c_has_rdy(0),
		.c_has_rfd(0),
		.c_has_sinit(0),
		.c_has_we(1),
		.c_limit_data_pitch(18),
		.c_mem_init_file("mif_file_16_1"),
		.c_pipe_stages(0),
		.c_reg_inputs(0),
		.c_sinit_value("0"),
		.c_width(8),
		.c_write_mode(0),
		.c_ybottom_addr("0"),
		.c_yclk_is_rising(1),
		.c_yen_is_high(0),
		.c_yhierarchy("hierarchy1"),
		.c_ymake_bmm(0),
		.c_yprimitive_type("16kx1"),
		.c_ysinit_is_high(1),
		.c_ytop_addr("1024"),
		.c_yuse_single_primitive(0),
		.c_ywe_is_high(0),
		.c_yydisable_warnings(1))
	inst (
		.ADDR(addr),
		.CLK(clk),
		.DIN(din),
		.DOUT(dout),
		.EN(en),
		.WE(we),
		.ND(),
		.RFD(),
		.RDY(),
		.SINIT());


// synthesis translate_on

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of rom_8x2k_lo is "black_box"

endmodule
module rom_8x2k_hi(
	addr,
	clk,
	din,
	dout,
	en,
	we);


input [10 : 0] addr;
input clk;
input [7 : 0] din;
output [7 : 0] dout;
input en;
input we;

// synthesis translate_off

      BLKMEMSP_V6_2 #(
		.c_addr_width(11),
		.c_default_data("0"),
		.c_depth(2048),
		.c_enable_rlocs(0),
		.c_has_default_data(1),
		.c_has_din(1),
		.c_has_en(1),
		.c_has_limit_data_pitch(0),
		.c_has_nd(0),
		.c_has_rdy(0),
		.c_has_rfd(0),
		.c_has_sinit(0),
		.c_has_we(1),
		.c_limit_data_pitch(18),
		.c_mem_init_file("mif_file_16_1"),
		.c_pipe_stages(0),
		.c_reg_inputs(0),
		.c_sinit_value("0"),
		.c_width(8),
		.c_write_mode(0),
		.c_ybottom_addr("0"),
		.c_yclk_is_rising(1),
		.c_yen_is_high(0),
		.c_yhierarchy("hierarchy1"),
		.c_ymake_bmm(0),
		.c_yprimitive_type("16kx1"),
		.c_ysinit_is_high(1),
		.c_ytop_addr("1024"),
		.c_yuse_single_primitive(0),
		.c_ywe_is_high(0),
		.c_yydisable_warnings(1))
	inst (
		.ADDR(addr),
		.CLK(clk),
		.DIN(din),
		.DOUT(dout),
		.EN(en),
		.WE(we),
		.ND(),
		.RFD(),
		.RDY(),
		.SINIT());


// synthesis translate_on

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of rom_8x2k_hi is "black_box"

endmodule
module ram_8x512_lo(
	addr,
	clk,
	din,
	dout,
	en,
	we);


input [8 : 0] addr;
input clk;
input [7 : 0] din;
output [7 : 0] dout;
input en;
input we;

// synthesis translate_off

      BLKMEMSP_V6_2 #(
		.c_addr_width(9),
		.c_default_data("0"),
		.c_depth(512),
		.c_enable_rlocs(0),
		.c_has_default_data(1),
		.c_has_din(1),
		.c_has_en(1),
		.c_has_limit_data_pitch(0),
		.c_has_nd(0),
		.c_has_rdy(0),
		.c_has_rfd(0),
		.c_has_sinit(0),
		.c_has_we(1),
		.c_limit_data_pitch(18),
		.c_mem_init_file("mif_file_16_1"),
		.c_pipe_stages(0),
		.c_reg_inputs(0),
		.c_sinit_value("0"),
		.c_width(8),
		.c_write_mode(0),
		.c_ybottom_addr("0"),
		.c_yclk_is_rising(1),
		.c_yen_is_high(0),
		.c_yhierarchy("hierarchy1"),
		.c_ymake_bmm(0),
		.c_yprimitive_type("16kx1"),
		.c_ysinit_is_high(1),
		.c_ytop_addr("1024"),
		.c_yuse_single_primitive(0),
		.c_ywe_is_high(0),
		.c_yydisable_warnings(1))
	inst (
		.ADDR(addr),
		.CLK(clk),
		.DIN(din),
		.DOUT(dout),
		.EN(en),
		.WE(we),
		.ND(),
		.RFD(),
		.RDY(),
		.SINIT());


// synthesis translate_on

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of ram_8x512_lo is "black_box"

endmodule
module ram_8x512_hi(
	addr,
	clk,
	din,
	dout,
	en,
	we);


input [8 : 0] addr;
input clk;
input [7 : 0] din;
output [7 : 0] dout;
input en;
input we;

// synthesis translate_off

      BLKMEMSP_V6_2 #(
		.c_addr_width(9),
		.c_default_data("0"),
		.c_depth(512),
		.c_enable_rlocs(0),
		.c_has_default_data(1),
		.c_has_din(1),
		.c_has_en(1),
		.c_has_limit_data_pitch(0),
		.c_has_nd(0),
		.c_has_rdy(0),
		.c_has_rfd(0),
		.c_has_sinit(0),
		.c_has_we(1),
		.c_limit_data_pitch(18),
		.c_mem_init_file("mif_file_16_1"),
		.c_pipe_stages(0),
		.c_reg_inputs(0),
		.c_sinit_value("0"),
		.c_width(8),
		.c_write_mode(0),
		.c_ybottom_addr("0"),
		.c_yclk_is_rising(1),
		.c_yen_is_high(0),
		.c_yhierarchy("hierarchy1"),
		.c_ymake_bmm(0),
		.c_yprimitive_type("16kx1"),
		.c_ysinit_is_high(1),
		.c_ytop_addr("1024"),
		.c_yuse_single_primitive(0),
		.c_ywe_is_high(0),
		.c_yydisable_warnings(1))
	inst (
		.ADDR(addr),
		.CLK(clk),
		.DIN(din),
		.DOUT(dout),
		.EN(en),
		.WE(we),
		.ND(),
		.RFD(),
		.RDY(),
		.SINIT());


// synthesis translate_on

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of ram_8x512_hi is "black_box"

endmodule
module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

    wire GSR;
    wire GTS;
    wire PRLD;

    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
module chipscope_icon(
    CONTROL0);


inout [35 : 0] CONTROL0;

endmodule
module chipscope_ila(
    CONTROL,
    CLK,
    TRIG0);


inout [35 : 0] CONTROL;
input CLK;
input [23 : 0] TRIG0;

endmodule
module ram_16x1k_sp (
  clka,
  ena,
  wea,
  addra,
  dina,
  douta
);

  input clka;
  input ena;
  input [1 : 0] wea;
  input [9 : 0] addra;
  input [15 : 0] dina;
  output [15 : 0] douta;

  // WARNING: This file provides a module declaration only, it does not support
  //          direct instantiation. Please use an instantiation template (VEO) to
  //          instantiate the IP within a design.

endmodule