dakies/OSS_Verilog huggingface dataset:
module axi4_retime_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
    parameter WIDTH   = 8,
    parameter DEPTH   = 2,
    parameter ADDR_W  = 1
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
    // Inputs
     input               clk_i
    ,input               rst_i
    ,input  [WIDTH-1:0]  data_in_i
    ,input               push_i
    ,input               pop_i

    // Outputs
    ,output [WIDTH-1:0]  data_out_o
    ,output              accept_o
    ,output              valid_o
);

//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;

//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [WIDTH-1:0]   ram_q[DEPTH-1:0];
reg [ADDR_W-1:0]  rd_ptr_q;
reg [ADDR_W-1:0]  wr_ptr_q;
reg [COUNT_W-1:0] count_q;

//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @ (posedge clk_i )
if (rst_i)
begin
    count_q   <= {(COUNT_W) {1'b0}};
    rd_ptr_q  <= {(ADDR_W) {1'b0}};
    wr_ptr_q  <= {(ADDR_W) {1'b0}};
end
else
begin
    // Push
    if (push_i & accept_o)
    begin
        ram_q[wr_ptr_q] <= data_in_i;
        wr_ptr_q        <= wr_ptr_q + 1;
    end

    // Pop
    if (pop_i & valid_o)
        rd_ptr_q      <= rd_ptr_q + 1;

    // Count up
    if ((push_i & accept_o) & ~(pop_i & valid_o))
        count_q <= count_q + 1;
    // Count down
    else if (~(push_i & accept_o) & (pop_i & valid_o))
        count_q <= count_q - 1;
end

//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign valid_o       = (count_q != 0);
assign accept_o      = (count_q != DEPTH);
/* verilator lint_on WIDTH */

assign data_out_o    = ram_q[rd_ptr_q];



endmodule
module axi4_cdc_fifo6_ram_dp_32_5
(
    // Inputs
     input           clk0_i
    ,input           rst0_i
    ,input  [ 4:0]  addr0_i
    ,input  [ 5:0]  data0_i
    ,input           wr0_i
    ,input           clk1_i
    ,input           rst1_i
    ,input  [ 4:0]  addr1_i
    ,input  [ 5:0]  data1_i
    ,input           wr1_i

    // Outputs
    ,output [ 5:0]  data0_o
    ,output [ 5:0]  data1_o
);

/* verilator lint_off MULTIDRIVEN */
reg [5:0]   ram [31:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */

reg [5:0] ram_read0_q;
reg [5:0] ram_read1_q;

// Synchronous write
always @ (posedge clk0_i)
begin
    if (wr0_i)
        ram[addr0_i] <= data0_i;

    ram_read0_q <= ram[addr0_i];
end

always @ (posedge clk1_i)
begin
    if (wr1_i)
        ram[addr1_i] <= data1_i;

    ram_read1_q <= ram[addr1_i];
end

assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;

endmodule
module axi4_cdc_fifo6_resync_bus
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
    parameter WIDTH     = 4
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
    input              wr_clk_i,
    input              wr_rst_i,
    input              wr_i,
    input  [WIDTH-1:0] wr_data_i,
    output             wr_busy_o,

    input              rd_clk_i,
    input              rd_rst_i,
    output [WIDTH-1:0] rd_data_o
);

wire rd_toggle_w;
wire wr_toggle_w;

//-----------------------------------------------------------------
// Write
//-----------------------------------------------------------------
wire write_req_w = wr_i && !wr_busy_o;

// Write storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] wr_buffer_q;

always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
    wr_buffer_q <= {(WIDTH){1'b0}};
else if (write_req_w)
    wr_buffer_q <= wr_data_i;

reg wr_toggle_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
    wr_toggle_q <= 1'b0;
else if (write_req_w)
    wr_toggle_q <= ~wr_toggle_q;

reg wr_busy_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
    wr_busy_q <= 1'b0;
else if (write_req_w)
    wr_busy_q <= 1'b1;
else if (wr_toggle_q == wr_toggle_w)
    wr_busy_q <= 1'b0;

assign wr_busy_o = wr_busy_q;

//-----------------------------------------------------------------
// Write -> Read request
//-----------------------------------------------------------------
axi4_cdc_fifo6_resync
u_sync_wr_toggle
(
    .clk_i(rd_clk_i),
    .rst_i(rd_rst_i),
    .async_i(wr_toggle_q),
    .sync_o(rd_toggle_w)
);

//-----------------------------------------------------------------
// Read
//-----------------------------------------------------------------
reg rd_toggle_q;
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
    rd_toggle_q <= 1'b0;
else
    rd_toggle_q <= rd_toggle_w;

// Read storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] rd_buffer_q;

always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
    rd_buffer_q <= {(WIDTH){1'b0}};
else if (rd_toggle_q != rd_toggle_w)
    rd_buffer_q <= wr_buffer_q; // Capture from other domain

assign rd_data_o = rd_buffer_q;

//-----------------------------------------------------------------
// Read->Write response
//-----------------------------------------------------------------
axi4_cdc_fifo6_resync
u_sync_rd_toggle
(
    .clk_i(wr_clk_i),
    .rst_i(wr_rst_i),
    .async_i(rd_toggle_q),
    .sync_o(wr_toggle_w)
);

endmodule
module axi4_cdc_fifo6_resync
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
    parameter RESET_VAL = 1'b0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
    input  clk_i,
    input  rst_i,
    input  async_i,
    output sync_o
);

(* ASYNC_REG = "TRUE" *) reg sync_ms;
(* ASYNC_REG = "TRUE" *) reg sync_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
    sync_ms  <= RESET_VAL;
    sync_q   <= RESET_VAL;
end
else
begin
    sync_ms  <= async_i;
    sync_q   <= sync_ms;
end

assign sync_o = sync_q;


endmodule
module axi4_cdc_fifo46_ram_dp_32_5
(
    // Inputs
     input           clk0_i
    ,input           rst0_i
    ,input  [ 4:0]  addr0_i
    ,input  [ 45:0]  data0_i
    ,input           wr0_i
    ,input           clk1_i
    ,input           rst1_i
    ,input  [ 4:0]  addr1_i
    ,input  [ 45:0]  data1_i
    ,input           wr1_i

    // Outputs
    ,output [ 45:0]  data0_o
    ,output [ 45:0]  data1_o
);

/* verilator lint_off MULTIDRIVEN */
reg [45:0]   ram [31:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */

reg [45:0] ram_read0_q;
reg [45:0] ram_read1_q;

// Synchronous write
always @ (posedge clk0_i)
begin
    if (wr0_i)
        ram[addr0_i] <= data0_i;

    ram_read0_q <= ram[addr0_i];
end

always @ (posedge clk1_i)
begin
    if (wr1_i)
        ram[addr1_i] <= data1_i;

    ram_read1_q <= ram[addr1_i];
end

assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;

endmodule
module axi4_cdc_fifo46_resync_bus
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
    parameter WIDTH     = 4
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
    input              wr_clk_i,
    input              wr_rst_i,
    input              wr_i,
    input  [WIDTH-1:0] wr_data_i,
    output             wr_busy_o,

    input              rd_clk_i,
    input              rd_rst_i,
    output [WIDTH-1:0] rd_data_o
);

wire rd_toggle_w;
wire wr_toggle_w;

//-----------------------------------------------------------------
// Write
//-----------------------------------------------------------------
wire write_req_w = wr_i && !wr_busy_o;

// Write storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] wr_buffer_q;

always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
    wr_buffer_q <= {(WIDTH){1'b0}};
else if (write_req_w)
    wr_buffer_q <= wr_data_i;

reg wr_toggle_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
    wr_toggle_q <= 1'b0;
else if (write_req_w)
    wr_toggle_q <= ~wr_toggle_q;

reg wr_busy_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
    wr_busy_q <= 1'b0;
else if (write_req_w)
    wr_busy_q <= 1'b1;
else if (wr_toggle_q == wr_toggle_w)
    wr_busy_q <= 1'b0;

assign wr_busy_o = wr_busy_q;

//-----------------------------------------------------------------
// Write -> Read request
//-----------------------------------------------------------------
axi4_cdc_fifo46_resync
u_sync_wr_toggle
(
    .clk_i(rd_clk_i),
    .rst_i(rd_rst_i),
    .async_i(wr_toggle_q),
    .sync_o(rd_toggle_w)
);

//-----------------------------------------------------------------
// Read
//-----------------------------------------------------------------
reg rd_toggle_q;
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
    rd_toggle_q <= 1'b0;
else
    rd_toggle_q <= rd_toggle_w;

// Read storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] rd_buffer_q;

always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
    rd_buffer_q <= {(WIDTH){1'b0}};
else if (rd_toggle_q != rd_toggle_w)
    rd_buffer_q <= wr_buffer_q; // Capture from other domain

assign rd_data_o = rd_buffer_q;

//-----------------------------------------------------------------
// Read->Write response
//-----------------------------------------------------------------
axi4_cdc_fifo46_resync
u_sync_rd_toggle
(
    .clk_i(wr_clk_i),
    .rst_i(wr_rst_i),
    .async_i(rd_toggle_q),
    .sync_o(wr_toggle_w)
);

endmodule
module axi4_cdc_fifo46_resync
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
    parameter RESET_VAL = 1'b0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
    input  clk_i,
    input  rst_i,
    input  async_i,
    output sync_o
);

(* ASYNC_REG = "TRUE" *) reg sync_ms;
(* ASYNC_REG = "TRUE" *) reg sync_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
    sync_ms  <= RESET_VAL;
    sync_q   <= RESET_VAL;
end
else
begin
    sync_ms  <= async_i;
    sync_q   <= sync_ms;
end

assign sync_o = sync_q;


endmodule
module axi4_cdc_fifo37_ram_dp_32_5
(
    // Inputs
     input           clk0_i
    ,input           rst0_i
    ,input  [ 4:0]  addr0_i
    ,input  [ 36:0]  data0_i
    ,input           wr0_i
    ,input           clk1_i
    ,input           rst1_i
    ,input  [ 4:0]  addr1_i
    ,input  [ 36:0]  data1_i
    ,input           wr1_i

    // Outputs
    ,output [ 36:0]  data0_o
    ,output [ 36:0]  data1_o
);

/* verilator lint_off MULTIDRIVEN */
reg [36:0]   ram [31:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */

reg [36:0] ram_read0_q;
reg [36:0] ram_read1_q;

// Synchronous write
always @ (posedge clk0_i)
begin
    if (wr0_i)
        ram[addr0_i] <= data0_i;

    ram_read0_q <= ram[addr0_i];
end

always @ (posedge clk1_i)
begin
    if (wr1_i)
        ram[addr1_i] <= data1_i;

    ram_read1_q <= ram[addr1_i];
end

assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;

endmodule
module axi4_cdc_fifo37_resync_bus
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
    parameter WIDTH     = 4
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
    input              wr_clk_i,
    input              wr_rst_i,
    input              wr_i,
    input  [WIDTH-1:0] wr_data_i,
    output             wr_busy_o,

    input              rd_clk_i,
    input              rd_rst_i,
    output [WIDTH-1:0] rd_data_o
);

wire rd_toggle_w;
wire wr_toggle_w;

//-----------------------------------------------------------------
// Write
//-----------------------------------------------------------------
wire write_req_w = wr_i && !wr_busy_o;

// Write storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] wr_buffer_q;

always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
    wr_buffer_q <= {(WIDTH){1'b0}};
else if (write_req_w)
    wr_buffer_q <= wr_data_i;

reg wr_toggle_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
    wr_toggle_q <= 1'b0;
else if (write_req_w)
    wr_toggle_q <= ~wr_toggle_q;

reg wr_busy_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
    wr_busy_q <= 1'b0;
else if (write_req_w)
    wr_busy_q <= 1'b1;
else if (wr_toggle_q == wr_toggle_w)
    wr_busy_q <= 1'b0;

assign wr_busy_o = wr_busy_q;

//-----------------------------------------------------------------
// Write -> Read request
//-----------------------------------------------------------------
axi4_cdc_fifo37_resync
u_sync_wr_toggle
(
    .clk_i(rd_clk_i),
    .rst_i(rd_rst_i),
    .async_i(wr_toggle_q),
    .sync_o(rd_toggle_w)
);

//-----------------------------------------------------------------
// Read
//-----------------------------------------------------------------
reg rd_toggle_q;
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
    rd_toggle_q <= 1'b0;
else
    rd_toggle_q <= rd_toggle_w;

// Read storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] rd_buffer_q;

always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
    rd_buffer_q <= {(WIDTH){1'b0}};
else if (rd_toggle_q != rd_toggle_w)
    rd_buffer_q <= wr_buffer_q; // Capture from other domain

assign rd_data_o = rd_buffer_q;

//-----------------------------------------------------------------
// Read->Write response
//-----------------------------------------------------------------
axi4_cdc_fifo37_resync
u_sync_rd_toggle
(
    .clk_i(wr_clk_i),
    .rst_i(wr_rst_i),
    .async_i(rd_toggle_q),
    .sync_o(wr_toggle_w)
);

endmodule
module axi4_cdc_fifo37_resync
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
    parameter RESET_VAL = 1'b0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
    input  clk_i,
    input  rst_i,
    input  async_i,
    output sync_o
);

(* ASYNC_REG = "TRUE" *) reg sync_ms;
(* ASYNC_REG = "TRUE" *) reg sync_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
    sync_ms  <= RESET_VAL;
    sync_q   <= RESET_VAL;
end
else
begin
    sync_ms  <= async_i;
    sync_q   <= sync_ms;
end

assign sync_o = sync_q;


endmodule
module capture_rle_cdc_ram_dp_32_5
(
    // Inputs
     input           clk0_i
    ,input           rst0_i
    ,input  [ 4:0]  addr0_i
    ,input  [ 31:0]  data0_i
    ,input           wr0_i
    ,input           clk1_i
    ,input           rst1_i
    ,input  [ 4:0]  addr1_i
    ,input  [ 31:0]  data1_i
    ,input           wr1_i

    // Outputs
    ,output [ 31:0]  data0_o
    ,output [ 31:0]  data1_o
);

/* verilator lint_off MULTIDRIVEN */
reg [31:0]   ram [31:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */

reg [31:0] ram_read0_q;
reg [31:0] ram_read1_q;

// Synchronous write
always @ (posedge clk0_i)
begin
    if (wr0_i)
        ram[addr0_i] <= data0_i;

    ram_read0_q <= ram[addr0_i];
end

always @ (posedge clk1_i)
begin
    if (wr1_i)
        ram[addr1_i] <= data1_i;

    ram_read1_q <= ram[addr1_i];
end

assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;

endmodule
module capture_rle_cdc_resync_bus
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
    parameter WIDTH     = 4
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
    input              wr_clk_i,
    input              wr_rst_i,
    input              wr_i,
    input  [WIDTH-1:0] wr_data_i,
    output             wr_busy_o,

    input              rd_clk_i,
    input              rd_rst_i,
    output [WIDTH-1:0] rd_data_o
);

wire rd_toggle_w;
wire wr_toggle_w;

//-----------------------------------------------------------------
// Write
//-----------------------------------------------------------------
wire write_req_w = wr_i && !wr_busy_o;

// Write storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] wr_buffer_q;

always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
    wr_buffer_q <= {(WIDTH){1'b0}};
else if (write_req_w)
    wr_buffer_q <= wr_data_i;

reg wr_toggle_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
    wr_toggle_q <= 1'b0;
else if (write_req_w)
    wr_toggle_q <= ~wr_toggle_q;

reg wr_busy_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
    wr_busy_q <= 1'b0;
else if (write_req_w)
    wr_busy_q <= 1'b1;
else if (wr_toggle_q == wr_toggle_w)
    wr_busy_q <= 1'b0;

assign wr_busy_o = wr_busy_q;

//-----------------------------------------------------------------
// Write -> Read request
//-----------------------------------------------------------------
capture_rle_cdc_resync
u_sync_wr_toggle
(
    .clk_i(rd_clk_i),
    .rst_i(rd_rst_i),
    .async_i(wr_toggle_q),
    .sync_o(rd_toggle_w)
);

//-----------------------------------------------------------------
// Read
//-----------------------------------------------------------------
reg rd_toggle_q;
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
    rd_toggle_q <= 1'b0;
else
    rd_toggle_q <= rd_toggle_w;

// Read storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] rd_buffer_q;

always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
    rd_buffer_q <= {(WIDTH){1'b0}};
else if (rd_toggle_q != rd_toggle_w)
    rd_buffer_q <= wr_buffer_q; // Capture from other domain

assign rd_data_o = rd_buffer_q;

//-----------------------------------------------------------------
// Read->Write response
//-----------------------------------------------------------------
capture_rle_cdc_resync
u_sync_rd_toggle
(
    .clk_i(wr_clk_i),
    .rst_i(wr_rst_i),
    .async_i(rd_toggle_q),
    .sync_o(wr_toggle_w)
);

endmodule
module capture_rle_cdc_resync
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
    parameter RESET_VAL = 1'b0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
    input  clk_i,
    input  rst_i,
    input  async_i,
    output sync_o
);

(* ASYNC_REG = "TRUE" *) reg sync_ms;
(* ASYNC_REG = "TRUE" *) reg sync_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
    sync_ms  <= RESET_VAL;
    sync_q   <= RESET_VAL;
end
else
begin
    sync_ms  <= async_i;
    sync_q   <= sync_ms;
end

assign sync_o = sync_q;


endmodule
module logic_capture_mem_axi_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
    parameter WIDTH   = 8,
    parameter DEPTH   = 4,
    parameter ADDR_W  = 2
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
    // Inputs
     input               clk_i
    ,input               rst_i
    ,input  [WIDTH-1:0]  data_in_i
    ,input               push_i
    ,input               pop_i

    // Outputs
    ,output [WIDTH-1:0]  data_out_o
    ,output              accept_o
    ,output              valid_o
);

//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;

//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [WIDTH-1:0]   ram_q[DEPTH-1:0];
reg [ADDR_W-1:0]  rd_ptr_q;
reg [ADDR_W-1:0]  wr_ptr_q;
reg [COUNT_W-1:0] count_q;

//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @ (posedge clk_i )
if (rst_i)
begin
    count_q   <= {(COUNT_W) {1'b0}};
    rd_ptr_q  <= {(ADDR_W) {1'b0}};
    wr_ptr_q  <= {(ADDR_W) {1'b0}};
end
else
begin
    // Push
    if (push_i & accept_o)
    begin
        ram_q[wr_ptr_q] <= data_in_i;
        wr_ptr_q        <= wr_ptr_q + 1;
    end

    // Pop
    if (pop_i & valid_o)
        rd_ptr_q      <= rd_ptr_q + 1;

    // Count up
    if ((push_i & accept_o) & ~(pop_i & valid_o))
        count_q <= count_q + 1;
    // Count down
    else if (~(push_i & accept_o) & (pop_i & valid_o))
        count_q <= count_q - 1;
end

//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign valid_o       = (count_q != 0);
assign accept_o      = (count_q != DEPTH);
/* verilator lint_on WIDTH */

assign data_out_o    = ram_q[rd_ptr_q];



endmodule
module logic_capture_mem_track_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
    parameter WIDTH   = 8,
    parameter DEPTH   = 4,
    parameter ADDR_W  = 2
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
    // Inputs
     input               clk_i
    ,input               rst_i
    ,input  [WIDTH-1:0]  data_in_i
    ,input               push_i
    ,input               pop_i

    // Outputs
    ,output [WIDTH-1:0]  data_out_o
    ,output              accept_o
    ,output              valid_o
);

//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;

//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [WIDTH-1:0]   ram_q[DEPTH-1:0];
reg [ADDR_W-1:0]  rd_ptr_q;
reg [ADDR_W-1:0]  wr_ptr_q;
reg [COUNT_W-1:0] count_q;

//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @ (posedge clk_i )
if (rst_i)
begin
    count_q   <= {(COUNT_W) {1'b0}};
    rd_ptr_q  <= {(ADDR_W) {1'b0}};
    wr_ptr_q  <= {(ADDR_W) {1'b0}};
end
else
begin
    // Push
    if (push_i & accept_o)
    begin
        ram_q[wr_ptr_q] <= data_in_i;
        wr_ptr_q        <= wr_ptr_q + 1;
    end

    // Pop
    if (pop_i & valid_o)
        rd_ptr_q      <= rd_ptr_q + 1;

    // Count up
    if ((push_i & accept_o) & ~(pop_i & valid_o))
        count_q <= count_q + 1;
    // Count down
    else if (~(push_i & accept_o) & (pop_i & valid_o))
        count_q <= count_q - 1;
end

//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign valid_o       = (count_q != 0);
assign accept_o      = (count_q != DEPTH);
/* verilator lint_on WIDTH */

assign data_out_o    = ram_q[rd_ptr_q];

endmodule
module logic_capture_fifo
(
    // Inputs
     input           clk_i
    ,input           rst_i
    ,input  [ 31:0]  data_in_i
    ,input           push_i
    ,input           pop_i

    // Outputs
    ,output [ 31:0]  data_out_o
    ,output          accept_o
    ,output          valid_o
);

//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [8:0]   rd_ptr_q;
reg [8:0]   wr_ptr_q;

//-----------------------------------------------------------------
// Write Side
//-----------------------------------------------------------------
wire [8:0] write_next_w = wr_ptr_q + 9'd1;

wire full_w = (write_next_w == rd_ptr_q);

always @ (posedge clk_i )
if (rst_i)
    wr_ptr_q <= 9'b0;
// Push
else if (push_i & !full_w)
    wr_ptr_q <= write_next_w;

//-----------------------------------------------------------------
// Read Side
//-----------------------------------------------------------------
wire read_ok_w = (wr_ptr_q != rd_ptr_q);
reg  rd_q;

always @ (posedge clk_i )
if (rst_i)
    rd_q <= 1'b0;
else
    rd_q <= read_ok_w;

always @ (posedge clk_i )
if (rst_i)
    rd_ptr_q     <= 9'b0;
// Read address increment
else if (read_ok_w && ((!valid_o) || (valid_o && pop_i)))
    rd_ptr_q <= rd_ptr_q + 9'd1;

//-------------------------------------------------------------------
// Read Skid Buffer
//-------------------------------------------------------------------
reg                rd_skid_q;
reg [31:0] rd_skid_data_q;

always @ (posedge clk_i )
if (rst_i)
begin
    rd_skid_q <= 1'b0;
    rd_skid_data_q <= 32'b0;
end
else if (valid_o && !pop_i)
begin
    rd_skid_q      <= 1'b1;
    rd_skid_data_q <= data_out_o;
end
else
begin
    rd_skid_q      <= 1'b0;
    rd_skid_data_q <= 32'b0;
end

//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
assign valid_o       = rd_skid_q | rd_q;
assign accept_o      = !full_w;

//-------------------------------------------------------------------
// Dual port RAM
//-------------------------------------------------------------------
wire [31:0] data_out_w;

logic_capture_fifo_dp_512_9
u_ram
(
    // Inputs
    .clk0_i(clk_i),
    .rst0_i(rst_i),
    .clk1_i(clk_i),
    .rst1_i(rst_i),

    // Write side
    .addr0_i(wr_ptr_q),
    .wr0_i(push_i & accept_o),
    .data0_i(data_in_i),
    .data0_o(),

    // Read side
    .addr1_i(rd_ptr_q),
    .data1_i(32'b0),
    .wr1_i(1'b0),
    .data1_o(data_out_w)
);

assign data_out_o = rd_skid_q ? rd_skid_data_q : data_out_w;

endmodule
module logic_capture_fifo_dp_512_9
(
    // Inputs
     input           clk0_i
    ,input           rst0_i
    ,input  [ 8:0]  addr0_i
    ,input  [ 31:0]  data0_i
    ,input           wr0_i
    ,input           clk1_i
    ,input           rst1_i
    ,input  [ 8:0]  addr1_i
    ,input  [ 31:0]  data1_i
    ,input           wr1_i

    // Outputs
    ,output [ 31:0]  data0_o
    ,output [ 31:0]  data1_o
);

/* verilator lint_off MULTIDRIVEN */
reg [31:0]   ram [511:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */

reg [31:0] ram_read0_q;
reg [31:0] ram_read1_q;

// Synchronous write
always @ (posedge clk0_i)
begin
    if (wr0_i)
        ram[addr0_i] <= data0_i;

    ram_read0_q <= ram[addr0_i];
end

always @ (posedge clk1_i)
begin
    if (wr1_i)
        ram[addr1_i] <= data1_i;

    ram_read1_q <= ram[addr1_i];
end

assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;

endmodule
module logic_capture_mem_fifo_ram
(
    // Inputs
     input           clk_i
    ,input           rst_i
    ,input  [ 31:0]  data_in_i
    ,input           push_i
    ,input           pop_i

    // Outputs
    ,output [ 31:0]  data_out_o
    ,output          accept_o
    ,output          valid_o
);



//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [10:0]   rd_ptr_q;
reg [10:0]   wr_ptr_q;

//-----------------------------------------------------------------
// Write Side
//-----------------------------------------------------------------
wire [10:0] write_next_w = wr_ptr_q + 11'd1;

wire full_w = (write_next_w == rd_ptr_q);

always @ (posedge clk_i )
if (rst_i)
    wr_ptr_q <= 11'b0;
// Push
else if (push_i & !full_w)
    wr_ptr_q <= write_next_w;

//-----------------------------------------------------------------
// Read Side
//-----------------------------------------------------------------
wire read_ok_w = (wr_ptr_q != rd_ptr_q);
reg  rd_q;

always @ (posedge clk_i )
if (rst_i)
    rd_q <= 1'b0;
else
    rd_q <= read_ok_w;

always @ (posedge clk_i )
if (rst_i)
    rd_ptr_q     <= 11'b0;
// Read address increment
else if (read_ok_w && ((!valid_o) || (valid_o && pop_i)))
    rd_ptr_q <= rd_ptr_q + 11'd1;

//-------------------------------------------------------------------
// Read Skid Buffer
//-------------------------------------------------------------------
reg                rd_skid_q;
reg [31:0] rd_skid_data_q;

always @ (posedge clk_i )
if (rst_i)
begin
    rd_skid_q <= 1'b0;
    rd_skid_data_q <= 32'b0;
end
else if (valid_o && !pop_i)
begin
    rd_skid_q      <= 1'b1;
    rd_skid_data_q <= data_out_o;
end
else
begin
    rd_skid_q      <= 1'b0;
    rd_skid_data_q <= 32'b0;
end

//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
assign valid_o       = rd_skid_q | rd_q;
assign accept_o      = !full_w;

//-------------------------------------------------------------------
// Dual port RAM
//-------------------------------------------------------------------
wire [31:0] data_out_w;

logic_capture_mem_fifo_ram_ram_dp_16384_11
u_ram
(
    // Inputs
    .clk0_i(clk_i),
    .rst0_i(rst_i),
    .clk1_i(clk_i),
    .rst1_i(rst_i),

    // Write side
    .addr0_i(wr_ptr_q),
    .wr0_i(push_i & accept_o),
    .data0_i(data_in_i),
    .data0_o(),

    // Read side
    .addr1_i(rd_ptr_q),
    .data1_i(32'b0),
    .wr1_i(1'b0),
    .data1_o(data_out_w)
);

assign data_out_o = rd_skid_q ? rd_skid_data_q : data_out_w;


//-------------------------------------------------------------------
// Level
//-------------------------------------------------------------------

endmodule
module logic_capture_mem_fifo_ram_ram_dp_16384_11
(
    // Inputs
     input           clk0_i
    ,input           rst0_i
    ,input  [ 10:0]  addr0_i
    ,input  [ 31:0]  data0_i
    ,input           wr0_i
    ,input           clk1_i
    ,input           rst1_i
    ,input  [ 10:0]  addr1_i
    ,input  [ 31:0]  data1_i
    ,input           wr1_i

    // Outputs
    ,output [ 31:0]  data0_o
    ,output [ 31:0]  data1_o
);

/* verilator lint_off MULTIDRIVEN */
reg [31:0]   ram [2047:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */

reg [31:0] ram_read0_q;
reg [31:0] ram_read1_q;

// Synchronous write
always @ (posedge clk0_i)
begin
    if (wr0_i)
        ram[addr0_i] <= data0_i;

    ram_read0_q <= ram[addr0_i];
end

always @ (posedge clk1_i)
begin
    if (wr1_i)
        ram[addr1_i] <= data1_i;

    ram_read1_q <= ram[addr1_i];
end

assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;



endmodule
module data_test2 (
  input                 rst,            //reset
  input                 clk,

  output  reg           din_stb,
  input         [1:0]   din_ready,
  output  reg   [1:0]   din_activate,
  output  reg   [31:0]  din,
  input         [23:0]  din_size,

  input                 dout_ready,
  output  reg           dout_activate,
  input         [31:0]  dout,
  output  reg           dout_stb,
  input         [23:0]  dout_size,

  output  reg           count_error,
  output  reg           incorrect_data,
  output  reg   [23:0]  count_detected,
  output  reg   [31:0]  detected_value

);

//Parameters
//Registers/Wires
reg             [31:0]  write_count;
reg             [31:0]  read_count;
//Submodules
//Asynchronous Logic
//Synchronous Logic

always @ (posedge clk) begin
  if (rst) begin
    din_stb             <=  0;
    din_activate        <=  0;
    din                 <=  0;
    write_count         <=  0;

    dout_activate       <=  0;
    dout_stb            <=  0;
    read_count          <=  0;

    count_error         <=  0;
    incorrect_data      <=  0;
    detected_value      <=  0;
    count_detected      <=  0;
  end
  else begin
    din_stb             <=  0;
    dout_stb            <=  0;
    count_error         <=  0;
    incorrect_data      <=  0;

    if ((din_ready > 0) && (din_activate == 0)) begin
      write_count       <=  0;
      din               <=  0;
      if (din_ready[0]) begin
        din_activate[0] <=  1;
      end
      else begin
        din_activate[1] <=  1;
      end
    end
    else if (din_activate != 0) begin
      if (write_count < din_size) begin
        din_stb         <=  1;
        din             <=  write_count;
        write_count     <=  write_count + 1;
      end
      else begin
        din_activate    <=  0;
      end
    end

    if (dout_ready && !dout_activate) begin
      read_count        <=  0;
      dout_activate     <=  1;
      if (dout_size != 24'h0800) begin
        count_error     <=  1;
        count_detected  <=  dout_size;
      end
    end
    else if (dout_activate) begin
      if (read_count < dout_size) begin
        dout_stb        <=  1;
        read_count      <=  read_count + 1;
      end
      else begin
        dout_activate   <=  0;
      end

      //Error Detection
      if (read_count > 0) begin
        if (dout !=  read_count - 1) begin
          incorrect_data  <=  1;
          count_detected  <=  read_count[23:0];
          detected_value  <=  dout;
        end
      end
      else begin
        if (dout != 0) begin
          incorrect_data  <=  1;
          count_detected  <=  read_count[23:0];
          detected_value  <=  dout;
        end
      end
    end
  end
end

endmodule
module hd_data_writer(
    input               clk,
    input               rst,
    input               enable,

    output  reg [31:0]  data,
    input               strobe
);

//Registers and Wires
reg             [31:0]  test_data;

//Submodules

//Asynchronous Logic


//Synchronous Logic
always @ (posedge clk) begin
    if (rst) begin
        test_data       <=  0;
        data            <=  0;
    end
    else begin
        if (enable) begin
            data            <=  test_data;
            if (strobe) begin
                test_data   <=  test_data + 1;
            end
        end
        else begin
            test_data   <=  0;
        end
    end
end

endmodule
module test_in (
  input               clk,
  input               rst,

  input               enable,
  output  reg         finished,
  input       [23:0]  write_count,

  input       [1:0]   ready,
  output  reg [1:0]   activate,
  output  reg [31:0]  fifo_data,
  input       [23:0]  fifo_size,
  output  reg         strobe
);


//Parameters
//Registers/Wires
reg           [23:0]  count;
reg           [23:0]  total_count;
//Sub modules
//Asynchronous Logic
//Synchronous Logic

always @ (posedge clk or posedge rst) begin
  if (rst) begin
    activate            <=  0;
    fifo_data           <=  0;
    strobe              <=  0;
    count               <=  0;
    total_count         <=  0;
    finished            <=  0;
  end
  else begin
    strobe              <=  0;
    if (!enable) begin
        total_count     <=  0;
        activate        <=  0;
        finished        <=  0;
    end
    else if (total_count < write_count) begin
      if ((ready > 0) && (activate == 0)) begin
        //A FIFO is available
        count             <=  0;
        if (ready[0]) begin
          activate[0]     <=  1;
        end
        else begin
          activate[1]     <=  1;
        end
      end
      else if ((activate > 0) && (count < fifo_size))begin
        fifo_data         <=  total_count;
        total_count       <=  total_count + 1;
        count             <=  count + 1;
        strobe            <=  1;
      end
      else begin
        activate          <=  0;
      end
    end
    else begin
        finished          <=  1;
        activate          <=  0;
    end
  end
end

endmodule
module hd_data_reader (
    input           clk,
    input           rst,

    input           enable,
    output  reg     error,

    input           hd_read_from_host,
    input   [31:0]  hd_data_from_host
);

//Registers/Wires
reg                 prev_enable;
wire                posedge_enable;
reg         [31:0]  test_data;

//Submodules

//Asynchronous Logic
assign              posedge_enable = (!prev_enable && enable);

//Synchronous Logic
always @ (posedge clk) begin
    if (rst) begin
        prev_enable         <=  0;
        error               <=  0;
        test_data           <=  0;
    end
    else begin
        prev_enable         <=  enable;
        if (posedge_enable) begin
            error           <=  0;
            test_data       <=  0;
        end
        else begin
            if (hd_read_from_host) begin
                if (hd_data_from_host != test_data) begin
                    error   <=  1;
                end
                test_data   <=  test_data + 1;
            end
        end
    end
end


endmodule
module test_out (
  input               clk,
  input               rst,

  input               enable,
  output  reg         busy,
  output  reg         error,

  input               ready,
  output  reg         activate,
  input       [23:0]  size,
  input       [31:0]  data,
  output  reg         strobe,
  output  reg [23:0]  total_count
  
);

reg           [31:0]  test_value;
reg           [23:0]  count;

always @ (posedge clk) begin
  if (rst) begin
    activate          <=  0;
    count             <=  0;
    test_value        <=  32'h0;
    error             <=  0;
    busy              <=  0;
    total_count       <=  0;
    strobe            <=  0;
  end
  else begin
    busy              <=  0;
    strobe            <=  0;
    //The user is not asking to check anything
    if (!enable) begin
      //activate        <=  0;
      //count           <=  0;
      test_value      <=  32'h0;
      error           <=  0;
      total_count     <=  0;
    end

    //Looking for total count
    //busy            <=  1;
    if (ready && !activate) begin
      count         <=  0;
      activate      <=  1;
    end
    else if (activate) begin
      busy            <= 1;
      if (count < size) begin
        strobe      <=  1;
        total_count <=  total_count + 1;
        count       <=  count + 1;
        if ((data != test_value) && enable) begin
          error     <=  1;
        end
      end
      else begin
        activate  <=  0;
      end
    end
    if (strobe) begin
      test_value  <= test_value + 1;
    end
  end
end

endmodule
module sata_platform (
  input                 rst,

  input                 tx_comm_reset,
  input                 tx_comm_wake,
  output                comm_init_detect,
  output                comm_wake_detect,
  output                rx_elec_idle,
  input                 tx_elec_idle,
  output                rx_byte_is_aligned,


  input         [31:0]  phy_tx_dout,
  input                 phy_tx_isk,
  output        [31:0]  phy_rx_din,
  output        [3:0]   phy_rx_isk,

  //Clock Interface
  input                 mgtclk_in,
  output           reg  cnt_rst,
  output                pll_locked,
  output                clk_75mhz,


  output                platform_ready,

  output                TXP0_OUT,
  output                TXN0_OUT,

  input                 RXP0_IN,
  input                 RXN0_IN,

  output                GTX115_TXP0_OUT,
  output                GTX115_TXN0_OUT,

  input                 GTX115_RXP0_IN,
  input                 GTX115_RXN0_IN
);

//Parameters
//Registers/Wires
//Submodules
//Asynchronous Logic
//Synchronous Logic
endmodule
module blk_mem #(
  parameter DATA_WIDTH    = 8,
  parameter ADDRESS_WIDTH = 4
)(
  input                             clka,
  input                             wea,
  input   [ADDRESS_WIDTH - 1  :0]   addra,
  input   [DATA_WIDTH - 1:0]        dina,
  input                             clkb,
  input   [ADDRESS_WIDTH - 1:0]     addrb,
  output  [DATA_WIDTH - 1:0]        doutb
);

//Parameters
//Registers/Wires
reg [DATA_WIDTH - 1:0] mem [0:2 ** ADDRESS_WIDTH];
reg [DATA_WIDTH - 1:0] dout;

//Submodules
//Asynchronous Logic
assign doutb = dout;

//Synchronous Logic
//write only on the A side
`ifdef SIMULATION
//Only initialize in simulation... somthing gets fucked when you try and do it on an FPGA
integer i;
initial begin
  i = 0;
  for (i = 0; i < (2 ** ADDRESS_WIDTH); i = i + 1) begin
    mem[i]  <=  0;
  end
end
`endif

always @ (posedge clka)
begin
  if ( wea ) begin
     mem[addra] <= dina;
  end
end

//read only on the b side
always @ (posedge clkb)
begin
     dout <= mem[addrb];
end


endmodule
module cross_clock_enable (
  input         rst,
  input         in_en,

  input         out_clk,
  output  reg   out_en

);

//Parameters
//Registers/Wires
reg       [2:0]  out_en_sync;
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge out_clk) begin
  if (rst) begin
    out_en_sync   <=  0;
    out_en        <=  0;
  end
  else begin
    if (out_en_sync[2:1] == 2'b11) begin
      out_en      <=  1;
    end
    else if (out_en_sync[2:1] == 2'b00) begin
      out_en      <=  0;
    end
    out_en_sync   <=  {out_en_sync[1:0], in_en};
  end
end
endmodule
module debounce #(
  parameter INITIAL_STATE     = 0,
  parameter DEBOUNCE_COUNT    = 100
)(
  input         clk,
  input         in_signal,
  output  reg   out_signal
);

reg [DEBOUNCE_COUNT - 1: 0] debounce;

initial begin
  out_signal    <=  INITIAL_STATE;
  debounce      <=  INITIAL_STATE;
end
always @ (posedge clk) begin

  debounce  <= {debounce[(DEBOUNCE_COUNT - 2) : 0], in_signal};

  if (debounce[0] == 1 && (& debounce)) begin
    out_signal         <=  1;
  end
  else if ((debounce[0] == 0) && (~| debounce)) begin
    out_signal         <=  0;
  end
end

endmodule
module uart (
	/********** ????a? & ???a? **********/
	input  wire				   clk,		 // ????a?
	input  wire				   reset,	 // ???????a?
	/********** ?V?????????`?? **********/
	input  wire				   cs_,		 // ???a??????
	input  wire				   as_,		 // ??????????`??
	input  wire				   rw,		 // Read / Write
	input  wire [`UartAddrBus] addr,	 // ?????
	input  wire [`WordDataBus] wr_data,	 // ?????z???`??
	output wire [`WordDataBus] rd_data,	 // ?i???????`??
	output wire				   rdy_,	 // ????
	/********** ????z?? **********/
	output wire				   irq_rx,	 // ???????????z??
	output wire				   irq_tx,	 // ???????????z??
	/********** UART?????????	**********/
	input  wire				   rx,		 // UART???????
	output wire				   tx		 // UART???????
);

	/********** ??????? **********/
	// ????????
	wire					   rx_busy;	 // ?????V??
	wire					   rx_end;	 // ???????????
	wire [`ByteDataBus]		   rx_data;	 // ?????`??
	// ????????
	wire					   tx_busy;	 // ?????V??
	wire					   tx_end;	 // ???????????
	wire					   tx_start; // ?????_????
	wire [`ByteDataBus]		   tx_data;	 // ?????`??

	/********** UART????????`?? **********/
	uart_ctrl uart_ctrl (
		/********** ????a? & ???a? **********/
		.clk	  (clk),	   // ????a?
		.reset	  (reset),	   // ???????a?
		/********** Host Interface **********/
		.cs_	  (cs_),	   // ???a??????
		.as_	  (as_),	   // ??????????`??
		.rw		  (rw),		   // Read / Write
		.addr	  (addr),	   // ?????
		.wr_data  (wr_data),   // ?????z???`??
		.rd_data  (rd_data),   // ?i???????`??
		.rdy_	  (rdy_),	   // ????
		/********** Interrupt  **********/
		.irq_rx	  (irq_rx),	   // ???????????z??
		.irq_tx	  (irq_tx),	   // ???????????z??
		/********** ??????? **********/
		// ????????
		.rx_busy  (rx_busy),   // ?????V??
		.rx_end	  (rx_end),	   // ???????????
		.rx_data  (rx_data),   // ?????`??
		// ????????
		.tx_busy  (tx_busy),   // ?????V??
		.tx_end	  (tx_end),	   // ???????????
		.tx_start (tx_start),  // ?????_????
		.tx_data  (tx_data)	   // ?????`??
	);

	/********** UART???????`?? **********/
	uart_tx uart_tx (
		/********** ????a? & ???a? **********/
		.clk	  (clk),	   // ????a?
		.reset	  (reset),	   // ???????a?
		/********** ??????? **********/
		.tx_start (tx_start),  // ?????_????
		.tx_data  (tx_data),   // ?????`??
		.tx_busy  (tx_busy),   // ?????V??
		.tx_end	  (tx_end),	   // ???????????
		/********** Transmit Signal **********/
		.tx		  (tx)		   // UART???????
	);

	/********** UART???????`?? **********/
	uart_rx uart_rx (
		/********** ????a? & ???a? **********/
		.clk	  (clk),	   // ????a?
		.reset	  (reset),	   // ???????a?
		/********** ??????? **********/
		.rx_busy  (rx_busy),   // ?????V??
		.rx_end	  (rx_end),	   // ???????????
		.rx_data  (rx_data),   // ?????`??
		/********** Receive Signal **********/
		.rx		  (rx)		   // UART???????
	);

endmodule
module bus_master_mux (
	/********** ÊäÈëÊä³öÐÅºÅ **********/
	// 0ºÅ×ÜÏßÖ÷¿Ø
	input  wire [`WordAddrBus] m0_addr,	   // µØÖ·
	input  wire				   m0_as_,	   // µØÖ·Ñ¡Í¨
	input  wire				   m0_rw,	   // ¶Á/Ð´
	input  wire [`WordDataBus] m0_wr_data, // Ð´ÈëµÄÊý¾Ý
	input  wire				   m0_grnt_,   // ¸³Óè×ÜÏß
	// 1ºÅ×ÜÏßÖ÷¿Ø
	input  wire [`WordAddrBus] m1_addr,	   // µØÖ·
	input  wire				   m1_as_,	   // µØÖ·Ñ¡Í¨
	input  wire				   m1_rw,	   // ¶Á/Ð´
	input  wire [`WordDataBus] m1_wr_data, // Ð´ÈëµÄÊý¾Ý
	input  wire				   m1_grnt_,   // ¸³Óè×ÜÏß
	// 3ºÅ×ÜÏßÖ÷¿Ø
	input  wire [`WordAddrBus] m2_addr,	   // µØÖ·
	input  wire				   m2_as_,	   // µØÖ·Ñ¡Í¨
	input  wire				   m2_rw,	   // ¶Á/Ð´
	input  wire [`WordDataBus] m2_wr_data, // Ð´ÈëµÄÊý¾Ý
	input  wire				   m2_grnt_,   // ¸³Óè×ÜÏß
	// 3ºÅ×ÜÏßÖ÷¿Ø
	input  wire [`WordAddrBus] m3_addr,	   // µØÖ·
	input  wire				   m3_as_,	   // µØÖ·Ñ¡Í¨
	input  wire				   m3_rw,	   // ¶Á/Ð´
	input  wire [`WordDataBus] m3_wr_data, // Ð´ÈëµÄÊý¾Ý
	input  wire				   m3_grnt_,   // ¸³Óè×ÜÏß
	/********** ¹²ÏíÐÅºÅ×ÜÏß´ÓÊô **********/
	output reg	[`WordAddrBus] s_addr,	   // µØÖ·
	output reg				   s_as_,	   // µØÖ·Ñ¡Í¨
	output reg				   s_rw,	   // ¶Á/Ð´
	output reg	[`WordDataBus] s_wr_data   // Ð´ÈëµÄÊý¾Ý
);

	/********** ×ÜÏßÖ÷¿Ø¶àÂ·¸´ÓÃÆ÷ **********/
	always @(*) begin
		/* Ñ¡Ôñ³ÖÓÐ×ÜÏßÊ¹ÓÃÈ¨µÄÖ÷¿Ø */
		if (m0_grnt_ == `ENABLE_) begin			 // 0ºÅ×ÜÏß×Ü¿Ø
			s_addr	  = m0_addr;
			s_as_	  = m0_as_;
			s_rw	  = m0_rw;
			s_wr_data = m0_wr_data;
		end else if (m1_grnt_ == `ENABLE_) begin // 1ºÅ×ÜÏß×Ü¿Ø
			s_addr	  = m1_addr;
			s_as_	  = m1_as_;
			s_rw	  = m1_rw;
			s_wr_data = m1_wr_data;
		end else if (m2_grnt_ == `ENABLE_) begin // 2ºÅ×ÜÏß×Ü¿Ø
			s_addr	  = m2_addr;
			s_as_	  = m2_as_;
			s_rw	  = m2_rw;
			s_wr_data = m2_wr_data;
		end else if (m3_grnt_ == `ENABLE_) begin // 3ºÅ×ÜÏß×Ü¿Ø
			s_addr	  = m3_addr;
			s_as_	  = m3_as_;
			s_rw	  = m3_rw;
			s_wr_data = m3_wr_data;
		end else begin							 // Ä¬ÈÏÖµ
			s_addr	  = `WORD_ADDR_W'h0;
			s_as_	  = `DISABLE_;
			s_rw	  = `READ;
			s_wr_data = `WORD_DATA_W'h0;
		end
	end

endmodule
module bus_addr_dec (
	/********** µØÖ· **********/
	input  wire [`WordAddrBus] s_addr, // ×ÜÏß×Ü¿ØÌá¹©µÄµØÖ·ÐÅºÅ
	/********** Êä³öÆ¬Ñ¡ÐÅºÅ **********/
	output reg				   s0_cs_, // 0ºÅ×ÜÏß´ÓÊôÆ¬Ñ¡ÐÅºÅ
	output reg				   s1_cs_, // 1ºÅ×ÜÏß´ÓÊôÆ¬Ñ¡ÐÅºÅ
	output reg				   s2_cs_, // 2ºÅ×ÜÏß´ÓÊôÆ¬Ñ¡ÐÅºÅ
	output reg				   s3_cs_, // 3ºÅ×ÜÏß´ÓÊôÆ¬Ñ¡ÐÅºÅ
	output reg				   s4_cs_, // 4ºÅ×ÜÏß´ÓÊôÆ¬Ñ¡ÐÅºÅ
	output reg				   s5_cs_, // 5ºÅ×ÜÏß´ÓÊôÆ¬Ñ¡ÐÅºÅ
	output reg				   s6_cs_, // 6ºÅ×ÜÏß´ÓÊôÆ¬Ñ¡ÐÅºÅ
	output reg				   s7_cs_  // 7ºÅ×ÜÏß´ÓÊôÆ¬Ñ¡ÐÅºÅ
);

	/********** ×ÜÏß´ÓÊôË÷Òý **********/
	wire [`BusSlaveIndexBus] s_index = s_addr[`BusSlaveIndexLoc]; // È¡µØÖ·ÖÐ¸ß3Î»±íÊ¾µÄ´ÓÊôºÅ

	/********** ×ÜÏß´ÓÊô¶àÂ·¸´ÓÃÆ÷**********/
	always @(*) begin
		/* ³õÊ¼»¯Æ¬Ñ¡ÐÅºÅ */
		s0_cs_ = `DISABLE_;
		s1_cs_ = `DISABLE_;
		s2_cs_ = `DISABLE_;
		s3_cs_ = `DISABLE_;
		s4_cs_ = `DISABLE_;
		s5_cs_ = `DISABLE_;
		s6_cs_ = `DISABLE_;
		s7_cs_ = `DISABLE_;
		/* Ñ¡ÔñµØÖ·¶ÔÓ¦µÄ´ÓÊô */
		case (s_index)
			`BUS_SLAVE_0 : begin // 0ºÅ×ÜÏß´ÓÊô
				s0_cs_	= `ENABLE_;
			end
			`BUS_SLAVE_1 : begin // 1ºÅ×ÜÏß´ÓÊô
				s1_cs_	= `ENABLE_;
			end
			`BUS_SLAVE_2 : begin // 2ºÅ×ÜÏß´ÓÊô
				s2_cs_	= `ENABLE_;
			end
			`BUS_SLAVE_3 : begin // 0ºÅ×ÜÏß´ÓÊô
				s3_cs_	= `ENABLE_;
			end
			`BUS_SLAVE_4 : begin // 4ºÅ×ÜÏß´ÓÊô
				s4_cs_	= `ENABLE_;
			end
			`BUS_SLAVE_5 : begin // 5ºÅ×ÜÏß´ÓÊô
				s5_cs_	= `ENABLE_;
			end
			`BUS_SLAVE_6 : begin // 6ºÅ×ÜÏß´ÓÊô
				s6_cs_	= `ENABLE_;
			end
			`BUS_SLAVE_7 : begin // 7ºÅ×ÜÏß´ÓÊô
				s7_cs_	= `ENABLE_;
			end
		endcase
	end

endmodule