dakies/OSS_Verilog huggingface dataset:
module systolic_array (
    input  wire       clk,
    input  wire       reset,

    input  wire [3:0] in_left_zero,
    input  wire [3:0] in_left_sign,
    input  wire [7:0] in_top,
    input  wire       reset_accumulators,
    input  wire       copy_accumulator_values_to_out_queue,
    input  wire       restart_out_queue,
    //input wire [2:0] apply_shift_to_out,
    //input wire       apply_relu_to_out,

    output wire [7:0] out
);
    reg  signed [16:0] accumulators      [3:0];
    wire signed [16:0] accumulators_next [3:0];
    reg  signed [16:0] out_queue         [3:0];
    reg          [1:0] out_queue_index;

    integer n;
    // // clocked accumulators[]
    // always @(posedge clk)
    //     for (n = 0; n < 4; n = n + 1)
    //         if (reset | reset_accumulators)
    //             accumulators[n] <= 0;
    //         else
    //             accumulators[n] <= accumulators_next[n];

    // // clocked out_queue[]
    // always @(posedge clk)
    //     for (n = 0; n < 4; n = n + 1)
    //         // if (reset)
    //         //     out_queue[n] <= 0;
    //         // else
    //             if (copy_accumulator_values_to_out_queue)
    //                 out_queue[n]    <= accumulators[n]; //accumulators_next[n];
            
    // // clocked out_queue_index[]
    // always @(posedge clk)
    //     if (reset | restart_out_queue)
    //         out_queue_index <= 0;
    //     else
    //         out_queue_index <= out_queue_index + 1;

    always @(posedge clk)
        for (n = 0; n < 4; n = n + 1) begin
            if (reset | reset_accumulators)
                accumulators[n] <= 0;
            else
                accumulators[n] <= accumulators_next[n];

            if (reset | restart_out_queue)
                out_queue_index <= 0;
            else
                out_queue_index <= out_queue_index + 1;

            if (copy_accumulator_values_to_out_queue)
                out_queue[n]    <= accumulators_next[n];
        end

    genvar i, j;
    generate
    for (j = 0; j < 1; j = j + 1)
        for (i = 0; i < 4; i = i + 1) begin : mac
            wire [16:0] value_curr  = accumulators     [i*1+j];
            wire [16:0] value_next  = accumulators_next[i*1+j];
            wire [16:0] value_queue = out_queue        [i*1+j];
            assign accumulators_next[i*1+j] =
                 reset ? 0 :
                 in_left_zero[i] ? accumulators[i*1+j] + 0 :
                (in_left_sign[i] ? accumulators[i*1+j] - $signed(in_top) :
                                   accumulators[i*1+j] + $signed(in_top));
        end
    endgenerate

    assign out = out_queue[out_queue_index] >> 8;
endmodule
module tt_um_rejunity_1_58bit (
    input  wire [7:0] ui_in,    // Dedicated inputs
    output wire [7:0] uo_out,   // Dedicated outputs
    input  wire [7:0] uio_in,   // IOs: Input path
    output wire [7:0] uio_out,  // IOs: Output path
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
    input  wire       ena,      // will go high when the design is enabled
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);
    assign uio_oe  = 0;         // bidirectional IOs set to INPUT
    assign uio_out = 0;         // drive bidirectional IO outputs to 0

    wire reset = ! rst_n;

    // decode ternary weights - 4 ternary weights per byte
    // wire [3:0] weights_zero = ~ { |ui_in[1:0], |ui_in[3:2],  |ui_in[5:4], |ui_in[7:6] };
    // wire [3:0] weights_sign =   {  ui_in[1  ],  ui_in[3  ],   ui_in[5  ],  ui_in[7  ] };
    // -----------------------------------------------------
    // wire [3:0] weights_zero = ~ { |ui_in[7:6], |ui_in[5:4],  |ui_in[3:2], |ui_in[1:0] };
    // wire [3:0] weights_sign =   {  ui_in[7  ],  ui_in[5  ],   ui_in[3  ],  ui_in[1  ] };

    // unpack ternary weights - 5 ternary weights per byte
    wire [4:0] weights_zero;
    wire [4:0] weights_sign;
    unpack_ternary_weights unpack_ternary_weights(
        .packed_weights(ui_in),
        .weights_zero(weights_zero),
        .weights_sign(weights_sign)
    );

    // @TODO: special weight to initiate readout
    wire       initiate_read_out = !ena;
    
    systolic_array systolic_array(
        .clk(clk),
        .reset(reset),

        .in_left_zero(weights_zero),
        .in_left_sign(weights_sign),
        .in_top(uio_in),

        .restart_inputs(initiate_read_out),
        .reset_accumulators(initiate_read_out),
        .copy_accumulator_values_to_out_queue(initiate_read_out),
        .restart_out_queue(initiate_read_out),
        
        .out(uo_out)
    );

endmodule
module multiplier(
	
	input signed [`WIDTH - 1 : 0] dataa,
	input signed [2 * `WIDTH - 1 : 0] datab,
	output signed [2 * `WIDTH - 1 : 0] dataout
);
assign dataout = dataa * datab;

	
endmodule
module adder(	

	input signed [2 * `WIDTH - 1 : 0] dataa,
	input signed [2 * `WIDTH - 1 : 0] datab,
	output signed [2 * `WIDTH - 1 : 0] dataout
);

assign dataout = dataa + datab;


endmodule
module onebyone18mul (
A1, A2, A3, A4, A5, A6, A7, A8, A9,
    
B1, B2, B3, B4, B5, B6, B7, B8, B9,
    
U1, U2, U3, U4, U5, U6, U7, U8, U9,

Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9,
	
I,

X,

Xout,

Yout
  );
  
	input wire signed [`WIDTH - 1:0] A1, A2, A3, A4, A5, A6, A7, A8, A9;
	input wire signed [`WIDTH - 1:0] B1, B2, B3, B4, B5, B6, B7, B8, B9;
	input wire signed [`WIDTH - 1:0] U1, U2, U3, U4, U5, U6, U7, U8, U9;
	input wire signed [2 * `WIDTH - 1:0] Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9;
	input wire signed [`WIDTH - 1:0] I;
	input wire signed [2 * `WIDTH - 1:0] X;
	output wire signed [2 * `WIDTH - 1:0] Xout;
	output wire signed [2 * `WIDTH - 1:0] Yout;

// In A1(A1[`WIDTH - 1:0]), the first A1 is the A1 in eq1 module and the second A1 is the one in this module
// This section is assigning the inputs from onebyone module to the respective inputs in other moudles
	
eq1 u1(
.A1(A1[`WIDTH - 1:0]),
.A2(A2[`WIDTH - 1:0]),
.A3(A3[`WIDTH - 1:0]),
.A4(A4[`WIDTH - 1:0]),
.A5(A5[`WIDTH - 1:0]),
.A6(A6[`WIDTH - 1:0]),
.A7(A7[`WIDTH - 1:0]),
.A8(A8[`WIDTH - 1:0]),
.A9(A9[`WIDTH - 1:0]),

.B1(B1[`WIDTH - 1:0]),
.B2(B2[`WIDTH - 1:0]),
.B3(B3[`WIDTH - 1:0]),
.B4(B4[`WIDTH - 1:0]),
.B5(B5[`WIDTH - 1:0]),
.B6(B6[`WIDTH - 1:0]),
.B7(B7[`WIDTH - 1:0]),
.B8(B8[`WIDTH - 1:0]),
.B9(B9[`WIDTH - 1:0]),

.U1(U1[`WIDTH - 1:0]),
.U2(U2[`WIDTH - 1:0]),
.U3(U3[`WIDTH - 1:0]),
.U4(U4[`WIDTH - 1:0]),
.U5(U5[`WIDTH - 1:0]),
.U6(U6[`WIDTH - 1:0]),
.U7(U7[`WIDTH - 1:0]),
.U8(U8[`WIDTH - 1:0]),
.U9(U9[`WIDTH - 1:0]),

.Y1(Y1[2 * `WIDTH - 1:0]),
.Y2(Y2[2 * `WIDTH - 1:0]),
.Y3(Y3[2 * `WIDTH - 1:0]),
.Y4(Y4[2 * `WIDTH - 1:0]),
.Y5(Y5[2 * `WIDTH - 1:0]),
.Y6(Y6[2 * `WIDTH - 1:0]),
.Y7(Y7[2 * `WIDTH - 1:0]),
.Y8(Y8[2 * `WIDTH - 1:0]),
.Y9(Y9[2 * `WIDTH - 1:0]),

.I(I[`WIDTH - 1:0]),

.out(Xout[2 * `WIDTH - 1:0])

);

eq2 u2(
.X(X[2 * `WIDTH - 1:0]),

.out(Yout[2 * `WIDTH - 1:0])
);

endmodule
module eq2 (
X,
out
  );
	input wire signed [2 * `WIDTH - 1:0] X;
	wire signed [2 * `WIDTH - 1:0] Xplus1;
	wire signed [2 * `WIDTH - 1:0] Xminus1;
	wire signed [2 * `WIDTH - 1:0] Xplus;
	wire signed [2 * `WIDTH - 1:0] Xminus;
	output wire signed [2 * `WIDTH - 1:0] out;

// {{(2 * `WIDTH-1){1'b0}}, 1'b1} this notation basically acts like concatenation
// This would result in a sign extended binary one. This is necessary to make it the same size as X
	
	assign Xplus1 = X + {{(2 * `WIDTH - 1){1'b0}}, 1'b1};
	assign Xminus1 = X - {{(2 * `WIDTH - 1){1'b0}}, 1'b1};	

// Xplus and Xminus equations check the most significant bit of Xplus1 and Xminus1 
// If most significant bit is 1, then get the one's complement of Xplus1 and assign it to Xplus
// If most significant bit is 0, then Xplus is Xplus1 from previous step

	assign Xplus = (Xplus1[2 * `WIDTH - 1])?(~Xplus1+{{(2 * `WIDTH - 1){1'b0}}, 1'b1}):Xplus1;
	assign Xminus =  (Xminus1[2 * `WIDTH - 1])?(~Xminus1+{{(2 * `WIDTH - 1){1'b0}}, 1'b1}):Xminus1;

// Right shift (Xplus - Xminus) by one bit 

	assign out = (Xplus - Xminus) >>> {{(2 * `WIDTH-1){1'b0}}, 1'b1};
endmodule
module onebyone (
A1, A2, A3, A4, A5, A6, A7, A8, A9,
    
B1, B2, B3, B4, B5, B6, B7, B8, B9,
    
U1, U2, U3, U4, U5, U6, U7, U8, U9,

Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9,
	
I,

clk,

X,

Xout,

Yout,

fin_flag,

counter_flag
  );
  
	input wire signed [`WIDTH - 1:0] A1, A2, A3, A4, A5, A6, A7, A8, A9;
	input wire signed [`WIDTH - 1:0] B1, B2, B3, B4, B5, B6, B7, B8, B9;
	input wire signed [`WIDTH - 1:0] U1, U2, U3, U4, U5, U6, U7, U8, U9;
	input wire signed [2 * `WIDTH - 1:0] Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9;
	input wire signed [`WIDTH - 1:0] I;
	input wire clk;
	input wire signed [2 * `WIDTH - 1:0] X;
	output wire signed [2 * `WIDTH - 1:0] Xout;
	output wire signed [2 * `WIDTH - 1:0] Yout;
	output wire fin_flag;
	output wire counter_flag;

// In A1(A1[`WIDTH - 1:0]), the first A1 is the A1 in eq1 module and the second A1 is the one in this module
// This section is assigning the inputs from onebyone module to the respective inputs in other moudles
	
eq1oneunit u1(
.A1(A1[`WIDTH - 1:0]),
.A2(A2[`WIDTH - 1:0]),
.A3(A3[`WIDTH - 1:0]),
.A4(A4[`WIDTH - 1:0]),
.A5(A5[`WIDTH - 1:0]),
.A6(A6[`WIDTH - 1:0]),
.A7(A7[`WIDTH - 1:0]),
.A8(A8[`WIDTH - 1:0]),
.A9(A9[`WIDTH - 1:0]),

.B1(B1[`WIDTH - 1:0]),
.B2(B2[`WIDTH - 1:0]),
.B3(B3[`WIDTH - 1:0]),
.B4(B4[`WIDTH - 1:0]),
.B5(B5[`WIDTH - 1:0]),
.B6(B6[`WIDTH - 1:0]),
.B7(B7[`WIDTH - 1:0]),
.B8(B8[`WIDTH - 1:0]),
.B9(B9[`WIDTH - 1:0]),

.U1(U1[`WIDTH - 1:0]),
.U2(U2[`WIDTH - 1:0]),
.U3(U3[`WIDTH - 1:0]),
.U4(U4[`WIDTH - 1:0]),
.U5(U5[`WIDTH - 1:0]),
.U6(U6[`WIDTH - 1:0]),
.U7(U7[`WIDTH - 1:0]),
.U8(U8[`WIDTH - 1:0]),
.U9(U9[`WIDTH - 1:0]),

.Y1(Y1[2 * `WIDTH - 1:0]),
.Y2(Y2[2 * `WIDTH - 1:0]),
.Y3(Y3[2 * `WIDTH - 1:0]),
.Y4(Y4[2 * `WIDTH - 1:0]),
.Y5(Y5[2 * `WIDTH - 1:0]),
.Y6(Y6[2 * `WIDTH - 1:0]),
.Y7(Y7[2 * `WIDTH - 1:0]),
.Y8(Y8[2 * `WIDTH - 1:0]),
.Y9(Y9[2 * `WIDTH - 1:0]),

.I(I[`WIDTH - 1:0]),

.clk(clk),

.fin_flag(fin_flag),
.counter_flag(counter_flag),

.out(Xout[2 * `WIDTH - 1:0])

);

eq2 u2(
.X(X[2 * `WIDTH - 1:0]),

.out(Yout[2 * `WIDTH - 1:0])
);

endmodule
module eq1 (
A1, A2, A3, A4, A5, A6, A7, A8, A9,
    
B1, B2, B3, B4, B5, B6, B7, B8, B9,
    
U1, U2, U3, U4, U5, U6, U7, U8, U9,

Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9,
	
I,

out
  );
	input wire signed [`WIDTH - 1:0] A1, A2, A3, A4, A5, A6, A7, A8, A9;
	input wire signed [`WIDTH - 1:0] B1, B2, B3, B4, B5, B6, B7, B8, B9;
	input wire signed [`WIDTH - 1:0] U1, U2, U3, U4, U5, U6, U7, U8, U9;

// Y matrix will be 16 bits since we are storing the multiplied value of A*Y + B*U

	input wire signed [2 * `WIDTH - 1:0] Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9;
	wire signed [2 * `WIDTH - 1:0] outY;
	wire signed [2 * `WIDTH - 1:0] outU;
	input wire signed [`WIDTH - 1:0] I;
	output wire signed [2 * `WIDTH - 1:0] out;

// Implementing the equations here. Multiply the corresponding indexes of the matrices and add them.
// outU and outY are intermediate signals used to store the sum.
	
	assign outY = (A1 * Y1)+ (A2 * Y2) + (A3 * Y3) + (A4 * Y4) + (A5 * Y5) + (A6 * Y6) + (A7 * Y7) + (A8 * Y8) + (A9 * Y9);
	assign outU = (B1 * U1)+ (B2 * U2) + (B3 * U3) + (B4 * U4) + (B5 * U5) + (B6 * U6) + (B7 * U7) + (B8 * U8) + (B9 * U9);
	assign out = outY + outU + I;
endmodule
module one_by_one (
clk, 
A1, A2, A3, A4, A5, A6, A7, A8, A9,
    
B1, B2, B3, B4, B5, B6, B7, B8, B9,
    
U1, U2, U3, U4, U5, U6, U7, U8, U9,

Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9,
	
I,

Initial_X,

eq1out,

out
  );
	
	
	input clk;
	
	input wire signed [`WIDTH - 1:0] A1, A2, A3, A4, A5, A6, A7, A8, A9;
	input wire signed [`WIDTH - 1:0] B1, B2, B3, B4, B5, B6, B7, B8, B9;
	input wire signed [`WIDTH - 1:0] U1, U2, U3, U4, U5, U6, U7, U8, U9;
	input wire signed [`WIDTH - 1:0] Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9;
	input wire signed [`WIDTH - 1:0] I;
	input wire signed [`WIDTH - 1:0] Initial_X;
	output wire signed [`WIDTH - 1:0] eq1out;
	output wire signed [`WIDTH - 1:0] out;
	
equation1 u1(
.clk(clk),
.A1(A1[`WIDTH - 1:0]),
.A2(A2[`WIDTH - 1:0]),
.A3(A3[`WIDTH - 1:0]),
.A4(A4[`WIDTH - 1:0]),
.A5(A5[`WIDTH - 1:0]),
.A6(A6[`WIDTH - 1:0]),
.A7(A7[`WIDTH - 1:0]),
.A8(A8[`WIDTH - 1:0]),
.A9(A9[`WIDTH - 1:0]),

.B1(B1[`WIDTH - 1:0]),
.B2(B2[`WIDTH - 1:0]),
.B3(B3[`WIDTH - 1:0]),
.B4(B4[`WIDTH - 1:0]),
.B5(B5[`WIDTH - 1:0]),
.B6(B6[`WIDTH - 1:0]),
.B7(B7[`WIDTH - 1:0]),
.B8(B8[`WIDTH - 1:0]),
.B9(B9[`WIDTH - 1:0]),

.U1(U1[`WIDTH - 1:0]),
.U2(U2[`WIDTH - 1:0]),
.U3(U3[`WIDTH - 1:0]),
.U4(U4[`WIDTH - 1:0]),
.U5(U5[`WIDTH - 1:0]),
.U6(U6[`WIDTH - 1:0]),
.U7(U7[`WIDTH - 1:0]),
.U8(U8[`WIDTH - 1:0]),
.U9(U9[`WIDTH - 1:0]),

.Y1(Y1[`WIDTH - 1:0]),
.Y2(Y2[`WIDTH - 1:0]),
.Y3(Y3[`WIDTH - 1:0]),
.Y4(Y4[`WIDTH - 1:0]),
.Y5(Y5[`WIDTH - 1:0]),
.Y6(Y6[`WIDTH - 1:0]),
.Y7(Y7[`WIDTH - 1:0]),
.Y8(Y8[`WIDTH - 1:0]),
.Y9(Y9[`WIDTH - 1:0]),

.I(I[`WIDTH - 1:0]),

.out(eq1out[`WIDTH - 1:0])

);

equation2 u2(

.dX(eq1out[`WIDTH - 1:0]),

.Initial_X(Initial_X[`WIDTH - 1:0]),

.out(out[`WIDTH - 1:0])
);

endmodule
module multiplier_unit#(parameter WIDTH = 9)
(
	
	input signed[WIDTH-1:0] dataa,
	input signed[WIDTH-1:0] datab,
	output signed[2*WIDTH-1:0] dataout
);
assign dataout = dataa * datab;

	
endmodule
module equation2 (
dX,
Initial_X,
out
  );
	input wire signed [`WIDTH - 1:0] dX;
	input wire signed [`WIDTH - 1:0] Initial_X;
	wire signed [`WIDTH - 1:0] X;
	wire signed [`WIDTH - 1:0] Xplus1;
	wire signed [`WIDTH - 1:0] Xminus1;
	wire signed [`WIDTH - 1:0] Xplus;
	wire signed [`WIDTH - 1:0] Xminus;
	output wire signed [`WIDTH - 1:0] out;
	
	assign X = dX + Initial_X;
	assign Xplus1 = X + {{(`WIDTH-1){1'b0}}, 1'b1};
	assign Xminus1 = X - {{(`WIDTH-1){1'b0}}, 1'b1};	
	assign Xplus = (Xplus1[`WIDTH - 1])?(~Xplus1+{{(`WIDTH-1){1'b0}}, 1'b1}):Xplus1;
	assign Xminus =  (Xminus1[`WIDTH - 1])?(~Xminus1+{{(`WIDTH-1){1'b0}}, 1'b1}):Xminus1;
	assign out = (Xplus - Xminus) >>> {{(`WIDTH-1){1'b0}}, 1'b1};
endmodule
module adder_unit#(parameter WIDTH=9)
(//input declarations

input signed[WIDTH-1:0] A_in,input signed[WIDTH-1:0] B_in,

//output declarations
output reg signed[WIDTH-1:0] C_out);

always@(*)
begin
	if(A_in[WIDTH-1]^B_in[WIDTH-1]==0)
		begin
		C_out[WIDTH-2:0]<= B_in[WIDTH-2:0] + A_in[WIDTH-2:0];
		C_out[WIDTH-1]<= A_in[WIDTH-1];
		end
	if(A_in[WIDTH-1]^B_in[WIDTH-1]==1)
	//if({A_in[WIDTH-1]B_in[WIDTH-1]}==01)
		begin
		C_out[WIDTH-2:0] <= (B_in[WIDTH-2:0]>A_in[WIDTH-2:0])?(B_in[WIDTH-2:0]-A_in[WIDTH-2:0]):(A_in[WIDTH-2:0]-B_in[WIDTH-2:0]);
		C_out[WIDTH-1] <= (B_in[WIDTH-2:0]>A_in[WIDTH-2:0])?(B_in[WIDTH-1]):(A_in[WIDTH-1]);
		end
end
endmodule
module convolution#(parameter WIDTH = 9)
(
	input clk,
	//input reg [3:0]counter,
	input signed [WIDTH-1:0] a0_in,input signed [WIDTH-1:0] a1_in,input signed [WIDTH-1:0] a2_in,input signed [WIDTH-1:0] a3_in,
	input signed [WIDTH-1:0] a4_in,input signed [WIDTH-1:0] a5_in,input signed [WIDTH-1:0] a6_in,input signed [WIDTH-1:0] a7_in,input signed [WIDTH-1:0] a8_in,
	input signed [WIDTH-1:0] y0_in,input signed [WIDTH-1:0] y1_in,input signed [WIDTH-1:0] y2_in,input signed [WIDTH-1:0] y3_in,
	input signed [WIDTH-1:0] y4_in,input signed [WIDTH-1:0] y5_in,input signed [WIDTH-1:0] y6_in,input signed [WIDTH-1:0] y7_in,input signed [WIDTH-1:0] y8_in,
	
	output wire signed [WIDTH-1:0]outreg1
);

reg signed[WIDTH-1:0] a_reg;
reg signed[WIDTH-1:0] y_reg;
wire signed[2*WIDTH-1:0]mult1_out;
//wire[2*WIDTH-1:0] outreg1;
reg signed[2*WIDTH-1:0]multi_out;
reg [3:0]clk_counter;
reg signed[WIDTH-1:0] sum1;


initial 
begin 
clk_counter=0;
sum1=0;
multi_out=0;
end
//assign mult1_out=0;
multiplier_unit mul1(a_reg,y_reg,mult1_out);
adder_unit add1({mult1_out[2*WIDTH-1],mult1_out[2*WIDTH-11:0]},sum1,outreg1);
always @ (posedge clk)
begin

	case(clk_counter)
		0:begin
			a_reg <= a0_in;			
			y_reg <= y0_in;
			//multi_out<=0;
			clk_counter<=clk_counter+1;
			end
		1:begin
			a_reg <= a1_in;//mult1 computed
			y_reg <= y1_in;
			//multi_out<=mult1_out;
			sum1<=outreg1;
			clk_counter<=clk_counter+1;
			end
		2:begin
			a_reg <= a2_in;//mult1 computed
			y_reg <= y2_in;
			//multi_out<=mult1_out;
			sum1<=outreg1;
			clk_counter<=clk_counter+1;
			end
		3:begin
			a_reg <= a3_in;//mult1 computed
			y_reg <= y3_in;
			//multi_out<=mult1_out;
			sum1<=outreg1;
			clk_counter<=clk_counter+1;
			end
		4:begin
			a_reg <= a4_in;//mult1 computed
			y_reg <= y4_in;
			//multi_out<=mult1_out;
			sum1<=outreg1;
			clk_counter<=clk_counter+1;
			end
		5:begin
			a_reg <= a5_in;//mult1 computed
			y_reg <= y5_in;
			//multi_out<=mult1_out;
			sum1<=outreg1;
			clk_counter<=clk_counter+1;
			end
		6:begin
			a_reg <= a6_in;//mult1 computed
			y_reg <= y6_in;
			//multi_out<=mult1_out;
			sum1<=outreg1;
			clk_counter<=clk_counter+1;
			end
		7:begin
			a_reg <= a7_in;//mult1 computed
			y_reg <= y7_in;
			//multi_out<=mult1_out;
			sum1<=outreg1;
			clk_counter<=clk_counter+1;
			end
		8:begin
			a_reg <= a8_in;//mult1 computed
			y_reg <= y8_in;
			//multi_out<=mult1_out;
			sum1<=outreg1;
			clk_counter<=clk_counter+1;
			
			end
	endcase

end




endmodule
module equation1 (
clk, 

A1, A2, A3, A4, A5, A6, A7, A8, A9,
    
B1, B2, B3, B4, B5, B6, B7, B8, B9,
    
U1, U2, U3, U4, U5, U6, U7, U8, U9,

Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9,
	
I,

out
  );
	input clk;
	
	input wire signed [`WIDTH - 1:0] A1, A2, A3, A4, A5, A6, A7, A8, A9;
	input wire signed [`WIDTH - 1:0] B1, B2, B3, B4, B5, B6, B7, B8, B9;
	input wire signed [`WIDTH - 1:0] U1, U2, U3, U4, U5, U6, U7, U8, U9;
	input wire signed [`WIDTH - 1:0] Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9;
	wire signed [`WIDTH - 1:0] outY;
	wire signed [`WIDTH - 1:0] outU;
	wire signed [`WIDTH - 1:0] ayplusbu;
	input wire signed [`WIDTH - 1:0] I;
	output wire signed [`WIDTH - 1:0] out;
	
	//assign outY = (A1 * Y1)+ (A2 * Y2) + (A3 * Y3) + (A4 * Y4) + (A5 * Y5) + (A6 * Y6) + (A7 * Y7) + (A8 * Y8) + (A9 * Y9);
	//assign outU = (B1 * U1)+ (B2 * U2) + (B3 * U3) + (B4 * U4) + (B5 * U5) + (B6 * U6) + (B7 * U7) + (B8 * U8) + (B9 * U9);
	convolution conv1(clk, A1, A2, A3, A4, A5, A6, A7, A8, A9,Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9,outY);
	convolution conv2(clk, B1, B2, B3, B4, B5, B6, B7, B8, B9,U1, U2, U3, U4, U5, U6, U7, U8, U9,outU);
	adder_unit add2(outY,outU,ayplusbu);
	adder_unit add3(I,ayplusbu,out);
 //out = outY + outU + I;
endmodule
module aib_redundancy ( //input of input mux
idata0_in1, idata0_in0, idata1_in1, idata1_in0, 
idataselb_in1, idataselb_in0, iddren_in1, iddren_in0,
irxen_in1, irxen_in0, itxen_in1, itxen_in0, async_dat_in1, async_dat_in0, 
//Output of input mux
idata0_out, idata1_out, idataselb_out, iddren_out,
irxen_out, itxen_out, async_dat_out,

//input of output mux
odat0_in1, odat0_in0, odat1_in1, odat1_in0, odat_async_in1, odat_async_in0,

//Output of output mux
odat0_out, odat1_out, odat_async_out,

//Mux selection signal
shift_en	

);

//Mux selection signal
input shift_en;

//input of input mux
input idata0_in1, idata0_in0; 
input idata1_in1, idata1_in0;
input idataselb_in1, idataselb_in0;
input iddren_in1, iddren_in0;
input [2:0] irxen_in1, irxen_in0;
input itxen_in1, itxen_in0; 
input async_dat_in1, async_dat_in0;

//output of input mux
output idata0_out; 
output idata1_out;
output idataselb_out;
output iddren_out;
output [2:0] irxen_out;
output itxen_out; 
output async_dat_out;


//input of output mux
input odat0_in1, odat0_in0; 
input odat1_in1, odat1_in0;
input odat_async_in1, odat_async_in0;

//output of output mux
output odat0_out; 
output odat1_out;
output odat_async_out;

// Buses in the design


//input mux
assign idata0_out = shift_en? idata0_in1 : idata0_in0;
assign idata1_out = shift_en? idata1_in1 : idata1_in0;
assign idataselb_out = shift_en? idataselb_in1 : idataselb_in0 ;
assign iddren_out = shift_en? iddren_in1 : iddren_in0;
assign irxen_out[2] = shift_en? irxen_in1[2] : irxen_in0[2];
assign irxen_out[1] = shift_en? irxen_in1[1] : irxen_in0[1];
assign irxen_out[0] = shift_en? irxen_in1[0] : irxen_in0[0];
assign itxen_out = shift_en? itxen_in1 : itxen_in0;

//Change to CKMUX
//assign async_dat_out = shift_en? async_dat_in1 : async_dat_in0;


aib_mux21 async_dat_out_ckmux (

						.mux_in0      (async_dat_in0),
						.mux_in1      (async_dat_in1),
						.mux_sel      (shift_en),
						.mux_out      (async_dat_out)
				);

//output mux
assign odat0_out = shift_en? odat0_in1 : odat0_in0;
assign odat1_out = shift_en? odat1_in1 : odat1_in0;

//Change to CKMUX
//assign odat_async_out = shift_en? odat_async_in1 : odat_async_in0;


aib_mux21 odat_async_out_ckmux (

						.mux_in0      (odat_async_in0),
						.mux_in1      (odat_async_in1),
						.mux_sel      (shift_en),
						.mux_out      (odat_async_out)
				);

endmodule
module aib_bitsync
  #(
    parameter DWIDTH = 1'b1,    // Sync Data input
    parameter RESET_VAL = 1'b0  // Reset value
    )
    (
    input  wire              clk,     // clock
    input  wire              rst_n,   // async reset
    input  wire [DWIDTH-1:0] data_in, // data in
    output wire [DWIDTH-1:0] data_out // data out
     );


   // End users may pass in RESET_VAL with a width exceeding 1 bit
   // Evaluate the value first and use 1 bit value
   localparam RESET_VAL_1B = (RESET_VAL == 'd0) ? 1'b0 : 1'b1;

   reg [DWIDTH-1:0]  dff2;
   reg [DWIDTH-1:0]  dff1;

   always @(posedge clk or negedge rst_n)
      if (!rst_n) begin
         dff2     <= {DWIDTH{RESET_VAL_1B}}; 
         dff1     <= {DWIDTH{RESET_VAL_1B}}; 
      end
      else begin
         dff2     <= dff1;
         dff1     <= data_in;
      end

   assign data_out = dff2;


endmodule // aib_bitsync
module aib_aux_channel 
   (
    // AIB IO Bidirectional 
    inout wire          iopad_dev_dect,
    inout wire          iopad_dev_dectrdcy,
    inout wire          iopad_dev_por,
    inout wire          iopad_dev_porrdcy,

    input               m_por_ovrd, //Master onlhy input, it overrides the por signal. For slave, it is tied to "0"
    input               m_device_detect_ovrd, //Slave only input, it overrides the device_detect signal. For Master, it is tied to "0"
    output wire         por_ms,
    output wire         m_device_detect,
    input               por_sl,
    output wire         osc_clk,
    input               ms_nsl, //"1", this is a Master. "0", this is a Slave
    input               irstb // Output buffer tri-state enable
    );


aib_aliasd aliaspor ( .sig_red(iopad_dev_porrdcy), .sig_in(iopad_dev_por));
aib_aliasd aliasdet ( .sig_red(iopad_dev_dectrdcy), .sig_in(iopad_dev_dect));

   wire device_detect_oe;
   wire device_detect_ie;
   
   wire por_oe;
   wire por_ie;

   wire device_detect_sl_main;

   wire por_ms_main;

   assign m_device_detect = device_detect_sl_main | m_device_detect_ovrd;

   assign por_ms = por_ms_main & m_por_ovrd;
   
   assign device_detect_oe = (ms_nsl == 1'b1) ? 1'b1 : 1'b0;
   assign device_detect_ie = !device_detect_oe;

   assign por_oe = (ms_nsl == 1'b1) ? 1'b0 : 1'b1;
   assign por_ie = !por_oe;

	   aib_io_buffer u_device_detect 
	     (
	      // Tx Path
	      .ilaunch_clk (1'b0),
	      .irstb       (irstb),
	      .idat0       (1'b1),
	      .idat1       (1'b1),
	      .async_data  (1'b1),
	      .oclkn       (),

	      // Rx Path
	      .iclkn       (1'b0),
	      .inclk       (1'b0),
	      .inclk_dist  (1'b0),
	      .oclk        (),
	      .oclk_b      (),
	      .odat0       (),
	      .odat1       (),
	      .odat_async  (device_detect_sl_main),

	      // Bidirectional Data 
	      .io_pad      (iopad_dev_dect),

	      // I/O configuration
	      .async       (1'b1),
	      .ddren       (1'b0),
	      .txen        (device_detect_oe),
	      .rxen        (device_detect_ie),
	      .weaken      (device_detect_ie),
	      .weakdir     (1'b0)
	      );

	   aib_io_buffer u_device_por 
	     (
	      // Tx Path
	      .ilaunch_clk (1'b0),
	      .irstb       (irstb),
	      .idat0       (por_sl),
	      .idat1       (por_sl),
	      .async_data  (por_sl),
	      .oclkn       (),

	      // Rx Path
	      .iclkn       (1'b0),
	      .inclk       (1'b0),
	      .inclk_dist  (1'b0),
	      .oclk        (),
	      .oclk_b      (),
	      .odat0       (),
	      .odat1       (),
	      .odat_async  (por_ms_main),

	      // Bidirectional Data 
	      .io_pad      (iopad_dev_por),

	      // I/O configuration
	      .async       (1'b1),
	      .ddren       (1'b0),
	      .txen        (por_oe),
	      .rxen        (por_ie),
	      .weaken      (por_ie),
	      .weakdir     (1'b1)
	      );


aib_osc_clk  aib_osc_clk
    (.osc_clk(osc_clk)
    );

endmodule // aib_aux_channel
module aib_aliasd( sig_in, sig_red );

    output   sig_red;
    input    sig_in;

    assign sig_red = sig_in;

 endmodule
module aib_rstnsync
  (
    input wire 	clk,		// Destination clock of reset to be synced
    input wire 	i_rst_n,        // Asynchronous reset input
    input wire	scan_mode,	// Scan bypass for reset
    output wire sync_rst_n	// Synchronized reset output
   
   );

   reg	first_stg_rst_n;					     
   wire prescan_sync_rst_n;
   
   always @(posedge clk or negedge i_rst_n)
     if (!i_rst_n)
       first_stg_rst_n <= 1'b0;
     else
       first_stg_rst_n <= 1'b1;

   aib_bitsync 
     #(.DWIDTH(1), .RESET_VAL(0)                      ) 
   i_sync_rst_n
     (
      .clk           (clk               ),
      .rst_n         (i_rst_n           ), 
      .data_in       (first_stg_rst_n   ),
      .data_out      (prescan_sync_rst_n) 
      );

    assign sync_rst_n = scan_mode ? i_rst_n : prescan_sync_rst_n;

      
   endmodule
module aib_mux21
    (
    input  wire              mux_in0,     // mux in 0
    input  wire              mux_in1,     // mux in 1
    input  wire              mux_sel,     // mux selector
    output  wire             mux_out      // mux out
     );

    assign mux_out = mux_sel ? mux_in1 : mux_in0;

endmodule
module aib_dcc

   (
    // AIB IO Bidirectional 
    input                  clk_in,    
    input                  ms_dcc_cal_req, 
    input                  ms_tx_dcc_dll_lock_req, 
    input                  sl_dcc_cal_req, 
    input                  sl_rx_dcc_dll_lock_req, 
    output wire            ms_dcc_cal_done,
    output wire            sl_dcc_cal_done,
    output wire            clk_out,
    input                  ms_nsl,
    input                  atpg_mode,
    input                  reset_n       

    );

reg       ms_dcc_cal_done_r, sl_dcc_cal_done_r;
wire      ms_dcc_cal_donew, sl_dcc_cal_donew;
wire      ms_dcc_cal_req_sync, sl_dcc_cal_req_sync;
wire      reset_n_sync;

assign clk_out = clk_in;
assign ms_dcc_cal_done = ms_dcc_cal_done_r;
assign sl_dcc_cal_done = sl_dcc_cal_done_r;

assign ms_dcc_cal_donew = !ms_tx_dcc_dll_lock_req ? 1'b0 :
                          (ms_nsl & ms_dcc_cal_req_sync ) ? 1'b1 : ms_dcc_cal_done_r;
assign sl_dcc_cal_donew = !sl_rx_dcc_dll_lock_req ? 1'b0 :
                          (!ms_nsl & sl_dcc_cal_req_sync ) ? 1'b1 : sl_dcc_cal_done_r;

aib_rstnsync aib_rstnsync
  (
    .clk(clk_in),            // Destination clock of reset to be synced
    .i_rst_n(reset_n),        // Asynchronous reset input
    .scan_mode(atpg_mode),      // Scan bypass for reset
    .sync_rst_n(reset_n_sync)      // Synchronized reset output

   );

       aib_bitsync i_mstxdlldcclockreq
           (
           .clk(clk_in),
           .rst_n(reset_n_sync), 
           .data_in(ms_dcc_cal_req),
           .data_out(ms_dcc_cal_req_sync)
           );

       aib_bitsync i_sltxdlldcclockreq
           (
           .clk(clk_in),
           .rst_n(reset_n_sync), 
           .data_in(sl_dcc_cal_req),
           .data_out(sl_dcc_cal_req_sync)
           );

always @(posedge clk_in or negedge reset_n_sync) begin
  if (~reset_n_sync)
   begin
    ms_dcc_cal_done_r <= 1'b0;
    sl_dcc_cal_done_r <= 1'b0;
   end
  else
   begin
    ms_dcc_cal_done_r <= ms_dcc_cal_donew;
    sl_dcc_cal_done_r <= sl_dcc_cal_donew;
   end
end



endmodule // aib_dcc
module aibcr3aux_osc_divby8 ( out_divby2, out_divby4, out_divby8,
     scan_out, vcc_aibcr3aux, vss_aibcr3aux, clkin, por, scan_clk,
     scan_in, scan_mode_n, scan_rst_n, scan_shift_n );

output  out_divby2, out_divby4, out_divby8, scan_out;

inout  vcc_aibcr3aux, vss_aibcr3aux;

input  clkin, por, scan_clk, scan_in, scan_mode_n, scan_rst_n,
     scan_shift_n;

wire out_divby2, net119, net114, out_divby4, net118, net113, net117, net120, out_divby8;

wire so0;
wire so1;

// specify 
//     specparam CDS_LIBNAME  = "aibcr3aux_lib";
//     specparam CDS_CELLNAME = "aibcr3aux_osc_divby8";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign out_divby2 = ~net119;
assign net119 = ~net114;
assign out_divby4 = ~net118;
assign net118 = ~net113;
assign net117 = ~net120;
assign out_divby8 = ~net117;
aibcr3aux_osc_div2_asyn_clr xdiv8_1 ( .scan_shift_n(scan_shift_n),
     .scan_clk(scan_clk), .scan_out(so0), .scan_in(scan_in),
     .scan_mode_n(scan_mode_n), .scan_rst_n(scan_rst_n),
     .vss_aibcraux(vss_aibcr3aux), .vcc_aibcraux(vcc_aibcr3aux),
     .clkout(net114), .irstb(por), .clkin(clkin));
aibcr3aux_osc_div2_asyn_clr xdiv8_2 ( .scan_shift_n(scan_shift_n),
     .scan_clk(scan_clk), .scan_out(so1), .scan_in(so0),
     .scan_mode_n(scan_mode_n), .scan_rst_n(scan_rst_n),
     .vss_aibcraux(vss_aibcr3aux), .vcc_aibcraux(vcc_aibcr3aux),
     .clkout(net113), .irstb(por), .clkin(net114));
aibcr3aux_osc_div2_asyn_clr xdiv8_3 ( .scan_shift_n(scan_shift_n),
     .scan_clk(scan_clk), .scan_out(scan_out), .scan_in(so1),
     .scan_mode_n(scan_mode_n), .scan_rst_n(scan_rst_n),
     .vss_aibcraux(vss_aibcr3aux), .vcc_aibcraux(vcc_aibcr3aux),
     .clkout(net120), .irstb(por), .clkin(net113));

endmodule
module aibcr3aux_osc_sync ( en_out, resetb_out, scan_out, vcc_aibcraux,
     vss_aibcraux, clk, d, resetb, scan_clk, scan_in, scan_mode_n,
     scan_rst_n, scan_shift_n );

output  en_out, resetb_out, scan_out;

inout  vcc_aibcraux, vss_aibcraux;

input  clk, d, resetb, scan_clk, scan_in, scan_mode_n, scan_rst_n,
     scan_shift_n;

wire scanmoden, scan_mode_n, scanrstn, scan_rst_n, scanclk, scan_clk, scanin, scan_in, scanshftn, scan_shift_n, resetb_out, net062, dff_clk, net036, net044, resetb, clk;

wire so0;
wire scanshft;

// specify 
//     specparam CDS_LIBNAME  = "aibcraux_lib";
//     specparam CDS_CELLNAME = "aibcraux_osc_sync";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign scanmoden = scan_mode_n;
assign scanrstn = scan_rst_n;
assign scanclk = scan_clk;
assign scanin = scan_in;
assign scanshftn = scan_shift_n;
assign scanshft = ~scan_shift_n;
assign resetb_out = scanmoden ? net062 : scanrstn;
assign dff_clk = scanmoden ? net036 : scanclk;
/*aibcr3aux_osc_ff xreset_sync ( .cdn(net044), .vbb(vss_aibcraux),
     .vss(vss_aibcraux), .vdd(vcc_aibcraux), .vpp(vcc_aibcraux),
     .q(net062), .so(so0), .cp(dff_clk), .d(vcc_aibcraux),
     .se_n(scanshftn), .si(scanin));*/
assign net044 = scanmoden ? resetb : scanrstn;
/*aibcr3aux_osc_sync_ff x7 (  
     .CDN(resetb_out), .CP(dff_clk), .D(d), .Q(en_out),
       .so(scan_out),
     .se_n(scanshftn), .si(so0));*/
aibcr3_ulvt16_2xarstsyncdff1_b2 x99(.CLR_N(resetb_out), .CK(dff_clk), .D(d), .Q(en_out), .SE(scanshft), .SI(so0));
assign scan_out = en_out;
// reset synchronizer
aibcr3_ulvt16_2xarstsyncdff1_b2 x31(.CLR_N(net044),.CK(dff_clk), .D(vcc_aibcraux), .Q(net062), .SE(scanshft), .SI(scanin));
assign so0 = net062;


assign net036 = ~clk;

endmodule
module aibcr3aux_osc_div2_asyn_clr ( clkout, scan_out, vcc_aibcraux,
     vss_aibcraux, clkin, irstb, scan_clk, scan_in, scan_mode_n,
     scan_rst_n, scan_shift_n );

output  clkout, scan_out;

inout  vcc_aibcraux, vss_aibcraux;

input  clkin, irstb, scan_clk, scan_in, scan_mode_n, scan_rst_n,
     scan_shift_n;

wire net26, clkout, dff_clk, scan_modn, net019, clkin, dff_rstb, scan_rstn, irstb, scanshftn, scan_shift_n, scan_clk, scan_mode_n, scan_rst_n;


// specify 
//     specparam CDS_LIBNAME  = "aibcr3aux_lib";
//     specparam CDS_CELLNAME = "aibcr3aux_osc_div2_asyn_clr";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign net26 = ~clkout;
aibcr3aux_osc_ff x0 ( .cdn(dff_rstb), .vbb(vss_aibcraux),
     .vss(vss_aibcraux), .vdd(vcc_aibcraux), .vpp(vcc_aibcraux),
     .q(clkout), .so(scan_out), .cp(dff_clk), .d(net26),
     .se_n(scanshftn), .si(scan_in));
assign dff_clk = scan_modn ? clkin : net019;
assign dff_rstb = scan_modn ? irstb : scan_rstn;
assign scanshftn = scan_shift_n;
assign net019 = scan_clk;
assign scan_modn = scan_mode_n;
assign scan_rstn = scan_rst_n;

endmodule
module aibcr3aux_osc_dft ( osc2dft_out, scan_out, testpin_cntr_code,
     vcc_aibcraux, vss_aibcraux, counter, osc_clkin, scan_clk, scan_in,
     scan_mode_n, scan_rst_n, scan_shift_n, testpin_clk,
     testpin_enable, testpin_resetb );

output  scan_out;

inout  vcc_aibcraux, vss_aibcraux;

input  osc_clkin, scan_clk, scan_in, scan_mode_n, scan_rst_n,
     scan_shift_n, testpin_clk, testpin_enable, testpin_resetb;

output [5:0]  testpin_cntr_code;
output [8:6]  osc2dft_out;

input [2:0]  counter;

wire net167, net165, so3, vss_aibcraux, net050, scanmoden, scanrstn, net033, dff_clk, scanclk, net038, sync_in, net092, net162, net093, scanin, scan_in, scan_clk, scan_rst_n, scan_mode_n, testpin_resetb, testpin_clk, enable, resetb, scanshftn, scanshft, scan_shift_n;

wire so6;
wire so5;
wire so4;

// specify 
//     specparam CDS_LIBNAME  = "aibcraux_lib";
//     specparam CDS_CELLNAME = "aibcraux_osc_dft";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

aibcr3aux_osc_6bcntr x6bcntr ( .scan_shift_n(scanshftn),
     .scan_out(scan_out), .scan_clk(scanclk), .scan_in(so6),
     .scan_mode_n(scanmoden), .scan_rst_n(scanrstn),
     .vss_aibcraux(vss_aibcraux), .vcc_aibcraux(vcc_aibcraux),
     .out_bin(testpin_cntr_code[5:0]), .clk(osc_clkin),
     .cntr(counter[2:0]), .en(enable), .reset_n(resetb));
assign net167 = net165 ? vss_aibcraux : so3;
assign net050 = scanmoden ? net033 : scanrstn;
assign dff_clk = scanmoden ? net038 : scanclk;
assign sync_in = scanmoden ? net092 : scanclk;
assign net162 = scanmoden ? net093 : scanrstn;
assign scanin = scan_in;
assign scanclk = scan_clk;
assign scanrstn = scan_rst_n;
assign scanmoden = scan_mode_n;
assign net033 = testpin_resetb;
assign net038 = testpin_clk;
assign osc2dft_out[6] = enable;
assign osc2dft_out[8] = sync_in;
assign osc2dft_out[7] = resetb;
aibcr3aux_osc_sync xsync ( .scan_shift_n(scanshftn), .scan_out(so6),
     .scan_clk(scanclk), .scan_in(so5), .scan_mode_n(scanmoden),
     .scan_rst_n(scanrstn), .vss_aibcraux(vss_aibcraux),
     .vcc_aibcraux(vcc_aibcraux), .en_out(enable), .resetb_out(resetb),
     .clk(osc_clkin), .d(sync_in), .resetb(net162));
aibcr3aux_osc_ff x23 ( .cdn(net162), .vbb(vss_aibcraux),
     .vss(vss_aibcraux), .vdd(vcc_aibcraux), .vpp(vcc_aibcraux),
     .q(net092), .so(so4), .cp(dff_clk), .d(net167), .se_n(scanshftn),
     .si(so3));
aibcr3aux_osc_ff x22 ( .cdn(net162), .vbb(vss_aibcraux),
     .vss(vss_aibcraux), .vdd(vcc_aibcraux), .vpp(vcc_aibcraux),
     .q(net165), .so(so5), .cp(sync_in), .d(vcc_aibcraux),
     .se_n(scanshftn), .si(so4));
aibcr3_sync_2ff  xsync0 (      .SE(scanshft), .D(vcc_aibcraux),  .Q(net093),     .CP(dff_clk),  .SI(scanin), .CDN(net050));
aibcr3_sync_2ff  x27 (  .SE(scanshft),     .D(testpin_enable),  .Q(so3), .CP(dff_clk),      .SI(net093), .CDN(net162));
assign scanshftn = ~scanshft;
assign scanshft = ~scan_shift_n;

endmodule
module aibcr3aux_osc_lsbuf ( out, vccl, vccreg, vss, vssreg, in );

output  out;

inout  vccl, vccreg, vss, vssreg;

input  in;

wire in2b, in2, out, inb, in;



assign in2b = ~in2;
assign out = ~in2b;
assign in2 = ~inb;
assign inb = ~in;

endmodule
module aibcr3aux_inclkdly
 
#(
 parameter PERIOD = 500
)
(
output clkout,

input  clkin, clkinb, csr_dly_ovrden, ib50u_ring, ib50uc, vcc_aibcr3aux,
     vssl_aibcr3aux,

input [3:0]  csr_dly_ovrd,
input [9:0]  iosc_fuse_trim
);
//wire vssl , net033 , nbias , vbias , nocon0 , net032 ;




 
assign #PERIOD clkout =  clkin;

endmodule
module aibcr3aux_osc ( ib50u1, ib50u2, ib50u3, ib50u4, oaib_dft2osc,
     oosc_atb0, oosc_atb1, oosc_clkout, oosc_monitor, oosc_reserved,
     scan_out, vcca_aibcraux, vcc_aibcraux, vss_aibcraux, iaib_dft2osc, iosc_atbmuxsel,
     iosc_bypclk, iosc_bypclken, iosc_cr_dftcounter, iosc_cr_ld_cntr,
     iosc_cr_pdb, iosc_cr_rdy_dly, iosc_cr_trim, iosc_cr_vccdreg_vsel,
     iosc_cr_vreg_rdy, iosc_fuse_trim, iosc_ic50u, iosc_it50u,
     iosc_monitoren, iosc_reserved, pipeline_global_en, scan_clk,
     scan_in, scan_mode_n, scan_rst_n, scan_shift_n, osc_extrref );

output  ib50u1, ib50u2, ib50u3, ib50u4, oosc_atb0, oosc_atb1,
     oosc_clkout, oosc_monitor, scan_out;

input  vcca_aibcraux, vcc_aibcraux, vss_aibcraux, iosc_bypclk, iosc_bypclken, iosc_cr_pdb,
     iosc_cr_rdy_dly, iosc_ic50u, iosc_it50u, iosc_monitoren,
     pipeline_global_en, scan_clk, scan_in, scan_mode_n, scan_rst_n,
     scan_shift_n;

inout osc_extrref;

output [12:0]  oaib_dft2osc;
output [3:0]  oosc_reserved;

input [2:0]  iosc_cr_vreg_rdy;
input [4:0]  iosc_cr_vccdreg_vsel;
input [3:0]  iosc_atbmuxsel;
input [2:0]  iaib_dft2osc;
input [2:0]  iosc_cr_dftcounter;
input [8:0]  iosc_cr_trim;
input [2:0]  iosc_cr_ld_cntr;
input [7:0]  iosc_reserved;
input [9:0]  iosc_fuse_trim;

wire chicken_bit;
wire comparator_out;
wire osc_2x;

			/////////////////////////////////
			// for VCS and ICC compatibility
			/////////////////////////////////

aibcr3aux_osc_ana  ana ( // .ib50u({ib50u3,ib50u1}), .ib100u({ib50u4,ib50u2}),
     .ib50u_1(ib50u1), .ib50u_2(ib50u3), .ib100u_1(ib50u2), .ib100u_2(ib50u4), .chicken_bit(chicken_bit),
     .comp_out(comparator_out), .osc_atb1(oosc_atb1),
     .osc_atb0(oosc_atb0), .vcca_aibcr3aux(vcca_aibcraux), .vcc_aibcr3aux(vcc_aibcraux),
     .vss_aibcr3aux(vss_aibcraux), .iosc_atbmuxsel(iosc_atbmuxsel[3:0]),
     .osc_out(osc_2x), .iosc_cr_pdb(iosc_cr_pdb),
     .iosc_cr_trim(iosc_cr_trim[8:0]),
     .iosc_cr_vccdreg_vsel(iosc_cr_vccdreg_vsel[4:0]),
     .iosc_cr_vreg_rdy(iosc_cr_vreg_rdy[2:0]),
     .iosc_fuse_trim(iosc_fuse_trim[9:0]), .iosc_ic50u(iosc_ic50u),
     .iosc_it50u(iosc_it50u), .osc_extrref(osc_extrref));
aibcr3aux_osc_dig dig ( .scan_shift_n(scan_shift_n),
     .pipeline_global_en(pipeline_global_en), .scan_out(scan_out),
     .scan_clk(scan_clk), .scan_in(scan_in), .scan_mode_n(scan_mode_n),
     .scan_rst_n(scan_rst_n), .chicken_bit(chicken_bit),
     .vss_aibcr3aux(vss_aibcraux), .vcc_aibcr3aux(vcc_aibcraux),
     .comp_in(comparator_out), .iosc_cr_ld_cntr(iosc_cr_ld_cntr[2:0]),
     .oosc_monitor(oosc_monitor), .oaib_dft2osc(oaib_dft2osc[12:0]),
     .oosc_clkout(oosc_clkout), .iaib_dft2osc(iaib_dft2osc[2:0]),
     .iosc_bypclk(iosc_bypclk), .iosc_bypclken(iosc_bypclken),
     .iosc_cr_dftcounter(iosc_cr_dftcounter[2:0]),
     .iosc_monitoren(iosc_monitoren), .irstb(iosc_cr_rdy_dly),
     .oscin_2x(osc_2x));

endmodule
module aibcr3aux_osc_ff ( q, so, vbb, vdd, vpp, vss, cdn, cp, d, se_n,
     si );

output  q, so;

inout  vbb, vdd, vpp, vss;

input  cdn, cp, d, se_n, si;

wire so, q, net68, se_n, si, SE;


// specify 
//     specparam CDS_LIBNAME  = "aibcraux_lib";
//     specparam CDS_CELLNAME = "aibcraux_osc_ff";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign SE = ~se_n;
// aibcr3_ff_r x0 (   .CDN(cdn), .CP(cp), .D(net68), .Q(q));
aibcr3_svt16_scdffcdn_cust x0 (.CDN(cdn), .CK(cp), .D(d), .Q(q), .SI(si), .SE(SE), .scQ(so));

endmodule
module aibcr3aux_osc_ana (
                                         ////////////////////////////////
                                         // inputs and output pins
                                         ////////////////////////////////

    input [3:0] iosc_atbmuxsel,
    input [4:0] iosc_cr_vccdreg_vsel,  // controls supply to osc, not implemented
    input [2:0] iosc_cr_vreg_rdy,      // comparator reference, not implemented
    input iosc_ic50u,                      // 50uA supply, not implemented
    input iosc_it50u,                      // 50uA supply, not implemented
    input [9:0] iosc_fuse_trim,     
    input [8:0] iosc_cr_trim,          // trim osc freq, not implemented
                                           // except iosc_cr_trim[7] (chicken bit)
    input iosc_cr_pdb,                     // 0: turn off oscillator

    inout vss_aibcr3aux,
    inout vcc_aibcr3aux,
    inout vcca_aibcr3aux,

    output osc_out,                         // oscillator output
    output osc_atb0,
    output osc_atb1,
    output chicken_bit,
    output comp_out,                         // deprecate
    // output [2:1] ib50u,
    output ib50u_1,
    output ib50u_2, 
    // output [2:1] ib100u,
    output ib100u_2,
    output ib100u_1,   
    inout  osc_extrref
);

                                         ////////////////////////////////
                                         // constants
                                         ////////////////////////////////

    parameter PERIOD = 500;               // oscillator period
    parameter CYCLE  = 100000000;        // number of cycles


                                         ////////////////////////////////
                                         // local variables
                                         ////////////////////////////////
    reg osc_clk;
    reg q;
                                         ////////////////////////////////
                                         // generate oscillator clock
                                         ////////////////////////////////
    initial begin
        osc_clk = 1'b0;
    end
    always begin
        #250 osc_clk = ~osc_clk;         // 250ps is the half period of clock
    end


                                         ////////////////////////////////
                                         // osc power up/down condition
                                         ////////////////////////////////
    // need to add case statement to allow oscillator to spin, only if the
    // osc_extrref is weakly pulled down at the chip level. update pending   
 
    and (osc_out, osc_clk, iosc_cr_pdb);
    assign chicken_bit = iosc_fuse_trim[9] ? iosc_fuse_trim[7] : iosc_cr_trim[7];
    assign {osc_atb0,osc_atb1} = 2'bzz;

endmodule
module aibcr3aux_osc_6bcntr ( out_bin, scan_out, vcc_aibcraux,
     vss_aibcraux, clk, cntr, en, reset_n, scan_clk, scan_in,
     scan_mode_n, scan_rst_n, scan_shift_n );

output  scan_out;

inout  vcc_aibcraux, vss_aibcraux;

input  clk, en, reset_n, scan_clk, scan_in, scan_mode_n, scan_rst_n,
     scan_shift_n;

output [5:0]  out_bin;

input [2:0]  cntr;

wire clkin, net77, overflow, net78, en, clk, clkdiv2, net038, net037, scan_out;

// Buses in the design

wire  [5:0]  cnt;
wire so0;
wire so1;


// specify 
//     specparam CDS_LIBNAME  = "aibcraux_lib";
//     specparam CDS_CELLNAME = "aibcraux_osc_6bcntr";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign clkin = ~net77;
assign overflow = ~cnt[2];
assign out_bin[5:0] = cnt[5:0];
assign net77 = ~(net78 & en);
assign net78 = cntr[0] ? clkdiv2 : clk;
aibcr3aux_osc_div2_asyn_clr x13 ( .scan_shift_n(scan_shift_n),
     .scan_out(so0), .scan_clk(scan_clk), .scan_in(scan_in),
     .scan_mode_n(scan_mode_n), .scan_rst_n(scan_rst_n),
     .vss_aibcraux(vss_aibcraux), .vcc_aibcraux(vcc_aibcraux),
     .clkout(clkdiv2), .irstb(reset_n), .clkin(clk));
aibcr3aux_osc_3bcntr xbincntr_lsb ( .scan_shift_n(scan_shift_n),
     .scan_out(so1), .scan_clk(scan_clk), .scan_in(so0),
     .scan_mode_n(scan_mode_n), .scan_rst_n(scan_rst_n),
     .vss_aibcraux(vss_aibcraux), .vcc_aibcraux(vcc_aibcraux),
     .bin_cnt(cnt[2:0]), .clk(clkin), .rstb(reset_n));
aibcr3aux_osc_3bcntr xbincntr_msb ( .scan_shift_n(scan_shift_n),
     .scan_out(net037), .scan_clk(scan_clk), .scan_in(so1),
     .scan_mode_n(scan_mode_n), .scan_rst_n(scan_rst_n),
     .vss_aibcraux(vss_aibcraux), .vcc_aibcraux(vcc_aibcraux),
     .bin_cnt(cnt[5:3]), .clk(overflow), .rstb(reset_n));
assign net038 = ~net037;
assign scan_out = ~net038;

endmodule
module aibcr3aux_lvshift ( out, vccl_aibcr3aux, vcc_aibcr3aux, vssl_aibcr3aux, in);

output  out;

input  vccl_aibcr3aux, vcc_aibcr3aux, vssl_aibcr3aux;

input  in;
reg out;
//wire NET58 , in_shift , in_shiftb , inb , in_sw , NET59 ;
//no vccl_aibcr3aux, vcc_aibcr3aux and vssl_aibcr3aux tracking as of now.
always @ (in, vccl_aibcr3aux, vcc_aibcr3aux)
begin
	if (vccl_aibcr3aux == 1'b0 && vcc_aibcr3aux == 1'b0) 
	begin
		out = 1'b0;		
	end
	else if (vccl_aibcr3aux == 1'b0 && vcc_aibcr3aux == 1'b1)
	begin
		out = 1'b1;
	end
	else if (vccl_aibcr3aux == 1'b1 && vcc_aibcr3aux == 1'b0)
	begin
		out = 1'b0;
	end
	else if (vccl_aibcr3aux == 1'b1 && vcc_aibcr3aux == 1'b1)
	begin
		out = in;
	end
	else
	begin
		out = 1'bx;
	end	
end
endmodule
module aibcr3aux_osc_clkgatesync ( clkgatesyncout, scan_out,
     vcc_aibcraux, vss_aibcraux, ckin, en, rstb, scan_clk, scan_in,
     scan_mode_n, scan_rst_n, scan_shift_n );

output  clkgatesyncout, scan_out;

inout  vcc_aibcraux, vss_aibcraux;

input  ckin, en, rstb, scan_clk, scan_in, scan_mode_n, scan_rst_n,
     scan_shift_n;

wire net023, ckin, clkgatesyncout, net027, net024, scanshft, scan_shift_n, scan_modn, scan_rstn, scan_out, dff_rstb, rstb, dff_clk, scan_ck, scan_mode_n, scan_clk, scan_rst_n;


// specify 
//     specparam CDS_LIBNAME  = "aibcraux_lib";
//     specparam CDS_CELLNAME = "aibcraux_osc_clkgatesync";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign net023 = ~ckin;
assign clkgatesyncout = ~net027;
assign net027 = ~(net024 & ckin);
assign scanshft = ~scan_shift_n;
assign net024 = scan_modn ? scan_out : scan_rstn;
assign dff_rstb = scan_modn ? rstb : scan_rstn;
assign dff_clk = scan_modn ? net023 : scan_ck;
aibcr3_sync_2ff  xsync0 (      .SE(scanshft), .D(en),  .Q(scan_out),     .CP(dff_clk),  .SI(scan_in), .CDN(dff_rstb));
assign scan_modn = scan_mode_n;
assign scan_ck = scan_clk;
assign scan_rstn = scan_rst_n;

endmodule
module aibcr3aux_osc_dly_unit ( q, so, cdn, cp, d, se_n, si, vbb, vdd,
     vpp, vss );

output  q, so;

input  cdn, cp, d, se_n, si, vbb, vdd, vpp, vss;

wire net21;
wire net22;

// specify 
//     specparam CDS_LIBNAME  = "aibcraux_lib";
//     specparam CDS_CELLNAME = "aibcraux_osc_dly_unit";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

aibcr3aux_osc_ff x0 ( .cdn(cdn), .vbb(vbb), .vss(vss), .vdd(vdd),
     .vpp(vpp), .q(net21), .so(net22), .cp(cp), .d(d), .se_n(se_n),
     .si(si));
aibcr3aux_osc_ff x1 ( .cdn(cdn), .vbb(vbb), .vss(vss), .vdd(vdd),
     .vpp(vpp), .q(q), .so(so), .cp(cp), .d(net21), .se_n(se_n),
     .si(net22));

endmodule
module aibcr3aux_osc_3bcntr ( bin_cnt, scan_out, vcc_aibcraux,
     vss_aibcraux, clk, rstb, scan_clk, scan_in, scan_mode_n,
     scan_rst_n, scan_shift_n );

output  scan_out;

inout  vcc_aibcraux, vss_aibcraux;

input  clk, rstb, scan_clk, scan_in, scan_mode_n, scan_rst_n,
     scan_shift_n;

output [2:0]  bin_cnt;

wire net150, net152, net147, net144, vcc_aibcraux, net065, scanmoden, scanclk, clk, net064, net063, net151, scanshftn, scan_shift_n, scanin, scan_in, scan_mode_n, scanrstn, scan_rst_n, scan_clk, net017, rstb;

// Buses in the design

wire  [2:0]  binary;

wire so0;
wire so1;

// specify 
//     specparam CDS_LIBNAME  = "aibcraux_lib";
//     specparam CDS_CELLNAME = "aibcraux_osc_3bcntr";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign net150 = net152 ^ binary[2];
assign net147 = binary[0] ^ binary[1];
assign net144 = vcc_aibcraux ^ binary[0];
assign net065 = scanmoden ? clk : scanclk;
assign net064 = scanmoden ? clk : scanclk;
assign net063 = scanmoden ? clk : scanclk;
assign net152 = ~net151;
assign net151 = ~(binary[1] & binary[0]);
assign scanshftn = scan_shift_n;
assign scanin = scan_in;
assign scanmoden = scan_mode_n;
assign scanrstn = scan_rst_n;
assign scanclk = scan_clk;
assign bin_cnt[2:0] = binary[2:0];
aibcr3aux_osc_ff x8 ( .cdn(net017), .vbb(vss_aibcraux),
     .vss(vss_aibcraux), .vdd(vcc_aibcraux), .vpp(vcc_aibcraux),
     .q(binary[0]), .so(so0), .cp(net064), .d(net144),
     .se_n(scanshftn), .si(scanin));
aibcr3aux_osc_ff x18 ( .cdn(net017), .vbb(vss_aibcraux),
     .vss(vss_aibcraux), .vdd(vcc_aibcraux), .vpp(vcc_aibcraux),
     .q(binary[2]), .so(scan_out), .cp(net065), .d(net150),
     .se_n(scanshftn), .si(so1));
aibcr3aux_osc_ff x16 ( .cdn(net017), .vbb(vss_aibcraux),
     .vss(vss_aibcraux), .vdd(vcc_aibcraux), .vpp(vcc_aibcraux),
     .q(binary[1]), .so(so1), .cp(net063), .d(net147),
     .se_n(scanshftn), .si(so0));
assign net017 = scanmoden ? rstb : scanrstn;

endmodule
module aibcr3aux_osc_sync_ff ( Q, so,  
       CDN, CP, D, se_n, si );

output  Q, so;

//inout  inh_BN, inh_BP, inh_VN, inh_VP;

input  CDN, CP, D, se_n, si;

wire net95, se_n, so, Q;


// specify 
//     specparam CDS_LIBNAME  = "aibcraux_lib";
//     specparam CDS_CELLNAME = "aibcraux_osc_sync_ff";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign net95 = ~se_n;
aibcr3_sync_3ff xsync0 (  .SE(net95),     .D(D),  .Q(Q), .CP(CP),  .SI(si),     .CDN(CDN));
assign so = Q;

endmodule