dakies/OSS_Verilog huggingface dataset:
module frac_lut4(in,
                 sram,
                 sram_inv,
                 mode,
                 mode_inv,
                 lut3_out,
                 lut4_out);
//----- INPUT PORTS -----
input [0:3] in;
//----- INPUT PORTS -----
input [0:15] sram;
//----- INPUT PORTS -----
input [0:15] sram_inv;
//----- INPUT PORTS -----
input [0:0] mode;
//----- INPUT PORTS -----
input [0:0] mode_inv;
//----- OUTPUT PORTS -----
output [0:1] lut3_out;
//----- OUTPUT PORTS -----
output [0:0] lut4_out;

//----- BEGIN wire-connection ports -----
wire [0:3] in;
wire [0:1] lut3_out;
wire [0:0] lut4_out;
//----- END wire-connection ports -----


//----- BEGIN Registered ports -----
//----- END Registered ports -----


wire [0:0] INVTX1_0_out;
wire [0:0] INVTX1_1_out;
wire [0:0] INVTX1_2_out;
wire [0:0] INVTX1_3_out;
wire [0:0] OR2_0_out;
wire [0:0] buf4_0_out;
wire [0:0] buf4_1_out;
wire [0:0] buf4_2_out;
wire [0:0] buf4_3_out;

// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----

	OR2 OR2_0_ (
		.a(mode),
		.b(in[3]),
		.out(OR2_0_out));

	INVTX1 INVTX1_0_ (
		.in(in[0]),
		.out(INVTX1_0_out));

	INVTX1 INVTX1_1_ (
		.in(in[1]),
		.out(INVTX1_1_out));

	INVTX1 INVTX1_2_ (
		.in(in[2]),
		.out(INVTX1_2_out));

	INVTX1 INVTX1_3_ (
		.in(OR2_0_out),
		.out(INVTX1_3_out));

	buf4 buf4_0_ (
		.in(in[0]),
		.out(buf4_0_out));

	buf4 buf4_1_ (
		.in(in[1]),
		.out(buf4_1_out));

	buf4 buf4_2_ (
		.in(in[2]),
		.out(buf4_2_out));

	buf4 buf4_3_ (
		.in(OR2_0_out),
		.out(buf4_3_out));

	frac_lut4_mux frac_lut4_mux_0_ (
		.in(sram[0:15]),
		.sram({buf4_0_out, buf4_1_out, buf4_2_out, buf4_3_out}),
		.sram_inv({INVTX1_0_out, INVTX1_1_out, INVTX1_2_out, INVTX1_3_out}),
		.lut3_out(lut3_out[0:1]),
		.lut4_out(lut4_out));

endmodule
module mux_2level_tapbuf_basis_input3_mem3(in,
                                           mem,
                                           mem_inv,
                                           out);
//----- INPUT PORTS -----
input [0:2] in;
//----- INPUT PORTS -----
input [0:2] mem;
//----- INPUT PORTS -----
input [0:2] mem_inv;
//----- OUTPUT PORTS -----
output [0:0] out;

//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----


//----- BEGIN Registered ports -----
//----- END Registered ports -----



// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----

	TGATE TGATE_0_ (
		.in(in[0]),
		.sel(mem[0]),
		.selb(mem_inv[0]),
		.out(out));

	TGATE TGATE_1_ (
		.in(in[1]),
		.sel(mem[1]),
		.selb(mem_inv[1]),
		.out(out));

	TGATE TGATE_2_ (
		.in(in[2]),
		.sel(mem[2]),
		.selb(mem_inv[2]),
		.out(out));

endmodule
module mux_2level_tapbuf_basis_input2_mem1(in,
                                           mem,
                                           mem_inv,
                                           out);
//----- INPUT PORTS -----
input [0:1] in;
//----- INPUT PORTS -----
input [0:0] mem;
//----- INPUT PORTS -----
input [0:0] mem_inv;
//----- OUTPUT PORTS -----
output [0:0] out;

//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----


//----- BEGIN Registered ports -----
//----- END Registered ports -----



// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----

	TGATE TGATE_0_ (
		.in(in[0]),
		.sel(mem),
		.selb(mem_inv),
		.out(out));

	TGATE TGATE_1_ (
		.in(in[1]),
		.sel(mem_inv),
		.selb(mem),
		.out(out));

endmodule
module mux_2level_tapbuf_basis_input4_mem4(in,
                                           mem,
                                           mem_inv,
                                           out);
//----- INPUT PORTS -----
input [0:3] in;
//----- INPUT PORTS -----
input [0:3] mem;
//----- INPUT PORTS -----
input [0:3] mem_inv;
//----- OUTPUT PORTS -----
output [0:0] out;

//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----


//----- BEGIN Registered ports -----
//----- END Registered ports -----



// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----

	TGATE TGATE_0_ (
		.in(in[0]),
		.sel(mem[0]),
		.selb(mem_inv[0]),
		.out(out));

	TGATE TGATE_1_ (
		.in(in[1]),
		.sel(mem[1]),
		.selb(mem_inv[1]),
		.out(out));

	TGATE TGATE_2_ (
		.in(in[2]),
		.sel(mem[2]),
		.selb(mem_inv[2]),
		.out(out));

	TGATE TGATE_3_ (
		.in(in[3]),
		.sel(mem[3]),
		.selb(mem_inv[3]),
		.out(out));

endmodule
module mux_2level_tapbuf_basis_input2_mem2(in,
                                           mem,
                                           mem_inv,
                                           out);
//----- INPUT PORTS -----
input [0:1] in;
//----- INPUT PORTS -----
input [0:1] mem;
//----- INPUT PORTS -----
input [0:1] mem_inv;
//----- OUTPUT PORTS -----
output [0:0] out;

//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----


//----- BEGIN Registered ports -----
//----- END Registered ports -----



// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----

	TGATE TGATE_0_ (
		.in(in[0]),
		.sel(mem[0]),
		.selb(mem_inv[0]),
		.out(out));

	TGATE TGATE_1_ (
		.in(in[1]),
		.sel(mem[1]),
		.selb(mem_inv[1]),
		.out(out));

endmodule
module mux_2level_basis_input5_mem5(in,
                                    mem,
                                    mem_inv,
                                    out);
//----- INPUT PORTS -----
input [0:4] in;
//----- INPUT PORTS -----
input [0:4] mem;
//----- INPUT PORTS -----
input [0:4] mem_inv;
//----- OUTPUT PORTS -----
output [0:0] out;

//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----


//----- BEGIN Registered ports -----
//----- END Registered ports -----



// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----

	TGATE TGATE_0_ (
		.in(in[0]),
		.sel(mem[0]),
		.selb(mem_inv[0]),
		.out(out));

	TGATE TGATE_1_ (
		.in(in[1]),
		.sel(mem[1]),
		.selb(mem_inv[1]),
		.out(out));

	TGATE TGATE_2_ (
		.in(in[2]),
		.sel(mem[2]),
		.selb(mem_inv[2]),
		.out(out));

	TGATE TGATE_3_ (
		.in(in[3]),
		.sel(mem[3]),
		.selb(mem_inv[3]),
		.out(out));

	TGATE TGATE_4_ (
		.in(in[4]),
		.sel(mem[4]),
		.selb(mem_inv[4]),
		.out(out));

endmodule
module mux_1level_tapbuf_basis_input4_mem4(in,
                                           mem,
                                           mem_inv,
                                           out);
//----- INPUT PORTS -----
input [0:3] in;
//----- INPUT PORTS -----
input [0:3] mem;
//----- INPUT PORTS -----
input [0:3] mem_inv;
//----- OUTPUT PORTS -----
output [0:0] out;

//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----


//----- BEGIN Registered ports -----
//----- END Registered ports -----



// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----

	TGATE TGATE_0_ (
		.in(in[0]),
		.sel(mem[0]),
		.selb(mem_inv[0]),
		.out(out));

	TGATE TGATE_1_ (
		.in(in[1]),
		.sel(mem[1]),
		.selb(mem_inv[1]),
		.out(out));

	TGATE TGATE_2_ (
		.in(in[2]),
		.sel(mem[2]),
		.selb(mem_inv[2]),
		.out(out));

	TGATE TGATE_3_ (
		.in(in[3]),
		.sel(mem[3]),
		.selb(mem_inv[3]),
		.out(out));

endmodule
module mux_1level_tapbuf_basis_input3_mem3(in,
                                           mem,
                                           mem_inv,
                                           out);
//----- INPUT PORTS -----
input [0:2] in;
//----- INPUT PORTS -----
input [0:2] mem;
//----- INPUT PORTS -----
input [0:2] mem_inv;
//----- OUTPUT PORTS -----
output [0:0] out;

//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----


//----- BEGIN Registered ports -----
//----- END Registered ports -----



// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----

	TGATE TGATE_0_ (
		.in(in[0]),
		.sel(mem[0]),
		.selb(mem_inv[0]),
		.out(out));

	TGATE TGATE_1_ (
		.in(in[1]),
		.sel(mem[1]),
		.selb(mem_inv[1]),
		.out(out));

	TGATE TGATE_2_ (
		.in(in[2]),
		.sel(mem[2]),
		.selb(mem_inv[2]),
		.out(out));

endmodule
module frac_lut4_mux_basis_input2_mem1(in,
                                       mem,
                                       mem_inv,
                                       out);
//----- INPUT PORTS -----
input [0:1] in;
//----- INPUT PORTS -----
input [0:0] mem;
//----- INPUT PORTS -----
input [0:0] mem_inv;
//----- OUTPUT PORTS -----
output [0:0] out;

//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----


//----- BEGIN Registered ports -----
//----- END Registered ports -----



// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----

	TGATE TGATE_0_ (
		.in(in[0]),
		.sel(mem),
		.selb(mem_inv),
		.out(out));

	TGATE TGATE_1_ (
		.in(in[1]),
		.sel(mem_inv),
		.selb(mem),
		.out(out));

endmodule
module DFFR(RST,
            CK,
            D,
            Q,
            QN);
//----- GLOBAL PORTS -----
input [0:0] RST;
//----- GLOBAL PORTS -----
input [0:0] CK;
//----- INPUT PORTS -----
input [0:0] D;
//----- OUTPUT PORTS -----
output [0:0] Q;
//----- OUTPUT PORTS -----
output [0:0] QN;

//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----


//----- BEGIN Registered ports -----
//----- END Registered ports -----

// ----- Internal logic should start here -----


// ----- Internal logic should end here -----
endmodule
module ADDF(A,
            B,
            CI,
            SUM,
            CO);
//----- INPUT PORTS -----
input [0:0] A;
//----- INPUT PORTS -----
input [0:0] B;
//----- INPUT PORTS -----
input [0:0] CI;
//----- OUTPUT PORTS -----
output [0:0] SUM;
//----- OUTPUT PORTS -----
output [0:0] CO;

//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----


//----- BEGIN Registered ports -----
//----- END Registered ports -----

// ----- Internal logic should start here -----


// ----- Internal logic should end here -----
endmodule
module OR2(a,
           b,
           out);
//----- INPUT PORTS -----
input [0:0] a;
//----- INPUT PORTS -----
input [0:0] b;
//----- OUTPUT PORTS -----
output [0:0] out;

//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----


//----- BEGIN Registered ports -----
//----- END Registered ports -----

// ----- Verilog codes of a 2-input 1-output AND gate -----
	assign out[0] = a[0] | b[0];

`ifdef ENABLE_TIMING
// ------ BEGIN Pin-to-pin Timing constraints -----
	specify
		(a => out) = (0.01, 0.01);
		(b => out) = (0.005, 0.005);
	endspecify
// ------ END Pin-to-pin Timing constraints -----
`endif
endmodule
module and2_top_formal_verification_random_tb;
// ----- Default clock port is added here since benchmark does not contain one -------
	reg [0:0] clk;

// ----- Shared inputs -------
	reg [0:0] a;
	reg [0:0] b;

// ----- FPGA fabric outputs -------
	wire [0:0] c_gfpga;

// ----- Benchmark outputs -------
	wire [0:0] c_bench;

// ----- Output vectors checking flags -------
	reg [0:0] c_flag;

// ----- Error counter -------
	integer nb_error= 0;

// ----- FPGA fabric instanciation -------
	and2_top_formal_verification FPGA_DUT(
		.a(a),
		.b(b),
		.c(c_gfpga)
	);
// ----- End FPGA Fabric Instanication -------

// ----- Reference Benchmark Instanication -------
	and2 REF_DUT(
		.a(a),
		.b(b),
		.c(c_bench)
	);
// ----- End reference Benchmark Instanication -------

// ----- Clock 'clk' Initialization -------
	initial begin
		clk[0] <= 1'b0;
		while(1) begin
			#0.8625563979
			clk[0] <= !clk[0];
		end
	end

// ----- Begin reset signal generation -----
// ----- End reset signal generation -----

// ----- Input Initialization -------
	initial begin
		a <= 1'b0;
		b <= 1'b0;

		c_flag[0] <= 1'b0;
	end

// ----- Input Stimulus -------
	always@(negedge clk[0]) begin
		a <= $random;
		b <= $random;
	end

// ----- Begin checking output vectors -------
// ----- Skip the first falling edge of clock, it is for initialization -------
	reg [0:0] sim_start;

	always@(negedge clk[0]) begin
		if (1'b1 == sim_start[0]) begin
			sim_start[0] <= ~sim_start[0];
		end else 
begin
			if(!(c_gfpga === c_bench) && !(c_bench === 1'bx)) begin
				c_flag <= 1'b1;
			end else begin
				c_flag<= 1'b0;
			end
		end
	end

	always@(posedge c_flag) begin
		if(c_flag) begin
			nb_error = nb_error + 1;
			$display("Mismatch on c_gfpga at time = %t", $realtime);
		end
	end


// ----- Begin output waveform to VCD file-------
	initial begin
		$dumpfile("and2_formal.vcd");
		$dumpvars(1, and2_top_formal_verification_random_tb);
	end
// ----- END output waveform to VCD file -------

initial begin
	sim_start[0] <= 1'b1;
	$timeformat(-9, 2, "ns", 20);
	$display("Simulation start");
// ----- Can be changed by the user for his/her need -------
	#12.07578945
	if(nb_error == 0) begin
		$display("Simulation Succeed");
	end else begin
		$display("Simulation Failed with %d error(s)", nb_error);
	end
	$finish;
end

endmodule
module mux_tree_tapbuf_size10_mem(prog_clk,
                                  ccff_head,
                                  ccff_tail,
                                  mem_out,
                                  mem_outb);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:3] mem_out;
//----- OUTPUT PORTS -----
output [0:3] mem_outb;

//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----


//----- BEGIN Registered ports -----
//----- END Registered ports -----



// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
	assign ccff_tail[0] = mem_out[3];
// ----- END Local output short connections -----

	DFF DFF_0_ (
		.CK(prog_clk),
		.D(ccff_head),
		.Q(mem_out[0]),
		.QN(mem_outb[0]));

	DFF DFF_1_ (
		.CK(prog_clk),
		.D(mem_out[0]),
		.Q(mem_out[1]),
		.QN(mem_outb[1]));

	DFF DFF_2_ (
		.CK(prog_clk),
		.D(mem_out[1]),
		.Q(mem_out[2]),
		.QN(mem_outb[2]));

	DFF DFF_3_ (
		.CK(prog_clk),
		.D(mem_out[2]),
		.Q(mem_out[3]),
		.QN(mem_outb[3]));

endmodule
module mux_tree_tapbuf_size8_mem(prog_clk,
                                 ccff_head,
                                 ccff_tail,
                                 mem_out,
                                 mem_outb);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:3] mem_out;
//----- OUTPUT PORTS -----
output [0:3] mem_outb;

//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----


//----- BEGIN Registered ports -----
//----- END Registered ports -----



// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
	assign ccff_tail[0] = mem_out[3];
// ----- END Local output short connections -----

	DFF DFF_0_ (
		.CK(prog_clk),
		.D(ccff_head),
		.Q(mem_out[0]),
		.QN(mem_outb[0]));

	DFF DFF_1_ (
		.CK(prog_clk),
		.D(mem_out[0]),
		.Q(mem_out[1]),
		.QN(mem_outb[1]));

	DFF DFF_2_ (
		.CK(prog_clk),
		.D(mem_out[1]),
		.Q(mem_out[2]),
		.QN(mem_outb[2]));

	DFF DFF_3_ (
		.CK(prog_clk),
		.D(mem_out[2]),
		.Q(mem_out[3]),
		.QN(mem_outb[3]));

endmodule
module mux_tree_tapbuf_size9_mem(prog_clk,
                                 ccff_head,
                                 ccff_tail,
                                 mem_out,
                                 mem_outb);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:3] mem_out;
//----- OUTPUT PORTS -----
output [0:3] mem_outb;

//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----


//----- BEGIN Registered ports -----
//----- END Registered ports -----



// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
	assign ccff_tail[0] = mem_out[3];
// ----- END Local output short connections -----

	DFF DFF_0_ (
		.CK(prog_clk),
		.D(ccff_head),
		.Q(mem_out[0]),
		.QN(mem_outb[0]));

	DFF DFF_1_ (
		.CK(prog_clk),
		.D(mem_out[0]),
		.Q(mem_out[1]),
		.QN(mem_outb[1]));

	DFF DFF_2_ (
		.CK(prog_clk),
		.D(mem_out[1]),
		.Q(mem_out[2]),
		.QN(mem_outb[2]));

	DFF DFF_3_ (
		.CK(prog_clk),
		.D(mem_out[2]),
		.Q(mem_out[3]),
		.QN(mem_outb[3]));

endmodule
module mux_tree_tapbuf_size11_mem(prog_clk,
                                  ccff_head,
                                  ccff_tail,
                                  mem_out,
                                  mem_outb);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:3] mem_out;
//----- OUTPUT PORTS -----
output [0:3] mem_outb;

//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----


//----- BEGIN Registered ports -----
//----- END Registered ports -----



// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
	assign ccff_tail[0] = mem_out[3];
// ----- END Local output short connections -----

	DFF DFF_0_ (
		.CK(prog_clk),
		.D(ccff_head),
		.Q(mem_out[0]),
		.QN(mem_outb[0]));

	DFF DFF_1_ (
		.CK(prog_clk),
		.D(mem_out[0]),
		.Q(mem_out[1]),
		.QN(mem_outb[1]));

	DFF DFF_2_ (
		.CK(prog_clk),
		.D(mem_out[1]),
		.Q(mem_out[2]),
		.QN(mem_outb[2]));

	DFF DFF_3_ (
		.CK(prog_clk),
		.D(mem_out[2]),
		.Q(mem_out[3]),
		.QN(mem_outb[3]));

endmodule
module mux_tree_tapbuf_size5_mem(prog_clk,
                                 ccff_head,
                                 ccff_tail,
                                 mem_out,
                                 mem_outb);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:2] mem_out;
//----- OUTPUT PORTS -----
output [0:2] mem_outb;

//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----


//----- BEGIN Registered ports -----
//----- END Registered ports -----



// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
	assign ccff_tail[0] = mem_out[2];
// ----- END Local output short connections -----

	DFF DFF_0_ (
		.CK(prog_clk),
		.D(ccff_head),
		.Q(mem_out[0]),
		.QN(mem_outb[0]));

	DFF DFF_1_ (
		.CK(prog_clk),
		.D(mem_out[0]),
		.Q(mem_out[1]),
		.QN(mem_outb[1]));

	DFF DFF_2_ (
		.CK(prog_clk),
		.D(mem_out[1]),
		.Q(mem_out[2]),
		.QN(mem_outb[2]));

endmodule
module mult8(a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7,
			b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7,
			out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7,
			out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15);
input a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7;
input b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7;
output out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7;
output out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15;

 assign a = {a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7};
 assign b = {b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7};
 assign out = {out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7, out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15};

 assign out = a*b;

endmodule
module sync_cdc_bit #
(
    parameter integer C_SYNC_STAGES = 3
)
(
    input   wire    clk,
    input   wire    d,
    output  wire    q
);

    xpm_cdc_single #
    (
        .DEST_SYNC_FF   ( C_SYNC_STAGES ),  // DECIMAL; range: 2-10
        .INIT_SYNC_FF   ( 0             ),  // DECIMAL; 0 = disable simulation init values, 1=enable simulation init values
        .SIM_ASSERT_CHK ( 0             ),  // DECIMAL; 0 = disable simulation messages, 1=enable simulation messages
        .SRC_INPUT_REG  ( 0             )   // DECIMAL; 0 = do not register input, 1 = register input
    )
    xpm_cdc_single_inst
    (
        .src_clk        ( 1'b0 ),   // 1-bit input: optional; required when SRC_INPUT_REG = 1
        .dest_clk       ( clk  ),   // 1-bit input: Clock signal for the destination clock domain.
        .src_in         ( d    ),   // 1-bit input: Input signal to be synchronized to dest_clk domain.
        .dest_out       ( q    )    // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
    );
    
endmodule
module hb_clk_obuf #
(
    parameter integer DRIVE_STRENGTH = 8,
    parameter         SLEW_RATE      = "SLOW"
)
(
    input   wire    cen,
    input   wire    clk,
    output  wire    hb_ck_p,
    output  wire    hb_ck_n
);

    wire    oddr_clk_p;
    wire    oddr_clk_n;

/*----------------------------------------------------------------------------------------------------------------------------*/
    
    ODDR #
    (
        .DDR_CLK_EDGE ( "SAME_EDGE" ),  // "OPPOSITE_EDGE" or "SAME_EDGE"
        .INIT         ( 1'b0        ),  // Initial value of Q: 1'b0 or 1'b1
        .SRTYPE       ( "ASYNC"     )   // Set/Reset type: "SYNC" or "ASYNC"
    )
    ODDR_ck_p
    (
        .Q  ( oddr_clk_p ),     // 1-bit DDR output
        .C  ( clk        ),     // 1-bit clock input
        .CE ( 1'b1       ),     // 1-bit clock enable input
        .D1 ( cen        ),     // 1-bit data input (positive edge)
        .D2 ( 1'b0       ),     // 1-bit data input (negative edge)
        .R  ( 1'b0       ),     // 1-bit reset
        .S  ( 1'b0       )      // 1-bit set
    );
    
    
    OBUF #
    (
        .DRIVE  ( DRIVE_STRENGTH ),     // Specify the output drive strength
        .SLEW   ( SLEW_RATE      )      // Specify the output slew rate
    )
    OBUF_ck_p
    (
        .I  ( oddr_clk_p ),     // Buffer input
        .O  ( hb_ck_p    )      // Buffer output (connect directly to top-level port)
    );
    
/*----------------------------------------------------------------------------------------------------------------------------*/
    
    ODDR #
    (
        .DDR_CLK_EDGE ( "SAME_EDGE" ),  // "OPPOSITE_EDGE" or "SAME_EDGE"
        .INIT         ( 1'b0        ),  // Initial value of Q: 1'b0 or 1'b1
        .SRTYPE       ( "ASYNC"     )   // Set/Reset type: "SYNC" or "ASYNC"
    )
    ODDR_ck_n
    (
        .Q  ( oddr_clk_n ),     // 1-bit DDR output
        .C  ( clk        ),     // 1-bit clock input
        .CE ( 1'b1       ),     // 1-bit clock enable input
        .D1 ( ~cen       ),     // 1-bit data input (positive edge)
        .D2 ( 1'b1       ),     // 1-bit data input (negative edge)
        .R  ( 1'b0       ),     // 1-bit reset
        .S  ( 1'b0       )      // 1-bit set
    );
    
    
    OBUF #
    (
        .DRIVE  ( DRIVE_STRENGTH ),     // Specify the output drive strength
        .SLEW   ( SLEW_RATE      )      // Specify the output slew rate
    )
    OBUF_ck_n
    (
        .I  ( oddr_clk_n ),     // Buffer input
        .O  ( hb_ck_n    )      // Buffer output (connect directly to top-level port)
    );
    
    

endmodule
module gpio_splitter
(
    input   wire    [9:0]   gpio,
    
    output  wire            pwr_off_req,
    output  wire    [4:0]   lcd_led_level,
    output  wire    [1:0]   act_led,
    output  wire            shtr_drive_ena,
    output  wire            focus_drive_ena
);
    
    assign  pwr_off_req      = gpio[0];
    
    assign  lcd_led_level[0] = gpio[1];
    assign  lcd_led_level[1] = gpio[2];
    assign  lcd_led_level[2] = gpio[3];
    assign  lcd_led_level[3] = gpio[4];
    assign  lcd_led_level[4] = gpio[5];
    
    assign  act_led[0]       = gpio[6];
    assign  act_led[1]       = gpio[7];
    
    assign  shtr_drive_ena   = gpio[8];
    assign  focus_drive_ena  = gpio[9];
    
endmodule
module gpio_concat
(
    output  wire    [19:0]  gpio,
    
    input   wire            btn_0_down,
    input   wire            btn_1_down,
    input   wire            btn_2_down,
    input   wire            btn_3_down,
    
    input   wire            btn_0_up,
    input   wire            btn_1_up,
    input   wire            btn_2_up,
    input   wire            btn_3_up,
    
    input   wire            btn_0_shrt,
    input   wire            btn_1_shrt,
    input   wire            btn_2_shrt,
    input   wire            btn_3_shrt,
    
    input   wire            btn_0_long,
    input   wire            btn_1_long,
    input   wire            btn_2_long,
    input   wire            btn_3_long,
    
    input   wire            btn_0_imm,
    input   wire            btn_1_imm,
    input   wire            btn_2_imm,
    input   wire            btn_3_imm
);
    
    assign  gpio[0]  = btn_0_down;
    assign  gpio[1]  = btn_1_down;
    assign  gpio[2]  = btn_2_down;
    assign  gpio[3]  = btn_3_down;
    
    assign  gpio[4]  = btn_0_up;
    assign  gpio[5]  = btn_1_up;
    assign  gpio[6]  = btn_2_up;
    assign  gpio[7]  = btn_3_up;
    
    assign  gpio[8]  = btn_0_shrt;
    assign  gpio[9]  = btn_1_shrt;
    assign  gpio[10] = btn_2_shrt;
    assign  gpio[11] = btn_3_shrt;
    
    assign  gpio[12] = btn_0_long;
    assign  gpio[13] = btn_1_long;
    assign  gpio[14] = btn_2_long;
    assign  gpio[15] = btn_3_long;
    
    assign  gpio[16] = btn_0_imm;
    assign  gpio[17] = btn_1_imm;
    assign  gpio[18] = btn_2_imm;
    assign  gpio[19] = btn_3_imm;
    
endmodule
module m_axis_stub
(
    (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_RSTIF, POLARITY ACTIVE_LOW" *)
    (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 M_RSTIF RST" *)
    input   wire    m_axis_aresetn,

    (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_CLKIF, ASSOCIATED_BUSIF M_AXIS_STUB, ASSOCIATED_RESET m_axis_aresetn" *)
    (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_CLKIF CLK" *)
    input   wire    m_axis_aclk,

    (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_STUB, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
    (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_STUB TDATA"  *) output  wire    [31:0]  m_axis_stub_tdata,
    (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_STUB TVALID" *) output  wire            m_axis_stub_tvalid,
    (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_STUB TREADY" *) input   wire            m_axis_stub_tready,
    (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_STUB TUSER"  *) output  wire            m_axis_stub_tlast
);
    
    assign m_axis_stub_tdata  = {32{1'b0}};
    assign m_axis_stub_tvalid = 1'b0;
    assign m_axis_stub_tlast  = 1'b0;

endmodule
module edge_to_pulse #
(
    parameter CLK_HZ = 27000000,
    parameter PULSE_DURATION_MS = 1,
    parameter EDGE_TYPE = "RISING"      // RISING / FALLING / BOTH
)
(
    input   wire    clk,
    input   wire    rstn,
    input   wire    edge_in,
    output  reg     pulse_out = 1'b0
);
    
    localparam DELAY_MS = CLK_HZ / 1000;
    
/*-------------------------------------------------------------------------------------------------------------------------------------*/
    
    reg             in_1 = 1'b0;
    reg             state = 1'b0;
    reg     [31:0]  delay_tc   = 32'd0;
    
    
    always @(posedge clk) begin
        if (~rstn) begin
            state <= 1'b0;
            in_1  <= 1'b0;
            pulse_out <= 1'b0;
        end else begin
            in_1 <= edge_in;
        
            case (state)
                1'b0: begin
                    delay_tc <= 32'd0;
                    if (EDGE_TYPE == "ANY") begin
                        state <= (edge_in ^ in_1)? 1'b1 : 1'b0;
                    end else begin
                        if (EDGE_TYPE == "RISING") begin
                            state <= (edge_in & ~in_1)? 1'b1 : 1'b0;
                        end else begin
                            state <= (~edge_in & in_1)? 1'b1 : 1'b0;
                        end
                    end
                end
                
                1'b1: begin
                    if (delay_tc < PULSE_DURATION_MS * DELAY_MS) begin
                        delay_tc <= delay_tc + 1'b1;
                        pulse_out <= 1'b1;
                    end else begin
                        state <= 1'b0;
                        pulse_out <= 1'b0;
                    end
                end
            endcase
        end
    end


endmodule
module s_axis_stub #
(
    parameter   TREADY = 1'b0
)
(
    (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_RSTIF, POLARITY ACTIVE_LOW" *)
    (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_RSTIF RST" *)
    input   wire    s_axis_aresetn,

    (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_CLKIF, ASSOCIATED_BUSIF S_AXIS_STUB, ASSOCIATED_RESET s_axis_aresetn" *)
    (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_CLKIF CLK" *)
    input   wire    s_axis_aclk,

    (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_STUB, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 4, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
    (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_STUB TDATA"  *) input   wire    [31:0]  s_axis_stub_tdata,
    (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_STUB TVALID" *) input   wire            s_axis_stub_tvalid,
    (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_STUB TREADY" *) output  wire            s_axis_stub_tready,
    (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_STUB TLAST"  *) input   wire            s_axis_stub_tlast,
    (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_STUB TUSER"  *) input   wire    [3:0]   s_axis_stub_tuser
);
    
    assign s_axis_stub_tready = TREADY;

endmodule
module pipeline #
(
    parameter   PIPE_WIDTH  = 32,
    parameter   PIPE_STAGES = 8
)
(
    input   wire                        clk,
    input   wire                        cen,
    input   wire                        srst,
    input   wire    [PIPE_WIDTH - 1:0]  pipe_in,
    output  wire    [PIPE_WIDTH - 1:0]  pipe_out
);
    
/*-------------------------------------------------------------------------------------------------------------------------------------*/
    
    genvar i;
    
    generate
        for (i = 0; i < PIPE_WIDTH; i = i + 1) begin: loop
        
            reg [PIPE_STAGES - 1:0] pipe_gen;
            
            always @(posedge clk) begin
                if (srst) begin
                    pipe_gen <= {PIPE_STAGES{1'b0}};
                end else begin
                    if (cen) begin
                        pipe_gen <= (PIPE_STAGES > 1)? {pipe_gen[PIPE_STAGES - 2:0], pipe_in[i]} : pipe_in[i];
                    end
                end
            end
            
            assign pipe_out[i] = pipe_gen[PIPE_STAGES - 1];
        end
    endgenerate
    
endmodule
module axis_pipeliner #
(
    parameter integer PIPE_DATA_IN_WIDTH  = 32,
    parameter integer PIPE_DATA_OUT_WIDTH = 32,
    parameter integer PIPE_QUAL_WIDTH = 4,
    parameter integer PIPE_STAGES = 8
)
(
    input   wire                                axis_aclk,
    input   wire                                axis_aresetn,
    
    input   wire    [PIPE_DATA_IN_WIDTH - 1:0]  s_axis_tdata,
    input   wire    [PIPE_QUAL_WIDTH - 1:0]     s_axis_tuser,
    input   wire                                s_axis_tvalid,
    output  wire                                s_axis_tready,
    input   wire                                s_axis_tlast,
    
    output  wire    [PIPE_DATA_OUT_WIDTH - 1:0] m_axis_tdata,
    output  wire    [PIPE_QUAL_WIDTH - 1:0]     m_axis_tuser,
    output  wire                                m_axis_tvalid,
    input   wire                                m_axis_tready,
    output  wire                                m_axis_tlast,
    
    output  wire                                pipe_cen,
    output  wire    [PIPE_DATA_IN_WIDTH - 1:0]  pipe_in_data,
    input   wire    [PIPE_DATA_OUT_WIDTH - 1:0] pipe_out_data
);
    
/*-------------------------------------------------------------------------------------------------------------------------------------*/
    
    reg     [PIPE_STAGES - 1:0]  tvalid_pipe = {PIPE_STAGES{1'b0}};
    reg     [PIPE_STAGES - 1:0]  tlast_pipe  = {PIPE_STAGES{1'b0}};
    
    
    always @(posedge axis_aclk) begin
        if (~axis_aresetn) begin
            tvalid_pipe <= {PIPE_STAGES{1'b0}};
            tlast_pipe  <= {PIPE_STAGES{1'b0}};
        end else begin
            if (pipe_cen) begin
                tvalid_pipe <= (PIPE_STAGES > 1)? {tvalid_pipe[PIPE_STAGES - 2:0], s_axis_tvalid} : s_axis_tvalid;
                tlast_pipe  <= (PIPE_STAGES > 1)? {tlast_pipe[PIPE_STAGES - 2:0],  s_axis_tlast}  : s_axis_tlast;
            end
        end
    end
    
    
    assign s_axis_tready = s_axis_tvalid & (~tvalid_pipe[PIPE_STAGES - 1] | m_axis_tready);
    assign pipe_cen      = s_axis_tready |  ~tvalid_pipe[PIPE_STAGES - 1] | m_axis_tready;
    assign pipe_in_data  = s_axis_tdata;
    
    assign m_axis_tdata  = pipe_out_data;
    assign m_axis_tvalid = tvalid_pipe[PIPE_STAGES - 1];
    assign m_axis_tlast  = tlast_pipe[PIPE_STAGES - 1];
    
/*-------------------------------------------------------------------------------------------------------------------------------------*/

    genvar i;
    generate
        for (i = 0; i < PIPE_QUAL_WIDTH; i = i + 1) begin: loop
            reg [PIPE_STAGES - 1:0] pipe_gen = {PIPE_STAGES{1'b0}};
            
            always @(posedge axis_aclk) begin
                if (pipe_cen) begin
                    pipe_gen <= (PIPE_STAGES > 1)? {pipe_gen[PIPE_STAGES - 2:0], s_axis_tuser[i]} : s_axis_tuser[i];
                end
            end
            
            assign m_axis_tuser[i] = pipe_gen[PIPE_STAGES - 1];
        end
    endgenerate
    
endmodule
module debouncer #
(
    parameter CLK_HZ = 27000000,
    parameter DEBOUNCE_MS = 20,
    parameter IDLE_STATE = 1'b1
)
(
    input   wire    clk,
    input   wire    rstn,
    input   wire    noisy_in,
    output  reg     filtered_out = IDLE_STATE
);
    
    localparam DELAY_MS = CLK_HZ / 1000;
    
    wire            out_sync;
    reg             out_sync_1 = IDLE_STATE;
    reg     [31:0]  delay_tc   = 32'd0;

/*-------------------------------------------------------------------------------------------------------------------------------------*/
    
    xpm_cdc_single #
    (
        .DEST_SYNC_FF   (3),    // DECIMAL; range: 2-10
        .INIT_SYNC_FF   (0),    // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
        .SIM_ASSERT_CHK (0),    // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
        .SRC_INPUT_REG  (0)     // DECIMAL; 0=do not register input, 1=register input
    )
    xpm_cdc_single_inst
    (
        .src_clk    ( 1'b0      ),  // 1-bit input: optional; required when SRC_INPUT_REG = 1
        .dest_clk   ( clk       ),  // 1-bit input: Clock signal for the destination clock domain.
        
        .src_in     ( noisy_in  ),  // 1-bit input: Input signal to be synchronized to dest_clk domain.
        .dest_out   ( out_sync  )   // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
    );
    
/*-------------------------------------------------------------------------------------------------------------------------------------*/
    
    always @(posedge clk) begin
        if (~rstn) begin
            filtered_out <= IDLE_STATE;
            out_sync_1 <= IDLE_STATE;
        end else begin
            out_sync_1 <= out_sync;
            
            if (out_sync ^ out_sync_1) begin
                delay_tc <= 32'd0;
            end else begin
                if (delay_tc == DEBOUNCE_MS * DELAY_MS) begin
                    filtered_out <= out_sync_1;
                end else begin
                    delay_tc <= delay_tc + 1'b1;
                end
            end
        end
    end


endmodule
module i2c_interconnect
(
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S0_IIC SCL_I" *)    output  wire    s0_scl_i,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S0_IIC SCL_O" *)    input   wire    s0_scl_o,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S0_IIC SCL_T" *)    input   wire    s0_scl_t,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S0_IIC SDA_I" *)    output  wire    s0_sda_i,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S0_IIC SDA_O" *)    input   wire    s0_sda_o,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S0_IIC SDA_T" *)    input   wire    s0_sda_t,
    
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S1_IIC SCL_I" *)    output  wire    s1_scl_i,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S1_IIC SCL_O" *)    input   wire    s1_scl_o,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S1_IIC SCL_T" *)    input   wire    s1_scl_t,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S1_IIC SDA_I" *)    output  wire    s1_sda_i,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S1_IIC SDA_O" *)    input   wire    s1_sda_o,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S1_IIC SDA_T" *)    input   wire    s1_sda_t,

    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 M_IIC SCL_I" *)     input   wire    m_scl_i,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 M_IIC SCL_O" *)     output  wire    m_scl_o,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 M_IIC SCL_T" *)     output  wire    m_scl_t,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 M_IIC SDA_I" *)     input   wire    m_sda_i,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 M_IIC SDA_O" *)     output  wire    m_sda_o,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 M_IIC SDA_T" *)     output  wire    m_sda_t
);

/*-------------------------------------------------------------------------------------------------------------------------------------*/ 

    assign s0_scl_i = m_scl_i;
    assign s1_scl_i = m_scl_i;
    
    assign s0_sda_i = m_sda_i;
    assign s1_sda_i = m_sda_i;
    
    assign m_scl_o = s0_scl_o & s1_scl_o;
    assign m_scl_t = s0_scl_t & s1_scl_t;
    
    assign m_sda_o = s0_sda_o & s1_sda_o;
    assign m_sda_t = s0_sda_t & s1_sda_t;
    
endmodule
module yuv444_to_yuv422
(
    input   wire            clk,
    input   wire            cen,
    
    input   wire    [7:0]   y0_in,
    input   wire    [7:0]   u0_in,
    input   wire    [7:0]   v0_in,
    
    input   wire    [7:0]   y1_in,
    input   wire    [7:0]   u1_in,
    input   wire    [7:0]   v1_in,
    
    output  reg     [7:0]   y0_out = {8{1'b0}},
    output  wire    [7:0]   u_out,
    output  reg     [7:0]   y1_out = {8{1'b0}},
    output  wire    [7:0]   v_out
);
    
/*-------------------------------------------------------------------------------------------------------------------------------------*/
    
    reg     [8:0]  u_sum = {9{1'b0}};
    reg     [8:0]  v_sum = {9{1'b0}};
    
    
    always @(posedge clk) begin
        if (cen) begin
            y0_out <= y0_in;
            y1_out <= y1_in;
            u_sum  <= u0_in + u1_in + 1'b1;
            v_sum  <= v0_in + v1_in + 1'b1;
        end
    end
    
    
    assign u_out = u_sum[8:1];
    assign v_out = v_sum[8:1];

endmodule
module axis_img_border_remover #
(
    parameter   BYPASS_BIT_MASK = 16'h4000
)
(
    input   wire            axis_aclk,
    input   wire            axis_aresetn,
    
    input   wire    [15:0]  s_axis_tdata,
    input   wire            s_axis_tvalid,
    output  reg             s_axis_tready   = 1'b0,
    input   wire            s_axis_tlast,
    input   wire            s_axis_tuser,
    
    output  reg     [15:0]  m_axis_tdata    = {16{1'b0}},
    output  reg             m_axis_tvalid   = 1'b0,
    input   wire            m_axis_tready,
    output  reg             m_axis_tlast    = 1'b0,
    output  reg             m_axis_tuser    = 1'b0
);
    
/*-------------------------------------------------------------------------------------------------------------------------------------*/
    
    localparam  [1:0]   ST_RST  = 2'd0,
                        ST_GET  = 2'd1,
                        ST_SEND = 2'd2;
                        
    reg         [1:0]   state = ST_RST;
    
    
    always @(posedge axis_aclk) begin
        if (~axis_aresetn) begin
            s_axis_tready <= 1'b0;
            m_axis_tvalid <= 1'b0;
            state <= ST_RST;
        end else begin
            case (state)
                ST_RST: begin
                    s_axis_tready <= 1'b1;
                    m_axis_tvalid <= 1'b0;
                    state <= ST_GET;
                end
            
                ST_GET: begin
                    if (s_axis_tvalid && (s_axis_tdata & BYPASS_BIT_MASK)) begin
                        s_axis_tready <= 1'b0;
                        m_axis_tvalid <= 1'b1;
                        m_axis_tdata  <= s_axis_tdata & (~BYPASS_BIT_MASK);
                        m_axis_tlast  <= s_axis_tlast;
                        m_axis_tuser  <= s_axis_tuser;
                        state <= ST_SEND;
                    end
                end
                
                ST_SEND: begin
                    if (m_axis_tready) begin
                        m_axis_tvalid <= 1'b0;
                        s_axis_tready <= 1'b1;
                        state <= ST_GET;
                    end
                end
                
                default: begin
                    state <= ST_RST;
                end
                
            endcase
        end
    end
    
endmodule
module bpr_3x1_interpol
(
    input   wire            clk,
    input   wire            cen,
    input   wire            srst,
    
    input   wire    [14:0]  pix_in_0,
    input   wire    [14:0]  pix_in_1,
    input   wire    [14:0]  pix_in_2,
    
    output  wire    [14:0]  pix_out_avg
);
    
/*-------------------------------------------------------------------------------------------------------------------------------------*/

    wire    [14:0]  pix_01_avg;
    wire    [14:0]  pix_12_avg;
    
    
    bpr_averager bpr_averager_01
    (
        .clk            (clk), 
        .cen            (cen), 
        .srst           (srst), 
        .pix_in_0       (pix_in_0), 
        .pix_in_1       (pix_in_1), 
        .pix_out_avg    (pix_01_avg)
    );
    
    
    bpr_averager bpr_averager_12
    (
        .clk            (clk), 
        .cen            (cen), 
        .srst           (srst), 
        .pix_in_0       (pix_in_1), 
        .pix_in_1       (pix_in_2), 
        .pix_out_avg    (pix_12_avg)
    );
    
    
    bpr_averager bpr_averager_result
    (
        .clk            (clk), 
        .cen            (cen), 
        .srst           (srst), 
        .pix_in_0       (pix_01_avg), 
        .pix_in_1       (pix_12_avg), 
        .pix_out_avg    (pix_out_avg)
    );
    
endmodule
module bpr_averager
(
    input   wire            clk,
    input   wire            cen,
    input   wire            srst,
    
    input   wire    [14:0]  pix_in_0,
    input   wire    [14:0]  pix_in_1,
    
    output  wire    [14:0]  pix_out_avg
);

    localparam  BOTH_BAD  = 2'b00,
                PIX_1_BAD = 2'b01,
                PIX_0_BAD = 2'b10,
                BOTH_GOOD = 2'b11;
    
/*-------------------------------------------------------------------------------------------------------------------------------------*/

    reg     [14:0]  pix_out = {15{1'b0}};
    wire            pix_0_good_flag = pix_in_0[14];
    wire            pix_1_good_flag = pix_in_1[14];
    wire    [14:0]  pix_sum = pix_in_0[13:0] + pix_in_1[13:0] + 1'b1;
    
    always @(posedge clk) begin
        if (cen) begin
            if (srst) begin
                pix_out <= {15{1'b0}};
            end else begin
                case ({pix_1_good_flag, pix_0_good_flag})
                    BOTH_GOOD: pix_out <= {1'b1, pix_sum[14:1]};
                    PIX_0_BAD: pix_out <= pix_in_1;
                    PIX_1_BAD: pix_out <= pix_in_0;
                    BOTH_BAD:  pix_out <= {1'b0, {14{1'b0}}};
                endcase
            end
        end
    end
    
    assign pix_out_avg = pix_out;
    
endmodule
module edge_to_pulse #
(
    parameter CLK_HZ = 27000000,
    parameter PULSE_DURATION_MS = 1,
    parameter EDGE_TYPE = "RISING"      // RISING / FALLING / BOTH
)
(
    input   wire    clk,
    input   wire    rstn,
    input   wire    edge_in,
    output  reg     pulse_out = 1'b0
);
    
    localparam DELAY_MS = CLK_HZ / 1000;
    
/*-------------------------------------------------------------------------------------------------------------------------------------*/
    
    reg             in_1 = 1'b0;
    reg             state = 1'b0;
    reg     [31:0]  delay_tc   = 32'd0;
    
    
    always @(posedge clk) begin
        if (~rstn) begin
            state <= 1'b0;
            in_1  <= 1'b0;
            pulse_out <= 1'b0;
        end else begin
            in_1 <= edge_in;
        
            case (state)
                1'b0: begin
                    delay_tc <= 32'd0;
                    if (EDGE_TYPE == "BOTH") begin
                        state <= (edge_in ^ in_1)? 1'b1 : 1'b0;
                    end else begin
                        if (EDGE_TYPE == "RISING") begin
                            state <= (edge_in & ~in_1)? 1'b1 : 1'b0;
                        end else begin
                            state <= (~edge_in & in_1)? 1'b1 : 1'b0;
                        end
                    end
                end
                
                1'b1: begin
                    if (delay_tc < PULSE_DURATION_MS * DELAY_MS) begin
                        delay_tc <= delay_tc + 1'b1;
                        pulse_out <= 1'b1;
                    end else begin
                        state <= 1'b0;
                        pulse_out <= 1'b0;
                    end
                end
            endcase
        end
    end


endmodule
module s_axis_stub
(
    (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_RSTIF, POLARITY ACTIVE_LOW" *)
    (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_RSTIF RST" *)
    input   wire    s_axis_aresetn,

    (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_CLKIF, ASSOCIATED_BUSIF S_AXIS_STUB, ASSOCIATED_RESET s_axis_aresetn" *)
    (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_CLKIF CLK" *)
    input   wire    s_axis_aclk,

    (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_STUB, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 4, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
    (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_STUB TDATA"  *) input   wire    [31:0]  s_axis_stub_tdata,
    (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_STUB TVALID" *) input   wire            s_axis_stub_tvalid,
    (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_STUB TREADY" *) output  wire            s_axis_stub_tready,
    (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_STUB TLAST"  *) input   wire            s_axis_stub_tlast,
    (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_STUB TUSER"  *) input   wire    [3:0]   s_axis_stub_tuser
);
    
    assign s_axis_stub_tready = 1'b0;

endmodule