dakies/OSS_Verilog huggingface dataset:
module top (
	input clk,
	input rst,
	output [`LEDS_NR-1:0] led
);

wire rst_s;
wire tick_hz;

localparam HZ_PRESC = 12_000_000,
		HZ_SIZE = $clog2(HZ_PRESC);

reg [HZ_SIZE-1:0]  hertz_cpt;
wire [HZ_SIZE-1:0]  hertz_cpt_d = hertz_cpt - 1'b1;

always @(posedge clk) begin
	/* 1Hz clk */
	if (tick_hz) begin
		hertz_cpt <= HZ_PRESC;
	end else begin
		hertz_cpt <= hertz_cpt_d;
	end
end


reg [`LEDS_NR-1:0] ctr_q;
wire [`LEDS_NR-1:0] ctr_d;

// Sequential code (flip-flop)
always @(posedge clk or posedge rst_s) begin
	if (rst_s) begin
		ctr_q <= 'd1;
	end else if (tick_hz) begin
		ctr_q <= ctr_d;
	end
end

// Combinational code (boolean logic)
assign ctr_d = {ctr_q[0], ctr_q[`LEDS_NR-1:1]};
assign led = ctr_q;
assign tick_hz = (hertz_cpt == 0);
assign rst_s = !rst;

endmodule
module top (
    input clk,
    output tlvds_p,
    output tlvds_n,
	input key
);

reg [24:0] ctr_q;
wire [24:0] ctr_d;
wire i_tick;

// Sequential code (flip-flop)
always @(posedge clk)
    ctr_q <= ctr_d;

// Combinational code (boolean logic)
assign ctr_d = ctr_q + 1'b1;
assign i_tick = |ctr_q[24:23];

TLVDS_TBUF diff_buf(
		.OEN(~key),
        .O(tlvds_p),
        .OB(tlvds_n),
        .I(i_tick)
    );

endmodule
module top (
    input clk,
	input key,
    output tlvds_p,
    output tlvds_n
);

reg [24:0] ctr_q;
wire [24:0] ctr_d;
wire i_tick;
wire w_ddr;

// Sequential code (flip-flop)
always @(posedge clk)
    ctr_q <= ctr_d;

// Combinational code (boolean logic)
assign ctr_d = ctr_q + 1'b1;
assign i_tick = |ctr_q[24:23];

ODDR oddr_0(
	.D0(1'b0),
	.D1(1'b1),
	.CLK(i_tick),
	.Q0(w_ddr),
	.Q1(),
	.TX()
);

TLVDS_TBUF diff_buf(
		.OEN(~key),
        .O(tlvds_p),
        .OB(tlvds_n),
        .I(w_ddr)
    );

endmodule
module top();
  wire gen_000_;
  wire gen_001_;
  wire gen_002_;
  wire gen_003_;
  wire gen_004_;
  wire gen_005_;
  wire gen_006_;
  wire gen_007_;
  wire gen_008_;
  wire gen_009_;
  wire gen_010_;
  wire gen_011_;
  LUT4 mylut (
    .F(gen_000_),
    .I0(gen_001_),
    .I1(gen_002_),
    .I2(gen_003_),
    .I3(gen_004_ )
  );
  defparam mylut.INIT = 16'h0000;
  LUT4 mylut2 (
    .F(gen_005_),
    .I0(gen_000_),
    .I1(gen_007_),
    .I2(gen_008_),
    .I3(gen_009_ )
  );
  /*defparam mylut2.INIT = 16'haaaa;
  DFFE mydff (
    .CE(gen_010_),
    .CLK(gen_011_),
    .D(gen_000_),
    .Q(gen_006_)
  );*/
endmodule
module top(outp);
  output outp;
  wire gen_000_;
  OBUF myobuf (
    .I(gen_000_),
    .O(outp)
  );
endmodule
module top;

	wire clk;
	(* BEL="R29C29_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(1), .OUTPUT_USED(0)) clk_ibuf (.O(clk));

	wire [7:0] leds;
	(* BEL="R1C8_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) led7_obuf (.I(leds[7]));
	(* BEL="R1C8_IOBB", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) led6_obuf (.I(leds[6]));
	(* BEL="R1C10_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) led5_obuf (.I(leds[5]));
	(* BEL="R1C10_IOBB", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) led4_obuf (.I(leds[4]));
	(* BEL="R1C11_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) led3_obuf (.I(leds[3]));
	(* BEL="R1C11_IOBB", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) led2_obuf (.I(leds[2]));
	(* BEL="R1C12_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) led1_obuf (.I(leds[1]));
	(* BEL="R1C12_IOBB", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) led0_obuf (.I(leds[0]));

reg [25:0] ctr;
always @(posedge clk)
	ctr <= ctr + 1'b1;

assign leds = ctr[25:18];

endmodule
module top;

	wire clk;
	(* BEL="R5C20_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(1), .OUTPUT_USED(0)) clk_ibuf (.O(clk));

	wire [2:0] leds;
	(* BEL="R11C7_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) led2_obuf (.I(leds[2]));
	(* BEL="R11C10_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) led1_obuf (.I(leds[1]));
	(* BEL="R11C10_IOBB", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) led0_obuf (.I(leds[0]));

reg [25:0] ctr;
always @(posedge clk)
	ctr <= ctr + 1'b1;

assign leds = ctr[25:23];

endmodule
module top ( out, clk, reset );
    output out;
    input clk, reset;
    reg out;

    always @(posedge clk, posedge reset)
      if (reset)
          out <= 0;
      else
          out <= ~out;
endmodule
module attosoc (
	input clk,
	output reg [7:0] led
);

	reg [5:0] reset_cnt = 0;
	wire resetn = &reset_cnt;

	always @(posedge clk) begin
		reset_cnt <= reset_cnt + !resetn;
	end

	parameter integer MEM_WORDS = 256;
	parameter [31:0] STACKADDR = (4*MEM_WORDS);       // end of memory
	parameter [31:0] PROGADDR_RESET = 32'h 0000_0000; // ROM at 0x0
	parameter integer ROM_BYTES = 256;

	reg [7:0] rom [0:ROM_BYTES-1];
	wire [31:0] rom_rdata = {rom[mem_addr+3], rom[mem_addr+2], rom[mem_addr+1], rom[mem_addr+0]};
	initial $readmemh("attosoc/firmware.hex", rom);

	wire mem_valid;
	wire mem_instr;
	wire mem_ready;
	wire [31:0] mem_addr;
	wire [31:0] mem_wdata;
	wire [3:0] mem_wstrb;
	wire [31:0] mem_rdata;

    wire rom_ready = mem_valid && mem_addr[31:24] == 8'h00;

	wire iomem_valid;
	wire iomem_ready;
	wire [31:0] iomem_addr;
	wire [31:0] iomem_wdata;
	wire [3:0] iomem_wstrb;
	wire [31:0] iomem_rdata;

	assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
	assign iomem_ready = 1'b1;
	assign iomem_wstrb = mem_wstrb;
	assign iomem_addr = mem_addr;
	assign iomem_wdata = mem_wdata;

	wire [31:0] spimemio_cfgreg_do;


    always @(posedge clk)
        if (iomem_valid && iomem_wstrb[0])
            led <= iomem_wdata[7:0];

	assign mem_ready = (iomem_valid && iomem_ready) || rom_ready;

	assign mem_rdata = rom_rdata;

	picorv32 #(
		.STACKADDR(STACKADDR),
		.PROGADDR_RESET(PROGADDR_RESET),
		.PROGADDR_IRQ(32'h 0000_0000),
		.BARREL_SHIFTER(0),
		.COMPRESSED_ISA(0),
		.ENABLE_MUL(0),
		.ENABLE_DIV(0),
		.ENABLE_IRQ(0),
		.ENABLE_IRQ_QREGS(0)
	) cpu (
		.clk         (clk        ),
		.resetn      (resetn     ),
		.mem_valid   (mem_valid  ),
		.mem_instr   (mem_instr  ),
		.mem_ready   (mem_ready  ),
		.mem_addr    (mem_addr   ),
		.mem_wdata   (mem_wdata  ),
		.mem_wstrb   (mem_wstrb  ),
		.mem_rdata   (mem_rdata  )
	);



endmodule
module top;

	wire clk;
	(* BEL="R29C29_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(1), .OUTPUT_USED(0)) clk_ibuf (.O(clk));

	wire [7:0] leds;
	(* BEL="R1C8_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) led7_obuf (.I(leds[7]));
	(* BEL="R1C8_IOBB", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) led6_obuf (.I(leds[6]));
	(* BEL="R1C10_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) led5_obuf (.I(leds[5]));
	(* BEL="R1C10_IOBB", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) led4_obuf (.I(leds[4]));
	(* BEL="R1C11_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) led3_obuf (.I(leds[3]));
	(* BEL="R1C11_IOBB", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) led2_obuf (.I(leds[2]));
	(* BEL="R1C12_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) led1_obuf (.I(leds[1]));
	(* BEL="R1C12_IOBB", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) led0_obuf (.I(leds[0]));

attosoc soc(
	.clk(clk),
	.led(leds)
);

endmodule
module top;

  wire XTAL_IN;
	(* BEL="R5C20_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(1), .OUTPUT_USED(0)) clk_ibuf (.O(XTAL_IN));
  wire nRST;
	(* BEL="R11C3_IOBB", keep *)
	GENERIC_IOB #(.INPUT_USED(1), .OUTPUT_USED(0)) rst_ibuf (.O(nRST));


	wire LCD_CLK;
	(* BEL="R7C1_IOBB", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_clk_obuf (.I(LCD_CLK));
	wire LCD_HYNC;
	(* BEL="R7C1_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_hync_obuf (.I(LCD_HYNC));
	wire LCD_SYNC;
	(* BEL="R1C5_IOBB", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_sync_obuf (.I(LCD_SYNC));
	wire LCD_DEN;
	(* BEL="R6C1_IOBC", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_den_obuf (.I(LCD_DEN));

	wire	[4:0]	LCD_R;
	(* BEL="R7C20_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_r0_obuf (.I(LCD_R[0]));
	(* BEL="R6C20_IOBH", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_r1_obuf (.I(LCD_R[1]));
	(* BEL="R6C20_IOBG", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_r2_obuf (.I(LCD_R[2]));
	(* BEL="R6C20_IOBF", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_r3_obuf (.I(LCD_R[3]));
	(* BEL="R6C20_IOBD", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_r4_obuf (.I(LCD_R[4]));
	wire	[5:0]	LCD_G;
	(* BEL="R6C20_IOBC", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_g0_obuf (.I(LCD_G[0]));
	(* BEL="R6C20_IOBB", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_g1_obuf (.I(LCD_G[1]));
	(* BEL="R6C20_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_g2_obuf (.I(LCD_G[2]));
	(* BEL="R1C17_IOBB", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_g3_obuf (.I(LCD_G[3]));
	(* BEL="R1C17_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_g4_obuf (.I(LCD_G[4]));
	(* BEL="R1C14_IOBB", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_g5_obuf (.I(LCD_G[5]));
	wire	[4:0]	LCD_B;
	(* BEL="R1C14_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_b0_obuf (.I(LCD_B[0]));
	(* BEL="R1C10_IOBB", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_b1_obuf (.I(LCD_B[1]));
	(* BEL="R1C10_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_b2_obuf (.I(LCD_B[2]));
	(* BEL="R1C7_IOBB", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_b3_obuf (.I(LCD_B[3]));
	(* BEL="R1C7_IOBA", keep *)
	GENERIC_IOB #(.INPUT_USED(0), .OUTPUT_USED(1)) lcd_b4_obuf (.I(LCD_B[4]));

	wire		CLK_SYS;	
	wire		CLK_PIX;

assign CLK_SYS = XTAL_IN;
assign CLK_PIX = XTAL_IN;

	VGAMod	D1
	(
		.CLK		(	CLK_SYS     ),
		.nRST		(	nRST		),

		.PixelClk	(	CLK_PIX		),
		.LCD_DE		(	LCD_DEN	 	),
		.LCD_HSYNC	(	LCD_HYNC 	),
    	.LCD_VSYNC	(	LCD_SYNC 	),

		.LCD_B		(	LCD_B		),
		.LCD_G		(	LCD_G		),
		.LCD_R		(	LCD_R		)
	);

	assign		LCD_CLK		=	CLK_PIX;

endmodule
module \$lut (A, Y);
	parameter WIDTH = 0;
	parameter LUT = 0;
	input [WIDTH-1:0] A;
	output Y;

	LUT #(.K(`LUT_K), .INIT(LUT)) _TECHMAP_REPLACE_ (.I(A), .Q(Y));
endmodule
module cordic_stage_16(clk, rst_n, x_in, y_in, angle_in, angle_adj, x_out, y_out, angle_out);
    parameter SHIFT = 1;

    // inputs
    input clk;
    input rst_n;
    input signed [16-1:0] x_in;
    input signed [16-1:0] y_in;
    input signed [16-1:0] angle_in;
    input signed [16-1:0] angle_adj;

    // outputs
    output reg signed [16-1:0] x_out;
    output reg signed [16-1:0] y_out;
    output reg signed [16-1:0] angle_out;

    // internal signal
    reg signed [16-1:0] new_x;
    reg signed [16-1:0] new_y;
    reg signed [16-1:0] new_angle;

    wire sign;
    wire signed [16-1:0] shifted_x;
    wire signed [16-1:0] shifted_y;

    assign sign = angle_in[16-1];  // angle sign bit
    assign shifted_x = x_in >>> SHIFT;
    assign shifted_y = y_in >>> SHIFT;

    always @(*)
    begin
        new_x = sign ? (x_in + shifted_y) : (x_in - shifted_y);
        new_y = sign ? (y_in - shifted_x) : (y_in + shifted_x);
        new_angle = sign ? (angle_in + angle_adj) : (angle_in - angle_adj);
    end

    always @(posedge clk)
    begin
        if (rst_n == 1'b0)
        begin
            x_out <= 0;
            y_out <= 0;
            angle_out <= 0;
        end
        else begin
            x_out <= new_x;
            y_out <= new_y;
            angle_out <= new_angle;        
        end
    end

endmodule
module cordic_10_16(clk, rst_n, angle_in, cos_out, sin_out);

    // inputs
    input clk;
    input rst_n;
    input signed [16-1:0] angle_in;

    // outputs
    output signed [16-1:0] cos_out;
    output signed [16-1:0] sin_out;

    // internal signals
    reg signed [16-1:0] x_in; 
    reg signed [16-1:0] y_in;
    reg signed [16-1:0] z_in;

    wire signed [16-1:0] xbus [0:10-1];
    wire signed [16-1:0] ybus [0:10-1];
    wire signed [16-1:0] zbus [0:10-1];

    assign cos_out = xbus[10-1];
    assign sin_out = ybus[10-1];

    always @(*)
    begin
        case($unsigned(angle_in[16-1:16-2]))
            2'b00:
                begin
                    x_in <= 16'd19896;
                    y_in <= 0;
                    z_in <= angle_in;
                end
            2'b11:
                begin
                    x_in <= 16'd19896;
                    y_in <= 0;
                    z_in <= angle_in;
                end
            2'b01:
                begin
                    x_in <= 0;
                    y_in <= 16'd19896;
                    z_in <= $signed({2'b00, angle_in[16-3:0]});
                end
            2'b10:
                begin
                    x_in <= 0;
                    y_in <= -16'd19896;
                    z_in <= $signed({2'b11, angle_in[16-3:0]});
                end
        endcase
    end

    // generate instances of cordic_stage
        cordic_stage_16 #(0) stage0(clk, rst_n, x_in, y_in, z_in, 16'sd8192, xbus[0], ybus[0], zbus[0]);
    cordic_stage_16 #(1) stage1(clk, rst_n, xbus[0], ybus[0], zbus[0], 16'sd4836, xbus[1], ybus[1], zbus[1]);
    cordic_stage_16 #(2) stage2(clk, rst_n, xbus[1], ybus[1], zbus[1], 16'sd2555, xbus[2], ybus[2], zbus[2]);
    cordic_stage_16 #(3) stage3(clk, rst_n, xbus[2], ybus[2], zbus[2], 16'sd1297, xbus[3], ybus[3], zbus[3]);
    cordic_stage_16 #(4) stage4(clk, rst_n, xbus[3], ybus[3], zbus[3], 16'sd651, xbus[4], ybus[4], zbus[4]);
    cordic_stage_16 #(5) stage5(clk, rst_n, xbus[4], ybus[4], zbus[4], 16'sd326, xbus[5], ybus[5], zbus[5]);
    cordic_stage_16 #(6) stage6(clk, rst_n, xbus[5], ybus[5], zbus[5], 16'sd163, xbus[6], ybus[6], zbus[6]);
    cordic_stage_16 #(7) stage7(clk, rst_n, xbus[6], ybus[6], zbus[6], 16'sd81, xbus[7], ybus[7], zbus[7]);
    cordic_stage_16 #(8) stage8(clk, rst_n, xbus[7], ybus[7], zbus[7], 16'sd41, xbus[8], ybus[8], zbus[8]);
    cordic_stage_16 #(9) stage9(clk, rst_n, xbus[8], ybus[8], zbus[8], 16'sd20, xbus[9], ybus[9], zbus[9]);


endmodule
module sddac(clk, rst_n, sig_in, sd_out);

    // inputs
    input clk;                          // clock
    input rst_n;                        // synchronous reset, active low
    input signed [15:0] sig_in;         // 16 bits in Q(1,15) format

    // outputs
    output reg sd_out = 0;

    // internal signals
    reg signed [17:0] state1 = 0;       // Q(1,17)
    reg signed [19:0] state2 = 0;       // Q(1,19)
    reg signed [16:0] state1_in;        // Q(0,17)
    reg signed [18:0] state2_in;        // Q(0,19)
    reg signed [20:0] quant_in;         // Q(2,19)
    reg signed [16:0] qq;
    reg        [7:0]  lfsr_reg = 0;
    reg               quantizer;
    wire lfsr_fb;

    // linear feedback shift register feedback
    assign lfsr_fb = (lfsr_reg[4] ^ lfsr_reg[2]);

    // combination process
    always @(*)
    begin
        `ifdef DEBUG_SDDAC
        qq = $signed(quantizer ? -17'h8000 : 17'h8000);
        `endif
        quant_in  = state2 + $signed(lfsr_fb ? -21'h4000 : 21'h4000);
        quantizer = quant_in[20];
        state1_in = sig_in - $signed(quantizer ? -17'h8000 : 17'h8000);        // Q(-1,17) - Q(0,17) -> Q(0,17)
        state2_in = state1 - $signed(quantizer ? -19'h10000 : 19'h10000);      // Q(-1,19) - Q(0,19) -> Q(0,19)
    end

    // clocked process
    always @(posedge clk)
    begin
        if (rst_n == 1'b0)
        begin
            state1 <= 0;
            state2 <= 0;
            lfsr_reg <= 8'hff;
        end
        else begin
            `ifdef DEBUG_SDDAC
            $display("feedback : %f", qq*$pow(2.0,-15));
            $display("state1_in: %f", state1_in*$pow(2.0,-17));
            $display("state2_in: %f", state2_in*$pow(2.0,-19));
            $display("");
            `endif
            state1 <= state1 + $signed({ state1_in[16], state1_in});
            state2 <= state2 + $signed({ state2_in[18], state2_in});
            sd_out <= !quantizer;
            lfsr_reg <= {lfsr_reg[6:0], lfsr_fb};
        end
    end

endmodule
module PRBS7(
    input wire clk, 
    input wire next,
    output wire out);

reg [6:0] d;

always @(posedge clk) 
begin
    if (next == 1)
        d <= { d[5:0], d[6] ^ d[5] };
    
    if (d == 0)
        d <= 1;
end

assign out = d[0];

endmodule
module top(clk, led, rst);

    // inputs
    input wire  clk;        // clock 12 MHz
    input wire  rst;

    wire dout;
    reg  wre = 0;
    wire din;
    wire random_bit;
    
    reg next_bit        = 0;
    reg [3:0] address   = 0;
    reg [1:0] state     = 0;
    reg [23:0] blinkCounter = 0;

    // outputs
    output reg [7:0] led = 0;  // leds for debugging

    // test state machine
    always @(posedge clk)
    begin
        next_bit <= 0;
        wre <= 0;
        if (rst == 0)
        begin
            blinkCounter <= 0;
            led[6:0]     <= 0;
        end
        else
        begin
            blinkCounter <= blinkCounter + 1;
            case(state)
                2'b00:  begin next_bit <= 1; address <= address + 1; end    /* setup for next test */
                2'b01:  begin wre <= 1; end                                 /* write bit */
                2'b10:  begin ; end
                2'b11:  
                    begin 
                        if (random_bit != dout)
                            led[6:0] <= led[6:0] + 1;
                    end                
            endcase
            state  <= state + 1;

        end

        led[7] <= blinkCounter[23];
    end

    PRBS7 prbs
    (
        .clk(clk),
        .next(next_bit),
        .out(random_bit)
    );

    LUTRAM16S1 ram
    (
        .clk(clk),
        .wre(wre),
        .ad(address),
        .di(random_bit),
        .do(dout)
    );

endmodule
module Gowin_PLLVR (clkout, clkin, lock_o, reset, reset_p, clkfb, clkoutd_o, fdiv, idiv, odiv);

output wire clkout;
output wire lock_o;
input wire clkin;
input wire reset;
input wire reset_p;
input wire clkfb;
output wire clkoutd_o;
input wire [5:0] fdiv;
input wire [5:0] idiv;
input wire [5:0] odiv;

wire clkoutp_o;
wire clkoutd3_o;
wire gw_gnd;
wire gw_vcc;

assign gw_gnd = 1'b0;
assign gw_vcc = 1'b1;

PLLVR pllvr_inst (
    .CLKOUT(clkout),
    .LOCK(lock_o),
    .CLKOUTP(clkoutp_o),
    .CLKOUTD(clkoutd_o),
    .CLKOUTD3(clkoutd3_o),
    .RESET(reset),
    .RESET_P(reset_p),
    .CLKIN(clkin),
    .CLKFB(gw_gnd),
    .FBDSEL(fdiv),
    .IDSEL(idiv),
    .ODSEL(odiv),
    .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
    .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
    .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
	.VREN(gw_vcc)
);

defparam pllvr_inst.FCLKIN = "27";
defparam pllvr_inst.DYN_IDIV_SEL = "true";
defparam pllvr_inst.IDIV_SEL = 5;
defparam pllvr_inst.DYN_FBDIV_SEL = "true";
defparam pllvr_inst.FBDIV_SEL = 12;
defparam pllvr_inst.DYN_ODIV_SEL = "true";
defparam pllvr_inst.ODIV_SEL = 8;
defparam pllvr_inst.PSDA_SEL = "0000";
defparam pllvr_inst.DYN_DA_EN = "false";
defparam pllvr_inst.DUTYDA_SEL = "1000";
defparam pllvr_inst.CLKOUT_FT_DIR = 1'b1;
defparam pllvr_inst.CLKOUTP_FT_DIR = 1'b1;
defparam pllvr_inst.CLKOUT_DLY_STEP = 0;
defparam pllvr_inst.CLKOUTP_DLY_STEP = 0;
defparam pllvr_inst.CLKFB_SEL = "internal";
defparam pllvr_inst.CLKOUT_BYPASS = "false";
defparam pllvr_inst.CLKOUTP_BYPASS = "false";
defparam pllvr_inst.CLKOUTD_BYPASS = "false";
defparam pllvr_inst.DYN_SDIV_SEL = 126;
defparam pllvr_inst.CLKOUTD_SRC = "CLKOUTP";
defparam pllvr_inst.CLKOUTD3_SRC = "CLKOUTP";
defparam pllvr_inst.DEVICE = "GW1NSR-4C";

endmodule //Gowin_rPLL
module Gowin_rPLL (clkout, clkin, lock_o, reset, reset_p, clkfb, clkoutd_o, fdiv, idiv);
output wire clkout;
output wire lock_o;
input wire clkin;
input wire reset;
input wire reset_p;
input wire clkfb;
output wire clkoutd_o;
input wire [5:0] fdiv;
input wire [5:0] idiv;

parameter DEVICE = "GW1N-1",
	      FCLKIN = "24",
	      FBDIV_SEL = 0,
		  IDIV_SEL =  0,
	      ODIV_SEL =  8,
	      DYN_ODIV_SEL="false",
          DYN_FBDIV_SEL="false",
          DYN_IDIV_SEL="false",
	      DYN_SDIV_SEL=2,
          PSDA_SEL="0000";

wire clkoutp_o;
wire clkoutd3_o;
wire gw_gnd;
wire gw_vcc;

assign gw_gnd = 1'b0;
assign gw_vcc = 1'b1;

rPLL rpll_inst (
    .CLKOUT(clkout),
    .LOCK(lock_o),
    .CLKOUTP(clkoutp_o),
    .CLKOUTD(clkoutd_o),
    .CLKOUTD3(clkoutd3_o),
    .RESET(reset),
    .RESET_P(reset_p),
    .CLKIN(clkin),
    .CLKFB(gw_gnd),
    .FBDSEL(fdiv),
    .IDSEL(idiv),
    .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
    .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
    .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
    .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd})
);

defparam rpll_inst.DEVICE = DEVICE;
defparam rpll_inst.FCLKIN = FCLKIN;
defparam rpll_inst.FBDIV_SEL = FBDIV_SEL;
defparam rpll_inst.DYN_IDIV_SEL = DYN_IDIV_SEL;
defparam rpll_inst.IDIV_SEL = IDIV_SEL;
defparam rpll_inst.DYN_FBDIV_SEL = DYN_FBDIV_SEL;
defparam rpll_inst.DYN_ODIV_SEL = DYN_ODIV_SEL;
defparam rpll_inst.ODIV_SEL = ODIV_SEL;
defparam rpll_inst.PSDA_SEL = PSDA_SEL;
defparam rpll_inst.DYN_DA_EN = "false";
defparam rpll_inst.DUTYDA_SEL = "1000";
defparam rpll_inst.CLKOUT_FT_DIR = 1'b1;
defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1;
defparam rpll_inst.CLKOUT_DLY_STEP = 0;
defparam rpll_inst.CLKOUTP_DLY_STEP = 0;
defparam rpll_inst.CLKFB_SEL = "internal";
defparam rpll_inst.CLKOUT_BYPASS = "false";
defparam rpll_inst.CLKOUTP_BYPASS = "false";
defparam rpll_inst.CLKOUTD_BYPASS = "false";
defparam rpll_inst.DYN_SDIV_SEL = DYN_SDIV_SEL;
defparam rpll_inst.CLKOUTD_SRC = "CLKOUTP";
defparam rpll_inst.CLKOUTD3_SRC = "CLKOUTP";

endmodule //Gowin_rPLL
module TOP
(
	input			rst,
    input           clk,

	output			LCD_CLK,
	output			LCD_HYNC,
	output			LCD_SYNC,
	output			LCD_DEN,
	output	[4:0]	LCD_R,
	output	[5:0]	LCD_G,
	output	[4:0]	LCD_B,

	output [2:0] led

);

	wire		CLK_SYS;	
	wire		CLK_PIX;
	wire LED_R;
	wire LED_G;
	wire LED_B;

/* //使用内部时钟
    Gowin_OSC chip_osc(
        .oscout(oscout_o) //output oscout
    );
*/
    /*Gowin_PLL chip_pll(
        .clkout(CLK_SYS), //output clkout      //200M
        .clkoutd(CLK_PIX), //output clkoutd   //33.33M
        .clkin(XTAL_IN) //input clkin
    );*/	

assign CLK_SYS = clk;
assign CLK_PIX = clk;
assign led[0] = LED_R;
assign led[1] = LED_G;
assign led[2] = LED_B;

	VGAMod	D1
	(
		.CLK		(	CLK_SYS     ),
		.nRST		(	rst		),

		.PixelClk	(	CLK_PIX		),
		.LCD_DE		(	LCD_DEN	 	),
		.LCD_HSYNC	(	LCD_HYNC 	),
    	.LCD_VSYNC	(	LCD_SYNC 	),

		.LCD_B		(	LCD_B		),
		.LCD_G		(	LCD_G		),
		.LCD_R		(	LCD_R		)
	);

	assign		LCD_CLK		=	CLK_PIX;

    //RGB LED TEST
    reg 	[31:0] Count;
    reg     [1:0] rgb_data;
	always @(  posedge CLK_SYS or negedge rst  )
	begin
		if(  !rst  )
		begin
		Count		<= 32'd0;
        rgb_data    <= 2'b00;
		end
		else if ( Count == 12000000 )
		begin
			Count <= 4'b0;
            rgb_data <= rgb_data + 1'b1;
		end
		else
		Count <= Count + 1'b1;
	end
    assign  LED_R = ~(rgb_data == 2'b01);
    assign  LED_G = ~(rgb_data == 2'b10);
    assign  LED_B = ~(rgb_data == 2'b11);

endmodule
module image_rom(
	input wire clk,
	input wire reset,
	input wire [11:0] ad,
	output wire [8:0] data
);

	wire gnd, vcc;
	assign gnd = 1'b0;
	assign vcc = 1'b1;

	wire [8:0] dummy_w [1:0];
	wire [8:0] data_w [1:0];
	assign data = data_w[ad[11]];

	pROMX9 rom2(
		.AD({ad[10:0], gnd, gnd, gnd}),
		.DO({dummy_w[0], data_w[1]}),
		.CLK(clk),
		.OCE(vcc),
		.CE(vcc),
		.RESET(reset)
	);
	defparam rom2.READ_MODE = 1'b1;
	defparam rom2.BIT_WIDTH = 9;
	defparam rom2.RESET_MODE = "SYNC";
`include "img-rom2.vh"

	pROMX9 rom3(
		.AD({ad[10:0], gnd, gnd, gnd}),
		.DO({dummy_w[1], data_w[0]}),
		.CLK(clk),
		.OCE(vcc),
		.CE(vcc),
		.RESET(reset)
	);
	defparam rom3.READ_MODE = 1'b1;
	defparam rom3.BIT_WIDTH = 9;
	defparam rom3.RESET_MODE = "SYNC";
`include "img-rom3.vh"

endmodule
module video_ram(
	input wire clk,
	input wire reset,
	input wire write_clk,
	input wire write_reset,
	input wire write_ce,
	input wire [10:0] write_ad,
	input wire [7:0]  write_data,
	input wire [10:0] read_ad,
	output wire [7:0] read_data
);

	wire gnd, vcc;
	assign gnd = 1'b0;
	assign vcc = 1'b1;

	wire [23:0] dummy_w;

	SDPB mem(
		.DO({dummy_w, read_data}),
		.DI({{24{gnd}}, write_data}),
		.ADA({write_ad, gnd, gnd, gnd}),
		.ADB({ read_ad, gnd, gnd, gnd}),
		.CLKA(write_clk),
		.CLKB(clk),
		.OCE(vcc),
		.CEA(write_ce),
		.CEB(vcc),
		.BLKSELA(3'b000),
		.BLKSELB(3'b000),
		.RESETA(write_reset),
		.RESETB(reset)
	);
	defparam mem.READ_MODE = 1'b1;
	defparam mem.BIT_WIDTH_0 = 8;
	defparam mem.BIT_WIDTH_1 = 8;
	defparam mem.BLK_SEL_0 = 3'b000;
	defparam mem.BLK_SEL_1 = 3'b000;
	defparam mem.RESET_MODE = "SYNC";
`include "img-video-ram.vh"
endmodule
module top (
    input clk,
	input rst_i,
    output elvds_p,
    output elvds_n,
	output LED_B
);

	ELVDS_TBUF diff_buf(
			.OEN(w_oen),
			.O(elvds_p),
			.OB(elvds_n),
			.I(oser_out)
		);

	OSER10 os(
		.D0(1'b0),
		.D1(1'b1),
		.D2(1'b0),
		.D3(1'b1),
		.D4(1'b0),
		.D5(1'b1),
		.D6(1'b0),
		.D7(1'b1),
		.D8(1'b0),
		.D9(1'b1),
		.FCLK(fclk_w),
		.PCLK(pclk_w),
		.RESET(1'b0),
		.Q(oser_out)
	);
	defparam os.GSREN = "false";
	defparam os.LSREN = "true";

	wire clk_w;
	wire pclk_w;
	wire fclk_w;

	assign pclk_o = pclk_w;
	assign fclk_o = fclk_w;

	reg [2:0] count;
	wire clkA;
	reg clkB;
	always @(posedge fclk_w) begin
		if (!rst_i) begin
			count <= 0;
		end else begin 
			if (count == 3'd4) begin
				count <= 0;
			end else begin
				count <= count+1;
			end
		end 
	end
	assign clkA = count[1];

	always@(negedge fclk_w) begin
		clkB <= clkA;
	end
	assign pclk_w = clkA | clkB;

	// slow 
	reg [24:0] ctr_q;
	wire [24:0] ctr_d;
	wire tick_w;

	// Sequential code (flip-flop)
	always @(posedge clk)
		ctr_q <= ctr_d;

	// Combinational code (boolean logic)
	assign ctr_d = ctr_q + 1'b1;
	assign tick_w = ctr_q[24];

	assign fclk_w = tick_w;
	assign LED_B = tick_w;
endmodule
module video_ram(
	input wire clk,
	input wire reset,
	input wire wre,
	input wire [8:0]  write_data,
	input wire [10:0] ad,
	output wire [8:0] read_data
);

	wire gnd, vcc;
	assign gnd = 1'b0;
	assign vcc = 1'b1;

	wire [26:0] dummy;

	SPX9 mem(
		.DO({dummy, read_data}),
		.DI({{27{gnd}}, write_data}),
		.AD({ad, gnd, gnd, gnd}),
		.CLK(clk),
		.CE(vcc),
		.WRE(wre),
		.OCE(vcc),
		.BLKSEL(3'b000),
		.RESET(reset)
	);
	defparam mem.READ_MODE = 1'b1;
	defparam mem.WRITE_MODE = 2'b01;
	defparam mem.BIT_WIDTH = 9;
	defparam mem.BLK_SEL = 3'b000;
	defparam mem.RESET_MODE = "SYNC";
`include "img-video-ram1.vh"
endmodule
module image_rom(
	input wire clk,
	input wire reset,
	input wire [11:0] ad,
	output wire [7:0] data
);

	wire gnd, vcc;
	assign gnd = 1'b0;
	assign vcc = 1'b1;

	wire [23:0] dummy_w [1:0];
	wire [7:0] data_w [1:0];
	assign data = data_w[ad[11]];

	pROM rom(
		.AD({ad[10:0], gnd, gnd, gnd}),
		.DO({dummy_w[0], data_w[0]}),
		.CLK(clk),
		.OCE(vcc),
		.CE(vcc),
		.RESET(reset)
	);
	defparam rom.READ_MODE = 1'b1;
	defparam rom.BIT_WIDTH = 8;
	defparam rom.RESET_MODE = "SYNC";
`include "img-rom.vh"

	pROM rom1(
		.AD({ad[10:0], gnd, gnd, gnd}),
		.DO({dummy_w[1], data_w[1]}),
		.CLK(clk),
		.OCE(vcc),
		.CE(vcc),
		.RESET(reset)
	);
	defparam rom1.READ_MODE = 1'b1;
	defparam rom1.BIT_WIDTH = 8;
	defparam rom1.RESET_MODE = "SYNC";
`include "img-rom1.vh"

endmodule
module idsp(input wire clk, input wire reset, 
	output wire [63:0] product, 
	output wire [63:0] product1, 
	output wire [63:0] product2, 
	output wire [63:0] product3, 
	output wire [63:0] product4);

	wire [17:0] sob;
	wire [17:0] sob1;
	wire [17:0] sob2;
	wire [17:0] sob3;
	wire [17:0] sob4;
	wire gnd = 1'b0;

	PADD18 padd18_0(
		.A({18'hf12}),
		.B({18'h6}),
		.SI({18{gnd}}),
		.SBI({18{gnd}}),
		.ASEL(gnd),
		.CE(1'b1),
		.CLK(clk),
		.RESET(reset),
		.SO(sob),
		.SBO(),
		.DOUT(product[17:0])
	);
	defparam padd18_0.AREG=1'b1;
	defparam padd18_0.BREG=1'b1;
	defparam padd18_0.ADD_SUB=1'b0;
	defparam padd18_0.BSEL_MODE=1'b0;
	defparam padd18_0.SOREG=1'b0;
	defparam padd18_0.PADD_RESET_MODE="SYNC";

	PADD18 padd18_1(
		.A({18'h2}),
		.B({18'hf12}),
		.SI(sob),
		.SBI({18{gnd}}),
		.ASEL(1'b1),
		.CE(1'b1),
		.CLK(clk),
		.RESET(reset),
		.SO(sob1),
		.SBO(),
		.DOUT(product1[17:0])
	);
	defparam padd18_1.AREG=1'b1;
	defparam padd18_1.BREG=1'b1;
	defparam padd18_1.ADD_SUB=1'b1;
	defparam padd18_1.BSEL_MODE=1'b0;
	defparam padd18_1.SOREG=1'b0;
	defparam padd18_1.PADD_RESET_MODE="SYNC";

	PADD18 padd18_2(
		.A({18'h3}),
		.B({18'h8f12}),
		.SI(sob1),
		.SBI({18{gnd}}),
		.ASEL(1'b1),
		.CE(1'b1),
		.CLK(clk),
		.RESET(reset),
		.SO(sob2),
		.SBO(),
		.DOUT(product2[17:0])
	);
	defparam padd18_2.AREG=1'b1;
	defparam padd18_2.BREG=1'b1;
	defparam padd18_2.ADD_SUB=1'b1;
	defparam padd18_2.BSEL_MODE=1'b0;
	defparam padd18_2.SOREG=1'b0;
	defparam padd18_2.PADD_RESET_MODE="SYNC";

	PADD18 padd18_3(
		.A({18'h4}),
		.B({18'haf12}),
		.SI(sob2),
		.SBI({18{gnd}}),
		.ASEL(1'b1),
		.CE(1'b1),
		.CLK(clk),
		.RESET(reset),
		.SO(sob3),
		.SBO(),
		.DOUT(product3[17:0])
	);
	defparam padd18_3.AREG=1'b1;
	defparam padd18_3.BREG=1'b1;
	defparam padd18_3.ADD_SUB=1'b1;
	defparam padd18_3.BSEL_MODE=1'b0;
	defparam padd18_3.SOREG=1'b0;
	defparam padd18_3.PADD_RESET_MODE="SYNC";

	PADD18 padd18_4(
		.A({18'h123}),
		.B({18'hff12}),
		.SI(sob3),
		.SBI({18{gnd}}),
		.ASEL(1'b1),
		.CE(1'b1),
		.CLK(clk),
		.RESET(reset),
		.SO(sob4),
		.SBO(),
		.DOUT(product4[17:0])
	);
	defparam padd18_4.AREG=1'b1;
	defparam padd18_4.BREG=1'b1;
	defparam padd18_4.ADD_SUB=1'b1;
	defparam padd18_4.BSEL_MODE=1'b0;
	defparam padd18_4.SOREG=1'b0;
	defparam padd18_4.PADD_RESET_MODE="SYNC";
endmodule
module video_ram(
	input wire clk,
	input wire reset,
	input wire write_clk,
	input wire write_reset,
	input wire write_ce,
	input wire read_wre,
	input wire [10:0] write_ad,
	input wire [7:0]  write_data,
	input wire   [10:0] read_ad,
	output wire [7:0] read_data
);

	wire gnd, vcc;
	assign gnd = 1'b0;
	assign vcc = 1'b1;

	wire [7:0] dummy;

	DPB mem(
		.DOB({dummy, read_data}),
		.DIA({{8{gnd}}, write_data}),
		.DIB({16{gnd}}),
		.ADA({write_ad, gnd, gnd, gnd}),
		.ADB({ read_ad, gnd, gnd, gnd}),
		.CLKA(write_clk),
		.CLKB(clk),
		.OCEA(vcc),
		.OCEB(vcc),
		.CEA(write_ce),
		.CEB(vcc),
		.WREA(vcc),
		.WREB(read_wre),
		.BLKSELA(3'b000),
		.BLKSELB(3'b000),
		.RESETA(write_reset),
		.RESETB(reset)
	);
	defparam mem.READ_MODE0 = 1'b1;
	defparam mem.READ_MODE1 = 1'b1;
	defparam mem.WRITE_MODE0 = 2'b01;
	defparam mem.WRITE_MODE1 = 2'b01;
	defparam mem.BIT_WIDTH_0 = 8;
	defparam mem.BIT_WIDTH_1 = 8;
	defparam mem.BLK_SEL_0 = 3'b000;
	defparam mem.BLK_SEL_1 = 3'b000;
	defparam mem.RESET_MODE = "SYNC";
`include "img-video-ram.vh"
endmodule
module video_ram(
	input wire clk,
	input wire reset,
	input wire write_clk,
	input wire write_reset,
	input wire write_ce,
	input wire read_wre,
	input wire [9:0] write_ad,
	input wire [15:0]  write_data,
	input wire   [9:0] read_ad,
	output wire [15:0] read_data
);

	wire gnd, vcc;
	assign gnd = 1'b0;
	assign vcc = 1'b1;

	wire [15:0] dummy;

	DPB mem(
		.DOB({read_data}),
		.DIA({write_data}),
		.DIB({16{gnd}}),
		.ADA({write_ad, gnd, gnd, vcc, vcc}),
		.ADB({ read_ad, gnd, gnd, vcc, vcc}),
		.CLKA(write_clk),
		.CLKB(clk),
		.OCEA(gnd),
		.OCEB(gnd),
		.CEA(write_ce),
		.CEB(vcc),
		.WREA(vcc),
		.WREB(read_wre),
		.BLKSELA(3'b000),
		.BLKSELB(3'b000),
		.RESETA(write_reset),
		.RESETB(reset)
	);
	defparam mem.READ_MODE0 = 1'b0;
	defparam mem.READ_MODE1 = 1'b0;
	defparam mem.WRITE_MODE0 = 2'b01;
	defparam mem.WRITE_MODE1 = 2'b01;
	defparam mem.BIT_WIDTH_0 = 16;
	defparam mem.BIT_WIDTH_1 = 16;
	defparam mem.BLK_SEL_0 = 3'b000;
	defparam mem.BLK_SEL_1 = 3'b000;
	defparam mem.RESET_MODE = "SYNC";
`include "img-video-ram.vh"
endmodule
module top (
    input clk,
	input rst_i,
    output tlvds_p,
    output tlvds_n,
	output LED_B
);

	TLVDS_TBUF diff_buf(
			.OEN(w_oen),
			.O(tlvds_p),
			.OB(tlvds_n),
			.I(oser_out)
		);

	OSER10 os(
		.D0(1'b0),
		.D1(1'b1),
		.D2(1'b0),
		.D3(1'b1),
		.D4(1'b0),
		.D5(1'b1),
		.D6(1'b0),
		.D7(1'b1),
		.D8(1'b0),
		.D9(1'b1),
		.FCLK(fclk_w),
		.PCLK(pclk_w),
		.RESET(1'b0),
		.Q(oser_out)
	);
	defparam os.GSREN = "false";
	defparam os.LSREN = "true";

	wire clk_w;
	wire pclk_w;
	wire fclk_w;

	assign pclk_o = pclk_w;
	assign fclk_o = fclk_w;

	reg [2:0] count;
	wire clkA;
	reg clkB;
	always @(posedge fclk_w) begin
		if (!rst_i) begin
			count <= 0;
		end else begin 
			if (count == 3'd4) begin
				count <= 0;
			end else begin
				count <= count+1;
			end
		end 
	end
	assign clkA = count[1];

	always@(negedge fclk_w) begin
		clkB <= clkA;
	end
	assign pclk_w = clkA | clkB;

	// slow 
	reg [24:0] ctr_q;
	wire [24:0] ctr_d;
	wire tick_w;

	// Sequential code (flip-flop)
	always @(posedge clk)
		ctr_q <= ctr_d;

	// Combinational code (boolean logic)
	assign ctr_d = ctr_q + 1'b1;
	assign tick_w = ctr_q[24];

	assign fclk_w = tick_w;
	assign LED_B = tick_w;
endmodule
module video_ram(
	input wire clk,
	input wire reset,
	input wire write_clk,
	input wire write_reset,
	input wire write_ce,
	input wire [10:0] write_ad,
	input wire [8:0]  write_data,
	input wire [10:0] read_ad,
	output wire [8:0] read_data
);

	wire gnd, vcc;
	assign gnd = 1'b0;
	assign vcc = 1'b1;

	wire [26:0] dummy_w;

	SDPX9B mem(
		.DO({dummy_w, read_data}),
		.DI({{27{gnd}}, write_data}),
		.ADA({write_ad, gnd, gnd, gnd}),
		.ADB({ read_ad, gnd, gnd, gnd}),
		.CLKA(write_clk),
		.CLKB(clk),
		.OCE(vcc),
		.CEA(write_ce),
		.CEB(vcc),
		.BLKSELA(3'b000),
		.BLKSELB(3'b000),
		.RESETA(write_reset),
		.RESETB(reset)
	);
	defparam mem.READ_MODE = 1'b1;
	defparam mem.BIT_WIDTH_0 = 9;
	defparam mem.BIT_WIDTH_1 = 9;
	defparam mem.BLK_SEL_0 = 3'b000;
	defparam mem.BLK_SEL_1 = 3'b000;
	defparam mem.RESET_MODE = "SYNC";
`include "img-video-ram1.vh"
endmodule
module video_ram(
	input wire clk,
	input wire reset,
	input wire wre,
	input wire [7:0]  write_data,
	input wire [10:0] ad,
	output wire [7:0] read_data
);

	wire gnd, vcc;
	assign gnd = 1'b0;
	assign vcc = 1'b1;

	wire [23:0] dummy;

	SP mem(
		.DO({dummy, read_data}),
		.DI({{24{gnd}}, write_data}),
		.AD({ad, gnd, gnd, gnd}),
		.CLK(clk),
		.CE(vcc),
		.WRE(wre),
		.OCE(vcc),
		.BLKSEL(3'b000),
		.RESET(reset)
	);
	defparam mem.READ_MODE = 1'b1;
	defparam mem.WRITE_MODE = 2'b01;
	defparam mem.BIT_WIDTH = 8;
	defparam mem.BLK_SEL = 3'b000;
	defparam mem.RESET_MODE = "SYNC";
`include "img-video-ram.vh"
endmodule
module idsp(input wire clk, input wire reset, 
	output wire [63:0] product, 
	output wire [63:0] product1, 
	output wire [63:0] product2, 
	output wire [63:0] product3, 
	output wire [63:0] product4);

wire [17:0] soa;
wire [17:0] sob;
wire [17:0] soa0;
wire [17:0] sob0;
wire [17:0] soa1;
wire [17:0] sob1;
wire [17:0] soa2;
wire [17:0] sob2;
wire gnd = 1'b0;

MULT18X18 mult_0(
	.A({18'h12345}),
	.B({18'hfd}),
	.SIA({18{gnd}}),
	.SIB({18{gnd}}),
	.ASIGN(gnd),
	.BSIGN(gnd),
	.ASEL(gnd),
	.BSEL(gnd),
	.CE(1'b1),
	.CLK(clk),
	.RESET(reset),
	.SOA(soa),
	.SOB(sob),
	.DOUT(product)
);
defparam mult_0.AREG=1'b1;
defparam mult_0.BREG=1'b1;
defparam mult_0.OUT_REG=1'b0;
defparam mult_0.PIPE_REG=1'b0;
defparam mult_0.ASIGN_REG=1'b0;
defparam mult_0.BSIGN_REG=1'b0;
defparam mult_0.SOA_REG=1'b0;
defparam mult_0.MULT_RESET_MODE="SYNC";

MULT18X18 mult_1(
	.A({18'h2}),
	.B({18'h2}),
	.SIA(soa),
	.SIB(sob),
	.ASIGN(gnd),
	.BSIGN(gnd),
	.ASEL(1'b1),
	.BSEL(gnd),
	.CE(1'b1),
	.CLK(clk),
	.RESET(reset),
	.SOA(soa0),
	.SOB(sob0),
	.DOUT(product1)
);
defparam mult_1.AREG=1'b1;
defparam mult_1.BREG=1'b1;
defparam mult_1.OUT_REG=1'b1;
defparam mult_1.PIPE_REG=1'b0;
defparam mult_1.ASIGN_REG=1'b0;
defparam mult_1.BSIGN_REG=1'b0;
defparam mult_1.SOA_REG=1'b1;
defparam mult_1.MULT_RESET_MODE="SYNC";

MULT18X18 mult_2(
	.A({18'h4}),
	.B({18'h4}),
	.SIA(soa0),
	.SIB(sob0),
	.ASIGN(gnd),
	.BSIGN(gnd),
	.ASEL(1'b1),
	.BSEL(gnd),
	.CE(1'b1),
	.CLK(clk),
	.RESET(reset),
	.SOA(soa1),
	.SOB(sob1),
	.DOUT(product2)
);
defparam mult_2.AREG=1'b1;
defparam mult_2.BREG=1'b1;
defparam mult_2.OUT_REG=1'b0;
defparam mult_2.PIPE_REG=1'b0;
defparam mult_2.ASIGN_REG=1'b0;
defparam mult_2.BSIGN_REG=1'b0;
defparam mult_2.SOA_REG=1'b0;
defparam mult_2.MULT_RESET_MODE="SYNC";

MULT18X18 mult_3(
	.A({18'h4}),
	.B({18'h5}),
	.SIA(soa1),
	.SIB(sob1),
	.ASIGN(gnd),
	.BSIGN(gnd),
	.ASEL(1'b1),
	.BSEL(gnd),
	.CE(1'b1),
	.CLK(clk),
	.RESET(reset),
	.SOA(soa2),
	.SOB(sob2),
	.DOUT(product3)
);
defparam mult_3.AREG=1'b1;
defparam mult_3.BREG=1'b1;
defparam mult_3.OUT_REG=1'b0;
defparam mult_3.PIPE_REG=1'b0;
defparam mult_3.ASIGN_REG=1'b0;
defparam mult_3.BSIGN_REG=1'b0;
defparam mult_3.SOA_REG=1'b1;
defparam mult_3.MULT_RESET_MODE="SYNC";

MULT18X18 mult_4(
	.A({18'h4}),
	.B({18'h6}),
	.SIA(soa2),
	.SIB(sob2),
	.ASIGN(gnd),
	.BSIGN(gnd),
	.ASEL(1'b1),
	.BSEL(gnd),
	.CE(1'b1),
	.CLK(clk),
	.RESET(reset),
	.SOA(),
	.SOB(),
	.DOUT(product4)
);
defparam mult_4.AREG=1'b1;
defparam mult_4.BREG=1'b1;
defparam mult_4.OUT_REG=1'b1;
defparam mult_4.PIPE_REG=1'b0;
defparam mult_4.ASIGN_REG=1'b0;
defparam mult_4.BSIGN_REG=1'b0;
defparam mult_4.SOA_REG=1'b0;
defparam mult_4.MULT_RESET_MODE="SYNC";
endmodule
module idsp(input wire clk, input wire reset, 
	output wire [63:0] product, 
	output wire [63:0] product1, 
	output wire [63:0] product2, 
	output wire [63:0] product3, 
	output wire [63:0] product4);

	wire [8:0] sob;
	wire [8:0] sob0;
	wire [8:0] sob1;
	wire [8:0] sob2;
	wire gnd = 1'b0;

	PADD9 padd_0(
		.A({9'h1}),
		.B({9'h6}),
		.SI({9{gnd}}),
		.SBI(sob),
		.ASEL(gnd),
		.CE(1'b1),
		.CLK(clk),
		.RESET(reset),
		.SO(),
		.SBO(),
		.DOUT(product[8:0])
	);
	defparam padd_0.AREG=1'b0;
	defparam padd_0.BREG=1'b1;
	defparam padd_0.ADD_SUB=1'b0;
	defparam padd_0.BSEL_MODE=1'b1;
	defparam padd_0.SOREG=1'b0;
	defparam padd_0.PADD_RESET_MODE="SYNC";

	PADD9 padd_1(
		.A({9'h2}),
		.B({9'h5}),
		.SI({9{gnd}}),
		.SBI(sob0),
		.ASEL(gnd),
		.CE(1'b1),
		.CLK(clk),
		.RESET(reset),
		.SO(),
		.SBO(sob),
		.DOUT(product1[8:0])
	);
	defparam padd_1.AREG=1'b0;
	defparam padd_1.BREG=1'b1;
	defparam padd_1.ADD_SUB=1'b0;
	defparam padd_1.BSEL_MODE=1'b1;
	defparam padd_1.SOREG=1'b0;
	defparam padd_1.PADD_RESET_MODE="SYNC";

	PADD9 padd_2(
		.A({9'h3}),
		.B({9'h4}),
		.SI({9{gnd}}),
		.SBI(sob1),
		.ASEL(gnd),
		.CE(1'b1),
		.CLK(clk),
		.RESET(reset),
		.SO(),
		.SBO(sob0),
		.DOUT(product2[8:0])
	);
	defparam padd_2.AREG=1'b0;
	defparam padd_2.BREG=1'b1;
	defparam padd_2.ADD_SUB=1'b0;
	defparam padd_2.BSEL_MODE=1'b1;
	defparam padd_2.SOREG=1'b0;
	defparam padd_2.PADD_RESET_MODE="SYNC";

	PADD9 padd_3(
		.A({9'h4}),
		.B({9'h3}),
		.SI({9{gnd}}),
		.SBI(sob2),
		.ASEL(gnd),
		.CE(1'b1),
		.CLK(clk),
		.RESET(reset),
		.SO(),
		.SBO(sob1),
		.DOUT(product3[8:0])
	);
	defparam padd_3.AREG=1'b0;
	defparam padd_3.BREG=1'b1;
	defparam padd_3.ADD_SUB=1'b0;
	defparam padd_3.BSEL_MODE=1'b1;
	defparam padd_3.SOREG=1'b0;
	defparam padd_3.PADD_RESET_MODE="SYNC";

	PADD9 padd_4(
		.A({9'h123}),
		.B({9'hd}),
		.SI({9{gnd}}),
		.SBI({9{gnd}}),
		.ASEL(gnd),
		.CE(1'b1),
		.CLK(clk),
		.RESET(reset),
		.SO(),
		.SBO(sob2),
		.DOUT(product4[8:0])
	);
	defparam padd_4.AREG=1'b0;
	defparam padd_4.BREG=1'b1;
	defparam padd_4.ADD_SUB=1'b0;
	defparam padd_4.BSEL_MODE=1'b0;
	defparam padd_4.SOREG=1'b0;
	defparam padd_4.PADD_RESET_MODE="SYNC";
	endmodule
module top(input wire clk, output wire [5:0]led, input wire key_i);
	wire gnd;
	assign gnd = 1'b0;
	wire dummy;
	reg [5:0] fdiv;
	reg [5:0] idiv;
	reg [5:0] odiv;
    Gowin_PLLVR rpll_0(
        .clkout(led[0]),
        .clkin(clk),
		.lock_o(led[1]),
		.reset(gnd),
		.reset_p(gnd),
		.clkfb(gnd),
		.clkoutd_o(led[2]),
		.fdiv(fdiv),
		.idiv(idiv),
		.odiv(6'b111100) // 8
        );

    Gowin_PLLVR rpll_1(
        .clkout(led[3]),
        .clkin(clk),
		.lock_o(led[4]),
		.reset(gnd),
		.reset_p(gnd),
		.clkfb(gnd),
		.clkoutd_o(led[5]),
		.fdiv(~6'd9),
		.idiv(~6'd2),
		.odiv(6'b111100) // 8
        );

	// dynamic
	always @ (posedge clk) begin
		if (key_i) begin
			fdiv <= ~6'd12;
			idiv <= ~6'd5;
			odiv <= 6'b111000; // 16
		end else begin
			fdiv <= ~6'd9;
			idiv <= ~6'd2;
			odiv <= ~6'b111100; // 8
		end
	end
endmodule
module video_ram(
	input wire clk,
	input wire reset,
	input wire write_clk,
	input wire write_reset,
	input wire write_ce,
	input wire read_wre,
	input wire [10:0] write_ad,
	input wire [8:0]  write_data,
	input wire   [10:0] read_ad,
	output wire [8:0] read_data
);

	wire gnd, vcc;
	assign gnd = 1'b0;
	assign vcc = 1'b1;

	wire [8:0] dummy;

	DPX9B mem(
		.DOB({dummy, read_data}),
		.DIA({{9{gnd}},write_data}),
		.DIB({18{gnd}}),
		.ADA({write_ad, gnd, gnd, gnd}),
		.ADB({ read_ad, gnd, gnd, gnd}),
		.CLKA(write_clk),
		.CLKB(clk),
		.OCEA(vcc),
		.OCEB(vcc),
		.CEA(write_ce),
		.CEB(vcc),
		.WREA(vcc),
		.WREB(read_wre),
		.BLKSELA(3'b000),
		.BLKSELB(3'b000),
		.RESETA(write_reset),
		.RESETB(reset)
	);
	defparam mem.READ_MODE0 = 1'b1;
	defparam mem.READ_MODE1 = 1'b1;
	defparam mem.WRITE_MODE0 = 2'b01;
	defparam mem.WRITE_MODE1 = 2'b01;
	defparam mem.BIT_WIDTH_0 = 9;
	defparam mem.BIT_WIDTH_1 = 9;
	defparam mem.BLK_SEL_0 = 3'b000;
	defparam mem.BLK_SEL_1 = 3'b000;
	defparam mem.RESET_MODE = "SYNC";
`include "img-video-ram1.vh"
endmodule
module image_rom(
	input wire clk,
	input wire reset,
	input wire [10:0] ad,
	output wire [15:0] data
);

	wire gnd, vcc;
	assign gnd = 1'b0;
	assign vcc = 1'b1;

	wire [15:0] dummy [1:0];
	wire [15:0] data_mux [1:0];
	assign data = data_mux[ad[10]];

	pROM rom(
		.AD({ad[9:0], gnd, gnd, gnd, gnd}),
		.DO({dummy[0], data_mux[0]}),
		.CLK(clk),
		.OCE(vcc),
		.CE(vcc),
		.RESET(reset)
	);
	defparam rom.READ_MODE = 1'b1;
	defparam rom.BIT_WIDTH = 16;
	defparam rom.RESET_MODE = "SYNC";
`include "img-rom.vh"

	pROM rom1(
		.AD({ad[9:0], gnd, gnd, gnd, gnd}),
		.DO({dummy[1], data_mux[1]}),
		.CLK(clk),
		.OCE(vcc),
		.CE(vcc),
		.RESET(reset)
	);
	defparam rom1.READ_MODE = 1'b1;
	defparam rom1.BIT_WIDTH = 16;
	defparam rom1.RESET_MODE = "SYNC";
`include "img-rom1.vh"

endmodule
module idsp(input wire clk, input wire reset, 
	output wire [63:0] product, 
	output wire [63:0] product1, 
	output wire [63:0] product2, 
	output wire [63:0] product3, 
	output wire [63:0] product4);

wire [8:0] soa;
wire [8:0] sob;
wire [8:0] soa0;
wire [8:0] sob0;
wire [8:0] soa1;
wire [8:0] sob1;
wire [8:0] soa2;
wire [8:0] sob2;
wire gnd = 1'b0;

MULT9X9 mult_0(
	.A({9'h123}),
	.B({9'hfd}),
	.SIA({9{gnd}}),
	.SIB({9{gnd}}),
	.ASIGN(gnd),
	.BSIGN(gnd),
	.ASEL(gnd),
	.BSEL(gnd),
	.CE(1'b1),
	.CLK(clk),
	.RESET(reset),
	.SOA(soa),
	.SOB(sob),
	.DOUT(product[17:0])
);
defparam mult_0.AREG=1'b1;
defparam mult_0.BREG=1'b1;
defparam mult_0.OUT_REG=1'b0;
defparam mult_0.PIPE_REG=1'b0;
defparam mult_0.ASIGN_REG=1'b0;
defparam mult_0.BSIGN_REG=1'b0;
defparam mult_0.SOA_REG=1'b0;
defparam mult_0.MULT_RESET_MODE="SYNC";

MULT9X9 mult_1(
	.A({9'h2}),
	.B({9'h2}),
	.SIA(soa),
	.SIB(sob),
	.ASIGN(gnd),
	.BSIGN(gnd),
	.ASEL(1'b1),
	.BSEL(gnd),
	.CE(1'b1),
	.CLK(clk),
	.RESET(reset),
	.SOA(soa0),
	.SOB(sob0),
	.DOUT(product1[17:0])
);
defparam mult_1.AREG=1'b1;
defparam mult_1.BREG=1'b1;
defparam mult_1.OUT_REG=1'b1;
defparam mult_1.PIPE_REG=1'b0;
defparam mult_1.ASIGN_REG=1'b0;
defparam mult_1.BSIGN_REG=1'b0;
defparam mult_1.SOA_REG=1'b1;
defparam mult_1.MULT_RESET_MODE="SYNC";

MULT9X9 mult_2(
	.A({9'h4}),
	.B({9'h4}),
	.SIA(soa0),
	.SIB(sob0),
	.ASIGN(gnd),
	.BSIGN(gnd),
	.ASEL(1'b1),
	.BSEL(gnd),
	.CE(1'b1),
	.CLK(clk),
	.RESET(reset),
	.SOA(soa1),
	.SOB(sob1),
	.DOUT(product2[17:0])
);
defparam mult_2.AREG=1'b1;
defparam mult_2.BREG=1'b1;
defparam mult_2.OUT_REG=1'b0;
defparam mult_2.PIPE_REG=1'b0;
defparam mult_2.ASIGN_REG=1'b0;
defparam mult_2.BSIGN_REG=1'b0;
defparam mult_2.SOA_REG=1'b0;
defparam mult_2.MULT_RESET_MODE="SYNC";

MULT9X9 mult_3(
	.A({9'h4}),
	.B({9'h5}),
	.SIA(soa1),
	.SIB(sob1),
	.ASIGN(gnd),
	.BSIGN(gnd),
	.ASEL(1'b1),
	.BSEL(gnd),
	.CE(1'b1),
	.CLK(clk),
	.RESET(reset),
	.SOA(soa2),
	.SOB(sob2),
	.DOUT(product3[17:0])
);
defparam mult_3.AREG=1'b1;
defparam mult_3.BREG=1'b1;
defparam mult_3.OUT_REG=1'b0;
defparam mult_3.PIPE_REG=1'b0;
defparam mult_3.ASIGN_REG=1'b0;
defparam mult_3.BSIGN_REG=1'b0;
defparam mult_3.SOA_REG=1'b1;
defparam mult_3.MULT_RESET_MODE="SYNC";

MULT9X9 mult_4(
	.A({9'h4}),
	.B({9'h6}),
	.SIA(soa2),
	.SIB(sob2),
	.ASIGN(gnd),
	.BSIGN(gnd),
	.ASEL(1'b1),
	.BSEL(gnd),
	.CE(1'b1),
	.CLK(clk),
	.RESET(reset),
	.SOA(),
	.SOB(),
	.DOUT(product4[17:0])
);
defparam mult_4.AREG=1'b1;
defparam mult_4.BREG=1'b1;
defparam mult_4.OUT_REG=1'b1;
defparam mult_4.PIPE_REG=1'b0;
defparam mult_4.ASIGN_REG=1'b0;
defparam mult_4.BSIGN_REG=1'b0;
defparam mult_4.SOA_REG=1'b0;
defparam mult_4.MULT_RESET_MODE="SYNC";
endmodule
module video_ram(
	input wire clk,
	input wire reset,
	input wire write_clk,
	input wire write_reset,
	input wire write_ce,
	input wire read_wre,
	input wire [9:0] write_ad,
	input wire [17:0]  write_data,
	input wire   [9:0] read_ad,
	output wire [17:0] read_data
);

	wire gnd, vcc;
	assign gnd = 1'b0;
	assign vcc = 1'b1;

	wire [17:0] dummy;

	DPX9B mem(
		.DOB({read_data}),
		.DIA({write_data}),
		.DIB({18{gnd}}),
		.ADA({write_ad, gnd, gnd, vcc, vcc}),
		.ADB({ read_ad, gnd, gnd, vcc, vcc}),
		.CLKA(write_clk),
		.CLKB(clk),
		.OCEA(gnd),
		.OCEB(gnd),
		.CEA(write_ce),
		.CEB(vcc),
		.WREA(vcc),
		.WREB(read_wre),
		.BLKSELA(3'b000),
		.BLKSELB(3'b000),
		.RESETA(write_reset),
		.RESETB(reset)
	);
	defparam mem.READ_MODE0 = 1'b0;
	defparam mem.READ_MODE1 = 1'b0;
	defparam mem.WRITE_MODE0 = 2'b01;
	defparam mem.WRITE_MODE1 = 2'b01;
	defparam mem.BIT_WIDTH_0 = 18;
	defparam mem.BIT_WIDTH_1 = 18;
	defparam mem.BLK_SEL_0 = 3'b000;
	defparam mem.BLK_SEL_1 = 3'b000;
	defparam mem.RESET_MODE = "SYNC";
`include "img-video-ram1.vh"
endmodule
module image_rom(
	input wire clk,
	input wire reset,
	input wire [10:0] ad,
	output wire [17:0] data
);

	wire gnd, vcc;
	assign gnd = 1'b0;
	assign vcc = 1'b1;

	wire [17:0] dummy_w [1:0];
	wire [17:0] data_w [1:0];
	assign data = data_w[ad[10]];

	pROMX9 rom2(
		.AD({ad[9:0], gnd, gnd, gnd, gnd}),
		.DO({dummy_w[0], data_w[1]}),
		.CLK(clk),
		.OCE(vcc),
		.CE(vcc),
		.RESET(reset)
	);
	defparam rom2.READ_MODE = 1'b1;
	defparam rom2.BIT_WIDTH = 18;
	defparam rom2.RESET_MODE = "SYNC";
`include "img-rom2.vh"

	pROMX9 rom3(
		.AD({ad[9:0], gnd, gnd, gnd, gnd}),
		.DO({dummy_w[1], data_w[0]}),
		.CLK(clk),
		.OCE(vcc),
		.CE(vcc),
		.RESET(reset)
	);
	defparam rom3.READ_MODE = 1'b1;
	defparam rom3.BIT_WIDTH = 18;
	defparam rom3.RESET_MODE = "SYNC";
`include "img-rom3.vh"

endmodule
module idsp(input wire clk, input wire reset,
	output wire [63:0] product, 
	output wire [63:0] product1, 
	output wire [63:0] product2, 
	output wire [63:0] product3, 
	output wire [63:0] product4
	);

wire [17:0] soa;
wire [17:0] sob;
wire [17:0] soa0;
wire [17:0] sob0;
wire [17:0] soa1;
wire [17:0] sob1;
wire [17:0] soa2;
wire [17:0] sob2;
wire gnd = 1'b0;

wire [54:0]caso;
wire [54:0]caso0;

ALU54D alu0(
	.A(54'hde1ec7ab1e),
	.B(54'hcad),
	.DOUT(product[53:0]),
	.CASI(gnd),
	.CASO(caso),
	.ASIGN(gnd),
	.BSIGN(gnd),
	.ACCLOAD(1'b1),
	.CLK(clk),
	.CE(1'b1),
	.RESET(reset)
);
	defparam alu0.AREG=1'b0;
	defparam alu0.BREG=1'b0;
	defparam alu0.ASIGN_REG=1'b0;
	defparam alu0.BSIGN_REG=1'b0;
	defparam alu0.ACCLOAD_REG=1'b0;
	defparam alu0.OUT_REG=1'b1;
	defparam alu0.B_ADD_SUB=1'b1;
	defparam alu0.C_ADD_SUB=1'b0;
	defparam alu0.ALUD_MODE=2'b0;
	defparam alu0.ALU_RESET_MODE="SYNC";

ALU54D alu1(
	.A(54'h1111),
	.B(54'h2),
	.DOUT(product1[53:0]),
	.CASI(caso),
	.CASO(caso0),
	.ASIGN(gnd),
	.BSIGN(gnd),
	.ACCLOAD(gnd),
	.CLK(clk),
	.CE(1'b1),
	.RESET(reset)
);
	defparam alu1.AREG=1'b1;
	defparam alu1.BREG=1'b0;
	defparam alu1.ASIGN_REG=1'b0;
	defparam alu1.BSIGN_REG=1'b0;
	defparam alu1.ACCLOAD_REG=1'b0;
	defparam alu1.OUT_REG=1'b0;
	defparam alu1.B_ADD_SUB=1'b0;
	defparam alu1.C_ADD_SUB=1'b0;
	defparam alu1.ALUD_MODE=1;
	defparam alu1.ALU_RESET_MODE="SYNC";

ALU54D alu2(
	.A(54'h100000000),
	.B(54'h00000f000),
	.DOUT(product2[53:0]),
	.CASI(caso0),
	.CASO(),
	.ASIGN(gnd),
	.BSIGN(gnd),
	.ACCLOAD(gnd),
	.CLK(clk),
	.CE(1'b1),
	.RESET(reset)
);
	defparam alu2.AREG=1'b1;
	defparam alu2.BREG=1'b1;
	defparam alu2.ASIGN_REG=1'b1;
	defparam alu2.BSIGN_REG=1'b1;
	defparam alu2.ACCLOAD_REG=1'b1;
	defparam alu2.OUT_REG=1'b0;
	defparam alu2.B_ADD_SUB=1'b0;
	defparam alu2.C_ADD_SUB=1'b0;
	defparam alu2.ALUD_MODE=2;
	defparam alu2.ALU_RESET_MODE="SYNC";
endmodule