dakies/OSS_Verilog huggingface dataset:
module sobel_filter
#(
	parameter	VESA_STD	= "VESA_180X720_60FPS",
	parameter	X_START		= 0,
	parameter	Y_START		= 0,
	parameter	X_END		= 640,
	parameter	Y_END		= 720,
	parameter	Y_DEPTH		= 8,
	
	parameter	X_LSB_CNT_WIDTH	= 4,
	parameter	X_MSB_CNT_WIDTH	= 6,
	parameter	Y_LSB_CNT_WIDTH	= 4,
	parameter	Y_MSB_CNT_WIDTH	= 6
)
(
	input	i_arst,
	input	i_pclk,
	
	input	i_vsync,
	input	i_hsync,
	input	i_de,
	input	[Y_DEPTH-1:0]i_y_11_01,
	input	[Y_DEPTH-1:0]i_y_00_01,
	input	[Y_DEPTH-1:0]i_y_01_01,
	
	output	o_x_en,
	output	o_vsync,
	output	o_hsync,
	output	o_de,
	output	[Y_DEPTH-1:0]o_y
);

localparam	HOR_SYNC_POLARITY	= `HOR_SYNC_POLARITY;
localparam	VER_SYNC_POLARITY	= `VER_SYNC_POLARITY;
wire	c_act_vs_por;
wire	c_ina_vs_por;
wire	c_act_hs_por;
wire	c_ina_hs_por;
wire	c_act_de_por;
wire	c_ina_de_por;

reg		r_vsync_1P;
reg		r_de_1P;

wire	w_x_en_1P;
wire	w_hsync_1P;

wire	w_x_en_9P;
wire	w_vsync_9P;
wire	w_hsync_9P;
wire	w_de_9P;
wire	[Y_DEPTH-1:0]w_y_9P;

generate
	if (HOR_SYNC_POLARITY == "NEGATIVE")
	begin
		assign	c_act_hs_por	= 1'b0;
		assign	c_ina_hs_por	= 1'b1;
	end
	else
	begin
		assign	c_act_hs_por	= 1'b1;
		assign	c_ina_hs_por	= 1'b0;
	end
	
	if (VER_SYNC_POLARITY == "NEGATIVE")
	begin
		assign	c_act_vs_por	= 1'b0;
		assign	c_ina_vs_por	= 1'b1;
	end
	else
	begin
		assign	c_act_vs_por	= 1'b1;
		assign	c_ina_vs_por	= 1'b0;
	end
endgenerate

assign	c_act_de_por	= 1'b1;
assign	c_ina_de_por	= 1'b0;

sobel_feldman
//sobel_scharr
#(
	.Y_DEPTH(Y_DEPTH)
)
inst_sobel_pixel
(
	.i_arst			(i_arst),
	.i_pclk			(i_pclk),
	
	.i_pixel_11_01	(i_y_11_01),
	.i_pixel_00_01	(i_y_00_01),
	.i_pixel_01_01	(i_y_01_01),
	
	.o_pixel		(w_y_9P)
);

filter_size
#(
	.VESA_STD	(VESA_STD),
	.X_START	(0),
	.Y_START	(0),
	.X_END		(640),
	.Y_END		(720),
	
	.X_LSB_CNT_WIDTH(4),
	.X_MSB_CNT_WIDTH(6),
	.Y_LSB_CNT_WIDTH(4),
	.Y_MSB_CNT_WIDTH(6)
)
isnt_filter_size
(
	.i_arst		(i_arst),
	.i_pclk		(i_pclk),
	.i_hsync	(i_hsync),
	.o_hsync	(w_hsync_1P),
	.o_x_en		(w_x_en_1P)
);

shift_reg
#(
	.D_WIDTH(4),
	.TAPE(8)
)
inst_shift_reg
(
	.i_arst(i_arst),
	.i_clk(i_pclk),
	
	.i_d({w_x_en_1P, r_vsync_1P, w_hsync_1P, r_de_1P}),
	.o_q({w_x_en_9P, w_vsync_9P, w_hsync_9P, w_de_9P})
);

always@(posedge i_arst or posedge i_pclk)
begin
	if (i_arst)
	begin
		r_vsync_1P	<= c_ina_vs_por;
		r_de_1P		<= c_ina_de_por;
	end
	else
	begin
		r_vsync_1P	<= i_vsync;
		r_de_1P		<= i_de;
	end
end

assign	o_x_en	= w_x_en_9P;
assign	o_vsync	= w_vsync_9P;
assign	o_hsync	= w_hsync_9P;
assign	o_de	= w_de_9P;
assign	o_y		= w_y_9P;

endmodule
module multi_n2_ext2
#(
	parameter	D_WIDTH	= 8
)
(
	input	i_arst,
	input	i_clk,
	
	input	[D_WIDTH-1:0]i_d,
	output	[D_WIDTH+2-1:0]o_q
);

reg		[D_WIDTH+2-1:0]r_q_1P;

wire	[D_WIDTH+2-1:0]w_d_0P;

assign	w_d_0P	= {1'b0, i_d, 1'b0};

always@(posedge i_arst or posedge i_clk)
begin
	if (i_arst)
		r_q_1P	<= {D_WIDTH+2{1'b0}};
	else
		r_q_1P	<= ~w_d_0P+1'b1;
end

assign	o_q	= r_q_1P;

endmodule
module multi_n1_ext5
#(
	parameter	D_WIDTH	= 8
)
(
	input	i_arst,
	input	i_clk,
	
	input	[D_WIDTH-1:0]i_d,
	output	[D_WIDTH+5-1:0]o_q
);

reg		[D_WIDTH+5-1:0]r_q_1P;

wire	[D_WIDTH+5-1:0]w_d_0P;

assign	w_d_0P	= {5'b00000, i_d};

always@(posedge i_arst or posedge i_clk)
begin
	if (i_arst)
		r_q_1P	<= {D_WIDTH+5{1'b0}};
	else
		r_q_1P	<= ~w_d_0P+1'b1;
end

assign	o_q	= r_q_1P;

endmodule
module multi_p2_ext2
#(
	parameter	D_WIDTH	= 8
)
(
	input	i_arst,
	input	i_clk,
	
	input	[D_WIDTH-1:0]i_d,
	output	[D_WIDTH+2-1:0]o_q
);

reg		[D_WIDTH+2-1:0]r_q_1P;

wire	[D_WIDTH+2-1:0]w_d_0P;

assign	w_d_0P	= {1'b0, i_d, 1'b0};

always@(posedge i_arst or posedge i_clk)
begin
	if (i_arst)
		r_q_1P	<= {D_WIDTH+2{1'b0}};
	else
		r_q_1P	<= w_d_0P;
end

assign	o_q	= r_q_1P;

endmodule
module multi_p2_ext5
#(
	parameter	D_WIDTH	= 8
)
(
	input	i_arst,
	input	i_clk,
	
	input	[D_WIDTH-1:0]i_d,
	output	[D_WIDTH+5-1:0]o_q
);

reg		[D_WIDTH+5-1:0]r_q_1P;

wire	[D_WIDTH+5-1:0]w_d_0P;

assign	w_d_0P	= {4'b0, i_d, 1'b0};

always@(posedge i_arst or posedge i_clk)
begin
	if (i_arst)
		r_q_1P	<= {D_WIDTH+5{1'b0}};
	else
		r_q_1P	<= w_d_0P;
end

assign	o_q	= r_q_1P;

endmodule
module multi_p1_ext5
#(
	parameter	D_WIDTH	= 8
)
(
	input	i_arst,
	input	i_clk,
	
	input	[D_WIDTH-1:0]i_d,
	output	[D_WIDTH+5-1:0]o_q
);

reg		[D_WIDTH+5-1:0]r_q_1P;

wire	[D_WIDTH+5-1:0]w_d_0P;

assign	w_d_0P	= {5'b0000, i_d};

always@(posedge i_arst or posedge i_clk)
begin
	if (i_arst)
		r_q_1P	<= {D_WIDTH+5{1'b0}};
	else
		r_q_1P	<= w_d_0P;
end

assign	o_q	= r_q_1P;

endmodule
module sobel_scharr_tb();

localparam	Y_DEPTH	= 8;

reg		r_arst;
reg		r_pclk;

reg		[Y_DEPTH-1:0]r_pixel_11_11;
reg		[Y_DEPTH-1:0]r_pixel_00_11;
reg		[Y_DEPTH-1:0]r_pixel_01_11;

reg		[Y_DEPTH-1:0]r_pixel_11_11_1P;
reg		[Y_DEPTH-1:0]r_pixel_00_11_1P;
reg		[Y_DEPTH-1:0]r_pixel_01_11_1P;

wire	[Y_DEPTH-1:0]w_pixel;

sobel_scharr
#(
	.Y_DEPTH(Y_DEPTH)
)
inst_sobel_scharr
(
	.i_arst(r_arst),
	.i_pclk(r_pclk),
	
	.i_pixel_11_11(r_pixel_11_11_1P),
	.i_pixel_00_11(r_pixel_00_11_1P),
	.i_pixel_01_11(r_pixel_01_11_1P),
	
	.o_pixel(w_pixel)
);

initial
begin
	r_pclk	<= 1'b1;
	forever
		#2.5	r_pclk	<= ~r_pclk;
end

initial
begin
		r_arst			<= 1'b1;
		r_pixel_11_11	<= {Y_DEPTH{1'b0}};
		r_pixel_00_11	<= {Y_DEPTH{1'b0}};
		r_pixel_01_11	<= {Y_DEPTH{1'b0}};
	
	#10	r_arst			<= 1'b0;
		r_pixel_11_11	<= 8'd225;
		r_pixel_00_11	<= 8'd0;
		r_pixel_01_11	<= 8'd76;
		
	#5	r_pixel_11_11	<= 8'd105;
		r_pixel_00_11	<= 8'd255;
		r_pixel_01_11	<= 8'd149;
		
	#5	r_pixel_11_11	<= 8'd178;
		r_pixel_00_11	<= 8'd128;
		r_pixel_01_11	<= 8'd29;
	
	#5	r_pixel_11_11	<= {Y_DEPTH{1'b0}};
		r_pixel_00_11	<= {Y_DEPTH{1'b0}};
		r_pixel_11_11	<= {Y_DEPTH{1'b0}};
end

always@(posedge r_arst or posedge r_pclk)
begin
	if (r_arst)
	begin
		r_pixel_11_11_1P	<= {Y_DEPTH{1'b0}};
		r_pixel_00_11_1P	<= {Y_DEPTH{1'b0}};
		r_pixel_01_11_1P	<= {Y_DEPTH{1'b0}};
	end
	else
	begin
		r_pixel_11_11_1P	<= r_pixel_11_11;
		r_pixel_00_11_1P	<= r_pixel_00_11;
		r_pixel_01_11_1P	<= r_pixel_01_11;
	end
end

endmodule
module sobel_feldman_tb();

localparam	Y_DEPTH	= 8;

reg		r_arst;
reg		r_pclk;

reg		[Y_DEPTH-1:0]r_pixel_11_11;
reg		[Y_DEPTH-1:0]r_pixel_00_11;
reg		[Y_DEPTH-1:0]r_pixel_01_11;

reg		[Y_DEPTH-1:0]r_pixel_11_11_1P;
reg		[Y_DEPTH-1:0]r_pixel_00_11_1P;
reg		[Y_DEPTH-1:0]r_pixel_01_11_1P;

wire	[Y_DEPTH-1:0]w_pixel;

sobel_feldman
#(
	.Y_DEPTH(Y_DEPTH)
)
inst_sobel_pixel
(
	.i_arst(r_arst),
	.i_pclk(r_pclk),
	
	.i_pixel_11_11(r_pixel_11_11_1P),
	.i_pixel_00_11(r_pixel_00_11_1P),
	.i_pixel_01_11(r_pixel_01_11_1P),
	
	.o_pixel(w_pixel)
);

initial
begin
	r_pclk	<= 1'b1;
	forever
		#2.5	r_pclk	<= ~r_pclk;
end

initial
begin
		r_arst			<= 1'b1;
		r_pixel_11_11	<= {Y_DEPTH{1'b0}};
		r_pixel_00_11	<= {Y_DEPTH{1'b0}};
		r_pixel_01_11	<= {Y_DEPTH{1'b0}};
	
	#10	r_arst			<= 1'b0;
		r_pixel_11_11	<= 8'd225;
		r_pixel_00_11	<= 8'd0;
		r_pixel_01_11	<= 8'd76;
		
	#5	r_pixel_11_11	<= 8'd105;
		r_pixel_00_11	<= 8'd255;
		r_pixel_01_11	<= 8'd149;
		
	#5	r_pixel_11_11	<= 8'd178;
		r_pixel_00_11	<= 8'd128;
		r_pixel_01_11	<= 8'd29;
	
	#5	r_pixel_11_11	<= {Y_DEPTH{1'b0}};
		r_pixel_00_11	<= {Y_DEPTH{1'b0}};
		r_pixel_11_11	<= {Y_DEPTH{1'b0}};
end

always@(posedge r_arst or posedge r_pclk)
begin
	if (r_arst)
	begin
		r_pixel_11_11_1P	<= {Y_DEPTH{1'b0}};
		r_pixel_00_11_1P	<= {Y_DEPTH{1'b0}};
		r_pixel_01_11_1P	<= {Y_DEPTH{1'b0}};
	end
	else
	begin
		r_pixel_11_11_1P	<= r_pixel_11_11;
		r_pixel_00_11_1P	<= r_pixel_00_11;
		r_pixel_01_11_1P	<= r_pixel_01_11;
	end
end

endmodule
module apb3_slave #(
	// user parameter starts here
	//
	parameter	ADDR_WIDTH	= 12,
	parameter	DATA_WIDTH	= 31,
	parameter	NUM_REG		= 4
) (
	// user logic starts here
	output [1:0] 			apb3LED,
	output				apb3Interrupt,
	//
	input				clk,
	input				resetn,
	input	[ADDR_WIDTH-1:0]	PADDR,
	input				PSEL,
	input				PENABLE,
	output				PREADY,
	input				PWRITE,
	input 	[DATA_WIDTH-1:0] 	PWDATA,
	output	[DATA_WIDTH-1:0] 	PRDATA,
	output				PSLVERROR

);


///////////////////////////////////////////////////////////////////////////////

localparam [1:0]	IDLE   = 2'b00,
			SETUP  = 2'b01,
			ACCESS = 2'b10;

reg [1:0] 		busState, 
			busNext;
reg [DATA_WIDTH-1:0]	slaveReg [0:NUM_REG-1];
reg [DATA_WIDTH-1:0]	slaveRegOut;
reg			slaveReady;
wire	 		actWrite,
			actRead;
integer			byteIndex;


///////////////////////////////////////////////////////////////////////////////

	always@(posedge clk or negedge resetn)
	begin
		if(!resetn) 
			busState <= IDLE; 
		else
			busState <= busNext; 
	end

	always@(*)
	begin
		busNext = busState;

		case(busState)
			IDLE:
			begin
				if(PSEL && !PENABLE)
					busNext = SETUP;
				else
					busNext = IDLE;
			end
			SETUP:
			begin
				if(PENABLE)
					busNext = ACCESS;
				else
					busNext = IDLE;
			end
			ACCESS:
			begin
				if(PENABLE)
					busNext = ACCESS;
				else
					busNext = IDLE;
			end
			default:
			begin
				busNext = IDLE;
			end
		endcase
	end


	assign actWrite = PWRITE  & (busNext == ACCESS);
	assign actRead  = !PWRITE & (busNext == SETUP);
	assign PSLVERROR = 1'b0; //FIXME
	assign PRDATA = slaveRegOut;
	assign PREADY = slaveReady;

	always@ (posedge clk)
	begin
		slaveReady <= (busState == IDLE);
	end

	always@ (posedge clk or negedge resetn)
	begin
		if(!resetn)
			for(byteIndex = 0; byteIndex < NUM_REG; byteIndex = byteIndex + 1)
			slaveReg[byteIndex] <= {{DATA_WIDTH}{1'b0}};
		else begin
			for(byteIndex = 0; byteIndex < NUM_REG; byteIndex = byteIndex + 1)
			if(actWrite && PADDR[3:0] == (byteIndex*4))
				slaveReg[byteIndex] <= PWDATA;
			else
				slaveReg[byteIndex] <= slaveReg[byteIndex];
				
		end

	end

	always@ (posedge clk or negedge resetn)
	begin
		if(!resetn)
			slaveRegOut <= {{DATA_WIDTH}{1'b0}};
		else begin
			if(actRead)
				slaveRegOut <= slaveReg[PADDR[7:2]];
			else
				slaveRegOut <= slaveRegOut;
				
		end

	end

	//custom logic starts here
	assign apb3LED 		= slaveReg[0][1:0];
	assign apb3Interrupt 	= slaveReg[0][2];
	//
endmodule
module aib_adaptrxdp_map (

input wire  [39:0]  din,
input wire  [79:0]  rx_fifo_data_out,      // Data from rx fifo

input wire         rx_aib_transfer_clk,
input wire         rx_aib_transfer_rst_n,
input wire         rx_clock_fifo_rd_clk,
input wire         rx_reset_fifo_rd_rst_n,

output reg  [79:0]   r_fifo_dout,
output reg  [39:0]   reg_dout

);


always @(posedge rx_clock_fifo_rd_clk or negedge rx_reset_fifo_rd_rst_n) begin
   if (!rx_reset_fifo_rd_rst_n) 
     begin
      r_fifo_dout[79:0] <= {80{1'b0}};
     end
   else begin
       r_fifo_dout[79:0] <= rx_fifo_data_out[79:0];
   end
end


always @(posedge rx_aib_transfer_clk or negedge rx_aib_transfer_rst_n) begin
   if (!rx_aib_transfer_rst_n) 
    begin
     reg_dout[39:0] <= {40{1'b0}};
    end
   else begin
       reg_dout[39:0] <= din[39:0];
   end
end


endmodule
module aib_adapttxdp_fifo_ram
  #(
    parameter DWIDTH = 'd40,             // FIFO Input data width 
    parameter DEPTH  = 'd16              // FIFO Depth 
    )
(
    input  wire              r_double_write,	// Write to 2 consecutive locations
    input  wire		     r_stop_write, // Disable/enable writing when FIFO is full    
    input  wire		     wr_full,
    input  wire              wr_clk,     // Write Domain Clock
    input  wire		     wr_rst_n,   // Write Domain Reset 
    input  wire              wr_en,      // Write Data Enable
    input  wire [DEPTH-1:0] wr_ptr,     // Write Pointer
    input  wire [DWIDTH-1:0] wr_data,    // Write Data In
    input  wire [DWIDTH-1:0] wr_data2,    // Write Data In
    input  wire [DEPTH-1:0] rd_ptr,     // Read Pointer
    output reg  [DWIDTH-1:0] rd_data   // Read Data

);

   //********************************************************************
   // Infer Memory or use Dual Port Memory from Quartus/ASIC Memory
   //********************************************************************
   
   integer		m;
   integer		i;
//   reg [DWIDTH-1:0]          fifo_mem [((1<<AWIDTH)-1):0];
   reg [DWIDTH-1:0]          fifo_mem [DEPTH-1:0];
   
   always @(negedge wr_rst_n or posedge wr_clk) begin
      if (~wr_rst_n) begin
         for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1)
            fifo_mem[m] <= 'd0;	
      end 
      else if (wr_en && (~wr_full||~r_stop_write)) begin
         for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1) begin
           if (wr_ptr[m]) begin
             fifo_mem[m] <= wr_data;
             if (r_double_write & m < DEPTH-1) // In double write mode, wr_ptr always increments by 2
               fifo_mem[m+1] <= wr_data2;
             end  
         end   
      end
   end
   
// assign rd_data = fifo_mem[rd_ptr];
// Read ptr must be one-hot
always @ *
begin: data_out 
  rd_data = fifo_mem[0];
  for (i='d0; i<=(DEPTH-1'b1); i=i+1'b1) begin
    if (rd_ptr[i]) begin
      rd_data = fifo_mem[i];
    end       
  end   
end 

endmodule
module aib_adapttxdp_reg (
  input wire         tx_clock_fifo_rd_clk,
  input wire         tx_reset_fifo_rd_rst_n,
  input wire [1:0]   r_tx_fifo_mode,
  input wire [39:0]  data_in,
  
  output reg [39:0] reg_dout
);

always @(posedge tx_clock_fifo_rd_clk or negedge tx_reset_fifo_rd_rst_n) begin
   if (!tx_reset_fifo_rd_rst_n) 
     reg_dout <= {40{1'b0}};
   else if (r_tx_fifo_mode[1:0] == 2'b11) begin
       reg_dout[39:0] <= data_in[39:0];
   end
end

endmodule
module aib_adapt_cmn_pulse_stretch 
  #(
    parameter RESET_VAL = 'd0   // reset value
    )
  (
    input  wire         clk,         // clock
    input  wire         rst_n,       // async reset
    input  wire [2:0]   num_stages,  // number of stages required
    input  wire         data_in,     // data in
    output  reg         data_out     // stretched data out             
   );

   reg                  data_d1, data_d2, data_d3, data_d4;
   reg                  data_d5, data_d6, data_d7;
   reg                  data_out_comb;

   localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0;  // To eliminate truncating warning
      
   always @* begin
      data_out_comb = data_in;
      
      case (num_stages)
        3'b000: data_out_comb = data_in;
        3'b001: data_out_comb = data_d1 | data_in;
        3'b010: data_out_comb = data_d2 | data_d1 | data_in;
        3'b011: data_out_comb = data_d3 | data_d2 | data_d1 | data_in;
        3'b100: data_out_comb = data_d4 | data_d3 | data_d2 | data_d1 | data_in;
        3'b101: data_out_comb = data_d5 | data_d4 | data_d3 | data_d2 | data_d1 | data_in;
        3'b110: data_out_comb = data_d6 | data_d5 | data_d4 | data_d3 | data_d2 | data_d1 | data_in;
        3'b111: data_out_comb = data_d7 | data_d6 | data_d5 | data_d4 | data_d3 | data_d2 | data_d1 | data_in;
        default: data_out_comb = data_in;
      endcase // case(num_stages)
   end // always @ *

   always @(negedge rst_n or posedge clk) begin
      if (~rst_n) begin
         data_d1 <= reset_value;
         data_d2 <= reset_value;
         data_d3 <= reset_value;
         data_d4 <= reset_value;
         data_d5 <= reset_value;
         data_d6 <= reset_value;
         data_d7 <= reset_value;
         data_out <= reset_value;
      end
      else begin
         data_d1 <= data_in;
         data_d2 <= data_d1;
         data_d3 <= data_d2;
         data_d4 <= data_d3;
         data_d5 <= data_d4;
         data_d6 <= data_d5;
         data_d7 <= data_d6;
         data_out <= data_out_comb;
      end
   end // always @ (negedge rst_n or posedge clk)
      
endmodule
module aib_rstnsync
  (
    input wire 	clk,		// Destination clock of reset to be synced
    input wire 	i_rst_n,        // Asynchronous reset input
    input wire	scan_mode,	// Scan bypass for reset
    output wire sync_rst_n	// Synchronized reset output
   
   );

   reg	first_stg_rst_n;					     
   wire prescan_sync_rst_n;
   
   always @(posedge clk or negedge i_rst_n)
     if (!i_rst_n)
       first_stg_rst_n <= 1'b0;
     else
       first_stg_rst_n <= 1'b1;

       c3lib_bitsync
       #(
       .SRC_DATA_FREQ_MHZ (200),        
       .DST_CLK_FREQ_MHZ  (1000),        
       .DWIDTH            (1),   
       .RESET_VAL         (0)           
       )
   i_sync_rst_n
     (
      .clk           (clk               ),
      .rst_n         (i_rst_n           ), 
      .data_in       (first_stg_rst_n   ),
      .data_out      (prescan_sync_rst_n) 
      );

    assign sync_rst_n = scan_mode ? i_rst_n : prescan_sync_rst_n;

      
   endmodule
module aib_adaptrxdp_word_align 
  #(
    parameter DWIDTH = 'd40             // FIFO Input data width 
    )
    (
    input  wire               wr_clk,      	  // clock
    input  wire               wr_rst_n,       	  // async reset
    input  wire               r_wa_en,            // Word-align enable  
    input  wire [DWIDTH-1:0]  aib_hssi_rx_data_in,    // Write Data In
    output wire		      wa_lock,		  // Go to FIFO, status reg
    output wire [19:0]	      word_align_testbus
    );
    

reg		        wm_bit;
reg		        wm_bit_d1;
reg		        wm_bit_d2;
reg		        wm_bit_d3;
reg		        wm_bit_d4;
reg		        wm_bit_d5;
reg			wa_lock_lt;
wire			wa_lock_int;
//********************************************************************
// Main logic 
//********************************************************************



//Word-align
always @(negedge wr_rst_n or posedge wr_clk) begin
   if (wr_rst_n == 1'b0) begin
     wm_bit 	 <= 1'b0;
     wm_bit_d1 <= 1'b0;
     wm_bit_d2 <= 1'b0;
     wm_bit_d3 <= 1'b0;
     wm_bit_d4 <= 1'b0;
     wm_bit_d5 <= 1'b0;
   end
   else begin
     wm_bit 	 <= aib_hssi_rx_data_in[39];
     wm_bit_d1 <= wm_bit;
     wm_bit_d2 <= wm_bit_d1;
     wm_bit_d3 <= wm_bit_d2;
     wm_bit_d4 <= wm_bit_d3;
     wm_bit_d5 <= wm_bit_d4;
   end
end

always @(negedge wr_rst_n or posedge wr_clk) begin
   if (wr_rst_n == 1'b0) begin
     wa_lock_lt 	 <= 1'b0;
   end
   else begin
     wa_lock_lt 	 <= wa_lock_int || wa_lock_lt;
   end
end

assign wa_lock_int = wm_bit && ~wm_bit_d1 && wm_bit_d2 && ~wm_bit_d3 && wm_bit_d4 && ~wm_bit_d5 || ~r_wa_en;

assign wa_lock = wa_lock_int || wa_lock_lt;



assign word_align_testbus = {13'd0, wa_lock, wm_bit, wm_bit_d1, wm_bit_d2, wm_bit_d3, wm_bit_d4, wm_bit_d5};
  
endmodule
module aib_adaptrxdp_fifo_ram
  #(
    parameter DWIDTH = 'd40,             // FIFO Input data width 
    parameter DEPTH  = 'd16              // FIFO Depth 
    )
(
    input  wire		     r_stop_write, // Disable/enable writing when FIFO is full    
    input  wire              wr_clk,     // Write Domain Clock
    input  wire		     wr_rst_n,   // Write Domain Reset 
    input  wire		     wr_full,
    input  wire              wr_en,      // Write Data Enable
    input  wire [DEPTH-1:0] wr_ptr,     // Write Pointer
    input  wire [DWIDTH-1:0] wr_data,    // Write Data In
    input  wire [DEPTH-1:0] rd_ptr,     // Read Pointer
    output reg  [DWIDTH-1:0] rd_data,   // Read Data
    output reg  [DWIDTH-1:0] rd_data2    // Read Data

);

   //********************************************************************
   // Infer Memory or use Dual Port Memory from Quartus/ASIC Memory
   //********************************************************************

   wire 	[DEPTH-1:0]	rd_ptr2;   
   integer		m;
   integer		i, j;
//   reg [DWIDTH-1:0]          fifo_mem [((1<<AWIDTH)-1):0];
   reg [DWIDTH-1:0]          fifo_mem [DEPTH-1:0];
   
   always @(negedge wr_rst_n or posedge wr_clk) begin
      if (~wr_rst_n) begin
         for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1)
            fifo_mem[m] <= 'd0;	
      end 
      else if (wr_en &&  (~wr_full||~r_stop_write)) begin
         for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1) begin
           if (wr_ptr[m]) begin
             fifo_mem[m] <= wr_data;
             end  
         end   
      end
   end

   assign rd_ptr2 = {rd_ptr[DEPTH-2:0], rd_ptr[DEPTH-1]};   
   
   always @ *
   begin: data_out 
     rd_data = fifo_mem[0];
     for (i='d0; i<=(DEPTH-1'b1); i=i+1'b1) begin
       if (rd_ptr[i]) begin
         rd_data = fifo_mem[i];
       end       
     end   
      end 
      
      always @ *
      begin: data_out2 
        rd_data2 = fifo_mem[0];
     for (j='d0; j<=(DEPTH-1'b1); j=j+1'b1) begin
          if (rd_ptr2[j]) begin
            rd_data2 = fifo_mem[j];
       end       
     end   
   end 
   
endmodule
module aibndaux_top_slave (  o_crdet, u_crdet, u_crdet_r, u_dn_por, u_dn_por_r, i_dn_por, i_crdet_ovrd);

output o_crdet;

inout u_crdet, u_crdet_r, u_dn_por, u_dn_por_r;

input  i_dn_por, i_crdet_ovrd;

wire o_crete_detect;
assign vccl_aibndaux = 1'b1;
assign vssl_aibndaux = 1'b0;
assign o_crdet = o_crete_detect | i_crdet_ovrd; 

aibndaux_aliasd aliasd2 ( .PLUS(u_dn_por), .MINUS(u_dn_por_r));
aibndaux_pasred_simple xpasred ( .crete_detect(o_crete_detect),
                                 .iopad_crdet(u_crdet), 
                                 .vssl_aibndaux(vssl_aibndaux),
                                 .vccl_aibndaux(vccl_aibndaux), 
                                 .iopad_dn_por(u_dn_por),
                                 .dn_por(i_dn_por)
     );
endmodule
module aibndaux_aliasd ( PLUS, MINUS );

	input   PLUS;
	output  MINUS;

	assign MINUS = PLUS;

endmodule
module aib_dlycell_dll_comb_inv_1__w_sup(
    input  wire in,
    output wire out,
    inout  wire VDD,
    inout  wire VSS
);

parameter DELAY = 0;

assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in );

endmodule
module aib_dlycell_dll_comb_nand_1__w_sup(
    input  wire [1:0] in,
    output wire out,
    inout  wire VDD,
    inout  wire VSS
);

parameter DELAY = 0;

assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~&in );

endmodule
module aib_dlycell_dll_comb_aib_dlycell_core_1__w_sup(
    input  wire bk1,
    input  wire ci_p,
    input  wire in_p,
    output wire co_p,
    output wire out_p,
    inout  wire VDD,
    inout  wire VSS
);

wire sr0_o;
wire sr1_o;

aib_dlycell_dll_comb_nand_1__w_sup XNAND_SR0 (
    .in( {sr1_o,bk1} ),
    .out( sr0_o ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dlycell_dll_comb_nand_1__w_sup XNAND_SR1 (
    .in( {sr0_o,in_p} ),
    .out( sr1_o ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dlycell_dll_comb_nand_1__w_sup XNAND_in (
    .in( {bk1,in_p} ),
    .out( co_p ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dlycell_dll_comb_nand_1__w_sup XNAND_out (
    .in( {sr1_o,ci_p} ),
    .out( out_p ),
    .VDD( VDD ),
    .VSS( VSS )
);

endmodule
module aibcr3_dlycell_dll_comb__w_sup(
    input  wire bk,
    input  wire ci_p,
    input  wire in_p,
    output wire co_p,
    output wire out_p,
    inout  wire VDD,
    inout  wire VSS
);

wire bk1;
wire bk_mid;
wire mid_in;
wire mid_out;

aib_dlycell_dll_comb_inv_1__w_sup XBKInv0 (
    .in( bk ),
    .out( bk_mid ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dlycell_dll_comb_inv_1__w_sup XBKInv1 (
    .in( bk_mid ),
    .out( bk1 ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dlycell_dll_comb_aib_dlycell_core_1__w_sup XCore_1 (
    .bk1( bk1 ),
    .ci_p( mid_out ),
    .in_p( in_p ),
    .co_p( mid_in ),
    .out_p( out_p ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dlycell_dll_comb_aib_dlycell_core_1__w_sup XCore_0 (
    .bk1( bk1 ),
    .ci_p( ci_p ),
    .in_p( mid_in ),
    .co_p( co_p ),
    .out_p( mid_out ),
    .VDD( VDD ),
    .VSS( VSS )
);

endmodule
module aibcr3_dlycell_dll_comb(
    input  wire bk,
    input  wire ci_p,
    input  wire in_p,
    output wire co_p,
    output wire out_p
);

wire VDD_val;
wire VSS_val;

wire out_p_int;

assign VDD_val = 1'b1;
assign VSS_val = 1'b0;

aibcr3_dlycell_dll_comb__w_sup XDUT (
    .bk( bk ),
    .ci_p( ci_p ),
    .in_p( in_p ),
    .co_p( co_p ),
    .out_p( out_p_int ),
    .VDD( VDD_val ),
    .VSS( VSS_val )
);

// from tttt_25_0p850_0p970
assign #(20, 24) out_p = out_p_int;

endmodule
module aib_dcc_dlyline64_inv_1__w_sup(
    input  wire in,
    output wire out,
    inout  wire VDD,
    inout  wire VSS
);

parameter DELAY = 0;

assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in );

endmodule
module aib_dcc_dlyline64_nand_2__w_sup(
    input  wire [1:0] in,
    output wire out,
    inout  wire VDD,
    inout  wire VSS
);

parameter DELAY = 20;

assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~&in );

endmodule
module aib_dcc_dlyline64_nand_3__w_sup(
    input  wire [1:0] in,
    output wire out,
    inout  wire VDD,
    inout  wire VSS
);

parameter DELAY = 20;

assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~&in );

endmodule
module aib_dcc_dlyline64_aib_dlycell_core_1__w_sup(
    input  wire bk1,
    input  wire ci_p,
    input  wire in_p,
    output wire co_p,
    output wire out_p,
    inout  wire VDD,
    inout  wire VSS
);

wire sr0_o;
wire sr1_o;

aib_dcc_dlyline64_nand_2__w_sup XNAND_SR0 (
    .in( {sr1_o,bk1} ),
    .out( sr0_o ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dcc_dlyline64_nand_2__w_sup XNAND_SR1 (
    .in( {sr0_o,in_p} ),
    .out( sr1_o ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dcc_dlyline64_nand_3__w_sup XNAND_in (
    .in( {bk1,in_p} ),
    .out( co_p ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dcc_dlyline64_nand_3__w_sup XNAND_out (
    .in( {sr1_o,ci_p} ),
    .out( out_p ),
    .VDD( VDD ),
    .VSS( VSS )
);

endmodule
module aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup(
    input  wire bk,
    input  wire ci_p,
    input  wire in_p,
    output wire co_p,
    output wire out_p,
    inout  wire VDD,
    inout  wire VSS
);

wire bk1;
wire bk_mid;

aib_dcc_dlyline64_inv_1__w_sup XBKInv0 (
    .in( bk ),
    .out( bk_mid ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dcc_dlyline64_inv_1__w_sup XBKInv1 (
    .in( bk_mid ),
    .out( bk1 ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dcc_dlyline64_aib_dlycell_core_1__w_sup XCore (
    .bk1( bk1 ),
    .ci_p( ci_p ),
    .in_p( in_p ),
    .co_p( co_p ),
    .out_p( out_p ),
    .VDD( VDD ),
    .VSS( VSS )
);

endmodule
module aib_dcc_dlyline64_aib_dlycell_no_flop_3__w_sup(
    input  wire bk,
    input  wire ci_p,
    input  wire in_p,
    output wire co_p,
    output wire out_p,
    inout  wire VDD,
    inout  wire VSS
);

wire bk1;
wire bk_mid;

aib_dcc_dlyline64_inv_1__w_sup XBKInv0 (
    .in( bk ),
    .out( bk_mid ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dcc_dlyline64_inv_1__w_sup XBKInv1 (
    .in( bk_mid ),
    .out( bk1 ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dcc_dlyline64_aib_dlycell_core_1__w_sup XCore (
    .bk1( bk1 ),
    .ci_p( ci_p ),
    .in_p( in_p ),
    .co_p( co_p ),
    .out_p( out_p ),
    .VDD( VDD ),
    .VSS( VSS )
);

endmodule
module aibcr3_dcc_dlyline64(
    input  wire b63,
    input  wire [63:0] bk,
    input  wire dlyin,
    output wire a63,
    output wire dlyout
);

wire VDD_val;
wire VSS_val;

assign VDD_val = 1'b1;
assign VSS_val = 1'b0;

aibcr3_dcc_dlyline64__w_sup XDUT (
    .b63( b63 ),
    .bk( bk ),
    .dlyin( dlyin ),
    .a63( a63 ),
    .dlyout( dlyout ),
    .VDD( VDD_val ),
    .VSS( VSS_val )
);

endmodule
module aib_dlycell_dcc_inv_1__w_sup(
    input  wire in,
    output wire out,
    inout  wire VDD,
    inout  wire VSS
);

parameter DELAY = 0;

assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in );

endmodule
module aib_dlycell_dcc_nand_2__w_sup(
    input  wire [1:0] in,
    output wire out,
    inout  wire VDD,
    inout  wire VSS
);

parameter DELAY = 0;

assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~&in );

endmodule
module aib_dlycell_dcc_nand_3__w_sup(
    input  wire [1:0] in,
    output wire out,
    inout  wire VDD,
    inout  wire VSS
);

parameter DELAY = 0;

assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~&in );

endmodule
module aib_dlycell_dcc_aib_dlycell_core_1__w_sup(
    input  wire bk1,
    input  wire ci_p,
    input  wire in_p,
    output wire co_p,
    output wire out_p,
    inout  wire VDD,
    inout  wire VSS
);

wire sr0_o;
wire sr1_o;

aib_dlycell_dcc_nand_2__w_sup XNAND_SR0 (
    .in( {sr1_o,bk1} ),
    .out( sr0_o ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dlycell_dcc_nand_2__w_sup XNAND_SR1 (
    .in( {sr0_o,in_p} ),
    .out( sr1_o ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dlycell_dcc_nand_3__w_sup XNAND_in (
    .in( {bk1,in_p} ),
    .out( co_p ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dlycell_dcc_nand_3__w_sup XNAND_out (
    .in( {sr1_o,ci_p} ),
    .out( out_p ),
    .VDD( VDD ),
    .VSS( VSS )
);

endmodule
module aibcr3_dlycell_dcc__w_sup(
    input  wire bk,
    input  wire ci_p,
    input  wire in_p,
    output wire co_p,
    output wire out_p,
    inout  wire VDD,
    inout  wire VSS
);

wire bk1;
wire bk_mid;

aib_dlycell_dcc_inv_1__w_sup XBKInv0 (
    .in( bk ),
    .out( bk_mid ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dlycell_dcc_inv_1__w_sup XBKInv1 (
    .in( bk_mid ),
    .out( bk1 ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dlycell_dcc_aib_dlycell_core_1__w_sup XCore (
    .bk1( bk1 ),
    .ci_p( ci_p ),
    .in_p( in_p ),
    .co_p( co_p ),
    .out_p( out_p ),
    .VDD( VDD ),
    .VSS( VSS )
);

endmodule
module aibcr3_dlycell_dcc(
    input  wire bk,
    input  wire ci_p,
    input  wire in_p,
    output wire co_p,
    output wire out_p
);

wire VDD_val;
wire VSS_val;

wire out_p_int;

assign VDD_val = 1'b1;
assign VSS_val = 1'b0;

aibcr3_dlycell_dcc__w_sup XDUT (
    .bk( bk ),
    .ci_p( ci_p ),
    .in_p( in_p ),
    .co_p( co_p ),
    .out_p( out_p_int ),
    .VDD( VDD_val ),
    .VSS( VSS_val )
);

// from tttt_25_0p850_0p970
assign #(20, 24) out_p = out_p_int;

endmodule
module aibcr3_dcc_phasedet_single (
        output wire     t_down, 
        output wire     t_up, 
        input wire      CLKA, 
        input wire      CLKB,
        input wire      RSTb
    );


    aibcr3_dcc_phasedet phasedet (
        .t_down (),
        .t_up   (t_up),
        .CLKA   (CLKA),
        .CLKB   (CLKB),
        .RSTb   (RSTb)
    );

    assign t_down = !t_up;

endmodule
module aibcr3_buffx1 ( oclk, oclkb, oclkn, odat0, odat1, odat_async,
     pd_data, iopad, async_dat, clkdr, iclkin_dist,
     iclkn, idat0, idat1, idataselb, iddren, ilaunch_clk, ilpbk_dat,
     ilpbk_en, indrv, ipadrstb, ipdrv, irstb, irxen, istrbclk, itxen,
     por_aib_vcc1, por_aib_vcchssi, test_weakpd, test_weakpu,
     testmode_en);

output  oclk, oclkb, oclkn, odat0, odat1, odat_async, pd_data;

inout  iopad;

input  async_dat, clkdr, iclkin_dist, iclkn, idat0, idat1, idataselb,
     iddren, ilaunch_clk, ilpbk_dat, ilpbk_en, ipadrstb, irstb,
     istrbclk, itxen, por_aib_vcc1, por_aib_vcchssi, test_weakpd,
     test_weakpu, testmode_en;

input [1:0]  ipdrv;
input [1:0]  indrv;
input [2:0]  irxen;

// Buses in the design

wire  [1:0]  ipdrv_buf;

wire  [1:0]  indrv_buf;


aibcr3_analog x0 ( oclkb, oclk, rx_idat, odat_async, 
     iopad, oclkn, clkbuf_en, datbuf_en, iclkn, indrv_buf[1:0],
     ipdrv_buf[1:0], itx_en_buf, por_aib_vcc1, por_aib_vcchssi, tx_dat,
     weak_pulldownen, weak_pullupenb);
aibcr3_digital x1 ( clkbuf_en, datbuf_en, indrv_buf[1:0],
     ipdrv_buf[1:0], itx_en_buf, odat0, odat1, pd_data, net18, net17,
     net16, tx_dat, weak_pulldownen, weak_pullupenb, 
     async_dat, clkdr, iclkin_dist, idat0, idat1, idataselb, iddren,
     ilaunch_clk, ilpbk_dat, ilpbk_en, indrv[1:0], ipadrstb,
     ipdrv[1:0], irstb, irxen[2:0], istrbclk, itxen, rx_idat,
     test_weakpd, test_weakpu, testmode_en);


endmodule
module aibcr3_dcc_crsdlyline ( SOOUT, bk, crsDLY, CLK,
     CLKIN, PDb, SE, SI, gry );

output  SOOUT, crsDLY;

input  CLK, CLKIN, PDb, SE, SI;

output [255:0]  bk;

input [10:3]  gry;

// Buses in the design

wire  [0:4]  net0118;

wire  [0:5]  net0119;

wire  [0:4]  net0120;

wire  [6:0]  cgry;

wire  [6:0]  bgry;

wire  [6:0]  dgry;

wire  [6:0]  agry;

wire         gry9b;
wire         gry10b;
wire	     SO_crc;
wire         net082;
wire         net096;
wire         net0108;

// scan out pin
assign SOOUT = SO_crc;

// 4x delay line, each containing 64 delay cells
aibcr3_dcc_dlyline64 I10 ( .a63(net14),  .dlyout(net18), .b63(net14),  .bk(bk[255:192]), .dlyin(net15));
aibcr3_dcc_dlyline64 I9  ( .a63(net15), .dlyout(net17), .b63(net18),  .bk(bk[191:128]), .dlyin(net16));
aibcr3_dcc_dlyline64 I1  ( .a63(net16), .dlyout(dly64), .b63(net17),  .bk(bk[127:64]), .dlyin(clk64));
aibcr3_dcc_dlyline64 I8  ( .a63(clk64), .dlyout(crsDLY), .b63(dly64), .bk(bk[63:0]),
.dlyin(CLK));

// 4x gray to thermometer code conversion
aibcr3_dcc_gry2thm64 I6 ( net097, bk[63:0], net0128, RSTb,
     agry[6:0], SE, SI);
aibcr3_dcc_gry2thm64 I5 ( net0101, bk[127:64], net0126,
     RSTb, bgry[6:0], SE, net097);
aibcr3_dcc_gry2thm64 I3 ( net0103, bk[191:128], net0124,
     RSTb, cgry[6:0], SE, net0101);
aibcr3_dcc_gry2thm64 I15 ( SO_crc, bk[255:192], net0122,
     RSTb, dgry[6:0], SE, net0103);

// combinatorial logic
assign agry[5:0] = gry[8:3];
assign ENDbar = ~cgry[6];
assign ENCbar = ~bgry[6];
assign agry[6] = ~(gry9b & gry10b);
assign ENBbar = ~agry[6];
//assign tie_HI = 1'b1;
assign net0122 = CLKIN;
assign net0124 = CLKIN;
assign net0128 = CLKIN;
assign net0126 = CLKIN;
assign RSTb    = PDb;
assign bgry[5] = ~(gry[8] | ENBbar);
assign dgry[4:0] = ~(net0120[0:4] | {ENDbar,ENDbar,ENDbar,ENDbar,ENDbar} );
assign dgry[5] = ~(gry[8] | ENDbar);
assign cgry[5:0] = ~(net0119[0:5] | {ENCbar,ENCbar,ENCbar,ENCbar,ENCbar,ENCbar});
assign bgry[4:0] = ~(net0118[0:4] | {ENBbar,ENBbar,ENBbar,ENBbar,ENBbar});
assign gry9b = ~gry[9];
assign gry10b = ~gry[10];
assign net0120[0:4] = ~gry[7:3];
assign net082 = ~( gry[3] | gry[4] | gry[5] );
assign net0108 = ~( gry[6] | gry[7] | gry[8] );
assign net096 = ~( net082 & net0108 );
assign dgry[6] = ~( net096 | gry[9] | gry10b );
assign net0119[0:5] = ~gry[8:3];
assign bgry[6] = gry[10];
assign cgry[6] = ~ ( gry[9] | gry10b );
assign net0118[0:4] = ~gry[7:3];


endmodule
module aibcr3_digital ( clkbuf_en, datbuf_en, indrv_buf, ipdrv_buf,
     itx_en_buf, odat0, odat1, pd_dataout, rx_disable, sync_datbuf_en0,
     sync_datbuf_en1, tx_dat, weak_pulldownen, weak_pullupenb, 
      async_data, clkdr, iclkin_dist, idat0, idat1,
     idataselb, iddrctrl, ilaunch_clk, ilpbk_dat, ilpbk_en, indrv,
     ipadrstb, ipdrv, irstb, irxen, istrbclk, itx_en, rx_idat,
     test_weakpd, test_weakpu, testmode_en 
);

output  clkbuf_en, datbuf_en, itx_en_buf, odat0, odat1, pd_dataout,
     rx_disable, sync_datbuf_en0, sync_datbuf_en1, tx_dat,
     weak_pulldownen, weak_pullupenb;


input  async_data, clkdr, iclkin_dist, idat0, idat1, idataselb,
     iddrctrl, ilaunch_clk, ilpbk_dat, ilpbk_en, ipadrstb, irstb,
     istrbclk, itx_en, rx_idat, test_weakpd, test_weakpu, testmode_en;


output [1:0]  ipdrv_buf;
output [1:0]  indrv_buf;

input [1:0]  ipdrv;
input [1:0]  indrv;
input [2:0]  irxen;

wire rx_idat_buf_nc;

assign pd_dataout = 1'b0;

aibcr3_rxdig x3 ( clkbuf_en, datbuf_en, odat0, odat1, rx_disable,
     rx_idat_buf_nc, sync_datbuf_en0, sync_datbuf_en1,
     iclkin_dist, ipadrstb, irstb, irxen[2:0], istrbclk, rx_idat);
aibcr3_txdig x1 ( indrv_buf[1:0], ipdrv_buf[1:0], itx_en_buf, tx_dat,
     weak_pulldownen, weak_pullupenb, async_data, clkdr,
     idat0, idat1, idataselb, iddrctrl, ilaunch_clk, ilpbk_dat,
     ilpbk_en, indrv[1:0], ipadrstb, ipdrv[1:0], irstb, itx_en,
     rx_disable, test_weakpd, test_weakpu, testmode_en);

endmodule
module aibcr3_latch (
	input wire E,
	input wire CDN,
	input wire D,
	output reg Q
);

wire latch_reset;
assign latch_reset = !CDN;

//cadence async_set_reset "latch_reset"
//synopsys async_set_reset "latch_reset"
always@(*) begin
	if (latch_reset) Q <= 0;
	else if (E) Q <= D;
end
endmodule
module aibcr3_txdig ( indrv_buf, ipdrv_buf, itx_en_buf, tx_dat_out,
     weak_pulldownen, weak_pullupenb, async_data, clkdr,
     idat0, idat1, idataselb, iddrctrl, ilaunch_clk, ilpbk_dat,
     ilpbk_en, indrv, ipadrstb, ipdrv, irstb, itx_en, rx_enb,
     test_weakpd, test_weakpu, testmode_en );

output wire itx_en_buf, tx_dat_out, weak_pulldownen, weak_pullupenb;


input wire async_data, clkdr, idat0, idat1, idataselb, iddrctrl,
     ilaunch_clk, ilpbk_dat, ilpbk_en, ipadrstb, irstb, itx_en, rx_enb,
     test_weakpd, test_weakpu, testmode_en;

output wire [1:0]  indrv_buf;
output wire [1:0]  ipdrv_buf;

input wire [1:0]  indrv;
input wire [1:0]  ipdrv;

wire mux_din;
wire net036;
wire itx_enb;
wire ff1_dout;
wire ff0_dout;
wire clk;
wire ff1_latch_dout_buf2;
wire ff0_dout_buf2;
wire async_dat_buf;
wire ipadrstb_buf;
wire weak_pulld_enb;
wire test_weakpu_buf;
wire test_weakpd_buf;
wire ff1_latch_buf1;
wire ff1_latch_dout;
wire anlg_rst_nd_out;
wire io_disable_b;

// Missing wire declarations
wire mux_out;
wire txenb_rxenb;
wire ff1_hold_buf0;
wire ff1_hold_buf1;
wire ff0_hold_buf1;
wire ff0_dout_buf1;
wire irstb_buf;
wire din0;
wire din1;
wire clkb;
wire ff1_latch_input;


assign txenb_rxenb = ~net036;
assign itx_en_buf = ~itx_enb;
assign ff1_hold_buf0 = iddrctrl ? ff1_dout : ff0_dout;
//assign mux_din = idataselb ? mux_out : async_dat_buf;
assign net036 = ~(rx_enb & itx_enb);
assign weak_pulldownen = ~(ipadrstb_buf & weak_pulld_enb);
assign weak_pullupenb = ~ (ipadrstb_buf & test_weakpu_buf);
assign itx_enb = ~(itx_en & ipadrstb);
assign weak_pulld_enb = ~(test_weakpd_buf | txenb_rxenb);
assign test_weakpu_buf = test_weakpu;
assign test_weakpd_buf = test_weakpd;
assign ipadrstb_buf = ipadrstb;
assign ipdrv_buf[1] = ipdrv[1];
assign ipdrv_buf[0] = ipdrv[0];
assign indrv_buf[1] = indrv[1];
assign indrv_buf[0] = indrv[0];
assign ff1_hold_buf1 = ff1_hold_buf0;
assign ff0_dout_buf1 = ff0_dout;
assign ff0_dout_buf2 = ff0_dout_buf1;
assign irstb_buf = irstb;
assign async_dat_buf = async_data;
assign tx_dat_out = mux_din;
assign din0 = idat0;
assign din1 = idat1;
assign clkb = ~clk;
assign clk = ilaunch_clk;
assign ff1_latch_dout_buf2 = ff1_latch_buf1;
assign ff1_latch_buf1 = ff1_latch_dout;
assign ff1_latch_input = ff1_hold_buf1;

/* replaced by latch
aibcr3_ulvt16_dffcdn_cust x29 ( ff1_latch_dout, irstb_buf,
     clkb, ff1_latch_input); 
*/
aibcr3_latch x29 (.Q(ff1_latch_dout), .E(clkb), .CDN(irstb_buf), .D(ff1_latch_input));

aibcr3_ulvt16_dffcdn_cust x25 ( .Q(ff1_dout), .CDN(irstb_buf), .CK(clk),
     .D(din1));
aibcr3_ulvt16_dffcdn_cust x18 ( .Q(ff0_dout), .CDN(irstb_buf), .CK(clk),
     .D(din0));

aibcr3_bypmux bypmux(
        .out    (mux_din),
        .byp    (idataselb),
        .in1    (mux_out),
        .in0    (async_dat_buf));

aibcr3_ddrmux ddrmux(
        .out    (mux_out), 
        .clk    (clk), 
        .in0    (ff0_dout_buf2),
        .in1    (ff1_latch_dout_buf2));

endmodule
module aibcr3aux_top_master  
   (
    output wire  o_por_vcchssi,
    output wire  o_por_vccl,
    output wire  osc_clkout,
    inout  wire  device_detect, //Shrink aux74/75 due to limit microbump/C4 bump pin
    inout  wire  por,   //Shrink aux85/87 pin due to limit microbump/C4 bump pin
    input        m_por_ovrd, 
    input        i_osc_clk 
     ); 
     
`ifdef LEVEL_SHIFTER_TEST
wire   vccl_aibcr3aux;
wire   vcc_aibcr3aux;
`else
wire   vccl_aibcr3aux = 1'b1;
wire   vcc_aibcr3aux  = 1'b1;
`endif
wire   vssl_aibcr3aux =1'b0;

//Changed instantiation to match with the schematic, Jennifer 05/04/18
wire por_out;     //After IO buffer
wire por_out_vcc; //After level shifter
aibcr3aux_pasred_baldwin xpasred (
     .iopad_crdet(device_detect),
     .vssl_aibcr3aux(vssl_aibcr3aux),
     .vccl_aibcr3aux(vccl_aibcr3aux),
     .iopad_dn_por(por),
     .dn_por(por_dummy));
assign o_por_vcc = (m_por_ovrd & por_out_vcc); 
assign osc_clkout = i_osc_clk;
assign o_por_vcchssi = o_por_vcc;
assign o_por_vccl = 1'b0;

aibcr3_lvshift_vcc xlvlshf1 (
     .vccl_aibcr3aux(vccl_aibcr3aux), .vcc_aibcr3aux(vcc_aibcr3aux),
     .out(por_out_vcc), .in(por));  //Output go to AND gate to produce o_por_vccl

endmodule
module aibcr3_lvshift_vcc ( out, vccl_aibcr3aux, vcc_aibcr3aux,  in);

output  out;

input  vccl_aibcr3aux, vcc_aibcr3aux;

input  in;
reg out;

always @ (in, vccl_aibcr3aux, vcc_aibcr3aux)
begin
	if (vccl_aibcr3aux == 1'b0 && vcc_aibcr3aux == 1'b0) 
	begin
		out = 1'b0;		
	end
	else if (vccl_aibcr3aux == 1'b0 && vcc_aibcr3aux == 1'b1)
	begin
		out = 1'b1;
	end
	else if (vccl_aibcr3aux == 1'b1 && vcc_aibcr3aux == 1'b0)
	begin
		out = 1'b0;
	end
	else if (vccl_aibcr3aux == 1'b1 && vcc_aibcr3aux == 1'b1)
	begin
		out = in;
	end
	else
	begin
		out = 1'bx;
	end	
end
endmodule
module aibcr3_ulvt16_dffcdn_cust ( 
	input wire CK,
	input wire CDN,
	input wire D,
	output reg Q
);

always@(posedge CK or negedge CDN) begin
	if (!CDN) begin
		Q <= 1'b0;
	end
	else begin
		Q <= D;
	end
end

endmodule
module aibcr3_ulvt16_dffsdn_cust ( 
	input wire CK,
	input wire SDN,
	input wire D,
	output reg Q
);

always@(posedge CK or negedge SDN) begin
	if (!SDN) begin
		Q <= 1'b1;
	end
	else begin
		Q <= D;
	end
end

endmodule
module aibcr3_dlycell_dcc_rep ( output co_p, output out_p, input bk, input ci_p, input in_p );

aibcr3_dlycell_dcc I7 (.co_p(co_p), .out_p(out_p), .bk(bk), .ci_p(ci_p),.in_p(in_p));

//`ifdef TIMESCALE_EN
//                timeunit 1ps;
//                timeprecision 1ps;
//`endif
//
//output  co_p, out_p;
//
//input  bk, ci_p, in_p;
//
//wire bkbl;
//
//parameter   BUF_DELAY = 20;
//
//assign net0150 = ~in_p;
//assign bkb     = ! bk;
//assign net0173 = ! (net0150 & bk);
//assign net0174 = ! (net0150 & bkb);
//assign bkl     = ! (net0173 & bkbl);
//assign bkbl    = ! (net0174 & bkl);
//
//assign #BUF_DELAY co_p = bkl? in_p : 1'b0;
//assign #BUF_DELAY out_p = bkl? ci_p : in_p;

endmodule
module aibcr3_bypmux (
        input wire byp,
        input wire in0,
        input wire in1,
        output wire out
    );

`ifdef BEHAVIORAL
    assign out = (byp) ? in1 : in0;
`else
    data_mux_2_1 mx(.sel(byp), .in0(in0), .in1(in1), .out(out));
`endif

endmodule
module aibcr3_bypmux_x4 (
        input wire byp,
        input wire in0,
        input wire in1,
        output wire out
    );

`ifdef BEHAVIORAL
    assign out = (byp) ? in1 : in0;
`else
    data_mux_2_1 mx(.sel(byp), .in0(in0), .in1(in1), .out(out));
`endif

endmodule
module aibcr3_ulvt16_2xarstsyncdff1_b2 (CLR_N, CK, D, SE, SI, Q);
    input CLR_N, CK, D, SE, SI;
    output logic Q;
    wire data;

        assign data = SE ?  SI : D ; 
	
`ifdef BEHAVIORAL

    reg flop_0;

	always @(posedge CK or negedge CLR_N)
		if (!CLR_N) {Q,flop_0} <= 0;
		else if (CLR_N) {Q,flop_0} <= {flop_0,data};
		else {Q,flop_0} <= 0;

`else

data_sync_for_aib
# ( 
    .ActiveLow    ( 1    ),
    .ResetVal     ( 1'b0 ),
    .SyncRegWidth ( 2    )
    )
u_data_sync
  ( 
    .clk      ( CK       ),
    .rst_in   ( CLR_N    ),
    .data_in  ( data     ),
    .data_out ( Q        )
    );

`endif

endmodule
module aibcr3_dcc_dly_rep ( clkrep, idat, rb_dcc_byp );

output  clkrep;

input  idat, rb_dcc_byp;

wire tielo;
wire buf_idat;
wire dcc_byp_n;
wire dcc_byp_p;
wire idat_mux0;
wire idat_mux2;


assign tielo = 1'b0;
assign tiehi = 1'b1;
aibcr3_dcc_interpolator x12 (
    .intout(idat_mux0),
    .a_in(net014),
    .sn({tiehi, tiehi, tiehi, tiehi, tiehi, tiehi, tiehi}),
    .sp({tielo, tielo, tielo, tielo, tielo, tielo, tielo}));

assign buf_idat = idat;
assign idat_mux2 = idat_mux0;
assign dcc_byp_p = rb_dcc_byp ;
assign clkrep = dcc_byp_p ? buf_idat : idat_mux2;


aibcr3_dlycell_dcc_rep x17 ( net030, net014, tielo, tiehi,
     buf_idat);

endmodule
module aibcr3_dcc_dly ( SOOUT, clk_dly, clk_mindly, PDb,
     SE, SI, SMCLK, clk_dcd, dll_lock_reg, gray, launch, measure );

output  SOOUT, clk_dly, clk_mindly;


input  PDb, SE, SI, SMCLK, clk_dcd, dll_lock_reg, launch, measure;

input [10:0]  gray;

// Buses in the design

wire  [0:255]  net105;

assign tieLO = 1'b0;
assign tieHI = 1'b1;
//assign net102 = tieLO? measure : tieLO;
data_mux_2_1 mindly_mux(.in0(measure), .in1(clk_dcd), .sel(dll_lock_reg), .out(clkin_mindly));
data_mux_2_1 dlyline_mux(.in0(launch), .in1(clk_dcd), .sel(dll_lock_reg), .out(clkin_dlyline));


// Actual delay path
aibcr3_dcc_dlyline I0 ( SO_dlyline, net105[0:255], net029, clk_dly,
       clkin_dlyline, PDb, SE, SI, SMCLK, gray[10:0]);

// Intrinsic delay compensation path
aibcr3_dcc_8ph_intp I1 ( SOOUT, clk_mindly,   SMCLK, PDb,
     net104, {tieLO, tieLO, tieLO}, SE, SO_dlyline);
aibcr3_dlycell_dcc I7 ( .co_p(net103), .out_p(net104), .bk(tieLO), .ci_p(tieHI),
     .in_p(clkin_mindly));

endmodule
module aibcr3_analog ( oclkn, oclkp, odat, odat_async,
     iopad, iopad_out, clk_en, data_en, iclkn, indrv_buf, ipdrv_buf,
     itx_en_buf, por_aib_vcc1, por_aib_vcchssi, txdin, weak_pulldownen,
     weak_pullupenb
);

output wire oclkn, oclkp, odat, odat_async;


inout wire iopad, iopad_out;

input wire clk_en, data_en, iclkn, itx_en_buf, por_aib_vcc1,
     por_aib_vcchssi, txdin, weak_pulldownen, weak_pullupenb;

input wire [1:0]  indrv_buf;
input wire [1:0]  ipdrv_buf;

wire net14;
wire tielo;
wire odat_maxout;
wire odat_mid;

assign tielo = 1'b0;

`ifdef BEHAVIORAL
    assign odat_maxout = tielo? tielo : net14;
    assign odat = odat_maxout;
`else
    // Dummy loading / delays, these need to be preserved
    aibcr3_bypmux_x4 delay_mux  (.out(odat_maxout), .byp(tielo), .in1(tielo), .in0(net14));
    buffer delay_buf     (.out(odat_mid), .in(odat_maxout));
    // BCA: delay_buf_2 is the additional delay buffer that Ayar put in aibcr3_rxdig on this same
    // timing path. We moved it here because we are using Intel's aibcr3_rxdig, but still wanted
    // the matching delay of the additional buffer.
    buffer delay_buf_2   (.out(odat), .in(odat_mid));
`endif

aibcr3_frontend u_aibcr3_frontend (
    .clk_en(clk_en),
    .data_en(data_en),
    .din(txdin),
    .iclkn(iclkn),
    .indrv_buf(indrv_buf[1:0]),
    .ipdrv_buf(ipdrv_buf[1:0]),
    .itx_en_buf(itx_en_buf),
    .por(por_aib_vcchssi),
    .weak_pulldownen(weak_pulldownen),
    .weak_pullupenb(weak_pullupenb),
    .iopad_out(iopad_out),
    .oclkn(oclkn),
    .oclkp(oclkp),
    .odat(net14),
    .odat_async(odat_async),
    .iopad(iopad)
);

endmodule
module aibcr3_ddrmux (
        input wire clk,
        input wire in0,
        input wire in1,
        output wire out
    );

`ifdef BEHAVIORAL
    assign out = (clk) ? in1 : in0;
`else
    data_mux_2_1 mx(.sel(clk), .in0(in0), .in1(in1), .out(out));
`endif

endmodule
module aibcr3_cmos_nand_x64 ( out_p, so, code_valid,
     dll_reset_n, in_p, scan_rst_n, sck_in, se_n, si, sm_grey,
     sm_igray, sm_n );

output  out_p, so;

input  code_valid, dll_reset_n, in_p, scan_rst_n, sck_in, se_n, si,
     sm_n;

input [6:0]  sm_grey;
input [2:0]  sm_igray;

// Buses in the design

wire  [63:0]  bk;

wire  [6:0]  grey;

wire  [2:0]  i_gray;

wire         so_g2th;
wire         net110;
wire         clk_prebuf;


assign tie_HI   = 1'b1;
assign tie_LO   = 1'b0;
assign nrst     = net110;
assign clk_buf0 = clk_prebuf;
assign SE       = ! se_n;
assign sm_n_buf = sm_n;
assign ck       = clk_buf0;
assign clk_prebuf = sm_n_buf? out_p : sck_in;
assign net110     = sm_n_buf? dll_reset_n : scan_rst_n;

aibcr3_dll_8ph_intp x4 ( .SOOUT(so), .intout(out_p), .CLKIN(ck), .PDb(nrst), .fanout(net104),
     .gray(i_gray[2:0]), .iSE(SE), .iSI(so_g2th));

aibcr3_dll_gry2thm64 x1 ( bk[63:0], tie_LO, 
     grey[6:0], tie_LO);

aibcr3_dll_ibkmux x17 ( so_sync, grey[6:0], i_gray[2:0], 
     ck, nrst, SE, code_valid, si, sm_grey[6:0], sm_igray[2:0]);

aibcr3_dlycell_dll_comb I7 ( .co_p(net108), .out_p(net109), .bk(tie_LO), .ci_p(tie_HI),
     .in_p(net106));

aibcr3_dll_dlyline64 x0 ( .a63(net106), .dlyout(net104), .b63(net109),
     .bk(bk[63:0]), .dlyin(in_p), .CLKIN(ck), .iSE(SE), .RSTb(nrst), .iSI(so_sync), .SOOUT(so_g2th));

endmodule
module clk_gate_cel(
output clkout, // Clock gated
input  clk,    // Clock input
input  en,     // Clock enable
input  te      // Test enable
);

wire clk_en;
reg  latch;
assign clk_en = te | en;

always @(clk or clk_en)
  begin
    if(!clk)
      latch = clk_en;
  end

assign clkout = latch & clk;

endmodule // clk_gate_cel
module clk_inv_cel(
output clkout, // clock output
input  clk     // clock input
);

assign clkout = ~clk;

endmodule // clk_inv_cel
module clk_and2_cel(
output clkout, // AND output
input  clk1, // clock 1
input  clk2  // clock 2
);

assign clkout = clk1 & clk2;

endmodule // clk_and2_cel
module clk_resize_cel(
output clkout, // clock output
input  clk     // clock input
);

assign clkout = clk;

endmodule // clk_resize_cel
module clk_or3_cel(
output clkout, // OR output
input  clk1, // clock 1
input  clk2, // clock 2
input  clk3  // clock 3
);

wire clkout_1_2;
wire clkout_3;

// First OR level for clk1 and clk2
clk_or2_cel clk_or2_1(
.clkout (clkout_1_2), // OR output
.clk1   (clk1),       // clock 1
.clk2   (clk2)        // clock 2
);

// First OR level for clk3
clk_or2_cel clk_or2_2(
.clkout (clkout_3), // OR output
.clk1   (clk3),     // clock 1
.clk2   (1'b0)      // clock 2
);

// Second OR level for clk1, clk2 and clk3
clk_or2_cel clk_or2_3(
.clkout (clkout),      // OR output
.clk1   (clkout_1_2),  // clock 1
.clk2   (clkout_3)     // clock 2
);

endmodule // clk_or3_cel
module clk_and4_cel(
output clkout, // AND output
input  clk1,   // clock 1
input  clk2,  // clock 2
input  clk3,  // clock 3
input  clk4  // clock 3
);

assign clkout = clk1 & clk2 & clk3 & clk4;

endmodule // clk_and4_cel
module clk_buf_cel(
output clkout, // clock output
input  clk     // clock input
);

assign clkout = clk;

endmodule // clk_buf_cel