dakies/OSS_Verilog huggingface dataset:
module asic_dffqn #(parameter PROP = "DEFAULT")   (
    input  	d,
    input  	clk,
    output reg  qn
    );

   always @ (posedge clk)
     qn <= ~d;

endmodule
module asic_latq #(parameter PROP = "DEFAULT")   (
    input      d,
    input      clk,
    output reg q
    );

   always @ (clk or d)
     if(clk)
       q <= d;

endmodule
module asic_ao21 #(parameter PROP = "DEFAULT")  (
   input  a0,
   input  a1,
   input  b0,
   output z
   );

   assign z = (a0 & a1) | b0;

endmodule
module asic_sdffsq #(parameter PROP = "DEFAULT")   (
    input      d,
    input      si,
    input      se,
    input      clk,
    input      nset,
    output reg q
    );

   always @ (posedge clk or negedge nset)
     if(!nset)
       q <= 1'b1;
     else
       q <= se ? si : d;

endmodule
module asic_sdffrqn #(parameter PROP = "DEFAULT")   (
    input      d,
    input      si,
    input      se,
    input      clk,
    input      nreset,
    output reg qn
    );

   always @ (posedge clk or negedge nreset)
     if(!nreset)
       qn <= 1'b1;
     else
       qn <=  se ? ~si : ~d;

endmodule
module asic_xor4 #(parameter PROP = "DEFAULT")   (
    input  a,
    input  b,
    input  c,
    input  d,
    output z
    );

   assign z =  a ^ b ^ c ^ d;

endmodule
module asic_dmux7 #(parameter PROP = "DEFAULT")   (
    input  sel6,
    input  sel5,
    input  sel4,
    input  sel3,
    input  sel2,
    input  sel1,
    input  sel0,
    input  in6,
    input  in5,
    input  in4,
    input  in3,
    input  in2,
    input  in1,
    input  in0,
    output out
    );

   assign out = sel0 & in0 |
		sel1 & in1 |
		sel2 & in2 |
		sel3 & in3 |
		sel4 & in4 |
		sel5 & in5 |
		sel6 & in6;

endmodule
module asic_csa42 #(parameter PROP = "DEFAULT")  ( input  a,
    input  b,
    input  c,
    input  d,
    input  cin,
    output sum,
    output carry,
    output cout
    );

   assign cout   = (a & b) | (b & c) | (a & c);
   assign sumint = a ^ b ^ c;
   assign sum    = cin ^ d ^ sumint;
   assign carry  = (cin & d) | (cin & sumint) | (d & sumint);

endmodule
module asic_header #(parameter PROP = "DEFAULT")   (
    input  sleep,  // 1 = disabled vdd
    input  vddin,  // input supply
    output vddout  // gated output supply
    );

   // Primitive Device
   pmos m0 (vddout, vssin, sleep); //d,s,g

endmodule
module asic_tbuf #(parameter PROP = "DEFAULT")  (
   input  a,
   input  oe,
   output z
   );

   assign z = oe ? a : 1'bz;

endmodule
module asic_ao211 #(parameter PROP = "DEFAULT")  (
   input  a0,
   input  a1,
   input  b0,
   input  c0,
   output z
   );

   assign z = (a0 & a1) | b0 | c0;

endmodule
module asic_and4 #(parameter PROP = "DEFAULT")  (
   input  a,
   input  b,
   input  c,
   input  d,
   output z
   );

   assign z = a & b & c & d;

endmodule
module asic_clknor2 #(parameter PROP = "DEFAULT")   (
    input  a,
    input  b,
    output z
    );

   assign z = ~(a | b);

endmodule
module asic_aoi22 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  b0,
    input  b1,
    output z
    );

   assign z = ~((a0 & a1) | (b0 & b1));

endmodule
module asic_dffsq #(parameter PROP = "DEFAULT")   (
    input      d,
    input      clk,
    input      nset,
    output reg q
    );

   always @ (posedge clk or negedge nset)
     if(!nset)
       q <= 1'b1;
     else
       q <= d;

endmodule
module asic_dmux4 #(parameter PROP = "DEFAULT")   (
    input  sel3,
    input  sel2,
    input  sel1,
    input  sel0,
    input  in3,
    input  in2,
    input  in1,
    input  in0,
    output out
    );

   assign out = sel0 & in0 |
		sel1 & in1 |
		sel2 & in2 |
		sel3 & in3;

endmodule
module asic_antenna #(parameter PROP = "DEFAULT")   (
    input  vss,
    output z
    );

endmodule
module asic_iddr #(parameter PROP = "DEFAULT")   (
    input      clk,     // clock
    input      in,      // data input sampled on both edges of clock
    output reg outrise, // rising edge sample
    output reg outfall  // falling edge sample
    );

   // Negedge Sample
   always @ (negedge clk)
     outfall <= in;

   // Posedge Sample
   reg 	       inrise;
   always @ (posedge clk)
     inrise <= in;

   // Posedge Latch (for hold)
   always @ (clk or inrise)
     if(~clk)
       outrise <= inrise;

endmodule
module asic_clkand2 #(parameter PROP = "DEFAULT")   (
    input  a,
    input  b,
    output z
    );

   assign z = a & b;

endmodule
module asic_aoi33 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  a2,
    input  b0,
    input  b1,
    input  b2,
    output z
    );

   assign z = ~((a0 & a1 & a2) | (b0 & b1 & b2));

endmodule
module asic_latnq #(parameter PROP = "DEFAULT")   (
    input      d,
    input      clk,
    output reg q
    );

   always @ (clk or d)
     if(~clk)
       q <= d;

endmodule
module asic_dmux3 #(parameter PROP = "DEFAULT")   (
    input  sel2,
    input  sel1,
    input  sel0,
    input  in2,
    input  in1,
    input  in0,
    output out
    );

   assign out = sel0 & in0 |
		sel1 & in1 |
		sel2 & in2;

endmodule
module asic_clknand2 #(parameter PROP = "DEFAULT")   (
    input  a,
    input  b,
    output z
    );

   assign z = ~(a & b);

endmodule
module asic_xnor4 #(parameter PROP = "DEFAULT")   (
    input  a,
    input  b,
    input  c,
    input  d,
    output z
    );

   assign z =  ~(a ^ b ^ c ^ d);

endmodule
module asic_csa32 #(parameter PROP = "DEFAULT")
   (
     input  a,
     input  b,
     input  c,
     output sum,
     output carry
     );

   assign sum = a ^ b ^ c;
   assign carry = (a & b) | (b & c) | (c & a);

endmodule
module asic_oai31 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  a2,
    input  b0,
    output z
    );

   assign z = ~((a0 | a1 | a2) & b0);

endmodule
module asic_oa22 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  b0,
    input  b1,
    output z
    );

   assign z = (a0 | a1) & (b0 | b1);

endmodule
module asic_dsync #(parameter PROP = "DEFAULT")   (
    input  clk,    // clock
    input  nreset, // async active low reset
    input  in,     // input data
    output out     // synchronized data
    );

   localparam SYNCPIPE=2;

   reg [SYNCPIPE-1:0] sync_pipe;
   always @ (posedge clk or negedge nreset)
     if(!nreset)
       sync_pipe[SYNCPIPE-1:0] <= 'b0;
     else
       sync_pipe[SYNCPIPE-1:0] <= {sync_pipe[SYNCPIPE-1:0],in};

   assign out = sync_pipe[SYNCPIPE-1];

endmodule
module asic_nand2 #(parameter PROP = "DEFAULT")   (
    input  a,
    input  b,
    output z
    );

   assign z = ~(a & b);

endmodule
module asic_sdffq #(parameter PROP = "DEFAULT")   (
    input      d,
    input      si,
    input      se,
    input      clk,
    output reg q
    );

   always @ (posedge clk)
       q <= se ? si : d;

endmodule
module asic_tielo #(parameter PROP = "DEFAULT")  (
   output z
   );

   assign z = 1'b0;

endmodule
module asic_dffsqn #(parameter PROP = "DEFAULT")   (
    input d,
    input clk,
    input nset,
    output reg  qn
    );

   always @ (posedge clk or negedge nset)
     if(!nset)
       qn <= 1'b0;
     else
       qn <= ~d;

endmodule
module asic_nor3 #(parameter PROP = "DEFAULT")   (
    input  a,
    input  b,
    input  c,
    output z
    );

   assign z = ~(a | b | c);

endmodule
module asic_oa222 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  b0,
    input  b1,
    input  c0,
    input  c1,
    output z
    );

   assign z = (a0 | a1) & (b0 | b1) & (c0 | c1);

endmodule
module asic_oai222 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  b0,
    input  b1,
    input  c0,
    input  c1,
    output z
    );

   assign z = ~((a0 | a1) & (b0 | b1) & (c0 | c1));

endmodule
module asic_or4 #(parameter PROP = "DEFAULT")   (
    input  a,
    input  b,
    input  c,
    input  d,
    output z
    );

   assign z = a | b | c | d;

endmodule
module asic_mux2 #(parameter PROP = "DEFAULT")   (
    input  d0,
    input  d1,
    input  s,
    output z
    );

   assign z = (d0 & ~s) | (d1 & s);

endmodule
module asic_aoi31 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  a2,
    input  b0,
    output z
    );

   assign z = ~((a0 & a1 & a2) | b0);

endmodule
module asic_ao31 #(parameter PROP = "DEFAULT")  (
   input  a0,
   input  a1,
   input  a2,
   input  b0,
   output z
   );

   assign z = (a0 & a1 & a2) | b0;

endmodule
module asic_xnor2 #(parameter PROP = "DEFAULT")   (
    input  a,
    input  b,
    output z
    );

   assign z =  ~(a ^ b);

endmodule
module asic_muxi4 #(parameter PROP = "DEFAULT")   (
    input  d0,
    input  d1,
    input  d2,
    input  d3,
    input  s0,
    input  s1,
    output z
    );

   assign z = ~((d0 & ~s1 & ~s0) |
		(d1 & ~s1 &  s0) |
		(d2 &  s1 & ~s0) |
		(d2 &  s1 &  s0));

endmodule
module asic_sdffsqn #(parameter PROP = "DEFAULT")   (
    input      d,
    input      si,
    input      se,
    input      clk,
    input      nset,
    output reg qn
    );

   always @ (posedge clk or negedge nset)
     if(!nset)
       qn <= 1'b0;
     else
       qn <= se ? ~si : ~d;

endmodule
module asic_isohi
  #(parameter PROP = "DEFAULT")
   (
    input  iso, // isolation signal
    input  in, // input
    output out  // out = iso | in
    );

   assign out = iso | in;

endmodule // asic_isohi
module asic_tiehi #(parameter PROP = "DEFAULT")   (
    output z
    );

   assign z = 1'b1;

endmodule
module asic_buf #(parameter PROP = "DEFAULT")   (
    input  a,
    output z
    );

   assign z = a;

endmodule
module asic_oddr #(parameter PROP = "DEFAULT")  (
   input  clk, // clock input
   input  in0, // data for clk=0
   input  in1, // data for clk=1
   output out  // dual data rate output
   );

   //Making in1 stable for clk=1
   reg 	  in1_sh;
   always @ (clk or in1)
     if(~clk)
       in1_sh <= in1;

   //Using clock as data selctor
   assign out = clk ? in1_sh : in0;

endmodule
module asic_oa221 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  b0,
    input  b1,
    input  c0,
    output z
    );

   assign z = (a0 | a1) & (b0 | b1) & (c0);

endmodule
module asic_or2 #(parameter PROP = "DEFAULT")   (
    input  a,
    input  b,
    output z
    );

   assign z = a | b;

endmodule
module asic_oai221 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  b0,
    input  b1,
    input  c0,
    output z
    );

   assign z = ~((a0 | a1) & (b0 | b1) & (c0));

endmodule
module asic_xor2 #(parameter PROP = "DEFAULT")   (
    input  a,
    input  b,
    output z
    );

   assign z =  a ^ b;

endmodule
module asic_inv #(parameter PROP = "DEFAULT")   (
    input  a,
    output z
    );

   assign z = ~a;

endmodule
module asic_delay #(parameter PROP = "DEFAULT")   (
    input  a,
    output z
    );

   assign z = a;

endmodule
module asic_and2 #(parameter PROP = "DEFAULT")  (
   input  a,
   input  b,
   output z
   );

   assign z = a & b;

endmodule
module asic_oa21 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  b0,
    output z
    );

   assign z = (a0 | a1) & b0;

endmodule
module asic_oai311 #(parameter PROP = "DEFAULT")  (
   input  a0,
   input  a1,
   input  a2,
   input  b0,
   input  c0,
   output z
   );

   assign z = ~((a0 | a1 | a2) & b0 & c0);

endmodule
module asic_mux4 #(parameter PROP = "DEFAULT")  (
   input  d0,
   input  d1,
   input  d2,
   input  d3,
   input  s0,
   input  s1,
   output z
   );

   assign z = (d0 & ~s1 & ~s0) |
	      (d1 & ~s1 &  s0) |
	      (d2 &  s1 & ~s0) |
	      (d2 &  s1 &  s0);

endmodule
module asic_mux3 #(parameter PROP = "DEFAULT")   (
    input  d0,
    input  d1,
    input  d2,
    input  s0,
    input  s1,
    output z
    );

   assign z = (d0 & ~s0 & ~s1) |
	      (d1 & s0  & ~s1) |
	      (d2 & s1);

endmodule
module asic_or3 #(parameter PROP = "DEFAULT")  (
    input a,
    input b,
    input c,
    output z
   );

   assign z = a | b | c ;

endmodule
module asic_oai32 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  a2,
    input  b0,
    input  b1,
    output z
    );

   assign z = ~((a0 | a1 | a2) & (b0 | b1));

endmodule
module asic_nor2 #(parameter PROP = "DEFAULT")   (
    input  a,
    input  b,
    output z
    );

   assign z = ~(a | b);

endmodule
module asic_xor3 #(parameter PROP = "DEFAULT")  (
   input  a,
   input  b,
   input  c,
   output z
   );

   assign z =  a ^ b ^ c;

endmodule
module asic_ao222 #(parameter PROP = "DEFAULT")  (
   input  a0,
   input  a1,
   input  b0,
   input  b1,
   input  c0,
   input  c1,
   output z
   );

   assign z = (a0 & a1) | (b0 & b1) | (c0 & c1);

endmodule
module asic_dffq #(parameter PROP = "DEFAULT")   (
    input      d,
    input      clk,
    output reg q
    );

   always @ (posedge clk)
     q <= d;

endmodule
module asic_ao311 #(parameter PROP = "DEFAULT")  (
   input  a0,
   input  a1,
   input  a2,
   input  b0,
   input  c0,
   output z
   );

   assign z = (a0 & a1 & a2) | b0 | c0;

endmodule
module asic_rsync #(parameter PROP = "DEFAULT")  (
   input  clk,
   input  nrst_in,
   output nrst_out
   );

   localparam SYNCPIPE=2;

   reg [SYNCPIPE-1:0] sync_pipe;
   always @ (posedge clk or negedge nrst_in)
     if(!nrst_in)
       sync_pipe[SYNCPIPE-1:0] <= 'b0;
     else
       sync_pipe[SYNCPIPE-1:0] <= {sync_pipe[SYNCPIPE-2:0],1'b1};
   assign nrst_out = sync_pipe[SYNCPIPE-1];

endmodule
module asic_oai21 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  b0,
    output z
    );

   assign z = ~((a0 | a1) & b0);

endmodule
module asic_clkmux2 #(parameter PROP = "DEFAULT")   (
    input  clk0,
    input  clk1,
    input  sel,
    output z
    );

   assign z = sel ? clk0 : clk1;

endmodule
module asic_clkbuf #(parameter PROP = "DEFAULT")   (
    input  a,
    output z
    );

   assign z = a;

endmodule
module asic_nand4 #(parameter PROP = "DEFAULT")   (
    input  a,
    input  b,
    input  c,
    input  d,
    output z
    );

   assign z = ~(a & b & c & d);

endmodule
module asic_clkxor2 #(parameter PROP = "DEFAULT")   (
    input  a,
    input  b,
    output z
    );

   assign z = a ^ b;

endmodule
module asic_nand3 #(parameter PROP = "DEFAULT")   (
    input  a,
    input  b,
    input  c,
    output z
    );

   assign z = ~(a & b & c);

endmodule
module asic_muxi2 #(parameter PROP = "DEFAULT")   (
    input  d0,
    input  d1,
    input  s,
    output z
    );

   assign z = ~((d0 & ~s) | (d1 & s));

endmodule
module asic_and3 #(parameter PROP = "DEFAULT")  (
   input  a,
   input  b,
   input  c,
   output z
   );

   assign z = a & b & c;

endmodule
module asic_ao33 #(parameter PROP = "DEFAULT")  (
   input  a0,
   input  a1,
   input  a2,
   input  b0,
   input  b1,
   input  b2,
   output z
   );

   assign z = (a0 & a1 & a2) | (b0 & b1 & b2);

endmodule
module asic_ao22 #(parameter PROP = "DEFAULT")  (
   input  a0,
   input  a1,
   input  b0,
   input  b1,
   output z
   );

   assign z = (a0 & a1) | (b0 & b1);

endmodule
module asic_dmux8 #(parameter PROP = "DEFAULT")   (
    input  sel7,
    input  sel6,
    input  sel5,
    input  sel4,
    input  sel3,
    input  sel2,
    input  sel1,
    input  sel0,
    input  in7,
    input  in6,
    input  in5,
    input  in4,
    input  in3,
    input  in2,
    input  in1,
    input  in0,
    output out
    );

   assign out = sel0 & in0 |
		sel1 & in1 |
		sel2 & in2 |
		sel3 & in3 |
		sel4 & in4 |
		sel5 & in5 |
		sel6 & in6 |
		sel7 & in7;

endmodule
module asic_decap #(parameter PROP = "DEFAULT")   (
    input  vss,
    output vdd
    );

endmodule
module asic_aoi21 #(parameter PROP = "DEFAULT")  (
   input  a0,
   input  a1,
   input  b0,
   output z
   );

   assign z = ~((a0 & a1) | b0);

endmodule
module asic_clkicgand #(parameter PROP = "DEFAULT")  (
   input  clk, // clock input
   input  te, // test enable
   input  en, // enable (from positive edge FF)
   output eclk // enabled clock output
   );

   reg 	  en_stable;

   always @ (clk or en or te)
     if (~clk)
       en_stable <= en | te;

   assign eclk =  clk & en_stable;

endmodule
module asic_dmux2 #(parameter PROP = "DEFAULT")   (
    input  sel1,
    input  sel0,
    input  in1,
    input  in0,
    output out
    );

   assign out = sel0 & in0 |
		sel1 & in1;

endmodule
module asic_isolo
  #(parameter PROP = "DEFAULT")
   (
    input  iso, // isolation signal
    input  in, // input
    output out  // out = ~iso & in
    );

   assign out = ~iso & in;

endmodule
module asic_dmux6 #(parameter PROP = "DEFAULT")  (
   input  sel5,
   input  sel4,
   input  sel3,
   input  sel2,
   input  sel1,
   input  sel0,
   input  in5,
   input  in4,
   input  in3,
   input  in2,
   input  in1,
   input  in0,
   output out
    );

   assign out = sel0 & in0 |
		sel1 & in1 |
		sel2 & in2 |
		sel3 & in3 |
		sel4 & in4 |
		sel5 & in5;

endmodule
module asic_aoi32 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  a2,
    input  b0,
    input  b1,
    output z
    );

   assign z = ~((a0 & a1 & a2) | (b0 & b1));

endmodule
module asic_oa33 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  a2,
    input  b0,
    input  b1,
    input  b2,
    output z
    );

   assign z = (a0 | a1 | a2) & (b0 | b1 | b2);

endmodule
module asic_oa31 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  a2,
    input  b0,
    output z
    );

   assign z = (a0 | a1 | a2) & b0;

endmodule
module asic_clkicgor #(parameter PROP = "DEFAULT")  (
   input  clk,// clock input
   input  te, // test enable
   input  en, // enable
   output eclk  // enabled clock output
   );

   reg 	  en_stable;

   always @ (clk or en or te)
     if (clk)
       en_stable <= en | te;

   assign eclk =  clk | ~en_stable;

endmodule
module asic_xnor3 #(parameter PROP = "DEFAULT")   (
    input  a,
    input  b,
    input  c,
    output z
    );

   assign z =  ~(a ^ b ^ c);

endmodule
module asic_dffnq #(parameter PROP = "DEFAULT")   (
    input      d,
    input      clk,
    output reg q
    );

   always @ (negedge clk)
     q <= d;

endmodule
module asic_clkinv #(parameter PROP = "DEFAULT")  (
    input  a,
    output z
    );

   assign z = ~a;

endmodule
module asic_dffrqn #(parameter PROP = "DEFAULT")   (
    input      d,
    input      clk,
    input      nreset,
    output reg qn
    );

   always @ (posedge clk or negedge nreset)
     if(!nreset)
       qn <= 1'b1;
     else
       qn <= ~d;

endmodule
module asic_nor4 #(parameter PROP = "DEFAULT")   (
    input  a,
    input  b,
    input  c,
    input  d,
    output z
    );

   assign z = ~(a | b | c | d);

endmodule
module asic_sdffrq #(parameter PROP = "DEFAULT")   (
    input      d,
    input      si,
    input      se,
    input      clk,
    input      nreset,
    output reg q
    );

   always @ (posedge clk or negedge nreset)
     if(!nreset)
       q <= 1'b0;
     else
       q <= se ? si : d;

endmodule
module asic_oai33 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  a2,
    input  b0,
    input  b1,
    input  b2,
    output z
    );

   assign z = ~((a0 | a1 | a2) & (b0 | b1 | b2));

endmodule
module asic_aoi211 #(parameter PROP = "DEFAULT")  (
   input  a0,
   input  a1,
   input  b0,
   input  c0,
   output z
   );

   assign z = ~((a0 & a1) | b0 | c0);

endmodule
module asic_keeper #(parameter PROP = "DEFAULT")   (
    inout z
    );

endmodule
module asic_clkor2 #(parameter PROP = "DEFAULT")   (
    input  a,
    input  b,
    output z
    );

   assign z = a | b;

endmodule
module asic_dmux5 #(parameter PROP = "DEFAULT")   (
    input  sel4,
    input  sel3,
    input  sel2,
    input  sel1,
    input  sel0,
    input  in4,
    input  in3,
    input  in2,
    input  in1,
    input  in0,
    output out
    );

   assign out = sel0 & in0 |
		sel1 & in1 |
		sel2 & in2 |
		sel3 & in3 |
		sel4 & in4;

endmodule
module asic_sdffqn #(parameter PROP = "DEFAULT")   (
    input      d,
    input      si,
    input      se,
    input      clk,
    output reg qn
    );

   always @ (posedge clk)
     qn <= se ? ~si : ~d;

endmodule
module asic_aoi222 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  b0,
    input  b1,
    input  c0,
    input  c1,
    output z
    );

   assign z = ~((a0 & a1) | (b0 & b1) | (c0 & c1));

endmodule
module asic_dffrq #(parameter PROP = "DEFAULT")   (
    input      d,
    input      clk,
    input      nreset,
    output reg q
    );

   always @ (posedge clk or negedge nreset)
     if(!nreset)
       q <= 1'b0;
     else
       q <= d;

endmodule
module dut(/*AUTOARG*/
   // Outputs
   dut_active, clkout, wait_out, access_out, packet_out,
   // Inputs
   clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
   );

   parameter N  = 1;
   parameter PW = 104;
      
   //clock, reset
   input            clk1;
   input            clk2;
   input            nreset;
   input [N*N-1:0]  vdd;
   input 	    vss;
   output 	    dut_active;
   output 	    clkout;
   
   //Stimulus Driven Transaction
   input [N-1:0]     access_in;
   input [N*PW-1:0]  packet_in;
   output [N-1:0]    wait_out;

   //DUT driven transactoin
   output [N-1:0]    access_out;
   output [N*PW-1:0] packet_out;
   input [N-1:0]     wait_in;

   /*AUTOINPUT*/
   /*AUTOOUTPUT*/
   /*AUTOWIRE*/

   wire [31:0] 	     gray;
   
   //tie offs for Dv
   assign dut_active = 1'b1;
   assign wait_out   = 1'b0;
   assign clkout     = clk1;
   assign access_out = access_in;
   
   //convert binary to gray
   oh_bin2gray #(.DW(32))
   b2g (.gray (gray[31:0]),
	.bin  (packet_in[39:8]));
   
   //convert gray back to binary
   oh_gray2bin #(.DW(32))
   g2b(.bin  (packet_out[39:8]),
       .gray (gray[31:0]));

   //check for error
   assign error = |(packet_in[39:8] ^ packet_out[39:8]);
   
endmodule // dut
module dut(/*AUTOARG*/
   // Outputs
   dut_active, clkout, wait_out, access_out, packet_out,
   // Inputs
   clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
   );

   parameter N  = 1;
   parameter PW = 104;
      
   //clock, reset
   input             clk1;
   input 	     clk2;   
   input             nreset;
   input [N*N-1:0]   vdd;
   input 	     vss;
   output 	     dut_active;
   output 	     clkout;
   
   //Stimulus Driven Transaction
   input [N-1:0]     access_in;
   input [N*PW-1:0]  packet_in;
   output [N-1:0]    wait_out;

   //DUT driven transactoin
   output [N-1:0]    access_out;
   output [N*PW-1:0] packet_out;
   input [N-1:0]     wait_in;

   /*AUTOINPUT*/
   /*AUTOOUTPUT*/
   /*AUTOWIRE*/
    

   //tie offs for Dv
   assign dut_active   = 1'b1;
   assign clkout       = clk2;
   
   oh_fifo_cdc #(.DW(PW),
		 .DEPTH(16))
   oh_fifo_cdc(.clk_in			(clk1), 
	       .clk_out			(clk2),
	       /*AUTOINST*/
	       // Outputs
	       .wait_out		(wait_out),
	       .access_out		(access_out),
	       .packet_out		(packet_out[PW-1:0]),
	       // Inputs
	       .nreset			(nreset),
	       .access_in		(access_in),
	       .packet_in		(packet_in[PW-1:0]),
	       .wait_in			(wait_in));
   
endmodule // dv_elink
module tb_dut
  #(parameter PW              = 256,      // packet width
    parameter N               = 36,       // ctrl/status width
    parameter TARGET          = "DEFAULT" // physical synthesis/sim target
    )
   (// basic test interface
    input 	    clk, // standard clock used for interface
    input 	    fastclk, // fast clock (optional for core)
    input 	    slowclk, // fast clock (optional for core)
    input 	    nreset, // async active low reset
    input 	    go, // go dut (if not self-booting)
    input [N-1:0]   ctrl, // env generic ctrl vector
    // environment packet interface
    input 	    valid, // env packet valid signal
    input [PW-1:0]  packet, // env packet to drive
    input 	    ready, // env is ready for packet
    // dut status signals
    output 	    dut_active, // dut reset sequence done
    output 	    dut_error, // per cycle error signal
    output 	    dut_done, // dut is done
    output [N-1:0]  dut_status, // dut generic status vector
    // dut response packets
    output 	    dut_valid, //dut packet valid signal
    output [PW-1:0] dut_packet, // dut packet to drive
    output 	    dut_ready // dut is ready for packet
    );

endmodule // tb_dut
module oh_simchecker #(parameter DW = 32 // Datapath width
		       )
  (
   //Inputs 
   input 	  clk,
   input 	  nreset,
   input [DW-1:0] result, // result to check
   input [DW-1:0] reference, // reference result
   output reg 	  diff //fail indicator
   );
   
   always @ (negedge clk or negedge nreset)
     if(~nreset)
       diff <= 1'b0;   
     else  if(result!==reference)
       begin
	  diff <= 1'b1;	  
`ifdef CFG_SIM 
	  $display("ERROR(%0t): result= %d(%h) reference= %d(%h)", $time, result,result, reference, reference);
`endif
       end
     else
       diff <= 1'b0;	  
   
endmodule // oh_simchecker
module testbench();

   localparam DW = 144;
   localparam CW = 8;
   localparam FILENAME = "test.mem"; //

   /*AUTOINPUT*/
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire			nreset;			// From oh_simctrl of oh_simctrl.v
   wire			start;			// From oh_simctrl of oh_simctrl.v
   wire			stim_done;		// From oh_stimulus of oh_stimulus.v
   wire [DW-1:0]	stim_packet;		// From oh_stimulus of oh_stimulus.v
   wire			stim_valid;		// From oh_stimulus of oh_stimulus.v
   wire			vdd;			// From oh_simctrl of oh_simctrl.v
   wire			vss;			// From oh_simctrl of oh_simctrl.v
   // End of automatics

   oh_stimulus #(.DW(DW),
		 .CW(CW),
		 .FILENAME(FILENAME))
   oh_stimulus(.dut_ready		(1'b1),
	       .dut_clk			(dut_clk),
	       .ext_valid		(1'b0),
	       .ext_packet		({(DW + CW){1'b0}}),
	       .ext_clk			(ext_clk),
	       .ext_start		(start),
	       /*AUTOINST*/
	       // Outputs
	       .stim_valid		(stim_valid),
	       .stim_packet		(stim_packet[DW-1:0]),
	       .stim_done		(stim_done),
	       // Inputs
	       .nreset			(nreset));

   oh_simctrl oh_simctrl(.stim_done	(1'b0),
			 .test_done	(1'b1),
			 .test_diff	(1'b0),
			 .dut_active    (1'b1),
			 .clk1		(ext_clk),
			 .clk2		(dut_clk),
			 /*AUTOINST*/
			 // Outputs
			 .nreset		(nreset),
			 .start			(start),
			 .vdd			(vdd),
			 .vss			(vss));

endmodule // tb
module testbench
  #(parameter PW        = 256,         // packet total width
    parameter CW        = 16,          // packet control width
    parameter N         = 32,          // ctrl/status width
    parameter DEPTH     = 8192,        // simulus memory depth
    parameter TARGET    = "DEFAULT",   // physical synthesis/sim target
    parameter FILENAME  = "NONE"     // Simulus hexfile for $readmemh
    )
   (
    // control signals to drive
    input 	    nreset, // async active low reset
    input 	    clk, // core clock
    input 	    fastclk, // fast clock
    input 	    slowclk, //slow clock
    input [2:0]     mode, //0=load,1=go,2=bypass,3=rng
    input [N-1:0]   ctrl, // generic ctrl vector
    input [N-1:0]   seed, // seed(s) for rng
    // external write interface
    input 	    ext_clk, //ext packet clock
    input 	    ext_valid, // ext valid signal
    input [PW-1:0]  ext_packet, // ext packet
    input 	    ext_ready, // external ready to receive
    // dut response packets
    output 	    dut_clk, // due packet clock
    output 	    dut_valid, //dut packet valid signal
    output [PW-1:0] dut_packet, // dut packet to drive
    output 	    dut_ready, // dut is ready for packet
    // dut status interface
    output [N-1:0]  dut_status, // generic status vector
    output 	    dut_error,// dut error flag (leads to failure)
    output 	    dut_done, // test done
    output 	    dut_fail  // test failed
    );

   //#################################
   // LOCAL WIRES
   //#################################

   /*AUTOWIRE*/
   /*AUTOINPUT*/

   //#################################
   // DUT LOGIC
   //#################################

   assign dut_ready  = 1'b1;
   assign dut_error  = 1'b0;
   assign dut_done   = 1'b0;
   assign dut_valid  = 1'b0;
   assign dut_clk    = clk;

   oh_lfsr #(.N(N))
   oh_lfsr (// outputs
	    .out      (dut_status[N-1:0] ),
	    // inputs
	    .taps     (ctrl[N-1:0]),
	    .seed     (seed[N-1:0]),
	    .en	      (1'b1),
	    .clk      (clk),
	    .nreset   (nreset));

endmodule // tb
module dv_top ();
   parameter DW       = 64;        // Memory width
   parameter MAW      = 15;        // Memory address width

   //regs/wires
   reg [1023:0] filename;
   wire [DW-1:0] ext_packet;
   
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire			nreset;			// From dv_ctrl of dv_ctrl.v
   wire			start;			// From dv_ctrl of dv_ctrl.v
   wire			stim_access;		// From stimulus of stimulus.v
   wire			stim_done;		// From stimulus of stimulus.v
   wire [DW-1:0]	stim_packet;		// From stimulus of stimulus.v
   wire			vdd;			// From dv_ctrl of dv_ctrl.v
   wire			vss;			// From dv_ctrl of dv_ctrl.v
   // End of automatics

   assign test_done  = 1'b1;
   assign dut_active = 1'b1;
   //Reset and clocks
   dv_ctrl dv_ctrl(.clk1		(ext_clk),
		   .clk2		(dut_clk),
		   /*AUTOINST*/
		   // Outputs
		   .nreset		(nreset),
		   .start		(start),
		   .vdd			(vdd),
		   .vss			(vss),
		   // Inputs
		   .dut_active		(dut_active),
		   .stim_done		(stim_done),
		   .test_done		(test_done));

   //Stimulus
   assign ext_start   = start;
   assign ext_access  = 'b0;
   assign ext_packet  = 'b0;
   assign dut_wait    = 'b0;

   
   stimulus #(.DW(DW),.MAW(MAW),.HEXFILE("firmware.hex"))
   stimulus(
		     /*AUTOINST*/
	    // Outputs
	    .stim_access		(stim_access),
	    .stim_packet		(stim_packet[DW-1:0]),
	    .stim_done			(stim_done),
	    // Inputs
	    .nreset			(nreset),
	    .ext_start			(ext_start),
	    .ext_clk			(ext_clk),
	    .ext_access			(ext_access),
	    .ext_packet			(ext_packet[DW-1:0]),
	    .dut_clk			(dut_clk),
	    .dut_wait			(dut_wait));
   

endmodule // unmatched end(function|task|module|primitive|interface|package|class|clocking)
module testbench
  #(parameter PW             = 256,         // packet total width
    parameter CW             = 16,          // packet control width
    parameter N              = 32,          // ctrl/status width
    parameter DEPTH          = 8192,        // simulus memory depth
    parameter TARGET         = "DEFAULT"    // physical synthesis/sim target
    )
   (
    // control signals to drive
    input 	    nreset, // async active low reset
    input 	    clk, // core clock
    input 	    fastclk, // fast clock
    input 	    slowclk, //slow clock
    input [2:0]     mode, //0=idle,1=load,2=go,3=rng,4=bypass
    input [N-1:0]   ctrl, // generic ctrl vector
    input [N-1:0]  seed, // seed(s) for rng
    // external write interface
    input 	    ext_clk, //ext packet clock
    input 	    ext_valid, // ext valid signal
    input [PW-1:0]  ext_packet, // ext packet
    input 	    ext_ready, // external ready to receive
    // dut response packets
    output 	    dut_clk, // due packet clock
    output 	    dut_valid, //dut packet valid signal
    output [PW-1:0] dut_packet, // dut packet to drive
    output 	    dut_ready, // dut is ready for packet
    // dut status interface
    output [N-1:0]  dut_status, // generic status vector
    output 	    dut_error,// dut error flag (leads to failure)
    output 	    dut_done, // test done
    output 	    dut_fail  // test failed
    );

endmodule // testbench
module dut(/*AUTOARG*/
   // Outputs
   dut_active, clkout, wait_out, access_out, packet_out,
   // Inputs
   clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
   );

   parameter N  = 1;
   parameter PW = 104;
      
   //clock, reset
   input            clk1;
   input            clk2;
   input            nreset;
   input [N*N-1:0]  vdd;
   input 	    vss;
   output 	    dut_active;
   output 	    clkout;
   
   //Stimulus Driven Transaction
   input [N-1:0]     access_in;
   input [N*PW-1:0]  packet_in;
   output [N-1:0]    wait_out;

   //DUT driven transactoin
   output [N-1:0]    access_out;
   output [N*PW-1:0] packet_out;
   input [N-1:0]     wait_in;

   /*AUTOINPUT*/
   /*AUTOOUTPUT*/
   /*AUTOWIRE*/
    

   //tie offs for Dv
   assign dut_active   = 1'b1;
   assign wait_out     = 1'b0;
   assign clk          = clk1;   
   
   oh_clockdiv oh_clockdiv (.clkout	(clkout),
			    .clkout90	(clkout90),
			    .clk	(clk),
			    .nreset     (nreset),
			    .en		(1'b1),
			    .divcfg	(packet_in[11:8])
			    );
   
   
endmodule // dv_elink
module dut(/*AUTOARG*/
   // Outputs
   dut_active, clkout, wait_out, access_out, packet_out,
   // Inputs
   clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
   );

   parameter N  = 1;
   parameter PW = 104;
      
   //clock, reset
   input            clk1;
   input            clk2;
   input            nreset;
   input [N*N-1:0]  vdd;
   input 	    vss;
   output 	    dut_active;
   output 	    clkout;
   
   //Stimulus Driven Transaction
   input [N-1:0]     access_in;
   input [N*PW-1:0]  packet_in;
   output [N-1:0]    wait_out;

   //DUT driven transactoin
   output [N-1:0]    access_out;
   output [N*PW-1:0] packet_out;
   input [N-1:0]     wait_in;

   /*AUTOINPUT*/
   /*AUTOOUTPUT*/
   /*AUTOWIRE*/
    

   //tie offs for Dv
   assign dut_active   = 1'b1;
   assign wait_out     = 1'b0;
   assign clk          = clk1;
   assign clkout       = clk2;
   
   oh_debouncer #(.CLKPERIOD(10))   
   oh_debouncer (.clean_out  (clean_out),
		 .nreset     (nreset),
		 .clk	     (clk),
		 .noisy_in   (packet_in[PW-1])
		 );
   
endmodule // dv_elink
module testbench();

   localparam N = 32;

   /*AUTOINPUT*/
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire			clk1;			// From oh_simctrl of oh_simctrl.v
   wire			clk2;			// From oh_simctrl of oh_simctrl.v
   wire			nreset;			// From oh_simctrl of oh_simctrl.v
   wire			out;			// From oh_pulse of oh_pulse.v
   wire			start;			// From oh_simctrl of oh_simctrl.v
   wire			vdd;			// From oh_simctrl of oh_simctrl.v
   wire			vss;			// From oh_simctrl of oh_simctrl.v
   // End of automatics

   oh_pulse #(.N(N))
   oh_pulse(.en		(1'b1),
	    .clk	(clk1),
	    .mask	(32'h0000000f),
	     /*AUTOINST*/
	    // Outputs
	    .out			(out),
	    // Inputs
	    .nreset			(nreset));

   oh_simctrl oh_simctrl(//TODO: implement
			.stim_done	(1'b0),
			.test_done	(1'b0),
			.test_diff	(1'b0),
			.dut_active     (1'b1),
			/*AUTOINST*/
			 // Outputs
			 .nreset		(nreset),
			 .clk1			(clk1),
			 .clk2			(clk2),
			 .start			(start),
			 .vdd			(vdd),
			 .vss			(vss));

endmodule // tb
module oh_simctrl
  #(parameter TIMEOUT         = 5000, // timeout value (cycles)
    parameter PERIOD_CLK      = 10,   // core clock period
    parameter PERIOD_FASTCLK  = 10,   // fast clock period
    parameter PERIOD_SLOWCLK  = 10,   // slow clock period
    parameter RANDOM_CLK       = 0,   // randomize clock
    parameter RANDOM_DATA      = 0    // randomize data
    )
   (
    //control signals to drive
    output reg 	     nreset, // async active low reset
    output reg 	     clk, // main clock
    output reg 	     fastclk, // second(fast) clock
    output reg 	     slowclk, // third (slow) clock
    output reg [2:0] mode, //0=idle,1=load,2=go,3=rng,4=bypass
    //input from testbench
    input 	     dut_fail, // dut fail indicator
    input 	     dut_done // dut/tb signaled done
    );

   // TODO: parametrize?
   localparam TIME_RESET = 50;
   localparam TIME_WAIT  = 50;
   localparam TIME_LOAD  = 50;

   //signal declarations
   reg [6:0]   clk_phase;
   reg [6:0]   fastclk_phase;
   reg [6:0]   slowclk_phase;
   integer     seed, r;
   wire [2:0]  gomode;

   //#################################
   // CONFIGURATION
   //#################################

   initial
     begin
	$timeformat(-9, 0, " ns", 20);
     end

   //#################################
   // RESET/STARTUP SEQUENCE
   //#################################
   generate
      if (RANDOM_DATA)
	assign gomode = 3'b011;//rng
      else
  	assign gomode = 3'b010;//stim data
   endgenerate

   initial
     begin
	#(1)
	nreset   = 'b0;
	clk      = 'b0;
	fastclk  = 'b0;
	slowclk  = 'b0;
	mode     = 3'b0;
	#(clk_phase * TIME_RESET)  //hold reset a while
	nreset   = 'b1;
	#(clk_phase * TIME_WAIT)
	mode     = 3'b001;    // load stimulus
	#(clk_phase * TIME_LOAD)
	mode     = gomode;
     end // initial begin

   //#################################
   // CLK GENERATORS
   //#################################

   generate
      if (RANDOM_CLK) begin
	 initial
	   begin
	      //TODO: improve
	      clk_phase     = $urandom_range(50,50);
	      fastclk_phase = $urandom_range(500,50);
	      slowclk_phase = $urandom_range(50,1);
	   end
      end
      else begin
	 initial begin
	    clk_phase     = PERIOD_CLK/2;
	    fastclk_phase = PERIOD_FASTCLK/2;
	    slowclk_phase = PERIOD_SLOWCLK/2;
	 end
      end
   endgenerate

   always
     #(clk_phase) clk = ~clk;

   always
     #(fastclk_phase) fastclk = ~fastclk;

   always
     #(slowclk_phase) slowclk = ~slowclk;

   //#################################
   // END OF TEST
   //#################################

   always @ (posedge clk)
     if(dut_done)
       begin
	  #500
	    if(dut_fail)
	      $display("[OH] DUT TEST FAILED");
	    else
	      $display("[OH] DUT TEST PASSED");
	  $finish;
       end

   //#################################
   // TIMEOUT
   //#################################
   initial
     begin
	#(TIMEOUT)
	$display("[OH] DUT TEST TIMEOUT");
	$finish;
     end

endmodule
module oh_mux12
  #(parameter N = 1 ) // width of mux
   (
    input 	    sel11,
    input 	    sel10,
    input 	    sel9,
    input 	    sel8,
    input 	    sel7,
    input 	    sel6,
    input 	    sel5,
    input 	    sel4,
    input 	    sel3,
    input 	    sel2,
    input 	    sel1,
    input 	    sel0,
    input [N-1:0]  in11,
    input [N-1:0]  in10,
    input [N-1:0]  in9,
    input [N-1:0]  in8,
    input [N-1:0]  in7,
    input [N-1:0]  in6,
    input [N-1:0]  in5,
    input [N-1:0]  in4,
    input [N-1:0]  in3,
    input [N-1:0]  in2,
    input [N-1:0]  in1,
    input [N-1:0]  in0,
    output [N-1:0] out //selected data output
    );

   assign out[N-1:0] = ({(N){sel0}}  & in0[N-1:0] |
			 {(N){sel1}}  & in1[N-1:0] |
			 {(N){sel2}}  & in2[N-1:0] |
			 {(N){sel3}}  & in3[N-1:0] |
			 {(N){sel4}}  & in4[N-1:0] |
			 {(N){sel5}}  & in5[N-1:0] |
			 {(N){sel6}}  & in6[N-1:0] |
			 {(N){sel7}}  & in7[N-1:0] |
			 {(N){sel8}}  & in8[N-1:0] |
			 {(N){sel9}}  & in9[N-1:0] |
			 {(N){sel10}} & in10[N-1:0] |
			 {(N){sel11}} & in11[N-1:0]);

endmodule // oh_mux12
module oh_oai311 #(parameter DW = 1 ) // array width
   (
    input [DW-1:0]  a0,
    input [DW-1:0]  a1,
    input [DW-1:0]  a2,
    input [DW-1:0]  b0,
    input [DW-1:0]  c0, 
    output [DW-1:0] z
    );
   
   assign z = ~((a0 | a1 | a2) & b0 & c0);
   
endmodule
module oh_mx3 #(parameter DW = 1 ) // array width
   (
    input [DW-1:0]  d0,
    input [DW-1:0]  d1,
    input [DW-1:0]  d2,
    input [DW-1:0]  s0,
    input [DW-1:0]  s1,
    output [DW-1:0] z
    );
   
   assign z = (d0 & ~s0 & ~s1) |
	      (d1 & s0  & ~s1) |
	      (d2 & s1);
   
endmodule
module oh_fall2pulse
  #( parameter N = 1) //data width
   (
    input 	   clk, // clock
    input 	   nreset, // async active low reset
    input [N-1:0]  in, // edge input
    output [N-1:0] out     // one cycle pulse
    );

   reg [N-1:0] 	   in_reg;

   always @ (posedge clk or negedge nreset)
     if(!nreset)
       in_reg[N-1:0] <= 'b0 ;
     else
       in_reg[N-1:0] <= in[N-1:0] ;

   assign out[N-1:0] = ~in[N-1:0] & in_reg[N-1:0] ;

endmodule // oh_fall2pulse
module oh_lat1
  #(parameter N    = 1,        // number of sync stages
    parameter SYN  = "TRUE",   // synthesizable (or not)
    parameter TYPE = "DEFAULT" // scell type/size
    )
   (input 	   clk, // clk
    input [N-1:0]  in,  // input data
    output [N-1:0] out  // output data
    );

   generate
      if(SYN == "TRUE") begin
	 reg [N-1:0]      out_reg;
	 always @ (clk or in)
	   if (clk)
	     out_reg[N-1:0] <= in[N-1:0];

	 assign out[N-1:0] = out_reg[N-1:0];
      end
      else begin
	 for (i=0;i<N;i=i+1) begin
	    asic_lat1 #(.TYPE(TYPE))
	    asic_lat1 (.clk(clk),
		       .in(in[i]),
		       .out(out[i]));
	 end
      end
   endgenerate

endmodule // oh_lat1
module oh_mux4 #(parameter N = 1 ) // width of mux
   (
    input 	   sel3,
    input 	   sel2,
    input 	   sel1,
    input 	   sel0,
    input [N-1:0]  in3,
    input [N-1:0]  in2,
    input [N-1:0]  in1,
    input [N-1:0]  in0,
    output [N-1:0] out  //selected data output
    );

   assign out[N-1:0] = ({(N){sel0}} & in0[N-1:0] |
			{(N){sel1}} & in1[N-1:0] |
			{(N){sel2}} & in2[N-1:0] |
			{(N){sel3}} & in3[N-1:0]);

`ifdef TARGET_SIM
   wire 	    error;
   assign error = (sel0 | sel1 | sel2 | sel3) &
   		  ~(sel0 ^ sel1 ^ sel2 ^ sel3);
   always @ (posedge error)
     begin
	#1 if(error)
	  $display ("ERROR at in oh_mux4 %m at ",$time);
     end
`endif
endmodule // oh_mux4
module oh_or2 #(parameter DW = 1 ) // array width
   (
    input [DW-1:0]  a,
    input [DW-1:0]  b,
    output [DW-1:0] z
    );
   
   assign z = ( a | b);
   
endmodule
module oh_dsync
  #(parameter SYNCPIPE = 2,        // number of sync stages
    parameter DELAY    = 0,        // random delay
    parameter TARGET   = "DEFAULT" // scell type/size
    )
   (
    input  clk, // clock
    input  nreset, // clock
    input  din, // input data
    output dout    // synchronized data
    );

   generate
      if(TARGET == "DEFAULT")	begin
	 reg [SYNCPIPE:0] sync_pipe;
	 always @ (posedge clk or negedge nreset)
	   if(!nreset)
	     sync_pipe[SYNCPIPE:0] <= 'b0;
	   else
	     sync_pipe[SYNCPIPE:0] <= {sync_pipe[SYNCPIPE-1:0],din};
	 // drive randomize delay from testbench
	 assign dout = (DELAY & sync_pipe[SYNCPIPE]) |  //extra cycle
		       (~DELAY & sync_pipe[SYNCPIPE-1]); //default
      end // block: reg
      else
	begin
	   asic_dsync  #(.TARGET(TARGET),
			 .SYNCPIPE(SYNCPIPE))
	   asic_dsync (.clk(clk),
		       .nreset(nreset),
		       .din(din),
		       .dout(dout));
	end
   endgenerate
endmodule // oh_dsync
module oh_aoi211 #(parameter DW = 1 ) // array width
   (
    input [DW-1:0]  a0,
    input [DW-1:0]  a1,
    input [DW-1:0]  b0,
    input [DW-1:0]  c0, 
    output [DW-1:0] z
    );
   
   assign z = ~((a0 & a1) | b0 | c0);
   
endmodule
module oh_aoi21 #(parameter DW = 1 ) // array width
   (
    input [DW-1:0]  a0,
    input [DW-1:0]  a1,
    input [DW-1:0]  b0, 
    output [DW-1:0] z
    );
   
   assign z = ~((a0 & a1) | b0);
   
endmodule
module oh_ao311 #(parameter DW = 1 ) // array width
   (
    input [DW-1:0]  a0,
    input [DW-1:0]  a1,
    input [DW-1:0]  a2,
    input [DW-1:0]  b0,
    input [DW-1:0]  c0, 
    output [DW-1:0] z
    );
   
   assign z = (a0 & a1 & a2) | b0 | c0;
   
endmodule
module oh_and4 #(parameter DW = 1 ) // array width
   (
    input [DW-1:0]  a,
    input [DW-1:0]  b,
    input [DW-1:0]  c,
    input [DW-1:0]  d, 
    output [DW-1:0] z
    );
   
   assign z = (a&b&c&d);
   
endmodule
module oh_debouncer
  #( parameter BOUNCE    = 100,      // bounce time (s)
     parameter FREQUENCY = 1000000,  // clock frequency (1Mhz)
     parameter SYN       = "TRUE",   // synthesizable (or not)
     parameter TYPE      = "DEFAULT" // scell type/size
     )
   (
    input  clk, // clock to synchronize to
    input  nreset, // syncronous active high reset
    input  noisy_in, // noisy input signal to filter
    output clean_out // clean signal to logic
    );

   parameter integer COUNTER_WIDTH  = $clog2(BOUNCE*FREQUENCY);

   //regs
   reg 	  noisy_reg;
   reg 	  clean_reg;

   // synchronize incoming signal
   oh_dsync #(.SYN(SYN),
	      .TYPE(TYPE))
   dsync (.dout   (noisy_synced),
	  .clk    (clk),
	  .nreset (nreset),
	  .din	  (noisy_in));

   // synchronize reset to clk
   oh_rsync #(.SYN(SYN),
	      .TYPE(TYPE))
   rsync (.nrst_out (nreset_synced),
	  .clk	    (clk),
	  .nrst_in  (nreset));

   // detecting change in state on input
   always @ (posedge clk or negedge nreset)
     if(!nreset)
       noisy_reg <= 1'b0;
     else
       noisy_reg <= noisy_synced;

   assign change_detected = noisy_reg ^ noisy_synced;

   // synchronous counter "filter"
   oh_counter #(.N(COUNTER_WIDTH),
		.SYN(SYN),
		.TYPE(TYPE))
   oh_counter (// Outputs
	       .count	   (),
	       .wraparound (wraparound),
	       // Inputs
	       .clk	   (clk),
	       .in	   (1'b1),
	       .dec        (1'b0),
	       .en	   (1'b1),
	       .autowrap   (1'b0),
	       .load  	   (change_detected | ~nreset_synced),
	       .load_data  ({(COUNTER_WIDTH){1'b0}})
	       );

   // sample noisy signal safely
   always @ (posedge clk or negedge nreset)
     if(!nreset)
       clean_reg <= 'b0;
     else if(wraparound)
       clean_reg <= noisy_reg;

   assign clean_out = clean_reg;

endmodule // oh_debouncer
module oh_pulse2pulse
  #(parameter SYN      = "TRUE",   // true=synthesizable
    parameter TYPE     = "DEFAULT" // scell type/size
    )
   (
   input  nrstin, //input domain reset
   input  din, //input pulse (one clock cycle)
   input  clkin, //input clock
   input  nrstout, //output domain reset
   input  clkout, //output clock
   output dout    //output pulse (one clock cycle)
   );

   // local wires
   reg 	  toggle_reg;
   reg 	  pulse_reg;
   wire   toggle;

   //pulse to toggle
   assign toggle = din ? ~toggle_reg : toggle_reg;

   always @ (posedge clkin)
     if(~nrstin)
       toggle_reg <= 1'b0;
     else
       toggle_reg <= toggle;

   //metastability synchronizer
   oh_dsync #(.TYPE(TYPE),
	      .SYN(SYN))
   sync(.dout	(toggle_sync),
	.din      (toggle),
	.nreset   (nrstout),
	.clk      (clkout));

   //toogle to pulse
   always @ (posedge clkout)
     if(!nrstout)
       pulse_reg <= 1'b0;
     else
       pulse_reg <= toggle_sync;

   assign dout = pulse_reg ^ toggle_sync;

endmodule // oh_pulse2pulse
module oh_nor3 #(parameter DW = 1 ) // array width
   (
    input [DW-1:0]  a,
    input [DW-1:0]  b,
    input [DW-1:0]  c,
    output [DW-1:0] z
    );
   
   assign z = ~(a | b | c);
   
endmodule
module oh_oai22 #(parameter DW = 1 ) // array width
   (
    input [DW-1:0]  a0,
    input [DW-1:0]  a1,
    input [DW-1:0]  b0,
    input [DW-1:0]  b1, 
    output [DW-1:0] z
    );
   
   assign z = ~((a0 | a1) & (b0 | b1));
   
endmodule
module oh_aoi22 #(parameter DW = 1 ) // array width
   (
    input [DW-1:0]  a0,
    input [DW-1:0]  a1,
    input [DW-1:0]  b0,
    input [DW-1:0]  b1,
    output [DW-1:0] z
    );
   
   assign z = ~((a0 & a1) | (b0 & b1));
   
endmodule
module oh_lfsr
  #(parameter N    =  32,      // length of LFSR
    parameter TYPE = "GALOIS"  // lfsr type (only galois supported ...)
    )
   (
    input 	       clk,
    input 	       nreset, //async reset
    input 	       en, // enables (advances) lfsr
    input [N-1:0]      taps, // taps
    input [N-1:0]      seed, // seed
    output reg [N-1:0] out  // output value/state vector
    );

   generate
      if (TYPE == "GALOIS") begin
	 always @ (posedge clk or negedge nreset)
	   if(~nreset)
	     out[N-1:0] <= seed[N-1:0];
	   else if(en)
	     out[N-1:0] <= ({(N){out[0]}} & taps[N-1:0]) ^
	                   (out[N-1:0] >> 1);
      end
      else if (TYPE == "FIBONACCI") begin
	 initial
	   $display("UNSUPPORTED");
      end
   endgenerate

endmodule // oh_lfsr
module oh_xor4 #(parameter DW = 1 ) // array width
   (
    input [DW-1:0]  a,
    input [DW-1:0]  b,
    input [DW-1:0]  c,
    input [DW-1:0]  d,
    output [DW-1:0] z
    );
   
   assign z =  a ^ b ^ c ^ d;
   
endmodule
module oh_inv #(parameter DW = 1 ) // array width
   (
    input [DW-1:0]  a,
    output [DW-1:0] z
    );
   
   assign z = ~a;
      
endmodule
module oh_aoi31 #(parameter DW = 1 ) // array width
   (
    input [DW-1:0]  a0,
    input [DW-1:0]  a1,
    input [DW-1:0]  a2,
    input [DW-1:0]  b0, 
    output [DW-1:0] z
    );
   
   assign z = ~((a0 & a1 & a2) | b0);
   
endmodule