dakies/OSS_Verilog huggingface dataset:
module iuq_cpl_itag( inc, i, o);
   parameter         SIZE = 7;
   parameter         WRAP = 40;

   input [0:1]       inc;
   input [0:SIZE-1]  i;

   output [0:SIZE-1] o;

   wire [1:SIZE]     a;
   wire [1:SIZE]     b;
   wire [1:SIZE]     rslt;
   wire              rollover;
   wire              rollover_m1;
   wire              inc_1;
   wire              inc_2;
   wire [0:1]        wrap_sel;


   (* analysis_not_referenced="true" *)

   wire 	     unused;
   // Increment by 1 or 2.
   // Go back to zero at WRAP
   // Flip bit zero when a rollover occurs
   // eg 0...39, 64..103
   assign unused = rslt[SIZE];

   assign a = {i[1:SIZE - 1], inc[1]};
   assign b = {{SIZE-2{1'b0}},{inc[0], inc[1]}};
   assign rslt = a + b;

   assign rollover = {{32-SIZE+1{1'b0}},i[1:SIZE - 1]} == WRAP;
   assign rollover_m1 = {{32-SIZE+1{1'b0}},i[1:SIZE - 1]} == WRAP - 1;

   assign inc_1 = inc[0] ^ inc[1];
   assign inc_2 = inc[0] & inc[1];

   assign wrap_sel[0] = (rollover & inc_1) | (rollover_m1 & inc_2);
   assign wrap_sel[1] = rollover & inc_2;

   assign o[0] = i[0] ^ |(wrap_sel);

   assign o[1:SIZE-1] = (wrap_sel[0:1] == 2'b10) ? {SIZE-1{1'b0}} :
                        (wrap_sel[0:1] == 2'b01) ? {{SIZE-2{1'b0}},{1'b1}} :
                         rslt[1:SIZE-1];

endmodule
module iuq_rn_map_inc #(
   	parameter         SIZE = 7,
   	parameter         WRAP = 40)
   (
	   inc,
	   i,
	   o
	);
   input [0:1]       inc;
   input [0:SIZE-1]  i;

   output [0:SIZE-1] o;

   localparam [0:31]         value_1 = 32'h00000001;

   wire [0:SIZE]     a;
   wire [0:SIZE]     b;
   wire [0:SIZE]     rslt;
   wire              rollover;
   wire              rollover_m1;
   wire              inc_1;
   wire              inc_2;
   wire [0:1]        wrap_sel;

   // Increment by 1 or 2.
   // Go back to zero at WRAP
   // Flip bit zero when a rollover occurs
   // eg 0...39, 64..103

   assign a = {i[0:SIZE - 1], inc[1]};
   assign b = {{SIZE-1{1'b0}}, inc[0], inc[1]};
   assign rslt = a + b;

   assign rollover = i[0:SIZE - 1] == WRAP;
   assign rollover_m1 = i[0:SIZE - 1] == WRAP - 1;

   assign inc_1 = inc[0] ^ inc[1];
   assign inc_2 = inc[0] & inc[1];

   assign wrap_sel[0] = (rollover & inc_1) | (rollover_m1 & inc_2);
   assign wrap_sel[1] = rollover & inc_2;

   assign o[0:SIZE - 1] = (wrap_sel[0:1] == 2'b10) ? {SIZE{1'b0}} :
                          (wrap_sel[0:1] == 2'b01) ? value_1[32-SIZE:31] :
                          rslt[0:SIZE - 1];

endmodule
module iuq_cpl_ctrl_inc(
   inc,
   i,
   o
);
`include "tri_a2o.vh"
   parameter         SIZE = 7;
   parameter         WRAP = 40;
   input [0:1]       inc;
   input [0:SIZE-1]  i;

   output [0:SIZE-1] o;

      wire [1:SIZE]     a;
      wire [1:SIZE]     b;
      wire [1:SIZE]     rslt;
      wire              rollover;
      wire              rollover_m1;
      wire              inc_1;
      wire              inc_2;
      wire [0:1]        wrap_sel;

      // Increment by 1 or 2.
      // Go back to zero at WRAP
      // Flip bit zero when a rollover occurs
      // eg 0...39, 64..103

      assign a = {i[1:SIZE - 1], inc[1]};
      assign b = {1'b0, inc[0], inc[1]};
      assign rslt = a + b;

      assign rollover = i[1:SIZE - 1] == WRAP;
      assign rollover_m1 = i[1:SIZE - 1] == WRAP - 1;

      assign inc_1 = inc[0] ^ inc[1];
      assign inc_2 = inc[0] & inc[1];

      assign wrap_sel[0] = (rollover & inc_1) | (rollover_m1 & inc_2);
      assign wrap_sel[1] = rollover & inc_2;

      assign o[0] = i[0] ^ |(wrap_sel);

      assign o[1:SIZE - 1] = (wrap_sel[0:1] == 2'b10) ? 0 :
                             (wrap_sel[0:1] == 2'b01) ? 1 :
                             rslt[1:SIZE - 1];

endmodule
module xu0_bcd_dtbcd(
   input [0:9]   a,
   output [0:11] y
);

   assign y[0]  = ((~a[3]) & a[6] & a[7]) | (a[4] & a[6] & a[7] & a[3]) | (a[6] & a[7] & (~a[8]));
   assign y[1]  = (a[0] & a[3] & a[8] & (~a[4])) | (a[0] & (~a[7])) | (a[0] & (~a[6]));
   assign y[2]  = (a[1] & a[3] & a[8] & (~a[4])) | (a[1] & (~a[7])) | (a[1] & (~a[6]));
   assign y[3]  = a[2];
   assign y[4]  = (a[6] & (~a[7]) & a[8]) | (a[3] & a[6] & a[7] & a[8]) | ((~a[4]) & a[6] & a[8] & a[7]);
   assign y[5]  = (a[0] & a[4] & a[6] & a[7] & a[8] & (~a[3])) | (a[3] & (~a[8]) & a[6]) | (a[3] & (~a[6]));
   assign y[6]  = (a[1] & a[4] & a[7] & a[6] & a[8] & (~a[3])) | (a[4] & (~a[8]) & a[6]) | (a[4] & (~a[6]));
   assign y[7]  = a[5];
   assign y[8]  = (a[4] & a[6] & a[7] & a[8]) | (a[3] & a[6] & a[7] & a[8]) | (a[6] & (~a[7]) & (~a[8]));
   assign y[9]  = (a[0] & (~a[3]) & (~a[4]) & a[7] & a[6]) | (a[3] & a[6] & (~a[7]) & a[8]) | (a[0] & a[7] & (~a[8]) & a[6]) | (a[7] & (~a[6]));
   assign y[10] = (a[1] & (~a[3]) & (~a[4]) & a[6] & a[7]) | (a[4] & a[6] & (~a[7]) & a[8]) | (a[1] & a[6] & a[7] & (~a[8])) | (a[8] & (~a[6]));
   assign y[11] = a[9];

endmodule
module rv_rpri(
	       cond,
	       pri
	       );
   parameter         size = 32;
   input [0:size-1]  cond;
   output [0:size-1] pri;

   parameter         s = size - 1;
   wire [0:s] 	     or_l1;
   wire [0:s] 	     or_l2;
   wire [0:s] 	     or_l3;
   wire [0:s] 	     or_l4;
 (* analysis_not_referenced="<0>true" *)
   wire [0:s] 	     or_l5;

   // Odd Numbered Levels are inverted

   assign or_l1[s] = (~cond[s]);
   assign or_l1[0:s - 1] = ~(cond[0:s - 1] | cond[1:s]);

   generate
      if (s >= 2)
        begin : or_l2_gen0
           assign or_l2[s - 1:s] = (~or_l1[s - 1:s]);
           assign or_l2[0:s - 2] = ~(or_l1[2:s] & or_l1[0:s - 2]);
        end
   endgenerate
   generate
      if (s < 2)
        begin : or_l2_gen1
           assign or_l2 = (~or_l1);
        end
   endgenerate

   generate
      if (s >= 4)
        begin : or_l3_gen0
           assign or_l3[s - 3:s] = (~or_l2[s - 3:s]);
           assign or_l3[0:s - 4] = ~(or_l2[4:s] | or_l2[0:s - 4]);
        end
   endgenerate
   generate
      if (s < 4)
        begin : or_l3_gen1
           assign or_l3 = (~or_l2);
        end
   endgenerate

   generate
      if (s >= 8)
        begin : or_l4_gen0
           assign or_l4[s - 7:s] = (~or_l3[s - 7:s]);
           assign or_l4[0:s - 8] = ~(or_l3[8:s] & or_l3[0:s - 8]);
        end
   endgenerate
   generate
      if (s < 8)
        begin : or_l4_gen1
           assign or_l4 = (~or_l3);
        end
   endgenerate

   generate
      if (s >= 16)
        begin : or_l5_gen0
           assign or_l5[s - 15:s] = (~or_l4[s - 15:s]);
           assign or_l5[0:s - 16] = ~{or_l4[16:s] | or_l4[0:s - 16]};
        end
   endgenerate
   generate
      if (s < 16)
        begin : or_l5_gen1
           assign or_l5 = (~or_l4);
        end
   endgenerate

   //assert size > 32 report "Maximum Size of 32 Exceeded!" severity error;

   assign pri[s] = cond[s];
   assign pri[0:s - 1] = cond[0:s - 1] & or_l5[1:s];

endmodule
module lq_spr_dacen(
   spr_msr_pr,
   spr_msr_ds,
   spr_dbcr0_dac,
   spr_dbcr_dac_us,
   spr_dbcr_dac_er,
   val,
   load,
   store,
   dacr_en,
   dacw_en
);

//-------------------------------------------------------------------
// Generics
//-------------------------------------------------------------------
//parameter            `THREADS = 4;

input [0:`THREADS-1]  spr_msr_pr;
input [0:`THREADS-1]  spr_msr_ds;

input [0:2*`THREADS-1]  spr_dbcr0_dac;
input [0:2*`THREADS-1]  spr_dbcr_dac_us;
input [0:2*`THREADS-1]  spr_dbcr_dac_er;

input [0:`THREADS-1]  val;
input                 load;
input                 store;

output [0:`THREADS-1] dacr_en;
output [0:`THREADS-1] dacw_en;

// Signals
wire [0:1]            spr_dbcr0_dac_tid[0:`THREADS-1];
wire [0:1]            spr_dbcr_dac_us_tid[0:`THREADS-1];
wire [0:1]            spr_dbcr_dac_er_tid[0:`THREADS-1];
wire [0:`THREADS-1]   dac_ld_en;
wire [0:`THREADS-1]   dac_st_en;
wire [0:`THREADS-1]   dac_us_en;
wire [0:`THREADS-1]   dac_er_en;

generate begin : sprTid
   genvar tid;
   for (tid=0; tid<`THREADS; tid=tid+1) begin : sprTid
      assign spr_dbcr0_dac_tid[tid]   = spr_dbcr0_dac[tid*2:tid*2+1];
      assign spr_dbcr_dac_us_tid[tid] = spr_dbcr_dac_us[tid*2:tid*2+1];
      assign spr_dbcr_dac_er_tid[tid] = spr_dbcr_dac_er[tid*2:tid*2+1];
   end
end
endgenerate

generate begin : dacen_gen
      genvar               t;
      for (t = 0; t <= `THREADS - 1; t = t + 1) begin : dacen_gen
         assign dac_ld_en[t] = spr_dbcr0_dac_tid[t][0] & load;
         assign dac_st_en[t] = spr_dbcr0_dac_tid[t][1] & store;

         assign dac_us_en[t] = ((~spr_dbcr_dac_us_tid[t][0]) & (~spr_dbcr_dac_us_tid[t][1])) | (spr_dbcr_dac_us_tid[t][0] & (spr_dbcr_dac_us_tid[t][1] ~^ spr_msr_pr[t]));

         assign dac_er_en[t] = ((~spr_dbcr_dac_er_tid[t][0]) & (~spr_dbcr_dac_er_tid[t][1])) | (spr_dbcr_dac_er_tid[t][0] & (spr_dbcr_dac_er_tid[t][1] ~^ spr_msr_ds[t]));
         assign dacr_en[t] = val[t] & dac_ld_en[t] & dac_us_en[t] & dac_er_en[t];
         assign dacw_en[t] = val[t] & dac_st_en[t] & dac_us_en[t] & dac_er_en[t];
      end
   end
endgenerate

endmodule
module lq_agen_glbloc(
   x_b,
   y_b,
   g08,
   t08
);

input [0:7]     x_b;
input [0:7]     y_b;

output          g08;

output          t08;

wire [0:7]      g01;

wire [0:7]      t01;

wire [0:3]      g02_b;

wire [0:3]      t02_b;

wire [0:1]      g04;

wire [0:1]      t04;

wire            g08_b;

wire            t08_b;

//assign g01[0] = (~(x_b[0] | y_b[0]));
tri_nor2 #(.WIDTH(8)) g01_0 (.y(g01[0:7]), .a(x_b[0:7]), .b(y_b[0:7]));

//assign t01[0] = (~(x_b[0] & y_b[0]));
tri_nand2 #(.WIDTH(8)) t01_0 (.y(t01[0:7]), .a(x_b[0:7]), .b(y_b[0:7]));

//assign g02_b[0] = (~(g01[0] | (t01[0] & g01[1])));
tri_aoi21 g02_b_0 (.y(g02_b[0]), .a0(t01[0]), .a1(g01[1]), .b0(g01[0]));

//assign g02_b[1] = (~(g01[2] | (t01[2] & g01[3])));
tri_aoi21 g02_b_1 (.y(g02_b[1]), .a0(t01[2]), .a1(g01[3]), .b0(g01[2]));

//assign g02_b[2] = (~(g01[4] | (t01[4] & g01[5])));
tri_aoi21 g02_b_2 (.y(g02_b[2]), .a0(t01[4]), .a1(g01[5]), .b0(g01[4]));

//assign g02_b[3] = (~(g01[6] | (t01[6] & g01[7])));
tri_aoi21 g02_b_3 (.y(g02_b[3]), .a0(t01[6]), .a1(g01[7]), .b0(g01[6]));

//assign t02_b[0] = (~(t01[0] & t01[1]));
tri_nand2 t02_b_0 (.y(t02_b[0]), .a(t01[0]), .b(t01[1]));

//assign t02_b[1] = (~(t01[2] & t01[3]));
tri_nand2 t02_b_1 (.y(t02_b[1]), .a(t01[2]), .b(t01[3]));

//assign t02_b[2] = (~(t01[4] & t01[5]));
tri_nand2 t02_b_2 (.y(t02_b[2]), .a(t01[4]), .b(t01[5]));

//assign t02_b[3] = (~(t01[6] & t01[7]));
tri_nand2 t02_b_3 (.y(t02_b[3]), .a(t01[6]), .b(t01[7]));

//assign g04[0] = (~(g02_b[0] & (t02_b[0] | g02_b[1])));
tri_oai21 g04_0 (.y(g04[0]), .a0(t02_b[0]), .a1(g02_b[1]), .b0(g02_b[0]));

//assign g04[1] = (~(g02_b[2] & (t02_b[2] | g02_b[3])));
tri_oai21 g04_1 (.y(g04[1]), .a0(t02_b[2]), .a1(g02_b[3]), .b0(g02_b[2]));

//assign t04[0] = (~(t02_b[0] | t02_b[1]));
tri_nor2 t04_0 (.y(t04[0]), .a(t02_b[0]), .b(t02_b[1]));

//assign t04[1] = (~(t02_b[2] | t02_b[3]));
tri_nor2 t04_1 (.y(t04[1]), .a(t02_b[2]), .b(t02_b[3]));

//assign g08_b = (~(g04[0] | (t04[0] & g04[1])));
tri_aoi21 g08_b_0 (.y(g08_b), .a0(t04[0]), .a1(g04[1]), .b0(g04[0]));

//assign t08_b = (~((t04[0] & t04[1])));
tri_nand2 t08_b_0 (.y(t08_b), .a(t04[0]), .b(t04[1]));

//assign g08 = (~(g08_b));		// output
tri_inv g08_0 (.y(g08), .a(g08_b));

//assign t08 = (~(t08_b));		// output
tri_inv t08_0 (.y(t08), .a(t08_b));

endmodule
module lq_agen_csmux(
   sum_0,
   sum_1,
   ci_b,
   sum
);

input [0:7]     sum_0;		// after xor
input [0:7]     sum_1;
input           ci_b;

output [0:7]    sum;

wire [0:7]      sum0_b;

wire [0:7]      sum1_b;

wire            int_ci;

wire            int_ci_t;

wire            int_ci_b;

//assign int_ci = (~ci_b);
tri_inv int_ci_0 (.y(int_ci), .a(ci_b));

//assign int_ci_t = (~ci_b);
tri_inv int_ci_t_0 (.y(int_ci_t), .a(ci_b));

//assign int_ci_b = (~int_ci_t);
tri_inv int_ci_b_0 (.y(int_ci_b), .a(int_ci_t));

//assign sum0_b[0] = (~(sum_0[0] & int_ci_b));
tri_nand2 #(.WIDTH(8)) sum0_b_0 (.y(sum0_b[0:7]), .a(sum_0[0:7]), .b({8{int_ci_b}}));

//assign sum[0] = (~(sum0_b[0] & sum1_b[0]));
tri_nand2 #(.WIDTH(8)) sum0 (.y(sum[0:7]), .a(sum0_b[0:7]), .b(sum1_b[0:7]));

endmodule
module lq_spr_dvccmp(
   en,
   en00,
   cmp,
   dvcm,
   dvcbe,
   dvc_cmpr
);

//-------------------------------------------------------------------
// Generics
//-------------------------------------------------------------------
parameter			    REGSIZE = 64;

input			        en;
input			        en00;
input [8-(REGSIZE/8):7]	cmp;
input [0:1]			    dvcm;
input [8-(REGSIZE/8):7]	dvcbe;
output			        dvc_cmpr;

// Signals
wire [8-(REGSIZE/8):7]	cmp_mask_or;
wire [8-(REGSIZE/8):7]	cmp_mask_and;
wire				    cmp_and;
wire				    cmp_or;
wire				    cmp_andor;

assign cmp_mask_or = (cmp | (~dvcbe)) & {(REGSIZE/8){|(dvcbe)}};
assign cmp_mask_and = (cmp & dvcbe);

assign cmp_and = &(cmp_mask_or);

assign cmp_or = |(cmp_mask_and);

generate
  if (REGSIZE == 32) begin : cmp_andor_gen32
 	 assign cmp_andor = (&(cmp_mask_or[4:5]) & |(dvcbe[4:5])) |
 	                    (&(cmp_mask_or[6:7]) & |(dvcbe[6:7]));
  end
endgenerate

generate
  if (REGSIZE == 64) begin : cmp_andor_gen64
 	 assign cmp_andor = (&(cmp_mask_or[0:1]) & |(dvcbe[0:1])) |
 	                    (&(cmp_mask_or[2:3]) & |(dvcbe[2:3])) |
 	                    (&(cmp_mask_or[4:5]) & |(dvcbe[4:5])) |
 	                    (&(cmp_mask_or[6:7]) & |(dvcbe[6:7]));
  end
endgenerate

assign dvc_cmpr = (dvcm[0:1] == 2'b00) ?  en00          :
                  (dvcm[0:1] == 2'b01) ? (en & cmp_and) :
                  (dvcm[0:1] == 2'b10) ? (en & cmp_or)  :
                                         (en & cmp_andor);

endmodule
module xu0_dlmzb(
   // Inputs
   input [32:63]  byp_dlm_ex2_rs1,
   input [32:63]  byp_dlm_ex2_rs2,
   input [0:2]    byp_dlm_ex2_xer,

   // Outputs
   output [0:9]   dlm_byp_ex2_xer,
   output [0:3]   dlm_byp_ex2_cr,
   output [60:63] dlm_byp_ex2_rt
);


   wire [0:7]     a;
   wire [0:7]     a0;
   wire [0:7]     a1;
   wire [0:7]     a2;
   wire [0:3]     y;

   // Null == 0
   assign a[0] = |(byp_dlm_ex2_rs1[32:39]);
   assign a[1] = |(byp_dlm_ex2_rs1[40:47]);
   assign a[2] = |(byp_dlm_ex2_rs1[48:55]);
   assign a[3] = |(byp_dlm_ex2_rs1[56:63]);
   assign a[4] = |(byp_dlm_ex2_rs2[32:39]);
   assign a[5] = |(byp_dlm_ex2_rs2[40:47]);
   assign a[6] = |(byp_dlm_ex2_rs2[48:55]);
   assign a[7] = |(byp_dlm_ex2_rs2[56:63]);

   assign a0[1:7] = a[0:6] & a[1:7];
   assign a1[2:7] = a0[0:5] & a0[2:7];
   assign a2[4:7] = a1[0:3] & a1[4:7];

   assign a0[0:0] = a[0:0];
   assign a1[0:1] = a0[0:1];
   assign a2[0:3] = a1[0:3];

   assign y = (a2[0:7] == 8'b00000000) ? 4'b0001 : 		// Null in last  4B
              (a2[0:7] == 8'b10000000) ? 4'b0010 :
              (a2[0:7] == 8'b11000000) ? 4'b0011 :
              (a2[0:7] == 8'b11100000) ? 4'b0100 :
              (a2[0:7] == 8'b11110000) ? 4'b0101 :
              (a2[0:7] == 8'b11111000) ? 4'b0110 :
              (a2[0:7] == 8'b11111100) ? 4'b0111 :
              4'b1000;

   assign dlm_byp_ex2_cr[0] = (~a2[7]) & a2[3];
   assign dlm_byp_ex2_cr[1] = (~a2[7]) & (~a2[3]);		   // Null in first 4B
   assign dlm_byp_ex2_cr[2] = a2[7];		               // Null not found
   assign dlm_byp_ex2_cr[3] = byp_dlm_ex2_xer[0];		   // SO Copy

   assign dlm_byp_ex2_xer = {byp_dlm_ex2_xer[0:2], 3'b000, y[0:3]};

   assign dlm_byp_ex2_rt = y;

endmodule
module fu_alg_bypmux(
   ex3_byp_sel_byp_neg,
   ex3_byp_sel_byp_pos,
   ex3_byp_sel_neg,
   ex3_byp_sel_pos,
   ex3_prd_sel_neg_hi,
   ex3_prd_sel_neg_lo,
   ex3_prd_sel_neg_lohi,
   ex3_prd_sel_pos_hi,
   ex3_prd_sel_pos_lo,
   ex3_prd_sel_pos_lohi,
   ex3_sh_lvl3,
   f_fmt_ex3_pass_frac,
   f_alg_ex3_res
);
   //--------- BYPASS CONTROLS -----------------
   input          ex3_byp_sel_byp_neg;
   input          ex3_byp_sel_byp_pos;
   input          ex3_byp_sel_neg;
   input          ex3_byp_sel_pos;
   input          ex3_prd_sel_neg_hi;
   input          ex3_prd_sel_neg_lo;
   input          ex3_prd_sel_neg_lohi;
   input          ex3_prd_sel_pos_hi;
   input          ex3_prd_sel_pos_lo;
   input          ex3_prd_sel_pos_lohi;

   //--------- BYPASS DATA -----------------
   input [0:162]  ex3_sh_lvl3;
   input [0:52]   f_fmt_ex3_pass_frac;

   //-------- BYPASS OUTPUT ---------------
   output [0:162] f_alg_ex3_res;

   // ENTITY


   parameter      tiup = 1'b1;
   parameter      tidn = 1'b0;

   wire [0:162]   m0_b;
   wire [0:162]   m1_b;
   wire [0:162]   ex3_sh_lvl3_b;
   wire [0:52]    f_fmt_ex3_pass_frac_b;


   //#-------------------------------------------------
   //# bypass mux & operand flip
   //#-------------------------------------------------
   //# integer operation positions
   //#         32          32
   //#       99:130    131:162

   assign ex3_sh_lvl3_b[0:162] = (~(ex3_sh_lvl3[0:162]));
   assign f_fmt_ex3_pass_frac_b[0:52] = (~(f_fmt_ex3_pass_frac[0:52]));

   //--------------------------------------------------------------

   assign m0_b[0:52] = (~(({53{ex3_byp_sel_pos}} & ex3_sh_lvl3[0:52]) |
                          ({53{ex3_byp_sel_neg}} & ex3_sh_lvl3_b[0:52])));

   assign m1_b[0:52] = (~(({53{ex3_byp_sel_byp_pos}} & f_fmt_ex3_pass_frac[0:52]) |
                          ({53{ex3_byp_sel_byp_neg}} & f_fmt_ex3_pass_frac_b[0:52])));
   //---------------------------------------------------------------
   //---------------------------------------------------------------

   assign m0_b[53:98] = (~({46{ex3_prd_sel_pos_hi}} & ex3_sh_lvl3[53:98]));

   assign m1_b[53:98] = (~({46{ex3_prd_sel_neg_hi}} & ex3_sh_lvl3_b[53:98]));

   //---------------------------------------------------------------

   assign m0_b[99:130] = (~({32{ex3_prd_sel_pos_lohi}} & ex3_sh_lvl3[99:130]));

   assign m1_b[99:130] = (~({32{ex3_prd_sel_neg_lohi}} & ex3_sh_lvl3_b[99:130]));

   //---------------------------------------------------------------

   assign m0_b[131:162] = (~({32{ex3_prd_sel_pos_lo}} & ex3_sh_lvl3[131:162]));

   assign m1_b[131:162] = (~({32{ex3_prd_sel_neg_lo}} & ex3_sh_lvl3_b[131:162]));

   //---------------------------------------------------------------

   assign f_alg_ex3_res[0:162] = (~(m0_b[0:162] & m1_b[0:162]));


endmodule
module xu0_bcd_bcdtd(
   input [0:11] a,
   output [0:9] y
);

   assign y[0] = (a[5] & a[0] & a[8] & (~a[4])) | (a[9] & a[0] & (~a[8])) | (a[1] & (~a[0]));
   assign y[1] = (a[6] & a[0] & a[8] & (~a[4])) | (a[10] & a[0] & (~a[8])) | (a[2] & (~a[0]));
   assign y[2] = a[3];
   assign y[3] = (a[9] &  (~a[0]) & a[4] & (~a[8])) | (a[5] & (~a[8]) & (~a[4])) | (a[5] & (~a[0]) & (~a[4])) | (a[4] & a[8]);
   assign y[4] = (a[10] & (~a[0]) & a[4] & (~a[8])) | (a[6] & (~a[8]) & (~a[4])) | (a[6] & (~a[0]) & (~a[4])) | (a[0] & a[8]);
   assign y[5] = a[7];
   assign y[6] = a[0] | a[4] | a[8];
   assign y[7] = ((~a[4]) & a[9] &  (~a[8])) | (a[4] & a[8]) | a[0];
   assign y[8] = ((~a[0]) & a[10] & (~a[8])) | (a[0] & a[8]) | a[4];
   assign y[9] = a[11];

endmodule
module lq_stq_rot(
   rot_sel,
   mask,
   se_b,
   rot_data,
   data_rot
);
   input [0:3]  rot_sel;
   input [0:3]  mask;
   input        se_b;
   input [0:7]  rot_data;


   output [0:7] data_rot;

   wire [0:5]   se1;
   wire [0:7]   mx1_d0;
   wire [0:7]   mx1_d1;
   wire [0:7]   mx1_d2;
   wire [0:7]   mx1_d3;
   wire [0:7]   mx1_s0;
   wire [0:7]   mx1_s1;
   wire [0:7]   mx1_s2;
   wire [0:7]   mx1_s3;
   wire [0:7]   mx1_0_b;
   wire [0:7]   mx1_1_b;
   wire [0:7]   mx1;
   wire [0:7]   mask_exp;

   //--------------------------------------------------------------------------------------
   // Muxing <0,2,4,6 bytes>
   //--------------------------------------------------------------------------------------
   assign mx1_s0[0:7] = {8{rot_sel[0]}};
   assign mx1_s1[0:7] = {8{rot_sel[1]}};
   assign mx1_s2[0:7] = {8{rot_sel[2]}};
   assign mx1_s3[0:7] = {8{rot_sel[3]}};

   // Generate a Mask that is dependent on the size of the operation
   assign mask_exp[0] = mask[0];		                        // 8B
   assign mask_exp[1] = mask[0];		                        // 8B
   assign mask_exp[2] = mask[0];		                        // 8B
   assign mask_exp[3] = mask[0];		                        // 8B
   assign mask_exp[4] = mask[0] | mask[1];		                // 8B/4B
   assign mask_exp[5] = mask[0] | mask[1];		                // 8B/4B
   assign mask_exp[6] = mask[0] | mask[1] | mask[2];		    // 8B/4B/2B
   assign mask_exp[7] = mask[0] | mask[1] | mask[2] | mask[3];  // 8B/4B/2B/1B

   assign se1[0:3] = {4{((~se_b))}};
   assign se1[4:5] = {2{(((~se_b)) & mask[2])}};

   assign mx1_d0 = (rot_data[0:7]) & mask_exp;
   assign mx1_d1 = ({2'b0, rot_data[0:5]}) & mask_exp;
   assign mx1_d2 = ({4'b0, rot_data[0:3]}) & mask_exp;
   assign mx1_d3 = ({6'b0, rot_data[0:1]}) & mask_exp;


   //assign mx1_0_b[0:7] = (~((mx1_s0[0:7] & mx1_d0[0:7]) | (mx1_s1[0:7] & mx1_d1[0:7])));
   tri_aoi22 #(.WIDTH(8)) mx1_0_b_0 (.y(mx1_0_b[0:7]), .a0(mx1_s0[0:7]), .a1(mx1_d0[0:7]), .b0(mx1_s1[0:7]), .b1(mx1_d1[0:7]));

   //assign mx1_1_b[0:7] = (~((mx1_s2[0:7] & mx1_d2[0:7]) | (mx1_s3[0:7] & mx1_d3[0:7])));
   tri_aoi22 #(.WIDTH(8)) mx1_1_b_0 (.y(mx1_1_b[0:7]), .a0(mx1_s2[0:7]), .a1(mx1_d2[0:7]), .b0(mx1_s3[0:7]), .b1(mx1_d3[0:7]));

   //assign mx1[0:7] = (~(mx1_0_b[0:7] & mx1_1_b[0:7]));
   tri_nand2 #(.WIDTH(8)) mx1_0 (.y(mx1[0:7]), .a(mx1_0_b[0:7]), .b(mx1_1_b[0:7]));

   assign data_rot = {(mx1[0:5] | se1[0:5]), mx1[6:7]};

endmodule
module fu_divsqrt_q_table(
   x,
   cin,
   q
);
`include "tri_a2o.vh"

   input [0:3]  x;
   input        cin;

   output  q;

   wire    nor123;
   wire    nor123_b;

   wire    x0_b;
   wire    not0and1or2or3_b;
   wire    nor01;
   wire    nor23;
   wire    not0or1or2or3_and_cin_b;


//// Implements this table:
//    assign exx_q_bit0_prebuf = (exx_sum4 == 4'b0000) ? exx_q_bit0_cin :
//                               (exx_sum4 == 4'b0001) ? 1'b1 :
//                               (exx_sum4 == 4'b0010) ? 1'b1 :
//                               (exx_sum4 == 4'b0011) ? 1'b1 :
//                               (exx_sum4 == 4'b0100) ? 1'b1 :
//                               (exx_sum4 == 4'b0101) ? 1'b1 :
//                               (exx_sum4 == 4'b0110) ? 1'b1 :
//                               (exx_sum4 == 4'b0111) ? 1'b1 :
//                               1'b0;


   tri_nor3 #(.WIDTH(1), .BTR("NOR3_X4M_A9TH"))  DIVSQRT_N_TABLE_NOR3_01(nor123, x[1], x[2], x[3]);
   tri_inv  #(.WIDTH(1), .BTR("INV_X3M_A9TH"))   DIVSQRT_N_TABLE_INV_02a(nor123_b, nor123);
   tri_inv  #(.WIDTH(1), .BTR("INV_X5B_A9TH"))   DIVSQRT_N_TABLE_INV_02b(x0_b, x[0]);

   tri_nand2 #(.WIDTH(1), .BTR("NAND2_X4A_A9TH")) DIVSQRT_N_TABLE_NAND2_03(not0and1or2or3_b, x0_b, nor123_b);
//
   tri_nor2 #(.WIDTH(1), .BTR("NOR2_X8B_A9TH"))  DIVSQRT_N_TABLE_NOR2_01a(nor01, x[0], x[1]);
   tri_nor2 #(.WIDTH(1), .BTR("NOR2_X4B_A9TH"))  DIVSQRT_N_TABLE_NOR2_01b(nor23, x[2], x[3]);

   tri_nand3 #(.WIDTH(1), .BTR("NAND3_X6M_A9TH")) DIVSQRT_N_TABLE_NAND3_02(not0or1or2or3_and_cin_b, nor01, nor23, cin);
//

   tri_nand2 #(.WIDTH(1), .BTR("NAND2_X8A_A9TH")) DIVSQRT_N_TABLE_NAND2_04(q, not0or1or2or3_and_cin_b, not0and1or2or3_b);


endmodule
module lq_agen_csmuxe(
   sum_0,
   sum_1,
   ci_b,
   sum
);

input [0:3]     sum_0;		// after xor
input [0:3]     sum_1;
input           ci_b;

output [0:3]    sum;

wire [0:3]      sum0_b;

wire [0:3]      sum1_b;

wire            int_ci;

wire            int_ci_t;

wire            int_ci_b;

//assign int_ci = (~ci_b);
tri_inv int_ci_0 (.y(int_ci), .a(ci_b));

//assign int_ci_t = (~ci_b);
tri_inv int_ci_t_0 (.y(int_ci_t), .a(ci_b));

//assign int_ci_b = (~int_ci_t);
tri_inv int_ci_b_0 (.y(int_ci_b), .a(int_ci_t));

//assign sum0_b[0] = (~(sum_0[0] & int_ci_b));
tri_nand2 #(.WIDTH(4)) sum0_b_0 (.y(sum0_b[0:3]), .a(sum_0[0:3]), .b({4{int_ci_b}}));

//assign sum1_b[0] = (~(sum_1[0] & int_ci));
tri_nand2 #(.WIDTH(4)) sum1_b_0 (.y(sum1_b[0:3]), .a(sum_1[0:3]), .b({4{int_ci}}));

//assign sum[0] = (~(sum0_b[0] & sum1_b[0]));
tri_nand2 #(.WIDTH(4)) sum0 (.y(sum[0:3]), .a(sum0_b[0:3]), .b(sum1_b[0:3]));

endmodule
module fu_divsqrt_nq_table(
   x,
   nq
);
`include "tri_a2o.vh"

   input [0:3]  x;
   output  nq;

   wire    not1111;
   wire    nq_b;

//// Implements this table:
//   assign exx_nq_bit0        = (exx_sum4 == 4'b1000) ? 1'b1 :
//                               (exx_sum4 == 4'b1001) ? 1'b1 :
//                               (exx_sum4 == 4'b1010) ? 1'b1 :
//                               (exx_sum4 == 4'b1011) ? 1'b1 :
//                               (exx_sum4 == 4'b1100) ? 1'b1 :
//                               (exx_sum4 == 4'b1101) ? 1'b1 :
//                               (exx_sum4 == 4'b1110) ? 1'b1 :
//                               1'b0;


   tri_nand4 #(.WIDTH(1), .BTR("NAND4_X4M_A9TH")) DIVSQRT_NQ_TABLE_NAND4_00(not1111, x[0], x[1], x[2], x[3]);

   tri_nand2 #(.WIDTH(1), .BTR("NAND2_X6A_A9TH")) DIVSQRT_NQ_TABLE_NAND2_00(nq_b, x[0], not1111);

   tri_inv   #(.WIDTH(1), .BTR("INV_X11M_A9TH")) DIVSQRT_NQ_TABLE_INV_00(nq, nq_b);

endmodule
module lq_agen_glbloc_lsb(
   x_b,
   y_b,
   g08
);
input [0:7]     x_b;
input [0:7]     y_b;

output          g08;

wire [0:7]      g01;

wire [0:6]      t01;

wire [0:3]      g02_b;

wire [0:2]      t02_b;

wire [0:1]      g04;

wire [0:0]      t04;

wire            g08_b;

//assign g01[0] = (~(x_b[0] | y_b[0]));
tri_nor2 #(.WIDTH(8)) g01_0 (.y(g01[0:7]), .a(x_b[0:7]), .b(y_b[0:7]));

//assign t01[0] = (~(x_b[0] & y_b[0]));
tri_nand2 #(.WIDTH(7)) t01_0 (.y(t01[0:6]), .a(x_b[0:6]), .b(y_b[0:6]));

//assign g02_b[0] = (~(g01[0] | (t01[0] & g01[1])));
tri_aoi21 g02_b_0 (.y(g02_b[0]), .a0(t01[0]), .a1(g01[1]), .b0(g01[0]));

//assign g02_b[1] = (~(g01[2] | (t01[2] & g01[3])));
tri_aoi21 g02_b_1 (.y(g02_b[1]), .a0(t01[2]), .a1(g01[3]), .b0(g01[2]));

//assign g02_b[2] = (~(g01[4] | (t01[4] & g01[5])));
tri_aoi21 g02_b_2 (.y(g02_b[2]), .a0(t01[4]), .a1(g01[5]), .b0(g01[4]));

//assign g02_b[3] = (~(g01[6] | (t01[6] & g01[7])));
tri_aoi21 g02_b_3 (.y(g02_b[3]), .a0(t01[6]), .a1(g01[7]), .b0(g01[6]));

//assign t02_b[0] = (~(t01[0] & t01[1]));
tri_nand2 t02_b_0 (.y(t02_b[0]), .a(t01[0]), .b(t01[1]));

//assign t02_b[1] = (~(t01[2] & t01[3]));
tri_nand2 t02_b_1 (.y(t02_b[1]), .a(t01[2]), .b(t01[3]));

//assign t02_b[2] = (~(t01[4] & t01[5]));
tri_nand2 t02_b_2 (.y(t02_b[2]), .a(t01[4]), .b(t01[5]));

//assign g04[0] = (~(g02_b[0] & (t02_b[0] | g02_b[1])));
tri_oai21 g04_0 (.y(g04[0]), .a0(t02_b[0]), .a1(g02_b[1]), .b0(g02_b[0]));

//assign g04[1] = (~(g02_b[2] & (t02_b[2] | g02_b[3])));
tri_oai21 g04_1 (.y(g04[1]), .a0(t02_b[2]), .a1(g02_b[3]), .b0(g02_b[2]));

//assign t04[0] = (~(t02_b[0] | t02_b[1]));
tri_nor2 t04_0 (.y(t04[0]), .a(t02_b[0]), .b(t02_b[1]));

//assign g08_b = (~(g04[0] | (t04[0] & g04[1])));
tri_aoi21 g08_b_0 (.y(g08_b), .a0(t04[0]), .a1(g04[1]), .b0(g04[0]));

//assign g08 = (~(g08_b));		// output
tri_inv g08_0 (.y(g08), .a(g08_b));

endmodule
module rv_pri(
	      cond,
	      pri
	      );
   parameter         size = 32;
   input [0:size-1]  cond;
   output [0:size-1] pri;

   parameter         s = size - 1;
   wire [0:s] 	     or_l1;
   wire [0:s] 	     or_l2;
   wire [0:s] 	     or_l3;
   wire [0:s] 	     or_l4;
   wire [0:s] 	     or_l5;
   (* analysis_not_referenced="true" *)
   wire              or_cond;


   // Odd Numbered Levels are inverted

   assign or_l1[0] = (~cond[0]);
   assign or_l1[1:s] = ~(cond[0:s - 1] | cond[1:s]);

   generate
      if (s >= 2)
        begin : or_l2_gen0
           assign or_l2[0:1] = (~or_l1[0:1]);
           assign or_l2[2:s] = ~(or_l1[2:s] & or_l1[0:s - 2]);
        end
   endgenerate
   generate
      if (s < 2)
        begin : or_l2_gen1
           assign or_l2 = (~or_l1);
        end
   endgenerate

   generate
      if (s >= 4)
        begin : or_l3_gen0
           assign or_l3[0:3] = (~or_l2[0:3]);
           assign or_l3[4:s] = ~(or_l2[4:s] | or_l2[0:s - 4]);
        end
   endgenerate
   generate
      if (s < 4)
        begin : or_l3_gen1
           assign or_l3 = (~or_l2);
        end
   endgenerate

   generate
      if (s >= 8)
        begin : or_l4_gen0
           assign or_l4[0:7] = (~or_l3[0:7]);
           assign or_l4[8:s] = ~(or_l3[8:s] & or_l3[0:s - 8]);
        end
   endgenerate
   generate
      if (s < 8)
        begin : or_l4_gen1
           assign or_l4 = (~or_l3);
        end
   endgenerate

   generate
      if (s >= 16)
        begin : or_l5_gen0
           assign or_l5[0:15] = (~or_l4[0:15]);
           assign or_l5[16:s] = ~(or_l4[16:s] | or_l4[0:s - 16]);
        end
   endgenerate
   generate
      if (s < 16)
        begin : or_l5_gen1
           assign or_l5 = (~or_l4);
        end
   endgenerate

   //assert size > 32 report "Maximum Size of 32 Exceeded!" severity error;

   assign pri[0] = cond[0];
   assign pri[1:s] = cond[1:s] & or_l5[0:s - 1];
   assign or_cond = (~or_l5[s]);

endmodule // rv_pri
module xu_fctr
#(
   parameter               CLOCKGATE = 1,
   parameter               PASSTHRU = 1,
   parameter               DELAY_WIDTH = 4,
   parameter               WIDTH = 2
)
(
   input [0:`NCLK_WIDTH-1] nclk,

   input                   force_t,
   input                   thold_b,
   input                   sg,
   input                   d_mode,
   input                   delay_lclkr,
   input                   mpw1_b,
   input                   mpw2_b,

   input                   scin,
   output                  scout,

   input [0:WIDTH-1]       din,
   output [0:WIDTH-1]      dout,
   input [0:DELAY_WIDTH-1] delay,

   inout                   vdd,
   inout                   gnd
);


   // Latches
   wire [0:DELAY_WIDTH-1]  delay_q[0:WIDTH-1];
   wire [0:DELAY_WIDTH-1]  delay_d[0:WIDTH-1];
   // Scanchains
   localparam              delay_offset = 0;
   localparam              scan_right = delay_offset + DELAY_WIDTH*WIDTH;
   wire [0:scan_right-1]   siv;
   wire [0:scan_right-1]   sov;
   // Signals
   wire [0:WIDTH-1]     set;
   wire [0:WIDTH-1]     zero_b;
   wire [0:WIDTH-1]     act;

   generate
      genvar                  t;
      for (t=0;t<=WIDTH-1;t=t+1)
      begin : threads_gen
         wire [0:DELAY_WIDTH-1]   delay_m1;

         assign set[t] = din[t];
         assign zero_b[t] = |(delay_q[t]);
         assign delay_m1 = delay_q[t] - {{DELAY_WIDTH-1{1'b0}},1'b1};

         if (CLOCKGATE == 0) begin : clockgate_0
            assign act[t] = set[t] | zero_b[t];

            assign delay_d[t] = ({set[t], zero_b[t]} == 2'b11) ? delay :
                                ({set[t], zero_b[t]} == 2'b10) ? delay :
                                ({set[t], zero_b[t]} == 2'b01) ? delay_m1 :
                                delay_q[t];
         end
         if (CLOCKGATE == 1) begin : clockgate_1
            assign act[t] = set[t] | zero_b[t];

            assign delay_d[t] = (set[t] == 1'b1) ? delay :
                                delay_m1;
         end

         if (PASSTHRU == 1)begin : PASSTHRU_gen_1
            assign dout[t] = zero_b[t] | din[t];
         end
         if (PASSTHRU == 0) begin : PASSTHRU_gen_0
            assign dout[t] = zero_b[t];
         end


         tri_rlmreg_p #(.WIDTH(DELAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) delay_latch(
            .nclk(nclk),
            .vd(vdd),
            .gd(gnd),
            .act(act[t]),
            .force_t(force_t),
            .d_mode(d_mode),
            .delay_lclkr(delay_lclkr),
            .mpw1_b(mpw1_b),
            .mpw2_b(mpw2_b),
            .thold_b(thold_b),
            .sg(sg),
            .scin(siv[delay_offset+DELAY_WIDTH*t:delay_offset+DELAY_WIDTH*(t+1)-1]),
            .scout(sov[delay_offset+DELAY_WIDTH*t:delay_offset+DELAY_WIDTH*(t+1)-1]),
            .din(delay_d[t]),
            .dout(delay_q[t])
         );
      end
   endgenerate

assign siv[0:scan_right - 1] = {sov[1:scan_right - 1], scin};
assign scout = sov[0];

endmodule
module fu_loc8inc_lsb(
   x,
   co_b,
   s0,
   s1
);
   input [0:4]  x;		//48 to 52
   output       co_b;
   output [0:4] s0;
   output [0:4] s1;

   wire [0:4]   x_b;
   wire [0:4]   t2_b;
   wire [0:4]   t4;

   // FOLDED layout
   //   i0_xb   i2_xb   i4_xb   skip   skip   skip   skip
   //   i1_xb   i3_xb   skip    skip   skip   skip   skip
   //   i0_t2   i2_t2   i4_t2   skip   skip   skip   skip
   //   skip    i1_t2   i3_t2   skip   skip   skip   skip
   //   i0_t2   i2_t2   i4_t2   skip   skip   skip   skip
   //   i0_t8   i1_t2   i3_t2   skip   skip   skip   skip
   //   i0_s0   i2_s0   i4_s0   skip   skip   skip   skip
   //   i1_s0   i3_s0   skip    skip   skip   skip   skip
   //   i0_s1   i2_s1   i4_s1   skip   skip   skip   skip
   //   i1_s1   i3_s1   skip    skip   skip   skip   skip

   //-------------------------------
   // buffer off non critical path
   //-------------------------------

   assign x_b[0] = (~x[0]);
   assign x_b[1] = (~x[1]);
   assign x_b[2] = (~x[2]);
   assign x_b[3] = (~x[3]);
   assign x_b[4] = (~x[4]);

   //--------------------------
   // local carry chain
   //--------------------------

   assign t2_b[0] = (~(x[0]));
   assign t2_b[1] = (~(x[1] & x[2]));
   assign t2_b[2] = (~(x[2] & x[3]));
   assign t2_b[3] = (~(x[3] & x[4]));
   assign t2_b[4] = (~(x[4]));

   assign t4[0] = (~(t2_b[0]));
   assign t4[1] = (~(t2_b[1] | t2_b[3]));
   assign t4[2] = (~(t2_b[2] | t2_b[4]));
   assign t4[3] = (~(t2_b[3]));
   assign t4[4] = (~(t2_b[4]));

   assign co_b = (~(t4[0] & t4[1]));

   //------------------------
   // sum generation
   //------------------------

   assign s0[0] = (~(x_b[0]));
   assign s0[1] = (~(x_b[1]));
   assign s0[2] = (~(x_b[2]));
   assign s0[3] = (~(x_b[3]));
   assign s0[4] = (~(x_b[4]));

   assign s1[0] = (~(x_b[0] ^ t4[1]));
   assign s1[1] = (~(x_b[1] ^ t4[2]));
   assign s1[2] = (~(x_b[2] ^ t4[3]));
   assign s1[3] = (~(x_b[3] ^ t4[4]));
   assign s1[4] = (~(t4[4]));

endmodule
module i2c_com(clock_i2c        ,  //i2c控制接口传输所需时钟，0-400khz，此处为20khz
               camera_rstn      ,     
               ack              ,  //应答信号
               i2c_data         ,  //sdin接口传输的32位数据
               start            ,  //开始传输标志
               tr_end           ,  //传输结束标志
               i2c_sclk         ,  //FPGA与camera iic时钟接口
               i2c_sdat            //FPGA与camera iic数据接口
);        
    input [31:0]i2c_data;
    input camera_rstn;
    input clock_i2c;
    output ack;
    input start;
    output tr_end;
    output i2c_sclk;
    inout i2c_sdat;
    reg [5:0] cyc_count;
    reg reg_sdat;
    reg sclk;
    reg ack1,ack2,ack3;
    reg tr_end;
 
   
    wire i2c_sclk;
    wire i2c_sdat;
    wire ack;
   
    assign ack=ack1|ack2|ack3;
    assign i2c_sclk=sclk|(((cyc_count>=4)&(cyc_count<=39))?~clock_i2c:0);
    assign i2c_sdat=reg_sdat?1'bz:0; 
   
    always@(posedge clock_i2c)
    begin
       if(!camera_rstn)
         cyc_count<=6'b111111;
       else 
		   begin
           if(start==0)
             cyc_count<=0;
           else if(cyc_count<6'b111111)
             cyc_count<=cyc_count+1;
         end
    end
	 
	 
    always@(posedge clock_i2c)
    begin
       if(!camera_rstn)
       begin
          tr_end<=0;
          ack1<=1;
          ack2<=1;
          ack3<=1;
          sclk<=1;
          reg_sdat<=1;
       end
       else
          case(cyc_count)
          0:begin ack1<=1;ack2<=1;ack3<=1;tr_end<=0;sclk<=1;reg_sdat<=1;end
          1:reg_sdat<=0;                 //开始传输
          2:sclk<=0;
          3:reg_sdat<=i2c_data[31];
          4:reg_sdat<=i2c_data[30];
          5:reg_sdat<=i2c_data[29];
          6:reg_sdat<=i2c_data[28];
          7:reg_sdat<=i2c_data[27];
          8:reg_sdat<=i2c_data[26];
          9:reg_sdat<=i2c_data[25];
          10:reg_sdat<=i2c_data[24];
          11:reg_sdat<=1;                //应答信号
          12:begin reg_sdat<=i2c_data[23];ack1<=i2c_sdat;end
          13:reg_sdat<=i2c_data[22];
          14:reg_sdat<=i2c_data[21];
          15:reg_sdat<=i2c_data[20];
          16:reg_sdat<=i2c_data[19];
          17:reg_sdat<=i2c_data[18];
          18:reg_sdat<=i2c_data[17];
          19:reg_sdat<=i2c_data[16];
          20:reg_sdat<=1;                //应答信号       
          21:begin reg_sdat<=i2c_data[15];ack1<=i2c_sdat;end
          22:reg_sdat<=i2c_data[14];
          23:reg_sdat<=i2c_data[13];
          24:reg_sdat<=i2c_data[12];
          25:reg_sdat<=i2c_data[11];
          26:reg_sdat<=i2c_data[10];
          27:reg_sdat<=i2c_data[9];
          28:reg_sdat<=i2c_data[8];
          29:reg_sdat<=1;                //应答信号       
          30:begin reg_sdat<=i2c_data[7];ack2<=i2c_sdat;end
          31:reg_sdat<=i2c_data[6];
          32:reg_sdat<=i2c_data[5];
          33:reg_sdat<=i2c_data[4];
          34:reg_sdat<=i2c_data[3];
          35:reg_sdat<=i2c_data[2];
          36:reg_sdat<=i2c_data[1];
          37:reg_sdat<=i2c_data[0];
          38:reg_sdat<=1;                //应答信号       
          39:begin ack3<=i2c_sdat;sclk<=0;reg_sdat<=0;end
          40:sclk<=1;
          41:begin reg_sdat<=1;tr_end<=1;end
          endcase
       
end
endmodule
module ov5640_power_on_delay(                  
    input  clk_50M        ,
    input  reset_n        ,
    output camera1_rstn   ,
    output camera2_rstn   ,
    output camera_pwnd    ,
    output reg initial_en
);
reg [18:0]cnt1;
reg [15:0]cnt2;
reg [19:0]cnt3;
reg camera_rstn_reg;
reg camera_pwnd_reg;

assign camera1_rstn=camera_rstn_reg;
assign camera2_rstn=camera_rstn_reg;
assign camera_pwnd=camera_pwnd_reg;

//5ms, delay from sensor power up stable to Pwdn pull down
always@(posedge clk_50M)begin
  if(reset_n==1'b0) begin
	    cnt1<=0;
		camera_pwnd_reg<=1'b1;// 1'b1 
  end
  else if(cnt1<19'h40000) begin
       cnt1<=cnt1+1'b1;
       camera_pwnd_reg<=1'b1;
  end
  else
     camera_pwnd_reg<=1'b0;         
end

//1.3ms, delay from pwdn low to resetb pull up
always@(posedge clk_50M)begin
  if(camera_pwnd_reg==1)  begin
	 cnt2<=0;
     camera_rstn_reg<=1'b0;  
  end
  else if(cnt2<16'hffff) begin
       cnt2<=cnt2+1'b1;
       camera_rstn_reg<=1'b0;
  end
  else
     camera_rstn_reg<=1'b1;         
end

//21ms, delay from resetb pul high to SCCB initialization
always@(posedge clk_50M)begin
  if(camera_rstn_reg==0) begin
         cnt3<=0;
         initial_en<=1'b0;
  end
  else if(cnt3<20'hfffff) begin
        cnt3<=cnt3+1'b1;
        initial_en<=1'b0;
  end
  else
       initial_en<=1'b1;    
end

endmodule
module cmos_8_16bit(
	input 				   pclk 		,   
	input 				   rst_n		,
	input				   de_i	        ,
	input	[7:0]	       pdata_i	    ,
    input                  vs_i         ,

    output  wire           pixel_clk    ,
 	output	reg			   de_o         ,
	output  reg [15:0]	   pdata_o
); 
reg			de_out1          ;
reg [15:0]	pdata_out1       ;
reg			de_out2          ;
reg [15:0]	pdata_out2       ;    
reg [1:0]   cnt             ;
wire        pclk_IOCLKBUF   ;
reg         vs_i_reg        ;
reg         enble           ;
reg [7:0] pdata_i_reg;
reg de_i_r,de_i_r1;
reg			de_out3          ;
reg [15:0]	pdata_out3       ;  
always @(posedge pclk)begin
       vs_i_reg <= vs_i ;
end
    always@(posedge pclk)
        begin
            if(!rst_n)
                enble <= 1'b0;
            else if(!vs_i_reg&&vs_i)
                enble <= 1'b1;
            else
                enble <= enble;
        end

GTP_IOCLKBUF #(
    .GATE_EN("FALSE")//
) u_GTP_IOCLKBUF (
    .CLKOUT(pclk_IOCLKBUF),// OUTPUT  
    .CLKIN(pclk), // INPUT  
    .DI(1'b1)     // INPUT  
);

GTP_IOCLKDIV #(
    .GRS_EN("TRUE"),
    .DIV_FACTOR("2")
) u_GTP_IOCLKDIV (
    .CLKDIVOUT(pixel_clk),// OUTPUT  
    .CLKIN(pclk_IOCLKBUF),    // INPUT  
    .RST_N(rst_n)     // INPUT  
);

    always@(posedge pclk)
        begin
            if(!rst_n)
                cnt <= 2'b0;
            else if(de_i == 1'b1 && cnt == 2'd1)
                cnt <= 2'b0;
            else if(de_i == 1'b1)
                cnt <= cnt + 1'b1;
        end
    

    always@(posedge pclk)
        begin
            if(!rst_n)
                pdata_i_reg <= 8'b0;
            else if(de_i == 1'b1)
                pdata_i_reg <= pdata_i;
        end
    
    always@(posedge pclk)
        begin
            if(!rst_n)
                pdata_out1 <= 16'b0;
            else if(de_i == 1'b1 && cnt == 2'd1)
                pdata_out1 <= {pdata_i_reg,pdata_i};
        end
  

   always@(posedge pclk)begin
        de_i_r <= de_i;
        de_i_r1 <= de_i_r;
   end
    always@(posedge pclk)
        begin
            if(!rst_n)
                de_out1 <= 1'b0;
            else if(!de_i_r1 && de_i_r )//ÉÏÉýÑØ
                de_out1 <= 1'b1;
            else if(de_i_r1 && !de_i_r )//ÏÂ½µÑØ
                de_out1 <= 1'b0;
            else
                de_out1 <= de_out1;
        end


 
    always@(posedge pixel_clk)begin
        de_out2<=de_out1;
        de_out3<=de_out2;
        de_o   <=de_out3;
    end
    always@(posedge pixel_clk)begin
        pdata_out2<=pdata_out1;
        pdata_out3<=pdata_out2;
        pdata_o   <=pdata_out3;
    end
endmodule
module video_enhance(
input  wire            pix_clk,
input  wire            vs_in,
input  wire            hs_in,
input  wire            de_in,
input  wire [7 : 0]    r_in,
input  wire [7 : 0]    g_in,
input  wire [7 : 0]    b_in,

output wire            vs_out,
output wire            hs_out,
output wire            de_out,
output wire [7 : 0]    r_out,
output wire [7 : 0]    g_out,
output wire [7 : 0]    b_out,

input  wire [7 : 0]   video_enhance_lightdown_num,
input  wire           video_enhance_lightdown_sw ,
input  wire [7 : 0]   video_enhance_darkup_num   ,
input  wire           video_enhance_darkup_sw    

   );

wire [7 : 0] y_out;
wire [7 : 0] u_out;
wire [7 : 0] v_out;

//wire [7 : 0] r_out;
//wire [7 : 0] g_out;
//wire [7 : 0] b_out;

wire         yuv_vs_out;
wire         yuv_hs_out;
wire         yuv_de_out;

rgb2yuv video_enhance_rgb2yuv(
.clk   (pix_clk),//input        
.r_in  (r_in),//input  [7:0] 
.g_in  (g_in),//input  [7:0] 
.b_in  (b_in),//input  [7:0] 
.vs_in (vs_in),//input        
.hs_in (hs_in),//input        
.de_in (de_in),//input        
.y_out (y_out),//output [7:0] 
.u_out (u_out),//output [7:0] 
.v_out (v_out),//output [7:0] 
.vs_out(yuv_vs_out),//output       
.hs_out(yuv_hs_out),//output       
.de_out(yuv_de_out), //output
.video_enhance_lightdown_num(video_enhance_lightdown_num),// input  wire [7 : 0]          
.video_enhance_lightdown_sw (video_enhance_lightdown_sw ),// input  wire           
.video_enhance_darkup_num   (video_enhance_darkup_num   ),// input  wire [7 : 0]   
.video_enhance_darkup_sw    (video_enhance_darkup_sw    ) // input  wire           
         
);

yuv2rgb video_enhance_yuv2rgb(
.clk   (pix_clk),//input       
.y_in  (y_out),//input [7:0] 
.u_in  (u_out),//input [7:0] 
.v_in  (v_out),//input [7:0] 
.vs_in (yuv_vs_out),//input       
.hs_in (yuv_hs_out),//input       
.de_in (yuv_de_out),//input       
.r_out (r_out),//output [7:0]
.g_out (g_out),//output [7:0]
.b_out (b_out),//output [7:0]
.vs_out(vs_out),//output      
.hs_out(hs_out),//output      
.de_out(de_out) //output      
);

endmodule
module vesa_debug#(
parameter PIX_WIGHT = 16
)
(
input wire    pix_clk,
input wire    rstn,
input wire    vs,
input wire    de,
output reg [15 : 0]   vesa_data
);
reg de_d0;
reg de_d1;
wire de_pos;
wire de_neg;
assign de_pos_d0 = de && !de_d0;
assign de_neg = !de_d0 && de_d1;
always @(posedge pix_clk)begin
    if(!rstn||vs) begin
        vesa_data <= 16'hA500;
    end
    else if(de) begin
        vesa_data <= vesa_data + 'd1;
    end
    else if(de_neg) begin
        vesa_data <= 16'hA500;
    end
end
always @(posedge pix_clk)begin
    if(!rstn||vs) begin
        de_d0 <= 'd0;
    end
    else begin
        de_d0 <= de;
        de_d1 <= de_d0;
    end
end
endmodule
module ipsxb_rst_sync_v1_1 #
    (
    parameter DATA_WIDTH = 1'd1, //
    parameter DFT_VALUE  = {DATA_WIDTH{1'b0}}
    )
    (
     input   wire                   clk,
     input   wire                   rst_n,
     input   wire  [DATA_WIDTH-1:0] sig_async,
     output  wire  [DATA_WIDTH-1:0] sig_synced
    );

reg     [DATA_WIDTH-1:0]  sig_async_r1;
reg     [DATA_WIDTH-1:0]  sig_async_r2;

always@(posedge clk or negedge rst_n)
begin
    if (!rst_n)
    begin
        sig_async_r1 <= DFT_VALUE;
        sig_async_r2 <= DFT_VALUE;
    end
    else
    begin
        sig_async_r1 <= sig_async;
        sig_async_r2 <= sig_async_r1;
    end
end

assign sig_synced = sig_async_r2;

endmodule
module ipsxb_seu_uart_tx(
    input  wire         clk                     ,
    input  wire         clk_en                  ,
    input  wire         rst_n                   ,

    input  wire [31:0]  tx_fifo_rd_data         ,
    input  wire         tx_fifo_rd_data_valid   ,  // Transfer the data until tx_fifo is empty
    output reg          tx_fifo_rd_data_req     ,

    output reg          txd
);

localparam IDLE  = 2'b00;
localparam START = 2'b01;
localparam DATA  = 2'b10;
localparam END   = 2'b11;

reg  [1:0]   tx_cs             ;
reg  [1:0]   tx_ns             ;
reg  [5:0]   tx_data_cnt       ;
wire         data_end          ;
reg  [2:0]   cnt               ;
wire         bit_en            ; //5 div from clk_en
reg          transmitting      ;
wire [37:0]  tx_frame_data     ;

always @(posedge clk or negedge rst_n)
begin
    if(~rst_n)
        cnt <= 3'd0;
    else if(~transmitting)
        cnt <= 3'd0;
    else if(clk_en)
    begin
        if(cnt == 3'd5)
            cnt <= 3'd0;
        else
            cnt <= cnt + 3'd1;
    end
    else;
end

assign bit_en = (cnt == 3'd5) && clk_en;

always @(posedge clk or negedge rst_n)
begin
    if(~rst_n)
        tx_cs <= IDLE;
    else if(bit_en)
        tx_cs <= tx_ns;
    else;
end

always@(*)
begin
    case(tx_cs)
        IDLE: begin
            if(transmitting)
                tx_ns = START;
            else
                tx_ns = IDLE;
        end
        START: begin
            tx_ns = DATA;
        end
        DATA: begin
            if(data_end)
                tx_ns = END;
            else
                tx_ns = DATA;
        end
        END: begin
            if(transmitting && tx_fifo_rd_data_valid)
                tx_ns = START;
            else
                tx_ns = IDLE;
        end
        default: begin
            tx_ns = IDLE;
        end
    endcase
end

//read data from fifo ,once a time
always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        transmitting <= 0; 
    else if(tx_fifo_rd_data_valid) 
        transmitting <= 1;        
    else if(~tx_fifo_rd_data_valid && (tx_cs == END) && bit_en)
        transmitting <= 0;        
    else;
end

always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        tx_fifo_rd_data_req <= 0;
    else if(tx_fifo_rd_data_valid && transmitting && data_end && bit_en)
        tx_fifo_rd_data_req <= 1;
    else
        tx_fifo_rd_data_req <= 0;
end

//tx data cnt
always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        tx_data_cnt <= 6'd0;
    else if(tx_cs == DATA) 
        if(bit_en) 
            tx_data_cnt <= tx_data_cnt + 6'd1;
        else;
    else
        tx_data_cnt <= 6'd0;
end

assign data_end = tx_data_cnt == 6'd37;

assign tx_frame_data = {tx_fifo_rd_data[31:24],2'b01,tx_fifo_rd_data[23:16],2'b01,tx_fifo_rd_data[15:8],2'b01,tx_fifo_rd_data[7:0]};

always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        txd <= 1'b1;
    else if(tx_cs == START) 
        txd <= 1'b0;
    else if(tx_cs == DATA)
        txd <= tx_frame_data[tx_data_cnt];
    else
        txd <= 1'b1;
end

endmodule