dakies/OSS_Verilog huggingface dataset:
module aibcr3_dcc_dly_rep ( clkrep, idat, rb_dcc_byp );

output  clkrep;

input  idat, rb_dcc_byp;

wire tielo;
wire buf_idat;
wire dcc_byp_n;
wire dcc_byp_p;
wire idat_mux0;
wire idat_mux2;


assign tielo = 1'b0;
assign tiehi = 1'b1;
aibcr3_dcc_interpolator x12 ( idat_mux0, net014, {tiehi,
     tiehi, tiehi, tiehi, tiehi, tiehi, tiehi}, {tielo, tielo, tielo,
     tielo, tielo, tielo, tielo});

assign buf_idat = idat;
assign idat_mux2 = idat_mux0;
assign dcc_byp_p = rb_dcc_byp ; 
assign clkrep = dcc_byp_p ? buf_idat : idat_mux2;


aibcr3_dlycell_dcc_rep x17 ( net030, net014, tielo, tielo,
     buf_idat);

endmodule
module aibcr3_dlycell_dll_c (
input         in_p,
input         bk,
input         ci_p,
output        out_p,
output        co_p
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter   NAND_DELAY = 20;
/*
wire   tp;
wire   fp;
wire   tn;
wire   fn;

assign #NAND_DELAY co_p  = ~(in_p & bk);
assign #NAND_DELAY tp    = ~(in_p & fp);
assign #NAND_DELAY fp    = ~(tp & bk);
assign #NAND_DELAY out_p = ~(tp & ci_p);
assign #NAND_DELAY co_n  = ~(in_n & bk);
assign #NAND_DELAY tn    = ~(in_n & fn);
assign #NAND_DELAY fn    = ~(tn & bk);
assign #NAND_DELAY out_n = ~(tn & ci_n);
*/

reg    tp;

assign #NAND_DELAY co_p  = ~(in_p & bk);

always @(*)
  if (~in_p)    tp <= #NAND_DELAY 1'b1;
  else if (~bk) tp <= #NAND_DELAY 1'b0;

assign #NAND_DELAY out_p = ~(tp & ci_p);


endmodule
module aibcr3_triinv_dig ( out, en, enb, in, vcc, vssl );

output  out;

input  en, enb, in, vcc, vssl;


assign out = ((en == 1'b1) & (enb == 1'b0))? ~in : 1'bz; 


endmodule
module aibcr3_dcc_dly ( SOOUT, clk_dly, clk_mindly, PDb,
     SE, SI, SMCLK, clk_dcd, dll_lock_reg, gray, launch, measure );

output  SOOUT, clk_dly, clk_mindly;


input  PDb, SE, SI, SMCLK, clk_dcd, dll_lock_reg, launch, measure;

input [10:0]  gray;

// Buses in the design

wire  [0:255]  net105;

assign tieLO = 1'b0;
assign tieHI = 1'b1;
//assign net102 = tieLO? measure : tieLO;
assign clkin_mindly = dll_lock_reg? clk_dcd : measure; 
assign clkin_dlyline = dll_lock_reg? clk_dcd : launch;


// Actual delay path
aibcr3_dcc_dlyline I0 ( SO_dlyline, net105[0:255], net029, clk_dly,
       clkin_dlyline, PDb, SE, SI, SMCLK, gray[10:0]);

// Intrinsic delay compensation path
aibcr3_dcc_8ph_intp I1 ( SOOUT, clk_mindly,   SMCLK, PDb,
     net104, {tieLO, tieLO, tieLO}, SE, SO_dlyline);
aibcr3_dlycell_dcc I7 ( net103, net104, tieLO, tieHI,
     clkin_mindly);

endmodule
module aibcr3_dlycell_dll (
input         in_p,
input         bk,
input         ci_p,
output        out_p,
output        co_p,
input         ck,
input         si,
input         SE,
input         RSTb,
output        so
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter   NAND_DELAY = 20;
/*
wire   tp;
wire   fp;
wire   tn;
wire   fn;

assign #NAND_DELAY co_p  = ~(in_p & bk);
assign #NAND_DELAY tp    = ~(in_p & fp);
assign #NAND_DELAY fp    = ~(tp & bk);
assign #NAND_DELAY out_p = ~(tp & ci_p);
assign #NAND_DELAY co_n  = ~(in_n & bk);
assign #NAND_DELAY tn    = ~(in_n & fn);
assign #NAND_DELAY fn    = ~(tn & bk);
assign #NAND_DELAY out_n = ~(tn & ci_n);
*/

reg    tp;
wire   bk1;

aibcr3_svt16_scdffcdn_cust I316 ( bk1, so, RSTb, ck,
     bk, SE, si);

assign #NAND_DELAY co_p  = ~(in_p & bk1);

always @(*)
  if (~in_p)    tp <= #NAND_DELAY 1'b1;
  else if (~bk1) tp <= #NAND_DELAY 1'b0;

assign #NAND_DELAY out_p = ~(tp & ci_p);


endmodule
module aibcr3_analog ( oclkn, oclkp, odat, odat_async, 
     iopad, clk_en, data_en, iclkn, indrv_buf, ipdrv_buf,
     itx_en_buf, por_aib_vcc1, por_aib_vcchssi, txdin, weak_pulldownen,
     weak_pullupenb  
);

output  oclkn, oclkp, odat, odat_async;


inout iopad;

input  clk_en, data_en, iclkn, itx_en_buf, por_aib_vcc1,
     por_aib_vcchssi, txdin, weak_pulldownen, weak_pullupenb;

input [1:0]  indrv_buf;
input [1:0]  ipdrv_buf;

wire net14;

assign tielo = 1'b0;
assign odat_maxout = tielo? tielo : net14;
assign odat = odat_maxout;

aibcr3_esd x5 ( iopad );

aibcr3_rxanlg x0 ( oclkn, oclkp, net14, odat_async, 
     iopad, 
     clk_en, data_en, iclkn, por_aib_vcchssi, por_aib_vcc1);

aibcr3_txanlg x1 ( iopad, txdin, indrv_buf[1:0],
     ipdrv_buf[1:0], itx_en_buf, por_aib_vcc1, weak_pulldownen,
     weak_pullupenb);


endmodule
module aibcr3_sync_ff ( Q, so,   
      CDN, CP, D, se_n, si );

output  Q, so;


input  CDN, CP, D, se_n, si;

wire Q, so, net047, se_n;


// specify 
//     specparam CDS_LIBNAME  = "aibcr_lib";
//     specparam CDS_CELLNAME = "aibcr_sync_ff";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign Q = so;
assign net047 = !se_n;
aibcr3_sync_3ff  xsync0 (  .SE(net047),     .D(D),  .Q(so), .CP(CP),  .SI(si),     .CDN(CDN));

endmodule
module aibcr3_io_cmos_8ph_interpolator_rep (
input         nfrzdrv,
input         fout_p,
input         fout_n,
input   [2:0] gray,
output        out_p,
output        out_n,
output        osc_out_p,
output        osc_out_n
);

`ifdef TIMESCALE_EN
		timeunit 1ps; 
		timeprecision 1ps; 
`endif

parameter   NAND_DELAY = 20;

wire         a_in_p;
wire         b_in_p;
wire         c_in_p;
wire         a_in_n;
wire         b_in_n;
wire         c_in_n;
wire         x_p;
wire         x_n;
wire         x_pb;
wire         x_nb;
wire  [6:0]  sn;
reg   [6:0]  sp;

assign #(0 * NAND_DELAY) a_in_p = nfrzdrv? ~fout_n : 1'b0;
assign #(2 * NAND_DELAY) b_in_p = nfrzdrv? ~fout_n : 1'b0;
assign #(4 * NAND_DELAY) c_in_p = nfrzdrv? ~fout_n : 1'b0;

assign #(0 * NAND_DELAY) a_in_n = nfrzdrv? ~fout_p : 1'b1;
assign #(2 * NAND_DELAY) b_in_n = nfrzdrv? ~fout_p : 1'b1;
assign #(4 * NAND_DELAY) c_in_n = nfrzdrv? ~fout_p : 1'b1;

always @(*)
  case (gray[2:0])
    3'b000 :  sp[6:0] = 7'b000_0000;
    3'b001 :  sp[6:0] = 7'b000_0001;
    3'b011 :  sp[6:0] = 7'b000_0011;
    3'b010 :  sp[6:0] = 7'b000_0111;
    3'b110 :  sp[6:0] = 7'b000_1111;
    3'b111 :  sp[6:0] = 7'b001_1111;
    3'b101 :  sp[6:0] = 7'b011_1111;
    3'b100 :  sp[6:0] = 7'b111_1111;
  endcase

assign sn[6:0] = ~sp[6:0];

aibcr3_io_ip8phs x8phs_n (
.c_in     ( {c_in_n, b_in_n, a_in_n} ),
.sp       ( sp[6:0]                ),
.sn       ( sn[6:0]                ),
.c_out    ( x_n                    )
);

aibcr3_io_ip8phs x8phs_p (
.c_in     ( {c_in_p, b_in_p, a_in_p} ),
.sp       ( sp[6:0]                ),
.sn       ( sn[6:0]                ),
.c_out    ( x_p                    )
);

//cross couple
assign x_pb = ~x_p;
assign x_nb = ~x_n;
assign out_p = ~x_p;
assign out_n = ~x_n;
assign osc_out_p = ~x_p;
assign osc_out_n = ~x_n;

`ifdef LEC
assign x_p = ~x_n;
assign x_n = ~x_p;
`endif

endmodule
module aibcr3_red_clkmux2 ( muxout, in0, in1, sel, vcc, vssl );

output  muxout;

input  in0, in1, sel, vcc, vssl;




assign muxout = sel ?  in1 : in0 ;


endmodule
module aibcr3_dcc_helper ( ckout, clk_dcd, dcc_byp,
     launch, measure, rstb );

output  ckout;

input  clk_dcd, dcc_byp, launch, measure, rstb;

wire net72;
wire net73;
wire net49;
wire net029;
wire net71;
wire launchb;

assign tieHI = 1'b1;
assign tieLO = 1'b0;
assign net075 = ~rstb;
assign net50 = ~net72;
assign net72 = ~net73;
assign net029 = ~net72;
assign net52 = ~net075;
assign ckout = net49;
assign net71 = net029? measure : launch;
assign net49 = dcc_byp? clk_dcd : net50;
//assign launchb = ~launch;

aibcr3_ulvt16_dffcdn_cust x24 ( .Q(sync1), .CDN(net52), .CK(launch),
     .D(tieHI));
aibcr3_ulvt16_dffcdn_cust x25 ( .Q(sync1out), .CDN(net52), .CK(launch),
     .D(sync1));

aibcr3_ulvt16_dffcdn_cust x23 ( .Q(net73), .CDN(syncrstb), .CK(net71),
     .D(net72));

// 2nd synchronizer
aibcr3_ulvt16_dffcdn_cust x21 ( .Q(net55), .CDN(net52), .CK(launch),
     .D(sync1out));
aibcr3_ulvt16_dffcdn_cust x22 ( .Q(syncrstb), .CDN(net52), .CK(launch),
     .D(net55));



endmodule
module aibcr3_dcc_phasedet
#(
parameter FF_DELAY     = 200
)
( 
output wire 	  t_down, 
output reg 	  t_up, 
input  wire 	  CLKA, 
input  wire	  CLKB,
input  wire	  RSTb);

`ifdef TIMESCALE_EN
                timeunit 100fs;
                timeprecision 100fs;
`endif

always @(posedge CLKB or negedge RSTb)
  if (~RSTb)           t_up <= #FF_DELAY 1'b1;
  else                 t_up <= #FF_DELAY CLKA;

assign t_down = !t_up;


endmodule
module aibcr3_red_clkmux3 ( muxout, in0, in1, in2, sel0, sel1, sel2,
     vcc, vssl );

output  muxout;

input  in0, in1, in2, sel0, sel1, sel2, vcc, vssl;

reg muxout;

always @ ( sel0 or sel1 or sel2 or in0 or in1 or in2 )
	case ( {sel2,sel1,sel0} )
		3'b001 : muxout = in0 ;
		3'b010 : muxout = in1 ;
		3'b100 : muxout = in2 ;
		default : muxout = 1'bx ;
	endcase
endmodule
module aibcr3_split_align (
input          din,           		// input
output         dout_p,           	// splitted output positive
output         dout_n           	// splitted output negative
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter  INV_DELAY      = 15;  // 15ps

assign #(2 * INV_DELAY) dout_p = din;
assign #(2 * INV_DELAY) dout_n = ~din;

endmodule
module aibcr3_io_cmos_nand_x1 (
input         in_p,
input         in_n,
input         bk,
input         ci_p,
input         ci_n,
output        out_p,
output        out_n,
output        co_p,
output        co_n
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter   NAND_DELAY = 20;
/*
wire   tp;
wire   fp;
wire   tn;
wire   fn;

assign #NAND_DELAY co_p  = ~(in_p & bk);
assign #NAND_DELAY tp    = ~(in_p & fp);
assign #NAND_DELAY fp    = ~(tp & bk);
assign #NAND_DELAY out_p = ~(tp & ci_p);
assign #NAND_DELAY co_n  = ~(in_n & bk);
assign #NAND_DELAY tn    = ~(in_n & fn);
assign #NAND_DELAY fn    = ~(tn & bk);
assign #NAND_DELAY out_n = ~(tn & ci_n);
*/

reg    tp;
reg    tn;

assign #NAND_DELAY co_p  = ~(in_p & bk);

always @(*)
  if (~in_p)    tp <= #NAND_DELAY 1'b1;
  else if (~bk) tp <= #NAND_DELAY 1'b0;

assign #NAND_DELAY out_p = ~(tp & ci_p);

assign #NAND_DELAY co_n  = ~(in_n & bk);

always @(*)
  if (~in_n)    tn <= #NAND_DELAY 1'b1;
  else if (~bk) tn <= #NAND_DELAY 1'b0;

assign #NAND_DELAY out_n = ~(tn & ci_n);

endmodule
module aibcr3_io_nand_delay_line_min_rep(
input         nfrzdrv,
input         in_p,
input         in_n,
output        out_p,
output        out_n
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter   NAND_DELAY = 20;

wire         fout_p;
wire         fout_n;
wire         osc_out_p;
wire         osc_out_n;

//---------------------------------------------------------------------------------------------------------------------------------------------
//  
//---------------------------------------------------------------------------------------------------------------------------------------------

aibcr3_io_cmos_nand_x1 UD00 (
.in_p       ( in_p	),
.in_n       ( in_n	),
.bk         ( 1'b0	),
.ci_p       ( 1'b1	),
.ci_n       ( 1'b1	),
.out_p      ( fout_p	),
.out_n      ( fout_n	),
.co_p       ( 		),
.co_n       ( 		)
);

aibcr3_io_cmos_8ph_interpolator_rep xinterp (
.nfrzdrv    ( nfrzdrv     ),
.fout_p     ( fout_p      ),
.fout_n     ( fout_n      ),
.gray       ( 3'b000      ),
.out_p      ( out_p       ),
.out_n      ( out_n       ),
.osc_out_p  ( osc_out_p   ),
.osc_out_n  ( osc_out_n   )
);

endmodule
module aibcr3_latch (
	input wire E,
	input wire CDN,
	//input wire vcc,
	//input wire vss,
	input wire D,
	output reg Q
);

always@(*) begin
	if (!CDN) begin
		Q <= 0;
	end
	else begin
		if (E)
			Q <= D;
	end
end
endmodule
module aibcr3_cmos_nand_x64 ( out_p, so, code_valid,
     dll_reset_n, in_p, scan_rst_n, sck_in, se_n, si, sm_grey,
     sm_igray, sm_n );

output  out_p, so;

input  code_valid, dll_reset_n, in_p, scan_rst_n, sck_in, se_n, si,
     sm_n;

input [6:0]  sm_grey;
input [2:0]  sm_igray;

// Buses in the design

wire  [63:0]  bk;

wire  [6:0]  grey;

wire  [2:0]  i_gray;

wire         so_g2th;
wire         net110;
wire         clk_prebuf;


assign tie_HI   = 1'b1;
assign tie_LO   = 1'b0;
assign nrst     = net110;
assign clk_buf0 = clk_prebuf;
assign SE       = ! se_n;
assign sm_n_buf = sm_n;
assign ck       = clk_buf0;
assign clk_prebuf = sm_n_buf? out_p : sck_in;
assign net110     = sm_n_buf? dll_reset_n : scan_rst_n;

aibcr3_dll_8ph_intp x4 ( so, out_p, ck, nrst, net104,
     i_gray[2:0], SE, so_g2th);

aibcr3_dll_gry2thm64 x1 ( bk[63:0], tie_LO, 
     grey[6:0], tie_LO);

aibcr3_dll_ibkmux x17 ( so_sync, grey[6:0], i_gray[2:0], 
     ck, nrst, SE, code_valid, si, sm_grey[6:0], sm_igray[2:0]);

aibcr3_dlycell_dll_c I7 ( .co_p(net108), .out_p(net109), .bk(tie_LO), .ci_p(tie_HI),
     .in_p(net106));

aibcr3_dll_dlyline64 x0 ( .a63(net106), .dlyout(net104), .b63(net109),
     .bk(bk[63:0]), .dlyin(in_p), .CLKIN(ck), .iSE(SE), .RSTb(nrst), .iSI(so_sync), .SOOUT(so_g2th));

endmodule
module aibcr3_io_nand_delay_line_min(
input         nfrzdrv,
input         in_p,
input         in_n,
output        out_p,
output        out_n
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter   NAND_DELAY = 20;

wire         fout_p;
wire         fout_n;
wire         osc_out_p;
wire         osc_out_n;

//---------------------------------------------------------------------------------------------------------------------------------------------
//  
//---------------------------------------------------------------------------------------------------------------------------------------------

aibcr3_io_cmos_nand_x1 UD00 (
.in_p       ( in_p	),
.in_n       ( in_n	),
.bk         ( 1'b0	),
.ci_p       ( 1'b1	),
.ci_n       ( 1'b1	),
.out_p      ( fout_p	),
.out_n      ( fout_n	),
.co_p       ( 		),
.co_n       ( 		)
);

aibcr3_io_cmos_8ph_interpolator xinterp (
.nfrzdrv    ( nfrzdrv     ),
.fout_p     ( fout_p      ),
.fout_n     ( fout_n      ),
.gray       ( 3'b000      ),
.out_p      ( out_p       ),
.out_n      ( out_n       ),
.osc_out_p  ( osc_out_p   ),
.osc_out_n  ( osc_out_n   )
);

endmodule
module aibcr3_aliasd(ra, rb);
 input ra;
 output rb;
  assign rb = ra;
endmodule
module aibcr3_dcc_8ph_intp ( SOOUT, intout, CLKIN, PDb,
     fanout, gray, iSE, iSI );

output  SOOUT, intout;

input  CLKIN, PDb, fanout, iSE, iSI;

input [2:0]  gray;

// Buses in the design

reg  [6:0]  sp_int;
reg  [6:0]  sp;
wire [6:0]  sn;

wire CK;
wire RSTb;
wire SE;

assign CK = CLKIN;
assign RSTb = PDb;
assign SE = iSE;

always @(*)
  case (gray[2:0])
    3'b000 :  sp_int[6:0] = 7'b000_0000;
    3'b001 :  sp_int[6:0] = 7'b000_0001;
    3'b011 :  sp_int[6:0] = 7'b000_0011;
    3'b010 :  sp_int[6:0] = 7'b000_0111;
    3'b110 :  sp_int[6:0] = 7'b000_1111;
    3'b111 :  sp_int[6:0] = 7'b001_1111;
    3'b101 :  sp_int[6:0] = 7'b011_1111;
    3'b100 :  sp_int[6:0] = 7'b111_1111;
  endcase

// assign sn_int[6:0] = ~sp_int[6:0];

/*
assign net0154 = sn_int[0];
assign net0271 = sn_int[1];
assign net0265 = sn_int[2];
assign g2b     = sn_int[3];
assign net0374 = sn_int[4];
assign net0372 = sn_int[5];
assign net057  = sn_int[6];

assign net058  = sp_int[0];
assign net0337 = sp_int[1];
assign net0331 = sp_int[2];
assign net0268 = sp_int[3];
assign net0324 = sp_int[4];
assign net0338 = sp_int[5];
assign net0153 = sp_int[6];
*/
/*
aibcr3_svt16_scdffsdn_cust x144 ( sn[0], SO0,   CK, sn_int[0],
     RSTb, SE, iSI);
aibcr3_svt16_scdffsdn_cust I99 ( sn[3], SO8,   CK, sn_int[3],
     RSTb, SE, SO7);
aibcr3_svt16_scdffsdn_cust I97 ( sn[5], SO10,   CK, sn_int[5],
     RSTb, SE, SO9);
aibcr3_svt16_scdffsdn_cust I96 ( sn[1], SO12,   CK, sn_int[1],
     RSTb, SE, SO11);
aibcr3_svt16_scdffsdn_cust x147 ( sn[6], SO2,   CK, sn_int[6],
     RSTb, SE, SO1);
aibcr3_svt16_scdffsdn_cust I102 ( sn[2], SO4,   CK, sn_int[2],
     RSTb, SE, SO3);
aibcr3_svt16_scdffsdn_cust I100 ( sn[4], SO6,   CK, sn_int[4],
     RSTb, SE, SO5);
*/

aibcr3_svt16_scdffcdn_cust x146 ( sp[0], SO1,   RSTb, CK,
     sp_int[0], SE, iSI);
aibcr3_svt16_scdffcdn_cust I51 ( sp[2], SO3,   RSTb, CK,
     sp_int[2], SE, SO2);
aibcr3_svt16_scdffcdn_cust I50 ( sp[4], SO4,   RSTb, CK,
     sp_int[4], SE, SO3);
aibcr3_svt16_scdffcdn_cust x151 ( sp[6], SO2,   RSTb, CK,
     sp_int[6], SE, SO1);
aibcr3_svt16_scdffcdn_cust I43 ( sp[1], SOOUT,   RSTb, CK,
     sp_int[1], SE, SO6);
aibcr3_svt16_scdffcdn_cust I49 ( sp[3], SO5,   RSTb, CK,
     sp_int[3], SE, SO4);
aibcr3_svt16_scdffcdn_cust I46 ( sp[5], SO6,   RSTb, CK,
     sp_int[5], SE, SO5);

assign sn = ~sp;

aibcr3_dcc_interpolator x142 ( intout, fanout, sn[6:0],
     sp[6:0]);

endmodule
module aibcr3_lvshift_diff ( out, outb, in, inb, por
     );

output  out, outb;


input  in, inb, por;
reg out, outb;
wire NET58 , in_shift , in_shiftb , inb , in_sw , NET59 ;
//no vcc_input, vcc_output and vss tracking as of now.
always @ (in, por, inb)
begin
	if (por == 1'b1)
	begin
		out = 1'b0;
		outb = 1'b1;
	end
	else if (por == 1'b0)
	begin
	     if ( in==1'b0 && inb==1'b0)
		begin
			out = 1'b1;
			outb = 1'b1;
		end
	     else if ( in==1'b1 && inb==1'b1)
		begin
			out = 1'bx;
			outb = 1'bx;
		end	
	     else
		begin	
			out = in;
			outb = inb;	
		end
	end
	else
	begin
		out = 1'bx;
		outb = 1'bx;
	end	
end
endmodule
module aibcr3_signal_buf ( sig_out, sig_in, vcc, vssl );

output  sig_out;

input  sig_in, vcc, vssl;

wire sig_out, sig_in;


// specify 
//     specparam CDS_LIBNAME  = "aibcr_lib";
//     specparam CDS_CELLNAME = "aibcr_signal_buf";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign sig_out = sig_in;

endmodule
module aibcr3_txanlg ( txpadout, din, indrv_buf,
     ipdrv_buf, itx_en_buf, por, weak_pulldownen, weak_pullupenb );

inout  txpadout;

input  din, itx_en_buf, por, weak_pulldownen, weak_pullupenb;

input [1:0]  ipdrv_buf;
input [1:0]  indrv_buf;

// Buses in the design

wire  [1:0]  nc2;

wire  [1:0]  ndrv_enb_shift;

wire  [1:0]  pdrv_en_buf;

wire  [1:0]  ipdrv_in;

wire  [1:0]  ndrv_enb_buf;

wire  [1:0]  pgin;

wire  [1:0]  indrv_in;

wire  [1:0]  ngin;

wire  [1:0]  pdrv_en_shift;

wire  [1:0]  nc0;

wire din_buf;
wire por_buf;

assign tieLO = 1'b0;
assign en_buf = itx_en_buf;
assign weak_pullupenbb = !weak_pullupenb;
assign por_buf = por;

aibcr3_lvshift I41 ( .out(tristateb), .outb(tristate), .in(en_buf),
     .por_high(tieLO), .por_low(por_buf));
aibcr3_lvshift I4 ( .out(nc4), .outb(weak_pullupenbb_shift), 
     .in(weak_pullupenbb), .por_high(tieLO), .por_low(por_buf));
aibcr3_lvshift I19 ( .out(weak_pden_shift), .outb(nc3), 
     .in(weak_pulldownen), .por_high(por_buf), .por_low(tieLO));
aibcr3_lvshift I29 ( .out(din_shift), .outb(nc1), .in(din), .por_high(tieLO),
     .por_low(por_buf));


assign net071 = ~ ( din_buf | tristate ) ; 
assign net072 = ~ ( din_buf & tristateb ); 
assign net074 = weak_pullupenbb_shift;
assign weak_pden_buf = weak_pden_shift;

/*
aibcr3_ulvt16_nand2_a8 I21[1:0] ( pgin[1:0], GNDC, VCCL, din_buf,
     pdrv_en_buf[1:0]);
aibcr3_lvlshift I40[1:0] ( ndrv_enb_shift[1:0], nc2[1:0], GNDC, VCCL,
     VCORE, indrv_in[1:0], tieLO, por_buf);
aibcr3_lvlshift I8[1:0] ( nc0[1:0], pdrv_en_shift[1:0], GNDC, VCCL,
     VCORE, ipdrv_in[1:0], por_buf, tieLO);
aibcr3_tx_driver_pulldown I24 ( GNDC, txpadout, ngin[1:0], net071,
     weak_pden_buf);
aibcr3_svt16_nand2_a1 I38[1:0] ( indrv_in[1:0], GNDC, VCORE,
     indrv_buf[1:0], en_buf);
aibcr3_svt16_nand2_a1 I37[1:0] ( ipdrv_in[1:0], GNDC, VCORE,
     ipdrv_buf[1:0], en_buf);
aibcr3_ulvt16_nor2_a8 I22[1:0] ( ngin[1:0], GNDC, VCCL, din_buf,
     ndrv_enb_buf[1:0]);
aibcr3_TIEHI I15 ( tieHI, GNDC, VCORE);
aibcr3_ulvt16_buf_a4 I16 ( din_buf, GNDC, VCCL, din_shift);
aibcr3_ulvt16_buf_a4 I7 ( por_buf, GNDC, VCORE, por);
aibcr3_svt16_buf_a4 I35[1:0] ( pdrv_en_buf[1:0], GNDC, VCCL,
     pdrv_en_shift[1:0]);
aibcr3_svt16_buf_a4 I13[1:0] ( ndrv_enb_buf[1:0], GNDC, VCCL,
     ndrv_enb_shift[1:0]);
aibcr3_tx_driver_pullup I23 ( VCCL, txpadout, pgin[1:0], net072,
     net074);
*/

assign (weak0, weak1) txpadout = ((weak_pden_buf & net074) == 1'b1) ? 1'b0: (((weak_pden_buf | net074) == 1'b0)? 1'b1: 1'bz);
assign txpadout = ( tristateb & din) ? 1'b1: 1'bz;
assign txpadout = ( tristateb & ~din)? 1'b0: 1'bz;


endmodule
module aibcr3_clktree_avmm_pcs 
#(
parameter SKEW_DELAY     = 60   //min:20ps; typ :60ps; max:100ps
)
(
   input  wire         clkin,                   //clock source
   output wire 	       lstrbclk_l_0, 	        //buffered clock
   output wire         lstrbclk_l_1,            //buffered clock
   output wire         lstrbclk_l_2,            //buffered clock
   output wire         lstrbclk_l_3,            //buffered clock
   output wire         lstrbclk_l_4,            //buffered clock
   output wire         lstrbclk_l_5,            //buffered clock
   output wire         lstrbclk_l_6,            //buffered clock
   output wire         lstrbclk_l_7,            //buffered clock
   output wire         lstrbclk_r_0,            //buffered clock
   output wire         lstrbclk_r_1,            //buffered clock
   output wire         lstrbclk_r_2,            //buffered clock
   output wire         lstrbclk_r_3,            //buffered clock
   output wire         lstrbclk_r_4,            //buffered clock
   output wire         lstrbclk_r_5,            //buffered clock
   output wire         lstrbclk_r_6,            //buffered clock
   output wire         lstrbclk_r_7,            //buffered clock
   output wire         lstrbclk_rep, 	        //replica for DLL
   output wire         lstrbclk_mimic0,         //mimic path for load matching
   output wire         lstrbclk_mimic1,         //mimic path for load matching   
   output wire         lstrbclk_mimic2          //mimic path for load matching
);

`ifdef TIMESCALE_EN
  timeunit 1ps;
  timeprecision 1ps;
`endif
  
                assign #SKEW_DELAY lstrbclk_l_0 = clkin;
                assign #SKEW_DELAY lstrbclk_l_1 = clkin;
                assign #SKEW_DELAY lstrbclk_l_2 = clkin;
                assign #SKEW_DELAY lstrbclk_l_3 = clkin;
                assign #SKEW_DELAY lstrbclk_l_4 = clkin;
                assign #SKEW_DELAY lstrbclk_l_5 = clkin;
                assign #SKEW_DELAY lstrbclk_l_6 = clkin;
                assign #SKEW_DELAY lstrbclk_l_7 = clkin;
                assign #SKEW_DELAY lstrbclk_r_0 = clkin;
                assign #SKEW_DELAY lstrbclk_r_1 = clkin;
                assign #SKEW_DELAY lstrbclk_r_2 = clkin;
                assign #SKEW_DELAY lstrbclk_r_3 = clkin;
                assign #SKEW_DELAY lstrbclk_r_4 = clkin;
                assign #SKEW_DELAY lstrbclk_r_5 = clkin;
                assign #SKEW_DELAY lstrbclk_r_6 = clkin;
                assign #SKEW_DELAY lstrbclk_r_7 = clkin;
                assign #SKEW_DELAY lstrbclk_rep = clkin;
                assign #SKEW_DELAY lstrbclk_mimic0 = clkin;
                assign #SKEW_DELAY lstrbclk_mimic1 = clkin;
                assign #SKEW_DELAY lstrbclk_mimic2 = clkin;

endmodule // aibcr_clktree_avmm_pcs
module aibcr3_lvshift_lospeed ( out, outb, vcc_input, vcc_output, vss, in, por_high, por_low
     );

output  out, outb;

inout  vcc_input, vcc_output, vss;

input  in, por_high, por_low;
reg out, outb;
wire NET58 , in_shift , in_shiftb , inb , in_sw , NET59 ;
//no vcc_input, vcc_output and vss tracking as of now.
always @ (in, por_high, por_low)
begin
	if ((por_high == 1'b0) && (por_low == 1'b1))
	begin
		out = 1'b0;
		outb = 1'b1;
	end
	else if ((por_high == 1'b1) && (por_low == 1'b0))
	begin
                out = 1'b1;
                outb = 1'b0;
	end
	else if ((por_high == 1'b0) && (por_low == 1'b0))
	begin
		out = in;
		outb = ~in;	
	end
	else
	begin
		out = 1'bx;
		outb = 1'bx;
	end	
end
endmodule
module aibcr3_dcc_dlyline ( SOOUT, bk_TP, crsDLY, dlyline_out, 
      CLK, PDb, SE, SI, SMCLK, gry );

output  SOOUT, crsDLY, dlyline_out;

input  CLK, PDb, SE, SI, SMCLK;

output [255:0]  bk_TP;

input [10:0]  gry;

// Buses in the design

wire  [2:0]  bufgry;

assign bufgry[2:0] = gry[2:0];
assign CLKIN = SMCLK;
assign net0113 = CLKIN;

aibcr3_dcc_8ph_intp I57 ( SOOUT, dlyline_out, net0113,
     PDb, crsDLY, bufgry[2:0], SE, SO_crc);
aibcr3_dcc_crsdlyline I58 ( SO_crc, bk_TP[255:0], crsDLY,  
     CLK, CLKIN, PDb, SE, SI, gry[10:3]);

endmodule
module aibcr3_ff_p ( 
	input wire CP,
	input wire SDN,
	input wire D,
	output reg Q
);

always@(posedge CP or negedge SDN) begin
	if (!SDN) begin
		Q <= 1'b1;
	end
	else begin
		Q <= D;
	end
end
endmodule
module aibcr3_esd ( io );

inout  io;



endmodule
module aibcr3_opio_esd (io);

  inout io;

endmodule
module aibcr3_sync_3ff (CDN, CP, D, SE, SI, Q);
    input CDN, CP, D, SE, SI;
    output reg Q;
    wire data;
    reg flop_1,flop_0;

        assign data = SE ?  SI : D ; 
	
	always @(posedge CP or negedge CDN)
		if (!CDN) {Q,flop_1,flop_0} <= 0;
		else if (CDN) {Q,flop_1,flop_0} <= {flop_1,flop_0,data};
		else {Q,flop_1,flop_0} <= 0;
endmodule
module aibcr3_txdig ( indrv_buf, ipdrv_buf, itx_en_buf, tx_dat_out,
     weak_pulldownen, weak_pullupenb, async_data, clkdr,
     idat0, idat1, idataselb, iddrctrl, ilaunch_clk, ilpbk_dat,
     ilpbk_en, indrv, ipadrstb, ipdrv, irstb, itx_en, rx_enb,
     test_weakpd, test_weakpu, testmode_en );

output  itx_en_buf, tx_dat_out, weak_pulldownen, weak_pullupenb;


input  async_data, clkdr, idat0, idat1, idataselb, iddrctrl,
     ilaunch_clk, ilpbk_dat, ilpbk_en, ipadrstb, irstb, itx_en, rx_enb,
     test_weakpd, test_weakpu, testmode_en;

output [1:0]  indrv_buf;
output [1:0]  ipdrv_buf;

input [1:0]  indrv;
input [1:0]  ipdrv;

wire net036;
wire itx_enb;
wire ff1_dout;
wire ff0_dout;
wire clk;
wire ff1_latch_dout_buf2;
wire ff0_dout_buf2;
wire async_dat_buf;
wire ipadrstb_buf;
wire weak_pulld_enb;
wire test_weakpu_buf;
wire test_weakpd_buf;
wire ff1_latch_buf1;
wire ff1_latch_dout;
wire anlg_rst_nd_out;
wire io_disable_b;

assign txenb_rxenb = ~net036;
assign itx_en_buf = ~itx_enb;
assign ff1_hold_buf0 = iddrctrl ? ff1_dout : ff0_dout;
assign mux_out = clk ? ff1_latch_dout_buf2 : ff0_dout_buf2;
assign mux_din = idataselb ? mux_out : async_dat_buf;
assign net036 = ~(rx_enb & itx_enb);
assign weak_pulldownen = ~(ipadrstb_buf & weak_pulld_enb);
assign weak_pullupenb = ~ (ipadrstb_buf & test_weakpu_buf);
assign itx_enb = ~(itx_en & ipadrstb);
assign weak_pulld_enb = ~(test_weakpd_buf | txenb_rxenb);
assign test_weakpu_buf = test_weakpu;
assign test_weakpd_buf = test_weakpd;
assign ipadrstb_buf = ipadrstb;
assign ipdrv_buf[1] = ipdrv[1];
assign ipdrv_buf[0] = ipdrv[0];
assign indrv_buf[1] = indrv[1];
assign indrv_buf[0] = indrv[0];
assign ff1_hold_buf1 = ff1_hold_buf0;
assign ff0_dout_buf1 = ff0_dout;
assign ff0_dout_buf2 = ff0_dout_buf1;
assign irstb_buf = irstb;
assign async_dat_buf = async_data;
assign tx_dat_out = mux_din;
assign din0 = idat0;
assign din1 = idat1;
assign clkb = ~clk;
assign clk = ilaunch_clk;
assign ff1_latch_dout_buf2 = ff1_latch_buf1;
assign ff1_latch_buf1 = ff1_latch_dout;
assign ff1_latch_input = ff1_hold_buf1;

/* replaced by latch
aibcr3_ulvt16_dffcdn_cust x29 ( ff1_latch_dout, irstb_buf,
     clkb, ff1_latch_input); 
*/
aibcr3_latch x29 (.Q(ff1_latch_dout), .E(clkb), .CDN(irstb_buf), .D(ff1_latch_input));

aibcr3_ulvt16_dffcdn_cust x25 ( .Q(ff1_dout), .CDN(irstb_buf), .CK(clk),
     .D(din1));
aibcr3_ulvt16_dffcdn_cust x18 ( .Q(ff0_dout), .CDN(irstb_buf), .CK(clk),
     .D(din0));


endmodule
module aibcr3_sync_2ff (CDN, CP, D, SE, SI, Q);
    input CDN, CP, D, SE, SI;
    output reg Q;
    wire data;
    reg flop_0;

        assign data = SE ?  SI : D ; 
	
	always @(posedge CP or negedge CDN)
		if (!CDN) {Q,flop_0} <= 0;
		else if (CDN) {Q,flop_0} <= {flop_0,data};
		else {Q,flop_0} <= 0;
endmodule
module aibcr3_rxanlg (  oclkn, oclkp, odat, odat_async, iopad, 
     clk_en, data_en, iclkn, por, por_vccl );

output  oclkn, oclkp, odat, odat_async;

inout  iopad;


input  clk_en, data_en, iclkn, por, por_vccl ;

wire clk_enb, clk_en_buf, preoclkpb, preoclkp, oclkpb;
wire clk_en_vccl, data_en_vccl, nc_clk_enb_vccl, nc_data_enb_vccl;
wire preoclknb, preoclkn, oclknb;
wire data_enb, data_en_buf, preodatb, preodat, odatb, preodatn, odat_inv_b, odat_inv;
wire oclkn_vccl, oclkp_vccl, odat_vccl, odat_async_vccl;
wire por_buf;
wire por_vccl_buf;


aibcr3_lvshift I4 ( .por_low(por_vccl_buf),.por_high(1'b0) , 
      .out(clk_en_vccl), .outb(nc_clk_enb_vccl),
     .in(clk_en));

aibcr3_lvshift I3 ( .por_low(por_vccl_buf),.por_high(1'b0), 
      .out(data_en_vccl), .outb(nc_data_enb_vccl),
     .in(data_en));


assign por_vccl_buf = por_vccl;
assign por_buf = por;
//wire nc1, nc2, nc3, nc4;
wire oclkp_lvlshift, oclkn_lvlshift;
wire preodatnb, odat_inv_lvlshift, odat_async_lvlshift, odat_lvlshift ;

assign clk_enb = ~clk_en_vccl;
assign clk_en_buf = ~clk_enb;

assign oclkp_vccl = (iopad & clk_en_buf);
assign oclkp = oclkp_lvlshift;

assign oclkn_vccl = ~oclkp_vccl;
assign oclkn = oclkn_lvlshift;

assign data_enb = ~data_en_vccl;
assign data_en_buf = ~data_enb;

assign odat_vccl = (iopad & data_en_buf);
assign odat = odat_lvlshift;

assign odat_async_vccl = ~odat_vccl;
assign odat_async = ~odat_inv_lvlshift;

aibcr3_lvshift_diff x15 ( .inb(oclkn_vccl), .por(por_buf), 
      .out(oclkp_lvlshift),
     .outb(oclkn_lvlshift), .in(oclkp_vccl));
aibcr3_lvshift_diff x14 ( .inb(odat_async_vccl), .por(por_buf),
     .out(odat_lvlshift), .outb(odat_inv_lvlshift), .in(odat_vccl));
endmodule
module aibcr3_lvshift ( out, outb, in, por_high, por_low
     );

output  out, outb;


input  in, por_high, por_low;
reg out, outb;
wire NET58 , in_shift , in_shiftb , inb , in_sw , NET59 ;
//no vcc_input, vcc_output and vss tracking as of now.
always @ (in, por_high, por_low)
begin
	if ((por_high == 1'b0) && (por_low == 1'b1))
	begin
		out = 1'b0;
		outb = 1'b1;
	end
	else if ((por_high == 1'b1) && (por_low == 1'b0))
	begin
                out = 1'b1;
                outb = 1'b0;
	end
	else if ((por_high == 1'b0) && (por_low == 1'b0))
	begin
		out = in;
		outb = ~in;	
	end
	else
	begin
		out = 1'bx;
		outb = 1'bx;
	end	
end
endmodule
module aibcr3_inv_split_align ( din, dout, vccl, vssl );

  input din;
  output dout;
  input vssl;
  input vccl;


  assign dout = ~din ;

endmodule
module c3aibadapt_txasync_rsvd_capture (
// 
input   wire   [2:0]    pld_tx_ssr_reserved_in,

// SR
input   wire            tx_async_hssi_fabric_ssr_load,

// TXCLK_CTL
input   wire            tx_clock_async_tx_osc_clk,         

// TXRST_CTL
input   wire            tx_reset_async_tx_osc_clk_rst_n,  

// SR
output  wire   [2:0]    tx_async_hssi_fabric_ssr_reserved 
);

wire [2:0] nc_0;

// SLOW SR:
generate
  genvar i;
    for (i=0; i < 3; i=i+1) begin: c3adapt_cmn_async_capture_bit
       c3aibadapt_cmn_async_capture_bit
     #(
       .SYNC_STAGE  (3),
       .RESET_VAL   (0)
       )
       async_tx_reserved_ssr_in     
      (
          .clk         (tx_clock_async_tx_osc_clk),
          .rst_n       (tx_reset_async_tx_osc_clk_rst_n),
          .data_in     (pld_tx_ssr_reserved_in[i]),
          .unload      (tx_async_hssi_fabric_ssr_load),
          .data_in_sync_out (nc_0[i]),
          .data_out    (tx_async_hssi_fabric_ssr_reserved[i])
      );
   end
endgenerate
 
endmodule
module c3aibadapt_txasync_rsvd_update (
// SR
input   wire            tx_async_fabric_hssi_ssr_load, 
input   wire    [2:0]   tx_async_fabric_hssi_ssr_reserved,

// TXCLK_CTL
input   wire            tx_clock_async_rx_osc_clk,      

// TXRST_CTL
input   wire            tx_reset_async_rx_osc_clk_rst_n, 

// HIP IF
output  wire   [2:0]    pld_tx_ssr_reserved_out 
);

// SLOW SR: 
c3aibadapt_async_update
    #( .AWIDTH       (3),
       .RESET_VAL    (1)
     ) async_tx_reserved_ssr_out 
     ( .clk             (tx_clock_async_rx_osc_clk),
       .rst_n           (tx_reset_async_rx_osc_clk_rst_n),
       .sr_load         (tx_async_fabric_hssi_ssr_load),
       .async_data_in   (tx_async_fabric_hssi_ssr_reserved),
       .async_data_out  (pld_tx_ssr_reserved_out)
     );

endmodule
module c3aibadapt_async_update  
 #(
    parameter AWIDTH    = 1,    // Async input width
    parameter RESET_VAL = 0     // Reset value
  )
(
input  wire              clk,     
input  wire              rst_n,   
input  wire              sr_load,
input  wire [AWIDTH-1:0] async_data_in, 
output reg  [AWIDTH-1:0] async_data_out 
);

localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0;

always @(negedge rst_n or posedge clk)
  if (rst_n == 1'b0)
    begin
      async_data_out[AWIDTH-1:0] <= {(AWIDTH){reset_value}};
    end
  else
    begin
      async_data_out[AWIDTH-1:0] <= sr_load ? async_data_in[AWIDTH-1:0] : async_data_out[AWIDTH-1:0];
    end


endmodule
module c3aibadapt_txasync_direct (
// PCS IF
input	wire		pld_pma_fpll_lc_lock,

// AIB IF
input   wire            aib_hssi_pld_pma_txdetectrx,

// PCS IF
output	wire		pld_pma_txdetectrx,

// AIB IF
output  wire            aib_hssi_pld_pma_fpll_lc_lock

);


assign pld_pma_txdetectrx            = aib_hssi_pld_pma_txdetectrx;
assign aib_hssi_pld_pma_fpll_lc_lock = pld_pma_fpll_lc_lock;

endmodule
module c3aibadapt_tx_dprio(

// tx_datapath
        output   wire    [15:0]  avmm_tx_datapath_user_datain,
        output   wire            r_10g_mode    ,
        output   wire            r_bonding_dft_in_en,
        output   wire            r_bonding_dft_in_value,
        output   wire    [7:0]   r_comp_cnt,
        output   wire    [1:0]   r_compin_sel,
        output   wire            r_double_read,
        output   wire            r_ds_bypass_pipeln,
        output   wire            r_ds_master,
        output   wire    [3:0]   r_empty,
        output   wire            r_empty_type  ,
        output   wire    [2:0]   r_fifo_mode,
        output   wire    [3:0]   r_full,
        output   wire            r_full_type   ,
        output   wire    [2:0]   r_gb_idwidth  ,
        output   wire    [1:0]   r_gb_odwidth  ,
        output   wire            r_indv,
        output   wire    [3:0]   r_pempty,
        output   wire            r_pempty_type ,
        output   wire    [3:0]   r_pfull,
        output   wire            r_pfull_type  ,
        output   wire    [2:0]   r_phcomp_rd_delay,
        output   wire            r_stop_read   ,
        output   wire            r_stop_write  ,
        output   wire            r_us_bypass_pipeln,
        output   wire            r_us_master,

// tx_async
	output   wire    [23:0]  avmm_tx_async_user_datain,
// txclk_ctrl
	output wire    [9:0]  tx_user_clk_config
// txrst_ctrl
);



endmodule
module c3aibadapt_txdp_word_align 
  #(
    parameter DWIDTH = 'd40             // FIFO Input data width 
    )
    (
    input  wire               wr_clk,      	  // clock
    input  wire               wr_rst_n,       	  // async reset
    input  wire               wr_srst_n,       	  // sync reset
    input  wire               r_wa_en,            // Word-align enable  
    input  wire [DWIDTH-1:0]  aib_hssi_tx_data_in,    // Write Data In
    input  wire		      mark_bit_location,
    output wire		      wa_lock,		  // Go to FIFO, status reg
    output wire [19:0]	      word_align_testbus
    );
    
 //********************************************************************
// Define Parameters 
//********************************************************************


//********************************************************************
// Define variables 
//********************************************************************

reg		        wm_bit;
reg		        wm_bit_d1;
reg		        wm_bit_d2;
reg		        wm_bit_d3;
reg		        wm_bit_d4;
reg		        wm_bit_d5;
reg			wa_lock_lt;
wire			wa_lock_int;
//********************************************************************
// Main logic 
//********************************************************************



//Word-align
always @(negedge wr_rst_n or posedge wr_clk) begin
   if (wr_rst_n == 1'b0) begin
     wm_bit 	 <= 1'b0;
     wm_bit_d1 <= 1'b0;
     wm_bit_d2 <= 1'b0;
     wm_bit_d3 <= 1'b0;
     wm_bit_d4 <= 1'b0;
     wm_bit_d5 <= 1'b0;
   end
   else if (wr_srst_n == 1'b0) begin
     wm_bit 	 <= 1'b0;
     wm_bit_d1 <= 1'b0;
     wm_bit_d2 <= 1'b0;
     wm_bit_d3 <= 1'b0;
     wm_bit_d4 <= 1'b0;
     wm_bit_d5 <= 1'b0;
   end
   else begin
     wm_bit 	 <= ~mark_bit_location ? aib_hssi_tx_data_in[39] : aib_hssi_tx_data_in[19];
     wm_bit_d1 <= wm_bit;
     wm_bit_d2 <= wm_bit_d1;
     wm_bit_d3 <= wm_bit_d2;
     wm_bit_d4 <= wm_bit_d3;
     wm_bit_d5 <= wm_bit_d4;
   end
end

always @(negedge wr_rst_n or posedge wr_clk) begin
   if (wr_rst_n == 1'b0) begin
     wa_lock_lt 	 <= 1'b0;
   end
   else if (wr_srst_n == 1'b0) begin
     wa_lock_lt 	 <= 1'b0;
   end   else begin
     wa_lock_lt 	 <= wa_lock_int || wa_lock_lt;
   end
end

assign wa_lock_int = wm_bit && ~wm_bit_d1 && wm_bit_d2 && ~wm_bit_d3 && wm_bit_d4 && ~wm_bit_d5 || ~r_wa_en;

assign wa_lock = wa_lock_int || wa_lock_lt;

//assign wa_error = (data_out[39] || ~data_out[79]) && r_wa_en && rd_en_reg;

//always @(negedge wr_rst_n or posedge wr_clk) begin
//   if (wr_rst_n == 1'b0) begin
//     wa_error_cnt <= 1'b0;
//   end
//   else if (wa_error_cnt < 4'b1111 && wa_error) begin
//     wa_error_cnt 	<= wa_error_cnt + 1'b1;
//   end
//end

assign word_align_testbus = {13'd0, wa_lock, wm_bit, wm_bit_d1, wm_bit_d2, wm_bit_d3, wm_bit_d4, wm_bit_d5};
  
endmodule
module c3aibadapt_txdp_fifo_ram
  #(
    parameter DWIDTH = 'd40,             // FIFO Input data width 
    parameter DEPTH  = 'd16              // FIFO Depth 
    )
(
    input  wire              r_double_read,	// Read from 2 consecutive locations
    input  wire		     r_stop_write, // Disable/enable writing when FIFO is full    
    input  wire              wr_clk,     // Write Domain Clock
    input  wire		     wr_rst_n,   // Write Domain Reset 
    input  wire		     wr_full,
    input  wire              wr_en,      // Write Data Enable
    input  wire [DEPTH-1:0] wr_ptr,     // Write Pointer
    input  wire [DWIDTH-1:0] wr_data,    // Write Data In
    input  wire [DEPTH-1:0] rd_ptr,     // Read Pointer
    output reg  [DWIDTH-1:0] rd_data,   // Read Data
    output reg  [DWIDTH-1:0] rd_data2    // Read Data

);

   //********************************************************************
   // Infer Memory or use Dual Port Memory from Quartus/ASIC Memory
   //********************************************************************

   wire 	[DEPTH-1:0]	rd_ptr2;   
   integer		m;
   integer		i, j;
//   reg [DWIDTH-1:0]          fifo_mem [((1<<AWIDTH)-1):0];
   reg [DWIDTH-1:0]          fifo_mem [DEPTH-1:0];
   
   always @(negedge wr_rst_n or posedge wr_clk) begin
      if (~wr_rst_n) begin
         for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1)
            fifo_mem[m] <= 'd0;	
      end 
      else if (wr_en &&  (~wr_full||~r_stop_write)) begin
         for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1) begin
           if (wr_ptr[m]) begin
             fifo_mem[m] <= wr_data;
             end  
         end   
      end
   end

   assign rd_ptr2 = {rd_ptr[DEPTH-2:0], rd_ptr[DEPTH-1]};   
   
   always @ *
   begin: data_out 
     rd_data = fifo_mem[0];
     for (i='d0; i<=(DEPTH-1'b1); i=i+1'b1) begin
       if (rd_ptr[i]) begin
         rd_data = fifo_mem[i];
       end       
     end   
      end 
      
      always @ *
      begin: data_out2 
        rd_data2 = fifo_mem[0];
     for (j='d0; j<=(DEPTH-1'b1); j=j+1'b1) begin
          if (rd_ptr2[j]) begin
            rd_data2 = fifo_mem[j];
       end       
     end   
   end 
   
endmodule
module c3aibadapt_txchnl_testbus 
    (
    input   wire  [2:0]           r_tx_datapath_tb_sel,  // testbus sel
    input   wire [19:0]           tx_fifo_testbus1, 		// RX FIFO
    input   wire [19:0]           tx_fifo_testbus2, 		// RX FIFO
    input   wire [19:0]           word_align_testbus,
    input   wire [19:0]           tx_cp_bond_testbus,
    input   wire [19:0]           tx_hrdrst_testbus,    
    
    output  reg [19:0]		  tx_chnl_testbus
     );
   
    always @* begin
      case (r_tx_datapath_tb_sel)
        3'b000: tx_chnl_testbus = word_align_testbus;
        3'b001: tx_chnl_testbus = tx_fifo_testbus1;
        3'b010: tx_chnl_testbus = tx_fifo_testbus2;
        3'b011: tx_chnl_testbus = tx_cp_bond_testbus;
        3'b100: tx_chnl_testbus = tx_hrdrst_testbus;
        default: tx_chnl_testbus = {20{1'b0}};
      endcase // case(r_rx_testbus_sel)
    end // always @ *
         
endmodule // c3aibadapt_tx_chnl_testbus
module c3aibadapt_txclk_gate
(
	input	wire		cp,
	input	wire		e,
	input	wire		te,
	output	wire		q
);

	wire	clk;
	wire	clk_n;
	wire	clken;
	reg	latch_clken;

	assign clk = cp;
	assign clk_n = ~cp;
	assign clken = e || te;

        always @(clk_n or clken)
        begin
		if (clk_n)
                begin
                        latch_clken <= clken;
                end
        end

	assign q = clk & latch_clken;

endmodule // c3aibadapt_txclk_gate
module c3aibadapt_ssr_in 
 #(
    parameter NUM_OF_PCS_CHAIN   = 16, 
    parameter NUM_OF_HIP_CHAIN   = 16,
    parameter NUM_OF_RESERVED_CHAIN_SSRIN = 5,
    parameter NUM_OF_PARITY_BIT_SSRIN = 6
  )
(
input wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1):0] sr_parallel_in,
input wire                    sr_load,
input wire                    clk,
input wire                    rst_n,
input wire                    r_sr_hip_en,
input wire                    r_sr_parity_en,
input wire                    r_sr_reserbits_in_en,
output wire                   sr_serial_out
);

wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1):0]  sr_datain_int;
wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1):0]  sr_dataout_int;

assign sr_datain_int[0] = sr_dataout_int[0];

generate
  genvar i; 
  for (i=0; i < (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN) ; i=i+1) begin: c3adapt_sr_in_bit
       c3aibadapt_sr_in_bit 
       #(
           .RESET_VAL (0)
        ) c3adapt_sr_in_bit
         (
           // input
           .sr_load_in   (sr_parallel_in[i]),
           .sr_shift_in  (sr_datain_int[i]),
           .sr_load      (sr_load),
           .clk          (clk),
           .rst_n        (rst_n),
           // output
           .sr_dataout   (sr_dataout_int[i])
         );
  end
endgenerate

generate
  genvar j;
  for (j=1; j < (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN); j=j+1)
  begin: ssr_in_chain_connection
    if (j == (NUM_OF_PCS_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN)) begin
        assign sr_datain_int[j] = r_sr_reserbits_in_en ? sr_dataout_int[j-1] : sr_dataout_int[NUM_OF_PCS_CHAIN-1];
    end
    else begin
        assign sr_datain_int[j] = sr_dataout_int[j-1];
    end
  end
endgenerate

assign sr_serial_out = r_sr_hip_en          ? sr_dataout_int[NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1] :
                       r_sr_parity_en       ? sr_dataout_int[NUM_OF_PCS_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN + NUM_OF_PARITY_BIT_SSRIN - 1] : 
                       r_sr_reserbits_in_en ? sr_dataout_int[NUM_OF_PCS_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1] : sr_dataout_int[NUM_OF_PCS_CHAIN - 1];

endmodule
module c3aibadapt_sr_in_bit
 #(
    parameter RESET_VAL    = 0     // Reset value
  )
(
input wire  sr_load_in,
input wire  sr_shift_in,
input wire  sr_load,
input wire  clk,
input wire  rst_n,

output reg  sr_dataout
);

localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0;

always @(negedge rst_n or posedge clk)
  if (rst_n == 1'b0)
    begin
      sr_dataout <= reset_value;
    end
  else
    begin
      sr_dataout <= sr_load ? sr_load_in : sr_shift_in;
    end


endmodule
module c3aibadapt_sr_async_capture_bus 
   #(
      parameter RESET_VAL     = 1, // 1: Active high; 0: Active low
      parameter DWIDTH           = 2  // Sync Data input 
    )
   (
   // Inputs
   input  wire               clk,      	  // clock
   input  wire               rst_n,       // async reset
   input  wire [DWIDTH-1:0]  data_in,     // data in
   input  wire		     unload,      // unload data out
   input  wire		     r_capt_mode,      // capture mode
   // Outputs
   output reg  [DWIDTH-1:0]  data_out     // data out
   );

//******************************************************************************
// Define regs
//******************************************************************************
reg  [DWIDTH-1:0]		data_in_sync_d0;
reg  [DWIDTH-1:0]		data_in_sync_d1;
wire [DWIDTH-1:0] 		data_in_sync;
reg				sample;

   localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0;  // To eliminate truncating warning


// hd_dpcmn_bitsync2
c3lib_bitsync
  #(
  .SRC_DATA_FREQ_MHZ    (500),         // Source data freq
  .DST_CLK_FREQ_MHZ    (1000),        // Dest clock freq
  .DWIDTH               (DWIDTH),      // Sync Data input
  .RESET_VAL            (reset_value)  // Reset value
  )
   bitsync2
      (
      .clk      (clk),
      .rst_n    (rst_n),
      .data_in  (data_in),
      .data_out (data_in_sync)
      );

   always @(negedge rst_n or posedge clk) begin
      if (rst_n == 1'b0) begin
        begin
          data_in_sync_d0 	<= {DWIDTH{reset_value}};
          data_in_sync_d1 	<= {DWIDTH{reset_value}};
        end
     end
     else begin
          data_in_sync_d0 	<= data_in_sync;
          data_in_sync_d1 	<= data_in_sync_d0;
        end
   end        
     
     
     
   always @(negedge rst_n or posedge clk) begin
      if (rst_n == 1'b0) begin
        begin
          sample 		<= 1'b0;
          data_out 		<= {DWIDTH{reset_value}};
        end
     end
     else begin
     // No sample during unload
         if (unload) begin
           sample <= 1'b0;
         end
     // Sample on the first data change after unload      
         else begin  
           if (r_capt_mode) begin
             if (~sample)   
               sample   <= 1'b1;
               data_out <= data_in_sync;
           end
           else begin
             if  (~sample && data_in_sync == data_in_sync_d0 && data_in_sync_d0 == data_in_sync_d1) begin
               sample   <= 1'b1;
               data_out <= data_in_sync_d1;
             end
           end
           
         end  
     end
   end

endmodule
module c3aibadapt_fsr_out 
 #(
    parameter NUM_OF_PCS_CHAIN   = 16, 
    parameter NUM_OF_HIP_CHAIN   = 16,
    parameter NUM_OF_PARITY_BIT_FSROUT = 1 
  )
(
input wire                    sr_serial_in,
input wire                    sr_load,
input wire                    clk,
input wire                    rst_n,
input wire                    r_sr_hip_en,
input wire                    r_sr_parity_en,
//input wire  [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0] r_sr_bit,
output wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0] sr_parallel_out
);

localparam NUM_OF_UNUSED_HIP_CHAIN = NUM_OF_HIP_CHAIN - NUM_OF_PARITY_BIT_FSROUT;

wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0]  sr_datain_int;
wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0]  sr_dataout_int;

assign sr_datain_int[0] = sr_serial_in;

generate
  genvar i;
  for (i=0; i < (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN); i=i+1) begin: c3adapt_sr_out_bit
       c3aibadapt_sr_out_bit
       #(
           .RESET_VAL (0)
        ) c3adapt_sr_out_bit
         (
           // input
           .sr_shift_in  (sr_datain_int[i]),
           .sr_load      (sr_load),
           .clk          (clk),
           .rst_n        (rst_n),
           // output
           .sr_dataout   (sr_dataout_int[i])
         );
  end
endgenerate

generate
  genvar j;
  for (j=1; j < (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN); j=j+1)
  begin: fsr_out_chain_connection
    assign sr_datain_int[j] = sr_dataout_int[j-1];
  end
endgenerate


assign sr_parallel_out = r_sr_hip_en ? sr_dataout_int : !r_sr_parity_en ? {{NUM_OF_HIP_CHAIN{1'b0}},sr_dataout_int[NUM_OF_PCS_CHAIN-1:0]} : {{NUM_OF_UNUSED_HIP_CHAIN{1'b0}}, sr_dataout_int[NUM_OF_PARITY_BIT_FSROUT+NUM_OF_PCS_CHAIN-1:0]};  

endmodule