dakies/OSS_Verilog huggingface dataset:
module cpu_sys_addr_router_001_default_decode
  #(
     parameter DEFAULT_CHANNEL = 1,
               DEFAULT_WR_CHANNEL = -1,
               DEFAULT_RD_CHANNEL = -1,
               DEFAULT_DESTID = 1 
   )
  (output [79 - 77 : 0] default_destination_id,
   output [5-1 : 0] default_wr_channel,
   output [5-1 : 0] default_rd_channel,
   output [5-1 : 0] default_src_channel
  );

  assign default_destination_id = 
    DEFAULT_DESTID[79 - 77 : 0];

  generate begin : default_decode
    if (DEFAULT_CHANNEL == -1) begin
      assign default_src_channel = '0;
    end
    else begin
      assign default_src_channel = 5'b1 << DEFAULT_CHANNEL;
    end
  end
  endgenerate

  generate begin : default_decode_rw
    if (DEFAULT_RD_CHANNEL == -1) begin
      assign default_wr_channel = '0;
      assign default_rd_channel = '0;
    end
    else begin
      assign default_wr_channel = 5'b1 << DEFAULT_WR_CHANNEL;
      assign default_rd_channel = 5'b1 << DEFAULT_RD_CHANNEL;
    end
  end
  endgenerate

endmodule
module cpu_sys_addr_router_default_decode
  #(
     parameter DEFAULT_CHANNEL = 2,
               DEFAULT_WR_CHANNEL = -1,
               DEFAULT_RD_CHANNEL = -1,
               DEFAULT_DESTID = 1 
   )
  (output [79 - 77 : 0] default_destination_id,
   output [5-1 : 0] default_wr_channel,
   output [5-1 : 0] default_rd_channel,
   output [5-1 : 0] default_src_channel
  );

  assign default_destination_id = 
    DEFAULT_DESTID[79 - 77 : 0];

  generate begin : default_decode
    if (DEFAULT_CHANNEL == -1) begin
      assign default_src_channel = '0;
    end
    else begin
      assign default_src_channel = 5'b1 << DEFAULT_CHANNEL;
    end
  end
  endgenerate

  generate begin : default_decode_rw
    if (DEFAULT_RD_CHANNEL == -1) begin
      assign default_wr_channel = '0;
      assign default_rd_channel = '0;
    end
    else begin
      assign default_wr_channel = 5'b1 << DEFAULT_WR_CHANNEL;
      assign default_rd_channel = 5'b1 << DEFAULT_RD_CHANNEL;
    end
  end
  endgenerate

endmodule
module draw(clk_25M, charBuffer, hSync, vSync, red, green, blue);
   			 
   input clk_25M;
   input [ASCII_SIZE-1:0] charBuffer [CHARS_VERT-1:0][CHARS_HORZ-1:0];
   
   output wire hSync, vSync;
   output reg [3-1:0] red, green, blue;

   // Text mode parameters
      
   // Opposite order of each array element to keep ROM human readable
   reg [0:ASCII_SIZE-1] fontRom [ROM_SIZE-1:0];

   wire 	       draw;
   wire [32-1:0]       hPos, vPos;
   hvSyncGen hvInst(clk_25M, hSync, vSync, draw, hPos, vPos);
 
   initial begin
       {{red}, {green}, {blue}} = 12'h000;
       // Initialise font ROM
       $readmemb("/home/suyash/vgaCharRom.bin", fontRom);
   end

   function getXYPixel;
      input [32-1:0] hPos, vPos;
      input [0:ASCII_SIZE-1] fontRom [ROM_SIZE-1:0];
      input [8-1:0] 	    charBuffer [CHARS_VERT-1:0][CHARS_HORZ-1:0];

       getXYPixel = fontRom[(charBuffer[vPos>>4][hPos>>3])<<4 + (vPos&4'b111)][hPos&3'b111];
   endfunction // getXYPixel

   always @(hPos, vPos) begin
       //$display("%d:%d", hPos, vPos);
       //{{red}, {green}, {blue}} = {12{getXYPixel(hPos, vPos, fontRom, charBuffer)}};
       {{red}, {green}, {blue}} = {12{fontRom[(charBuffer[vPos/16][hPos/8])*16 + (vPos&4'b1111)][hPos&3'b111]}};
       
       //$display("For hPos: %d vPos: %d, got x: %d y: %d %d %d %d", hPos, vPos, charBuffer[vPos>>4][hPos>>3]<<4 + vPos&4'b1111, hPos&3'b111, vPos>>4, hPos>>4, vPos&4'b1111);
   end
endmodule // draw
module hvSyncGen(clk_25M, hSync, vSync, draw, hPos, vPos);
   input clk_25M;   
   output hSync, vSync, draw;
   output [32-1:0] hPos, vPos;
   
`ifdef DEBUG
   parameter FP_H = 48, H = 640, BP_H = 48, RT_H = 96;
   parameter FP_V = 33, V = 480, BP_V = 33, RT_V = 2;
`else
   parameter FP_H = 16, H = 640, BP_H = 48, RT_H = 96;
   parameter FP_V = 10, V = 480, BP_V = 33, RT_V = 2;
`endif
   
   integer hCounter, vCounter;
   
   function genXSync;
      input integer   counter, fp, disp, bp, rt;
       begin : genXSync_block
	   genXSync = (counter > disp + fp) && (counter < disp + fp + rt) 
	     ? 1'b1 : 1'b0;
       end
   endfunction // function

   function genDrawPulse;
      input integer hCounter, vCounter;
      input integer fp_h, h;
      input integer fp_v, v;
       
       if ((hCounter - fp_h < h && hCounter > fp_h) && (vCounter - fp_v < v && vCounter > fp_v)) begin
	   genDrawPulse = 1'b1;
       end else begin
	   genDrawPulse = 1'b0;
       end
   endfunction // genDrawPulse

   assign hPos = (hCounter < H) ? hCounter : 0;
   assign vPos = (vCounter < V) ? vCounter : 0;
   
   assign hSync = genXSync(hCounter, FP_H, H, BP_H, RT_H);
   assign vSync = genXSync(vCounter, FP_V, V, BP_V, RT_V);
   assign draw = genDrawPulse(hCounter, vCounter, FP_H, H, FP_V, V);

   initial begin
       hCounter = 0;
       vCounter = 0;
   end

   always @(posedge (hCounter == 0)) begin
       vCounter = (vCounter == FP_V + V + BP_V + RT_V) ? 1'b0 : vCounter + 1;
   end
   
   always @(posedge clk_25M) begin
       hCounter = (hCounter == FP_H + H + BP_H + RT_H) ? 1'b0 : hCounter + 1;
   end
endmodule // hvSyncGen
module mul_hash(clk, a, ab0, ab1, ab2, ab3);

input clk;
input[7:0] a;

// 4 terms of multiply
output reg [23:0] ab0;
output reg [23:0] ab1;
output reg [23:0] ab2;
output reg [23:0] ab3;

wire [63:0] b = 64'h0b4e0ef37bc32127;

reg [7:0] a_reg0;
reg [7:0] a_reg1;
reg [7:0] a_reg2;

wire [15:0] b0  = b[15: 0];
wire [15:0] b1  = b[31:16];
wire [15:0] b2  = b[47:32];
wire [15:0] b3  = b[63:48];
  
reg [23:0] ab0_reg0;
reg [23:0] ab1_reg0;
reg [23:0] ab2_reg0;
reg [23:0] ab3_reg0;

reg [23:0] ab0_reg1;
reg [23:0] ab1_reg1;
reg [23:0] ab2_reg1;
reg [23:0] ab3_reg1;

// Register inputs and outputs
always @ (posedge clk) begin
  a_reg0      <= a;
  a_reg1      <= a_reg0;
  a_reg2      <= a_reg1;

  ab0_reg0 <= a_reg2 * b0;
  ab1_reg0 <= a_reg2 * b1;
  ab2_reg0 <= a_reg2 * b2;
  ab3_reg0 <= a_reg2 * b3;

  ab0_reg1 <= ab0_reg0;
  ab1_reg1 <= ab1_reg0;
  ab2_reg1 <= ab2_reg0;
  ab3_reg1 <= ab3_reg0;

  ab0 <= ab0_reg1;
  ab1 <= ab1_reg1;
  ab2 <= ab2_reg1;
  ab3 <= ab3_reg1;
end

endmodule
module hashtable(clk,
	addr0,addr0_valid,addr1,addr1_valid,
	dout0,dout0_valid,dout1,dout1_valid
);
parameter NBITS = 15;
parameter DWIDTH = 16;
parameter MEM_SIZE = 32768;
parameter INIT_FILE = "./hashtable1.mif";
parameter BM_AWIDTH = (NBITS-3);

input clk;
input [NBITS-1:0] addr0;
input addr0_valid;
input [NBITS-1:0] addr1;
input addr1_valid;
output reg [DWIDTH-1:0] dout0;
output reg dout0_valid;
output reg [DWIDTH-1:0] dout1;
output reg dout1_valid;

reg [NBITS-1:0] addr0_r1;
reg [NBITS-1:0] addr1_r1;
reg [NBITS-1:0] addr0_r2;
reg [NBITS-1:0] addr1_r2;

wire [BM_AWIDTH-1:0] bm_addr0;
wire [BM_AWIDTH-1:0] bm_addr1;
wire [2:0] bm_bit0;
wire [2:0] bm_bit1;
reg  [2:0] bm_bit0_reg1;
reg  [2:0] bm_bit1_reg1;
reg  [2:0] bm_bit0_reg2;
reg  [2:0] bm_bit1_reg2;

reg out0_valid_reg1;
reg out1_valid_reg1;
reg q0_valid;
reg q1_valid;
wire [7:0] q0;
wire [7:0] q1;

assign bm_addr0 = addr0[NBITS-1:3];
assign bm_addr1 = addr1[NBITS-1:3];
assign bm_bit0  = addr0[2:0];
assign bm_bit1  = addr1[2:0];

always @ (posedge clk) begin
    out0_valid_reg1 <= addr0_valid;
    out1_valid_reg1 <= addr1_valid;
    q0_valid <= out0_valid_reg1;
    q1_valid <= out1_valid_reg1;
    bm_bit0_reg1 <= bm_bit0;
    bm_bit0_reg2 <= bm_bit0_reg1;
    bm_bit1_reg1 <= bm_bit1;
    bm_bit1_reg2 <= bm_bit1_reg1;

    //propogate addresses
    addr0_r1 <= addr0;
    addr1_r1 <= addr1;
    addr0_r2 <= addr0_r1;
    addr1_r2 <= addr1_r1;

    dout0 <= addr0_r2;
    dout1 <= addr1_r2;
    //dout0_valid <= q0_valid & (q0[DWIDTH-1]==0);
    //dout1_valid <= q1_valid & (q1[DWIDTH-1]==0);

    //use bitmap to indicate whether it is a match or not
    dout0_valid <= q0_valid & ((q0 >> bm_bit0_reg2) & 1);
    dout1_valid <= q1_valid & ((q1 >> bm_bit1_reg2) & 1);
end

rom_2port #(
	.DWIDTH(8),
	.AWIDTH(BM_AWIDTH),
	.MEM_SIZE(MEM_SIZE),
	.INIT_FILE(INIT_FILE)
)
rom_2port_inst (
	.q_a       (q0),    
	.q_b       (q1),    
	.address_a (bm_addr0),
	.address_b (bm_addr1),
	.clock     (clk)
);

endmodule
module mul_hash(clk,a,p);
input clk;
input[63:0] a;
output reg [63:0] p;

localparam ANDMSK = 64'hdfdfdfdfdfdfdfdf;
wire [63:0] b = 64'h0b4e0ef37bc32127;

reg [63:0] a_reg0;
reg [63:0] a_reg1;
reg [63:0] a_reg2;

(* srl_style = "register" *) reg [63:0] a_reg3;
(* srl_style = "register" *) reg [63:0] a_reg4;
(* srl_style = "register" *) reg [63:0] a_reg5;

(* srl_style = "register" *) reg [63:0] sum_reg0;
(* srl_style = "register" *) reg [63:0] sum_reg1;
(* srl_style = "register" *) reg [63:0] sum_reg2;

always @ (posedge clk) begin
  a_reg3   <= a_reg2;
  a_reg4   <= a_reg3;
  a_reg5   <= a_reg4;

  sum_reg0 <= a_reg5 * b;
  sum_reg1 <= sum_reg0;
  sum_reg2 <= sum_reg1;
end

// Sign and mask handling
reg in_v_reg0;
reg in_v_reg1;

wire signed [63:0] temp;
wire [63:0] after_and;

reg sign;
reg sign_r1;
reg sign_r2;
reg sign_r3;
reg sign_r4;
reg sign_r5;
reg sign_r6;
reg sign_r7;

reg valid;
reg valid_r1;
reg valid_r2;
reg valid_r3;
reg valid_r4;
reg valid_r5;
reg valid_r6;
reg valid_r7;
reg valid_r8;
reg valid_r9;
reg valid_r10;

always @ (posedge clk) begin
    a_reg0 <= a;

    a_reg1 <= a_reg0 & ANDMSK;
    if(a_reg0[63]) begin
			  sign <= 1;
		end else begin
			  sign <= 0;
		end		

    if(sign) begin
        a_reg2 <= ~a_reg1 + 1;
    end else begin
        a_reg2 <= a_reg1;
    end

		sign_r1 <= sign;
		sign_r2 <= sign_r1;
		sign_r3 <= sign_r2;
		sign_r4 <= sign_r3;
		sign_r5 <= sign_r4;
		sign_r6 <= sign_r5;
		sign_r7 <= sign_r6;

		if(sign_r7) begin
			p <= ~sum_reg2 + 1;
		end else begin
			p <= sum_reg2;
		end
end

endmodule
module rom_2port #(
	parameter DWIDTH    = 8,
	parameter AWIDTH    = 8,
	parameter MEM_SIZE  = (2**AWIDTH),
	parameter INIT_FILE = ""
) (

  input  wire              clock,
  input  wire [AWIDTH-1:0] address_a,
  input  wire [AWIDTH-1:0] address_b,

  output reg  [DWIDTH-1:0] q_a,
  output reg  [DWIDTH-1:0] q_b
);

  reg [DWIDTH-1:0] mem [0:(1<<AWIDTH)-1];
  reg [AWIDTH-1:0] address_a_r;
  reg [AWIDTH-1:0] address_b_r;

  always @ (posedge clock) begin
    address_a_r <= address_a;
    address_b_r <= address_b;

    q_a <= mem[address_a_r];
    q_b <= mem[address_b_r];
  end

  initial begin
    if (INIT_FILE!="")
      $readmemh(INIT_FILE, mem);
  end

endmodule
module uram_2rw_reg #(
	parameter DWIDTH    = 8,
	parameter AWIDTH    = 8,
  parameter LWIDTH    = DWIDTH,
	parameter MEM_SIZE  = (2**AWIDTH)
) (

  input  wire              clock,

  input  wire              en_a,
  input  wire [AWIDTH-1:0] address_a,
  input  wire [LWIDTH-1:0] wr_data_a,
  input  wire              wr_en_a,
  output wire [DWIDTH-1:0] q_a,

  input  wire              en_b,
  input  wire [AWIDTH-1:0] address_b,
  input  wire [LWIDTH-1:0] wr_data_b,
  input  wire              wr_en_b,
  output wire [DWIDTH-1:0] q_b
);

  localparam DEPTH = (LWIDTH==DWIDTH) ? AWIDTH : 
                   AWIDTH-$clog2(LWIDTH/DWIDTH);

  localparam SEL_BITS = AWIDTH-DEPTH;

  (* ram_style = "ultra" *)
  reg [LWIDTH-1:0] mem [0:(1<<DEPTH)-1];

  reg              en_a_r;
  reg              wr_en_a_r;
  reg [AWIDTH-1:0] address_a_r;
  reg [LWIDTH-1:0] wr_data_a_r;
  reg [LWIDTH-1:0] q_a_r;

  reg              en_b_r;
  reg              wr_en_b_r;
  reg [AWIDTH-1:0] address_b_r;
  reg [LWIDTH-1:0] wr_data_b_r;
  reg [LWIDTH-1:0] q_b_r;

  // Input register
  always @ (posedge clock) begin
    en_a_r      <= en_a;
    wr_en_a_r   <= wr_en_a;
    address_a_r <= address_a;
    wr_data_a_r <= wr_data_a;

    en_b_r      <= en_b;
    wr_en_b_r   <= wr_en_b;
    address_b_r <= address_b;
    wr_data_b_r <= wr_data_b;
  end

  always @ (posedge clock)
    if (en_a_r)
      if (wr_en_a_r)
        mem[address_a_r[AWIDTH-1:SEL_BITS]] <= wr_data_a_r;

  always @ (posedge clock)
    if (en_a_r)
      if (!wr_en_a_r)
        q_a_r <= mem[address_a_r[AWIDTH-1:SEL_BITS]];

  always @ (posedge clock)
    if (en_b_r)
      if (wr_en_b_r)
        mem[address_b_r[AWIDTH-1:SEL_BITS]] <= wr_data_b_r;

  always @ (posedge clock)
    if (en_b_r)
      if (!wr_en_b_r)
        q_b_r <= mem[address_b_r[AWIDTH-1:SEL_BITS]];

  generate
    if (DWIDTH==LWIDTH) begin
      assign q_a = q_a_r;
      assign q_b = q_b_r;
    end else begin
      reg [SEL_BITS-1:0] sel_a;
      reg [SEL_BITS-1:0] sel_b;

      always @ (posedge clock) begin
        sel_a <= address_a_r[SEL_BITS-1:0];
        sel_b <= address_b_r[SEL_BITS-1:0];
      end

      assign q_a = q_a_r[sel_a*DWIDTH +: DWIDTH];
      assign q_b = q_b_r[sel_b*DWIDTH +: DWIDTH];
    end
  endgenerate

endmodule
module rom_2port_noreg #(
	parameter DWIDTH    = 8,
	parameter AWIDTH    = 8,
	parameter MEM_SIZE  = (2**AWIDTH),
	parameter INIT_FILE = ""
) (

  input  wire              clock,
  input  wire [AWIDTH-1:0] address_a,
  input  wire [AWIDTH-1:0] address_b,

  output reg  [DWIDTH-1:0] q_a,
  output reg  [DWIDTH-1:0] q_b
);

  reg [DWIDTH-1:0] mem [0:(1<<AWIDTH)-1];

  always @ (posedge clock) begin
    q_a <= mem[address_a];
    q_b <= mem[address_b];
  end

  initial begin
    if (INIT_FILE!="")
      $readmemh(INIT_FILE, mem);
  end

endmodule
module rom_1port_mlab #(
	parameter DWIDTH    = 8,
	parameter AWIDTH    = 8,
	parameter MEM_SIZE  = (2**AWIDTH),
	parameter INIT_FILE = ""
) (
  input  wire              clock,
  input  wire [AWIDTH-1:0] address,
  output reg  [DWIDTH-1:0] q
);

  reg [DWIDTH-1:0] mem [0:(1<<AWIDTH)-1];
  reg [AWIDTH-1:0] address_r;

  always @ (posedge clock) begin
    address_r <= address;
    q <= mem[address_r];
  end

  initial begin
    if (INIT_FILE!="")
      $readmemh(INIT_FILE, mem);
  end

endmodule
module singledsp (
  input  wire        clk0,
  input  wire        clk1,
  input  wire        clk2,
  input  wire [2:0]  ena,

  input  wire [17:0] ax,
  input  wire [17:0] ay,

  output reg  [36:0] resulta
);

  reg [17:0] ax_r;
  reg [17:0] ay_r;
  reg [17:0] ax_rr;
  reg [17:0] ay_rr;
  reg [35:0] mul;

  always @ (posedge clk0)
    if (ena[0]) begin
      ax_r <= ax;
      ay_r <= ay;

      ax_rr <= ax_r;
      ay_rr <= ay_r;

      mul  <= ax_rr*ay_rr;

      resulta <= {1'b0, mul};
    end

endmodule
module dsp (
  input  wire        clk0,
  input  wire        clk1,
  input  wire        clk2,
  input  wire [2:0]  ena,

  input  wire [17:0] ax,
  input  wire [17:0] ay,

  input  wire [17:0] bx,
  input  wire [17:0] by,

  output reg  [36:0] resulta
);

  reg [17:0] ax_r;
  reg [17:0] ay_r;
  reg [17:0] bx_r;
  reg [17:0] by_r;

  reg [35:0] mul_a;
  reg [35:0] mul_b;

  reg [36:0] sum;

  always @ (posedge clk0)
    if (ena[0]) begin
      ax_r <= ax;
      ay_r <= ay;
      bx_r <= bx;
      by_r <= by;

      mul_a <= ax_r*ay_r;
      mul_b <= bx_r*by_r;

      sum <= mul_a + mul_b;

      resulta <= sum;
    end

endmodule
module top(output logic a);
   initial begin
      a  = 1; 
      a ^= 0;
   end
endmodule
module top;
   initial begin
      $display("Bin number 10 should be printed: %b", 2'd2);
   end
endmodule
module top(input [3:0] a, output [3:0] b);
    assign b = !a;
endmodule
module top;
   initial begin
      $display("Hex number ab should be printed: %h", 8'hAB);
   end
endmodule
module top(input [3:0] a, output [3:0] b);
    assign b = +a;
endmodule
module top(input [3:0] a, output [3:0] b);
    assign b = -a;
endmodule
module top(output logic a, b, c, d, e, f, g, h, i, j, k, l);
   initial begin
      a  = 1;
      a -= 1;
      b  = 4;
      b /= 2;
      c  = 5;
      c %= 2;
      d  = 1;
      d <<= 1;
      e  = 8;
      e >>= 1;
      f  = 1;
      f += 1;
      g  = 2;
      g *= 3;
      h  = 3;
      h &= 1;
      i  = 6;
      i |= 4;
      j  = 1;
      j ^= 0;
      k  = 5;
      k <<<= 1;
      l  = 5;
      l >>>= 1;
   end
endmodule
module top ();
	wire a = 0;
	wire b = 0;
	wire c = 0;
	wire d = 0;
	reg out;
	always @(*)
		out = (a | b) & (c | d);
endmodule
module top ();
	wire a = 1;
	reg b = 0;
	always @* begin
		if(a) b = 1;
		else b = 0;
	end
endmodule
module top
(
    input [0:3] in, // verilog_lint: waive packed-dimensions-range-ordering
    output out_1, out_2, out_3, out_4, out_5, out_6, out_7, out_8, out_9, out_10,
           out_11, out_12, out_13, out_14, out_15, out_16, out_17, out_18
);
    assign out_1 =  in[0] & in[1];
    assign out_2 =  in[0] | in[1];
    assign out_3 =  in[0] ~& in[1];
    assign out_4 =  in[0] ~| in[1];
    assign out_5 =  in[0] ^ in[1];
    assign out_6 =  in[0] ~^ in[1];
    assign out_7 =  in[0] ^~ in[1];
    assign out_8 =  ~in[0];
    assign out_9 =  in[0];
    assign out_10 =  &in[0];
    assign out_11 =  |in[0];
    assign out_12 =  ~&in[0];
    assign out_13 =  ~|in[0];
    assign out_14 =  ^in[0];
    assign out_15 =  ~^in[0];
    assign out_16 =  ^~in[0];
    assign out_17 =  in[0:1] && in [2:3];
    assign out_18 =  in[0:1] || in [2:3];

endmodule
module top (i, index_o);
  input [31:0] i;
  output [1:2] index_o; // verilog_lint: waive packed-dimensions-range-ordering
  wire [1:2] index_o; // verilog_lint: waive packed-dimensions-range-ordering
  assign index_o[1] = i[1];
  assign index_o[2] = i[0];
endmodule
module prim_secded_top (
  input logic [21:0] in_22,
  output logic [21:0] d_o_28,
  output logic [5:0] syndrome_o_28,
  output logic [1:0] err_o_28,

  input logic [31:0] in_32,
  output logic [31:0] d_o_32,
  output logic [6:0] syndrome_o_32,
  output logic [1:0] err_o_32,

  input logic [63:0] in_64,
  output logic [63:0] d_o_72,
  output logic [7:0] syndrome_o_64,
  output logic [1:0] err_o_64
);

  logic [27:0] enc_28;
  prim_secded_28_22_enc enc1 (
    .in  ( in_22 ),
    .out ( enc_28)
  );
  prim_secded_28_22_dec dec1 (
    .in ( enc_28),
    .d_o ( d_o_28),
    .syndrome_o ( syndrome_o_28),
    .err_o ( err_o_28)
  );

  logic [38:0] enc_39;
  prim_secded_39_32_enc enc2 (
    .in ( in_32),
    .out ( enc_39)
  );
  prim_secded_39_32_dec dec2 (
    .in ( enc_39),
    .d_o ( d_o_32),
    .syndrome_o ( syndrome_o_32),
    .err_o ( err_o_32)
  );

  logic [71:0] enc_72;
  prim_secded_72_64_enc enc3 (
    .in ( in_64),
    .out ( enc_72)
  );
  prim_secded_72_64_dec dec3 (
    .in ( enc_72),
    .d_o ( d_o_72),
    .syndrome_o ( syndrome_o_64),
    .err_o ( err_o_64)
  );
endmodule
module tft_ili9341_spi(
		input spiClk, input[8:0] data, input dataAvailable,
		output wire tft_sck, output reg tft_sdi, output reg tft_dc, output wire tft_cs,
		output reg idle
	);

	// Registers
	reg[0:2] counter = 3'b0;
	reg[8:0] internalData;
	reg internalSck;
	reg cs;
	
	initial internalSck <= 1'b1;
	initial idle <= 1'b1;
	initial cs <= 1'b0;
	
	// Combinational Assignments
	wire dataDc = internalData[8];
	wire[0:7] dataShift = internalData[7:0]; // MSB first
	
	assign tft_sck = internalSck & cs; // only drive sck with an active CS
	assign tft_cs = !cs; // active low
	
	// Update SPI CLK + Output data
	always @ (posedge spiClk) begin
		// Store new data in internal register
		if (dataAvailable) begin
			internalData <= data;
			idle <= 1'b0;
		end
		
		// Change data if we're actively sending
		if (!idle) begin
			// Toggle Clock on every active tick
			internalSck <= !internalSck;
				
			// Check if SCK will be low next
			if (internalSck) begin
				// Update pins
				tft_dc <= dataDc;
				tft_sdi <= dataShift[counter];
				cs <= 1'b1;
				
				// Advance counter
				counter <= counter + 1'b1;
				idle <= &counter; // we're just sending the last bit
			end
		end
		else begin
			internalSck <= 1'b1; // idle mode (also: sent last bit)
			if (internalSck) cs <= 1'b0; // idle for two bits in a row -> deactivate CS
		end
	end	
endmodule
module hq2x_in #(parameter LENGTH, parameter DWIDTH)
(
    input            clk,

    input [AWIDTH:0] rdaddr,
    input            rdbuf0, rdbuf1,
    output[DWIDTH:0] q0,q1,

    input [AWIDTH:0] wraddr,
    input            wrbuf,
    input [DWIDTH:0] data,
    input            wren
);

    localparam AWIDTH = $clog2(LENGTH)-1;
    wire  [DWIDTH:0] out[2];
    assign q0 = out[rdbuf0];
    assign q1 = out[rdbuf1];

    hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
    hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
endmodule
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
(
    input                   clock,
    input        [DWIDTH:0] data /*verilator public*/,
    input        [AWIDTH:0] rdaddress /*verilator public*/,
    input        [AWIDTH:0] wraddress /*verilator public*/,
    input                   wren /*verilator public*/,
    output logic [DWIDTH:0] q /*verilator public*/
);

(* max_depth = 1024 *) (* ramstyle = "no_rw_check" *) logic [DWIDTH:0] ram[0:NUMWORDS-1];

always_ff@(posedge clock) begin
    if(wren) ram[wraddress] <= data;
    q <= ram[rdaddress];
end

endmodule
module DiffCheck
(
    input clock,
    input [23:0] rgb1,
    input [23:0] rgb2,
    output reg result
);

    reg [7:0] r, g, b, r_q, g_q, b_q;
    reg [8:0] t, gx, u, t_q, gx_q;
    reg [9:0] y, v;

    // if y is inside (-96..96)
    reg y_inside, u_inside, v_inside;

    always_ff @(posedge clock) begin
        // stage 1
        r <= rgb1[7:1]   - rgb2[7:1];
        g <= rgb1[15:9]  - rgb2[15:9];
        b <= rgb1[23:17] - rgb2[23:17];

        // stage 2
        t <= $signed(r) + $signed(b);
        gx <= { g[7], g };
        { r_q, g_q, b_q } <= { r, g, b };

        // stage 3
        y <= $signed(t) + $signed(gx);
        u <= $signed(r_q) - $signed(b_q);
        v <= $signed({g_q, 1'b0}) - $signed(t);

        // stage 4
        // if y is inside (-96..96)
        y_inside <= (y < 10'h60 || y >= 10'h3a0);
        // if u is inside (-16, 16)
        u_inside <= (u < 9'h10 || u >= 9'h1f0);
        // if v is inside (-24, 24)
        v_inside <= (v < 10'h18 || v >= 10'h3e8);

        // stage 5
        result <= !(y_inside && u_inside && v_inside);
    end
endmodule
module InnerBlend
(
    input clock,
    input  [8:0] Op,
    input  [7:0] A,
    input  [7:0] B,
    input  [7:0] C,
    output reg [7:0] O
);

    function  [10:0] mul8x3;
        input   [7:0] op1;
        input   [2:0] op2;
    begin
        mul8x3 = 11'd0;
        if(op2[0]) mul8x3 = mul8x3 + op1;
        if(op2[1]) mul8x3 = mul8x3 + {op1, 1'b0};
        if(op2[2]) mul8x3 = mul8x3 + {op1, 2'b00};
    end
    endfunction

    reg OpOnes;
    reg [10:0] Amul, Bmul, Cmul;
    reg [10:0] At, Bt, Ct;
    reg [11:0] Res;

    reg [8:0] Op_q, Op_q_q, Op_q_q_q, Op_q_q_q_q;
    reg [7:0] A_q, A_q_q, A_q_q_q, A_q_q_q_q, B_q, B_q_q, C_q, C_q_q;

    always_ff @(posedge clock) begin
        // stage 1
        { Op_q, A_q, B_q, C_q } <= { Op, A, B, C };

        // stage 2
        OpOnes <= Op_q[4];
        Amul <= mul8x3(A_q, Op_q[7:5]);
        Bmul <= mul8x3(B_q, {Op_q[3:2], 1'b0});
        Cmul <= mul8x3(C_q, {Op_q[1:0], 1'b0});
        { Op_q_q, A_q_q, B_q_q, C_q_q } <= { Op_q, A_q, B_q, C_q };

        // stage 3
        At <=  Amul;
        Bt <= (OpOnes == 0) ? Bmul : {3'b0, B_q_q};
        Ct <= (OpOnes == 0) ? Cmul : {3'b0, C_q_q};
        { Op_q_q_q, A_q_q_q } <= { Op_q_q, A_q_q };

        // stage 4
        Res <= {At, 1'b0} + Bt + Ct;
        { Op_q_q_q_q, A_q_q_q_q } <= { Op_q_q_q, A_q_q_q };

        // stage 5
        O <= Op_q_q_q_q[8] ? A_q_q_q_q : Res[11:4];
    end
endmodule
module testbench();
   supply0 vss;
   supply1 vdd;
   
   // Skeleton
   initial
     begin
	$dumpfile("waveform.vcd");
	$dumpvars(0, testbench);
	#(1000)
	$finish;	
     end
   
   // Stimulus
   reg a,b;
   initial
     begin
	#100 a = 0; b = 0 ;
	#100 a = 0; b = 1 ;
	#100 a = 1; b = 0 ;
	#100 a = 1; b = 1 ;
     end
   
   // DUT
   defparam dut.NMODEL = "nmos";
   defparam dut.PMODEL = "pmos";   
   defparam dut.W      = {0,1,2,3};
   defparam dut.L      = {0,1,2,3};
   defparam dut.M      = {0,1,2,3};
   defparam dut.NF     = {0,1,2,3};
   
   oh_nor2 dut (/*AUTOINST*/
		 // Outputs
		 .z			(z),
		 // Inputs
		 .vdd			(vdd),
		 .vss			(vss),
		 .a			(a),
		 .b			(b));
   
   
endmodule // top
module testbench();
   supply0 vss;
   supply1 vdd;
   
   // Skeleton
   initial
     begin
	$dumpfile("waveform.vcd");
	$dumpvars(0, testbench);
	#(1000)
	$finish;	
     end
   
   // Stimulus
   reg a,b;
   initial
     begin
	#100 a = 0; b = 0 ;
	#100 a = 0; b = 1 ;
	#100 a = 1; b = 0 ;
	#100 a = 1; b = 1 ;
     end
   
   // DUT
   oh_nand2 #(.SIM("switch"),
	      .NMODEL("nmos"),
	      .PMODEL("pmos"),
	      .W({0,1,2,3}),
	      .L({4,5,6,7}),
	      .M({8,9,10,11}),
	      .NF({12,13,14,15}))
   dut (/*AUTOINST*/
	// Outputs
	.z			(z),
	// Inputs
	.vdd			(vdd),
	.vss			(vss),
	.a			(a),
	.b			(b));

   
   
endmodule // top
module oh_pmos #(parameter MODEL = "pmos",
		 parameter W     = "0",
		 parameter L     = "0",
		 parameter M     = "0",
		 parameter NF    = "0"
		 )
   (
    input  bulk,
    input  g,
    input  s,
    inout  d
    );

   //out,in,ctrlr
   pmos p (d,s,g);
   
   // Debug information
`ifdef OH_DEBUG
   initial
     begin
	$display("inst=%m model=%s w=%0d l=%0d m=%0d nf=%0d",
		 MODEL,W,L,M,NF);	  
     end
`endif
      
endmodule
module oh_nmos #(parameter MODEL = "nmos",
		 parameter W     = "0",
		 parameter L     = "0",
		 parameter M     = "0",
		 parameter NF    = "0"
		 )
   (
    input  bulk,
    input  g,
    input  s,
    inout  d
    );
   
   // Primitive Device
   nmos n (d, s, g);
   
   // Debug information
`ifdef OH_DEBUG
   initial
     begin
	$display("inst=%m model=%s w=%0d l=%0d m=%0d nf=%0d",
		 MODEL,W,L,M,NF);	  
     end
`endif
   
endmodule
module SysPLL_inferred(
  // Clock in ports
  input     CLK_IN,
  // Clock out ports
  output    CLK_OUT1,
  output    CLK_OUT2,
  // Status and control signals
  input     RESET,
  output    LOCKED
 );

  assign CLK_OUT1 = CLK_IN;
  assign CLK_OUT2 = CLK_IN;
  assign LOCKED = ~RESET;

endmodule
module tb_sim();

    // -----------------------------
    //  simulation setting
    // -----------------------------

    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #20000
        $finish();
    end

    localparam RATE = 1000.0/300.0;
//  localparam RATE = 1000.0/250.0;

    reg     reset = 1'b1;
    always #(RATE*100)  reset = 1'b0;

    reg     clk = 1'b1;
    always #(RATE/2.0)  clk = ~clk;



    tb_main
        i_tb_main
            (
                .reset      (reset),
                .clk        (clk)
            );
    
    
endmodule
module tb_sim();

    // -----------------------------
    //  simulation setting
    // -----------------------------

    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #2000000;
        $finish();
    end

    localparam RATE = 1000.0/300.0;
//  localparam RATE = 1000.0/250.0;

    reg     reset = 1'b1;
    always #(RATE*100)  reset = 1'b0;

    reg     clk = 1'b1;
    always #(RATE/2.0)  clk = ~clk;



    tb_main
        i_tb_main
            (
                .reset      (reset),
                .clk        (clk)
            );
    
    
endmodule
module tb_sim();

    // -----------------------------
    //  simulation setting
    // -----------------------------

    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #2000000
        $finish();
    end

    localparam RATE = 1000.0/300.0;
//  localparam RATE = 1000.0/250.0;

    reg     reset = 1'b1;
    always #(RATE*100)  reset = 1'b0;

    reg     clk = 1'b1;
    always #(RATE/2.0)  clk = ~clk;



    tb_main
        i_tb_main
            (
                .reset      (reset),
                .clk        (clk)
            );
    
    
endmodule
module tb_sim();
    
    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #1000000
        $finish;
    end
    

    // ---------------------------------
    //  clock & reset
    // ---------------------------------

    localparam RATE = 1000.0/100.00;

    logic       reset = 1;
    initial #100 reset = 0;

    logic       clk = 1'b1;
    always #(RATE/2.0) clk <= ~clk;

    
    // ---------------------------------
    //  main
    // ---------------------------------

    tb_main
        i_tb_main
            (
                .reset,
                .clk
            );
    
    
endmodule
module tb_sim();
    
    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(1, tb_sim);
        
    #10000
        $finish;
    end
    
    // ---------------------------------
    //  clock & reset
    // ---------------------------------

    localparam CLK_RATE = 1000.0/100.00;

    reg         reset = 1;
    initial #100 reset = 0;

    reg         clk = 1'b1;
    always #(CLK_RATE/2.0) clk <= ~clk;


    // ---------------------------------
    //  main
    // ---------------------------------

    tb_main
        i_tb_main
            (
                .reset,
                .clk
            );
    
endmodule
module tb_top();
    
    initial begin
        $dumpfile("tb_top.vcd");
        $dumpvars(0, tb_top);
        
        #100000;
            $finish;
    end
    
    localparam RATE = 1000.0/200.0;

    logic   clk = 1'b1;
    always #(RATE/2.0)  clk = ~clk;
    
    logic   reset = 1'b1;
    initial #(RATE*100) reset = 1'b0;

    tb_main
        u_tb_main
            (
                .reset  ,
                .clk    
            );
    
endmodule
module tb_sim();
    localparam RATE = 10.0;
    
    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #(RATE*100);
    #(20000*100)
        $finish();
    end

    reg     reset = 1'b1;
    always #(RATE*100)  reset = 1'b0;

    reg     clk = 1'b1;
    always #(RATE/2.0)  clk = ~clk;
    

    // -----------------------------
    //  main
    // -----------------------------

    tb_main
            #(
                .DEVICE     ("ULTRASCALE")
            )
        i_main
            (
                .reset,
                .clk
            );
    
    
endmodule
module tb_sim();
    localparam RATE = 10.0;
    
    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #1000000
        $finish();
    end

    reg     reset = 1'b1;
    always #(RATE*100)  reset = 1'b0;

    reg     clk = 1'b1;
    always #(RATE/2.0)  clk = ~clk;
    

    // -----------------------------
    //  main
    // -----------------------------

    tb_main
        i_main
            (
                .reset,
                .clk
            );


    /*
    logic [1:0] a;
    logic [1:0] b;
    logic [1:0] c;

    logic [1:0] d0;
    logic [1:0] d1;
    logic       msb_carry;
    logic       carry;
    logic       overflow;
    logic       zero;
    logic       negative;

    logic       my_eq ;
    logic       my_ne ;
    logic       my_lt ;
    logic       my_ge ;
    logic       my_ltu;
    logic       my_geu;

    logic       exp_eq ;
    logic       exp_ne ;
    logic       exp_lt ;
    logic       exp_ge ;
    logic       exp_ltu;
    logic       exp_geu;

    initial begin
        for (int i = 0; i < 4; ++i ) begin
            for (int j = 0; j < 4; ++j ) begin
                a = i[1:0];
                b = j[1:0];

                d0 = a;
                d1 = ~b;
                {msb_carry, c[0:0]} = {1'b0, d0[0:0]} + {1'b0, d1[0:0]} + 1'b1;
                {carry, c[1]}       = {1'b0, d0[1]} + {1'b0, d1[1]} + msb_carry;

                overflow = (msb_carry != carry);
                zero     = (c == '0);
                negative = c[1];

                my_eq = zero;
                my_ne = !zero; 
                my_lt =  (overflow != negative);
                my_ge  = (overflow == negative);
                my_ltu = !carry;
                my_geu = carry;

                exp_eq  = (  $signed(a)   == $signed(b));
                exp_ne  = (  $signed(a)   != $signed(b));
                exp_lt  = (  $signed(a)    < $signed(b));
                exp_ge  = (  $signed(a)   >= $signed(b));
                exp_ltu = ($unsigned(a)  < $unsigned(b));
                exp_geu = ($unsigned(a) >= $unsigned(b));


                $display("%b-%b=%b  carry=%b overflow=%b zero=%b, negative=%b", i[1:0], j[1:0], c, carry, overflow, zero, negative);
                $display(" eq  = %b  %b", exp_eq , my_eq  );
                $display(" ne  = %b  %b", exp_ne , my_ne  );
                $display(" lt  = %b  %b", exp_lt , my_lt  );
                $display(" ge  = %b  %b", exp_ge , my_ge  );
                $display(" ltu = %b  %b", exp_ltu, my_ltu );
                $display(" geu = %b  %b", exp_geu, my_geu );
            end
        end
        $finish;
    end
    */
    
endmodule
module tb_sim();
    localparam RATE = 10.0;
    
    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #2000000
        $finish();
    end

    reg     reset = 1'b1;
    always #(RATE*100)  reset = 1'b0;

    reg     clk = 1'b1;
    always #(RATE/2.0)  clk = ~clk;
    

    // -----------------------------
    //  main
    // -----------------------------

    tb_sim_main
        i_sim_main
            (
                .reset,
                .clk
            );
    
    
endmodule
module tb_sim();
    localparam RATE = 10.0;
    
    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #200000
        $finish();
    end

    reg     reset = 1'b1;
    always #(RATE*100)  reset = 1'b0;

    reg     clk = 1'b1;
    always #(RATE/2.0)  clk = ~clk;
    

    // -----------------------------
    //  main
    // -----------------------------

    tb_main
        i_tb_main
            (
                .reset          (reset),
                .clk            (clk)
            );
    
endmodule
module tb_sim();
    localparam RATE = 10.0;
    
    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #200000
        $finish();
    end

    reg     reset = 1'b1;
    always #(RATE*100)  reset = 1'b0;

    reg     clk = 1'b1;
    always #(RATE/2.0)  clk = ~clk;
    

    // -----------------------------
    //  main
    // -----------------------------

    tb_sim_main
        i_sim_main
            (
                .reset          (reset),
                .clk            (clk)
            );
    
endmodule
module tb_sim();
    localparam RATE = 10.0;
    
    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #10000
        $finish();
    end

    reg     reset = 1'b1;
    always #(RATE*100)  reset = 1'b0;

    reg     clk = 1'b1;
    always #(RATE/2.0)  clk = ~clk;
    

    // -----------------------------
    //  main
    // -----------------------------

    tb_main
        i_tb_main
            (
                .reset          (reset),
                .clk            (clk)
            );
    
endmodule
module tb_sim();
    localparam RATE  = 1000.0 / 100.0;
    
    
    initial begin
        $dumpfile("tb_sim.vcd"); 
        $dumpvars(0, tb_sim);
//      $dumpvars(3, tb_sim);
        
        #1000000;
            $finish;
    end
    
    
    reg     reset = 1'b1;
    initial #(RATE*100)      reset = 1'b0;
    
    reg     clk = 1'b1;
    always #(RATE/2.0)       clk = ~clk;
    

    // -----------------------------------------
    //  main
    // -----------------------------------------

    tb_main
        i_tb_main
            (
                .reset,
                .clk
            );
    
    
endmodule
module tb_sim();
    localparam RATE    = 1000.0/250.0;
    
    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
       
        #10000000;
            $finish;
    end
    
    reg     clk = 1'b1;
    always #(RATE/2.0)  clk = ~clk;
    
    reg     reset = 1'b1;
    initial #(RATE*100.5)   reset = 1'b0;
    
    
    tb_main
        i_tb_main
            (
                .reset      (reset),
                .clk        (clk)
            );
    
    
endmodule
module tb_sim();

    // -----------------------------
    //  simulation setting
    // -----------------------------

    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #100000
        $finish();
    end

    localparam RATE = 1000.0/300.0;
//  localparam RATE = 1000.0/250.0;

    reg     reset = 1'b1;
    always #(RATE*100)  reset = 1'b0;

    reg     clk = 1'b1;
    always #(RATE/2.0)  clk = ~clk;



    tb_main
        i_tb_main
            (
                .reset      (reset),
                .clk        (clk)
            );
    
    
endmodule
module tb_sim();

    // -----------------------------
    //  simulation setting
    // -----------------------------

    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #300000
        $finish();
    end

    localparam RATE = 1000.0/300.0;
//  localparam RATE = 1000.0/250.0;

    reg     reset = 1'b1;
    always #(RATE*100)  reset = 1'b0;

    reg     clk = 1'b1;
    always #(RATE/2.0)  clk = ~clk;

    tb_main
        i_tb_main
            (
                .reset      (reset),
                .clk        (clk)
            );
    
    
endmodule
module tb_sim();
    localparam RATE = 10.0;
    
    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #2000000
        $finish();
    end

    logic   reset = 1'b1;
    always #(RATE*100)  reset = 1'b0;

    logic   clk = 1'b1;
    always #(RATE/2.0)  clk = ~clk;
    

    // -----------------------------
    //  main
    // -----------------------------

    tb_main
        i_sim_main
            (
                .*
            );
    
    
endmodule
module tb_sim();

    // -----------------------------
    //  simulation setting
    // -----------------------------

    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #2000000
        $finish();
    end

    localparam RATE    = 10.0;

    reg     reset = 1'b1;
    always #(RATE*100)  reset = 1'b0;

    reg     clk = 1'b1;
    always #(RATE/2.0)  clk = ~clk;



    tb_main
        i_tb_main
            (
                .aresetn        (~reset),
                .aclk           (clk)
            );
    
    
endmodule
module tb_sim();
    
    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #1000000
        $finish;
    end
    

    // ---------------------------------
    //  clock & reset
    // ---------------------------------

    localparam RATE27  =    27.0/100.00;
    localparam RATE126 =   126.0/200.00;
    localparam RATE25  = 5*126.0/250.00;

    reg         in_reset_n = 1'b0;
    initial #100 in_reset_n = 1'b1;

    reg         in_clk = 1'b1;
    always #(RATE27/2.0) in_clk <= ~in_clk;

    reg			clk = 1'b1;
    always #(RATE25/2.0) clk <= ~clk;

    reg			clk_x5 = 1'b1;
    always #(RATE126/2.0) clk_x5 <= ~clk_x5;


    
    // ---------------------------------
    //  main
    // ---------------------------------

    tb_main
        i_tb_main
            (
                .in_reset_n,
                .in_clk,
                .clk,
                .clk_x5
            );
    
    
endmodule
module tb_sim_main();

    wire    [1:0]   led;
    wire            imu_sck;
    wire            imu_sda;

    ultra96v2_mpu9250
        i_top
            (
                .led        (led),
                .imu_sck    (imu_sck),
                .imu_sda    (imu_sda)
            );
    
endmodule
module tb_sim_main();

    logic   [1:0]   led;
    
    ultra96v2_rtos
        i_top
            (
                .*
            );
    
endmodule
module tb_sim_main();

    wire    [1:0]   led;

    ultra96v2_hls_test
        i_top
            (
                .led        (led)
            );
    
endmodule
module HPS(
  output wire [1 - 1 : 0 ] h2f_rst_n
 ,output wire [1 - 1 : 0 ] h2f_user0_clk
);


cyclonev_hps_interface_clocks_resets clocks_resets(
 .f2h_pending_rst_ack({
    1'b1 // 0:0
  })
,.f2h_warm_rst_req_n({
    1'b1 // 0:0
  })
,.f2h_dbg_rst_req_n({
    1'b1 // 0:0
  })
,.h2f_rst_n({
    h2f_rst_n[0:0] // 0:0
  })
,.f2h_cold_rst_req_n({
    1'b1 // 0:0
  })
,.h2f_user0_clk({
    h2f_user0_clk[0:0] // 0:0
  })
);


cyclonev_hps_interface_dbg_apb debug_apb(
 .DBG_APB_DISABLE({
    1'b0 // 0:0
  })
,.P_CLK_EN({
    1'b0 // 0:0
  })
);


cyclonev_hps_interface_tpiu_trace tpiu(
 .traceclk_ctl({
    1'b1 // 0:0
  })
);


cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
 .boot_from_fpga_ready({
    1'b0 // 0:0
  })
,.boot_from_fpga_on_failure({
    1'b0 // 0:0
  })
,.bsel_en({
    1'b0 // 0:0
  })
,.csel_en({
    1'b0 // 0:0
  })
,.csel({
    2'b01 // 1:0
  })
,.bsel({
    3'b001 // 2:0
  })
);


cyclonev_hps_interface_fpga2hps fpga2hps(
 .port_size_config({
    2'b11 // 1:0
  })
);


cyclonev_hps_interface_hps2fpga hps2fpga(
 .port_size_config({
    2'b11 // 1:0
  })
);


cyclonev_hps_interface_fpga2sdram f2sdram(
 .cfg_cport_rfifo_map({
    18'b000000000000000000 // 17:0
  })
,.cfg_axi_mm_select({
    6'b000000 // 5:0
  })
,.cfg_wfifo_cport_map({
    16'b0000000000000000 // 15:0
  })
,.cfg_cport_type({
    12'b000000000000 // 11:0
  })
,.cfg_rfifo_cport_map({
    16'b0000000000000000 // 15:0
  })
,.cfg_port_width({
    12'b000000000000 // 11:0
  })
,.cfg_cport_wfifo_map({
    18'b000000000000000000 // 17:0
  })
);

endmodule
module lms_ctr_mm_interconnect_0_router_007_default_decode
  #(
     parameter DEFAULT_CHANNEL = 0,
               DEFAULT_WR_CHANNEL = -1,
               DEFAULT_RD_CHANNEL = -1,
               DEFAULT_DESTID = 0 
   )
  (output [89 - 86 : 0] default_destination_id,
   output [15-1 : 0] default_wr_channel,
   output [15-1 : 0] default_rd_channel,
   output [15-1 : 0] default_src_channel
  );

  assign default_destination_id = 
    DEFAULT_DESTID[89 - 86 : 0];

  generate
    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
      assign default_src_channel = '0;
    end
    else begin : default_channel_assignment
      assign default_src_channel = 15'b1 << DEFAULT_CHANNEL;
    end
  endgenerate

  generate
    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
      assign default_wr_channel = '0;
      assign default_rd_channel = '0;
    end
    else begin : default_rw_channel_assignment
      assign default_wr_channel = 15'b1 << DEFAULT_WR_CHANNEL;
      assign default_rd_channel = 15'b1 << DEFAULT_RD_CHANNEL;
    end
  endgenerate

endmodule
module lms_ctr_mm_interconnect_0_cmd_mux
(
    // ----------------------
    // Sinks
    // ----------------------
    input                       sink0_valid,
    input [103-1   : 0]  sink0_data,
    input [15-1: 0]  sink0_channel,
    input                       sink0_startofpacket,
    input                       sink0_endofpacket,
    output                      sink0_ready,


    // ----------------------
    // Source
    // ----------------------
    output                      src_valid,
    output [103-1    : 0] src_data,
    output [15-1 : 0] src_channel,
    output                      src_startofpacket,
    output                      src_endofpacket,
    input                       src_ready,

    // ----------------------
    // Clock & Reset
    // ----------------------
    input clk,
    input reset
);
    localparam PAYLOAD_W        = 103 + 15 + 2;
    localparam NUM_INPUTS       = 1;
    localparam SHARE_COUNTER_W  = 1;
    localparam PIPELINE_ARB     = 1;
    localparam ST_DATA_W        = 103;
    localparam ST_CHANNEL_W     = 15;
    localparam PKT_TRANS_LOCK   = 62;

    assign	src_valid			=  sink0_valid;
    assign	src_data			=  sink0_data;
    assign	src_channel			=  sink0_channel;
    assign	src_startofpacket  	        =  sink0_startofpacket;
    assign	src_endofpacket		        =  sink0_endofpacket;
    assign	sink0_ready			=  src_ready;
endmodule
module lms_ctr_mm_interconnect_0_router_001_default_decode
  #(
     parameter DEFAULT_CHANNEL = 0,
               DEFAULT_WR_CHANNEL = -1,
               DEFAULT_RD_CHANNEL = -1,
               DEFAULT_DESTID = 10 
   )
  (output [89 - 86 : 0] default_destination_id,
   output [15-1 : 0] default_wr_channel,
   output [15-1 : 0] default_rd_channel,
   output [15-1 : 0] default_src_channel
  );

  assign default_destination_id = 
    DEFAULT_DESTID[89 - 86 : 0];

  generate
    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
      assign default_src_channel = '0;
    end
    else begin : default_channel_assignment
      assign default_src_channel = 15'b1 << DEFAULT_CHANNEL;
    end
  endgenerate

  generate
    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
      assign default_wr_channel = '0;
      assign default_rd_channel = '0;
    end
    else begin : default_rw_channel_assignment
      assign default_wr_channel = 15'b1 << DEFAULT_WR_CHANNEL;
      assign default_rd_channel = 15'b1 << DEFAULT_RD_CHANNEL;
    end
  endgenerate

endmodule
module lms_ctr_mm_interconnect_0_router_002_default_decode
  #(
     parameter DEFAULT_CHANNEL = 0,
               DEFAULT_WR_CHANNEL = -1,
               DEFAULT_RD_CHANNEL = -1,
               DEFAULT_DESTID = 0 
   )
  (output [89 - 86 : 0] default_destination_id,
   output [15-1 : 0] default_wr_channel,
   output [15-1 : 0] default_rd_channel,
   output [15-1 : 0] default_src_channel
  );

  assign default_destination_id = 
    DEFAULT_DESTID[89 - 86 : 0];

  generate
    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
      assign default_src_channel = '0;
    end
    else begin : default_channel_assignment
      assign default_src_channel = 15'b1 << DEFAULT_CHANNEL;
    end
  endgenerate

  generate
    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
      assign default_wr_channel = '0;
      assign default_rd_channel = '0;
    end
    else begin : default_rw_channel_assignment
      assign default_wr_channel = 15'b1 << DEFAULT_WR_CHANNEL;
      assign default_rd_channel = 15'b1 << DEFAULT_RD_CHANNEL;
    end
  endgenerate

endmodule
module lms_ctr_mm_interconnect_0_router_default_decode
  #(
     parameter DEFAULT_CHANNEL = 5,
               DEFAULT_WR_CHANNEL = -1,
               DEFAULT_RD_CHANNEL = -1,
               DEFAULT_DESTID = 10 
   )
  (output [89 - 86 : 0] default_destination_id,
   output [15-1 : 0] default_wr_channel,
   output [15-1 : 0] default_rd_channel,
   output [15-1 : 0] default_src_channel
  );

  assign default_destination_id = 
    DEFAULT_DESTID[89 - 86 : 0];

  generate
    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
      assign default_src_channel = '0;
    end
    else begin : default_channel_assignment
      assign default_src_channel = 15'b1 << DEFAULT_CHANNEL;
    end
  endgenerate

  generate
    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
      assign default_wr_channel = '0;
      assign default_rd_channel = '0;
    end
    else begin : default_rw_channel_assignment
      assign default_wr_channel = 15'b1 << DEFAULT_WR_CHANNEL;
      assign default_rd_channel = 15'b1 << DEFAULT_RD_CHANNEL;
    end
  endgenerate

endmodule
module lms_ctr_mm_interconnect_0_rsp_demux
(
    // -------------------
    // Sink
    // -------------------
    input  [1-1      : 0]   sink_valid,
    input  [103-1    : 0]   sink_data, // ST_DATA_W=103
    input  [15-1 : 0]   sink_channel, // ST_CHANNEL_W=15
    input                         sink_startofpacket,
    input                         sink_endofpacket,
    output                        sink_ready,

    // -------------------
    // Sources 
    // -------------------
    output reg                      src0_valid,
    output reg [103-1    : 0] src0_data, // ST_DATA_W=103
    output reg [15-1 : 0] src0_channel, // ST_CHANNEL_W=15
    output reg                      src0_startofpacket,
    output reg                      src0_endofpacket,
    input                           src0_ready,


    // -------------------
    // Clock & Reset
    // -------------------
    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
    input clk,
    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
    input reset

);

    localparam NUM_OUTPUTS = 1;
    wire [NUM_OUTPUTS - 1 : 0] ready_vector;

    // -------------------
    // Demux
    // -------------------
    always @* begin
        src0_data          = sink_data;
        src0_startofpacket = sink_startofpacket;
        src0_endofpacket   = sink_endofpacket;
        src0_channel       = sink_channel >> NUM_OUTPUTS;

        src0_valid         = sink_channel[0] && sink_valid;

    end

    // -------------------
    // Backpressure
    // -------------------
    assign ready_vector[0] = src0_ready;

    assign sink_ready = |(sink_channel & {{14{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});

endmodule