dakies/OSS_Verilog huggingface dataset:
module user_module_341262321634509394(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7 = io_in[6];
  wire net8 = io_in[7];
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13;
  wire net14;
  wire net15;
  wire net16;
  wire net17 = 1'b0;
  wire net18 = 1'b1;
  wire net19 = 1'b1;
  wire net20;
  wire net21;
  wire net22;
  wire net23;
  wire net24;
  wire net25;
  wire net26;
  wire net27;
  wire net28;
  wire net29;
  wire net30;
  wire net31;
  wire net32;
  wire net33;
  wire net34;
  wire net35;
  wire net36;
  wire net37;
  wire net38 = 1'b1;
  wire net39 = 1'b0;
  wire net40;
  wire net41 = 1'b0;

  assign io_out[0] = net9;
  assign io_out[1] = net10;
  assign io_out[2] = net11;
  assign io_out[3] = net12;
  assign io_out[4] = net13;
  assign io_out[5] = net14;
  assign io_out[6] = net15;
  assign io_out[7] = net16;

  and_cell gate1 (
    .a (net20),
    .b (net7),
    .out (net14)
  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  dff_cell flipflop2 (
    .d (net21),
    .clk (net22),
    .q (net23),
    .notq (net21)
  );
  dff_cell flipflop3 (
    .d (net24),
    .clk (net1),
    .q (net22),
    .notq (net24)
  );
  and_cell gate7 (
    .a (net25),
    .b (net3),
    .out (net10)
  );
  and_cell gate8 (
    .a (net26),
    .b (net4),
    .out (net11)
  );
  and_cell gate9 (
    .a (net27),
    .b (net5),
    .out (net12)
  );
  and_cell gate10 (
    .a (net28),
    .b (net6),
    .out (net13)
  );
  and_cell gate11 (
    .a (net29),
    .b (net2),
    .out (net9)
  );
  and_cell gate12 (
    .a (net30),
    .b (net8),
    .out (net15)
  );
  dff_cell flipflop4 (
    .d (net31),
    .clk (net23),
    .q (net32),
    .notq (net31)
  );
  dff_cell flipflop5 (
    .d (net33),
    .clk (net32),
    .q (net16),
    .notq (net33)
  );
  dff_cell flipflop6 (
    .d (net34),
    .clk (net32),
    .q (net29)
  );
  dff_cell flipflop7 (
    .d (net29),
    .clk (net32),
    .q (net25)
  );
  dff_cell flipflop8 (
    .d (net25),
    .clk (net32),
    .q (net35)
  );
  dff_cell flipflop9 (
    .d (net35),
    .clk (net32),
    .q (net28)
  );
  dff_cell flipflop10 (
    .d (net28),
    .clk (net32),
    .q (net27)
  );
  dff_cell flipflop11 (
    .d (net27),
    .clk (net32),
    .q (net26)
  );
  dff_cell flipflop12 (
    .d (net26),
    .clk (net32),
    .q (net36)
  );
  dff_cell flipflop13 (
    .d (net36),
    .clk (net32),
    .q (net20)
  );
  or_cell gate14 (
    .a (net35),
    .b (net36),
    .out (net30)
  );
  or_cell gate13 (
    .a (net37),
    .b (net20),
    .out (net34)
  );
  dff_cell flipflop15 (
    .d (net38),
    .clk (net32),
    .q (net40)
  );
  dff_cell flipflop14 (
    .d (net40),
    .clk (net32),
    .notq (net37)
  );
endmodule
module user_module_341163800289870419(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3;
  wire net4;
  wire net5;
  wire net6;
  wire net7;
  wire net8;
  wire net9;
  wire net10;
  wire net11 = 1'b0;
  wire net12 = 1'b1;
  wire net13 = 1'b1;
  wire net14;
  wire net15;
  wire net16;
  wire net17;
  wire net18;

  assign io_out[0] = net3;
  assign io_out[1] = net4;
  assign io_out[2] = net5;
  assign io_out[3] = net6;
  assign io_out[4] = net7;
  assign io_out[5] = net8;
  assign io_out[6] = net9;
  assign io_out[7] = net10;

  and_cell gate8 (
    .a (net14),
    .b (net15),
    .out (net9)
  );
  dff_cell flipflop2 (
    .d (net2),
    .clk (net1),
    .q (net14),
    .notq (net16)
  );
  dff_cell flipflop3 (
    .d (net14),
    .clk (net1),
    .q (net17),
    .notq (net15)
  );
  and_cell gate7 (
    .a (net16),
    .b (net17),
    .out (net10)
  );
  dff_cell flipflop1 (
    .d (net18),
    .clk (net1),
    .q (net3)
  );
  dff_cell flipflop4 (
    .d (net3),
    .clk (net1),
    .q (net4)
  );
  dff_cell flipflop5 (
    .d (net4),
    .clk (net1),
    .q (net5)
  );
  dff_cell flipflop6 (
    .d (net5),
    .clk (net1),
    .q (net6)
  );
  dff_cell flipflop7 (
    .d (net6),
    .clk (net1),
    .q (net7)
  );
  dff_cell flipflop8 (
    .d (net7),
    .clk (net1),
    .q (net8),
    .notq (net18)
  );
endmodule
module user_module_341154161238213203(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7 = io_in[6];
  wire net8 = io_in[7];
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13;
  wire net14 = 1'b1;
  wire net15;
  wire net16;
  wire net17;
  wire net18;
  wire net19;
  wire net20;
  wire net21;
  wire net22;
  wire net23;
  wire net24 = 1'b0;
  wire net25;
  wire net26;
  wire net27;

  assign io_out[0] = net9;
  assign io_out[1] = net10;
  assign io_out[2] = net11;
  assign io_out[3] = net12;
  assign io_out[4] = net13;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  xor_cell gate8 (
    .a (net1),
    .b (net5),
    .out (net9)
  );
  and_cell gate10 (
    .a (net1),
    .b (net5),
    .out (net15)
  );
  and_cell gate11 (
    .a (net15),
    .b (net16),
    .out (net17)
  );
  or_cell gate12 (
    .a (net17),
    .b (net18),
    .out (net19)
  );
  xor_cell gate13 (
    .a (net2),
    .b (net6),
    .out (net16)
  );
  xor_cell gate14 (
    .a (net15),
    .b (net16),
    .out (net10)
  );
  and_cell gate15 (
    .a (net2),
    .b (net6),
    .out (net18)
  );
  and_cell gate16 (
    .a (net19),
    .b (net20),
    .out (net21)
  );
  or_cell gate17 (
    .a (net21),
    .b (net22),
    .out (net23)
  );
  xor_cell gate18 (
    .a (net3),
    .b (net7),
    .out (net20)
  );
  xor_cell gate19 (
    .a (net19),
    .b (net20),
    .out (net11)
  );
  and_cell gate20 (
    .a (net3),
    .b (net7),
    .out (net22)
  );
  and_cell gate4 (
    .a (net23),
    .b (net25),
    .out (net26)
  );
  or_cell gate7 (
    .a (net26),
    .b (net27),
    .out (net13)
  );
  xor_cell gate9 (
    .a (net4),
    .b (net8),
    .out (net25)
  );
  xor_cell gate21 (
    .a (net23),
    .b (net25),
    .out (net12)
  );
  and_cell gate22 (
    .a (net4),
    .b (net8),
    .out (net27)
  );
endmodule
module user_module_341631644820570706(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2;
  wire net3;
  wire net4;
  wire net5 = 1'b1;
  wire net6 = 1'b0;
  wire net7 = 1'b1;
  wire net8 = 1'b1;
  wire net9;
  wire net10;
  wire net11;

  assign io_out[0] = net2;
  assign io_out[1] = net3;
  assign io_out[2] = net3;
  assign io_out[3] = net4;
  assign io_out[4] = net5;
  assign io_out[5] = net5;
  assign io_out[6] = net2;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  dff_cell flipflop2 (
    .d (net9),
    .clk (net1),
    .q (net2),
    .notq (net10)
  );
  dff_cell flipflop3 (
    .d (net2),
    .clk (net1),
    .q (net11),
    .notq (net9)
  );
  xor_cell gate7 (
    .a (net11),
    .b (net10),
    .out (net4)
  );
  or_cell gate8 (
    .a (net2),
    .b (net11),
    .out (net3)
  );
endmodule
module user_module_341431339142087251(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7 = io_in[6];
  wire net8 = io_in[7];
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13;
  wire net14;
  wire net15 = 1'b1;
  wire net16 = 1'b1;
  wire net17;
  wire net18;
  wire net19;
  wire net20;
  wire net21;
  wire net22;
  wire net23;
  wire net24;
  wire net25;
  wire net26;
  wire net27;
  wire net28;
  wire net29;
  wire net30;
  wire net31;
  wire net32;
  wire net33;
  wire net34;
  wire net35 = 1'b0;

  assign io_out[0] = net9;
  assign io_out[1] = net10;
  assign io_out[2] = net11;
  assign io_out[3] = net12;
  assign io_out[4] = net13;
  assign io_out[5] = net14;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (
    .in (net3),
    .out (net17)
  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  dff_cell flipflop2 (
    .d (net18),
    .clk (net19),
    .q (net20),
    .notq (net21)
  );
  buffer_cell gate7 (
    .in (net2),
    .out (net18)
  );
  buffer_cell gate8 (
    .in (net1),
    .out (net19)
  );
  not_cell gate9 (
    .in (net4),
    .out (net22)
  );
  not_cell gate10 (
    .in (net5),
    .out (net23)
  );
  and_cell gate11 (
    .a (net17),
    .b (net23),
    .out (net24)
  );
  not_cell gate12 (
    .in (net22),
    .out (net25)
  );
  not_cell gate13 (
    .in (net23),
    .out (net26)
  );
  and_cell gate14 (
    .a (net25),
    .b (net26),
    .out (net27)
  );
  or_cell gate15 (
    .a (net24),
    .b (net27),
    .out (net11)
  );
  not_cell gate16 (
    .in (net11),
    .out (net12)
  );
  not_cell gate17 (
    .in (net6),
    .out (net28)
  );
  not_cell gate18 (
    .in (net7),
    .out (net29)
  );
  not_cell gate19 (
    .in (net8),
    .out (net30)
  );
  and_cell gate20 (
    .a (net28),
    .b (net30),
    .out (net31)
  );
  not_cell gate21 (
    .in (net29),
    .out (net32)
  );
  not_cell gate22 (
    .in (net30),
    .out (net33)
  );
  and_cell gate23 (
    .a (net32),
    .b (net33),
    .out (net34)
  );
  or_cell gate24 (
    .a (net31),
    .b (net34),
    .out (net13)
  );
  not_cell gate25 (
    .in (net13),
    .out (net14)
  );
  buffer_cell gate26 (
    .in (net20),
    .out (net9)
  );
  buffer_cell gate27 (
    .in (net21),
    .out (net10)
  );
endmodule
module user_module_341224613878956628(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7 = io_in[6];
  wire net8 = io_in[7];
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13;
  wire net14 = 1'b0;
  wire net15 = 1'b1;
  wire net16 = 1'b1;
  wire net17;
  wire net18;
  wire net19;
  wire net20;
  wire net21;
  wire net22;
  wire net23;
  wire net24;
  wire net25;
  wire net26;
  wire net27;
  wire net28;

  assign io_out[0] = net9;
  assign io_out[1] = net10;
  assign io_out[2] = net11;
  assign io_out[3] = net12;
  assign io_out[4] = net13;

  and_cell gate1 (
    .a (net1),
    .b (net5),
    .out (net17)
  );
  or_cell gate2 (

  );
  xor_cell gate3 (
    .a (net2),
    .b (net6),
    .out (net18)
  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (
    .a (net19),
    .b (net20),
    .sel (net17),
    .out (net21)
  );
  dff_cell flipflop1 (

  );
  xor_cell gate7 (
    .a (net1),
    .b (net5),
    .out (net9)
  );
  xor_cell gate8 (
    .a (net17),
    .b (net18),
    .out (net10)
  );
  xor_cell gate9 (

  );
  and_cell gate10 (

  );
  mux_cell mux2 (

  );
  and_cell gate11 (
    .a (net2),
    .b (net6),
    .out (net19)
  );
  or_cell gate12 (

  );
  or_cell gate13 (
    .a (net2),
    .b (net6),
    .out (net20)
  );
  xor_cell gate14 (
    .a (net3),
    .b (net7),
    .out (net22)
  );
  mux_cell mux3 (
    .a (net23),
    .b (net24),
    .sel (net21),
    .out (net25)
  );
  xor_cell gate15 (
    .a (net21),
    .b (net22),
    .out (net11)
  );
  and_cell gate16 (
    .a (net3),
    .b (net7),
    .out (net23)
  );
  or_cell gate17 (

  );
  or_cell gate18 (
    .a (net3),
    .b (net7),
    .out (net24)
  );
  xor_cell gate19 (
    .a (net4),
    .b (net8),
    .out (net26)
  );
  mux_cell mux4 (
    .a (net27),
    .b (net28),
    .sel (net25),
    .out (net13)
  );
  xor_cell gate20 (
    .a (net25),
    .b (net26),
    .out (net12)
  );
  and_cell gate21 (
    .a (net4),
    .b (net8),
    .out (net27)
  );
  or_cell gate22 (
    .a (net4),
    .b (net8),
    .out (net28)
  );
endmodule
module user_module_339501025136214612(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7 = io_in[6];
  wire net8 = io_in[7];
  wire net9 = 1'b0;
  wire net10 = 1'b1;
  wire net11 = 1'b1;

  assign io_out[0] = net1;
  assign io_out[1] = net2;
  assign io_out[2] = net3;
  assign io_out[3] = net4;
  assign io_out[4] = net5;
  assign io_out[5] = net6;
  assign io_out[6] = net7;
  assign io_out[7] = net8;

endmodule
module user_module_341497964482527828(
  input wire [7:0] io_in,
  output wire [7:0] out
);
  wire [7:0] io_in__1;
  wire [6:0] add_121;
  wire [3:0] add_127;
  assign io_in__1 = io_in - ({1'h0, io_in[7:1]} & 8'h55);
  assign add_121 = (io_in__1[6:0] & 7'h33) + ({1'h0, io_in__1[7:2]} & 7'h33);
  assign add_127 = add_121[3:0] + {1'h0, add_121[6:4]};
  assign out = {4'h0, add_127};
endmodule
module user_module_341506274933867090(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4;
  wire net5;
  wire net6;
  wire net7;
  wire net8;
  wire net9;
  wire net10;
  wire net11;
  wire net12 = 1'b0;
  wire net13 = 1'b1;
  wire net14 = 1'b1;
  wire net15;
  wire net16;
  wire net17;
  wire net18;
  wire net19;
  wire net20;
  wire net21;
  wire net22;
  wire net23;

  assign io_out[0] = net4;
  assign io_out[1] = net5;
  assign io_out[2] = net6;
  assign io_out[3] = net7;
  assign io_out[4] = net8;
  assign io_out[5] = net9;
  assign io_out[6] = net10;
  assign io_out[7] = net11;

  and_cell gate1 (
    .a (net2),
    .b (net15),
    .out (net16)
  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (
    .in (net3),
    .out (net15)
  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (
    .d (net16),
    .clk (net1),
    .q (net4)
  );
  dff_cell flipflop2 (
    .d (net17),
    .clk (net1),
    .q (net7)
  );
  dff_cell flipflop3 (
    .d (net18),
    .clk (net1),
    .q (net6)
  );
  dff_cell flipflop10 (
    .d (net19),
    .clk (net1),
    .q (net5)
  );
  dff_cell flipflop4 (
    .d (net20),
    .clk (net1),
    .q (net8)
  );
  dff_cell flipflop5 (
    .d (net21),
    .clk (net1),
    .q (net9)
  );
  dff_cell flipflop6 (
    .d (net22),
    .clk (net1),
    .q (net10)
  );
  dff_cell flipflop7 (
    .d (net23),
    .clk (net1),
    .q (net11)
  );
  and_cell gate7 (
    .a (net4),
    .b (net15),
    .out (net19)
  );
  and_cell gate8 (
    .a (net5),
    .b (net15),
    .out (net18)
  );
  and_cell gate9 (
    .a (net6),
    .b (net15),
    .out (net17)
  );
  and_cell gate10 (
    .a (net7),
    .b (net15),
    .out (net20)
  );
  and_cell gate11 (
    .a (net8),
    .b (net15),
    .out (net21)
  );
  and_cell gate12 (
    .a (net9),
    .b (net15),
    .out (net22)
  );
  and_cell gate13 (
    .a (net10),
    .b (net15),
    .out (net23)
  );
endmodule
module user_module_341192621088047698(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4;
  wire net5 = 1'b0;
  wire net6 = 1'b1;
  wire net7 = 1'b1;
  wire net8;
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13;
  wire net14;
  wire net15;
  wire net16;

  assign io_out[0] = net4;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  not_cell gate9 (
    .in (net3),
    .out (net8)
  );
  not_cell gate10 (
    .in (net8),
    .out (net9)
  );
  not_cell gate7 (
    .in (net1),
    .out (net10)
  );
  not_cell gate8 (
    .in (net2),
    .out (net11)
  );
  not_cell gate11 (
    .in (net10),
    .out (net12)
  );
  not_cell gate12 (
    .in (net11),
    .out (net13)
  );
  and_cell gate13 (
    .a (net12),
    .b (net9),
    .out (net14)
  );
  and_cell gate14 (
    .a (net13),
    .b (net8),
    .out (net15)
  );
  or_cell gate15 (
    .a (net14),
    .b (net15),
    .out (net16)
  );
  not_cell gate16 (
    .in (net16),
    .out (net4)
  );
endmodule
module user_module_341569483755749970(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7 = io_in[6];
  wire net8 = io_in[7];
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13 = 1'b0;
  wire net14 = 1'b1;
  wire net15 = 1'b1;
  wire net16;
  wire net17;
  wire net18;
  wire net19;
  wire net20;
  wire net21;
  wire net22;
  wire net23;
  wire net24;
  wire net25;
  wire net26;
  wire net27;
  wire net28;
  wire net29;
  wire net30 = 1'b0;
  wire net31;
  wire net32;
  wire net33;
  wire net34;
  wire net35;
  wire net36;
  wire net37;
  wire net38;
  wire net39;
  wire net40;
  wire net41;
  wire net42;
  wire net43;

  assign io_out[0] = net9;
  assign io_out[3] = net10;
  assign io_out[6] = net11;
  assign io_out[7] = net12;

  xor_cell gate3 (
    .a (net16),
    .b (net17),
    .out (net18)
  );
  mux_cell mux1 (
    .a (net9),
    .b (net3),
    .sel (net2),
    .out (net19)
  );
  dff_cell flipflop1 (
    .d (net20),
    .clk (net1),
    .q (net9)
  );
  dff_cell flipflop2 (
    .d (net21),
    .clk (net1),
    .q (net11)
  );
  dff_cell flipflop3 (
    .d (net22),
    .clk (net1),
    .q (net10)
  );
  xor_cell gate9 (
    .a (net18),
    .b (net23),
    .out (net20)
  );
  or_cell gate10 (
    .a (net24),
    .b (net25),
    .out (net26)
  );
  and_cell gate11 (
    .a (net16),
    .b (net17),
    .out (net25)
  );
  and_cell gate8 (
    .a (net18),
    .b (net23),
    .out (net24)
  );
  dff_cell flipflop4 (
    .d (net27),
    .clk (net1),
    .q (net12)
  );
  mux_cell mux2 (
    .a (net11),
    .b (net4),
    .sel (net2),
    .out (net28)
  );
  mux_cell mux3 (
    .a (net10),
    .b (net5),
    .sel (net2),
    .out (net29)
  );
  buffer_cell gate22 (
    .in (net19),
    .out (net16)
  );
  buffer_cell gate23 (
    .in (net6),
    .out (net17)
  );
  buffer_cell gate24 (
    .in (net30),
    .out (net23)
  );
  xor_cell gate12 (
    .a (net31),
    .b (net32),
    .out (net33)
  );
  xor_cell gate13 (
    .a (net33),
    .b (net34),
    .out (net21)
  );
  or_cell gate14 (
    .a (net35),
    .b (net36),
    .out (net37)
  );
  and_cell gate15 (
    .a (net31),
    .b (net32),
    .out (net36)
  );
  and_cell gate16 (
    .a (net33),
    .b (net34),
    .out (net35)
  );
  buffer_cell gate17 (
    .in (net28),
    .out (net31)
  );
  buffer_cell gate18 (
    .in (net7),
    .out (net32)
  );
  buffer_cell gate19 (
    .in (net26),
    .out (net34)
  );
  xor_cell gate20 (
    .a (net38),
    .b (net39),
    .out (net40)
  );
  xor_cell gate21 (
    .a (net40),
    .b (net41),
    .out (net22)
  );
  or_cell gate25 (
    .a (net42),
    .b (net43),
    .out (net27)
  );
  and_cell gate26 (
    .a (net38),
    .b (net39),
    .out (net43)
  );
  and_cell gate27 (
    .a (net40),
    .b (net41),
    .out (net42)
  );
  buffer_cell gate28 (
    .in (net29),
    .out (net38)
  );
  buffer_cell gate29 (
    .in (net8),
    .out (net39)
  );
  buffer_cell gate30 (
    .in (net37),
    .out (net41)
  );
endmodule
module user_module_341520747710120530(
  input [7:0] io_in,
  output [7:0] io_out
);

  wire uart_tx;

  assign io_out[0] = uart_tx;

  hello_world_341520747710120530 hello_world(
    .clk(io_in[0]),
    .reset(io_in[1]),

    .uart_tx(uart_tx)
  );

endmodule
module hello_world_341520747710120530 (
    input clk,
    input reset,

    output reg uart_tx
  );

  parameter START_BIT = 1'b0;
  parameter STOP_BIT = 1'b1;
  parameter IDLE_BIT = 1'b1;

  reg        [3:0] bit_counter;
  reg        [3:0] byte_counter;

  reg       [3:0] next_bit_counter; //0 to 10
  reg       [3:0] next_byte_counter; //0 to MSG_LEN (one more than MSG_LEN-1, for one extra idle word length)

  parameter FRAME_LENGTH = 11; //bit lengths per word length

  parameter MSG_LEN = 13;
  wire [7:0] hello_world_ascii [0:MSG_LEN-1];
  assign hello_world_ascii[0]  = "M";
  assign hello_world_ascii[1]  = "M";
  assign hello_world_ascii[2]  = "0";
  assign hello_world_ascii[3]  = "H";
  assign hello_world_ascii[4]  = "A";
  assign hello_world_ascii[5]  = "I";
  assign hello_world_ascii[6]  = "!";
  assign hello_world_ascii[7]  = "\n";
  assign hello_world_ascii[8]  = "n";
  assign hello_world_ascii[9]  = "y";
  assign hello_world_ascii[10] = "a";
  assign hello_world_ascii[11] = "!";
  assign hello_world_ascii[12] = "\n";


  wire [0:FRAME_LENGTH-1] current_frame; //1 + 1 + 8 + 1
    assign current_frame = {
    IDLE_BIT,
    START_BIT,
    hello_world_ascii[byte_counter][0],
    hello_world_ascii[byte_counter][1],
    hello_world_ascii[byte_counter][2],
    hello_world_ascii[byte_counter][3],
    hello_world_ascii[byte_counter][4],
    hello_world_ascii[byte_counter][5],
    hello_world_ascii[byte_counter][6],
    hello_world_ascii[byte_counter][7],
    STOP_BIT
  };

  always @(posedge clk) begin
    if (reset) begin
      bit_counter  <= 0;
      byte_counter <= 0;
    end else begin
      bit_counter  <= next_bit_counter;
      byte_counter <= next_byte_counter;
    end
  end

  always @(*) begin
    next_bit_counter = bit_counter;
    next_byte_counter = byte_counter;

    if(bit_counter < FRAME_LENGTH-1) begin
      next_bit_counter = bit_counter + 1;
    end else begin
      next_bit_counter = 0;

      if(byte_counter < MSG_LEN) begin
        next_byte_counter = byte_counter + 1;
      end else begin
        next_byte_counter = 0;
      end
    end

    uart_tx = IDLE_BIT;
    if(byte_counter != MSG_LEN) begin
       uart_tx = current_frame[bit_counter];
    end //else leave a blank byte length at the
  end


endmodule
module user_module_341556236196512338(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7 = io_in[6];
  wire net8 = io_in[7];
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13;
  wire net14;
  wire net15;
  wire net16;
  wire net17 = 1'b0;
  wire net18 = 1'b1;
  wire net19 = 1'b1;

  assign io_out[0] = net9;
  assign io_out[1] = net10;
  assign io_out[2] = net11;
  assign io_out[3] = net12;
  assign io_out[4] = net13;
  assign io_out[5] = net14;
  assign io_out[6] = net15;
  assign io_out[7] = net16;

  not_cell not1 (
    .in (net1),
    .out (net9)
  );
  not_cell not2 (
    .in (net2),
    .out (net10)
  );
  not_cell not3 (
    .in (net3),
    .out (net11)
  );
  not_cell not4 (
    .in (net4),
    .out (net12)
  );
  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  not_cell gate7 (
    .in (net5),
    .out (net13)
  );
  not_cell gate8 (
    .in (net8),
    .out (net16)
  );
  not_cell gate9 (
    .in (net7),
    .out (net15)
  );
  not_cell gate10 (
    .in (net6),
    .out (net14)
  );
endmodule
module user_module_341440114308678227(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2;
  wire net3;
  wire net4;
  wire net5;
  wire net6;
  wire net7;
  wire net8;
  wire net9;
  wire net10 = 1'b0;
  wire net11 = 1'b1;
  wire net12 = 1'b1;
  wire net13;
  wire net14;
  wire net15;
  wire net16;
  wire net17;
  wire net18;
  wire net19;
  wire net20;
  wire net21;
  wire net22;
  wire net23;
  wire net24;
  wire net25;
  wire net26;

  assign io_out[0] = net2;
  assign io_out[1] = net3;
  assign io_out[2] = net4;
  assign io_out[3] = net5;
  assign io_out[4] = net6;
  assign io_out[5] = net7;
  assign io_out[6] = net8;
  assign io_out[7] = net9;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  dff_cell flipflop2 (
    .d (net13),
    .clk (net1),
    .q (net14),
    .notq (net13)
  );
  dff_cell flipflop3 (
    .d (net15),
    .clk (net13),
    .q (net16),
    .notq (net15)
  );
  dff_cell flipflop4 (
    .d (net17),
    .clk (net15),
    .q (net18),
    .notq (net17)
  );
  and_cell gate7 (
    .a (net13),
    .b (net15),
    .out (net19)
  );
  and_cell gate8 (
    .a (net19),
    .b (net17),
    .out (net2)
  );
  and_cell gate9 (
    .a (net14),
    .b (net15),
    .out (net20)
  );
  and_cell gate10 (
    .a (net20),
    .b (net17),
    .out (net3)
  );
  and_cell gate11 (
    .a (net13),
    .b (net16),
    .out (net21)
  );
  and_cell gate12 (
    .a (net21),
    .b (net17),
    .out (net4)
  );
  and_cell gate13 (
    .a (net14),
    .b (net16),
    .out (net22)
  );
  and_cell gate14 (
    .a (net22),
    .b (net17),
    .out (net5)
  );
  and_cell gate15 (
    .a (net13),
    .b (net15),
    .out (net23)
  );
  and_cell gate16 (
    .a (net23),
    .b (net18),
    .out (net6)
  );
  and_cell gate17 (
    .a (net14),
    .b (net15),
    .out (net24)
  );
  and_cell gate18 (
    .a (net24),
    .b (net18),
    .out (net7)
  );
  and_cell gate19 (
    .a (net13),
    .b (net16),
    .out (net25)
  );
  and_cell gate20 (
    .a (net25),
    .b (net18),
    .out (net8)
  );
  and_cell gate21 (
    .a (net14),
    .b (net16),
    .out (net26)
  );
  and_cell gate22 (
    .a (net26),
    .b (net18),
    .out (net9)
  );
endmodule
module user_module_341440781874102868(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4;
  wire net5;
  wire net6;
  wire net7;
  wire net8;
  wire net9;
  wire net10;
  wire net11;
  wire net12 = 1'b1;
  wire net13 = 1'b1;
  wire net14;
  wire net15;
  wire net16;
  wire net17;
  wire net18;
  wire net19;
  wire net20;
  wire net21;
  wire net22;
  wire net23;
  wire net24;
  wire net25 = 1'b0;

  assign io_out[0] = net4;
  assign io_out[1] = net5;
  assign io_out[2] = net6;
  assign io_out[3] = net7;
  assign io_out[4] = net8;
  assign io_out[5] = net9;
  assign io_out[6] = net10;
  assign io_out[7] = net11;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  not_cell gate5 (
    .in (net2),
    .out (net14)
  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  not_cell gate8 (
    .in (net3),
    .out (net15)
  );
  not_cell gate9 (
    .in (net1),
    .out (net16)
  );
  and_cell gate4 (
    .a (net17),
    .b (net15),
    .out (net4)
  );
  and_cell gate7 (
    .a (net18),
    .b (net3),
    .out (net5)
  );
  and_cell gate10 (
    .a (net19),
    .b (net15),
    .out (net6)
  );
  and_cell gate11 (
    .a (net20),
    .b (net3),
    .out (net7)
  );
  and_cell gate12 (
    .a (net21),
    .b (net15),
    .out (net8)
  );
  and_cell gate13 (
    .a (net22),
    .b (net3),
    .out (net9)
  );
  and_cell gate14 (
    .a (net23),
    .b (net15),
    .out (net10)
  );
  and_cell gate15 (
    .a (net16),
    .b (net14),
    .out (net17)
  );
  and_cell gate16 (
    .a (net16),
    .b (net14),
    .out (net18)
  );
  and_cell gate17 (
    .a (net16),
    .b (net2),
    .out (net19)
  );
  and_cell gate18 (
    .a (net16),
    .b (net2),
    .out (net20)
  );
  and_cell gate19 (
    .a (net1),
    .b (net14),
    .out (net21)
  );
  and_cell gate20 (
    .a (net1),
    .b (net14),
    .out (net22)
  );
  and_cell gate21 (
    .a (net1),
    .b (net2),
    .out (net23)
  );
  and_cell gate22 (
    .a (net1),
    .b (net2),
    .out (net24)
  );
  and_cell gate23 (
    .a (net24),
    .b (net3),
    .out (net11)
  );
endmodule
module user_module_340596276030603858(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2;
  wire net3 = 1'b1;
  wire net4 = 1'b1;
  wire net5 = 1'b0;
  wire net6 = 1'b0;
  wire net7 = 1'b0;
  wire net8 = 1'b0;
  wire net9 = 1'b0;
  wire net10 = 1'b0;
  wire net11 = 1'b0;
  wire net12 = 1'b0;
  wire net13 = 1'b0;
  wire net14 = 1'b0;
  wire net15 = 1'b0;
  wire net16 = 1'b0;
  wire net17 = 1'b0;
  wire net18 = 1'b0;
  wire net19 = 1'b0;
  wire net20 = 1'b0;
  wire net21 = 1'b0;
  wire net22 = 1'b0;
  wire net23 = 1'b0;
  wire net24 = 1'b0;
  wire net25 = 1'b0;
  wire net26 = 1'b0;
  wire net27 = 1'b0;
  wire net28 = 1'b0;
  wire net29 = 1'b0;
  wire net30 = 1'b0;
  wire net31 = 1'b0;
  wire net32 = 1'b0;
  wire net33 = 1'b0;
  wire net34 = 1'b0;
  wire net35 = 1'b0;
  wire net36 = 1'b0;
  wire net37 = 1'b0;
  wire net38 = 1'b0;
  wire net39 = 1'b0;
  wire net40 = 1'b0;
  wire net41 = 1'b0;
  wire net42 = 1'b0;
  wire net43 = 1'b0;
  wire net44 = 1'b0;
  wire net45 = 1'b0;
  wire net46 = 1'b0;
  wire net47 = 1'b0;
  wire net48 = 1'b0;
  wire net49 = 1'b0;
  wire net50 = 1'b0;
  wire net51 = 1'b0;
  wire net52 = 1'b0;

  assign io_out[0] = net2;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  buffer_cell gate7 (
    .in (net1),
    .out (net2)
  );
endmodule
module utm_core_341174563322724948(
    input clock,
    input reset,
    input mode,
    input [2:0] encoded_state_in,
    input [2:0] sym_in,
    input sym_in_valid,
    output [2:0] new_sym,
    output direction,
    output [2:0] encoded_next_state
);

reg [7:0] stored_state;
reg [2:0] symbuf;
reg symbuf_valid;

wire [7:0] state_in;
wire [7:0] state;
wire [7:0] next_state;
wire [2:0] sym;

always @(posedge clock) begin
    if (reset) begin
        stored_state <= 8'h01;
    end
    else if (sym_in_valid && symbuf_valid) begin
        stored_state <= next_state;
    end
    else begin
        stored_state <= stored_state;
    end
end

always @(posedge clock) begin
    if (reset) begin
        symbuf <= 3'b0;
    end
    else if (sym_in_valid) begin
        symbuf <= sym_in;
    end
    else begin
        symbuf <= symbuf;
    end
end

always @(posedge clock) begin
    if (reset) begin
        symbuf_valid <= 0;
    end
    else if (sym_in_valid) begin
        symbuf_valid <= 1;
    end
    else begin
        symbuf_valid <= symbuf_valid;
    end
end

decoder_3to8_341174563322724948 decode_state_in(
    .in(encoded_state_in),
    .out(state_in)
);

assign state = (mode == 0) ? state_in : stored_state;
assign sym = (mode == 0) ? sym_in : symbuf;

direction_341174563322724948 direction_block(
    .state(state),
    .s2(sym[2]),
    .s1(sym[1]),
    .s0(sym[0]),
    .direction(direction)
);

next_state_341174563322724948 next_state_block(
    .state_in(state),
    .s2(sym[2]),
    .s1(sym[1]),
    .s0(sym[0]),
    .state_out(next_state));

new_symbol_341174563322724948 new_sym_block(
    .state_in(state),
    .s2(sym[2]),
    .s1(sym[1]),
    .s0(sym[0]),
    .z2(new_sym[2]),
    .z1(new_sym[1]),
    .z0(new_sym[0])
);

encoder_8to3_341174563322724948 encode_state_out(
    .in(next_state),
    .out(encoded_next_state)
);

endmodule
module direction_341174563322724948(
    input [7:0] state,
    input s2,
    input s1,
    input s0,
    // 0 = left, 1 = right
    output direction
);

wire a,b,c,d,e,f,g,h;

assign a = state[0];
assign b = state[1];
assign c = state[2];
assign d = state[3];
assign e = state[4];
assign f = state[5];
assign g = state[6];
assign h = state[7];

assign direction = ((a | e | f) & s1)
                 | (((a & s0) | b | c | (e & s0) | f | g | h) & s2)
                 | ((d | (e & (~s1) & (~s0))) & (~s2))
                 | (g & (~s1));
endmodule
module next_state_341174563322724948(
    input [7:0] state_in,
    input s2,
    input s1,
    input s0,
    output [7:0] state_out
);

wire a,b,c,d,e,f,g,h;

assign a = state_in[0];
assign b = state_in[1];
assign c = state_in[2];
assign d = state_in[3];
assign e = state_in[4];
assign f = state_in[5];
assign g = state_in[6];
assign h = state_in[7];

wire sym_0;
assign sym_0 = (~s2) & (~s1) & (~s0);

// next H
assign state_out[7] = s2 & ((s0 & (b | c)) | h);

// next G
assign state_out[6] = (s2 & ( ((b | c) & (~s0)) | g)) | (f & s1);

// next F
assign state_out[5] = (e & (~s2) & s0) | (f & (~(s2 | s1))) | (s1 & (g | h));

// next E
assign state_out[4] = (a & s2 & (~s0)) | (d & (~s2) & s0) | (e & (s1 | (s2 & s0)));

// next D
assign state_out[3] = (b & s1) | (d & s2) | (e & (~s1) & (~s0));

// next C
assign state_out[2] = (a & (~s2) & s0) | (c & (~(s2 | s1))) | (d & sym_0);

// next B
assign state_out[1] = (a & sym_0) | (b & (~(s2 | s1))) | (c & s1) | (f & s2);

// next A
assign state_out[0] = (a & (s1 | (s2 & s0))) | (d & s1) | ((g | h) & (~(s2 | s1)));

endmodule
module new_symbol_341174563322724948(
    input [7:0] state_in,
    input s2,
    input s1,
    input s0,
    output z2,
    output z1,
    output z0
);

wire a,b,c,d,e,f,g,h;

assign a = state_in[0];
assign b = state_in[1];
assign c = state_in[2];
assign d = state_in[3];
assign e = state_in[4];
assign f = state_in[5];
assign g = state_in[6];
assign h = state_in[7];

assign z2 = ((~s2) & b) | (d & s0) | c | (e & (s0 | s1)) | (f & (~(s2 | s1)));
assign z1 = (a & (~s2)) | (d & (s2 | s1) & (~s0)) | (e & s2 & (~s0));
assign z0 = (s0 & ((a & s2) | (~a))) | (h & s1);

endmodule
module decoder_3to8_341174563322724948(
    input [2:0] in,
    output [7:0] out
);

assign out[0] = (~in[2]) & (~in[1]) & (~in[0]);
assign out[1] = (~in[2]) & (~in[1]) & ( in[0]);
assign out[2] = (~in[2]) & ( in[1]) & (~in[0]);
assign out[3] = (~in[2]) & ( in[1]) & ( in[0]);
assign out[4] = ( in[2]) & (~in[1]) & (~in[0]);
assign out[5] = ( in[2]) & (~in[1]) & ( in[0]);
assign out[6] = ( in[2]) & ( in[1]) & (~in[0]);
assign out[7] = ( in[2]) & ( in[1]) & ( in[0]);

endmodule
module encoder_8to3_341174563322724948(
    input [7:0] in,
    output [2:0] out
);

assign out[0] = in[1] | in[3] | in[5] | in[7];
assign out[1] = in[2] | in[3] | in[6] | in[7];
assign out[2] = in[4] | in[5] | in[6] | in[7];
endmodule
module user_module_341174563322724948(
  input [7:0] io_in,
  output [7:0] io_out
);

wire mode;
wire clock;
wire reset;

wire direction;

wire sym_valid;
wire [2:0] sym_in;
wire [2:0] new_sym;

// 1-hot state in & out
wire [7:0] state_in;
wire [7:0] state_out;

// 3-bit dense encoding of state in & out
wire [2:0] encoded_state_in;
wire [2:0] encoded_state_out;

assign mode = io_in[7];
assign clock = io_in[0];
assign reset = (mode == 0) ? 1'b1 : io_in[1];

assign encoded_state_in = (mode == 0) ? io_in[3:1] : 3'b0;
assign io_out[7:5] = encoded_state_out;

assign sym_valid = (mode == 0) ? 1'b0 : io_in[2];
assign sym_in = io_in[6:4];
assign io_out[4:2] = new_sym;

assign io_out[1] = direction;
assign io_out[0] = 1'b0;

utm_core_341174563322724948 core(
    .clock(clock),
    .reset(reset),
    .mode(mode),
    .encoded_state_in(encoded_state_in),
    .sym_in(sym_in),
    .sym_in_valid(sym_valid),
    .new_sym(new_sym),
    .direction(direction),
    .encoded_next_state(encoded_state_out)
);

endmodule
module user_module_341608574336631379(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7 = io_in[6];
  wire net8 = io_in[7];
  wire net9;
  wire net10;
  wire net11 = 1'b0;
  wire net12 = 1'b1;
  wire net13 = 1'b1;
  wire net14;
  wire net15;
  wire net16;
  wire net17;
  wire net18;
  wire net19;
  wire net20;
  wire net21;
  wire net22;
  wire net23;
  wire net24;
  wire net25;
  wire net26;
  wire net27;
  wire net28;
  wire net29;
  wire net30;
  wire net31;
  wire net32;
  wire net33;
  wire net34;
  wire net35;
  wire net36;
  wire net37;
  wire net38;
  wire net39;

  assign io_out[0] = net9;
  assign io_out[1] = net10;

  and_cell gate1 (
    .a (net14),
    .b (net8),
    .out (net15)
  );
  or_cell gate2 (

  );
  xor_cell gate3 (
    .a (net16),
    .b (net15),
    .out (net10)
  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  not_cell gate7 (
    .in (net2),
    .out (net17)
  );
  and_cell gate8 (
    .a (net17),
    .b (net18),
    .out (net19)
  );
  and_cell gate9 (
    .a (net20),
    .b (net3),
    .out (net21)
  );
  and_cell gate10 (
    .a (net4),
    .b (net22),
    .out (net23)
  );
  xor_cell gate11 (
    .a (net24),
    .b (net19),
    .out (net25)
  );
  xor_cell gate12 (
    .a (net21),
    .b (net23),
    .out (net26)
  );
  xor_cell gate13 (
    .a (net27),
    .b (net26),
    .out (net9)
  );
  xor_cell gate14 (
    .a (net28),
    .b (net29),
    .out (net30)
  );
  and_cell gate15 (
    .a (net31),
    .b (net32),
    .out (net29)
  );
  not_cell gate16 (
    .in (net5),
    .out (net32)
  );
  and_cell gate17 (
    .a (net3),
    .b (net7),
    .out (net33)
  );
  xor_cell gate18 (
    .a (net30),
    .b (net34),
    .out (net16)
  );
  buffer_cell gate19 (
    .in (net4),
    .out (net18)
  );
  buffer_cell gate20 (
    .in (net25),
    .out (net27)
  );
  buffer_cell gate21 (
    .in (net2),
    .out (net35)
  );
  buffer_cell gate22 (
    .in (net35),
    .out (net20)
  );
  buffer_cell gate23 (
    .in (net36),
    .out (net22)
  );
  buffer_cell gate24 (
    .in (net5),
    .out (net36)
  );
  buffer_cell gate25 (
    .in (net22),
    .out (net14)
  );
  buffer_cell gate26 (
    .in (net3),
    .out (net31)
  );
  buffer_cell gate27 (
    .in (net37),
    .out (net34)
  );
  buffer_cell gate28 (
    .in (net33),
    .out (net37)
  );
  buffer_cell gate29 (
    .in (net6),
    .out (net38)
  );
  buffer_cell gate30 (
    .in (net38),
    .out (net28)
  );
  buffer_cell gate31 (
    .in (net39),
    .out (net24)
  );
  buffer_cell gate32 (
    .in (net1),
    .out (net39)
  );
endmodule
module user_module_340218629792465491(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2;
  wire net3;
  wire net4;
  wire net5;
  wire net6;
  wire net7;
  wire net8 = 1'b0;
  wire net9 = 1'b1;
  wire net10 = 1'b1;
  wire net11;

  assign io_out[0] = net2;
  assign io_out[1] = net3;
  assign io_out[2] = net4;
  assign io_out[3] = net5;
  assign io_out[4] = net6;
  assign io_out[5] = net7;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  dff_cell flipflop2 (
    .d (net11),
    .clk (net1),
    .q (net2)
  );
  dff_cell flipflop3 (
    .d (net2),
    .clk (net1),
    .q (net3)
  );
  dff_cell flipflop4 (
    .d (net3),
    .clk (net1),
    .q (net4)
  );
  dff_cell flipflop5 (
    .d (net4),
    .clk (net1),
    .q (net5)
  );
  dff_cell flipflop6 (
    .d (net5),
    .clk (net1),
    .q (net6)
  );
  dff_cell flipflop7 (
    .d (net6),
    .clk (net1),
    .q (net7),
    .notq (net11)
  );
endmodule
module user_module_341432284947153491(
	input [7:0] io_in, 
	output [7:0] io_out
);

	wire clk, reset, sclk, ce, sin, in0, in1, in2;
	assign clk   = io_in[0];
	assign reset = io_in[1];
	assign sclk  = io_in[2];
	assign ce    = io_in[3];
	assign sin   = io_in[4];
	assign in0   = io_in[5];
	assign in1   = io_in[6];
	assign in2   = io_in[7];

	wire [6:0] out;
	wire sout;
	assign io_out = { sout, out };

	wire [2:0] ioexp_in;
	assign ioexp_in = { io_in[7], io_in[6], io_in[5] };

	spi_341432284947153491 #(.INBITS(3), .OUTBITS(7)) spi_core (
		.reset(reset),
		.clk(clk),
		.sclk(sclk),
		.ce(ce),
		.sin(sin),
		.sout(sout),
		.inputs(ioexp_in),
		.outputs(out)
	);

	// The SPI module latches in the inputs on neg CE and latches out the
	// outputs on pos CE

endmodule
module spi_341432284947153491 #(
	parameter INBITS = 4,
	parameter OUTBITS = 4
) (
	input                reset, // synchronous internal reset
	input                clk, // system clock
	input                sclk, // negative polarity
	input                ce, // active low
	input                sin,
	output               sout,
	input  [INBITS-1:0]  inputs,
	output [OUTBITS-1:0] outputs
);

	// Note: We shift IN the IO OUTPUTS. We shift OUT the IO INPUTS.
	reg [OUTBITS-1:0] inlatch; // serial input latch (latch on CE rising edge)
	reg [OUTBITS-1:0] inbuf; // serial input buffer (latch on CE rising edge)
	reg [INBITS-1:0] outlatch; // serial output latch (latch on CE falling edge)
	
	assign sout = outlatch[0];
	assign outputs = inlatch;

	wire ce_posedge, ce_negedge;
	posedge_341432284947153491 pe_ce(.clk(clk), .in(ce), .pedge(ce_posedge));
	negedge_341432284947153491 ne_ce(.clk(clk), .in(ce), .nedge(ce_negedge));

	wire sclk_posedge, sclk_negedge;
	posedge_341432284947153491 pe_sclk(.clk(clk), .in(sclk), .pedge(sclk_posedge));
	negedge_341432284947153491 ne_sclk(.clk(clk), .in(sclk), .nedge(sclk_negedge));

	always @(posedge clk) begin
		if (reset) begin
			inbuf <= 0;
			inlatch <= 0;
			outlatch <= 0;
		end else if (ce_posedge) begin
			inlatch <= inbuf;
		end else if (ce_negedge) begin
			outlatch <= inputs;
		//end else if (ce) begin
			//inbuf <= 0;
			//outlatch <= 0;
		end else begin
			if (sclk_posedge) begin
				outlatch <= { 1'b0, outlatch[INBITS-1:1] };
			end else if (sclk_negedge) begin
				inbuf <= { inbuf[OUTBITS-2:0], sin };
			end
		end
	end

endmodule
module posedge_341432284947153491(input clk, input in, output pedge);
	reg last, now;
	assign pedge = !last && now;
	always @(posedge clk) begin
		{last, now} = {now, in};
	end
endmodule
module negedge_341432284947153491(input clk, input in, output nedge);
	reg last, now;
	assign nedge = last && !now;
	always @(posedge clk) begin
		{last, now} = {now, in};
	end
endmodule
module user_module_341637831098106450(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3;
  wire net4;
  wire net5;
  wire net6;
  wire net7;
  wire net8 = 1'b0;
  wire net9 = 1'b1;
  wire net10 = 1'b1;
  wire net11;
  wire net12;
  wire net13;
  wire net14;
  wire net15;
  wire net16;
  wire net17;
  wire net18;
  wire net19;
  wire net20;
  wire net21 = 1'b1;
  wire net22;
  wire net23;

  assign io_out[0] = net3;
  assign io_out[1] = net4;
  assign io_out[2] = net4;
  assign io_out[3] = net5;
  assign io_out[4] = net6;
  assign io_out[5] = net6;
  assign io_out[6] = net7;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (
    .d (net11),
    .clk (net12),
    .q (net13)
  );
  and_cell gate7 (
    .a (net14),
    .b (net15),
    .out (net11)
  );
  dff_cell flipflop6 (
    .d (net13),
    .clk (net12),
    .q (net16)
  );
  dff_cell flipflop2 (
    .d (net16),
    .clk (net12),
    .q (net17)
  );
  dff_cell flipflop3 (
    .d (net17),
    .clk (net12),
    .q (net18)
  );
  dff_cell flipflop4 (
    .d (net19),
    .clk (net12),
    .q (net14)
  );
  or_cell gate17 (
    .a (net16),
    .b (net17),
    .out (net20)
  );
  or_cell gate18 (
    .a (net18),
    .b (net13),
    .out (net3)
  );
  or_cell gate22 (
    .a (net13),
    .b (net14),
    .out (net7)
  );
  not_cell gate24 (
    .in (net2),
    .out (net15)
  );
  mux_cell mux2 (
    .a (net21),
    .b (net22),
    .sel (net15),
    .out (net19)
  );
  buffer_cell gate11 (
    .in (net1),
    .out (net12)
  );
  dff_cell flipflop5 (
    .d (net18),
    .clk (net12),
    .q (net22)
  );
  or_cell gate13 (
    .a (net14),
    .b (net18),
    .out (net4)
  );
  not_cell gate14 (
    .in (net22),
    .out (net6)
  );
  or_cell gate15 (
    .a (net23),
    .b (net18),
    .out (net5)
  );
  or_cell gate16 (
    .a (net13),
    .b (net20),
    .out (net23)
  );
endmodule
module user_module_341464767397888596(
  input [7:0] io_in, 
  output [7:0] io_out
);

wire [2:0] a;
wire [2:0] b;
wire [3:0] c;

assign a = io_in[3:1];
assign b = io_in[6:4];
assign c = a+b;

assign io_out[0] = c[1] || (!c[2]&&!c[0]) || (c[2]&&c[0]);
assign io_out[1] = (!c[2]&&!c[0]) || (!c[1]&&!c[0]) || (c[1]&&c[0]);
assign io_out[2] = c[2] || (!c[1]&&!c[0]) || (c[1]&&c[0]);
assign io_out[3] = (!c[2]&&!c[0])|| (!c[2]&&c[1])|| (c[1]&&!c[0])|| (c[2]&&!c[1]&&c[0]);
assign io_out[4] = (c[1]&& !c[0]) || (!c[2]&&!c[1]);
assign io_out[5] = !c[1] || (c[2]&& !c[0]);
assign io_out[6] =  (!c[2]&& c[1])|| (c[1]&&!c[0])||(c[2]&&!c[1]);
assign io_out[7] = c[3];


endmodule
module user_module_3398002391929329472 (
  input [7:0] io_in,
  output [7:0] io_out
);

  MulInv8 mod1(.clock(1'b0), .reset(1'b0), .io_in(io_in), .io_out(io_out));

endmodule
module user_module_341353777861755476(
  input [7:0] io_in, 
  output [7:0] io_out
);

  // Frame data shift register because we don't have enough pins to load a whole 16-bit config "frame"
  wire frame_sr_clk = io_in[2];
  reg [15:0] frame_sr;

  always @(posedge frame_sr_clk)
    frame_sr <= {frame_sr[14:0], io_in[3]};

  srlut_341353777861755476 #(.K(4)) dut (
    .frame_strobe(io_in[0]),
    .cfg_mode_n(io_in[1]),
    .frame_data(frame_sr),
    .write_clk(io_in[2]),
    .write_data(io_in[3]),
    .lut_i(io_in[7:4]),
    .lut_o(io_out[0])
  );

  assign io_out[7:1] = 6'b0;

endmodule
module srlut_341353777861755476 #(parameter K=4) (
    input wire frame_strobe,
    input wire cfg_mode_n,
    input wire [2**K-1:0] frame_data, // {lut_init[W-1:0]}
    input wire write_clk,
    input wire write_data,

    input wire [K-1:0] lut_i,
    output wire lut_o
);
    localparam W=2**K;
    wire [W-1:0] lut_data;

    wire write_freeze, big_pulse, smol_pulse;

    write_pulse_gen_341353777861755476 pulse_gen_i (
        .clk(write_clk && cfg_mode_n),
        .big_pulse(big_pulse),
        .smol_pulse(smol_pulse)
    );

    // Storage array
    generate
        genvar ii;
        for (ii = 0; ii < W; ii = ii + 1'b1) begin: lut_loop
            wire bit_d;
            wire bit_strobe = ~(smol_pulse | frame_strobe);
            wire shift_buf_d;

            if (ii == 0)
                assign shift_buf_d = write_data;
            else
                assign shift_buf_d = lut_data[ii - 1];

            sky130_fd_sc_hd__ebufn_1 shift_buf_i (
                .A(shift_buf_d),
                .TE_B(big_pulse),
                .Z(bit_d)
            );

            sky130_fd_sc_hd__ebufn_1 cfg_buf_i (
                .A(frame_data[ii]),
                .TE_B(cfg_mode_n),
                .Z(bit_d)
            );

            sky130_fd_sc_hd__dlxtn_1 bit_cell_i (
                .D(bit_d),
                .GATE_N(~bit_strobe),
                .Q(lut_data[ii])
            );
        end
    endgenerate

    // LUT output mux
    assign lut_o = lut_data[lut_i];
endmodule
module buffer_chain_341353777861755476 (input A, output X);

    localparam N = 5;

    wire [N:0] c;
    assign c[0] = A;
    assign X = c[N];

    generate
        genvar ii;
        for (ii = 1'b0; ii < N; ii = ii + 1'b1) begin : bufs
            (* keep, dont_touch *) sky130_fd_sc_hd__clkdlybuf4s50_1 buf_i (.A(c[ii]), .X(c[ii + 1'b1]));
        end
    endgenerate

endmodule
module write_pulse_gen_341353777861755476 (input wire clk, output wire big_pulse, smol_pulse);
    wire clk_del0, clk_del1, clk_del2, clk_del3, clk_strb;
    buffer_chain_341353777861755476 dly0_i (.A(clk), .X(clk_del0)/* , .VPWR(1'b1), .VGND(1'b0) */);
    buffer_chain_341353777861755476 dly1_i (.A(clk_del0), .X(clk_del1)/* , .VPWR(1'b1), .VGND(1'b0) */);
    buffer_chain_341353777861755476 dly2_i (.A(clk_del1), .X(clk_del2)/* , .VPWR(1'b1), .VGND(1'b0) */);
    buffer_chain_341353777861755476 dly3_i (.A(clk_del2), .X(clk_del3)/* , .VPWR(1'b1), .VGND(1'b0) */);
    sky130_fd_sc_hd__and2b_2 cmpb_i (.A_N(clk_del3), .B(clk), .X(big_pulse)/* , .VPWR(1'b1), .VGND(1'b0) */);
    sky130_fd_sc_hd__and2b_2 cmps_i (.A_N(clk_del2), .B(clk_del1), .X(smol_pulse)/* , .VPWR(1'b1), .VGND(1'b0) */);
endmodule
module user_module_340579111348994642(
  input [7:0] io_in, 
  output [7:0] io_out
);

clock clock_top (
    .i_clk(io_in[0]),
    .i_rst(io_in[1]),
    .i_min_up(io_in[2]),
    .i_hour_up(io_in[3]),
    .i_freq(io_in[4]),
    .o_clk(io_out[0]),
    .o_latch(io_out[1]),
    .o_bit(io_out[2])
);

endmodule