dakies/OSS_Verilog huggingface dataset:
module oc8051_divide (clk, rst, enable, src1, src2, des1, des2, desOv);
//
// this module is part of alu
// clk          (in)
// rst          (in)
// enable       (in)  starts divison
// src1         (in)  first operand
// src2         (in)  second operand
// des1         (out) first result
// des2         (out) second result
// desOv        (out) Overflow output
//

input clk, rst, enable;
input [7:0] src1, src2;
output desOv;
output [7:0] des1, des2;

// wires
wire desOv;
wire div0, div1;
wire [7:0] rem0, rem1, rem2;
wire [8:0] sub0, sub1;
wire [15:0] cmp0, cmp1;
wire [7:0] div_out, rem_out;

// real registers
reg [1:0] cycle;
reg [5:0] tmp_div;
reg [7:0] tmp_rem;

// The main logic
assign cmp1 = src2 << ({2'h3 - cycle, 1'b0} + 3'h1);
assign cmp0 = src2 << ({2'h3 - cycle, 1'b0} + 3'h0);

assign rem2 = cycle != 0 ? tmp_rem : src1;

assign sub1 = {1'b0, rem2} - {1'b0, cmp1[7:0]};
assign div1 = |cmp1[15:8] ? 1'b0 : !sub1[8];
assign rem1 = div1 ? sub1[7:0] : rem2[7:0];

assign sub0 = {1'b0, rem1} - {1'b0, cmp0[7:0]};
assign div0 = |cmp0[15:8] ? 1'b0 : !sub0[8];
assign rem0 = div0 ? sub0[7:0] : rem1[7:0];

//
// in clock cycle 0 we first calculate two MSB bits, ...
// till finally in clock cycle 3 we calculate two LSB bits
assign div_out = {tmp_div, div1, div0};
assign rem_out = rem0;
assign desOv = src2 == 8'h0;

//
// divider works in four clock cycles -- 0, 1, 2 and 3
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    cycle <= #1 2'b0;
    tmp_div <= #1 6'h0;
    tmp_rem <= #1 8'h0;
  end else begin
    if (enable) cycle <= #1 cycle + 2'b1;
    tmp_div <= #1 div_out[5:0];
    tmp_rem <= #1 rem_out;
  end
end

//
// assign outputs
assign des1 = rem_out;
assign des2 = div_out;

endmodule
module oc8051_indi_addr (clk, rst, wr_addr, data_in, wr, wr_bit, ri_out, sel, bank);
//


input        clk,	// clock
             rst,	// reset
	     wr,	// write
             sel,	// select register
	     wr_bit;	// write bit addressable
input  [1:0] bank;	// select register bank
input  [7:0] data_in;	// data input
input  [7:0] wr_addr;	// write address

output [7:0] ri_out;

//reg [7:0] buff [31:0];
reg wr_bit_r;


reg [7:0] buff [0:7];

//
//write to buffer
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    buff[3'b000] <= #1 8'h00;
    buff[3'b001] <= #1 8'h00;
    buff[3'b010] <= #1 8'h00;
    buff[3'b011] <= #1 8'h00;
    buff[3'b100] <= #1 8'h00;
    buff[3'b101] <= #1 8'h00;
    buff[3'b110] <= #1 8'h00;
    buff[3'b111] <= #1 8'h00;
  end else begin
    if ((wr) & !(wr_bit_r)) begin
      case (wr_addr) /* synopsys full_case parallel_case */
        8'h00: buff[3'b000] <= #1 data_in;
        8'h01: buff[3'b001] <= #1 data_in;
        8'h08: buff[3'b010] <= #1 data_in;
        8'h09: buff[3'b011] <= #1 data_in;
        8'h10: buff[3'b100] <= #1 data_in;
        8'h11: buff[3'b101] <= #1 data_in;
        8'h18: buff[3'b110] <= #1 data_in;
        8'h19: buff[3'b111] <= #1 data_in;
      endcase
    end
  end
end

//
//read from buffer

assign ri_out = (({3'b000, bank, 2'b00, sel}==wr_addr) & (wr) & !wr_bit_r) ?
                 data_in : buff[{bank, sel}];



always @(posedge clk or posedge rst)
  if (rst) begin
    wr_bit_r <= #1 1'b0;
  end else begin
    wr_bit_r <= #1 wr_bit;
  end

endmodule
module oc8051_comp (sel, b_in, cy, acc, des, /*comp_wait, */eq);
//
// sel          (in)  select whithc sourses to compare (look defines.v) [oc8051_decoder.comp_sel]
// b_in         (in)  bit in - output from bit addressable memory space [oc8051_ram_sel.bit_out]
// cy           (in)  carry flag [oc8051_psw.data_out[7] ]
// acc          (in)  accumulator [oc8051_acc.data_out]
// ram          (in)  input from ram [oc8051_ram_sel.out_data]
// op2          (in)  immediate data [oc8051_op_select.op2_out -r]
// des          (in)  destination from alu [oc8051_alu.des1 -r]
// eq           (out) if (src1 == src2) eq = 1  [oc8051_decoder.eq]
//


input [1:0] sel;
input b_in, cy/*, comp_wait*/;
input [7:0] acc, des;

output eq;

reg eq_r;

assign eq = eq_r;// & comp_wait;


always @(sel or b_in or cy or acc or des)
begin
  case (sel) /* synopsys full_case parallel_case */
    `OC8051_CSS_AZ  : eq_r = (acc == 8'h00);
    `OC8051_CSS_DES : eq_r = (des == 8'h00);
    `OC8051_CSS_CY  : eq_r = cy;
    `OC8051_CSS_BIT : eq_r = b_in;
  endcase
end

endmodule
module oc8051_wb_iinterface(rst, clk, 
                  adr_i, dat_o, cyc_i, stb_i, ack_o,
		  adr_o, dat_i, cyc_o, stb_o, ack_i
		  );
//
// rst           (in)  reset - pin
// clk           (in)  clock - pini
input rst, clk;

//
// interface to oc8051 cpu
//
// adr_i    (in)  address
// dat_o    (out) data output
// stb_i    (in)  strobe
// ack_o    (out) acknowledge
// cyc_i    (in)  cycle
input         stb_i,
              cyc_i;
input  [15:0] adr_i;
output        ack_o;
output [31:0] dat_o;

//
// interface to instruction rom
//
// adr_o    (out) address
// dat_i    (in)  data input
// stb_o    (out) strobe
// ack_i    (in) acknowledge
// cyc_o    (out)  cycle
input         ack_i;
input  [31:0] dat_i;
output        stb_o,
              cyc_o;
output [15:0] adr_o;

//
// internal bufers and wires
//
reg [15:0] adr_o;
reg        stb_o;

assign ack_o = ack_i;
assign dat_o = dat_i;
//assign stb_o = stb_i || ack_i;
assign cyc_o = stb_o;
//assign adr_o = ack_i ? adr : adr_i;

always @(posedge clk or posedge rst)
  if (rst) begin
    stb_o <= #1 1'b0;
    adr_o <= #1 16'h0000;
  end else if (ack_i) begin
    stb_o <= #1 stb_i;
    adr_o <= #1 adr_i;
  end else if (!stb_o & stb_i) begin
    stb_o <= #1 1'b1;
    adr_o <= #1 adr_i;
  end

endmodule
module oc8051_ram_256x8_two_bist (
                     clk,
                     rst,
		     rd_addr,
		     rd_data,
		     rd_en,
		     wr_addr,
		     wr_data,
		     wr_en,
		     wr
`ifdef OC8051_BIST
	 ,
         scanb_rst,
         scanb_clk,
         scanb_si,
         scanb_so,
         scanb_en
`endif
		     );


input         clk, 
              wr, 
	      rst,
	      rd_en,
	      wr_en;
input  [7:0]  wr_data;
input  [7:0]  rd_addr,
              wr_addr;
output [7:0]  rd_data;

`ifdef OC8051_BIST
input   scanb_rst;
input   scanb_clk;
input   scanb_si;
output  scanb_so;
input   scanb_en;
`endif


`ifdef OC8051_RAM_XILINX
  xilinx_ram_dp xilinx_ram(
  	// read port
  	.CLKA(clk),
  	.RSTA(rst),
  	.ENA(rd_en),
  	.ADDRA(rd_addr),
  	.DIA(8'h00),
  	.WEA(1'b0),
  	.DOA(rd_data),
  
  	// write port
  	.CLKB(clk),
  	.RSTB(rst),
  	.ENB(wr_en),
  	.ADDRB(wr_addr),
  	.DIB(wr_data),
  	.WEB(wr),
  	.DOB()
  );
  
  defparam
  	xilinx_ram.dwidth = 8,
  	xilinx_ram.awidth = 8;

`else

  `ifdef OC8051_RAM_VIRTUALSILICON

  `else

    `ifdef OC8051_RAM_GENERIC
    
      generic_dpram #(8, 8) oc8051_ram1(
      	.rclk  ( clk            ),
      	.rrst  ( rst            ),
      	.rce   ( rd_en          ),
      	.oe    ( 1'b1           ),
      	.raddr ( rd_addr        ),
      	.do    ( rd_data        ),
      
      	.wclk  ( clk            ),
      	.wrst  ( rst            ),
      	.wce   ( wr_en          ),
      	.we    ( wr             ),
      	.waddr ( wr_addr        ),
      	.di    ( wr_data        )
      );
    
    `else

      reg    [7:0]  rd_data;
      //
      // buffer
      reg    [7:0]  buff [0:256];
      
      
      //
      // writing to ram
      always @(posedge clk)
      begin
       if (wr)
          buff[wr_addr] <= #1 wr_data;
      end
      
      //
      // reading from ram
      always @(posedge clk or posedge rst)
      begin
        if (rst)
          rd_data <= #1 8'h0;
        else if ((wr_addr==rd_addr) & wr & rd_en)
          rd_data <= #1 wr_data;
        else if (rd_en)
          rd_data <= #1 buff[rd_addr];
      end
    `endif  //OC8051_RAM_GENERIC
  `endif    //OC8051_RAM_VIRTUALSILICON  
`endif      //OC8051_RAM_XILINX

endmodule
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);

parameter INT_ROM_WID= 7;

input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;

wire ea;

assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;

initial
begin
    for (i=0; i<65536; i=i+1)
      buff [i] = 8'h00;
#2

    buff [16'h00_00] = 8'h02;
    buff [16'h00_01] = 8'h00;
    buff [16'h00_02] = 8'h2E;
    buff [16'h00_03] = 8'h7D;
    buff [16'h00_04] = 8'hAA;
    buff [16'h00_05] = 8'hE4;
    buff [16'h00_06] = 8'hFC;
    buff [16'h00_07] = 8'h74;
    buff [16'h00_08] = 8'h01;
    buff [16'h00_09] = 8'h7E;
    buff [16'h00_0a] = 8'h00;
    buff [16'h00_0b] = 8'hA8;
    buff [16'h00_0c] = 8'h04;
    buff [16'h00_0d] = 8'h08;
    buff [16'h00_0e] = 8'h80;
    buff [16'h00_0f] = 8'h05;
    buff [16'h00_10] = 8'hC3;
    buff [16'h00_11] = 8'h33;
    buff [16'h00_12] = 8'hCE;
    buff [16'h00_13] = 8'h33;
    buff [16'h00_14] = 8'hCE;
    buff [16'h00_15] = 8'hD8;
    buff [16'h00_16] = 8'hF9;
    buff [16'h00_17] = 8'hFF;
    buff [16'h00_18] = 8'hED;
    buff [16'h00_19] = 8'hFB;
    buff [16'h00_1a] = 8'hE4;
    buff [16'h00_1b] = 8'hEF;
    buff [16'h00_1c] = 8'h5B;
    buff [16'h00_1d] = 8'h60;
    buff [16'h00_1e] = 8'h04;
    buff [16'h00_1f] = 8'h7F;
    buff [16'h00_20] = 8'h01;
    buff [16'h00_21] = 8'h80;
    buff [16'h00_22] = 8'h02;
    buff [16'h00_23] = 8'h7F;
    buff [16'h00_24] = 8'h00;
    buff [16'h00_25] = 8'h8F;
    buff [16'h00_26] = 8'h80;
    buff [16'h00_27] = 8'h0C;
    buff [16'h00_28] = 8'hBC;
    buff [16'h00_29] = 8'h08;
    buff [16'h00_2a] = 8'hDC;
    buff [16'h00_2b] = 8'h80;
    buff [16'h00_2c] = 8'hFE;
    buff [16'h00_2d] = 8'h22;
    buff [16'h00_2e] = 8'h78;
    buff [16'h00_2f] = 8'h7F;
    buff [16'h00_30] = 8'hE4;
    buff [16'h00_31] = 8'hF6;
    buff [16'h00_32] = 8'hD8;
    buff [16'h00_33] = 8'hFD;
    buff [16'h00_34] = 8'h75;
    buff [16'h00_35] = 8'h81;
    buff [16'h00_36] = 8'h07;
    buff [16'h00_37] = 8'h02;
    buff [16'h00_38] = 8'h00;
    buff [16'h00_39] = 8'h03;
end

always @(posedge clk)
begin
  data1 <= #1 buff [addr];
  data2 <= #1 buff [addr+1];
  data3 <= #1 buff [addr+2];
end

endmodule
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);

parameter INT_ROM_WID= 7;

input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;

wire ea;

assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;

initial
begin
    for (i=0; i<65536; i=i+1)
      buff [i] = 8'h00;
#2

    buff [16'h00_00] = 8'h02;
    buff [16'h00_01] = 8'h00;
    buff [16'h00_02] = 8'h25;
    buff [16'h00_03] = 8'h7F;
    buff [16'h00_04] = 8'h2F;
    buff [16'h00_05] = 8'h7E;
    buff [16'h00_06] = 8'h0B;
    buff [16'h00_07] = 8'hEF;
    buff [16'h00_08] = 8'h6E;
    buff [16'h00_09] = 8'h60;
    buff [16'h00_0a] = 8'h15;
    buff [16'h00_0b] = 8'hEF;
    buff [16'h00_0c] = 8'hD3;
    buff [16'h00_0d] = 8'h9E;
    buff [16'h00_0e] = 8'h40;
    buff [16'h00_0f] = 8'h08;
    buff [16'h00_10] = 8'hC3;
    buff [16'h00_11] = 8'hEF;
    buff [16'h00_12] = 8'h9E;
    buff [16'h00_13] = 8'hFF;
    buff [16'h00_14] = 8'hF5;
    buff [16'h00_15] = 8'h80;
    buff [16'h00_16] = 8'h80;
    buff [16'h00_17] = 8'hEF;
    buff [16'h00_18] = 8'hC3;
    buff [16'h00_19] = 8'hEE;
    buff [16'h00_1a] = 8'h9F;
    buff [16'h00_1b] = 8'hFE;
    buff [16'h00_1c] = 8'hF5;
    buff [16'h00_1d] = 8'h90;
    buff [16'h00_1e] = 8'h80;
    buff [16'h00_1f] = 8'hE7;
    buff [16'h00_20] = 8'h8F;
    buff [16'h00_21] = 8'hA0;
    buff [16'h00_22] = 8'h80;
    buff [16'h00_23] = 8'hFE;
    buff [16'h00_24] = 8'h22;
    buff [16'h00_25] = 8'h78;
    buff [16'h00_26] = 8'h7F;
    buff [16'h00_27] = 8'hE4;
    buff [16'h00_28] = 8'hF6;
    buff [16'h00_29] = 8'hD8;
    buff [16'h00_2a] = 8'hFD;
    buff [16'h00_2b] = 8'h75;
    buff [16'h00_2c] = 8'h81;
    buff [16'h00_2d] = 8'h07;
    buff [16'h00_2e] = 8'h02;
    buff [16'h00_2f] = 8'h00;
    buff [16'h00_30] = 8'h03;
end

always @(posedge clk)
begin
  data1 <= #1 buff [addr];
  data2 <= #1 buff [addr+1];
  data3 <= #1 buff [addr+2];
end

endmodule
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);

parameter INT_ROM_WID= 7;

input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;

wire ea;

assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;

initial
begin
    for (i=0; i<65536; i=i+1)
      buff [i] = 8'h00;
#2

    buff [16'h00_00] = 8'h02;
    buff [16'h00_01] = 8'h00;
    buff [16'h00_02] = 8'h35;
    buff [16'h00_03] = 8'h90;
    buff [16'h00_04] = 8'h00;
    buff [16'h00_05] = 8'h00;
    buff [16'h00_06] = 8'h74;
    buff [16'h00_07] = 8'h01;
    buff [16'h00_08] = 8'hF0;
    buff [16'h00_09] = 8'hFF;
    buff [16'h00_0a] = 8'h7E;
    buff [16'h00_0b] = 8'h00;
    buff [16'h00_0c] = 8'h74;
    buff [16'h00_0d] = 8'hFF;
    buff [16'h00_0e] = 8'h2F;
    buff [16'h00_0f] = 8'hF5;
    buff [16'h00_10] = 8'h82;
    buff [16'h00_11] = 8'hEE;
    buff [16'h00_12] = 8'h34;
    buff [16'h00_13] = 8'hFF;
    buff [16'h00_14] = 8'hF5;
    buff [16'h00_15] = 8'h83;
    buff [16'h00_16] = 8'hE0;
    buff [16'h00_17] = 8'h04;
    buff [16'h00_18] = 8'hFD;
    buff [16'h00_19] = 8'h74;
    buff [16'h00_1a] = 8'h00;
    buff [16'h00_1b] = 8'h2F;
    buff [16'h00_1c] = 8'hF5;
    buff [16'h00_1d] = 8'h82;
    buff [16'h00_1e] = 8'hEE;
    buff [16'h00_1f] = 8'h34;
    buff [16'h00_20] = 8'h00;
    buff [16'h00_21] = 8'hF5;
    buff [16'h00_22] = 8'h83;
    buff [16'h00_23] = 8'hED;
    buff [16'h00_24] = 8'hF0;
    buff [16'h00_25] = 8'h0F;
    buff [16'h00_26] = 8'hBF;
    buff [16'h00_27] = 8'h00;
    buff [16'h00_28] = 8'h01;
    buff [16'h00_29] = 8'h0E;
    buff [16'h00_2a] = 8'hE4;
    buff [16'h00_2b] = 8'hB5;
    buff [16'h00_2c] = 8'h07;
    buff [16'h00_2d] = 8'hDE;
    buff [16'h00_2e] = 8'hEE;
    buff [16'h00_2f] = 8'hB4;
    buff [16'h00_30] = 8'h08;
    buff [16'h00_31] = 8'hDA;
    buff [16'h00_32] = 8'h80;
    buff [16'h00_33] = 8'hFE;
    buff [16'h00_34] = 8'h22;
    buff [16'h00_35] = 8'h78;
    buff [16'h00_36] = 8'h7F;
    buff [16'h00_37] = 8'hE4;
    buff [16'h00_38] = 8'hF6;
    buff [16'h00_39] = 8'hD8;
    buff [16'h00_3a] = 8'hFD;
    buff [16'h00_3b] = 8'h75;
    buff [16'h00_3c] = 8'h81;
    buff [16'h00_3d] = 8'h07;
    buff [16'h00_3e] = 8'h02;
    buff [16'h00_3f] = 8'h00;
    buff [16'h00_40] = 8'h03;
end

always @(posedge clk)
begin
  data1 <= #1 buff [addr];
  data2 <= #1 buff [addr+1];
  data3 <= #1 buff [addr+2];
end

endmodule
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);

parameter INT_ROM_WID= 7;

input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;

wire ea;

assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;

initial
begin
    for (i=0; i<65536; i=i+1)
      buff [i] = 8'h00;
#2

    buff [16'h00_00] = 8'h75;
    buff [16'h00_01] = 8'h20;
    buff [16'h00_02] = 8'h00;
    buff [16'h00_03] = 8'hD2;
    buff [16'h00_04] = 8'h02;
    buff [16'h00_05] = 8'h12;
    buff [16'h00_06] = 8'h00;
    buff [16'h00_07] = 8'h0E;
    buff [16'h00_08] = 8'h85;
    buff [16'h00_09] = 8'h20;
    buff [16'h00_0a] = 8'h80;
    buff [16'h00_0b] = 8'h02;
    buff [16'h00_0c] = 8'h00;
    buff [16'h00_0d] = 8'h12;
    buff [16'h00_0e] = 8'h75;
    buff [16'h00_0f] = 8'h80;
    buff [16'h00_10] = 8'h0A;
    buff [16'h00_11] = 8'h22;
    buff [16'h00_12] = 8'h00;
    buff [16'h00_13] = 8'h00;
end

always @(posedge clk)
begin
  data1 <= #1 buff [addr];
  data2 <= #1 buff [addr+1];
  data3 <= #1 buff [addr+2];
end

endmodule
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);

parameter INT_ROM_WID= 7;

input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;

wire ea;

assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;

initial
begin
    for (i=0; i<65536; i=i+1)
      buff [i] = 8'h00;
#2

    buff [16'h00_00] = 8'h02;
    buff [16'h00_01] = 8'h00;
    buff [16'h00_02] = 8'h19;
    buff [16'h00_03] = 8'h7F;
    buff [16'h00_04] = 8'h40;
    buff [16'h00_05] = 8'h7E;
    buff [16'h00_06] = 8'hFC;
    buff [16'h00_07] = 8'hAD;
    buff [16'h00_08] = 8'h07;
    buff [16'h00_09] = 8'h8D;
    buff [16'h00_0a] = 8'h80;
    buff [16'h00_0b] = 8'h0F;
    buff [16'h00_0c] = 8'hBF;
    buff [16'h00_0d] = 8'h00;
    buff [16'h00_0e] = 8'h01;
    buff [16'h00_0f] = 8'h0E;
    buff [16'h00_10] = 8'hBE;
    buff [16'h00_11] = 8'hFC;
    buff [16'h00_12] = 8'hF4;
    buff [16'h00_13] = 8'hBF;
    buff [16'h00_14] = 8'h4A;
    buff [16'h00_15] = 8'hF1;
    buff [16'h00_16] = 8'h80;
    buff [16'h00_17] = 8'hFE;
    buff [16'h00_18] = 8'h22;
    buff [16'h00_19] = 8'h78;
    buff [16'h00_1a] = 8'h7F;
    buff [16'h00_1b] = 8'hE4;
    buff [16'h00_1c] = 8'hF6;
    buff [16'h00_1d] = 8'hD8;
    buff [16'h00_1e] = 8'hFD;
    buff [16'h00_1f] = 8'h75;
    buff [16'h00_20] = 8'h81;
    buff [16'h00_21] = 8'h07;
    buff [16'h00_22] = 8'h02;
    buff [16'h00_23] = 8'h00;
    buff [16'h00_24] = 8'h03;
end

always @(posedge clk)
begin
  data1 <= #1 buff [addr];
  data2 <= #1 buff [addr+1];
  data3 <= #1 buff [addr+2];
end

endmodule
module oc8051_fpga_tb;

reg rst, clk, int1, int2, int3;

wire  sw1, sw2, sw3, sw4, int_act;
wire [7:0] p0_out, p1_out, p2_out, p3_out, data_out;
wire [13:0] dispout;
wire [15:0] ext_addr;

oc8051_fpga_top oc8051_fpga_top1(.clk(clk), .rst(rst), .int1(int1), .int2(int2), .int3(int3), .sw1(sw1), .sw2(sw2), .sw3(sw3), .sw4(sw4),
                      .int_act(int_act), .dispout(dispout), .p0_out(p0_out), .p1_out(p1_out), .p2_out(p2_out), .p3_out(p3_out), .data_out(data_out),
                      .ext_addr(ext_addr));

initial begin
  clk= 1'b0;
  rst= 1'b0;
  int1= 1'b1;
  int2= 1'b1;
  int3= 1'b1;
#22
  rst = 1'b1;
#1000
  int2= 1'b0;
#100
  int2= 1'b1;

#40000
  int3= 1'b0;
#100
  int3= 1'b1;
#40000

  rst = 1'b0;
#20
  $finish;
end

always clk = #5 ~clk;

initial $dumpvars;

//initial $monitor("time ",$time," rst ",rst, " int1 ", int1, " int2 ", int2, " int3 ", int3, " sw1 ", sw1, " sw2 ", sw2, " sw3 ", sw3, " sw4 ", sw4, " int act ", int_act, " p0_out %h", p0_out);

initial $monitor("time ",$time," rst ",rst, " int1 ", int1, " int2 ", int2, " int3 ", int3, " int act ", int_act, " p0_out %h", p0_out);

endmodule
module oc8051_xram (clk, rst, wr, addr, data_in, data_out, ack, stb);
//
// external data ram for simulation. part of oc8051_tb
// it's tehnology dependent
//
// clk          (in)  clock
// addr         (in)  addres
// data_in      (out) data input
// data_out     (in)  data output
// wr           (in)  write
// ack          (out) acknowlage
// stb          (in)  strobe
//

parameter DELAY=1;


input clk, wr, stb, rst;
input [7:0] data_in;
input [15:0] addr;
output [7:0] data_out;
output ack;

reg ackw, ackr;
reg [7:0] data_out;
reg [2:0] cnt;

//
// buffer
reg [7:0] buff [65535:0];  //64kb
//reg [7:0] buff [8388607:0];  //8Mb

assign ack =  ackw || ackr;


//
// writing to ram
always @(posedge clk or posedge rst)
begin
  if (rst)
    ackw <= #1 1'b0;
  else if (wr && stb && ((DELAY==3'b000) || (cnt==3'b000))) begin
    buff[addr] <= #1 data_in;
    ackw <= #1 1'b1;
  end else ackw <= #1 1'b0;
end

always @(posedge clk or posedge rst)
  if (rst)
    ackr <= #1 1'b0;
  else if (stb && !wr && ((DELAY==3'b000) || (cnt==3'b000))) begin
    data_out <= #1 buff[addr];
    ackr <= #1 1'b1;
  end else begin
    ackr <= #1 1'b0;
    data_out <= #1 8'h00;
  end

always @(posedge clk or posedge rst)
begin
  if (rst)
    cnt <= #1 DELAY;
  else if (cnt==3'b000)
    cnt <= #1 DELAY;
  else if (stb)
    cnt <= #1 cnt - 3'b001;
  else cnt <= #1 DELAY;
end


endmodule
module oc8051_serial (clk, rst, rxd, txd);

parameter FREQ  = 25000;
parameter BRATE = 9.6;

parameter DELAY = FREQ/BRATE;

input        clk,
             rst,
	     rxd;

output       txd;

reg          txd,
             transmit;
reg          txd_start;
reg   [8:0]  txd_data;
reg   [15:0] count;
reg   [8:0]  txd_buf;
reg   [63:0] wait_t;
reg   [7:0]  buff [0:65535];

reg          receive;
reg   [7:0]  rxd_buf;
reg   [63:0] wait_r;

reg   [7:0] tmp;

reg receive_r;
reg rxd_r;

initial
begin
  $readmemh("../../../serial.txt", buff);
end

/*
always @(posedge clk or posedge rst)
  if (rst) begin
    count <= #1 16'h0;
  end else begin
    count <= #1 count + 16'h1;
    $display (" serial h: %h   d: %d    count: %h", buff[count],  buff[count], count);
  end
*/

always @(posedge clk or posedge rst)
  if (rst) begin
    wait_t   <= #1 64'h0;
    txd_buf  <= #1 9'h1ff;
    txd      <= #1 1'b1;
    transmit <= #1 1'b0;
  end else if (txd_start) begin
    transmit <= #1 1'b1;
    txd_buf  <= #1 {txd_data, 1'b0};
  end else if ((wait_t >= DELAY) & transmit) begin
    wait_t         <= #1 64'h0;
    {txd_buf, txd} <= #1 {1'b1, txd_buf};
    transmit       <= #1 ~&{txd_buf, txd};
  end else begin
    wait_t  <= #1 wait_t + 64'h1;
  end

always @(posedge clk or posedge rst)
  if (rst) begin
    wait_r    <= #1 64'h0;
    rxd_buf   <= #1 8'hff;
    rxd_r     <= #1 1'b0;
    receive   <= #1 1'b0;
  end else if (rxd_r & !rxd & !receive) begin
    wait_r  <= #1 DELAY / 2;
    rxd_r <= #1 1'b0;
    receive <= #1 1'b1;
    rxd_buf <= #1 8'hff;
  end else if ((wait_r >= DELAY) & receive) begin
    wait_r  <= #1 64'h0;
    {rxd_buf, receive} <= #1 {rxd, rxd_buf};
  end else if (receive) begin
    wait_r  <= #1 wait_r + 64'h1;
  end else begin
    rxd_r <= #1 rxd;
  end


always @(posedge clk or posedge rst)
begin
  if (rst) begin
    receive_r <= #1 1'b0;
    txd_start <= #1 1'b0;
    txd_data  <= #1 8'h0;
    tmp       <= #1 8'h0;
  end else if (!receive & receive_r) begin
    receive_r <= #1 1'b0;
    if ((tmp==8'h3f) && (rxd_buf==8'h20)) begin
      txd_start <= #1 1'b1;
      txd_data  <= #1 8'h33;
    end else if (rxd_buf==8'h33) begin
      txd_start <= #1 1'b1;
      txd_data  <= #1 8'h36;
    end else if (rxd_buf==8'h36) begin
      txd_start <= #1 1'b1;
      txd_data  <= #1 8'h0a;
    end
    tmp         <= #1 rxd_buf;
    $display (" receive:  %s , %h", rxd_buf, rxd_buf);
  end else begin
    txd_start   <= #1 1'b0;
    receive_r   <= #1 receive;
  end
end

endmodule
module oc8051_xrom (rst, clk, addr, data, stb_i, cyc_i, ack_o);

parameter DELAY=5;


input rst, clk, stb_i, cyc_i;
input [15:0] addr;
output ack_o;
output [31:0] data;


reg ack_o;
reg [31:0] data;

reg [7:0] buff [0:65535];
//reg [7:0] buff [8388607:0];
reg [2:0] cnt;
integer i;


initial
begin
//  for (i=0; i<65536; i=i+1)
//    buff [i] = 8'h00;
  $readmemh("../../../bench/in/oc8051_xrom.in", buff);
end

always @(posedge clk or posedge rst)
begin
  if (rst) begin
    data <= #1 31'h0;
    ack_o <= #1 1'b0;
  end else if (stb_i && ((DELAY==3'b000) || (cnt==3'b000))) begin
    data <= #1 {buff[addr+3], buff[addr+2], buff[addr+1], buff [addr]};
    ack_o <= #1 1'b1;
  end else
    ack_o <= #1 1'b0;
end

always @(posedge clk or posedge rst)
begin
  if (rst)
    cnt <= #1 DELAY;
  else if (cnt == 3'b000)
    cnt <= #1 DELAY;
  else if (stb_i)
    cnt <= #1 cnt - 3'b001;
  else cnt <= #1 DELAY;
end

endmodule
module PLL (
	areset,
	inclk0,
	c0,
	c1,
	c2,
	locked);

	input	  areset;
	input	  inclk0;
	output	  c0;
	output	  c1;
	output	  c2;
	output	  locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0	  areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

endmodule
module single_port_ram_8bit #(parameter ADDR_WIDTH = 14) (
            input  wire [ADDR_WIDTH - 1 : 0]         addr,
            input  wire [7 : 0]                      din,
            input  wire                              write_en, 
            input  wire                              clk,
            output wire [7 : 0]         dout
);
    
            reg [ADDR_WIDTH - 1 : 0] addr_reg;
            reg [7:0]   mem [0 : (2**ADDR_WIDTH) - 1] /* synthesis syn_ramstyle="lsram" */ ;

            assign dout = mem[addr_reg];

            always@(posedge clk) begin
                addr_reg <= addr;   
                
                if(write_en) begin
                    mem[addr] <= din;
                end
            end
    
endmodule
module single_port_ram #(parameter ADDR_WIDTH = 14, DATA_WIDTH = 16) (
            input  wire [ADDR_WIDTH - 1 : 0]         addr,
            input  wire [DATA_WIDTH - 1 : 0]         din,
            input  wire [DATA_WIDTH / 8 - 1 : 0]     write_en, 
            input  wire                              clk,
            output wire [DATA_WIDTH - 1 : 0]         dout
);

    wire [DATA_WIDTH - 1 : 0]         dout_1st;
    wire [DATA_WIDTH - 1 : 0]         dout_2nd;
    
    reg  [ADDR_WIDTH - 1 : 0]         addr_reg;
    
    
    always @(posedge clk) begin
        addr_reg <= addr;
    end
    
    genvar i; 
    
    generate
        if (`MEM_SIZE_IN_BYTES == (48 * 1024)) begin: gen_if_proc
            for (i = 0; i < (DATA_WIDTH / 8); i = i + 1) begin : gen_for_proc1
                
                 single_port_ram_8bit #(.ADDR_WIDTH (ADDR_WIDTH - 1)) ram_8bit_1st (
                    .addr (addr[ADDR_WIDTH - 2 : 0]),
                    .din (din [(i + 1) * 8 - 1 : i * 8]),
                    .write_en (write_en[i] & (~addr[ADDR_WIDTH - 1])),
                    .clk (clk),
                    .dout (dout_1st [(i + 1) * 8 - 1 : i * 8]));
            end
            
            for (i = 0; i < (DATA_WIDTH / 8); i = i + 1) begin : gen_for_proc2
                
                 single_port_ram_8bit #(.ADDR_WIDTH (ADDR_WIDTH - 2)) ram_8bit_2nd (
                    .addr (addr[ADDR_WIDTH - 3 : 0]),
                    .din (din [(i + 1) * 8 - 1 : i * 8]),
                    .write_en (write_en[i] & (addr[ADDR_WIDTH - 1])),
                    .clk (clk),
                    .dout (dout_2nd [(i + 1) * 8 - 1 : i * 8]));
            end
            
            assign dout = addr_reg [ADDR_WIDTH - 1] ? dout_2nd : dout_1st;
        
        end else begin
        
            for (i = 0; i < (DATA_WIDTH / 8); i = i + 1) begin : gen_for_proc
                
                 single_port_ram_8bit #(.ADDR_WIDTH (ADDR_WIDTH)) ram_8bit (
                    .addr (addr),
                    .din (din [(i + 1) * 8 - 1 : i * 8]),
                    .write_en (write_en[i]),
                    .clk (clk),
                    .dout (dout [(i + 1) * 8 - 1 : i * 8]));
            end
        end
        
    endgenerate
    
                
endmodule
module dual_port_ram #(parameter ADDR_WIDTH = 5, DATA_WIDTH = 32) (
          input wire [ADDR_WIDTH - 1 : 0]       waddr, 
          input wire [ADDR_WIDTH - 1 : 0]       raddr,
          
          input wire [DATA_WIDTH - 1 : 0]       din,
          input wire                            write_en, 
          input wire                            clk, 
       
          output wire [DATA_WIDTH - 1 : 0]      dout
);

        reg [ADDR_WIDTH - 1 : 0] raddr_reg;
        reg [DATA_WIDTH - 1 : 0] mem [0 : (2**ADDR_WIDTH) - 1] /* synthesis syn_ramstyle="uram" */;

        assign dout = mem[raddr_reg] ;
        
        always @(posedge clk) begin
            raddr_reg <= raddr;
        end
        
        always@ (posedge clk) begin
            if (write_en) begin
                mem[waddr] <= din;
            end
        end

endmodule
module single_port_ram #(parameter ADDR_WIDTH = 14, DATA_WIDTH = 16) (
            input  wire [ADDR_WIDTH - 1 : 0]         addr,
            input  wire [DATA_WIDTH - 1 : 0]         din,
            input  wire [DATA_WIDTH / 8 - 1 : 0]     write_en, 
            input  wire                              clk,
            output wire [DATA_WIDTH - 1 : 0]         dout
);

    wire [DATA_WIDTH - 1 : 0]         dout_1st;
    wire [DATA_WIDTH - 1 : 0]         dout_2nd;
    
    reg  [ADDR_WIDTH - 1 : 0]         addr_reg;
    
    
    always @(posedge clk) begin
        addr_reg <= addr;
    end
    
    genvar i; 
    
    generate
        if (`MEM_SIZE_IN_BYTES == (48 * 1024)) begin: gen_if_proc
            for (i = 0; i < (DATA_WIDTH / 8); i = i + 1) begin : gen_for_proc_1st
                
                 single_port_ram_8bit #(.ADDR_WIDTH (ADDR_WIDTH - 1)) ram_8bit_1st (
                    .addr (addr[ADDR_WIDTH - 2 : 0]),
                    .din (din [(i + 1) * 8 - 1 : i * 8]),
                    .write_en (write_en[i] & (~addr[ADDR_WIDTH - 1])),
                    .clk (clk),
                    .dout (dout_1st [(i + 1) * 8 - 1 : i * 8]));
            end
            
            for (i = 0; i < (DATA_WIDTH / 8); i = i + 1) begin : gen_for_proc_2nd
                
                 single_port_ram_8bit #(.ADDR_WIDTH (ADDR_WIDTH - 2)) ram_8bit_2nd (
                    .addr (addr[ADDR_WIDTH - 3 : 0]),
                    .din (din [(i + 1) * 8 - 1 : i * 8]),
                    .write_en (write_en[i] & (addr[ADDR_WIDTH - 1])),
                    .clk (clk),
                    .dout (dout_2nd [(i + 1) * 8 - 1 : i * 8]));
            end
            
            assign dout = addr_reg [ADDR_WIDTH - 1] ? dout_2nd : dout_1st;
        
        end else begin
        
            for (i = 0; i < (DATA_WIDTH / 8); i = i + 1) begin : gen_for_proc
                
                 single_port_ram_8bit #(.ADDR_WIDTH (ADDR_WIDTH)) ram_8bit (
                    .addr (addr),
                    .din (din [(i + 1) * 8 - 1 : i * 8]),
                    .write_en (write_en[i]),
                    .clk (clk),
                    .dout (dout [(i + 1) * 8 - 1 : i * 8]));
            end
        end
        
    endgenerate
    
                
endmodule
module dual_port_ram #(parameter ADDR_WIDTH = 5, DATA_WIDTH = 32) (
          input wire [ADDR_WIDTH - 1 : 0]       waddr, 
          input wire [ADDR_WIDTH - 1 : 0]       raddr,
          
          input wire [DATA_WIDTH - 1 : 0]       din,
          input wire                            write_en, 
          input wire                            clk, 
          output reg [DATA_WIDTH - 1 : 0]       dout
);

    //    reg [ADDR_WIDTH - 1 : 0] raddr_reg;
        reg [DATA_WIDTH - 1 : 0] mem [(2**ADDR_WIDTH) - 1 : 0] /* synthesis syn_ramstyle="M9K" */;

    //    assign dout = mem[raddr_reg] ;
        
    //    always @(posedge rclk) begin
    //        raddr_reg <= raddr;
    //    end
        
        always @(posedge clk) begin
            if (write_en) begin
                mem[waddr] <= din;
            end
            
            dout <= mem[raddr] ;
        end

endmodule
module SP256K (

    input wire [13:0] AD,
    input wire [15:0] DI,
    input wire [3:0] MASKWE,
    input wire WE,
    input wire CS,
    input wire CK,
    input wire STDBY,
    input wire SLEEP,
    input wire PWROFF_N,
    output wire [15:0] DO
);


    wire [13 : 0]         addr;
    wire [15 : 0]         din;
    wire [1 : 0]          write_en;
    wire                  clk;
    reg [15 : 0]          dout;
    
    assign clk = CK;
    assign DO = dout;
    assign addr = AD;
    assign din = DI;
    assign write_en = {WE & MASKWE [2], WE & MASKWE [0]};
    
    

    reg [15 : 0] mem [(1<<14)-1:0];
    genvar i;
    generate
        for (i = 0; i < 2; i = i + 1) begin : gen_proc
            always @(posedge clk) begin
                if (write_en[i]) begin
                    mem[(addr)][8 * (i + 1) - 1 : 8 * i] <= din[8 * (i + 1) - 1 : 8 * i];
                end
            end
        end
    endgenerate
 
    always @(posedge clk) begin
        dout <= mem[addr];
    end

endmodule
module single_port_ram_lattice #(parameter ADDR_WIDTH = 14, DATA_WIDTH = 16) (
            input  wire [ADDR_WIDTH - 1 : 0]         addr,
            input  wire [DATA_WIDTH - 1 : 0]         din,
            input  wire [DATA_WIDTH / 8 - 1 : 0]     write_en, 
            input  wire                              clk,
            output wire [DATA_WIDTH - 1 : 0]         dout
);

     single_port_ram_lattice_16Kx16 one_blk (
                .addr       (addr),
                .din        (din),
                .write_en   (write_en),
                .clk        (clk),
                .dout       (dout));
                
endmodule
module single_port_ram #(parameter ADDR_WIDTH = 14, DATA_WIDTH = 16) (
            input  wire [ADDR_WIDTH - 1 : 0]         addr,
            input  wire [DATA_WIDTH - 1 : 0]         din,
            input  wire [DATA_WIDTH / 8 - 1 : 0]     write_en, 
            input  wire                              clk,
            output wire [DATA_WIDTH - 1 : 0]         dout
);
    
    single_port_ram_lattice #(.ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH)) single_port_ram_lattice_i (
        .addr (addr),
        .din (din),
        .write_en (write_en),
        .clk (clk),
        .dout (dout));

                
endmodule
module dual_port_ram #(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) (
          input wire [ADDR_WIDTH - 1 : 0]       waddr, 
          input wire [ADDR_WIDTH - 1 : 0]       raddr,
          
          input wire [DATA_WIDTH - 1 : 0]       din,
          input wire                            write_en, 
          input wire                            clk, 
          output wire [DATA_WIDTH - 1 : 0]      dout
);


    dual_port_ram_lattice #(.ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH)) dual_port_ram_lattice_i (
            .waddr (waddr),
            .raddr (raddr),
            
            .din (din),
            .write_en (write_en),
            
            .wclk (clk),
            .rclk (clk),
            .dout (dout) );
            
endmodule
module single_port_ram_lattice_16Kx16 (
            input  wire [13 : 0]         addr,
            input  wire [15 : 0]         din,
            input  wire [1 : 0]          write_en, 
            input  wire                  clk,
            output wire [15 : 0]         dout
);

	SP256K spram_i (
	  .AD       (addr),  // I
	  .DI       (din),  // I
	  .MASKWE   ({write_en[1], write_en[1], write_en[0], write_en[0]}),  // I
	  .WE       (|write_en),  // I
	  .CS       (1'b1),  // I
	  .CK       (clk),  // I
	  .STDBY    (1'b0),  // I
	  .SLEEP    (1'b0),  // I
	  .PWROFF_N (1'b1),  // I
	  .DO       (dout)   // O
	);
endmodule
module dual_port_ram_lattice #(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) (
          input wire [ADDR_WIDTH - 1 : 0]       waddr, 
          input wire [ADDR_WIDTH - 1 : 0]       raddr,
          
          input wire [DATA_WIDTH - 1 : 0]       din,
          input wire                            write_en, 
          input wire                            wclk, 
          input wire                            rclk,
          output reg [DATA_WIDTH - 1 : 0]       dout
);

    reg [DATA_WIDTH - 1 : 0] mem [(1<<ADDR_WIDTH)-1:0];
    
    always @(posedge wclk)  begin// Write memory.
        if (write_en) begin
            mem[waddr] <= din; // Using write address bus.
        end
    end
   
    always @(posedge rclk) begin // Read memory.
        dout <= mem[raddr]; // Using read address bus.
    end
endmodule
module single_port_ram #(parameter ADDR_WIDTH = 12, DATA_WIDTH = 16) (
			input  wire                               clk,
            input  wire [ADDR_WIDTH - 1 : 0]         addr,
            input  wire [DATA_WIDTH - 1 : 0]         din,
            input  wire [DATA_WIDTH / 8 - 1 : 0]     write_en, 
            output reg  [DATA_WIDTH - 1 : 0]         dout
);

    reg [7 : 0] mem_hi [(1<<ADDR_WIDTH)-1:0];
	reg [7 : 0] mem_low [(1<<ADDR_WIDTH)-1:0];
	always @(posedge clk) begin
		if (write_en[0]) begin
			mem_low[addr] <= din[7 : 0];
		end
		if (write_en[1]) begin
			mem_hi[addr] <= din[15 : 8];
		end
	end
 
    always @(posedge clk) begin
        dout <= {mem_hi[addr], mem_low[addr]};
    end
                
endmodule
module absolute_value #(parameter DATA_WIDTH=32)(
      
//========== INPUT ==========

        input  wire signed [DATA_WIDTH - 1 : 0]  data_in,
            
        
//========== OUTPUT ==========
        output wire  signed [DATA_WIDTH - 1 : 0] data_out
        
//========== IN/OUT ==========
);
    wire signed [DATA_WIDTH - 1 : 0]    data_sign_ext, data_tmp;
    wire signed [DATA_WIDTH - 1 : 0]    abs_value;
    
    assign data_sign_ext = {(DATA_WIDTH){data_in[DATA_WIDTH - 1]}};
    assign data_tmp      = data_in ^ data_sign_ext;
    assign abs_value     = data_tmp - data_sign_ext;
    
    assign data_out = abs_value;
    
endmodule
module crc16_CCITT #(parameter INIT_VALUE = 16'hFFFF) (
        input wire                  clk,
        input wire                  reset_n,
        
        input wire                  sync_reset,
        
        input wire                  crc_en,
        input wire [7:0]   data_in,
        
        output wire [15:0] crc_out
);

    reg [15:0] lfsr_q,lfsr_c;

    assign crc_out = lfsr_q;

    always @(*) begin
        lfsr_c[0] = lfsr_q[8] ^ lfsr_q[12] ^ data_in[0] ^ data_in[4];
        lfsr_c[1] = lfsr_q[9] ^ lfsr_q[13] ^ data_in[1] ^ data_in[5];
        lfsr_c[2] = lfsr_q[10] ^ lfsr_q[14] ^ data_in[2] ^ data_in[6];
        lfsr_c[3] = lfsr_q[11] ^ lfsr_q[15] ^ data_in[3] ^ data_in[7];
        lfsr_c[4] = lfsr_q[12] ^ data_in[4];
        lfsr_c[5] = lfsr_q[8] ^ lfsr_q[12] ^ lfsr_q[13] ^ data_in[0] ^ data_in[4] ^ data_in[5];
        lfsr_c[6] = lfsr_q[9] ^ lfsr_q[13] ^ lfsr_q[14] ^ data_in[1] ^ data_in[5] ^ data_in[6];
        lfsr_c[7] = lfsr_q[10] ^ lfsr_q[14] ^ lfsr_q[15] ^ data_in[2] ^ data_in[6] ^ data_in[7];
        lfsr_c[8] = lfsr_q[0] ^ lfsr_q[11] ^ lfsr_q[15] ^ data_in[3] ^ data_in[7];
        lfsr_c[9] = lfsr_q[1] ^ lfsr_q[12] ^ data_in[4];
        lfsr_c[10] = lfsr_q[2] ^ lfsr_q[13] ^ data_in[5];
        lfsr_c[11] = lfsr_q[3] ^ lfsr_q[14] ^ data_in[6];
        lfsr_c[12] = lfsr_q[4] ^ lfsr_q[8] ^ lfsr_q[12] ^ lfsr_q[15] ^ data_in[0] ^ data_in[4] ^ data_in[7];
        lfsr_c[13] = lfsr_q[5] ^ lfsr_q[9] ^ lfsr_q[13] ^ data_in[1] ^ data_in[5];
        lfsr_c[14] = lfsr_q[6] ^ lfsr_q[10] ^ lfsr_q[14] ^ data_in[2] ^ data_in[6];
        lfsr_c[15] = lfsr_q[7] ^ lfsr_q[11] ^ lfsr_q[15] ^ data_in[3] ^ data_in[7];

    end // always

    always @(posedge clk, negedge reset_n) begin
        if(!reset_n) begin
            lfsr_q <= INIT_VALUE;
        end else if (sync_reset) begin
            lfsr_q <= INIT_VALUE;
        end else begin
            lfsr_q <= crc_en ? lfsr_c : lfsr_q;
        end
    end // always
    
endmodule // crc16_CCITT
module creative(
    // Inputs
    RXD,
    osc_in,
    // Outputs
    LED_GREEN,
    LED_RED,
    TXD
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input  RXD;
input  osc_in;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output LED_GREEN;
output LED_RED;
output TXD;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire   FCCC_0_GL0;
wire   FCCC_0_LOCK;
wire   LED_GREEN_net_0;
wire   LED_RED_net_0;
wire   osc_in;
wire   RXD;
wire   TXD_net_0;
wire   LED_GREEN_net_1;
wire   LED_RED_net_1;
wire   TXD_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire   GND_net;
wire   [7:2]PADDR_const_net_0;
wire   [7:0]PWDATA_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net            = 1'b0;
assign PADDR_const_net_0  = 6'h00;
assign PWDATA_const_net_0 = 8'h00;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign LED_GREEN_net_1 = LED_GREEN_net_0;
assign LED_GREEN       = LED_GREEN_net_1;
assign LED_RED_net_1   = LED_RED_net_0;
assign LED_RED         = LED_RED_net_1;
assign TXD_net_1       = TXD_net_0;
assign TXD             = TXD_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------creative_FCCC_0_FCCC   -   Actel:SgCore:FCCC:2.0.201
creative_FCCC_0_FCCC FCCC_0(
        // Inputs
        .CLK0_PAD ( osc_in ),
        // Outputs
        .GL0      ( FCCC_0_GL0 ),
        .LOCK     ( FCCC_0_LOCK ) 
        );

//--------Reindeer
Reindeer Reindeer_0(
        // Inputs
        .clk              ( FCCC_0_GL0 ),
        .reset_n          ( FCCC_0_LOCK ),
        .RXD              ( RXD ),
        // Outputs
        .TXD              ( TXD_net_0 ),
        .processor_active ( LED_GREEN_net_0 ),
        .processor_paused ( LED_RED_net_0 ) 
        );


endmodule
module creative_FCCC_0_FCCC(
       LOCK,
       CLK0_PAD,
       GL0
    );
output LOCK;
input  CLK0_PAD;
output GL0;

    wire gnd_net, vcc_net, CLK0_PAD_net, GL0_net;
    
    VCC vcc_inst (.Y(vcc_net));
    GND gnd_inst (.Y(gnd_net));
    CLKINT GL0_INST (.A(GL0_net), .Y(GL0));
    CCC #( .INIT(210'h0000007FA0000044974000318C6318C1F18C61C00404040401C09)
        , .VCOFREQUENCY(580.000) )  CCC_INST (.Y0(), .Y1(), .Y2(), .Y3(
        ), .PRDATA({nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7}), .LOCK(
        LOCK), .BUSY(), .CLK0(vcc_net), .CLK1(vcc_net), .CLK2(vcc_net), 
        .CLK3(vcc_net), .NGMUX0_SEL(gnd_net), .NGMUX1_SEL(gnd_net), 
        .NGMUX2_SEL(gnd_net), .NGMUX3_SEL(gnd_net), .NGMUX0_HOLD_N(
        vcc_net), .NGMUX1_HOLD_N(vcc_net), .NGMUX2_HOLD_N(vcc_net), 
        .NGMUX3_HOLD_N(vcc_net), .NGMUX0_ARST_N(vcc_net), 
        .NGMUX1_ARST_N(vcc_net), .NGMUX2_ARST_N(vcc_net), 
        .NGMUX3_ARST_N(vcc_net), .PLL_BYPASS_N(vcc_net), .PLL_ARST_N(
        vcc_net), .PLL_POWERDOWN_N(vcc_net), .GPD0_ARST_N(vcc_net), 
        .GPD1_ARST_N(vcc_net), .GPD2_ARST_N(vcc_net), .GPD3_ARST_N(
        vcc_net), .PRESET_N(gnd_net), .PCLK(vcc_net), .PSEL(vcc_net), 
        .PENABLE(vcc_net), .PWRITE(vcc_net), .PADDR({vcc_net, vcc_net, 
        vcc_net, vcc_net, vcc_net, vcc_net}), .PWDATA({vcc_net, 
        vcc_net, vcc_net, vcc_net, vcc_net, vcc_net, vcc_net, vcc_net})
        , .CLK0_PAD(CLK0_PAD_net), .CLK1_PAD(gnd_net), .CLK2_PAD(
        gnd_net), .CLK3_PAD(gnd_net), .GL0(GL0_net), .GL1(), .GL2(), 
        .GL3(), .RCOSC_25_50MHZ(gnd_net), .RCOSC_1MHZ(gnd_net), 
        .XTLOSC(gnd_net));
    INBUF CLK0_PAD_INST (.PAD(CLK0_PAD), .Y(CLK0_PAD_net));
    
endmodule
module ct_rtu_expand_8(
  x_num,
  x_num_expand
);

// &Ports; @25
input   [2:0]  x_num;       
output  [7:0]  x_num_expand; 

// &Regs; @26

// &Wires; @27
wire    [2:0]  x_num;       
wire    [7:0]  x_num_expand; 


//==========================================================
//       expand 3 bits number to 8 bits one-hot number
//==========================================================
assign x_num_expand[0] = (x_num[2:0] == 3'd0);
assign x_num_expand[1] = (x_num[2:0] == 3'd1);
assign x_num_expand[2] = (x_num[2:0] == 3'd2);
assign x_num_expand[3] = (x_num[2:0] == 3'd3);
assign x_num_expand[4] = (x_num[2:0] == 3'd4);
assign x_num_expand[5] = (x_num[2:0] == 3'd5);
assign x_num_expand[6] = (x_num[2:0] == 3'd6);
assign x_num_expand[7] = (x_num[2:0] == 3'd7);

// &ModuleEnd; @41
endmodule
module ct_rtu_encode_32(
  x_num,
  x_num_expand
);

// &Ports; @25
input   [31:0]  x_num_expand; 
output  [4 :0]  x_num;       

// &Regs; @26

// &Wires; @27
wire    [4 :0]  x_num;       
wire    [31:0]  x_num_expand; 


//==========================================================
//  encode 32 bits one-hot number to 5 bits binary number
//==========================================================
assign x_num[4:0] =
           {5{x_num_expand[0]}}  & 5'd0
         | {5{x_num_expand[1]}}  & 5'd1
         | {5{x_num_expand[2]}}  & 5'd2
         | {5{x_num_expand[3]}}  & 5'd3
         | {5{x_num_expand[4]}}  & 5'd4
         | {5{x_num_expand[5]}}  & 5'd5
         | {5{x_num_expand[6]}}  & 5'd6
         | {5{x_num_expand[7]}}  & 5'd7
         | {5{x_num_expand[8]}}  & 5'd8
         | {5{x_num_expand[9]}}  & 5'd9
         | {5{x_num_expand[10]}} & 5'd10
         | {5{x_num_expand[11]}} & 5'd11
         | {5{x_num_expand[12]}} & 5'd12
         | {5{x_num_expand[13]}} & 5'd13
         | {5{x_num_expand[14]}} & 5'd14
         | {5{x_num_expand[15]}} & 5'd15
         | {5{x_num_expand[16]}} & 5'd16
         | {5{x_num_expand[17]}} & 5'd17
         | {5{x_num_expand[18]}} & 5'd18
         | {5{x_num_expand[19]}} & 5'd19
         | {5{x_num_expand[20]}} & 5'd20
         | {5{x_num_expand[21]}} & 5'd21
         | {5{x_num_expand[22]}} & 5'd22
         | {5{x_num_expand[23]}} & 5'd23
         | {5{x_num_expand[24]}} & 5'd24
         | {5{x_num_expand[25]}} & 5'd25
         | {5{x_num_expand[26]}} & 5'd26
         | {5{x_num_expand[27]}} & 5'd27
         | {5{x_num_expand[28]}} & 5'd28
         | {5{x_num_expand[29]}} & 5'd29
         | {5{x_num_expand[30]}} & 5'd30
         | {5{x_num_expand[31]}} & 5'd31;

// &ModuleEnd; @66
endmodule
module ct_rtu_expand_32(
  x_num,
  x_num_expand
);

// &Ports; @25
input   [4 :0]  x_num;       
output  [31:0]  x_num_expand; 

// &Regs; @26

// &Wires; @27
wire    [4 :0]  x_num;       
wire    [31:0]  x_num_expand; 


//==========================================================
//       expand 5 bits number to 32 bits one-hot number
//==========================================================
assign x_num_expand[0]  = (x_num[4:0] == 5'd0);
assign x_num_expand[1]  = (x_num[4:0] == 5'd1);
assign x_num_expand[2]  = (x_num[4:0] == 5'd2);
assign x_num_expand[3]  = (x_num[4:0] == 5'd3);
assign x_num_expand[4]  = (x_num[4:0] == 5'd4);
assign x_num_expand[5]  = (x_num[4:0] == 5'd5);
assign x_num_expand[6]  = (x_num[4:0] == 5'd6);
assign x_num_expand[7]  = (x_num[4:0] == 5'd7);
assign x_num_expand[8]  = (x_num[4:0] == 5'd8);
assign x_num_expand[9]  = (x_num[4:0] == 5'd9);
assign x_num_expand[10] = (x_num[4:0] == 5'd10);
assign x_num_expand[11] = (x_num[4:0] == 5'd11);
assign x_num_expand[12] = (x_num[4:0] == 5'd12);
assign x_num_expand[13] = (x_num[4:0] == 5'd13);
assign x_num_expand[14] = (x_num[4:0] == 5'd14);
assign x_num_expand[15] = (x_num[4:0] == 5'd15);
assign x_num_expand[16] = (x_num[4:0] == 5'd16);
assign x_num_expand[17] = (x_num[4:0] == 5'd17);
assign x_num_expand[18] = (x_num[4:0] == 5'd18);
assign x_num_expand[19] = (x_num[4:0] == 5'd19);
assign x_num_expand[20] = (x_num[4:0] == 5'd20);
assign x_num_expand[21] = (x_num[4:0] == 5'd21);
assign x_num_expand[22] = (x_num[4:0] == 5'd22);
assign x_num_expand[23] = (x_num[4:0] == 5'd23);
assign x_num_expand[24] = (x_num[4:0] == 5'd24);
assign x_num_expand[25] = (x_num[4:0] == 5'd25);
assign x_num_expand[26] = (x_num[4:0] == 5'd26);
assign x_num_expand[27] = (x_num[4:0] == 5'd27);
assign x_num_expand[28] = (x_num[4:0] == 5'd28);
assign x_num_expand[29] = (x_num[4:0] == 5'd29);
assign x_num_expand[30] = (x_num[4:0] == 5'd30);
assign x_num_expand[31] = (x_num[4:0] == 5'd31);

// &ModuleEnd; @65
endmodule