dakies/OSS_Verilog huggingface dataset:
module umi_arbiter
  #(parameter N      = 4,         // number of inputs
    parameter TARGET = "DEFAULT"  // SIM, ASIC, FPGA, ...
    )
   (// controls
    input              clk,
    input              nreset,
    input [1:0]        mode, // [00]=priority,[01]=roundrobin,[1x]=reserved
    input [N-1:0]      mask, // 1 = disable request, 0 = enable request
    input [N-1:0]      requests, // incoming requests
    output reg [N-1:0] grants  // outgoing grants
    );

   wire                collision;
   reg [N-1:0]         thermometer;
   wire [N-1:0]        spec_requests[0:N-1];
   wire [N-1:0]        spec_grants[0:N-1];
   genvar              i;

   // Thermometer mask that gets hotter with every collision
   // wraps to zero when all ones
   generate if (N > 1)
     begin
        always @ (posedge clk or negedge nreset)
          if (~nreset)
            thermometer[N-1:0] <= {N{1'b0}};
          else if(collision & (mode[1:0]==2'b10))
            thermometer[N-1:0] <= (&thermometer[N-2:0]) ? {N{1'b0}} : {thermometer[N-2:0],1'b1};
     end
   else
     begin
        always @ (posedge clk or negedge nreset)
          if (~nreset)
            thermometer[N-1:0] <= {N{1'b0}};
          else
            thermometer[N-1:0] <= {N{1'b0}};
     end
   endgenerate

   // 1. Create N rotated set of requests
   // 2. Feed requests into fixed priority encoders
   for (i=0;i<N;i=i+1)
     begin
        // double width needed for rotation
        assign spec_requests[i] = ~mask[N-1:0] &
                                  ~thermometer[N-1:0] &
                                   requests[N-1:0];

        // Priority Selection Using Masked Inputs
        umi_priority #(.N(N))
        umi_prioroty(// Outputs
                     .grants   (spec_grants[i][N-1:0]),
                     // Inputs
                     .requests (spec_requests[i][N-1:0]));
     end

   // Or together all grants
   always @*
     begin : imux
        integer    k;
        grants[N-1:0] = 'b0;
        for(k=0;k<N;k=k+1)
          grants[N-1:0] = grants[N-1:0] | spec_grants[k][N-1:0];
     end

   // Detect collision on pushback
   assign collision = |(requests[N-1:0] & ~grants[N-1:0]);

`ifdef VERILATOR
   assert property (@(posedge clk) $onehot0(grants));
`endif

endmodule
module umi_isolate
  #(parameter CW = 32, // umi command width
    parameter AW = 64, // umi address width
    parameter DW = 64, // umi data width
    parameter ISO = 0  // 1 = enable input isolation
    )
   (
    input           isolate,  // 1=clamp inputs to 0
    // floating signals
    input           umi_ready,
    input           umi_valid,
    input [CW-1:0]  umi_cmd,
    input [AW-1:0]  umi_dstaddr,
    input [AW-1:0]  umi_srcaddr,
    input [DW-1:0]  umi_data,
    // clamped signals
    output          umi_ready_iso,
    output          umi_valid_iso,
    output [CW-1:0] umi_cmd_iso,
    output [AW-1:0] umi_dstaddr_iso,
    output [AW-1:0] umi_srcaddr_iso,
    output [DW-1:0] umi_data_iso
    );

   generate
      if(ISO)
        begin : g0
           la_visolo #(.N(1))
           i_ready (.in(umi_ready),
                    .out(umi_ready_iso),
                    .iso(isolate));

           la_visolo #(.N(1))
           i_valid (.in(umi_valid),
                    .out(umi_valid_iso),
                    .iso(isolate));

           la_visolo #(.N(CW))
           i_cmd (.in(umi_cmd[CW-1:0]),
                  .out(umi_cmd_iso[CW-1:0]),
                  .iso(isolate));

           la_visolo #(.N(AW))
           i_dstaddr (.in(umi_dstaddr[AW-1:0]),
                      .out(umi_dstaddr_iso[AW-1:0]),
                      .iso(isolate));

           la_visolo #(.N(AW))
           i_srcaddr (.in(umi_srcaddr[AW-1:0]),
                      .out(umi_srcaddr_iso[AW-1:0]),
                      .iso(isolate));

           la_visolo #(.N(DW))
           i_data (.in(umi_srcaddr[DW-1:0]),
                   .out(umi_srcaddr_iso[DW-1:0]),
                   .iso(isolate));
        end
      else
        begin : g0
           assign umi_ready_iso           = umi_ready;
           assign umi_valid_iso           = umi_valid;
           assign umi_cmd_iso[CW-1:0]     = umi_cmd[CW-1:0];
           assign umi_dstaddr_iso[AW-1:0] = umi_dstaddr[AW-1:0];
           assign umi_srcaddr_iso[AW-1:0] = umi_srcaddr[AW-1:0];
           assign umi_data_iso[DW-1:0]    = umi_data[DW-1:0];
        end

   endgenerate

endmodule
module umi_mux
  #(parameter DW = 256, // UMI transaction width
    parameter CW = 32,
    parameter AW = 64,
    parameter N = 4     // number of inputs
    )
   (// Incoming UMI
    input [N-1:0]    umi_in_valid,
    input [N*CW-1:0] umi_in_cmd,
    input [N*AW-1:0] umi_in_dstaddr,
    input [N*AW-1:0] umi_in_srcaddr,
    input [N*DW-1:0] umi_in_data,
    output [N-1:0]   umi_in_ready,
    // Outgoing UMI
    output           umi_out_valid,
    input            umi_out_ready,
    output [CW-1:0]  umi_out_cmd,
    output [AW-1:0]  umi_out_dstaddr,
    output [AW-1:0]  umi_out_srcaddr,
    output [DW-1:0]  umi_out_data
    );

   // valid output
   assign umi_out_valid = |umi_in_valid[N-1:0];

   // ready pusback
   assign umi_in_ready[N-1:0] = {N{umi_out_ready}};

   // packet mux
   la_vmux #(.N(N),
             .W(CW))
   la_cmd_vmux(.out (umi_out_cmd[CW-1:0]),
               .sel (umi_in_valid[N-1:0]),
               .in  (umi_in_cmd[N*CW-1:0]));

   // packet mux
   la_vmux #(.N(N),
             .W(AW))
   la_dstaddr_vmux(.out (umi_out_dstaddr[AW-1:0]),
                   .sel (umi_in_valid[N-1:0]),
                   .in  (umi_in_dstaddr[N*AW-1:0]));

   // packet mux
   la_vmux #(.N(N),
             .W(AW))
   la_srcaddr_vmux(.out (umi_out_srcaddr[AW-1:0]),
                   .sel (umi_in_valid[N-1:0]),
                   .in  (umi_in_srcaddr[N*AW-1:0]));

   // packet mux
   la_vmux #(.N(N),
             .W(DW))
   la_data_vmux(.out (umi_out_data[DW-1:0]),
                .sel (umi_in_valid[N-1:0]),
                .in  (umi_in_data[N*DW-1:0]));

endmodule
module soc_fpga_ram(
  PortAClk,
  PortAAddr,
  PortADataIn,
  PortAWriteEnable,

  PortADataOut
);

parameter  DATAWIDTH = 2;
parameter  ADDRWIDTH = 2;

input                     PortAClk;
input   [(ADDRWIDTH-1):0] PortAAddr;
input   [(DATAWIDTH-1):0] PortADataIn;
input                     PortAWriteEnable;

output  [(DATAWIDTH-1):0] PortADataOut; 

parameter  MEMDEPTH = 2**(ADDRWIDTH);

reg [(DATAWIDTH-1):0] mem [(MEMDEPTH-1):0];
reg [(DATAWIDTH-1):0] PortADataOut;

always @(posedge PortAClk)
begin
  if(PortAWriteEnable)
  begin
    mem[PortAAddr]  <= PortADataIn;
  end
  else
  begin
    PortADataOut    <= mem[PortAAddr];
  end
end

endmodule
module counter(
  interrupt,
  pclk,
  presetn,
  timer_current_value,
  timer_enable,
  timer_load_count,
  timer_mode
);

// &Ports; @24
input           pclk;               
input           presetn;            
input           timer_enable;       
input   [31:0]  timer_load_count;   
input           timer_mode;         
output          interrupt;          
output  [31:0]  timer_current_value; 

// &Regs; @25
reg     [31:0]  counter;            
reg             interrupt;          
reg             timer_enable_flop;  

// &Wires; @26
wire            load_cnt_en;        
wire            pclk;               
wire            presetn;            
wire    [31:0]  timer_current_value; 
wire            timer_enable;       
wire    [31:0]  timer_load_count;   
wire            timer_mode;         


//==========================================================
//                 Counter
//==========================================================
always @(posedge pclk or negedge presetn)
begin
  if(!presetn)
  begin
      timer_enable_flop <=0;
  end
  else
  begin
      timer_enable_flop <=timer_enable ;
  end
end

assign load_cnt_en= (timer_enable && !timer_enable_flop)
                    || !(|counter[31:0]);

always @(posedge pclk or negedge presetn)
begin
  if(!presetn)
  begin
      counter[31:0] <=32'hffffffff;
  end
  else if(load_cnt_en)
  begin
    if(timer_mode)
    begin
      counter[31:0]<=timer_load_count[31:0];
    end
    else 
    begin
      counter[31:0]<=32'hffffffff;
    end
  end
  else if (timer_enable)
  begin
    counter[31:0]<=counter[31:0]-1'b1;
  end
  else
  begin
    counter[31:0]<=counter[31:0];
  end
end

assign timer_current_value[31:0]=counter[31:0];
//==========================================================
//                Interrupt sigals 
//==========================================================
//internel interrupt
always @(posedge pclk or negedge presetn)
begin
  if(!presetn)
  begin
    interrupt <=1'b0;
  end
  else if(!{|counter[31:0]})
  begin
    interrupt <=1'b1;
  end
  else
  begin
    interrupt<=1'b0 ;
  end
end

// &ModuleEnd; @94
endmodule
module wic(
  awake_data,
  awake_disable,
  awake_enable,
  int_cfg,
  int_exit,
  int_pending,
  int_vld,
  pad_cpu_rst_b,
  pending_clr,
  wic_awake_en,
  wic_clk
);

// &Ports; @29
input        awake_data;   
input        awake_disable; 
input        awake_enable; 
input        int_cfg;      
input        int_exit;     
input        int_vld;      
input        pad_cpu_rst_b; 
input        pending_clr;  
input        wic_clk;      
output       int_pending;  
output       wic_awake_en; 

// &Regs; @30
reg          int_pending;  
reg          int_vld_ff;   
reg          wic_awake_en; 

// &Wires; @31
wire         awake_data;   
wire         awake_disable; 
wire         awake_enable; 
wire         int_cfg;      
wire         int_exit;     
wire         int_level;    
wire         int_pulse;    
wire         int_vld;      
wire         pad_cpu_rst_b; 
wire         pending_clr;  
wire         wic_clk;      


//always@(posedge wic_clk or negedge pad_cpu_rst_b)
//begin
//  if (!pad_cpu_rst_b)
//    pending_ctrl_ff <= 1'b0;
//  else 
//    pending_ctrl_ff <= pending_ctrl;
//end

 
always@(posedge wic_clk or negedge pad_cpu_rst_b)
begin
  if (!pad_cpu_rst_b)
    wic_awake_en <= 1'b0;
  else if (awake_enable && awake_data)
    wic_awake_en <= 1'b1;
  else if (awake_disable && awake_data)
    wic_awake_en <= 1'b0;
end
//------------------------------------------------
//   sample level-sensitive interrupt
//------------------------------------------------

assign int_level = int_vld && !int_cfg && int_exit; 

//------------------------------------------------
//   sample pulse-sensitive interrupt
//------------------------------------------------
always@(posedge wic_clk or negedge pad_cpu_rst_b)
begin
  if (!pad_cpu_rst_b)
    int_vld_ff <= 1'b0;
  else 
    int_vld_ff <= int_vld;
end

assign int_pulse = int_vld && !int_vld_ff;

//------------------------------------------------
//        int  pending
//------------------------------------------------
always@(posedge wic_clk or negedge pad_cpu_rst_b)
begin
  if(!pad_cpu_rst_b)
    int_pending <= 1'b0;
  else if (!int_cfg)
    int_pending <= int_level;
  else if (pending_clr)
    int_pending <= 1'b0;
  else if(int_cfg)
    int_pending <= int_pulse;
end
// &ModuleEnd; @98
endmodule
module smpu_comp_hit(
  biu_pad_haddr,
  biu_pad_hprot,
  smpu_entry,
  smpu_entry0,
  smpu_hit,
  smpu_hsec
);

// &Ports; @20
input   [31:0]  biu_pad_haddr; 
input   [3 :0]  biu_pad_hprot; 
input   [31:0]  smpu_entry;   
input   [31:0]  smpu_entry0;  
output          smpu_hit;     
output          smpu_hsec;    

// &Regs; @21
reg     [22:0]  addr_mask;    

// &Wires; @22
wire            addr_match;   
wire    [31:0]  biu_pad_haddr; 
wire    [3 :0]  biu_pad_hprot; 
wire    [31:0]  smpu_entry;   
wire    [31:0]  smpu_entry0;  
wire            smpu_hit;     
wire            smpu_hsec;    



// &Force("bus", "biu_pad_haddr", 31, 0); @25
// &Force("bus", "biu_pad_hprot", 3, 0); @26

assign smpu_hit =1'b0;
// &Force("nonport", "addr_match"); @32

assign addr_match = {(smpu_entry[0] & !biu_pad_hprot[2]), 
                     (addr_mask[22:0] & biu_pad_haddr[31:9])}
                 ==  { 1'b1, smpu_entry[31:9]};

assign smpu_hsec  = {(smpu_entry0[0] & biu_pad_hprot[2]), 
                     (addr_mask[22:0] & biu_pad_haddr[31:9])}
                 ==  { 1'b1, smpu_entry0[31:9]};

//Generate the address mask for the addr 
// &CombBeg; @44
always @( smpu_entry[4:1])
begin
  case(smpu_entry[4:1])
    4'b0111 : addr_mask[22:0] = 23'h7f_ffff;
    4'b1000 : addr_mask[22:0] = 23'h7f_fffe;
    4'b1001 : addr_mask[22:0] = 23'h7f_fffc;
    default : addr_mask[22:0] = 23'h00_0000;
  endcase
// &CombEnd; @51
end


// &ModuleEnd; @54
endmodule
module sync(
  fast_clk,
  in,
  out,
  pad_cpu_rst_b,
  slow_clk
);

// &Ports; @21
input        fast_clk;     
input        in;           
input        pad_cpu_rst_b; 
input        slow_clk;     
output       out;          

// &Regs; @22
reg          input_lv;     
reg          reg_clr;      

// &Wires; @23
wire         fast_clk;     
wire         in;           
wire         input_vld;    
wire         out;          
wire         pad_cpu_rst_b; 
wire         slow_clk;     




assign input_vld = in ;


always@(posedge fast_clk or negedge pad_cpu_rst_b )
begin
  if (!pad_cpu_rst_b)
    input_lv <= 1'b0;
  else if (input_vld)
    input_lv <= 1'b1;
  else if (reg_clr)
    input_lv <= 1'b0;
end

always@(posedge slow_clk or negedge pad_cpu_rst_b )
begin
  if (!pad_cpu_rst_b)
    reg_clr <= 1'b0;
  else 
    reg_clr <= 1'b1;
end


assign out = input_lv;
// &ModuleEnd; @50
endmodule
module err_gen(
  haddr_s3,
  hburst_s3,
  hmastlock,
  hprot_s3,
  hrdata_s3,
  hready_s3,
  hresp_s3,
  hsel_s3,
  hsize_s3,
  htrans_s3,
  hwdata_s3,
  hwrite_s3,
  pad_cpu_rst_b,
  pll_core_cpuclk
);

// &Ports; @23
input   [31:0]  haddr_s3;       
input   [2 :0]  hburst_s3;      
input           hmastlock;      
input   [3 :0]  hprot_s3;       
input           hsel_s3;        
input   [2 :0]  hsize_s3;       
input   [1 :0]  htrans_s3;      
input   [31:0]  hwdata_s3;      
input           hwrite_s3;      
input           pad_cpu_rst_b;  
input           pll_core_cpuclk; 
output  [31:0]  hrdata_s3;      
output          hready_s3;      
output  [1 :0]  hresp_s3;       

// &Regs; @24
reg             hready_s3;      

// &Wires; @25
wire    [31:0]  hrdata_s3;      
wire    [1 :0]  hresp_s3;       
wire            hsel_s3;        
wire            pad_cpu_rst_b;  
wire            pll_core_cpuclk; 

// //&Force("input","pll_core_cpuclk"); @26
// //&Force("input","pad_cpu_rst_b"); @27
// &Force("input","hsel_s3"); @28
// &Force("input","haddr_s3"); @29
// &Force("bus", "haddr_s3", 31,0); @30
// &Force("input","hburst_s3"); @31
// &Force("bus", "hburst_s3", 2,0); @32
// &Force("input","hmastlock"); @33
// &Force("input","hprot_s3"); @34
// &Force("bus", "hprot_s3", 3,0); @35
// &Force("input","hsize_s3"); @36
// &Force("bus", "hsize_s3", 2,0); @37
// &Force("input","htrans_s3"); @38
// &Force("bus", "htrans_s3", 1,0); @39
// &Force("input","hwdata_s3"); @40
// &Force("input","hwrite_s3"); @41
// &Force("input","hsel_s3"); @42
// &Force("output","hready_s3"); @43
//assign hready_s3 = 1'b1;
assign hresp_s3[1:0]  =  2'b01 ;

always @(posedge pll_core_cpuclk or negedge pad_cpu_rst_b)
begin
  if(!pad_cpu_rst_b)
    begin
      hready_s3 <= 1'b0;
    end
  else if(hsel_s3)
    begin
      hready_s3 <= 1'b0;
    end
  else
    begin
      hready_s3 <= 1'b1;     
    end
end

// &Force("bus", "hwdata_s3", 31,0); @63
assign hrdata_s3[31:0] = 32'b0;

// &ModuleEnd; @66
endmodule
module fpga_clk_gen(
  clk_en,
  clkrst_b,
  cpu_clk,
  gate_en0,
  gate_en1,
  pad_clk,
  penable,
  per_clk,
  pmu_clk,
  prdata,
  psel,
  pwdata,
  pwrite,
  wic_clk
);

// &Ports; @20
input           clkrst_b;      
input           gate_en0;      
input           gate_en1;      
input           pad_clk;       
input           penable;       
input           psel;          
input   [2 :0]  pwdata;        
input           pwrite;        
output          clk_en;        
output          cpu_clk;       
output          per_clk;       
output          pmu_clk;       
output  [31:0]  prdata;        
output          wic_clk;       

// &Regs; @21
reg     [2 :0]  input_clkratio; 
reg     [31:0]  prdata;        

// &Wires; @22
wire            clk_en;        
wire            clkrst_b;      
wire            cpu_clk;       
wire            pad_clk;       
wire            penable;       
wire            per_clk;       
wire            pmu_clk;       
wire            psel;          
wire    [2 :0]  pwdata;        
wire            pwrite;        
wire            wic_clk;       


always@(posedge per_clk or negedge clkrst_b)
begin
  if (!clkrst_b)
    input_clkratio[2:0] <= 3'b0;
  else if(psel && pwrite && penable)
    input_clkratio[2:0] <= pwdata[2:0]; 
end

// &CombBeg; @32
always @( psel
       or pwrite)
begin
if(psel && !pwrite)
begin
  prdata[31:0] <= 32'b0;
end
// &CombEnd; @37
end

assign cpu_clk = pad_clk; 
assign wic_clk = pad_clk;
assign per_clk = pad_clk;
assign pmu_clk = pad_clk;

assign clk_en = 1'b1;
// &Force("output","per_clk"); @45


// &Force("input", "gate_en0"); @48
// &Force("input", "gate_en1"); @49
// &Force("nonport", "input_clkratio"); @50

// &ModuleEnd; @52
endmodule
module px_had_sync(
  clk1,
  clk2,
  rst1_b,
  rst2_b,
  sync_in,
  sync_out
);

// &Ports; @22
input        clk1;         
input        clk2;         
input        rst1_b;       
input        rst2_b;       
input        sync_in;      
output       sync_out;     

// &Regs; @23
reg          sync_ff1_clk1; 
reg          sync_ff2_clk1; 
reg          sync_ff3_clk1; 
reg          sync_ff_clk2; 

// &Wires; @24
wire         clk1;         
wire         clk2;         
wire         rst1_b;       
wire         rst2_b;       
wire         sync_in;      
wire         sync_out;     

  

//==============================================================================
// sync logic from clk2 to clk1
// step 1. flop once in clk2 domain
// step 2. flop twice in clk1 domain
// result: a pulse signal in clk1 domain
// constraint: slow clock --> fast clock
//==============================================================================

always @(posedge clk2 or negedge rst2_b)
begin
  if (!rst2_b)
    sync_ff_clk2 <= 1'b0;
  else
    sync_ff_clk2 <= sync_in;
end

always @(posedge clk1 or negedge rst1_b)
begin
  if (!rst1_b) begin
    sync_ff1_clk1 <= 1'b0;
    sync_ff2_clk1 <= 1'b0;
  end
  else begin
    sync_ff1_clk1 <= sync_ff_clk2;
    sync_ff2_clk1 <= sync_ff1_clk1;
  end   
end

// generates a pulse signal in clk1 domain
always @(posedge clk1 or negedge rst1_b)
begin
  if (!rst1_b)
    sync_ff3_clk1 <= 1'b0;
  else
    sync_ff3_clk1 <= sync_ff2_clk1;
end

assign sync_out = !sync_ff3_clk1 && sync_ff2_clk1;

// &ModuleEnd;  @66
endmodule
module ahb_fifo_counter(
  counter_done,
  counter_en,
  counter_load,
  cpu_clk,
  cpu_rst_b
);

// &Ports; @20
input           counter_en;   
input   [31:0]  counter_load; 
input           cpu_clk;      
input           cpu_rst_b;    
output          counter_done; 

// &Regs; @21
reg     [31:0]  counter;      
reg             counter_en_ff; 

// &Wires; @22
wire            counter_done; 
wire            counter_en;   
wire    [31:0]  counter_load; 
wire            cpu_clk;      
wire            cpu_rst_b;    
wire            load_cnt_en;  


always @(posedge cpu_clk or negedge cpu_rst_b)
begin
  if(!cpu_rst_b)
  begin
    counter_en_ff <= 1'b0;
  end
  else
  begin
    counter_en_ff <=counter_en ;
  end
end

assign load_cnt_en= (counter_en && !counter_en_ff);
                   /// || !(|counter[31:0]);

always @(posedge cpu_clk or negedge cpu_rst_b)
begin
  if(!cpu_rst_b)
  begin
    counter[31:0] <= 32'h0;
  end
  else if (load_cnt_en)
  begin
    counter[31:0] <= counter_load[31:0];
  end
  else if (counter_done)
    counter[31:0] <= 32'b0;
  else 
    counter[31:0] <= counter[31:0] -1'b1;
 end

assign counter_done = (counter[31:0] == 32'b0) ;
// &Force("output","counter_done"); @56
// &ModuleEnd; @57
endmodule
module ahb_fifo_entry(
  create_en,
  data_in,
  data_out,
  entry_clk,
  entry_rst_b
);

// &Ports; @20
input           create_en;  
input   [54:0]  data_in;    
input           entry_clk;  
input           entry_rst_b; 
output  [54:0]  data_out;   

// &Regs; @21
reg     [54:0]  data_out;   

// &Wires; @22
wire            create_en;  
wire    [54:0]  data_in;    
wire            entry_clk;  
wire            entry_rst_b; 


always @(posedge entry_clk or negedge entry_rst_b)
begin
  if (!entry_rst_b)
    data_out[54:0] <= 54'b0;
  else if (create_en)
    data_out[54:0] <= data_in[54:0];
  else
    data_out[54:0] <= data_out[54:0];
end

// &Force("output","data_out"); @34




// &ModuleEnd; @39
endmodule
module e906_mem_test_tb();

wire  bht_mem_test_pass;



initial
begin
  #100000;
  if(bht_mem_test_pass)
  begin
    $display("*************************************************\n");
    $display("*************BHT MEMORY TEST PASS!!!*************\n");
    $display("*************************************************\n");
  end
  else begin
    $display("*************************************************\n");
    $display("*************BHT MEMORY TEST FAIL!!!*************\n");
    $display("*************************************************\n");
    $display("*************************************************\n");
    $display("**********SORRY!!! MEMORY TEST FAIL!!!***********\n");
    $display("*************************************************\n");
    $finish;
  end

end

e906_bht_mem_test    x_bht_mem_test   (.bht_mem_test_pass(bht_mem_test_pass));

initial
begin
  $dumpfile("test.vcd");
  $dumpvars;
end

endmodule
module pa_fpu_src_type(
  inst_double,
  inst_single,
  src_cnan,
  src_id,
  src_in,
  src_inf,
  src_norm,
  src_qnan,
  src_snan,
  src_zero
);

// &Ports; @25
input           inst_double;  
input           inst_single;  
input   [63:0]  src_in;       
output          src_cnan;     
output          src_id;       
output          src_inf;      
output          src_norm;     
output          src_qnan;     
output          src_snan;     
output          src_zero;     

// &Regs; @26

// &Wires; @27
wire            inst_double;  
wire            inst_single;  
wire    [63:0]  src;          
wire            src_cnan;     
wire            src_expn_max; 
wire            src_expn_zero; 
wire            src_frac_msb; 
wire            src_frac_zero; 
wire            src_id;       
wire    [63:0]  src_in;       
wire            src_inf;      
wire            src_norm;     
wire            src_qnan;     
wire            src_snan;     
wire            src_zero;     


// &Depend("cpu_cfig.h"); @29
assign src[63:0] = src_in[63:0];

assign src_cnan  = !(&src[63:32]) && inst_single;

assign src_expn_zero = !(|src[62:52]) && inst_double ||
                       !(|src[30:23]) && inst_single;

assign src_expn_max  =  (&src[62:52]) && inst_double ||
                        (&src[30:23]) && inst_single;

assign src_frac_zero = !(|src[51:0]) && inst_double ||
                       !(|src[22:0]) && inst_single;

assign src_frac_msb  = src[51] && inst_double || src[22] && inst_single;

assign src_snan = src_expn_max  && !src_frac_msb && !src_frac_zero && !src_cnan;
assign src_qnan = src_expn_max  &&  src_frac_msb || src_cnan;
assign src_zero = src_expn_zero &&  src_frac_zero && !src_cnan;
assign src_id   = src_expn_zero && !src_frac_zero && !src_cnan;
assign src_inf  = src_expn_max  &&  src_frac_zero && !src_cnan;
assign src_norm =!(src_expn_zero && src_frac_zero) &&
                 ! src_expn_max  && !src_cnan;

// &Force("output","src_cnan"); @53

// &ModuleEnd; @55
endmodule
module pa_clk_top(
  clk_en,
  clk_en_f,
  forever_cpuclk,
  pll_core_cpuclk
);

// &Ports; @24
input        clk_en;         
input        pll_core_cpuclk; 
output       clk_en_f;       
output       forever_cpuclk; 

// &Regs; @25
reg          clk_en_f;       

// &Wires; @26
wire         clk_en;         
wire         forever_cpuclk; 
wire         pll_core_cpuclk; 


//assign forever_jtgclk = pad_had_jtg_tclk;
assign forever_cpuclk = pll_core_cpuclk;
// &Force("output","forever_cpuclk"); @30
// &Force("output", "axim_clk_en_f"); @32
always@(posedge forever_cpuclk)
begin
  clk_en_f <= clk_en;
end


// &ModuleEnd; @65
endmodule
module pa_clkrst_top(
  clk_en,
  clk_en_f,
  cpurst_b,
  forever_cpuclk,
  pad_cpu_rst_b,
  pad_yy_scan_mode,
  pad_yy_scan_rst_b,
  pll_core_cpuclk,
  sync_sys_apb_rst_b,
  sys_apb_clk,
  sys_apb_rst_b
);

// &Ports; @23
input        clk_en;            
input        pad_cpu_rst_b;     
input        pad_yy_scan_mode;  
input        pad_yy_scan_rst_b; 
input        pll_core_cpuclk;   
input        sys_apb_clk;       
input        sys_apb_rst_b;     
output       clk_en_f;          
output       cpurst_b;          
output       forever_cpuclk;    
output       sync_sys_apb_rst_b; 

// &Regs; @24

// &Wires; @25
wire         clk_en;            
wire         clk_en_f;          
wire         cpurst_b;          
wire         forever_cpuclk;    
wire         pad_cpu_rst_b;     
wire         pad_yy_scan_mode;  
wire         pad_yy_scan_rst_b; 
wire         pll_core_cpuclk;   
wire         sync_sys_apb_rst_b; 
wire         sys_apb_clk;       
wire         sys_apb_rst_b;     


// &Force("output", "forever_cpuclk"); @27

//----------------------------------------------------------
// clock top
//----------------------------------------------------------
// &Instance("pa_clk_top"); @32
pa_clk_top  x_pa_clk_top (
  .clk_en          (clk_en         ),
  .clk_en_f        (clk_en_f       ),
  .forever_cpuclk  (forever_cpuclk ),
  .pll_core_cpuclk (pll_core_cpuclk)
);


//----------------------------------------------------------
// reset top
//----------------------------------------------------------
// &Instance("pa_rst_top"); @37
pa_rst_top  x_pa_rst_top (
  .cpurst_b           (cpurst_b          ),
  .forever_cpuclk     (forever_cpuclk    ),
  .pad_cpu_rst_b      (pad_cpu_rst_b     ),
  .pad_yy_scan_mode   (pad_yy_scan_mode  ),
  .pad_yy_scan_rst_b  (pad_yy_scan_rst_b ),
  .sync_sys_apb_rst_b (sync_sys_apb_rst_b),
  .sys_apb_clk        (sys_apb_clk       ),
  .sys_apb_rst_b      (sys_apb_rst_b     )
);

// &ModuleEnd; @38
endmodule
module pa_dtu_cdc_pulse(
  dst_clk,
  dst_pulse,
  dst_rst_b,
  src_clk,
  src_pulse,
  src_rst_b
);

// &Ports; @21
input        dst_clk;      
input        dst_rst_b;    
input        src_clk;      
input        src_pulse;    
input        src_rst_b;    
output       dst_pulse;    

// &Regs; @22
reg          dst_sync1;    
reg          dst_sync2;    
reg          dst_sync3;    
reg          dst_sync4;    
reg          src_lvl;      
reg          src_sync1;    
reg          src_sync2;    
reg          src_sync3;    
reg          src_sync4;    

// &Wires; @23
wire         clear_src_lvl; 
wire         dst_clk;      
wire         dst_pulse;    
wire         dst_rst_b;    
wire         src_clk;      
wire         src_pulse;    
wire         src_rst_b;    


always @(posedge src_clk or negedge src_rst_b)
begin
  if(!src_rst_b)
    src_lvl <= 1'b0;
  else if(src_pulse)
    src_lvl <= 1'b1;
  else if(clear_src_lvl)
    src_lvl <= 1'b0;
end

always @(posedge dst_clk or negedge dst_rst_b)
begin
  if(!dst_rst_b)
    begin
      dst_sync1 <= 1'b0;
      dst_sync2 <= 1'b0;
      dst_sync3 <= 1'b0;
      dst_sync4 <= 1'b0;
    end
  else
    begin
      dst_sync1 <= src_lvl;
      dst_sync2 <= dst_sync1;
      dst_sync3 <= dst_sync2;
      dst_sync4 <= dst_sync3;
    end
end

always @(posedge src_clk or negedge src_rst_b)
begin
  if(!src_rst_b)
    begin
      src_sync1 <= 1'b0;
      src_sync2 <= 1'b0;
      src_sync3 <= 1'b0;
      src_sync4 <= 1'b0;
    end
  else
    begin
      src_sync1 <= dst_sync3;
      src_sync2 <= src_sync1;
      src_sync3 <= src_sync2;
      src_sync4 <= src_sync3;
    end
end
assign clear_src_lvl = src_sync3 && !src_sync4;

assign dst_pulse = dst_sync3 && !dst_sync4;

// &ModuleEnd; @74
endmodule
module pa_dtu_cdc_lvl(
  clk,
  dst_lvl,
  rst_b,
  src_lvl
);

// &Ports; @21
input        clk;    
input        rst_b;  
input        src_lvl; 
output       dst_lvl; 

// &Regs; @22
reg          sync1;  
reg          sync2;  
reg          sync3;  

// &Wires; @23
wire         clk;    
wire         dst_lvl; 
wire         rst_b;  
wire         src_lvl; 


always @(posedge clk or negedge rst_b)
begin
  if(!rst_b)
    begin
      sync1 <= 1'b0;
      sync2 <= 1'b0;
      sync3 <= 1'b0;
    end
  else 
    begin
      sync1 <= src_lvl;
      sync2 <= sync1;  
      sync3 <= sync2;
    end
end
assign dst_lvl = sync3;

// &ModuleEnd; @42
endmodule
module booth_code_25_bit(
  A,
  code,
  h,
  product,
  sn
);

// &Ports; @22
input   [24:0]  A;      
input   [2 :0]  code;   
output  [1 :0]  h;      
output  [24:0]  product; 
output          sn;     

// &Regs; @23
reg     [1 :0]  h;      
reg     [24:0]  product; 
reg             sn;     

// &Wires; @24
wire    [24:0]  A;      
wire    [2 :0]  code;   


parameter SRC_WIDTH = 25;

// &CombBeg; @28
always @( code[2:0]
       or A[24:0])
begin
case(code[2:0])
3'b000 : product[SRC_WIDTH-1:0] =    {SRC_WIDTH{1'b0}};
3'b001 : product[SRC_WIDTH-1:0] =  {A[SRC_WIDTH-1:0]};
3'b010 : product[SRC_WIDTH-1:0] =  {A[SRC_WIDTH-1:0]};
3'b011 : product[SRC_WIDTH-1:0] =  {A[SRC_WIDTH-2:0],1'b0};
3'b100 : product[SRC_WIDTH-1:0] = {~A[SRC_WIDTH-2:0],1'b0};
3'b101 : product[SRC_WIDTH-1:0] = {~A[SRC_WIDTH-1:0]};
3'b110 : product[SRC_WIDTH-1:0] = {~A[SRC_WIDTH-1:0]};
3'b111 : product[SRC_WIDTH-1:0] =    {SRC_WIDTH{1'b0}};
default: product[SRC_WIDTH-1:0] =    {SRC_WIDTH{1'bx}};
endcase
// &CombEnd; @40
end

// &CombBeg; @42
always @( A[24]
       or code[2:0])
begin
case(code[2:0])
3'b000 : sn =  1'b1;
3'b001 : sn = ~A[SRC_WIDTH-1];
3'b010 : sn = ~A[SRC_WIDTH-1];
3'b011 : sn = ~A[SRC_WIDTH-1];
3'b100 : sn =  A[SRC_WIDTH-1];
3'b101 : sn =  A[SRC_WIDTH-1];
3'b110 : sn =  A[SRC_WIDTH-1];
3'b111 : sn =  1'b1;
default: sn =  1'bx;
endcase
// &CombEnd; @54
end

// &CombBeg; @56
always @( code[2:0])
begin
case(code[2:0])
3'b000 : h[1:0] = 2'b00;
3'b001 : h[1:0] = 2'b00;
3'b010 : h[1:0] = 2'b00;
3'b011 : h[1:0] = 2'b00;
3'b100 : h[1:0] = 2'b10;
3'b101 : h[1:0] = 2'b01;
3'b110 : h[1:0] = 2'b01;
3'b111 : h[1:0] = 2'b00;
default: h[1:0] = {2{1'bx}};
endcase
// &CombEnd; @68
end

// &ModuleEnd; @70
endmodule
module pa_sysmap_hit(
  addr_ge_bottom_x,
  addr_ge_upaddr_x,
  sysmap_comp_hit_x,
  sysmap_hit_x
);

// &Ports; @23
input        addr_ge_bottom_x; 
input        sysmap_comp_hit_x; 
output       addr_ge_upaddr_x; 
output       sysmap_hit_x;     

// &Regs; @24

// &Wires; @25
wire         addr_ge_bottom_x; 
wire         addr_ge_upaddr_x; 
wire         addr_ls_top;      
wire         sysmap_comp_hit_x; 
wire         sysmap_hit_x;     



assign addr_ls_top      = sysmap_comp_hit_x;

assign addr_ge_upaddr_x = !addr_ls_top;
assign sysmap_hit_x     = addr_ge_bottom_x && addr_ls_top;

// &ModuleEnd; @33
endmodule
module pa_sysmap_reg(
  busif_base_addr_x_updt,
  busif_base_addr_x_value,
  busif_flg_x_updt,
  busif_flg_x_value,
  busif_wdata,
  cpurst_b,
  ifu_sysmap_rst_sample,
  pad_cpu_sysmap_addr_x,
  pad_cpu_sysmap_addr_x_attr,
  sysmap_base_addr_x_value,
  sysmap_clk,
  sysmap_flg_x_value
);


// &Ports; @25
input           busif_base_addr_x_updt;    
input           busif_flg_x_updt;          
input   [31:0]  busif_wdata;               
input           cpurst_b;                  
input           ifu_sysmap_rst_sample;     
input   [19:0]  pad_cpu_sysmap_addr_x;     
input   [2 :0]  pad_cpu_sysmap_addr_x_attr; 
input           sysmap_clk;                
output  [31:0]  busif_base_addr_x_value;   
output  [31:0]  busif_flg_x_value;         
output  [19:0]  sysmap_base_addr_x_value;  
output  [4 :0]  sysmap_flg_x_value;        

// &Regs; @26
reg     [19:0]  base_addr_value;           
reg     [2 :0]  flg_value_3;               

// &Wires; @27
wire            busif_base_addr_x_updt;    
wire    [31:0]  busif_base_addr_x_value;   
wire            busif_flg_x_updt;          
wire    [31:0]  busif_flg_x_value;         
wire    [31:0]  busif_wdata;               
wire            cpurst_b;                  
wire            ifu_sysmap_rst_sample;     
wire    [19:0]  pad_cpu_sysmap_addr_x;     
wire    [2 :0]  pad_cpu_sysmap_addr_x_attr; 
wire    [19:0]  sysmap_base_addr_x_value;  
wire            sysmap_clk;                
wire    [4 :0]  sysmap_flg_x_value;        


parameter ADDR_WIDTH = 32-12;
parameter FLG_WIDTH  = 5;

parameter FLG_RST_VALUE = {FLG_WIDTH{1'b0}};
parameter ADDR_RST_VALUE = {ADDR_WIDTH{1'b0}};

// &Force("bus", "busif_wdata", 31, 0); @35
// &Force("bus", "flg_x_reset_value", FLG_WIDTH-1, 0); @36
always @ (posedge sysmap_clk or negedge cpurst_b)
begin
  if (!cpurst_b)
    flg_value_3[FLG_WIDTH-3:0] <= {(FLG_WIDTH-2){1'b0}};
  else if(ifu_sysmap_rst_sample)
    flg_value_3[FLG_WIDTH-3:0] <= pad_cpu_sysmap_addr_x_attr[FLG_WIDTH-3:0];
  else if (busif_flg_x_updt)
    flg_value_3[FLG_WIDTH-3:0] <= busif_wdata[FLG_WIDTH-1:2];
end
assign busif_flg_x_value[31:0] = {{(32-FLG_WIDTH){1'b0}}, flg_value_3[FLG_WIDTH-3:0], 2'b0};
assign sysmap_flg_x_value[FLG_WIDTH-1:0] = {flg_value_3[FLG_WIDTH-3:0], 2'b0};

always @ (posedge sysmap_clk or negedge cpurst_b)
begin
  if (!cpurst_b)
    base_addr_value[ADDR_WIDTH-1:0] <= {ADDR_WIDTH{1'b0}};
  else if(ifu_sysmap_rst_sample)
    base_addr_value[ADDR_WIDTH-1:0] <= pad_cpu_sysmap_addr_x[ADDR_WIDTH-1:0];
  else if (busif_base_addr_x_updt)
    base_addr_value[ADDR_WIDTH-1:0] <= busif_wdata[ADDR_WIDTH-1:0];
end
assign busif_base_addr_x_value[31:0] = {{(32-ADDR_WIDTH){1'b0}}, base_addr_value[ADDR_WIDTH-1:0]};
assign sysmap_base_addr_x_value[ADDR_WIDTH-1:0] = base_addr_value[ADDR_WIDTH-1:0];

// &ModuleEnd; @61
endmodule
module pa_ifu_bht_array(
  bht_cen,
  bht_din,
  bht_dout,
  bht_idx,
  bht_wen,
  cp0_ifu_icg_en,
  cp0_yy_clk_en,
  forever_cpuclk,
  pad_yy_icg_scan_en
);

// &Ports; @24
input           bht_cen;           
input   [15:0]  bht_din;           
input   [8 :0]  bht_idx;           
input   [15:0]  bht_wen;           
input           cp0_ifu_icg_en;    
input           cp0_yy_clk_en;     
input           forever_cpuclk;    
input           pad_yy_icg_scan_en; 
output  [15:0]  bht_dout;          

// &Regs; @25

// &Wires; @26
wire    [15:0]  bht_bwen_b;        
wire            bht_cen;           
wire            bht_cen_b;         
wire            bht_clk;           
wire    [15:0]  bht_din;           
wire    [15:0]  bht_dout;          
wire            bht_gwen_b;        
wire            bht_icg_en;        
wire    [8 :0]  bht_idx;           
wire    [15:0]  bht_wen;           
wire            cp0_ifu_icg_en;    
wire            cp0_yy_clk_en;     
wire            forever_cpuclk;    
wire            pad_yy_icg_scan_en; 


//==========================================================
// BHT Array Module
// 1. Instance ICG Cell
// 2. Instance Memory Cell
//==========================================================

//------------------------------------------------
// 1. Instance ICG Cell
//------------------------------------------------
assign bht_icg_en = bht_cen;
// &Instance("gated_clk_cell", "x_bht_icg_cell"); @38
gated_clk_cell  x_bht_icg_cell (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (bht_clk           ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (bht_icg_en        ),
  .module_en          (cp0_ifu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);

// &Connect( .clk_in      (forever_cpuclk), @39
//           .external_en (1'b0          ), @40
//           .global_en   (cp0_yy_clk_en ), @41
//           .module_en   (cp0_ifu_icg_en), @42
//           .local_en    (bht_icg_en    ), @43
//           .clk_out     (bht_clk       ) @44
//          ); @45

//------------------------------------------------
// 2. Instance Memory Cell
//------------------------------------------------
assign bht_cen_b       = ~bht_cen;
assign bht_gwen_b      = ~(|bht_wen[15:0]);
assign bht_bwen_b[15:0] = ~bht_wen[15:0];

// &Instance("pa_spsram_128x16","x_pa_spsram_128x16"); @55
// &Instance("pa_spsram_256x16","x_pa_spsram_256x16"); @58
// &Instance("pa_spsram_512x16","x_pa_spsram_512x16"); @61
pa_spsram_512x16  x_pa_spsram_512x16 (
  .A          (bht_idx   ),
  .CEN        (bht_cen_b ),
  .CLK        (bht_clk   ),
  .D          (bht_din   ),
  .GWEN       (bht_gwen_b),
  .Q          (bht_dout  ),
  .WEN        (bht_bwen_b)
);

// &Instance("pa_spsram_1024x16","x_pa_spsram_1024x16"); @64
// &Connect( @66
//          .CLK    (bht_clk   ), @67
//          .CEN    (bht_cen_b ), @68
//          .GWEN   (bht_gwen_b), @69
//          .WEN    (bht_bwen_b), @70
//          .A      (bht_idx   ), @71
//          .D      (bht_din   ), @72
//          .Q      (bht_dout  ) @73
//        ); @74

// &ModuleEnd; @76
endmodule
module pa_ifu_ras_entry(
  cp0_ifu_icg_en,
  cp0_yy_clk_en,
  cpurst_b,
  forever_cpuclk,
  pad_yy_icg_scan_en,
  ras_entry_pc,
  ras_entry_upd,
  ras_upd_pc
);

// &Ports; @24
input           cp0_ifu_icg_en;    
input           cp0_yy_clk_en;     
input           cpurst_b;          
input           forever_cpuclk;    
input           pad_yy_icg_scan_en; 
input           ras_entry_upd;     
input   [23:0]  ras_upd_pc;        
output  [23:0]  ras_entry_pc;      

// &Regs; @25
reg     [23:0]  entry_pc;          

// &Wires; @26
wire            cp0_ifu_icg_en;    
wire            cp0_yy_clk_en;     
wire            cpurst_b;          
wire            entry_clk;         
wire            entry_clk_en;      
wire            forever_cpuclk;    
wire            pad_yy_icg_scan_en; 
wire    [23:0]  ras_entry_pc;      
wire            ras_entry_upd;     
wire    [23:0]  ras_upd_pc;        


//==========================================================
// IFU Ras Entry Module
// 1. Instance ICG Cell
// 2. Entry PC
//==========================================================

//------------------------------------------------
// 1. Instance ICG Cell
//------------------------------------------------
assign entry_clk_en = ras_entry_upd;
// &Instance("gated_clk_cell", "x_ras_entry_icg_cell"); @38
gated_clk_cell  x_ras_entry_icg_cell (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (entry_clk         ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (entry_clk_en      ),
  .module_en          (cp0_ifu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);

// &Connect(.clk_in      (forever_cpuclk), @39
//          .external_en (1'b0), @40
//          .global_en   (cp0_yy_clk_en), @41
//          .module_en   (cp0_ifu_icg_en), @42
//          .local_en    (entry_clk_en), @43
//          .clk_out     (entry_clk) @44
//         ); @45

//------------------------------------------------
// 2. Entry PC
//------------------------------------------------
always @(posedge entry_clk or negedge cpurst_b)
begin
  if(~cpurst_b)
  begin
    entry_pc[23:0] <= 24'b0;
  end
  else if(ras_entry_upd)
  begin
    entry_pc[23:0] <= ras_upd_pc[23:0];
  end
  else
  begin
    entry_pc[23:0] <= entry_pc[23:0];
  end
end


//==========================================================
// Rename for Output
//==========================================================
assign ras_entry_pc[23:0] = entry_pc[23:0];


// &ModuleEnd; @73
endmodule
module pa_rst_top(
  cpurst_b,
  forever_cpuclk,
  pad_cpu_rst_b,
  pad_yy_scan_mode,
  pad_yy_scan_rst_b,
  sync_sys_apb_rst_b,
  sys_apb_clk,
  sys_apb_rst_b
);

// &Ports; @23
input        forever_cpuclk;    
input        pad_cpu_rst_b;     
input        pad_yy_scan_mode;  
input        pad_yy_scan_rst_b; 
input        sys_apb_clk;       
input        sys_apb_rst_b;     
output       cpurst_b;          
output       sync_sys_apb_rst_b; 

// &Regs; @24
reg          ciu_rst_ff_1st;    
reg          ciu_rst_ff_2nd;    
reg          ciu_rst_ff_3rd;    
reg          sys_apb_rst_ff_1st; 

// &Wires; @25
wire         async_apb_rst_b;   
wire         async_ciu_rst_b;   
wire         cpurst_b;          
wire         forever_cpuclk;    
wire         pad_cpu_rst_b;     
wire         pad_yy_scan_mode;  
wire         pad_yy_scan_rst_b; 
wire         sync_sys_apb_rst_b; 
wire         sys_apb_clk;       
wire         sys_apb_rst_b;     


assign async_ciu_rst_b = pad_cpu_rst_b;// & !pad_yy_mbist_mode;

always @(posedge forever_cpuclk or negedge async_ciu_rst_b)
begin
  if (!async_ciu_rst_b)
  begin
    ciu_rst_ff_1st <= 1'b0;
    ciu_rst_ff_2nd <= 1'b0;
    ciu_rst_ff_3rd <= 1'b0;
  end
  else
  begin
    ciu_rst_ff_1st <= 1'b1;
    ciu_rst_ff_2nd <= ciu_rst_ff_1st;
    ciu_rst_ff_3rd <= ciu_rst_ff_2nd;
  end
end

assign cpurst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : ciu_rst_ff_3rd;
//assign hadrst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : pad_had_rst_b;
//assign trst_b   = pad_yy_scan_mode ? pad_yy_scan_rst_b : pad_had_jtg_trst_b;


assign async_apb_rst_b = sys_apb_rst_b;// & !pad_yy_mbist_mode;

always @(posedge sys_apb_clk or negedge async_apb_rst_b)
begin
  if (!async_apb_rst_b)
    sys_apb_rst_ff_1st <= 1'b0;
  else
    sys_apb_rst_ff_1st <= 1'b1;
end


assign sync_sys_apb_rst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : sys_apb_rst_ff_1st;


// &ModuleEnd; @77
endmodule
module pa_hpcp_event(
  clk_en,
  cnt_output,
  cnt_wen,
  cp0_hpcp_icg_en,
  cpurst_b,
  forever_cpuclk,
  hpcp_wdata,
  pad_yy_icg_scan_en
);

// &Ports; @23
input           clk_en;            
input           cnt_wen;           
input           cp0_hpcp_icg_en;   
input           cpurst_b;          
input           forever_cpuclk;    
input   [31:0]  hpcp_wdata;        
input           pad_yy_icg_scan_en; 
output  [31:0]  cnt_output;        

// &Regs; @24
reg     [4 :0]  counter;           

// &Wires @25
wire            clk_en;            
wire            cnt_clk;           
wire    [31:0]  cnt_output;        
wire            cnt_wen;           
wire            cp0_hpcp_icg_en;   
wire            cpurst_b;          
wire            forever_cpuclk;    
wire    [31:0]  hpcp_wdata;        
wire            pad_yy_icg_scan_en; 


// &Force("bus","hpcp_wdata",31,0); @27
//==========================================================
//                 Instance of Gated Cell  
//========================================================== 
// &Instance("gated_clk_cell", "x_gated_clk"); @31
gated_clk_cell  x_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (cnt_clk           ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (clk_en            ),
  .module_en          (cp0_hpcp_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);

// &Connect(.clk_in      (forever_cpuclk), @32
//          .external_en (1'b0), @33
//          .global_en   (1'b1), @34
//          .module_en   (cp0_hpcp_icg_en), @35
//          .local_en    (clk_en), @36
//          .clk_out     (cnt_clk)); @37

//==========================================================
//                 Implementation of counter  
//==========================================================
always @(posedge cnt_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    counter[4:0] <= 5'b0;
  else if(cnt_wen)
    counter[4:0] <= hpcp_wdata[4:0];
  else
    counter[4:0] <= counter[4:0];
end

//output
assign cnt_output[31:0] = {27'b0, counter[4:0]};

// &ModuleEnd; @55
endmodule
module pa_hpcp_cnt(
  clk_en,
  cnt_adder,
  cnt_en,
  cnt_hwen,
  cnt_output,
  cnt_wen,
  cp0_hpcp_icg_en,
  cpurst_b,
  forever_cpuclk,
  hpcp_wdata,
  pad_yy_icg_scan_en
);

// &Ports; @23
input           clk_en;            
input           cnt_adder;         
input           cnt_en;            
input           cnt_hwen;          
input           cnt_wen;           
input           cp0_hpcp_icg_en;   
input           cpurst_b;          
input           forever_cpuclk;    
input   [31:0]  hpcp_wdata;        
input           pad_yy_icg_scan_en; 
output  [63:0]  cnt_output;        

// &Regs; @24
reg     [63:0]  counter;           

// &Wires @25
wire            clk_en;            
wire            cnt_adder;         
wire            cnt_clk;           
wire            cnt_en;            
wire            cnt_hwen;          
wire    [63:0]  cnt_output;        
wire            cnt_wen;           
wire    [63:0]  counter_adder;     
wire            cp0_hpcp_icg_en;   
wire            cpurst_b;          
wire            forever_cpuclk;    
wire    [31:0]  hpcp_wdata;        
wire            pad_yy_icg_scan_en; 


//==========================================================
//                 Instance of Gated Cell  
//========================================================== 
// &Instance("gated_clk_cell", "x_gated_clk"); @30
gated_clk_cell  x_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (cnt_clk           ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (clk_en            ),
  .module_en          (cp0_hpcp_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);

// &Connect(.clk_in      (forever_cpuclk), @31
//          .external_en (1'b0), @32
//          .global_en   (1'b1), @33
//          .module_en   (cp0_hpcp_icg_en), @34
//          .local_en    (clk_en), @35
//          .clk_out     (cnt_clk)); @36

//==========================================================
//                 Implementation of counter  
//==========================================================
always @(posedge cnt_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    counter[63:0] <= 64'b0;
  else if(cnt_wen)
    counter[63:0] <= {counter[63:32], hpcp_wdata[31:0]};
  else if(cnt_hwen)
    counter[63:0] <= {hpcp_wdata[31:0], counter[31:0]};
  else if(cnt_en)   //if gateclk is not immplented                   
    counter[63:0] <= counter_adder[63:0];
  else
    counter[63:0] <= counter[63:0];
end

assign counter_adder[63:0] = counter[63:0] + {63'b0, cnt_adder};

//output
assign cnt_output[63:0] = counter[63:0];

// &ModuleEnd; @60
endmodule