module ghrd_10as066n2_pr_region_controller_0 (
		input  wire        avl_csr_read,                   //        avl_csr.read
		input  wire        avl_csr_write,                  //               .write
		input  wire [1:0]  avl_csr_address,                //               .address
		input  wire [31:0] avl_csr_writedata,              //               .writedata
		output wire [31:0] avl_csr_readdata,               //               .readdata
		output wire        bridge_freeze0_freeze,          // bridge_freeze0.freeze
		input  wire        bridge_freeze0_illegal_request, //               .illegal_request
		output wire        bridge_freeze1_freeze,          // bridge_freeze1.freeze
		input  wire        bridge_freeze1_illegal_request, //               .illegal_request
		input  wire        clock_clk,                      //          clock.clk
		output wire        pr_handshake_start_req,         //   pr_handshake.start_req
		input  wire        pr_handshake_start_ack,         //               .start_ack
		output wire        pr_handshake_stop_req,          //               .stop_req
		input  wire        pr_handshake_stop_ack,          //               .stop_ack
		input  wire        reset_reset,                    //          reset.reset
		output wire        reset_source_reset              //   reset_source.reset
	);

	ghrd_10as066n2_pr_region_controller_0_altera_pr_region_controller_171_lvntgla pr_region_controller_0 (
		.avl_csr_read                   (avl_csr_read),                   //   input,   width = 1,        avl_csr.read
		.avl_csr_write                  (avl_csr_write),                  //   input,   width = 1,               .write
		.avl_csr_address                (avl_csr_address),                //   input,   width = 2,               .address
		.avl_csr_writedata              (avl_csr_writedata),              //   input,  width = 32,               .writedata
		.avl_csr_readdata               (avl_csr_readdata),               //  output,  width = 32,               .readdata
		.bridge_freeze0_freeze          (bridge_freeze0_freeze),          //  output,   width = 1, bridge_freeze0.freeze
		.bridge_freeze0_illegal_request (bridge_freeze0_illegal_request), //   input,   width = 1,               .illegal_request
		.bridge_freeze1_freeze          (bridge_freeze1_freeze),          //  output,   width = 1, bridge_freeze1.freeze
		.bridge_freeze1_illegal_request (bridge_freeze1_illegal_request), //   input,   width = 1,               .illegal_request
		.clock_clk                      (clock_clk),                      //   input,   width = 1,          clock.clk
		.pr_handshake_start_req         (pr_handshake_start_req),         //  output,   width = 1,   pr_handshake.start_req
		.pr_handshake_start_ack         (pr_handshake_start_ack),         //   input,   width = 1,               .start_ack
		.pr_handshake_stop_req          (pr_handshake_stop_req),          //  output,   width = 1,               .stop_req
		.pr_handshake_stop_ack          (pr_handshake_stop_ack),          //   input,   width = 1,               .stop_ack
		.reset_reset                    (reset_reset),                    //   input,   width = 1,          reset.reset
		.reset_source_reset             (reset_source_reset)              //  output,   width = 1,   reset_source.reset
	);

endmodule