dakies/OSS_Verilog huggingface dataset:
module cfg_dprio_readdata_mux 
#(
   parameter DATA_WIDTH      = 16,  // Data width
   parameter NUM_INPUT       = 4    // Number of n-bit input
 )
( 
input  wire                             clk,
input  wire                             rst_n,
input  wire                             read,
input  wire [NUM_INPUT-1:0]             sel,      // 1-hot selection input
input  wire [DATA_WIDTH*NUM_INPUT-1:0]  data_in,  // data input

output reg  [DATA_WIDTH-1:0]            data_out  // data output
);


wire  [DATA_WIDTH-1:0] data_out_int[0:NUM_INPUT-1];
//wire  [DATA_WIDTH-1:0] input_array[0:NUM_INPUT-1];
wire  [DATA_WIDTH-1:0] data_out_d;
wire  [NUM_INPUT-1:0] data_out_bit[0:DATA_WIDTH-1];

generate
genvar i;
  for (i=0; i<NUM_INPUT; i=i+1)
    begin: array_assignment
//      assign input_array[i] = data_in[(DATA_WIDTH*(i+1))-1:DATA_WIDTH*i];
      // 2:1 mux for each data_in[DATA_WIDTH-1:0]
      assign data_out_int[i] = (sel[i]) ? data_in[(DATA_WIDTH*(i+1))-1:DATA_WIDTH*i] : {DATA_WIDTH{1'b0}};
    end
endgenerate

generate
genvar k,l;
  for (k=0; k<DATA_WIDTH; k=k+1)
  begin: bit_sel
    for (l=0; l<NUM_INPUT; l=l+1)
      begin: bit_sel_or
        // Create array of bit[0], bit[1],.... for muxed data
        assign data_out_bit[k][l] = data_out_int[l][k];
      end
  // bitwise ORED each array element
  assign data_out_d[k] = |data_out_bit[k];
  end
endgenerate


// Registering output
always @ (negedge rst_n or posedge clk)
  if (rst_n == 1'b0)
    begin
      data_out <= {DATA_WIDTH{1'b0}};
    end
  else
    begin
      if (read == 1'b1)
        begin
          data_out <= data_out_d;
        end
    end


/*
wire [DATA_WIDTH*(NUM_INPUT+1)-1:0] out_int;

// 1-hot muxing
generate
genvar i;
 for (i=0; i<NUM_INPUT; i=i+1)
   begin: modular_mux
   hd_dpcmn_dprio_readdata_mux_mod 
   #(
     .DATA_WIDTH(DATA_WIDTH)  // Data width
    ) hd_dpcmn_dprio_readdata_mux_mod
    ( 
     .sel      (sel[i]),                                        // 1-hot selection input
     .data_in1 (data_in[DATA_WIDTH*(i+1)-1:DATA_WIDTH*(i+0)]),  // data input
     .data_in0 (out_int[DATA_WIDTH*(i+1)-1:DATA_WIDTH*(i+0)]),  // data input
     .data_out (out_int[DATA_WIDTH*(i+2)-1:DATA_WIDTH*(i+1)])   // data output
    );
   end
endgenerate

assign out_int[DATA_WIDTH-1:0] = {DATA_WIDTH{1'b0}};

// Registering output
always @ (negedge rst_n or posedge clk)
  if (rst_n == 1'b0)
    begin
      data_out <= {DATA_WIDTH{1'b0}};
    end
  else
    begin
      if (read == 1'b1)
        begin
          data_out <= out_int[DATA_WIDTH*(NUM_INPUT+1)-1:DATA_WIDTH*NUM_INPUT];
        end
    end
*/    
endmodule
module cfg_dprio_csr_reg_nbits 
#(
   parameter DATA_WIDTH = 16  // Data width
 )
( 
input  wire                      clk,        // clock
input  wire                      csr_in,     // CSR serial in
input  wire                      csr_en,     // CSR enable  
output wire                      csr_out,    // CSR serial output
output wire [DATA_WIDTH-1:0]     csr_reg     // CSR output to DPRIO
);

wire   [DATA_WIDTH:0]        chain;

generate 
  genvar i;
  for (i=0; i < DATA_WIDTH; i=i+1)
    begin: csr_reg_bit
cfg_dprio_csr_reg_bit  csr_reg_bit (
                                   .clk (clk),
                                   .csr_in (chain[i]),
                                   .csr_en (csr_en), 
                                   .csr_chain (chain[i+1]),
                                   .csr_out (csr_reg[i])
                                  );
    end
endgenerate

// Connecting the csr_in and csr_out
assign csr_out  = chain[DATA_WIDTH];
assign chain[0] = csr_in;

endmodule
module cfg_dprio_ctrl_reg_bit 
(
input  wire      clk,              // clock
input  wire      dprio_in,         // DPRIO input
input  wire      csr_in,           // serial input
input  wire      dprio_sel,        // 1'b1=choose csr_in
                                   // 1'b0=choose dprio_in
input  wire      bit_en,           // Write enable signal
input  wire      hold_csr,         // Hold CSR value
input  wire      gated_cram,       // Gating CRAM output
input  wire      pma_csr_test_dis, // Disable PMA CSR test

output wire      sig_out,          // CRAM output
output wire      csr_out           // csr output
);

wire             d_int;
wire             bit_en_int;
wire             d_wr_en;

// Enable bit_in during CSR shift
assign bit_en_int = (dprio_sel == 1'b1) ? 1'b1 : bit_en;

// Data in for combined DPRIO-CSR register
assign d_int = (pma_csr_test_dis == 1'b0) ? sig_out  :
               (dprio_sel == 1'b0)        ? dprio_in :
               (hold_csr == 1'b0)         ? csr_in   : csr_out;

// Combined DPRIO-CSR 1-bit register
//always @ (posedge clk)
//  if (bit_en_int)
//    begin
//      csr_out <= d_int;
//    end
assign d_wr_en = (bit_en_int == 1'b1) ? d_int : csr_out;
  cfg_cmn_non_scan_reg dprio_ns_reg (
    .din  (d_wr_en),
    .clk  (clk),
    .dout (csr_out)
  );

// CRAM output
assign sig_out = (gated_cram == 1'b1) ? csr_out : 1'b0;

endmodule
module cfg_dprio_dis_ctrl_cvp
#(
   parameter CLK_FREQ_MHZ = 250, // Clock freq in MHz
   parameter TOGGLE_TYPE = 1,
   parameter VID = 1
 )
(
input  wire      rst_n,         // reset
input  wire      clk,           // clock
input  wire      dprio_dis_in,  // dprio_dis in
input  wire      csr_cvp_en,    // CSR enable
output wire      dprio_dis_out  // dprio_dis out
);

reg   dprio_dis_hold_1;
reg   dprio_dis_hold_2;
wire  dprio_dis_in_sync;
wire  dprio_dis_int;

// dprio_dis_in synchronizer
cdclib_bitsync2 
  #(
    .DWIDTH(1),    // Sync Data input 
    .RESET_VAL(1), // Reset value
    .CLK_FREQ_MHZ(CLK_FREQ_MHZ) ,
    .TOGGLE_TYPE(TOGGLE_TYPE),
    .VID(VID)
    ) dprio_dis_in_sync_1
    (
     .clk(clk),                   // clock
     .rst_n(rst_n),               // async reset
     .data_in(dprio_dis_in),      // data in
     .data_out(dprio_dis_in_sync) // data out
    );

// Hold dprio_dis logic
always @ (negedge rst_n or posedge clk)
  if (rst_n == 1'b0)
    begin
      dprio_dis_hold_1 <= 1'b1;
      dprio_dis_hold_2 <= 1'b1;
    end
  else
    begin
      dprio_dis_hold_1 <= (dprio_dis_int) ? dprio_dis_in_sync : 1'b0;
      dprio_dis_hold_2 <= dprio_dis_hold_1;
    end

// internal dprio_dis
assign dprio_dis_int = dprio_dis_hold_1 | dprio_dis_hold_2;

// dprio_dis_out
assign dprio_dis_out = (csr_cvp_en == 1'b1) ? dprio_dis_int : dprio_dis_in;

endmodule
module cfg_dprio_readdata_mux_mod 
#(
   parameter DATA_WIDTH      = 16  // Data width
 )
( 
input  wire                   sel,       // 1-hot selection input
input  wire [DATA_WIDTH-1:0]  data_in1,  // data input
input  wire [DATA_WIDTH-1:0]  data_in0,  // data input

output wire [DATA_WIDTH-1:0]  data_out   // data output
);

assign data_out = (sel == 1'b1) ? data_in1 : data_in0;

endmodule
module cfg_dprio_shadow_status_regs 
#(
   parameter DATA_WIDTH    = 16,      // Data width
   parameter CLK_FREQ_MHZ  = 250,      // Clock freq in MHz
   parameter TOGGLE_TYPE = 1,
   parameter VID = 1
 )
(
input  wire                                 rst_n,         // reset
input  wire                                 clk,           // clock
input  wire [DATA_WIDTH-1:0]                stat_data_in,  // status data input
input  wire                                 write_en,      // write data enable from DPRIO

output wire                                 write_en_ack,  // write data enable acknowlege to DPRIO
output reg  [DATA_WIDTH-1:0]                stat_data_out  // status data output

);

wire   write_en_sync;

// Bit sync for write_en
cdclib_bitsync2 
   #(
      .DWIDTH       (1), // Sync Data input 
      .RESET_VAL    (0), // Reset value
      .CLK_FREQ_MHZ (CLK_FREQ_MHZ),
      .TOGGLE_TYPE(TOGGLE_TYPE),
      .VID(VID)
    ) write_en_sync_1
   (
    .clk  (clk),              // read clock
    .rst_n(rst_n),            // async reset for read clock domain
    .data_in (write_en),      // data in
    .data_out(write_en_sync)  // data out
   );

// Write_en acknowlege
assign write_en_ack = write_en_sync;

// Registering data_in with write_en
always @(negedge rst_n or posedge clk)
  if (rst_n == 1'b0)
    begin
      stat_data_out   <= {DATA_WIDTH{1'b0}};
    end
  else if (write_en_sync == 1'b1)
    begin      
      stat_data_out <= stat_data_in;
    end


endmodule
module cfg_dprio_csr_test_mux
(
input  wire        rst_n,           // Active low hard reset
input  wire        clk,             // Clock
input  wire        cbdin,           // CSR configuration mode data input
input  wire        tcsrin,          // CSR test/scan mode data input
input  wire        csrdin,          // Previous CSR bit data output
input  wire        csr_seg,         // VSS for Seg0, VCC for seg[31:1]
input  wire        entest,          // enable test control input
input  wire        enscan,          // enable scan control input
input  wire        tverify,         // test verify control input
input  wire        load_csr,        // JTAG scan mode control input
input  wire        pipe_in,         // Input to the Pipeline register to suport 200MHz

output wire        csrdout,         // CSR input MUX Data output
output reg         pipe_out         // Pipelined register data output
);

reg                csr_reg;
wire               prog_mode;
wire               test_mode;
wire               scan_mode;
wire               verify_mode;
wire               jtag_mode;

// CSR register
always @(negedge rst_n or negedge clk)
  if (rst_n == 1'b0)
    begin
      csr_reg <= 1'b0;
    end
  else
    begin
      csr_reg <= cbdin;
    end
    
// CSR pipeline register
always @(negedge rst_n or posedge clk)
  if (rst_n == 1'b0)
    begin
      pipe_out <= 1'b0;
    end
  else
    begin
      pipe_out <= pipe_in;
    end
    
// Mode decoding
assign prog_mode   = (~entest) & (~enscan) & (~tverify) & (~load_csr);
assign test_mode   = (entest)  & (~enscan) & (~tverify) & (~load_csr);
assign scan_mode   = (~entest) & (enscan)  & (~tverify) & (~load_csr);
assign verify_mode = (entest)  & (~enscan) & (tverify)  & (~load_csr);
assign jtag_mode   = (~entest) & (~enscan) & (~tverify) & (load_csr);

// csrdout muxing logic
assign csrdout     = (prog_mode == 1'b1)   ? csr_reg :
                     (test_mode == 1'b1)   ? tcsrin  :
                     (scan_mode == 1'b1)   ? ((~csr_seg & tcsrin) | (csr_seg & csrdin)) :
                     (verify_mode == 1'b1) ? ((~csr_seg & tcsrin) | (csr_seg & csrdin)) :
                     (jtag_mode == 1'b1)   ? ((~csr_seg & cbdin)  | (csr_seg & csrdin)) : 1'b0;
                   
endmodule
module cfg_dprio_status_reg_nbits 
#(
   parameter DATA_WIDTH      = 16,  // Data width
   parameter ADDR_WIDTH      = 16   // Address width
 )
( 
input  wire                  rst_n,        // reset
input  wire                  clk,          // clock
input  wire                  read,         // read enable input
input  wire [ADDR_WIDTH-1:0] reg_addr,     // address input
input  wire [ADDR_WIDTH-1:0] target_addr,  // hardwired address value
input  wire [DATA_WIDTH-1:0] user_datain,  // status from custom logic

output reg  [DATA_WIDTH-1:0] user_readdata // status register outputs
);

// Registering the status input when reading
always @(negedge rst_n or posedge clk)
  begin
    if(~rst_n)
      begin
        user_readdata <= {DATA_WIDTH{1'b0}};
      end
    else
      begin
	if((reg_addr == target_addr) && (read == 1'b1))
	begin
	  user_readdata <= user_datain;
	end
      end
  end

endmodule
module cfg_cmn_latch (
  input      din,
  input      clk,
  output reg dout
);

  always @(*)
    if (clk)
      dout <= din;

endmodule
module cfg_dprio_readdata_sel
#(
   parameter ADDR_WIDTH      = 10  // Address width
 )
( 
input  wire [ADDR_WIDTH-1:0]  reg_addr,     // address input
input  wire [ADDR_WIDTH-1:0]  target_addr,  // target address input

output wire                   readdata_sel  // read select output
);

assign readdata_sel = (reg_addr == target_addr) ? 1'b1 : 1'b0;

endmodule
module cfg_bead
  (
    // Bead interface
    input wire                   scan_clk_in,
    input wire                   scan_data_in,
    input wire                   capture_in,
    input wire                   update_in,
    input wire                   clr_n_in,

    // Bead interface
    output wire                  scan_data_out,

    // BEAD_CFG_IF
    output wire                  bead_val
  );

  wire                   bead_val_int;
  wire                   scan_reg_in_int;
  wire                   bead_in_int;

  assign bead_val_int = bead_val | clr_n_in;
  assign scan_reg_in_int = (capture_in)? bead_val_int : scan_data_in;
  assign bead_in_int = scan_data_out & clr_n_in;

  // Non resettablei & non scannable reg
//  always @(posedge scan_clk_in)
//    scan_data_out <= scan_reg_in_int;
  cfg_cmn_non_scan_reg bead_ns_reg (
    .din  (scan_reg_in_int),
    .clk  (scan_clk_in),
    .dout (scan_data_out)
  );

  // Non resettable latch
//  always @(*)
//    if (update_in)
//      bead_val <= bead_in_int;
  cfg_cmn_latch bead_latch (
    .din (bead_in_int),
    .clk (update_in),
    .dout(bead_val)
  );

endmodule // cfg_bead
module cfg_cmn_non_scan_reg (
  input      din,
  input      clk,
  output reg dout
);

  always @(posedge clk)
    dout <= din;

endmodule
module cfg_dprio_status_reg_nregs 
#(
   parameter DATA_WIDTH      = 16,  // Data width
   parameter ADDR_WIDTH      = 16,  // Address width
   parameter NUM_STATUS_REGS = 10,  // Number of n-bit status registers
   parameter BYPASS_STAT_SYNC= 0,   // Parameter to bypass the Synchronization SM in case of individual status bits   
   parameter CLK_FREQ_MHZ    = 250,  // Clock freq in MHz
   parameter TOGGLE_TYPE     = 1,
   parameter VID             = 1
 )
( 
input  wire                                  rst_n,        // reset
input  wire                                  clk,          // clock
input  wire                                  read,         // read enable input
input  wire [ADDR_WIDTH-1:0]                 reg_addr,     // address input
input  wire [ADDR_WIDTH*NUM_STATUS_REGS-1:0] target_addr,  // hardwired address value
input  wire [DATA_WIDTH*NUM_STATUS_REGS-1:0] user_datain,  // status from custom logic
input  wire [NUM_STATUS_REGS-1:0]            write_en_ack, // write data acknowlege from user logic

output wire [NUM_STATUS_REGS-1:0]            write_en,     // write data enable to user logic
output wire [DATA_WIDTH*NUM_STATUS_REGS-1:0] user_readdata // status register outputs
);

wire [DATA_WIDTH*NUM_STATUS_REGS-1:0] user_datain_int;     // status from custom logic

generate
genvar i;
  for (i=0; i < NUM_STATUS_REGS; i=i+1)
  begin: stat_reg_nbits
// Status register synchronizers
cfg_dprio_status_sync_regs 
#(
   .DATA_WIDTH(DATA_WIDTH),             // Data width
   .BYPASS_STAT_SYNC(BYPASS_STAT_SYNC), // Parameter to bypass the Synchronization SM in case of individual status bits
   .CLK_FREQ_MHZ (CLK_FREQ_MHZ),
   .TOGGLE_TYPE(TOGGLE_TYPE),
   .VID(VID)
 ) cfg_dprio_status_sync_regs
(
 .rst_n(rst_n),                                                    // reset
 .clk(clk),                                                        // clock
 .stat_data_in(user_datain[DATA_WIDTH*(i+1)-1:DATA_WIDTH*i]),      // status data input
 .write_en_ack(write_en_ack[i]),                                   // write data acknowlege from user logic
 .write_en(write_en[i]),                                           // write data enable to user logic
 .stat_data_out(user_datain_int[DATA_WIDTH*(i+1)-1:DATA_WIDTH*i])  // status data output
);

// Status register for reading
  cfg_dprio_status_reg_nbits 
#(
   .DATA_WIDTH(DATA_WIDTH),  // Data width
   .ADDR_WIDTH(ADDR_WIDTH)   // Address width
 ) cfg_dprio_status_reg_nbits
( 
 .rst_n(rst_n),                                                 // reset
 .clk(clk),                                                     // clock
 .read(read),                                                   // read enable input
 .reg_addr(reg_addr),                                           // address input
 .target_addr(target_addr[ADDR_WIDTH*(i+1)-1:ADDR_WIDTH*i]),    // hardwired address value
 .user_datain(user_datain_int[DATA_WIDTH*(i+1)-1:DATA_WIDTH*i]),// status from custom logic

 .user_readdata(user_readdata[DATA_WIDTH*(i+1)-1:DATA_WIDTH*i]) // status register outputs
);
  end


endgenerate

endmodule
module cfg_dprio_ctrl_reg_nbits 
#(
   parameter DATA_WIDTH = 16,  // Data width
   parameter ADDR_WIDTH = 16   // Address width
 )
( 
input  wire                      clk,              // clock
input  wire                      write,            // write enable input
input  wire [ADDR_WIDTH-1:0]     reg_addr,         // address input
input  wire [ADDR_WIDTH-1:0]     target_addr,      // hardwired address value
input  wire [DATA_WIDTH-1:0]     writedata,        // write data input
input  wire                      csr_in,           // serial CSR input
input  wire                      hold_csr,         // Hold CSR value  
input  wire                      gated_cram,       // Gating CRAM output
input  wire                      dprio_sel,        // 1'b1=choose csr_in
                                                   // 1'b0=choose dprio_in
input  wire                      pma_csr_test_dis, // Disable PMA CSR test
input  wire [(DATA_WIDTH/8)-1:0] byte_en,          // Byte enable
input  wire                      broadcast_en,     // Broadcast enable (controlled by extra CSR bit)

output wire [DATA_WIDTH-1:0]     sig_out,          // signal output
output wire                      csr_out           // serial CSR output
);

wire   [DATA_WIDTH-1:0]      signal_in_int;
wire   [DATA_WIDTH:0]        chain;
wire   [DATA_WIDTH-1:0]      byte_en_int;

// Data to ctrl_reg_bit
assign signal_in_int = (write && ((!broadcast_en && (reg_addr == target_addr)) || broadcast_en)) ? writedata : chain[DATA_WIDTH:1];

// Enable signals to ctrl_reg_bit
generate
  genvar i;
  for (i=0; i < (DATA_WIDTH/8); i=i+1)
    begin: byte_enable
      assign byte_en_int[(i*8)+7:(i*8)] = {8{byte_en[i]}};
    end
endgenerate

generate 
  genvar j;
  for (j=0; j < DATA_WIDTH; j=j+1)
    begin: ctrl_reg_bit
cfg_dprio_ctrl_reg_bit  ctrl_reg_bit (
                                       .clk (clk), 
                                       .dprio_in (signal_in_int[j]), 
                                       .csr_in (chain[j]), 
                                       .dprio_sel (dprio_sel),
                                       .bit_en (byte_en_int[j]),
                                       .hold_csr (hold_csr), 
                                       .gated_cram (gated_cram),
                                       .pma_csr_test_dis(pma_csr_test_dis),
                                       .sig_out (sig_out[j]), 
                                       .csr_out (chain[j+1])
                                      );
    end
endgenerate

// Connecting the csr_in and csr_out
assign csr_out  = chain[DATA_WIDTH];
assign chain[0] = csr_in;

endmodule
module aibndpnr_dll_atech_clkgate_cgc01
(
    input    wire   clk,
    input    wire   en,
    input    wire   te,
    output   wire   clkout
);

wire    d;
reg     o;

assign  d = en | te;

always @ (d, clk)
    begin
       if (~clk)
          begin
             o <=d;
          end
    end 

assign clkout = clk & o;



endmodule
module aibndpnr_half_cycle_code_gen 
#(
parameter FF_DELAY     = 200
)
(
   input  wire         clk,                     //reference clock from pll
   input  wire         reset_n,                 //output for dll reset
   input  wire  [9:0]  pvt_ref_binary,          //output binary pvt value for delay chain
   input  wire         rb_half_code,   		//select between original or half cycle codes
   output reg   [9:0]  pvt_ref_half_binary 	//half cycle code (binary) for delay chain
);

`ifdef TIMESCALE_EN
  timeunit 1ps;
  timeprecision 1ps;
`endif

wire [6:0]  coarse_bin;
wire [2:0]  fint_bin, fint_bin_inc;
wire [2:0]  fine_bin;
wire [7:0]  coarse_divided_bin;
wire [3:0]  fine_divided_bin, coarse_frac_bin;

                        assign  coarse_divided_bin[7:0] = {1'b0,pvt_ref_binary[9:3]};
                        assign  fine_divided_bin[3:0] = {1'b0,pvt_ref_binary[2:0]};
                        assign  coarse_frac_bin[3:0] = {coarse_divided_bin[0],3'b000};
                        assign  fint_bin[2:0] = coarse_frac_bin[3:1] + fine_divided_bin[3:1];
                        assign  fint_bin_inc[2:0] = ((fine_divided_bin[0] >= 1'd1) && (fint_bin < 3'd7)) ? fint_bin[2:0] + 3'b001 : fint_bin[2:0];

        assign coarse_bin = coarse_divided_bin[7:1];
        assign fine_bin = fint_bin_inc;

        always @(posedge clk or negedge reset_n)
                begin
                        if(~reset_n) begin
				pvt_ref_half_binary <= #FF_DELAY 10'b00_0000_0000;
			end
			else case (rb_half_code)
				1'b0 : pvt_ref_half_binary <= #FF_DELAY pvt_ref_binary;
				1'b1 : pvt_ref_half_binary <= #FF_DELAY {coarse_bin,fine_bin};
				default : pvt_ref_half_binary <= #FF_DELAY {coarse_bin,fine_bin};
			endcase
		end 

endmodule // aibndpnr_half_cycle_code_gen
module aibndpnr_dll_ctrl (
   input  wire         clk,                     //reference clock from pll
   input  wire         reinit,                  //initialization enable
   input  wire         entest,                  //test enable
   input  wire         ndllrst_in,              //reset from core
   input  wire         rb_dll_en,               //dll enable
   input  wire         rb_dll_rst_en,           //dll reset enable
   input  wire         atpg_en_n,               //atpg
   input  wire         test_clr_n,              //test clear
   output wire         dll_reset_n             //output for dll reset
);

`ifdef TIMESCALE_EN
  timeunit 1ps;
  timeprecision 1ps;
`endif

wire         eni;
wire         dll_rst;

////////////////////////////////////////////////////////////////////
//                                                                //
//  reset and preset                                              //
//                                                                //
////////////////////////////////////////////////////////////////////

assign dll_rst = (rb_dll_rst_en) ?  ~ndllrst_in : 1'b0;                 //core reset at "1" if core_reset enabled
assign eni = ~entest & rb_dll_en & (~reinit) & (~dll_rst);              //dll enable and non-test
cdclib_rst_n_sync unrst  ( .rst_n(eni), .rst_n_bypass(test_clr_n), .clk(clk),  .scan_mode_n(atpg_en_n), .rst_n_sync(dll_reset_n) );

endmodule // aibndpnr_dll_ctrl
module aibndpnr_dll_atech_clkgate_cgc00
(
    input    wire   clk,
    input    wire   en,
    output   wire   clkout
);

reg     o;

always @ (en, clk)
    begin
       if (~clk)
          begin
             o <=en;
          end
    end 

assign clkout = clk & o;



endmodule
module aibndpnr_dll_atech_clkmux

// IMPORTANT NOTICE: This clock mux behavioral model
// must be mapped to either a transmission gate mux
// or a pass gate mux in the standard cell library.
// Failure to comply will result in glitch hazards.

(
             input    wire   clk1,
             input    wire   clk2,
             input    wire   s,		// Select
             output   wire   clkout
);

assign clkout = s ? clk1 : clk2;	// 2:1 clock mux

endmodule
module aibndpnr_sync 
#(
//-----------------------------------------------------------------------------------------------------------------------
//  Local calculated parameters
//-----------------------------------------------------------------------------------------------------------------------
parameter FF_DELAY     = 200
)

( q, so, clk, d, rb, ssb, si );

output reg  q, so;

input  clk, d, rb, ssb, si;

`ifdef DLL_SYNOPSYS

d04hgy23nd0c0 xsync0 ( .d(d), .clk(clk), .o(q0),
     .rb(rb), .si(si), .so(so0), .ssb(ssb));
d04hgy23nd0c0 xsync1 ( .d(q0), .clk(clk), .o(q),
     .rb(rb), .si(so0), .so(so), .ssb(ssb));

`else

reg           t_reg0;
reg           t_reg1;

always @(posedge clk or negedge rb)
    if (~rb) begin
        t_reg0 <= #FF_DELAY 1'b0;
        t_reg1 <= #FF_DELAY 1'b0;
        q <= #FF_DELAY 1'b0;
    end
    else begin
        t_reg0 <= #FF_DELAY d;
        t_reg1 <= #FF_DELAY t_reg0;
        q <= #FF_DELAY t_reg1;
    end

`endif

endmodule
module aibndpnr_redundancy ( //input of input mux
idata0_in1, idata0_in0, idata1_in1, idata1_in0, 
idataselb_in1, idataselb_in0, iddren_in1, iddren_in0,
irxen_in1, irxen_in0, itxen_in1, itxen_in0, indrv_in1, indrv_in0, ipdrv_in1, ipdrv_in0, async_dat_in1, async_dat_in0, 
//Output of input mux
idata0_out, idata1_out, idataselb_out, iddren_out,
irxen_out, itxen_out, indrv_out, ipdrv_out, async_dat_out,

//input of output mux
odat0_in1, odat0_in0, odat1_in1, odat1_in0, odat_async_in1, odat_async_in0,

//Output of output mux
odat0_out, odat1_out, odat_async_out,

//Mux selection signal
shift_en	//Removed VCCL & VSS port

);

//Power Supply
//input  vccl, vssl;

//Mux selection signal
input shift_en;

//input of input mux
input idata0_in1, idata0_in0; 
input idata1_in1, idata1_in0;
input idataselb_in1, idataselb_in0;
input iddren_in1, iddren_in0;
input [2:0] irxen_in1, irxen_in0;
input itxen_in1, itxen_in0; 
input [1:0] indrv_in1, indrv_in0; 
input [1:0] ipdrv_in1, ipdrv_in0;
input async_dat_in1, async_dat_in0;

//output of input mux
output idata0_out; 
output idata1_out;
output idataselb_out;
output iddren_out;
output [2:0] irxen_out;
output itxen_out; 
output [1:0] indrv_out; 
output [1:0] ipdrv_out;
output async_dat_out;


//input of output mux
input odat0_in1, odat0_in0; 
input odat1_in1, odat1_in0;
input odat_async_in1, odat_async_in0;

//output of output mux
output odat0_out; 
output odat1_out;
output odat_async_out;

// Buses in the design


//input mux
assign idata0_out = shift_en? idata0_in1 : idata0_in0;
assign idata1_out = shift_en? idata1_in1 : idata1_in0;
assign idataselb_out = shift_en? idataselb_in1 : idataselb_in0 ;
assign iddren_out = shift_en? iddren_in1 : iddren_in0;
assign irxen_out[2] = shift_en? irxen_in1[2] : irxen_in0[2];
assign irxen_out[1] = shift_en? irxen_in1[1] : irxen_in0[1];
assign irxen_out[0] = shift_en? irxen_in1[0] : irxen_in0[0];
assign itxen_out = shift_en? itxen_in1 : itxen_in0;
assign indrv_out[1] = shift_en? indrv_in1[1] : indrv_in0[1];
assign indrv_out[0] = shift_en? indrv_in1[0] : indrv_in0[0];
assign ipdrv_out[1] = shift_en? ipdrv_in1[1] : ipdrv_in0[1];
assign ipdrv_out[0] = shift_en? ipdrv_in1[0] : ipdrv_in0[0];

//Change to CKMUX
//assign async_dat_out = shift_en? async_dat_in1 : async_dat_in0;

altr_hps_ckmux21 async_dat_out_ckmux (
                                        .clk_0(async_dat_in0),
                                        .clk_1(async_dat_in1),
                                        .clk_sel(shift_en),
                                        .clk_o(async_dat_out)
                                );


//output mux
assign odat0_out = shift_en? odat0_in1 : odat0_in0;
assign odat1_out = shift_en? odat1_in1 : odat1_in0;

//Change to CKMUX
//assign odat_async_out = shift_en? odat_async_in1 : odat_async_in0;

altr_hps_ckmux21 odat_async_out_ckmux (
                                        .clk_0(odat_async_in0),
                                        .clk_1(odat_async_in1),
                                        .clk_sel(shift_en),
                                        .clk_o(odat_async_out)
                                );

endmodule
module aibnd_cmos_nand_x1 (
input         in_p,
input         bk,
input         ci_p,
input         code_valid,
input         ck, nrst, se_n, si,
output        out_p, so,
output        co_p
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter   NAND_DELAY = 15; //min: 5ps; typ: 10ps; max: 20ps

reg    tp;

aibnd_str_ff xsync ( .se_n(se_n), .so(so), .si(si), .rb(nrst), .code_valid(code_valid), .clk(ck), .d(bk), .q(bk_sync));

assign #NAND_DELAY co_p  = ~(in_p & bk_sync);

always @(*)
  if (~in_p)    tp <= #NAND_DELAY 1'b1;
  else if (~bk_sync) tp <= #NAND_DELAY 1'b0;

assign #NAND_DELAY out_p = ~(tp & ci_p);

endmodule
module aibnd_fine_dly_inv ( a, o1, vcc_io, vss_io );

  input a;
  output o1;
  input vss_io;
  input vcc_io;


  assign o1 = ~a ;

endmodule
module aibnd_nor2 ( clkout, clk, en, vccl_aibnd, vssl_aibnd );

output  clkout;

input  clk, en, vccl_aibnd, vssl_aibnd;

// List of primary aliased buses

/*
specify 
    specparam CDS_LIBNAME  = "aibnd_lib";
    specparam CDS_CELLNAME = "aibnd_nor2";
    specparam CDS_VIEWNAME = "schematic";
endspecify
*/

assign clkout = ~( clk | en ) ;

endmodule
module aibnd_clkbuf ( clkout, vccl, vssl, clkin );

output  clkout;

inout  vccl, vssl;

input  clkin;

wire clkin, clkout; // Conversion Sript Generated

assign clkout = !clkin;

endmodule
module aibnd_nand_x128_delay_line ( out_p, vcc_io, vcc_regphy, vss_io,
     f_gray, i_gray, in_p );

output  out_p;

inout  vcc_io, vcc_regphy, vss_io;

input  in_p;

input [2:0]  i_gray;
input [6:0]  f_gray;



aibnd_cmos_nand_x128 xnand128 ( .vcc_io(vcc_io),
     .vcc_regphy(vcc_regphy), .vss_io(vss_io), .out_p(fout_p),
     .in_p(in_p), .gray(f_gray[6:0]));
aibnd_cmos_fine_dly  xfine ( //.vcc_io(vcc_io), .vss_io(vss_io),
     .gray(i_gray[2:0]), .out_p(out_p), .fout_p(fout_p)
     //.vcc_regphy(vcc_regphy)
     );

endmodule
module aibnd_avmm_rst_sync ( pcs_clk, pcs_clkb, resetb_sync_buf,
     avmm_clk, avmm_rstb, vccl_aibnd, vssl_aibnd );

output  pcs_clk, pcs_clkb, resetb_sync_buf;

input  avmm_clk, avmm_rstb, vccl_aibnd, vssl_aibnd;

wire gated_avmm_clk, pcs_clk, reset_b_sync, resetb_sync_buf, avmm_clk, avmm_clk_inv, pcs_clkb, clockgateb; // Conversion Sript Generated


// specify 
//     specparam CDS_LIBNAME  = "aibnd_lib";
//     specparam CDS_CELLNAME = "aibnd_avmm_rst_sync";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign pcs_clk = gated_avmm_clk;
assign resetb_sync_buf = reset_b_sync;
assign avmm_clk_inv = !avmm_clk;
assign pcs_clkb = !gated_avmm_clk;
aibnd_2ff_scan  xsync ( .d(vccl_aibnd), .clk(avmm_clk),     .o(reset_b_sync) /*`ifndef INTCNOPWR , .vcc(vccl_aibnd) `endif*/ , .rb(avmm_rstb),     .si(vssl_aibnd) /*`ifndef INTCNOPWR , .vss(vssl_aibnd) `endif*/ , .so(nc_so_sync),     .ssb(vccl_aibnd));
aibnd_ff_r  fyn0 ( .o(clockgateb), .d(vccl_aibnd),     .clk(avmm_clk_inv) /*`ifndef INTCNOPWR , .vss(vssl_aibnd) , .vcc(vccl_aibnd) `endif*/ ,     .rb(reset_b_sync));
assign gated_avmm_clk = avmm_clk & clockgateb;

endmodule
module aibnd_latch (
	input wire clk,
	input wire rb,
	//input wire vcc,
	//input wire vss,
	input wire d,
	output reg o
);

always@(*) begin
	if (!rb) begin
		o <= 0;
	end
	else begin
		if (clk)
			o <= d;
	end
end
endmodule
module aibnd_red_custom_dig ( anlg_rstb_out, anlg_rstb,
     prev_io_shift_en, shift_en, vccl_aibnd, vssl_aibnd );

output  anlg_rstb_out;

input  anlg_rstb, prev_io_shift_en, shift_en, vccl_aibnd, vssl_aibnd;

wire anlg_rstb_out, io_disable_b, anlg_rstb, prev_io_shenb, shift_en, prev_io_shift_en; // Conversion Sript Generated


// specify 
//     specparam CDS_LIBNAME  = "aibnd_lib";
//     specparam CDS_CELLNAME = "aibnd_red_custom_dig";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign anlg_rstb_out = io_disable_b & anlg_rstb;
assign io_disable_b = !(prev_io_shenb & shift_en);
assign prev_io_shenb = !prev_io_shift_en;

endmodule
module aibnd_dcc_helper ( clkout, clk_dcd, dcc_byp, launch, launchb,
     measure, measureb, rstb, vcc_io, vss_io );

output  clkout;

input  clk_dcd, dcc_byp, launch, launchb, measure, measureb, rstb,
     vcc_io, vss_io;

wire clk, sel, measure, launch, net074, clkout, datab, data, rb, reset, q, rstb, dcc_byp, net073; // Conversion Sript Generated


// specify 
//     specparam CDS_LIBNAME  = "aibnd_lib";
//     specparam CDS_CELLNAME = "aibnd_dcc_helper";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign clk = sel ? measure : launch;
aibnd_dcc_mux mbn2 ( .vcc_aibnd(vcc_io), .vss_aibnd(vss_io), .clk0(q),
     .s(net073), .clkout(net074), .clk1(clk_dcd));
assign clkout = net074;
an_io_phdet_ff_ln  x2 ( /*`ifndef INTCNOPWR .vcc(vcc_io), .vss(vss_io), `endif*/ .q(q), .clk_p(clk),
     .dn(datab), .dp(data), .rst_n(syncrstb));
assign datab = !data;
assign rb = !reset;
assign data = !q;
assign sel = !data;
assign reset = !rstb;
aibnd_2ff_scan  fyn1 ( .si(vss_io), .so(net035), .ssb(vcc_io),     .o(syncrstb), .d(vcc_io), .clk(launch) /*`ifndef INTCNOPWR , .vss(vss_io) , .vcc(vcc_io) `endif*/ , .rb(rb));
aibnd_2ff_scan  hgy0 ( .d(vss_io), .clk(measure), .o(net038) /*`ifndef INTCNOPWR , .vcc(vcc_io) `endif*/ , .rb(vss_io), .si(vss_io) /*`ifndef INTCNOPWR , .vss(vss_io) `endif*/ , .so(net036),     .ssb(vcc_io));
assign net073 = dcc_byp;

endmodule
module aibnd_dcc_fine_dly ( out_p, therm_dn, therm_up, thermb_dn,
     thermb_up, vcc_pl, vss_pl, fout_p );

output  out_p;

inout  vcc_pl, vss_pl;

input  fout_p;

output [14:0]  therm_dn;
output [14:0]  thermb_dn;
output [14:0]  thermb_up;
output [14:0]  therm_up;

// Buses in the design

wire  [0:2]  net040;

aibnd_dcc_dly_inv inn1[2:0] ( .o1(cap_node1), .a(cap_node),
     .vcc_io(vcc_pl), .vss_io(vss_pl));
aibnd_dcc_dly_inv inn3[2:0] ( .o1(out_p), .a(net040[0:2]),
     .vcc_io(vcc_pl), .vss_io(vss_pl));
aibnd_dcc_dly_inv inn2[2:0] ( .o1(cap_node2), .a(cap_node1),
     .vcc_io(vcc_pl), .vss_io(vss_pl));
aibnd_dcc_dly_inv inn5[2:0] ( .o1(cap_node3), .a(cap_node2),
     .vcc_io(vcc_pl), .vss_io(vss_pl));
aibnd_dcc_dly_inv inn4[2:0] ( .o1(net040[0:2]), .a(cap_node3),
     .vcc_io(vcc_pl), .vss_io(vss_pl));
aibnd_dcc_dly_inv inn0[2:0] ( .o1(cap_node), .a(fout_p),
     .vcc_io(vcc_pl), .vss_io(vss_pl));
aibnd_dcc_fine_dly_x1 x119[14:0] ( .dout(cap_node2),
     .vcc_regphy(vcc_pl), .vss_io(vss_pl), .sn(therm_up[14:0]),
     .sp(thermb_up[14:0]));
aibnd_dcc_fine_dly_x1 x118[14:0] ( .dout(cap_node2),
     .vcc_regphy(vcc_pl), .vss_io(vss_pl), .sn(therm_dn[14:0]),
     .sp(thermb_dn[14:0]));
aibnd_dcc_fine_dly_x1 x114[14:0] ( .dout(cap_node1),
     .vcc_regphy(vcc_pl), .vss_io(vss_pl), .sn(therm_dn[14:0]),
     .sp(thermb_dn[14:0]));
aibnd_dcc_fine_dly_x1 x116[14:0] ( .dout(cap_node3),
     .vcc_regphy(vcc_pl), .vss_io(vss_pl), .sn(therm_up[14:0]),
     .sp(thermb_up[14:0]));
aibnd_dcc_fine_dly_x1 x115[14:0] ( .dout(cap_node1),
     .vcc_regphy(vcc_pl), .vss_io(vss_pl), .sn(therm_up[14:0]),
     .sp(thermb_up[14:0]));
aibnd_dcc_fine_dly_x1 xup[14:0] ( .dout(cap_node), .vcc_regphy(vcc_pl),
     .vss_io(vss_pl), .sn(therm_up[14:0]), .sp(thermb_up[14:0]));
aibnd_dcc_fine_dly_x1 xdn[14:0] ( .dout(cap_node), .vcc_regphy(vcc_pl),
     .vss_io(vss_pl), .sn(therm_dn[14:0]), .sp(thermb_dn[14:0]));
aibnd_dcc_fine_dly_x1 x117[14:0] ( .dout(cap_node3),
     .vcc_regphy(vcc_pl), .vss_io(vss_pl), .sn(therm_dn[14:0]),
     .sp(thermb_dn[14:0]));

endmodule
module aibnd_dcc_sense ( up, vcc_io, vcc_regphy, vss_io, clk_dcc,
     dll_reset_n, nfrzdrv, pvt_ref_half_gry );

output  up;

inout  vcc_io, vcc_regphy, vss_io;

input  clk_dcc, dll_reset_n, nfrzdrv;

input [9:0]  pvt_ref_half_gry;

wire up, net018, net022, net025; // Conversion Sript Generated



io_split_align  xsplit_align_0 ( 
     //.vcc_io(vcc_regphy), .vss_io(vss_io),
     .dout_n(clk_dcd_split_n), .dout_p(clk_dcd_split_p),
     .din(clk_dcc));
assign up = !net018;
assign net022 = !net025;
io_nand_delay_line_min  xdelay_line_match ( .nfrzdrv(nfrzdrv),
     //.vcc_regphy(vcc_regphy), .vcc_io(vcc_io), .vss_io(vss_io),
     .out_n(clkn_mindly), .out_p(clkp_mindly), .in_n(clk_dcd_split_n),
     .in_p(clk_dcd_split_p));
an_io_phdet_ff  xsampling ( /*`ifndef INTCNOPWR .vcc(vcc_io), .vss(vss_io), `endif*/ 
     .q(net018),
     .clk_p(clkp_dly), .dn(clkn_mindly), .dp(clkp_mindly),
     .rst_n(dll_reset_n));
an_io_phdet_ff  xload_match ( /*`ifndef INTCNOPWR .vcc(vcc_io), .vss(vss_io), `endif*/ 
    .q(net025),
     .clk_p(clkp_mindly), .dn(clkn_dly), .dp(clkp_dly),
     .rst_n(dll_reset_n));
io_nand_x128_delay_line  xdelay_line ( 
     //.vcc_io(vcc_io),
     //.vcc_regphy(vcc_regphy), .vss_io(vss_io),
     .i_gray(pvt_ref_half_gry[2:0]), .f_gray(pvt_ref_half_gry[9:3]),
     .out_n(clkn_dly), .out_p(clkp_dly), .osc_out_n(net014),
     .osc_out_p(net015), .osc_in_n(vcc_io), .osc_in_p(vss_io),
     .osc_mode(vss_io), .in_n(clk_dcd_split_n), .in_p(clk_dcd_split_p),
     .nfrzdrv(nfrzdrv));

endmodule
module aibnd_2ff_scan (
	input wire clk,
	input wire d,
	output wire o,
	input wire rb,
	input wire si,
	output wire so,
	input wire ssb
);

	wire mgm_d2_row1;
	wire mgm_d2_row2;
	wire mgm_d2_row3;
	
	wire q1, q2, q3, q4;

	assign o = !q1;
	//assign q1_inv = !q1;
	assign so = !q1 & !ssb;
	
	//assign d_inv	= !d;
	//assign si_inv	= !si_inv;
	//assign ssb_inv	= !ssb; 
	
	assign mgm_d2_row1 = !d & !si; 
	assign mgm_d2_row2 = !d & ssb;
	assign mgm_d2_row3 = !si & !ssb;
	
	assign mgm_d2 = mgm_d2_row1 | mgm_d2_row2 | mgm_d2_row3;	

aibnd_hgy_latch aibnd_hgy_latch_inst0 (
	.q (q1),
	.set (1'b0),
	.preset (!rb),
	.clk (clk),
	.d (!q4)
);

aibnd_hgy_latch aibnd_hgy_latch_inst1 (
	.q (q2),
	.set (1'b0),
	.preset (!rb),
	.clk (clk),
	.d (q3)
);

aibnd_hgy_latch aibnd_hgy_latch_inst2 (
	.q (q3),
	.set (1'b0),
	.preset (!rb),
	.clk (!clk),
	.d (mgm_d2)
);

aibnd_hgy_latch aibnd_hgy_latch_inst3 (
	.q (q4),
	.set (!rb),
	.preset (1'b0),
	.clk (!clk),
	.d (!q2)
);

endmodule
module aibnd_txdat_mimic (
	input wire vccl_aibnd,
	input wire vssl_aibnd,
	input wire idata_in,
	output wire idata_out
);

assign idata_out = idata_in;

endmodule
module aibnd_inv_split_align ( din, dout, vccl, vssl );

  input din;
  output dout;
  input vssl;
  input vccl;


  assign dout = ~din ;

endmodule
module aibnd_2to4dec ( nsel_out0b, nsel_out1b, nsel_out2b, nsel_out3b,
     psel_out0, psel_out1, psel_out2, psel_out3, enable, nsel_in,
     psel_in, vccl_aibnd, vssl_aibnd );

output  nsel_out0b, nsel_out1b, nsel_out2b, nsel_out3b, psel_out0,
     psel_out1, psel_out2, psel_out3;

input  enable, vccl_aibnd, vssl_aibnd;

input [1:0]  psel_in;
input [1:0]  nsel_in;

wire psel_out1, psel0_en, psel_out2, nsel0_en, enable, psel_out3, nsel1_en, nsel_out2b, nsel_out1b, nsel_out3b, psel_out0, nsel_out0b; // Conversion Sript Generated



assign psel_out1 = psel0_en | psel_out2;
assign nsel0_en = nsel_in[0] & enable;
assign psel_out2 = psel_in[1] & enable;
assign psel0_en = psel_in[0] & enable;
assign psel_out3 = enable & psel_in[0] & psel_in[1];
assign nsel1_en = !nsel_out2b;
assign nsel_out2b = !(nsel_in[1] & enable);
assign nsel_out1b = !(nsel0_en | nsel1_en);
assign nsel_out3b = !(enable & nsel_in[0] & nsel_in[1]);
assign psel_out0 = !nsel_out0b;
assign nsel_out0b = !enable;

endmodule
module aibnd_rxdat_mimic (
	input wire vccl_aibnd,
	input wire vssl_aibnd,
	input wire odat_in,
	output wire odat_out
);

assign odat_out = odat_in;

endmodule
module aibnd_clkmux2 ( mux_sel, oclk_in1, oclk_in0, oclk_out );

output  oclk_out;

input  oclk_in1, oclk_in0, mux_sel;

// List of primary aliased buses

/*
specify 
    specparam CDS_LIBNAME  = "aibnd_lib";
    specparam CDS_CELLNAME = "aibnd_red_clkmux2";
    specparam CDS_VIEWNAME = "schematic";
endspecify
*/

assign oclk_out = mux_sel ?  oclk_in1 : oclk_in0 ;


endmodule
module aibnd_quadph_code_gen 
#(
parameter FF_DELAY     = 200
)
(
   input  wire         clk,                     //reference clock from pll
   input  wire         reset_n,                 //output for dll reset
   input  wire  [9:0]  pvt_ref_binary,          //output binary pvt value for delay chain
   input  wire         rb_quad_code,   		//select between original or quadrature codes
   output reg   [9:0]  pvt_ref_quad_binary 	//quadrature code (binary) for delay chain
);

`ifdef TIMESCALE_EN
  timeunit 1ps;
  timeprecision 1ps;
`endif

wire [6:0] coarse_bin;
reg [2:0]  fint_bin;
wire [2:0] fine_bin;

reg [8:0]  coarse_divided_bin;
reg [4:0]  fine_divided_bin, coarse_frac_bin;

          always @(*)
                begin
                        if(~reset_n) begin
                                coarse_divided_bin = 9'b0_0000_0000;
                                fine_divided_bin = 5'b0_0000;
                                coarse_frac_bin = 5'b0_0000;
                                fint_bin = 3'b000;
                        end
                        else  begin
                                coarse_divided_bin = {2'b00,pvt_ref_binary[9:3]};
                                fine_divided_bin = {2'b00,pvt_ref_binary[2:0]};
//                                coarse_frac_bin = {1'b0,coarse_divided_bin[1:0],2'b00};  //****need to finalize what's the ratio between coarse/fine steps. current coding assumes 20ps/5ps=4
				coarse_frac_bin = {coarse_divided_bin[1:0],3'b000}; 
                                fint_bin = coarse_frac_bin[4:2] + fine_divided_bin[4:2];
                                         if ((fine_divided_bin[1:0] >= 2'd2)) begin
                                                fint_bin = fint_bin + 3'b001;
                                         end
                                         else begin
                                                fint_bin = fint_bin;
                                         end
                         end
                end

        assign coarse_bin = coarse_divided_bin[8:2];
 	assign fine_bin = fint_bin;

        always @(posedge clk or negedge reset_n)
                begin
                        if(~reset_n) begin
				pvt_ref_quad_binary <= #FF_DELAY 10'b00_0000_0000;
			end
			else case (rb_quad_code)
				1'b0 : pvt_ref_quad_binary <= #FF_DELAY pvt_ref_binary;
				1'b1 : pvt_ref_quad_binary <= #FF_DELAY {coarse_bin,fine_bin};
				default : pvt_ref_quad_binary <= #FF_DELAY {coarse_bin,fine_bin};
			endcase
		end 

endmodule // aibnd_quadph_code_gen
module aibnd_str_clktree_mimic 
#(
parameter SKEW_DELAY     = 60   //min:20ps; typ :60ps; max:100ps
)
(
   input  wire         clkin,                   //clock source
   output wire 	       lstrbclk_l_0, 	        //buffered clock
   output wire         lstrbclk_l_1,            //buffered clock
   output wire         lstrbclk_l_2,            //buffered clock
   output wire         lstrbclk_l_3,            //buffered clock
   output wire         lstrbclk_l_4,            //buffered clock
   output wire         lstrbclk_l_5,            //buffered clock
   output wire         lstrbclk_l_6,            //buffered clock
   output wire         lstrbclk_l_7,            //buffered clock
   output wire         lstrbclk_l_8,            //buffered clock
   output wire         lstrbclk_l_9,            //buffered clock
   output wire         lstrbclk_l_10,           //buffered clock
   output wire         lstrbclk_l_11,           //buffered clock
   output wire         lstrbclk_rep, 	        //replica for DLL
   output wire         lstrbclk_mimic0         //mimic path for load matching
);

`ifdef TIMESCALE_EN
  timeunit 1ps;
  timeprecision 1ps;
`endif
  
                assign #SKEW_DELAY lstrbclk_l_0 = clkin;
                assign #SKEW_DELAY lstrbclk_l_1 = clkin;
                assign #SKEW_DELAY lstrbclk_l_2 = clkin;
                assign #SKEW_DELAY lstrbclk_l_3 = clkin;
                assign #SKEW_DELAY lstrbclk_l_4 = clkin;
                assign #SKEW_DELAY lstrbclk_l_5 = clkin;
                assign #SKEW_DELAY lstrbclk_l_6 = clkin;
                assign #SKEW_DELAY lstrbclk_l_7 = clkin;
                assign #SKEW_DELAY lstrbclk_l_8 = clkin;
                assign #SKEW_DELAY lstrbclk_l_9 = clkin;
                assign #SKEW_DELAY lstrbclk_l_10 = clkin;
                assign #SKEW_DELAY lstrbclk_l_11 = clkin;
                assign #SKEW_DELAY lstrbclk_rep = clkin;
                assign #SKEW_DELAY lstrbclk_mimic0 = clkin;

endmodule // aibnd_str_clktree_mimic
module aibnd_aliasd ( PLUS, MINUS );

	input   PLUS;
	output  MINUS;

	assign MINUS = PLUS;

endmodule
module aibnd_dcc_4bupcnt ( full, q0, q1, q2, q3, vcc_pl, vss_pl, clk,
     dir, hold, nrst );

output  full, q0, q1, q2, q3;

inout  vcc_pl, vss_pl;

input  clk, dir, hold, nrst;

wire net066, q1b, q0b, net057, q3b, net038, net034, q1, net042, q3, q2, net063, q0, net040, net039, net065, net036, net092, net089, net064, net048, q2b, net090, net062, ck, dir, clk, hld, holdb, net087, net059, net017, full, hold, net072, net060, net018, net099, net091; // Conversion Sript Generated

assign net066 = !(q1b & q0b);
assign net057 = !(q3b & net038);
assign net034 = !(q1 & q0b);
assign net042 = !(q3 & q2);
assign net063 = !(q1b & q0);
assign net040 = !(q2 & q0b);
assign net039 = !(q2 & q1b);
assign net065 = !(q1 & q0b);
assign net038 = !(q2 & q1 & q0);
assign net036 = !(q3 & q2 & q1);
assign net092 = !(net063 & net034 & net036);
assign net089 = !(net066 & net065 & net064);
assign net064 = !(q3 & q2 & q1);
assign net048 = !(q2b & q1 & q0);
assign net090 = !(net042 & net039 & net040 & net040);
assign net062 = !(q3 & q2 & q1 & q1);
assign ck = !(dir & clk);
assign hld = !(dir & holdb);
assign q0b = !net087;
assign q3b = !net059;
assign q2b = !net017;
assign full = !net062;
assign holdb = !hold;
assign q1b = !net072;
assign q3 = !q3b;
assign q2 = !q2b;
assign q0 = !q0b;
assign q1 = !q1b;
aibnd_dcc_ff x102 ( .q(net059), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck),
     .d(net060), .vss_pl(vss_pl));
aibnd_dcc_ff xreg2 ( .q(net017), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck),
     .d(net091), .vss_pl(vss_pl));
aibnd_dcc_ff xreg0 ( .q(net087), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck),
     .d(net018), .vss_pl(vss_pl));
aibnd_dcc_ff xreg1 ( .q(net072), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck),
     .d(net099), .vss_pl(vss_pl));
assign net060 = hld ? q3 : net057;
assign net018 = hld ? q0 : net089;
assign net099 = hld ? q1 : net092;
assign net091 = hld ? q2 : net090;

endmodule
module aibnd_analog ( oclkn, oclkp, odat, odat_async, iopad, clk_en,
     data_en, iclkn, ndrv_enb, pdrv_en, txdin, vccl_aibnd, vssl_aibnd,
     weak_pulldownen, weak_pullupenb );

output  oclkn, oclkp, odat, odat_async;

inout  iopad;

input  clk_en, data_en, iclkn, txdin, vccl_aibnd, vssl_aibnd,
     weak_pulldownen, weak_pullupenb;

input [15:0]  pdrv_en;
input [15:0]  ndrv_enb;



aibnd_txanlg  xtxbuf ( .vssl_aibnd(vssl_aibnd),
     .vccl_aibnd(vccl_aibnd), .ndrv_enb(ndrv_enb[15:0]),
     .weak_pullupenb(weak_pullupenb), .txpadout(iopad), .din(txdin),
     .pdrv_en(pdrv_en[15:0]), .weak_pulldownen(weak_pulldownen));
aibnd_rxanlg  xrxbuf ( .vssl_aibnd(vssl_aibnd),
     .vccl_aibnd(vccl_aibnd), .odat_async(odat_async),
     .data_en(data_en), .clk_en(clk_en), .odat(odat), .oclkn(oclkn),
     .oclkp(oclkp), .iopad(iopad), .iclkn(iclkn));
aibnd_d8xsesdd1  xesd1 ( .vssl_aibnd(vssl_aibnd),
     .vccl_aibnd(vccl_aibnd), .iopad(iopad));
aibnd_d8xsesdd2  xesd2 ( .vssl_aibnd(vssl_aibnd),
     .vccl_aibnd(vccl_aibnd), .iopad(iopad));

endmodule