dakies/OSS_Verilog huggingface dataset:
module bus_control_test ();

	reg CLK;
	wire PHI1, PHI2;
	always #25 CLK = ~CLK;

	ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );

	wire ZTST, PGX;

	Bus_Control bus_control (
		.PHI1(PHI1),
		.PHI2(PHI2),
		.n_SBXY(1'b1), 
		.AND(1'b0), 
		.STOR(1'b0), 
		.Z_ADL0(1'b0), 
		.ACRL2(1'b0), 
		.DL_PCH(1'b0), 
		.n_ready(1'b0), 
		.INC_SB(1'b0), 
		.BRK6E(1'b0), 
		.STXY(1'b0), 
		.n_PCH_PCH(1'b1),
		.T0(1'b0), 
		.T1(1'b0), 
		.T6(1'b0), 
		.T7(1'b0), 
		.BR0(1'b0), 
		.X({130{1'b0}}),
		.ZTST(ZTST), 
		.PGX(PGX) );

	initial begin

		$dumpfile("bus_control_test.vcd");
		$dumpvars(0, bus_control_test);

		CLK <= 1'b0;

		repeat (256) @ (posedge CLK);
		$finish;
	end

endmodule // bus_control_test
module branch_logic_test ();

	reg CLK;
	wire PHI1, PHI2;
	always #25 CLK = ~CLK;

	ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );

	wire [7:0] DB;
	wire n_BRTAKEN, BRFW;

	BranchLogic branch_logic (
		.PHI1(PHI1), 
		.PHI2(PHI2),
		.n_IR5(1'b1), 
		.X({130{1'b0}}), 
		.n_COUT(1'b1), 
		.n_VOUT(1'b1), 
		.n_NOUT(1'b1), 
		.n_ZOUT(1'b1), 
		.DB(DB), 
		.BR2(1'b0),
		.n_BRTAKEN(n_BRTAKEN), 
		.BRFW(BRFW) );

	initial begin

		$dumpfile("branch_logic_test.vcd");
		$dumpvars(0, branch_logic_test);

		CLK <= 1'b0;

		repeat (256) @ (posedge CLK);
		$finish;
	end

endmodule // branch_logic_test
module flags_test ();

	reg CLK;
	wire PHI1, PHI2;
	always #25 CLK = ~CLK;

	ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );

	wire [7:0] DB;

	Flags flags (
		.PHI1(PHI1), 
		.PHI2(PHI2),
		.P_DB(1'b0), 
		.DB_P(1'b0), 
		.DBZ_Z(1'b0), 
		.DB_N(1'b0), 
		.IR5_C(1'b0), 
		.DB_C(1'b0), 
		.ACR_C(1'b0), 
		.IR5_D(1'b0), 
		.IR5_I(1'b0), 
		.DB_V(1'b0), 
		.Z_V(1'b0),
		.ACR(1'b0), 
		.AVR(1'b0), 
		.B_OUT(1'b0), 
		.n_IR5(1'b0), 
		.BRK6E(1'b0), 
		.Dec112(1'b0), 
		.SO_frompad(1'b0), 
		.DB(DB) );

	initial begin

		$dumpfile("flags_test.vcd");
		$dumpvars(0, flags_test);

		CLK <= 1'b0;

		repeat (256) @ (posedge CLK);
		$finish;
	end

endmodule // flags_test
module clock_test ();

	reg CLK;
	always #25 CLK = ~CLK;

	wire PHI1, PHI2, PHI1_topad, PHI2_topad;

	ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2), .PHI1_topad(PHI1_topad), .PHI2_topad(PHI2_topad) );

	initial begin

		$dumpfile("clock_test.vcd");
		$dumpvars(0, clock_test);

		CLK <= 1'b0;

		repeat (256) @ (posedge CLK);
		$finish;
	end

endmodule // clock_test
module alu_test ();

	reg CLK;
	wire PHI1, PHI2;
	always #25 CLK = ~CLK;

	ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );

	wire [7:0] SB, DB, ADL, ADH;
	wire ACR, AVR;

	ALU alu (
		.PHI2(PHI2),
		.NDB_ADD(1'b0), 
		.DB_ADD(1'b0), 
		.Z_ADD(1'b0), 
		.SB_ADD(1'b0), 
		.ADL_ADD(1'b0), 
		.ADD_SB06(1'b0), 
		.ADD_SB7(1'b0), 
		.ADD_ADL(1'b0),
		.ANDS(1'b0), 
		.EORS(1'b0), 
		.ORS(1'b0), 
		.SRS(1'b0), 
		.SUMS(1'b0), 
		.SB_AC(1'b0), 
		.AC_SB(1'b0), 
		.AC_DB(1'b0), 
		.SB_DB(1'b0), 
		.SB_ADH(1'b0), 
		.Z_ADH0(1'b0), 
		.Z_ADH17(1'b0),
		.n_ACIN(1'b1), 
		.n_DAA(1'b1), 
		.n_DSA(1'b1),
		.SB(SB), 
		.DB(DB), 
		.ADL(ADL), 
		.ADH(ADH),
		.ACR(ACR), 
		.AVR(AVR) );

	initial begin

		$dumpfile("alu_test.vcd");
		$dumpvars(0, alu_test);

		CLK <= 1'b0;

		repeat (256) @ (posedge CLK);
		$finish;
	end

endmodule // alu_test
module predecode_test ();

	reg CLK;
	wire PHI1, PHI2;
	always #25 CLK = ~CLK;

	ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );

	wire [7:0] Data_bus, n_PD;
	wire n_IMPLIED, n_TWOCYCLE;

	PreDecode predecode (
		.PHI2(PHI2),
		.Z_IR(1'b0),
		.Data_bus(Data_bus), 
		.n_PD(n_PD),
		.n_IMPLIED(n_IMPLIED), 
		.n_TWOCYCLE(n_TWOCYCLE) );

	initial begin

		$dumpfile("predecode_test.vcd");
		$dumpvars(0, predecode_test);

		CLK <= 1'b0;

		repeat (256) @ (posedge CLK);
		$finish;
	end

endmodule // predecode_test
module dispatch_test ();

	reg CLK;
	wire PHI1;
	wire PHI2;

	always #25 CLK = ~CLK;

	wire [7:0] DataBus;

	wire Z_IR;
	wire [7:0] n_PD;
	wire n_IMPLIED;
	wire n_TWOCYCLE;
	wire TRES2;
	wire n_ready;
	wire T0;
	wire T1;
	wire n_T2;
	wire n_T3;
	wire n_T4;
	wire n_T5;
	wire FETCH;
	wire IR01;
	wire [7:0] IR;
	wire [7:0] n_IR;
	wire [129:0] X;

	ClkGen clk (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2));

	PreDecode predecode (
		.PHI2(PHI2),
		.Z_IR(Z_IR),
		.Data_bus(DataBus), .n_PD(n_PD),
		.n_IMPLIED(n_IMPLIED), .n_TWOCYCLE(n_TWOCYCLE));

	ExtraCounter extra_counter (
		.PHI1(PHI1), .PHI2(PHI2), .TRES2(TRES2), .n_ready(n_ready), .T1(T1),
		.n_T2(n_T2), .n_T3(n_T3), .n_T4(n_T4), .n_T5(n_T5));

	IR ir (
		.PHI1(PHI1), .PHI2(PHI2),
		.n_PD(n_PD), .FETCH(FETCH),
		.IR01(IR01), .IR_out(IR), .n_IR_out(n_IR));

	Decoder decoder (
		.n_T0(n_T0), .n_T1X(n_T1X),
		.n_T2(n_T2), .n_T3(n_T3), .n_T4(n_T4), .n_T5(n_T5), 
		.IR01(IR01),
		.IR(IR), .n_IR(n_IR),
		.X(X));

	Dispatch dispatch (
		.PHI1(PHI1), .PHI2(PHI2),
		.BRK6E(1'b0), .RESP(1'b0), .ACR(1'b0), .DORES(1'b0), .PC_DB(1'b0), .RDY(1'b1), .B_OUT(1'b1), .BRFW(1'b0), .n_BRTAKEN(1'b0),
		.n_TWOCYCLE(n_TWOCYCLE), .n_IMPLIED(n_IMPLIED), .n_ADL_PCL(1'b0), 
		.X(X), 
		.TRES2(TRES2), .Z_IR(Z_IR), .FETCH(FETCH), .n_ready(n_ready), .T1(T1), .n_T0(n_T0), .T0(T0), .n_T1X(n_T1X));

	MemoryDevice mem (.DataBus(DataBus));

	initial begin

		$dumpfile("dispatch_test.vcd");
		$dumpvars(0, dispatch_test);

		CLK <= 1'b0;

		repeat (32) @ (posedge CLK);

		$finish;
	end

endmodule // dispatch_test
module MemoryDevice (DataBus);

	inout [7:0] DataBus;

	assign DataBus = 8'h8D; 	// STA abs

endmodule // MemoryDevice
module ir_test ();

	reg CLK;
	reg FETCH;
	wire PHI1;
	wire PHI2;

	always #1 CLK = ~CLK;

	ClkGen clk (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2));

	IR ir (
		.PHI1(PHI1), .PHI2(PHI2),
		.n_PD(8'ha5), .FETCH(FETCH) );

	initial begin

		$dumpfile("ir_test.vcd");
		$dumpvars(0, ir_test);

		CLK <= 1'b0;
		FETCH <= 1'b0;

		repeat (8) @ (posedge CLK);

		FETCH <= 1'b1;
		repeat (8) @ (posedge CLK);

		FETCH <= 1'b0;
		repeat (8) @ (posedge CLK);

		$finish;
	end

endmodule // ir_test
module brk_test ();

	reg CLK;
	wire PHI1, PHI2;
	always #25 CLK = ~CLK;

	ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );

	wire BRK6E, BRK7, BRK5_RDY, DORES, n_DONMI, B_OUT;

	BRKProcessing brk (
		.PHI1(PHI1),
		.PHI2(PHI2),
		.BRK5(1'b0), 
		.n_ready(1'b0), 
		.RESP(1'b0), 
		.n_NMIP(1'b1), 
		.BR2(1'b0), 
		.T0(1'b0), 
		.n_IRQP(1'b1), 
		.n_IOUT(1'b1),
		.BRK6E(BRK6E), 
		.BRK7(BRK7), 
		.BRK5_RDY(BRK5_RDY), 
		.DORES(DORES), 
		.n_DONMI(n_DONMI), 
		.B_OUT(B_OUT) );

	wire Z_ADL0, Z_ADL1, Z_ADL2;

	IntVector intaddr (
		.PHI2(PHI2),
		.BRK5_RDY(BRK5_RDY),
		.BRK7(BRK7),
		.DORES(DORES),
		.n_DONMI(n_DONMI),
		.Z_ADL0(Z_ADL0),
		.Z_ADL1(Z_ADL1),
		.Z_ADL2(Z_ADL2) );

	initial begin

		$dumpfile("brk_test.vcd");
		$dumpvars(0, brk_test);

		CLK <= 1'b0;

		repeat (256) @ (posedge CLK);
		$finish;
	end

endmodule // brk_test
module regs_control_test ();

	reg CLK;
	wire PHI1, PHI2;
	always #25 CLK = ~CLK;

	ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );

	wire STXY, n_SBXY, STKOP;

	Regs_Control regs_control (
		.PHI1(PHI1), 
		.PHI2(PHI2), 
		.STOR(1'b0), 
		.n_ready(1'b0), 
		.X({130{1'b0}}),
		.STXY(STXY), 
		.n_SBXY(n_SBXY), 
		.STKOP(STKOP) );

	initial begin

		$dumpfile("regs_control_test.vcd");
		$dumpvars(0, regs_control_test);

		CLK <= 1'b0;

		repeat (256) @ (posedge CLK);
		$finish;
	end

endmodule // regs_control_test
module pc_control_test ();

	reg CLK;
	wire PHI1, PHI2;
	always #25 CLK = ~CLK;

	ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );

	PC_Control pc_control (
		.PHI1(PHI1), 
		.PHI2(PHI2),
		.n_ready(1'b0), 
		.T0(1'b0), 
		.T1(1'b0), 
		.BR0(1'b0),
		.X({130{1'b0}}) );

	initial begin

		$dumpfile("pc_control_test.vcd");
		$dumpvars(0, pc_control_test);

		CLK <= 1'b0;

		repeat (256) @ (posedge CLK);
		$finish;
	end

endmodule // pc_control_test
module pc_test ();

	reg CLK;
	wire PHI1, PHI2;
	always #25 CLK = ~CLK;

	ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );

	wire [7:0] ADL, ADH, DB;

	PC pc (
		.PHI2(PHI2),
		.n_IPC(1'b0),
		.ADL_PCL(1'b0), 
		.PCL_PCL(1'b1), 
		.PCL_ADL(1'b0), 
		.PCL_DB(1'b0), 
		.ADH_PCH(1'b0), 
		.PCH_PCH(1'b1), 
		.PCH_ADH(1'b0), 
		.PCH_DB(1'b0),
		.ADL(ADL), 
		.ADH(ADH), 
		.DB(DB) );

	// Single bit

/*
	wire AD_bit, DB_bit;

	pc_carry pc_bit (
		.PHI2(PHI2), 
		.carry(1'b1), 
		.AD(AD_bit), 
		.DB(DB_bit), 
		.PC_AD(1'b0), 
		.PC_DB(1'b0), 
		.AD_PC(1'b0), 
		.PC_PC(1'b1) );
*/

	initial begin

		$dumpfile("pc_test.vcd");
		$dumpvars(0, pc_test);

		CLK <= 1'b0;

		repeat (256) @ (posedge CLK);
		$finish;
	end

endmodule // pc_test
module AdderExtModule(
  input [15:0] foo,
  output [15:0] bar
);
  assign bar = foo + 1;
endmodule
module SimpleExtModule(
  input [15:0] foo,
  output [15:0] bar
);
  assign bar = foo;
endmodule
module LargeParam #(parameter DATA=0, WIDTH=1) (
  output [WIDTH-1:0] out
);
  assign out = DATA;
endmodule
module ParameterizedViaHeaderAdderExtModule(
  input [15:0] foo,
  output [15:0] bar
);
  `include "VerilogHeaderFile.vh"
  assign bar = foo + VALUE;
endmodule
module mem_ctrl(
  input clock,

  input        sdram_valid, 
  input [3:0]  sdram_data_i,
  input        flash_valid,
  input [7:0]  flash_data_i,

  output       sdram_ready,
  output       flash_ready,

  output       out_valid,
  output [7:0] out_data
);

  reg[1:0] state_sdram; // READY, RECEIVING, BUSY
  reg      state_flash; // READY, BUSY

  reg[7:0] data_sdram;
  reg[7:0] data_flash;

/********** combinational **********/

  assign sdram_ready = (state_sdram != `BUSY_S);
  assign flash_ready = (state_flash != `BUSY_F);

  assign out_valid = (state_sdram == `BUSY_S) ||
                      (state_flash == `BUSY_F);
  assign out_data = (state_sdram == `BUSY_S) ?
                      data_sdram : data_flash;

/********** sequential **********/

  always @(posedge clock) begin
    if (state_sdram == `READY_S) begin
      if (sdram_valid) begin
        state_sdram <= `PENDING_S;
        data_sdram <= {4'b0000, sdram_data_i};
      end
    end else if (state_sdram == `PENDING_S) begin
      if (sdram_valid) begin
        state_sdram <= `BUSY_S;
        data_sdram <= {sdram_data_i, 4'b0000} | data_sdram;
      end
    end else if (state_sdram == `BUSY_S) begin
      state_sdram <= `PENDING_S;
    end

    if (state_flash == `READY_F) begin
      if (flash_valid) begin
        state_flash <= `BUSY_F;
        data_flash <= flash_data_i;
      end
    end else if (state_flash == `BUSY_F) begin
      state_flash <= `READY_F;
    end
  end
endmodule
module saturating_counter(
  input clock,
  input reset,

  input signal,
  output toggled
);

reg count;
reg last;

assign toggled = count;

always @(posedge clock) begin
  if (reset) begin
    count <= 0;
  end else if (last ^ signal) begin
    count <= 1;
  end

  last <= signal;
end
endmodule
module mem_ctrl(
  input clock,
  input reset,

  input        sdram_valid, 
  input [3:0]  sdram_data_i,
  input        flash_valid,
  input [7:0]  flash_data_i,

  output       sdram_ready,
  output       flash_ready,

  output       out_valid,
  output [7:0] out_data,

  output [2:0] coverage,
  output bug
);

  reg[1:0] state_sdram; // READY, RECEIVING, BUSY
  reg      state_flash; // READY, BUSY

  reg[7:0] data_sdram;
  reg[7:0] data_flash;

/********** combinational **********/

  assign sdram_ready = (state_sdram != `BUSY_S);
  assign flash_ready = (state_flash != `BUSY_F);

  assign out_valid = (state_sdram == `BUSY_S) ||
                      (state_flash == `BUSY_F);
  assign out_data = (state_sdram == `BUSY_S) ?
                      data_sdram : data_flash;

/********** sequential **********/

  always @(posedge clock) begin
    if (state_sdram == `READY_S) begin
      if (sdram_valid) begin
        state_sdram <= `PENDING_S;
        data_sdram <= {4'b0000, sdram_data_i};
      end
    end else if (state_sdram == `PENDING_S) begin
      if (sdram_valid) begin
        state_sdram <= `BUSY_S;
        data_sdram <= {sdram_data_i, 4'b0000} | data_sdram;
      end
    end else if (state_sdram == `BUSY_S) begin
      state_sdram <= `PENDING_S;
    end

    if (state_flash == `READY_F) begin
      if (flash_valid) begin
        state_flash <= `BUSY_F;
        data_flash <= flash_data_i;
      end
    end else if (state_flash == `BUSY_F) begin
      state_flash <= `READY_F;
    end
  end
endmodule
module des3(desOut, desIn, key1, key2, key3, decrypt, MY_CLK); 
output	[63:0]	desOut;
input	[63:0]	desIn;
input	[55:0]	key1;
input	[55:0]	key2;
input	[55:0]	key3;
input		decrypt;
input		MY_CLK;

wire	[55:0]	key_a;
wire	[55:0]	key_b;
wire	[55:0]	key_c;
wire	[63:0]	stage1_out, stage2_out;
reg	[55:0]	key_b_r [16:0];
reg	[55:0]	key_c_r [33:0];
integer		i;

assign key_a = decrypt ? key3 : key1;
assign key_b = key2;
assign key_c = decrypt ? key1 : key3;

always @(posedge MY_CLK)
	key_b_r[0] <= #1 key_b;

always @(posedge MY_CLK)
	for(i=0;i<16;i=i+1)
		key_b_r[i+1] <= #1 key_b_r[i];


always @(posedge MY_CLK)
	key_c_r[0] <= #1 key_c;

always @(posedge MY_CLK)
	for(i=0;i<33;i=i+1)
		key_c_r[i+1] <= #1 key_c_r[i];

des u0(	.desOut(stage1_out),	.desIn(desIn),		.key(key_a), .decrypt(decrypt), .clk(MY_CLK) );

des u1(	.desOut(stage2_out),	.desIn(stage1_out),	.key(key_b_r[16]), .decrypt(!decrypt), .clk(MY_CLK) );

des u2(	.desOut(desOut),	.desIn(stage2_out),	.key(key_c_r[33]), .decrypt(decrypt),	.clk(MY_CLK) );

endmodule
module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
	parameter CFG_ABITS = 10;
	parameter CFG_DBITS = 18;
	parameter CFG_ENABLE_A = 2;

	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;
	parameter [18431:0] INIT = 18432'bx;
	parameter TRANSP2 = 0;

	input CLK2;
	input CLK3;

	input [CFG_ABITS-1:0] A1ADDR;
	input [CFG_DBITS-1:0] A1DATA;
	input [CFG_ENABLE_A-1:0] A1EN;

	input [CFG_ABITS-1:0] B1ADDR;
	output [CFG_DBITS-1:0] B1DATA;
	input B1EN;

	localparam CLKAMUX = CLKPOL2 ? "CLKA" : "INV";
	localparam CLKBMUX = CLKPOL3 ? "CLKB" : "INV";

	localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "READBEFOREWRITE";

	generate if (CFG_DBITS == 1) begin
		DP16KD #(
			`include "bram_init_1_2_4.vh"
			.DATA_WIDTH_A(1),
			.DATA_WIDTH_B(1),
			.CLKAMUX(CLKAMUX),
			.CLKBMUX(CLKBMUX),
			.WRITEMODE_A(WRITEMODE_A),
			.WRITEMODE_B("READBEFOREWRITE"),
			.GSR("DISABLED")
		) _TECHMAP_REPLACE_ (
			`include "bram_conn_1.vh"
			.CLKA(CLK2), .CLKB(CLK3),
			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
			.RSTA(1'b0), .RSTB(1'b0)
		);
	end else if (CFG_DBITS == 2) begin
		DP16KD #(
			`include "bram_init_1_2_4.vh"
			.DATA_WIDTH_A(2),
			.DATA_WIDTH_B(2),
			.CLKAMUX(CLKAMUX),
			.CLKBMUX(CLKBMUX),
			.WRITEMODE_A(WRITEMODE_A),
			.WRITEMODE_B("READBEFOREWRITE"),
			.GSR("DISABLED")
		) _TECHMAP_REPLACE_ (
			`include "bram_conn_2.vh"
			.CLKA(CLK2), .CLKB(CLK3),
			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
			.RSTA(1'b0), .RSTB(1'b0)
		);
	end else if (CFG_DBITS <= 4) begin
		DP16KD #(
			`include "bram_init_1_2_4.vh"
			.DATA_WIDTH_A(4),
			.DATA_WIDTH_B(4),
			.CLKAMUX(CLKAMUX),
			.CLKBMUX(CLKBMUX),
			.WRITEMODE_A(WRITEMODE_A),
			.WRITEMODE_B("READBEFOREWRITE"),
			.GSR("DISABLED")
		) _TECHMAP_REPLACE_ (
			`include "bram_conn_4.vh"
			.CLKA(CLK2), .CLKB(CLK3),
			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
			.RSTA(1'b0), .RSTB(1'b0)
		);
	end else if (CFG_DBITS <= 9) begin
		DP16KD #(
			`include "bram_init_9_18_36.vh"
			.DATA_WIDTH_A(9),
			.DATA_WIDTH_B(9),
			.CLKAMUX(CLKAMUX),
			.CLKBMUX(CLKBMUX),
			.WRITEMODE_A(WRITEMODE_A),
			.WRITEMODE_B("READBEFOREWRITE"),
			.GSR("DISABLED")
		) _TECHMAP_REPLACE_ (
			`include "bram_conn_9.vh"
			.CLKA(CLK2), .CLKB(CLK3),
			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
			.RSTA(1'b0), .RSTB(1'b0)
		);
	end else if (CFG_DBITS <= 18) begin
		DP16KD #(
			`include "bram_init_9_18_36.vh"
			.DATA_WIDTH_A(18),
			.DATA_WIDTH_B(18),
			.CLKAMUX(CLKAMUX),
			.CLKBMUX(CLKBMUX),
			.WRITEMODE_A(WRITEMODE_A),
			.WRITEMODE_B("READBEFOREWRITE"),
			.GSR("DISABLED")
		) _TECHMAP_REPLACE_ (
			`include "bram_conn_18.vh"
			.CLKA(CLK2), .CLKB(CLK3),
			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
			.RSTA(1'b0), .RSTB(1'b0)
		);
	end else begin
		wire TECHMAP_FAIL = 1'b1;
	end endgenerate
endmodule
module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
	parameter A_SIGNED = 0;
	parameter B_SIGNED = 0;
	parameter A_WIDTH = 1;
	parameter B_WIDTH = 1;
	parameter Y_WIDTH = 1;

	input [A_WIDTH-1:0] A;
	input [B_WIDTH-1:0] B;
	output [Y_WIDTH-1:0] X, Y;

	input CI, BI;
	output [Y_WIDTH-1:0] CO;

	wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;

	wire [Y_WIDTH-1:0] A_buf, B_buf;
	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));

	function integer round_up2;
		input integer N;
		begin
			round_up2 = ((N + 1) / 2) * 2;
		end
	endfunction

	localparam Y_WIDTH2 = round_up2(Y_WIDTH);

	wire [Y_WIDTH2-1:0] AA = A_buf;
	wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
	wire [Y_WIDTH2-1:0] C = {CO, CI};
	wire [Y_WIDTH2-1:0] FCO, Y1;

	genvar i;
	generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
		CCU2C #(
			.INIT0(16'b0110011010101010),
			.INIT1(16'b0110011010101010),
			.INJECT1_0("NO"),
			.INJECT1_1("NO")
	   ) ccu2c_i (
			.CIN(C[i]),
			.A0(AA[i]), .B0(BB[i]), .C0(1'b0), .D0(1'b1),
			.A1(AA[i+1]), .B1(BB[i+1]), .C1(1'b0), .D1(1'b1),
			.S0(Y[i]), .S1(Y1[i]),
			.COUT(FCO[i])
		);

		assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
		if (i+1 < Y_WIDTH) begin
			assign CO[i+1] = FCO[i];
			assign Y[i+1] = Y1[i];
		end
	end endgenerate

	assign X = AA ^ BB;
endmodule
module MULT18X18D(
	input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17,
	input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17,
	input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17,
	input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB,
	input CLK0, CLK1, CLK2, CLK3,
	input CE0, CE1, CE2, CE3,
	input RST0, RST1, RST2, RST3,
	input SRIA0, SRIA1, SRIA2, SRIA3, SRIA4, SRIA5, SRIA6, SRIA7, SRIA8, SRIA9, SRIA10, SRIA11, SRIA12, SRIA13, SRIA14, SRIA15, SRIA16, SRIA17,
	input SRIB0, SRIB1, SRIB2, SRIB3, SRIB4, SRIB5, SRIB6, SRIB7, SRIB8, SRIB9, SRIB10, SRIB11, SRIB12, SRIB13, SRIB14, SRIB15, SRIB16, SRIB17,
	output SROA0, SROA1, SROA2, SROA3, SROA4, SROA5, SROA6, SROA7, SROA8, SROA9, SROA10, SROA11, SROA12, SROA13, SROA14, SROA15, SROA16, SROA17,
	output SROB0, SROB1, SROB2, SROB3, SROB4, SROB5, SROB6, SROB7, SROB8, SROB9, SROB10, SROB11, SROB12, SROB13, SROB14, SROB15, SROB16, SROB17,
	output ROA0, ROA1, ROA2, ROA3, ROA4, ROA5, ROA6, ROA7, ROA8, ROA9, ROA10, ROA11, ROA12, ROA13, ROA14, ROA15, ROA16, ROA17,
	output ROB0, ROB1, ROB2, ROB3, ROB4, ROB5, ROB6, ROB7, ROB8, ROB9, ROB10, ROB11, ROB12, ROB13, ROB14, ROB15, ROB16, ROB17,
	output ROC0, ROC1, ROC2, ROC3, ROC4, ROC5, ROC6, ROC7, ROC8, ROC9, ROC10, ROC11, ROC12, ROC13, ROC14, ROC15, ROC16, ROC17,
	output P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35,
	output SIGNEDP
);
	parameter REG_INPUTA_CLK = "NONE";
	parameter REG_INPUTA_CE = "CE0";
	parameter REG_INPUTA_RST = "RST0";
	parameter REG_INPUTB_CLK = "NONE";
	parameter REG_INPUTB_CE = "CE0";
	parameter REG_INPUTB_RST = "RST0";
	parameter REG_INPUTC_CLK = "NONE";
	parameter REG_PIPELINE_CLK = "NONE";
	parameter REG_PIPELINE_CE = "CE0";
	parameter REG_PIPELINE_RST = "RST0";
	parameter REG_OUTPUT_CLK = "NONE";
	parameter [127:0] CLK0_DIV = "ENABLED";
	parameter [127:0] CLK1_DIV = "ENABLED";
	parameter [127:0] CLK2_DIV = "ENABLED";
	parameter [127:0] CLK3_DIV = "ENABLED";
	parameter [127:0] GSR = "ENABLED";
	parameter [127:0] SOURCEB_MODE = "B_SHIFT";
	parameter [127:0] RESETMODE = "SYNC";
endmodule
module IDDRX2F(
	input D, SCLK, ECLK, RST,
	output Q0, Q1, Q2, Q3
);
	parameter GSR = "ENABLED";
endmodule
module LUT4(input A, B, C, D, output Z);
    parameter [15:0] INIT = 16'h0000;
    wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];
    wire [3:0] s2 = C ?       s3[ 7:4] :       s3[3:0];
    wire [1:0] s1 = B ?       s2[ 3:2] :       s2[1:0];
    assign Z =      A ?          s1[1] :         s1[0];
endmodule
module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
	           output S0, S1, COUT);

	parameter [15:0] INIT0 = 16'h0000;
	parameter [15:0] INIT1 = 16'h0000;
	parameter INJECT1_0 = "YES";
	parameter INJECT1_1 = "YES";

	// First half
	wire LUT4_0, LUT2_0;
	LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
	LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));

	wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
	assign S0 = LUT4_0 ^ gated_cin_0;

	wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
	wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);

	// Second half
	wire LUT4_1, LUT2_1;
	LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
	LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));

	wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
	assign S1 = LUT4_1 ^ gated_cin_1;

	wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
	assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);

endmodule
module TRELLIS_DPR16X4 (
	input [3:0] DI,
	input [3:0] WAD,
	input WRE, WCK,
	input [3:0] RAD,
	output [3:0] DO
);
	parameter WCKMUX = "WCK";
	parameter WREMUX = "WRE";
	parameter [63:0] INITVAL = 64'h0000000000000000;

	reg [3:0] mem[15:0];

	integer i;
	initial begin
		for (i = 0; i < 16; i = i + 1)
			mem[i] <= {INITVAL[i+3], INITVAL[i+2], INITVAL[i+1], INITVAL[i]};
	end

	wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;

	reg muxwre;
	always @(*)
		case (WREMUX)
			"1": muxwre = 1'b1;
			"0": muxwre = 1'b0;
			"INV": muxwre = ~WRE;
			default: muxwre = WRE;
		endcase

	always @(posedge muxwck)
		if (muxwre)
			mem[WAD] <= DI;

	assign DO = mem[RAD];
endmodule
module DPR16X4C (
		input [3:0] DI,
		input WCK, WRE,
		input [3:0] RAD,
		input [3:0] WAD,
		output [3:0] DO
);
	// For legacy Lattice compatibility, INITIVAL is a hex
	// string rather than a numeric parameter
	parameter INITVAL = "0x0000000000000000";

	function [63:0] convert_initval;
		input [143:0] hex_initval;
		reg done;
		reg [63:0] temp;
		reg [7:0] char;
		integer i;
		begin
			done = 1'b0;
			temp = 0;
			for (i = 0; i < 16; i = i + 1) begin
				if (!done) begin
					char = hex_initval[8*i +: 8];
					if (char == "x") begin
						done = 1'b1;
					end else begin
						if (char >= "0" && char <= "9")
							temp[4*i +: 4] = char - "0";
						else if (char >= "A" && char <= "F")
							temp[4*i +: 4] = 10 + char - "A";
						else if (char >= "a" && char <= "f")
							temp[4*i +: 4] = 10 + char - "a";
					end
				end
			end
			convert_initval = temp;
		end
	endfunction

	localparam conv_initval = convert_initval(INITVAL);

	reg [3:0] ram[0:15];
	integer i;
	initial begin
		for (i = 0; i < 15; i = i + 1) begin
			ram[i] <= conv_initval[4*i +: 4];
		end
	end

	always @(posedge WCK)
		if (WRE)
			ram[WAD] <= DI;

	assign DO = ram[RAD];

endmodule
module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
	parameter GSR = "ENABLED";
	parameter [127:0] CEMUX = "1";
	parameter CLKMUX = "CLK";
	parameter LSRMUX = "LSR";
	parameter SRMODE = "LSR_OVER_CE";
	parameter REGSET = "RESET";
	parameter [127:0] LSRMODE = "LSR";

	reg muxce;
	always @(*)
		case (CEMUX)
			"1": muxce = 1'b1;
			"0": muxce = 1'b0;
			"INV": muxce = ~CE;
			default: muxce = CE;
		endcase

	wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
	wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
	wire srval;
	generate
		if (LSRMODE == "PRLD")
			assign srval = M;
		else
			assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
	endgenerate

	initial Q = srval;

	generate
		if (SRMODE == "ASYNC") begin
			always @(posedge muxclk, posedge muxlsr)
				if (muxlsr)
					Q <= srval;
				else if (muxce)
					Q <= DI;
		end else begin
			always @(posedge muxclk)
				if (muxlsr)
					Q <= srval;
				else if (muxce)
					Q <= DI;
		end
	endgenerate
endmodule
module OBZ(input I, T, output O);
assign O = T ? 1'bz : I;
endmodule
module BB(input I, T, output O, inout B);
assign B = T ? 1'bz : I;
assign O = B;
endmodule
module FD1S3BX(input PD, D, CK, output Q);
	TRELLIS_FF #(
		.GSR("DISABLED"),
		.CEMUX("1"),
		.CLKMUX("CLK"),
		.LSRMUX("LSR"),
		.REGSET("SET"),
		.SRMODE("ASYNC")
	) tff_i (
		.CLK(CK),
		.LSR(PD),
		.DI(D),
		.Q(Q)
	);
endmodule
module  \$_DFF_N_ (input D, C, output Q);
  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(!C), .EN(1'b1), .ALn(1'b1), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
endmodule
module  \$_DFF_P_ (input D, C, output Q);
  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(1'b1), .ALn(1'b1), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
endmodule
module \$_DFF_NN0_ (input D, C, R, output Q);
  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(!C), .EN(1'b1), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
endmodule
module \$_DFF_NN1_ (input D, C, R, output Q);
  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(!C), .EN(1'b1), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
endmodule
module \$_DFF_NP0_ (input D, C, R, output Q);
  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(!C), .EN(1'b1), .ALn(!R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
endmodule
module \$_DFF_NP1_ (input D, C, R, output Q);
  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(!C), .EN(1'b1), .ALn(!R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
endmodule
module \$_DFF_PN0_ (input D, C, R, output Q);
  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(1'b1), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
endmodule
module \$_DFF_PN1_ (input D, C, R, output Q);
  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(1'b1), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
endmodule
module \$_DFF_PP0_ (input D, C, R, output Q);
  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(1'b1), .ALn(!R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
endmodule
module \$_DFF_PP1_ (input D, C, R, output Q);
  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(1'b1), .ALn(!R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
endmodule
module \$lut (A, Y);
  parameter WIDTH = 0;
  parameter LUT = 0;

  input [WIDTH-1:0] A;
  output Y;

  generate
    if (WIDTH == 1) begin
      CFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]));
    end else
    if (WIDTH == 2) begin
      CFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]));
    end else
    if (WIDTH == 3) begin
      CFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]));
    end else
    if (WIDTH == 4) begin
      CFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
    end else begin
      wire _TECHMAP_FAIL_ = 1;
    end
  endgenerate
endmodule
module ADD2 (

	input A, B,
	output Y
);
	assign Y = A & B;
endmodule
module ADD3 (
	input A, B, C,
	output Y
);
	assign Y = A & B & C;
endmodule
module ADD4 (
	input A, B, C, D,
	output Y
);
	assign Y = A & B & C & D;
endmodule
module CLKINT (
	input A,
	output Y
);
	assign Y = A;
endmodule
module CLKINT_PRESERVE (
	input A,
	output Y
);
	assign Y = A;
endmodule
module GCLKINT (
	input A, EN,
	output Y
);
	assign Y = A & EN;
endmodule
module RCLKINT (
	input A,
	output Y
);
	assign Y = A;
endmodule
module RGCLKINT (
	input A, EN,
	output Y
);
	assign Y = A & EN;
endmodule
module SLE (
	output Q,
	input ADn,
	input ALn,
	input CLK,
	input D,
	input LAT,
	input SD,
	input EN,
	input SLn
);
	reg q_latch, q_ff;

	always @(posedge CLK, negedge ALn) begin
		if (!ALn) begin
			q_ff <= !ADn;
		end else if (EN) begin
			if (!SLn)
				q_ff <= SD;
			else
				q_ff <= D;
		end
	end

	always @* begin
		if (!ALn) begin
			q_latch <= !ADn;
		end else if (CLK && EN) begin
			if (!SLn)
				q_ff <= SD;
			else
				q_ff <= D;
		end
	end

	assign Q = LAT ? q_latch : q_ff;
endmodule
module CLKBUF (
	input PAD,
	output Y
);
	assign Y = PAD;
endmodule
module INBUF (
	input PAD,
	output Y
);
	assign Y = PAD;
endmodule
module OUTBUF (
	input D,
	output PAD
);
	assign PAD = D;
endmodule
module \$__GW1NR_RAM16S4 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
	parameter CFG_ABITS = 4;
	parameter CFG_DBITS = 4;

        parameter [63:0] INIT = 64'bx;
	input CLK1;

	input  [CFG_ABITS-1:0] A1ADDR;
	output [CFG_DBITS-1:0] A1DATA;   
        input                  A1EN;

	input  [CFG_ABITS-1:0] B1ADDR;
	input  [CFG_DBITS-1:0] B1DATA;
	input  B1EN;

        `include "brams_init3.vh"

  RAM16S4
   #(.INIT_0(INIT_0),
     .INIT_1(INIT_1),
     .INIT_2(INIT_2),
     .INIT_3(INIT_3))
   _TECHMAP_REPLACE_
     (.AD(B1ADDR),
      .DI(B1DATA),
      .DO(A1DATA),
      .CLK(CLK1),
      .WRE(B1EN));

	
endmodule
module \$lut (A, Y);
  parameter WIDTH = 0;
  parameter LUT = 0;

  input [WIDTH-1:0] A;
  output Y;

  generate
    if (WIDTH == 1) begin
      LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
        .I0(A[0]));
    end else
    if (WIDTH == 2) begin
      LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
        .I0(A[0]), .I1(A[1]));
    end else
    if (WIDTH == 3) begin
      LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
        .I0(A[0]), .I1(A[1]), .I2(A[2]));
    end else
    if (WIDTH == 4) begin
      LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
        .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
    end else begin
      wire _TECHMAP_FAIL_ = 1;
    end
  endgenerate
endmodule
module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
	parameter CFG_ABITS = 10;
	parameter CFG_DBITS = 16;
	parameter CFG_ENABLE_A = 3;

        parameter [16383:0] INIT = 16384'hx;
        parameter CLKPOL2 = 1;
        parameter CLKPOL3 = 1;

	input CLK2;
	input CLK3;

	input [CFG_ABITS-1:0] A1ADDR;
	input [CFG_DBITS-1:0] A1DATA;   
        input [CFG_ENABLE_A-1:0] A1EN;

	input [CFG_ABITS-1:0] B1ADDR;
	output [CFG_DBITS-1:0] B1DATA;
	input B1EN;

	
	generate if (CFG_DBITS == 1) begin
		SDP   #(
			.READ_MODE(0),
			.BIT_WIDTH_0(1),
			.BIT_WIDTH_1(1),
			.BLK_SEL(3'b000),
			.RESET_MODE("SYNC")
		) _TECHMAP_REPLACE_ (
			.CLKA(CLK2),   .CLKB(CLK3),
			.WREA(A1EN),   .OCE(1'b0), .CEA(1'b1),
			.WREB(1'b0),   .CEB(B1EN),
			.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
			.DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
		);
	end else if (CFG_DBITS == 2) begin
		SDP    #(
			.READ_MODE(0),
			.BIT_WIDTH_0(2),
			.BIT_WIDTH_1(2),
			.BLK_SEL(3'b000),
			.RESET_MODE("SYNC")
		) _TECHMAP_REPLACE_ (
			.CLKA(CLK2),   .CLKB(CLK3),
			.WREA(A1EN),   .OCE(1'b0), .CEA(1'b1),
			.WREB(1'b0),   .CEB(B1EN),
			.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
                        .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
		);
	end else if (CFG_DBITS <= 4) begin
		SDP    #(
			.READ_MODE(0),
			.BIT_WIDTH_0(4),
			.BIT_WIDTH_1(4),
			.BLK_SEL(3'b000),
			.RESET_MODE("SYNC")
		) _TECHMAP_REPLACE_ (
			.CLKA(CLK2),   .CLKB(CLK3),
			.WREA(A1EN),   .OCE(1'b0),
			.WREB(1'b0),   .CEB(B1EN), .CEA(1'b1),
			.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
                        .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
		);
	end else if (CFG_DBITS <= 8) begin
		SDP    #(
			.READ_MODE(0),
			.BIT_WIDTH_0(8),
			.BIT_WIDTH_1(8),
			.BLK_SEL(3'b000),
			.RESET_MODE("SYNC")
		) _TECHMAP_REPLACE_ (
			.CLKA(CLK2),   .CLKB(CLK3),
			.WREA(A1EN),   .OCE(1'b0), .CEA(1'b1),
			.WREB(1'b0),   .CEB(B1EN),
			.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
                        .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
		);
	end else if (CFG_DBITS <= 16) begin
		SDP    #(
			.READ_MODE(0),
			.BIT_WIDTH_0(16),
			.BIT_WIDTH_1(16),
			.BLK_SEL(3'b000),
			.RESET_MODE("SYNC")
		) _TECHMAP_REPLACE_ (
			.CLKA(CLK2),   .CLKB(CLK3),
			.WREA(A1EN),   .OCE(1'b0),
			.WREB(1'b0),   .CEB(B1EN), .CEA(1'b1),
			.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
                        .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
		);
	end else begin
		wire TECHMAP_FAIL = 1'b1;
	end endgenerate
	
endmodule
module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
   parameter A_SIGNED = 0;
   parameter B_SIGNED = 0;
   parameter A_WIDTH = 1;
   parameter B_WIDTH = 1;
   parameter Y_WIDTH = 1;

   input [A_WIDTH-1:0] A;
   input [B_WIDTH-1:0] B;
   output [Y_WIDTH-1:0] X, Y;

   input 		CI, BI;
   output [Y_WIDTH-1:0] CO;

   wire 		_TECHMAP_FAIL_ = Y_WIDTH <= 2;

   wire [Y_WIDTH-1:0] 	A_buf, B_buf;
   \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
   \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));

   wire [Y_WIDTH-1:0] 	AA = A_buf;
   wire [Y_WIDTH-1:0] 	BB = BI ? ~B_buf : B_buf;
   wire [Y_WIDTH-1:0] 	C = {CO, CI};

   genvar 		i;
   generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
      ALU #(.ALU_MODE(32'b0))
      alu(.I0(AA[i]),
	  .I1(BB[i]),
	  .I3(1'b0),
	  .CIN(C[i]),
	  .COUT(CO[i]),
	  .SUM(Y[i])
	  );
   end endgenerate
   assign X = AA ^ BB;
endmodule
module LUT1(output F, input I0);
	parameter [1:0] INIT = 0;
	assign F = I0 ? INIT[1] : INIT[0];
endmodule
module LUT2(output F, input I0, I1);
	parameter [3:0] INIT = 0;
	wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
	assign F = I0 ? s1[1] : s1[0];
endmodule
module LUT3(output F, input I0, I1, I2);
	parameter [7:0] INIT = 0;
	wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
	wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
	assign F = I0 ? s1[1] : s1[0];
endmodule
module LUT4(output F, input I0, I1, I2, I3);
	parameter [15:0] INIT = 0;
	wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
	wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
	wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
	assign F = I0 ? s1[1] : s1[0];
endmodule
module DFF (output reg Q, input CLK, D);
	parameter [0:0] INIT = 1'b0;
	initial Q = INIT;
	always @(posedge CLK)
		Q <= D;
endmodule
module DFFN (output reg Q, input CLK, D);
	parameter [0:0] INIT = 1'b0;
	initial Q = INIT;
	always @(negedge CLK)
		Q <= D;
endmodule
module DFFR (output reg Q, input D, CLK, RESET);
	parameter [0:0] INIT = 1'b0;
	initial Q = INIT;
	always @(posedge CLK) begin
        if (RESET)
                Q <= 1'b0;
        else
                Q <= D;
	end
endmodule // DFFR (positive clock edge; synchronous reset)
module IBUF(output O, input I);
	assign O = I;
endmodule
module OBUF(output O, input I);
	assign O = I;
endmodule
module GSR (input GSRI);
	wire GSRO = GSRI;
endmodule
module ALU (input I0, input I1, input I3, input CIN, output COUT, output SUM);
   parameter [3:0] ALU_MODE = 0; // default 0 = ADD
   assign  {COUT, SUM} = CIN + I1 + I0;
endmodule // alu
module RAM16S4 (DO, DI, AD, WRE, CLK);
   parameter WIDTH  = 4;
   parameter INIT_0 = 16'h0000;
   parameter INIT_1 = 16'h0000;
   parameter INIT_2 = 16'h0000;
   parameter INIT_3 = 16'h0000;
   
   input  [WIDTH-1:0] AD;
   input  [WIDTH-1:0] DI;
   output [WIDTH-1:0] DO;
   input 	      CLK;
   input 	      WRE;

   reg [15:0] 	    mem0, mem1, mem2, mem3;
   
   initial begin
      mem0 = INIT_0;
      mem1 = INIT_1;
      mem2 = INIT_2;
      mem3 = INIT_3;	
   end
   
   assign	DO[0] = mem0[AD];
   assign	DO[1] = mem1[AD];
   assign	DO[2] = mem2[AD];
   assign	DO[3] = mem3[AD];
   
   always @(posedge CLK) begin
      if (WRE) begin
	 mem0[AD] <= DI[0];
	 mem1[AD] <= DI[1];
	 mem2[AD] <= DI[2];
	 mem3[AD] <= DI[3];
      end
   end
   
endmodule // RAM16S4
module \$lut (A, Y);
  parameter WIDTH = 0;
  parameter LUT = 0;

  input [WIDTH-1:0] A;
  output Y;

  generate
    if (WIDTH == 1) begin
      SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
        .I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0));
    end else
    if (WIDTH == 2) begin
      SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
        .I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0));
    end else
    if (WIDTH == 3) begin
      SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
        .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0));
    end else
    if (WIDTH == 4) begin
      SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
        .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
    end else begin
      wire _TECHMAP_FAIL_ = 1;
    end
  endgenerate
endmodule
module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
	parameter A_SIGNED = 0;
	parameter B_SIGNED = 0;
	parameter A_WIDTH = 1;
	parameter B_WIDTH = 1;
	parameter Y_WIDTH = 1;

	input [A_WIDTH-1:0] A;
	input [B_WIDTH-1:0] B;
	output [Y_WIDTH-1:0] X, Y;

	input CI, BI;
	output [Y_WIDTH-1:0] CO;

	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;

	wire [Y_WIDTH-1:0] A_buf, B_buf;
	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));

	wire [Y_WIDTH-1:0] AA = A_buf;
	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
	wire [Y_WIDTH-1:0] C = {CO, CI};

	genvar i;
	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
		SB_CARRY carry (
			.I0(AA[i]),
			.I1(BB[i]),
			.CI(C[i]),
			.CO(CO[i])
		);
		SB_LUT4 #(
			//         I0: 1010 1010 1010 1010
			//         I1: 1100 1100 1100 1100
			//         I2: 1111 0000 1111 0000
			//         I3: 1111 1111 0000 0000
			.LUT_INIT(16'b 0110_1001_1001_0110)
		) adder (
			.I0(1'b0),
			.I1(AA[i]),
			.I2(BB[i]),
			.I3(C[i]),
			.O(Y[i])
		);
	end endgenerate

	assign X = AA ^ BB;
endmodule
module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;
	parameter [36863:0] INIT = 36864'bx;

	input CLK2;
	input CLK3;

	input [8:0] A1ADDR;
	output [71:0] A1DATA;
	input A1EN;

	input [8:0] B1ADDR;
	input [71:0] B1DATA;
	input [7:0] B1EN;

	wire [15:0] A1ADDR_16 = {A1ADDR, 6'b0};
	wire [15:0] B1ADDR_16 = {B1ADDR, 6'b0};

	wire [7:0] DIP, DOP;
	wire [63:0] DI, DO;

	assign A1DATA = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32],
	                  DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };

	assign { DIP[7], DI[63:56], DIP[6], DI[55:48], DIP[5], DI[47:40], DIP[4], DI[39:32],
	         DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;

	RAMB36E1 #(
		.RAM_MODE("SDP"),
		.READ_WIDTH_A(72),
		.WRITE_WIDTH_B(72),
		.WRITE_MODE_A("READ_FIRST"),
		.WRITE_MODE_B("READ_FIRST"),
		.IS_CLKARDCLK_INVERTED(!CLKPOL2),
		.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
		`include "brams_init_36.vh"
		.SIM_DEVICE("7SERIES")
	) _TECHMAP_REPLACE_ (
		.DOBDO(DO[63:32]),
		.DOADO(DO[31:0]),
		.DOPBDOP(DOP[7:4]),
		.DOPADOP(DOP[3:0]),
		.DIBDI(DI[63:32]),
		.DIADI(DI[31:0]),
		.DIPBDIP(DIP[7:4]),
		.DIPADIP(DIP[3:0]),

		.ADDRARDADDR(A1ADDR_16),
		.CLKARDCLK(CLK2),
		.ENARDEN(A1EN),
		.REGCEAREGCE(|1),
		.RSTRAMARSTRAM(|0),
		.RSTREGARSTREG(|0),
		.WEA(4'b0),

		.ADDRBWRADDR(B1ADDR_16),
		.CLKBWRCLK(CLK3),
		.ENBWREN(|1),
		.REGCEB(|0),
		.RSTRAMB(|0),
		.RSTREGB(|0),
		.WEBWE(B1EN)
	);
endmodule
module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
	parameter CFG_ABITS = 10;
	parameter CFG_DBITS = 36;
	parameter CFG_ENABLE_B = 4;

	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;
	parameter [36863:0] INIT = 36864'bx;

	input CLK2;
	input CLK3;

	input [CFG_ABITS-1:0] A1ADDR;
	output [CFG_DBITS-1:0] A1DATA;
	input A1EN;

	input [CFG_ABITS-1:0] B1ADDR;
	input [CFG_DBITS-1:0] B1DATA;
	input [CFG_ENABLE_B-1:0] B1EN;

	wire [15:0] A1ADDR_16 = A1ADDR << (15 - CFG_ABITS);
	wire [15:0] B1ADDR_16 = B1ADDR << (15 - CFG_ABITS);
	wire [7:0] B1EN_8 = B1EN;

	wire [3:0] DIP, DOP;
	wire [31:0] DI, DO;

	wire [31:0] DOBDO;
	wire [3:0] DOPBDOP;

	assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
	assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;

	generate if (CFG_DBITS > 8) begin
		RAMB36E1 #(
			.RAM_MODE("TDP"),
			.READ_WIDTH_A(CFG_DBITS),
			.READ_WIDTH_B(CFG_DBITS),
			.WRITE_WIDTH_A(CFG_DBITS),
			.WRITE_WIDTH_B(CFG_DBITS),
			.WRITE_MODE_A("READ_FIRST"),
			.WRITE_MODE_B("READ_FIRST"),
			.IS_CLKARDCLK_INVERTED(!CLKPOL2),
			.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
			`include "brams_init_36.vh"
			.SIM_DEVICE("7SERIES")
		) _TECHMAP_REPLACE_ (
			.DIADI(32'd0),
			.DIPADIP(4'd0),
			.DOADO(DO[31:0]),
			.DOPADOP(DOP[3:0]),
			.ADDRARDADDR(A1ADDR_16),
			.CLKARDCLK(CLK2),
			.ENARDEN(A1EN),
			.REGCEAREGCE(|1),
			.RSTRAMARSTRAM(|0),
			.RSTREGARSTREG(|0),
			.WEA(4'b0),

			.DIBDI(DI),
			.DIPBDIP(DIP),
			.DOBDO(DOBDO),
			.DOPBDOP(DOPBDOP),
			.ADDRBWRADDR(B1ADDR_16),
			.CLKBWRCLK(CLK3),
			.ENBWREN(|1),
			.REGCEB(|0),
			.RSTRAMB(|0),
			.RSTREGB(|0),
			.WEBWE(B1EN_8)
		);
	end else begin
		RAMB36E1 #(
			.RAM_MODE("TDP"),
			.READ_WIDTH_A(CFG_DBITS),
			.READ_WIDTH_B(CFG_DBITS),
			.WRITE_WIDTH_A(CFG_DBITS),
			.WRITE_WIDTH_B(CFG_DBITS),
			.WRITE_MODE_A("READ_FIRST"),
			.WRITE_MODE_B("READ_FIRST"),
			.IS_CLKARDCLK_INVERTED(!CLKPOL2),
			.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
			`include "brams_init_32.vh"
			.SIM_DEVICE("7SERIES")
		) _TECHMAP_REPLACE_ (
			.DIADI(32'd0),
			.DIPADIP(4'd0),
			.DOADO(DO[31:0]),
			.DOPADOP(DOP[3:0]),
			.ADDRARDADDR(A1ADDR_16),
			.CLKARDCLK(CLK2),
			.ENARDEN(A1EN),
			.REGCEAREGCE(|1),
			.RSTRAMARSTRAM(|0),
			.RSTREGARSTREG(|0),
			.WEA(4'b0),

			.DIBDI(DI),
			.DIPBDIP(DIP),
			.DOBDO(DOBDO),
			.DOPBDOP(DOPBDOP),
			.ADDRBWRADDR(B1ADDR_16),
			.CLKBWRCLK(CLK3),
			.ENBWREN(|1),
			.REGCEB(|0),
			.RSTRAMB(|0),
			.RSTREGB(|0),
			.WEBWE(B1EN_8)
		);
	end endgenerate
endmodule
module \$lut (A, Y);
  parameter WIDTH = 0;
  parameter LUT = 0;

  input [WIDTH-1:0] A;
  output Y;

  generate
    if (WIDTH == 1) begin
      LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
        .I0(A[0]));
    end else
    if (WIDTH == 2) begin
      LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
        .I0(A[0]), .I1(A[1]));
    end else
    if (WIDTH == 3) begin
      LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
        .I0(A[0]), .I1(A[1]), .I2(A[2]));
    end else
    if (WIDTH == 4) begin
      LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
        .I0(A[0]), .I1(A[1]), .I2(A[2]),
        .I3(A[3]));
    end else
    if (WIDTH == 5) begin
      LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
        .I0(A[0]), .I1(A[1]), .I2(A[2]),
        .I3(A[3]), .I4(A[4]));
    end else
    if (WIDTH == 6) begin
      LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
        .I0(A[0]), .I1(A[1]), .I2(A[2]),
        .I3(A[3]), .I4(A[4]), .I5(A[5]));
    end else
    if (WIDTH == 7) begin
      wire T0, T1;
      LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
        .I0(A[0]), .I1(A[1]), .I2(A[2]),
        .I3(A[3]), .I4(A[4]), .I5(A[5]));
      LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
        .I0(A[0]), .I1(A[1]), .I2(A[2]),
        .I3(A[3]), .I4(A[4]), .I5(A[5]));
      MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[6]));
    end else
    if (WIDTH == 8) begin
      wire T0, T1, T2, T3, T4, T5;
      LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
        .I0(A[0]), .I1(A[1]), .I2(A[2]),
        .I3(A[3]), .I4(A[4]), .I5(A[5]));
      LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
        .I0(A[0]), .I1(A[1]), .I2(A[2]),
        .I3(A[3]), .I4(A[4]), .I5(A[5]));
      LUT6 #(.INIT(LUT[191:128])) fpga_lut_2 (.O(T2),
        .I0(A[0]), .I1(A[1]), .I2(A[2]),
        .I3(A[3]), .I4(A[4]), .I5(A[5]));
      LUT6 #(.INIT(LUT[255:192])) fpga_lut_3 (.O(T3),
        .I0(A[0]), .I1(A[1]), .I2(A[2]),
        .I3(A[3]), .I4(A[4]), .I5(A[5]));
      MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[6]));
      MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[6]));
      MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[7]));
    end else begin
      wire _TECHMAP_FAIL_ = 1;
    end
  endgenerate
endmodule
module _80_xilinx_lcu (P, G, CI, CO);
	parameter WIDTH = 2;

	input [WIDTH-1:0] P, G;
	input CI;

	output [WIDTH-1:0] CO;

	wire _TECHMAP_FAIL_ = WIDTH <= 2;

	genvar i;

`ifdef _CLB_CARRY

	localparam CARRY4_COUNT = (WIDTH + 3) / 4;
	localparam MAX_WIDTH    = CARRY4_COUNT * 4;
	localparam PAD_WIDTH    = MAX_WIDTH - WIDTH;

	wire [MAX_WIDTH-1:0] S  = {{PAD_WIDTH{1'b0}}, P & ~G};
	wire [MAX_WIDTH-1:0] C  = CO;

	generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice

		// Partially occupied CARRY4
		if ((i+1)*4 > WIDTH) begin

			// First one
			if (i == 0) begin
				CARRY4 carry4_1st_part
				(
				.CYINIT(CI),
				.CI    (1'd0),
				.DI    (G [(Y_WIDTH - 1):i*4]),
				.S     (S [(Y_WIDTH - 1):i*4]),
				.CO    (CO[(Y_WIDTH - 1):i*4]),
				);
			// Another one
			end else begin
				CARRY4 carry4_part
				(
				.CYINIT(1'd0),
				.CI    (C [i*4 - 1]),
				.DI    (G [(Y_WIDTH - 1):i*4]),
				.S     (S [(Y_WIDTH - 1):i*4]),
				.CO    (CO[(Y_WIDTH - 1):i*4]),
				);
			end

		// Fully occupied CARRY4
		end else begin

			// First one
			if (i == 0) begin
				CARRY4 carry4_1st_full
				(
				.CYINIT(CI),
				.CI    (1'd0),
				.DI    (G [((i+1)*4 - 1):i*4]),
				.S     (S [((i+1)*4 - 1):i*4]),
				.CO    (CO[((i+1)*4 - 1):i*4]),
				);
			// Another one
			end else begin
				CARRY4 carry4_full
				(
				.CYINIT(1'd0),
				.CI    (C [i*4 - 1]),
				.DI    (G [((i+1)*4 - 1):i*4]),
				.S     (S [((i+1)*4 - 1):i*4]),
				.CO    (CO[((i+1)*4 - 1):i*4]),
				);
			end

		end

	end endgenerate

`elsif _EXPLICIT_CARRY

	wire [WIDTH-1:0] C = {CO, CI};
	wire [WIDTH-1:0] S = P & ~G;

	generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
		MUXCY muxcy (
			.CI(C[i]),
			.DI(G[i]),
			.S(S[i]),
			.O(CO[i])
		);
	end endgenerate

`else

	wire [WIDTH-1:0] C = {CO, CI};
	wire [WIDTH-1:0] S = P & ~G;

	generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
		MUXCY muxcy (
			.CI(C[i]),
			.DI(G[i]),
			.S(S[i]),
			.O(CO[i])
		);
	end endgenerate
`endif

endmodule
module IBUF(output O, input I);
  parameter IOSTANDARD = "default";
  parameter IBUF_LOW_PWR = 0;
  assign O = I;
endmodule
module OBUF(output O, input I);
  parameter IOSTANDARD = "default";
  parameter DRIVE = 12;
  parameter SLEW = "SLOW";
  assign O = I;
endmodule
module BUFG(output O, input I);
  assign O = I;
endmodule
module BUFGCTRL(
    output O,
    input I0, input I1,
    input S0, input S1,
    input CE0, input CE1,
    input IGNORE0, input IGNORE1);

parameter [0:0] INIT_OUT = 1'b0;
parameter PRESELECT_I0 = "FALSE";
parameter PRESELECT_I1 = "FALSE";
parameter [0:0] IS_CE0_INVERTED = 1'b0;
parameter [0:0] IS_CE1_INVERTED = 1'b0;
parameter [0:0] IS_S0_INVERTED = 1'b0;
parameter [0:0] IS_S1_INVERTED = 1'b0;
parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;

wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
wire S0_true = (S0 ^ IS_S0_INVERTED);
wire S1_true = (S1 ^ IS_S1_INVERTED);

assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);

endmodule
module BUFHCE(output O, input I, input CE);

parameter [0:0] INIT_OUT = 1'b0;
parameter CE_TYPE = "SYNC";
parameter [0:0] IS_CE_INVERTED = 1'b0;

assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);

endmodule
module INV(output O, input I);
  assign O = !I;
endmodule
module LUT1(output O, input I0);
  parameter [1:0] INIT = 0;
  assign O = I0 ? INIT[1] : INIT[0];
endmodule
module LUT2(output O, input I0, I1);
  parameter [3:0] INIT = 0;
  wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
  assign O = I0 ? s1[1] : s1[0];
endmodule
module LUT3(output O, input I0, I1, I2);
  parameter [7:0] INIT = 0;
  wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
  wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  assign O = I0 ? s1[1] : s1[0];
endmodule
module LUT4(output O, input I0, I1, I2, I3);
  parameter [15:0] INIT = 0;
  wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
  wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
  wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  assign O = I0 ? s1[1] : s1[0];
endmodule
module LUT5(output O, input I0, I1, I2, I3, I4);
  parameter [31:0] INIT = 0;
  wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
  wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
  wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
  wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  assign O = I0 ? s1[1] : s1[0];
endmodule
module LUT6(output O, input I0, I1, I2, I3, I4, I5);
  parameter [63:0] INIT = 0;
  wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
  wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
  wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
  wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
  wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  assign O = I0 ? s1[1] : s1[0];
endmodule