dakies/OSS_Verilog huggingface dataset:
module mux_tree_tapbuf_size7
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    in,
    sram,
    sram_inv,
    out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input [0:6]in;
    input [0:2]sram;
    input [0:2]sram_inv;
    output out;

    wire const1_0_const1;
    wire [0:6]in;
    wire out;
    wire sky130_fd_sc_hd__mux2_1_0_X;
    wire sky130_fd_sc_hd__mux2_1_1_X;
    wire sky130_fd_sc_hd__mux2_1_2_X;
    wire sky130_fd_sc_hd__mux2_1_3_X;
    wire sky130_fd_sc_hd__mux2_1_4_X;
    wire sky130_fd_sc_hd__mux2_1_5_X;
    wire sky130_fd_sc_hd__mux2_1_6_X;
    wire [0:2]sram;
    wire [0:2]sram_inv;

    const1 const1_0_
    (
        .const1(const1_0_const1)
    );
    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[1]),
        .A1(in[0]),
        .S(sram[0]),
        .X(sky130_fd_sc_hd__mux2_1_0_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l1_in_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[3]),
        .A1(in[2]),
        .S(sram[0]),
        .X(sky130_fd_sc_hd__mux2_1_1_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l1_in_2_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[5]),
        .A1(in[4]),
        .S(sram[0]),
        .X(sky130_fd_sc_hd__mux2_1_2_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l1_in_3_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(const1_0_const1),
        .A1(in[6]),
        .S(sram[0]),
        .X(sky130_fd_sc_hd__mux2_1_3_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(sky130_fd_sc_hd__mux2_1_1_X),
        .A1(sky130_fd_sc_hd__mux2_1_0_X),
        .S(sram[1]),
        .X(sky130_fd_sc_hd__mux2_1_4_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l2_in_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(sky130_fd_sc_hd__mux2_1_3_X),
        .A1(sky130_fd_sc_hd__mux2_1_2_X),
        .S(sram[1]),
        .X(sky130_fd_sc_hd__mux2_1_5_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l3_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(sky130_fd_sc_hd__mux2_1_5_X),
        .A1(sky130_fd_sc_hd__mux2_1_4_X),
        .S(sram[2]),
        .X(sky130_fd_sc_hd__mux2_1_6_X)
    );
    sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A(sky130_fd_sc_hd__mux2_1_6_X),
        .X(out)
    );
endmodule
module mux_tree_tapbuf_size12_mem
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    ccff_head,
    prog_clk,
    prog_reset,
    ccff_tail,
    mem_out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input ccff_head;
    input prog_clk;
    input prog_reset;
    output ccff_tail;
    output [0:3]mem_out;

    wire ccff_head;
    wire ccff_tail;
    wire [0:3]mem_out;
    wire prog_clk;
    wire prog_reset;

assign ccff_tail = mem_out[3];
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(ccff_head),
        .RESET_B(prog_reset),
        .Q(mem_out[0])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[0]),
        .RESET_B(prog_reset),
        .Q(mem_out[1])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[1]),
        .RESET_B(prog_reset),
        .Q(mem_out[2])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[2]),
        .RESET_B(prog_reset),
        .Q(mem_out[3])
    );
endmodule
module mux_tree_tapbuf_size4_mem
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    ccff_head,
    prog_clk,
    prog_reset,
    ccff_tail,
    mem_out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input ccff_head;
    input prog_clk;
    input prog_reset;
    output ccff_tail;
    output [0:2]mem_out;

    wire ccff_head;
    wire ccff_tail;
    wire [0:2]mem_out;
    wire prog_clk;
    wire prog_reset;

assign ccff_tail = mem_out[2];
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(ccff_head),
        .RESET_B(prog_reset),
        .Q(mem_out[0])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[0]),
        .RESET_B(prog_reset),
        .Q(mem_out[1])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[1]),
        .RESET_B(prog_reset),
        .Q(mem_out[2])
    );
endmodule
module mux_tree_size2
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    in,
    sram,
    sram_inv,
    out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input [0:1]in;
    input [0:1]sram;
    input [0:1]sram_inv;
    output out;

    wire const1_0_const1;
    wire [0:1]in;
    wire out;
    wire sky130_fd_sc_hd__mux2_1_0_X;
    wire [0:1]sram;
    wire [0:1]sram_inv;

    const1 const1_0_
    (
        .const1(const1_0_const1)
    );
    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[1]),
        .A1(in[0]),
        .S(sram[0]),
        .X(sky130_fd_sc_hd__mux2_1_0_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(const1_0_const1),
        .A1(sky130_fd_sc_hd__mux2_1_0_X),
        .S(sram[1]),
        .X(out)
    );
endmodule
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    carry_follower_a,
    carry_follower_b,
    carry_follower_cin,
    carry_follower_cout
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input carry_follower_a;
    input carry_follower_b;
    input carry_follower_cin;
    output carry_follower_cout;

    wire carry_follower_a;
    wire carry_follower_b;
    wire carry_follower_cin;
    wire carry_follower_cout;

    sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_wrapper_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(carry_follower_a),
        .A1(carry_follower_b),
        .S(carry_follower_cin),
        .X(carry_follower_cout)
    );
endmodule
module mux_tree_tapbuf_size6_mem
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    ccff_head,
    prog_clk,
    prog_reset,
    ccff_tail,
    mem_out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input ccff_head;
    input prog_clk;
    input prog_reset;
    output ccff_tail;
    output [0:2]mem_out;

    wire ccff_head;
    wire ccff_tail;
    wire [0:2]mem_out;
    wire prog_clk;
    wire prog_reset;

assign ccff_tail = mem_out[2];
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(ccff_head),
        .RESET_B(prog_reset),
        .Q(mem_out[0])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[0]),
        .RESET_B(prog_reset),
        .Q(mem_out[1])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[1]),
        .RESET_B(prog_reset),
        .Q(mem_out[2])
    );
endmodule
module io(
          `ifdef USE_POWER_PINS
          VPWR,
          VGND, 
          `endif
          IO_ISOL_N,
          SOC_IN,
          SOC_OUT,
          SOC_DIR,
          FPGA_OUT,
          FPGA_DIR,
          FPGA_IN);
  
`ifdef USE_POWER_PINS
input VPWR;
input VGND;
`endif     
//----- GLOBAL PORTS -----
input [0:0] IO_ISOL_N;
//----- GPIN PORTS -----
input [0:0] SOC_IN;
//----- GPOUT PORTS -----
output [0:0] SOC_OUT;
//----- GPOUT PORTS -----
output [0:0] SOC_DIR;
//----- INPUT PORTS -----
input [0:0] FPGA_OUT;
//----- INPUT PORTS -----
input [0:0] FPGA_DIR;
//----- OUTPUT PORTS -----
output [0:0] FPGA_IN;

//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----


//----- BEGIN Registered ports -----
//----- END Registered ports -----

// ----- Internal logic should start here -----
  wire SOC_DIR_N;

  //
  sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE (                                  
                                        `ifdef USE_POWER_PINS 
                                        .VPWR(VPWR), 
                                        .VGND(VGND),  
                                        `endif 
                                        .B_N(IO_ISOL_N),
                                        .A(FPGA_DIR),
                                        .X(SOC_DIR)
                                       );

  //
  sky130_fd_sc_hd__inv_1 INV_SOC_DIR (`ifdef USE_POWER_PINS .VPWR(VPWR), .VGND(VGND),`endif .A(SOC_DIR), .Y(SOC_DIR_N));
  sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE (
                                            `ifdef USE_POWER_PINS 
                                            .VPWR(VPWR), 
                                            .VGND(VGND),  
                                            `endif 
                                            .TE_B(SOC_DIR_N),
                                            .A(SOC_IN),
                                            .Z(FPGA_IN)
                                            );

  //
  sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE (
                                            `ifdef USE_POWER_PINS 
                                             .VPWR(VPWR), 
                                             .VGND(VGND),  
                                             `endif 
                                             .TE_B(SOC_DIR),
                                             .A(FPGA_OUT),
                                             .Z(SOC_OUT)
                                             );

// ----- Internal logic should end here -----
endmodule
module mux_tree_tapbuf_size8
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    in,
    sram,
    sram_inv,
    out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input [0:7]in;
    input [0:3]sram;
    input [0:3]sram_inv;
    output out;

    wire const1_0_const1;
    wire [0:7]in;
    wire out;
    wire sky130_fd_sc_hd__mux2_1_0_X;
    wire sky130_fd_sc_hd__mux2_1_1_X;
    wire sky130_fd_sc_hd__mux2_1_2_X;
    wire sky130_fd_sc_hd__mux2_1_3_X;
    wire sky130_fd_sc_hd__mux2_1_4_X;
    wire sky130_fd_sc_hd__mux2_1_5_X;
    wire sky130_fd_sc_hd__mux2_1_6_X;
    wire sky130_fd_sc_hd__mux2_1_7_X;
    wire [0:3]sram;
    wire [0:3]sram_inv;

    const1 const1_0_
    (
        .const1(const1_0_const1)
    );
    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[1]),
        .A1(in[0]),
        .S(sram[0]),
        .X(sky130_fd_sc_hd__mux2_1_0_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[2]),
        .A1(sky130_fd_sc_hd__mux2_1_0_X),
        .S(sram[1]),
        .X(sky130_fd_sc_hd__mux2_1_1_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l2_in_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[4]),
        .A1(in[3]),
        .S(sram[1]),
        .X(sky130_fd_sc_hd__mux2_1_2_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l2_in_2_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[6]),
        .A1(in[5]),
        .S(sram[1]),
        .X(sky130_fd_sc_hd__mux2_1_3_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l2_in_3_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(const1_0_const1),
        .A1(in[7]),
        .S(sram[1]),
        .X(sky130_fd_sc_hd__mux2_1_4_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l3_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(sky130_fd_sc_hd__mux2_1_2_X),
        .A1(sky130_fd_sc_hd__mux2_1_1_X),
        .S(sram[2]),
        .X(sky130_fd_sc_hd__mux2_1_5_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l3_in_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(sky130_fd_sc_hd__mux2_1_4_X),
        .A1(sky130_fd_sc_hd__mux2_1_3_X),
        .S(sram[2]),
        .X(sky130_fd_sc_hd__mux2_1_6_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l4_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(sky130_fd_sc_hd__mux2_1_6_X),
        .A1(sky130_fd_sc_hd__mux2_1_5_X),
        .S(sram[3]),
        .X(sky130_fd_sc_hd__mux2_1_7_X)
    );
    sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A(sky130_fd_sc_hd__mux2_1_7_X),
        .X(out)
    );
endmodule
module mux_tree_tapbuf_size2_mem
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    ccff_head,
    prog_clk,
    prog_reset,
    ccff_tail,
    mem_out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input ccff_head;
    input prog_clk;
    input prog_reset;
    output ccff_tail;
    output [0:1]mem_out;

    wire ccff_head;
    wire ccff_tail;
    wire [0:1]mem_out;
    wire prog_clk;
    wire prog_reset;

assign ccff_tail = mem_out[1];
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(ccff_head),
        .RESET_B(prog_reset),
        .Q(mem_out[0])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[0]),
        .RESET_B(prog_reset),
        .Q(mem_out[1])
    );
endmodule
module mux_tree_tapbuf_size10_mem
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    ccff_head,
    prog_clk,
    prog_reset,
    ccff_tail,
    mem_out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input ccff_head;
    input prog_clk;
    input prog_reset;
    output ccff_tail;
    output [0:3]mem_out;

    wire ccff_head;
    wire ccff_tail;
    wire [0:3]mem_out;
    wire prog_clk;
    wire prog_reset;

assign ccff_tail = mem_out[3];
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(ccff_head),
        .RESET_B(prog_reset),
        .Q(mem_out[0])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[0]),
        .RESET_B(prog_reset),
        .Q(mem_out[1])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[1]),
        .RESET_B(prog_reset),
        .Q(mem_out[2])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[2]),
        .RESET_B(prog_reset),
        .Q(mem_out[3])
    );
endmodule
module logical_tile_io_mode_io_
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    ccff_head,
    gfpga_pad_io_soc_in,
    io_outpad,
    isol_n,
    prog_clk,
    prog_reset,
    ccff_tail,
    gfpga_pad_io_soc_dir,
    gfpga_pad_io_soc_out,
    io_inpad
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input ccff_head;
    input gfpga_pad_io_soc_in;
    input io_outpad;
    input isol_n;
    input prog_clk;
    input prog_reset;
    output ccff_tail;
    output gfpga_pad_io_soc_dir;
    output gfpga_pad_io_soc_out;
    output io_inpad;

    wire ccff_head;
    wire ccff_tail;
    wire direct_interc_1_out;
    wire gfpga_pad_io_soc_dir;
    wire gfpga_pad_io_soc_in;
    wire gfpga_pad_io_soc_out;
    wire io_inpad;
    wire io_outpad;
    wire isol_n;
    wire logical_tile_io_mode_physical__iopad_0_iopad_inpad;
    wire prog_clk;
    wire prog_reset;

    direct_interc direct_interc_0_
    (
        .in(logical_tile_io_mode_physical__iopad_0_iopad_inpad),
        .out(io_inpad)
    );
    direct_interc direct_interc_1_
    (
        .in(io_outpad),
        .out(direct_interc_1_out)
    );
    logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0
    (

        `ifdef USE_POWER_PINS 
        .VPWR(VPWR), 
        .VGND(VGND),  
        `endif 
        .ccff_head(ccff_head),
        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
        .iopad_outpad(direct_interc_1_out),
        .isol_n(isol_n),
        .prog_clk(prog_clk),
        .prog_reset(prog_reset),
        .ccff_tail(ccff_tail),
        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
        .iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad)
    );
endmodule
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    ccff_head,
    frac_lut4_in,
    prog_clk,
    prog_reset,
    ccff_tail,
    frac_lut4_lut2_out,
    frac_lut4_lut3_out,
    frac_lut4_lut4_out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input ccff_head;
    input [0:3]frac_lut4_in;
    input prog_clk;
    input prog_reset;
    output ccff_tail;
    output [0:1]frac_lut4_lut2_out;
    output [0:1]frac_lut4_lut3_out;
    output frac_lut4_lut4_out;

    wire ccff_head;
    wire ccff_tail;
    wire frac_lut4_0__undriven_mode_inv;
    wire [0:15]frac_lut4_0__undriven_sram_inv;
    wire frac_lut4_0_mode;
    wire [0:15]frac_lut4_0_sram;
    wire [0:3]frac_lut4_in;
    wire [0:1]frac_lut4_lut2_out;
    wire [0:1]frac_lut4_lut3_out;
    wire frac_lut4_lut4_out;
    wire prog_clk;
    wire prog_reset;

    frac_lut4 frac_lut4_0_
    (
            
        `ifdef USE_POWER_PINS 
        .VPWR(VPWR), 
        .VGND(VGND),  
        `endif 
        .in(frac_lut4_in),
        .mode(frac_lut4_0_mode),
        .mode_inv(frac_lut4_0__undriven_mode_inv),
        .sram(frac_lut4_0_sram),
        .sram_inv(frac_lut4_0__undriven_sram_inv),
        .lut2_out(frac_lut4_lut2_out),
        .lut3_out(frac_lut4_lut3_out),
        .lut4_out(frac_lut4_lut4_out)
    );
    frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem
    (     
        `ifdef USE_POWER_PINS 
        .VPWR(VPWR), 
        .VGND(VGND),  
        `endif 
        .ccff_head(ccff_head),
        .prog_clk(prog_clk),
        .prog_reset(prog_reset),
        .ccff_tail(ccff_tail),
        .mem_out({frac_lut4_0_sram[0], frac_lut4_0_sram[1], frac_lut4_0_sram[2], frac_lut4_0_sram[3], frac_lut4_0_sram[4], frac_lut4_0_sram[5], frac_lut4_0_sram[6], frac_lut4_0_sram[7], frac_lut4_0_sram[8], frac_lut4_0_sram[9], frac_lut4_0_sram[10], frac_lut4_0_sram[11], frac_lut4_0_sram[12], frac_lut4_0_sram[13], frac_lut4_0_sram[14], frac_lut4_0_sram[15], frac_lut4_0_mode})
    );
endmodule
module mux_tree_tapbuf_size4
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    in,
    sram,
    sram_inv,
    out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input [0:3]in;
    input [0:2]sram;
    input [0:2]sram_inv;
    output out;

    wire const1_0_const1;
    wire [0:3]in;
    wire out;
    wire sky130_fd_sc_hd__mux2_1_0_X;
    wire sky130_fd_sc_hd__mux2_1_1_X;
    wire sky130_fd_sc_hd__mux2_1_2_X;
    wire sky130_fd_sc_hd__mux2_1_3_X;
    wire [0:2]sram;
    wire [0:2]sram_inv;

    const1 const1_0_
    (
        .const1(const1_0_const1)
    );
    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[1]),
        .A1(in[0]),
        .S(sram[0]),
        .X(sky130_fd_sc_hd__mux2_1_0_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[2]),
        .A1(sky130_fd_sc_hd__mux2_1_0_X),
        .S(sram[1]),
        .X(sky130_fd_sc_hd__mux2_1_1_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l2_in_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(const1_0_const1),
        .A1(in[3]),
        .S(sram[1]),
        .X(sky130_fd_sc_hd__mux2_1_2_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l3_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(sky130_fd_sc_hd__mux2_1_2_X),
        .A1(sky130_fd_sc_hd__mux2_1_1_X),
        .S(sram[2]),
        .X(sky130_fd_sc_hd__mux2_1_3_X)
    );
    sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A(sky130_fd_sc_hd__mux2_1_3_X),
        .X(out)
    );
endmodule
module logical_tile_io_mode_physical__iopad
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    ccff_head,
    gfpga_pad_io_soc_in,
    iopad_outpad,
    isol_n,
    prog_clk,
    prog_reset,
    ccff_tail,
    gfpga_pad_io_soc_dir,
    gfpga_pad_io_soc_out,
    iopad_inpad
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input ccff_head;
    input gfpga_pad_io_soc_in;
    input iopad_outpad;
    input isol_n;
    input prog_clk;
    input prog_reset;
    output ccff_tail;
    output gfpga_pad_io_soc_dir;
    output gfpga_pad_io_soc_out;
    output iopad_inpad;

    wire ccff_head;
    wire ccff_tail;
    wire gfpga_pad_io_soc_dir;
    wire gfpga_pad_io_soc_in;
    wire gfpga_pad_io_soc_out;
    wire io_0_en;
    wire iopad_inpad;
    wire iopad_outpad;
    wire isol_n;
    wire prog_clk;
    wire prog_reset;

    io io_0_
    (   
        `ifdef USE_POWER_PINS 
        .VPWR(VPWR), 
        .VGND(VGND),  
        `endif 
        .FPGA_DIR(io_0_en),
        .FPGA_OUT(iopad_outpad),
        .IO_ISOL_N(isol_n),
        .SOC_IN(gfpga_pad_io_soc_in),
        .FPGA_IN(iopad_inpad),
        .SOC_DIR(gfpga_pad_io_soc_dir),
        .SOC_OUT(gfpga_pad_io_soc_out)
    );
    io_sky130_fd_sc_hd__dfrtp_1_mem io_sky130_fd_sc_hd__dfrtp_1_mem
    (
        `ifdef USE_POWER_PINS 
        .VPWR(VPWR), 
        .VGND(VGND),  
        `endif 
        .ccff_head(ccff_head),
        .prog_clk(prog_clk),
        .prog_reset(prog_reset),
        .ccff_tail(ccff_tail),
        .mem_out(io_0_en)
    );
endmodule
module mux_tree_tapbuf_size11_mem
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    ccff_head,
    prog_clk,
    prog_reset,
    ccff_tail,
    mem_out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input ccff_head;
    input prog_clk;
    input prog_reset;
    output ccff_tail;
    output [0:3]mem_out;

    wire ccff_head;
    wire ccff_tail;
    wire [0:3]mem_out;
    wire prog_clk;
    wire prog_reset;

assign ccff_tail = mem_out[3];
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(ccff_head),
        .RESET_B(prog_reset),
        .Q(mem_out[0])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[0]),
        .RESET_B(prog_reset),
        .Q(mem_out[1])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[1]),
        .RESET_B(prog_reset),
        .Q(mem_out[2])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[2]),
        .RESET_B(prog_reset),
        .Q(mem_out[3])
    );
endmodule
module mux_tree_tapbuf_size3
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    in,
    sram,
    sram_inv,
    out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input [0:2]in;
    input [0:1]sram;
    input [0:1]sram_inv;
    output out;

    wire const1_0_const1;
    wire [0:2]in;
    wire out;
    wire sky130_fd_sc_hd__mux2_1_0_X;
    wire sky130_fd_sc_hd__mux2_1_1_X;
    wire sky130_fd_sc_hd__mux2_1_2_X;
    wire [0:1]sram;
    wire [0:1]sram_inv;

    const1 const1_0_
    (
        .const1(const1_0_const1)
    );
    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[1]),
        .A1(in[0]),
        .S(sram[0]),
        .X(sky130_fd_sc_hd__mux2_1_0_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l1_in_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(const1_0_const1),
        .A1(in[2]),
        .S(sram[0]),
        .X(sky130_fd_sc_hd__mux2_1_1_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(sky130_fd_sc_hd__mux2_1_1_X),
        .A1(sky130_fd_sc_hd__mux2_1_0_X),
        .S(sram[1]),
        .X(sky130_fd_sc_hd__mux2_1_2_X)
    );
    sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A(sky130_fd_sc_hd__mux2_1_2_X),
        .X(out)
    );
endmodule
module mux_tree_tapbuf_size2
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    in,
    sram,
    sram_inv,
    out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input [0:1]in;
    input [0:1]sram;
    input [0:1]sram_inv;
    output out;

    wire const1_0_const1;
    wire [0:1]in;
    wire out;
    wire sky130_fd_sc_hd__mux2_1_0_X;
    wire sky130_fd_sc_hd__mux2_1_1_X;
    wire [0:1]sram;
    wire [0:1]sram_inv;

    const1 const1_0_
    (
        .const1(const1_0_const1)
    );
    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[1]),
        .A1(in[0]),
        .S(sram[0]),
        .X(sky130_fd_sc_hd__mux2_1_0_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(const1_0_const1),
        .A1(sky130_fd_sc_hd__mux2_1_0_X),
        .S(sram[1]),
        .X(sky130_fd_sc_hd__mux2_1_1_X)
    );
    sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A(sky130_fd_sc_hd__mux2_1_1_X),
        .X(out)
    );
endmodule
module frac_lut4
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    in,
    mode,
    mode_inv,
    sram,
    sram_inv,
    lut2_out,
    lut3_out,
    lut4_out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input [0:3]in;
    input mode;
    input mode_inv;
    input [0:15]sram;
    input [0:15]sram_inv;
    output [0:1]lut2_out;
    output [0:1]lut3_out;
    output lut4_out;

    wire [0:3]in;
    wire [0:1]lut2_out;
    wire [0:1]lut3_out;
    wire lut4_out;
    wire mode;
    wire mode_inv;
    wire sky130_fd_sc_hd__buf_2_0_X;
    wire sky130_fd_sc_hd__buf_2_1_X;
    wire sky130_fd_sc_hd__buf_2_2_X;
    wire sky130_fd_sc_hd__buf_2_3_X;
    wire sky130_fd_sc_hd__inv_1_0_Y;
    wire sky130_fd_sc_hd__inv_1_1_Y;
    wire sky130_fd_sc_hd__inv_1_2_Y;
    wire sky130_fd_sc_hd__inv_1_3_Y;
    wire sky130_fd_sc_hd__or2_1_0_X;
    wire [0:15]sram;
    wire [0:15]sram_inv;

    frac_lut4_mux frac_lut4_mux_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.in(sram),
        .sram({sky130_fd_sc_hd__buf_2_0_X, sky130_fd_sc_hd__buf_2_1_X, sky130_fd_sc_hd__buf_2_2_X, sky130_fd_sc_hd__buf_2_3_X}),
        .sram_inv({sky130_fd_sc_hd__inv_1_0_Y, sky130_fd_sc_hd__inv_1_1_Y, sky130_fd_sc_hd__inv_1_2_Y, sky130_fd_sc_hd__inv_1_3_Y}),
        .lut2_out(lut2_out),
        .lut3_out(lut3_out),
        .lut4_out(lut4_out)
    );
    sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A(in[0]),
        .X(sky130_fd_sc_hd__buf_2_0_X)
    );
    sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A(in[1]),
        .X(sky130_fd_sc_hd__buf_2_1_X)
    );
    sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A(in[2]),
        .X(sky130_fd_sc_hd__buf_2_2_X)
    );
    sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A(sky130_fd_sc_hd__or2_1_0_X),
        .X(sky130_fd_sc_hd__buf_2_3_X)
    );
    sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A(in[0]),
        .Y(sky130_fd_sc_hd__inv_1_0_Y)
    );
    sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A(in[1]),
        .Y(sky130_fd_sc_hd__inv_1_1_Y)
    );
    sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A(in[2]),
        .Y(sky130_fd_sc_hd__inv_1_2_Y)
    );
    sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A(sky130_fd_sc_hd__or2_1_0_X),
        .Y(sky130_fd_sc_hd__inv_1_3_Y)
    );
    sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or2_1_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A(mode),
        .B(in[3]),
        .X(sky130_fd_sc_hd__or2_1_0_X)
    );
endmodule
module mux_tree_tapbuf_size5
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    in,
    sram,
    sram_inv,
    out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input [0:4]in;
    input [0:2]sram;
    input [0:2]sram_inv;
    output out;

    wire const1_0_const1;
    wire [0:4]in;
    wire out;
    wire sky130_fd_sc_hd__mux2_1_0_X;
    wire sky130_fd_sc_hd__mux2_1_1_X;
    wire sky130_fd_sc_hd__mux2_1_2_X;
    wire sky130_fd_sc_hd__mux2_1_3_X;
    wire sky130_fd_sc_hd__mux2_1_4_X;
    wire [0:2]sram;
    wire [0:2]sram_inv;

    const1 const1_0_
    (
        .const1(const1_0_const1)
    );
    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[1]),
        .A1(in[0]),
        .S(sram[0]),
        .X(sky130_fd_sc_hd__mux2_1_0_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l1_in_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[3]),
        .A1(in[2]),
        .S(sram[0]),
        .X(sky130_fd_sc_hd__mux2_1_1_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(sky130_fd_sc_hd__mux2_1_1_X),
        .A1(sky130_fd_sc_hd__mux2_1_0_X),
        .S(sram[1]),
        .X(sky130_fd_sc_hd__mux2_1_2_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l2_in_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(const1_0_const1),
        .A1(in[4]),
        .S(sram[1]),
        .X(sky130_fd_sc_hd__mux2_1_3_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l3_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(sky130_fd_sc_hd__mux2_1_3_X),
        .A1(sky130_fd_sc_hd__mux2_1_2_X),
        .S(sram[2]),
        .X(sky130_fd_sc_hd__mux2_1_4_X)
    );
    sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A(sky130_fd_sc_hd__mux2_1_4_X),
        .X(out)
    );
endmodule
module sky130_fd_sc_hd__dfrtp_1
(
    CLK,
    D,
    RESET_B,
    Q
);

    input CLK;
    input D;
    input RESET_B;
    output Q;

    wire CLK;
    wire D;
    wire Q;
    wire RESET_B;

endmodule
module sky130_fd_sc_hd__sdfrtp_1
(
    CLK,
    D,
    RESET_B,
    SCD,
    SCE,
    Q
);

    input CLK;
    input D;
    input RESET_B;
    input SCD;
    input SCE;
    output Q;

    wire CLK;
    wire D;
    wire Q;
    wire RESET_B;
    wire SCD;
    wire SCE;

endmodule
module sky130_fd_sc_hd__inv_2
(
    A,
    Y
);

    input A;
    output Y;

    wire A;
    wire Y;

endmodule
module sky130_fd_sc_hd__mux2_1
(
    A0,
    A1,
    S,
    X
);

    input A0;
    input A1;
    input S;
    output X;

    wire A0;
    wire A1;
    wire S;
    wire X;

endmodule
module sky130_fd_sc_hd__inv_1
(
    A,
    Y
);

    input A;
    output Y;

    wire A;
    wire Y;

endmodule
module sky130_fd_sc_hd__mux2_1_wrapper
(
    A0,
    A1,
    S,
    X
);

    input A0;
    input A1;
    input S;
    output X;

    wire A0;
    wire A1;
    wire S;
    wire X;

endmodule
module sky130_fd_sc_hd__buf_2
(
    A,
    X
);

    input A;
    output X;

    wire A;
    wire X;

endmodule
module sky130_fd_sc_hd__buf_4
(
    A,
    X
);

    input A;
    output X;

    wire A;
    wire X;

endmodule
module sky130_fd_sc_hd__or2_1
(
    A,
    B,
    X
);

    input A;
    input B;
    output X;

    wire A;
    wire B;
    wire X;

endmodule
module RegfileModule 
  (
   input wire 		clk,

   input wire [4 : 0] 	Ra,
   input wire [4 : 0] 	Rb,
   input wire [4 : 0] 	Rc,

   input wire 		WERF,
   input wire 		RA2SEL,

   input wire [31 : 0] 	WD,

   input wire [4:0] 	XPReg,
   input wire 		WASEL,

   output wire [31 : 0] RD1,
   output wire [31 : 0] RD2
   );
   
   // Connects RA2 selection mux to ra2 port
   // on register file
   reg [4 : 0] 		ra2_loc;
   
   wire [4:0] 		WA;
   assign WA = WASEL ? XPReg : Rc;
   
   // Register file module instantiation for
   // memory declaration
   RegisterFile reg_file_instance_0 
     (
      .clk_i(clk),
       
      .w_add_i(WA),        // Rc <25:21>
      .w_dat_i(WD),
      .write_en_i(WERF),
       
      .a_add_sel(Ra),
      .b_add_sel(ra2_loc),
       
      .r_port_a_o(RD1),
      .r_port_b_o(RD2)
      );

   // Logic for selection of register 2
   always @(*) begin
       #2
         if (RA2SEL == 1'b1) begin
             ra2_loc = Rc;
         end else begin
             ra2_loc = Rb;
         end
   end
endmodule
module PCAdder #(
    parameter ARCHITECTURE = 32,
    parameter INCREMENT = 32'h00000004
)(
    input wire [ARCHITECTURE-1:0] pc_in_i,
    output wire [ARCHITECTURE-1:0] inc_pc_o
);

    Rip32 f_Adder_instance_1(
        .a_i(pc_in_i), 
        .b_i(INCREMENT), 
        .cin(1'b0),

        .cout(),
        .sum_o(inc_pc_o)
    );

endmodule
module ProgramCounter #(
			parameter ARCHITECTURE = 32 
			)(
			  input wire 			 RESET, // Resets PC to 0x0
			  input wire 			 clk, // Global clk
			  input wire [2:0] 		 PCSEL, // Selects source of next PC 
			  input wire [31:0] 		 XAddr,
			  input wire [31:0] 		 RstAddr,
			  input wire [31:0] 		 IllOpAddr,
			  input wire 			 IRQ,
			  input wire [31:0] 		 JT,
			  input wire [31:0] 		 ShftSextC, // 4*SextC 

			  output wire [ARCHITECTURE-1:0] pc_o, // Program counter output
			  output wire [31:0] 		 PcIncr,
			  output wire [31:0] 		 branchOffset
			  );
   
   reg [31:0] 						 pc;
   
   wire 						 MsbJt;
   
   assign pc_o = RESET ? RstAddr : pc;
   assign PcIncr = pc + 32'h00000004;
   assign MsbJt = pc[31] ?  JT[31] : pc[31];
   assign branchOffset = PcIncr + ShftSextC;

   always @(posedge clk) begin
       if (RESET) begin
	   pc = RstAddr;
       end else if (IRQ & ~pc_o[31]) begin
	   pc = XAddr;
       end else begin
	   case (PCSEL)
	     3'b000:
	       pc = {{pc[31]}, {PcIncr[30:0]}};
	     3'b001:
	       pc = {{pc[31]}, {branchOffset[30:0]}};
	     3'b010:
	       pc = {{MsbJt}, {JT[30:0]}};
	     3'b011:
	       pc = IllOpAddr;
	     3'b100:
	       pc = XAddr;
	     default:
	       pc = RstAddr;
	   endcase // case (PCSEL)
       end // else: !if(RESET)
   end // always @ (*)
endmodule // ProgramCounter
module MemoryModule (
    input wire 	      clk,
    
    input wire [31:0] InstAdd, // Address to fetch instruction from
    input wire [31:0] DataAdd, // Address to fetch data from
    input wire [31:0] MemDataContent,
  
    input wire 	      DataReadEn, // Enables output from memory
    input wire 	      DataWriteEn, // Enables writing to memory at end of cur. cycle

    output wire [31:0] MemDataOut, // Data from memory
    output wire [31:0] MemInstOut // Instruction from memory		   
);

   reg [31:0] 	       mem [8192:0]; // 32 KiB memory

   initial begin
      
   end

   always @(posedge clk) begin
      if (DataWriteEn & !DataReadEn) begin
	 mem[DataAdd] = MemDataContent;
      end
   end
   
   assign MemInstOut = mem[InstAdd];
   assign MemDataOut = mem[DataAdd];
      
endmodule // MemoryModule
module Rip32(sum_o, cout, a_i, b_i, cin);
    //main module of 16 bit Ripple carry adder
    input [31:0]a_i;
    input [31:0]b_i;
    input cin;
    output cout;
    output [31:0]sum_o;
    
    wire c16, cout;
    Rip16 m1(sum_o[15:0], c16, a_i[15:0], b_i[15:0], cin);
    Rip16 m2(sum_o[31:16], cout, a_i[31:16], b_i[31:16], c16);
endmodule
module Rip16(sum_o, cout, a_i, b_i, cin);
    //main module of 16 bit Ripple carry adder
    input [15:0]a_i;
    input [15:0]b_i;
    input cin;
    output cout;
    output [15:0]sum_o;
    wire c4, c8, c12, cout;
    Rip4 m1(sum_o[3:0], c4, a_i[3:0], b_i[3:0], cin);
    Rip4 m2(sum_o[7:4], c8, a_i[7:4], b_i[7:4], c4);
    Rip4 m3(sum_o[11:8], c12, a_i[11:8], b_i[11:8], c8);
    Rip4 m4(sum_o[15:12], cout, a_i[15:12], b_i[15:12], c12);
endmodule
module Rip4(sum_o, cout, a_i, b_i, cin);
 //sub module for 4 bit Ripple carry adder
    input [3:0]a_i;
    input [3:0]b_i;
    input cin;
    output cout;
    output [3:0]sum_o;
    wire c2, c3, c4, cout;
    Fa m1(sum_o[0], c2, a_i[0], b_i[0], cin);
    Fa m2(sum_o[1], c3, a_i[1], b_i[1], c2);
    Fa m3(sum_o[2], c4, a_i[2], b_i[2], c3);
    Fa m4(sum_o[3], cout, a_i[3], b_i[3], c4);
endmodule
module Fa(sum_o, cout, a_i, b_i, cin);
    //sub module for Full adder
    input a_i, b_i, cin;
    output sum_o, cout;
    wire w1, w2, w3;
    Ha m1(w1, w2, a_i, b_i);
    Ha m2(sum_o, w3, w1, cin);
    or m3(cout, w2, w3);
endmodule
module Ha(sum_o,cout,a_i,b_i);
 //sub module for Half adder
    input a_i,b_i;
    output sum_o,cout;
    xor m1(sum_o,a_i,b_i);
    and m2(cout,a_i,b_i);
endmodule
module RegisterFile (
    input wire 		 clk_i,
    
    input wire [4 : 0] 	 w_add_i,
    input wire [31 : 0]  w_dat_i,
    input wire 		 write_en_i,
    
    input wire [4 : 0] 	 a_add_sel,
    input wire [4 : 0] 	 b_add_sel,

    output wire [31 : 0] r_port_a_o,
    output wire [31 : 0] r_port_b_o
);

    reg [31 : 0] mem [31 : 0];  // 32, 32-bit registers

    // Write to particular register at posedge clk
    always @(posedge clk_i) begin
        if (write_en_i) begin
            if (w_add_i != 5'b11111) begin
                mem[w_add_i] = w_dat_i;
            end
        end
    end

   assign r_port_a_o = (a_add_sel != 5'b11111) ? mem[a_add_sel] : 32'h00000000;
   assign r_port_b_o = (b_add_sel != 5'b11111) ? mem[b_add_sel] : 32'h00000000;
   
endmodule
module Alu
  (
   input wire [5:0]  alufn,
   input wire [31:0] a,
   input wire [31:0] b,

   output reg [31:0] alu,
   output wire 	     z,
   output wire 	     v,
   output wire 	     n
   );

   wire [31:0] 	     asRes, cmpRes, shftRes, boolRes, mulRes;

   AddSub as_inst_0(.alufn0(alufn[0]), .a(a), .b(b), .s(asRes), .z(z), .v(v), .n(n));
   CmpModule cmp_inst_0(.alufn(alufn[2:1]), .a(a), .b(b), .cmp(cmpRes));
   LogicModule log_inst_0(.alufn(alufn), .a(a), .b(b), .res(boolRes));
   ShifterModule shft_inst_0(.alufn(alufn[1:0]), .a(a), .b(b[4:0]), .res(shftRes));
   MultModule mult_inst_0(.a(a), .b(b), .res(mulRes));

   always @(*) begin
       #3
         casex (alufn)
           6'b00xx0x: 
             alu = asRes;
           6'b00xx1x: 
             alu = mulRes;
           6'b01xxxx: 
             alu = boolRes;
           6'b10xxxx: 
             alu = shftRes;
           6'b11xxxx: 
             alu = cmpRes;
           default:
             alu = 32'h00000000;
         endcase        
   end
endmodule
module AddSub
  (
   input wire 	      alufn0,
   input wire [31:0]  a,
   input wire [31:0]  b,

   output wire [31:0] s,
   output wire 	      z,
   output wire 	      v,
   output wire 	      n
   );

   wire [31:0] 	      xb;

   integer 	      i = 0;
   
   assign xb = b ^ {32{alufn0}};
   assign s = a + xb + alufn0;
   assign z = (s == 32'h00000000);
   assign v = (a[31] & xb[31] & (~s[31])) + ((~a[31]) & (~xb[31]) & s[31]);
   assign n = s[31]; 

endmodule
module CmpModule
  (
   input wire [2:1]  alufn,
   input wire [31:0] a,
   input wire [31:0] b,

   output reg [31:0] cmp
   );
   wire [31:0] 	     s;
   wire 	     z;
   wire 	     v;
   wire 	     n;

   AddSub add_sub_inst_0
     ( 
       .alufn0(1'b1), .a(a), .b(b), .s(s), .z(z), .v(v), .n(n)
       );

   // Calculate LSB using combination of z, v, n and alufn[2:1]
   always @(alufn, z, v, n) begin
       if (alufn[2:1] == 2'b01) begin  // A == B
           cmp = {{31{1'b0}}, {z}};
       end else if (alufn[2:1] == 2'b10) begin // A < B
          cmp = {{31{1'b0}}, {n^v}};
       end else if (alufn[2:1] == 2'b11) begin // A <= B
          cmp = {{31{1'b0}}, {z | (n ^ v)}};
       end else begin
      	  cmp = 32'h00000000;
       end
   end

endmodule
module LogicModule
  (
   input wire [5:0]  alufn,
   input wire [31:0] a,
   input wire [31:0] b,

   output reg [31:0] res
   );

   integer 	     i = 0;

   always @(alufn[3:0], a, b) begin
       for (i = 0; i < 32; i = i + 1) begin
           res[i] = alufn[{{a[i]}, {b[i]}}];
       end 
   end

endmodule
module ShifterModule
  (
   input [1:0] 	       alufn,
   input signed [31:0] a,
   input signed [4:0]  b,

   output reg [31:0]   res
   );

   always @(alufn[1:0], a, b[4:0]) begin
       case (alufn[1:0])
         2'b00: 
           res = a << b[4:0];
         2'b01: 
           res = a >> b[4:0];
         2'b10: 
           res = a;
         2'b11: 
           res = a >>> b[4:0];
       endcase // case (alufn[1:0])
   end // always @ (alufn[1:0], a, b[4:0])
   
endmodule
module MultModule 
  (
   input wire [31:0]  a,
   input wire [31:0]  b,

   output wire [31:0] res
   );

   assign res = a * b;

endmodule
module pc_testbench;
    parameter ARCHITECTURE = 32;
    reg     rst_i;
    reg     clk_i;
    wire    [ARCHITECTURE-1:0]  pc_o;

    ProgramCounter #(32) program_counter_test_instance (
        .rst_i(rst_i),
        .clk_i(clk_i),
        .pc_o(pc_o)
    );

    initial begin
        clk_i = 0;
        rst_i = 0;

        #10
        // Initialize PC to zero
        rst_i = 1'b1;
        #10 clk_i = ~clk_i;
        #10 clk_i = ~clk_i;

        #10
        // Increment PC
        rst_i = 1'b0;
        #10 clk_i = ~clk_i;
        #10 clk_i = ~clk_i;

        #10 clk_i = ~clk_i;
        #10 clk_i = ~clk_i;

        #10 clk_i = ~clk_i;
        #10 clk_i = ~clk_i;

        #10 clk_i = ~clk_i;
        #10 clk_i = ~clk_i;
    end

endmodule
module Regfile_module_testbench;

    reg clk_i;

    reg  [4 : 0]     ra_i;
    reg  [4 : 0]     rb_i;
    reg  [4 : 0]     rc_i;

    reg  werf_i;
    reg  ra2sel_i;

    reg  [31 : 0]    wd_i;

    wire [31 : 0]    rd1_o;
    wire [31 : 0]    rd2_o;

    RegfileModule reg_file_module_instance_0 (
        .clk_i(clk_i),
        .ra_i(ra_i),
        .rb_i(rb_i),
        .rc_i(rc_i),
        .werf_i(werf_i),
        .ra2sel_i(ra2sel_i),
        .wd_i(wd_i),
        .rd1_o(rd1_o),
        .rd2_o(rd2_o)
    );

    reg [4 : 0] address = 5'h00000;
    integer i = 0;

    initial begin
        clk_i = 0;

        for (i = 0; i < 32; i = i + 1) begin 
            ra_i = address;
            rb_i = address;
            rc_i = address + 5'h00001;
            ra2sel_i = 1'b0;
            werf_i = 1;
            wd_i = 32'hDEADC0DE + i[31 : 0];

            #5 clk_i = ~clk_i;
            #5 clk_i = ~clk_i;  
            address = address + 5'h00001;      
        end

        address = 5'h00000;
        i = 0;

        #100
        
        for (i = 0; i < 32; i = i + 1) begin 
            ra_i = address;
            rb_i = address;
            rc_i = address + 5'h00001;
            ra2sel_i = 1'b1;
            werf_i = 1;
            wd_i = 32'hDEADC0DE + i[31 : 0];

            #5 clk_i = ~clk_i;
            #5 clk_i = ~clk_i;  
            address = address + 5'h00001;      
        end

        #100
        
        for (i = 0; i < 32; i = i + 1) begin 
            ra_i = address;
            rb_i = address;
            rc_i = address + 5'h00001;
            ra2sel_i = 1'b1;
            werf_i = 0;
            wd_i = 32'hDEADC0DE + i[31 : 0];

            #5 clk_i = ~clk_i;
            #5 clk_i = ~clk_i;  
            address = address + 5'h00001;      
        end

    end

endmodule
module ProcessorTestbench;
   parameter DisplayBufferSize = 256;
   
   reg clk;
   reg RESET;
   reg IRQ;
   
   wire [DisplayBufferSize-1:0] DisplayBuffer;

   integer 	i = 0;
   reg [31:0] 	ver[1023:0];
   
   assign expAddress = ver[i];
   
   Processor uut
     (
      .clk(clk),
      .RESET(RESET),
      .IRQ(IRQ),
       
      .DisplayBuffer(DisplayBuffer)
      );
   
   initial begin
       clk = 1;
       RESET = 0;
       IRQ = 0;  
       #20 RESET = 1;
       #25 RESET = 0;
       
   end
   
   always begin
       #40 clk = ~clk;
   end

endmodule // ProcessorTestbench
module PowerOfTwoMemory(
    input wire 	      clk,
		       
    input wire [31:0] InstAdd, // Address to fetch instruction from
    input wire [31:0] DataAdd, // Address to fetch data from
    input wire [31:0] MemDataContent,
		       
    input wire 	      DataReadEn, // Enables output from memory
    input wire 	      DataWriteEn, // Enables writing to memory at end of cur. cycle

    output reg [31:0] MemDataOut, // Data from memory
    output reg [31:0] MemInstOut); // Instruction from memory	
   
   reg [31:0] 	      mem [1023:0];
 	      
   initial begin
       mem[0] = 32'h77FF0008;
       mem[1] = 32'h77FF0001;
       mem[2] = 32'h77FF0001;
       mem[3] = 32'h77FF0005;
       mem[4] = 32'hD33A0001;
       mem[5] = 32'h7BF90001;
       mem[6] = 32'h77FF0002;
       mem[7] = 32'h671F03F7;
       mem[8] = 32'h6FFE0000;
       mem[9] = 32'hc31f0001;
       mem[10] = 32'hC35F0001;
       mem[11] = 32'h8318C000;
       mem[12] = 32'h77DFFFF7;
       mem[13] = 32'h7BF8FFFD;
       mem[14] = 32'hC31F0001;
       mem[15] = 32'h00000000;
   end
   
   always @(posedge clk) begin
       //#1
       if (DataWriteEn) begin
	   mem[DataAdd] = MemDataContent;
	end
   end
   
   always @(DataAdd, InstAdd) begin
       //#2
       MemInstOut = mem[InstAdd];
       MemDataOut = mem[DataAdd];
   end
endmodule // BasicTestMemory