dakies/OSS_Verilog huggingface dataset:
module fifo_xlnx_64x36_2clk(
	din,
	rd_clk,
	rd_en,
	rst,
	wr_clk,
	wr_en,
	dout,
	empty,
	full,
	rd_data_count,
	wr_data_count);


input [35 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [35 : 0] dout;
output empty;
output full;
output [6 : 0] rd_data_count;
output [6 : 0] wr_data_count;

// synthesis translate_off

      FIFO_GENERATOR_V4_3 #(
		.C_COMMON_CLOCK(0),
		.C_COUNT_TYPE(0),
		.C_DATA_COUNT_WIDTH(7),
		.C_DEFAULT_VALUE("BlankString"),
		.C_DIN_WIDTH(36),
		.C_DOUT_RST_VAL("0"),
		.C_DOUT_WIDTH(36),
		.C_ENABLE_RLOCS(0),
		.C_FAMILY("spartan3"),
		.C_FULL_FLAGS_RST_VAL(1),
		.C_HAS_ALMOST_EMPTY(0),
		.C_HAS_ALMOST_FULL(0),
		.C_HAS_BACKUP(0),
		.C_HAS_DATA_COUNT(0),
		.C_HAS_INT_CLK(0),
		.C_HAS_MEMINIT_FILE(0),
		.C_HAS_OVERFLOW(0),
		.C_HAS_RD_DATA_COUNT(1),
		.C_HAS_RD_RST(0),
		.C_HAS_RST(1),
		.C_HAS_SRST(0),
		.C_HAS_UNDERFLOW(0),
		.C_HAS_VALID(0),
		.C_HAS_WR_ACK(0),
		.C_HAS_WR_DATA_COUNT(1),
		.C_HAS_WR_RST(0),
		.C_IMPLEMENTATION_TYPE(2),
		.C_INIT_WR_PNTR_VAL(0),
		.C_MEMORY_TYPE(2),
		.C_MIF_FILE_NAME("BlankString"),
		.C_MSGON_VAL(1),
		.C_OPTIMIZATION_MODE(0),
		.C_OVERFLOW_LOW(0),
		.C_PRELOAD_LATENCY(0),
		.C_PRELOAD_REGS(1),
		.C_PRIM_FIFO_TYPE("512x36"),
		.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
		.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
		.C_PROG_EMPTY_TYPE(0),
		.C_PROG_FULL_THRESH_ASSERT_VAL(63),
		.C_PROG_FULL_THRESH_NEGATE_VAL(62),
		.C_PROG_FULL_TYPE(0),
		.C_RD_DATA_COUNT_WIDTH(7),
		.C_RD_DEPTH(64),
		.C_RD_FREQ(1),
		.C_RD_PNTR_WIDTH(6),
		.C_UNDERFLOW_LOW(0),
		.C_USE_DOUT_RST(1),
		.C_USE_ECC(0),
		.C_USE_EMBEDDED_REG(0),
		.C_USE_FIFO16_FLAGS(0),
		.C_USE_FWFT_DATA_COUNT(1),
		.C_VALID_LOW(0),
		.C_WR_ACK_LOW(0),
		.C_WR_DATA_COUNT_WIDTH(7),
		.C_WR_DEPTH(64),
		.C_WR_FREQ(1),
		.C_WR_PNTR_WIDTH(6),
		.C_WR_RESPONSE_LATENCY(1))
	inst (
		.DIN(din),
		.RD_CLK(rd_clk),
		.RD_EN(rd_en),
		.RST(rst),
		.WR_CLK(wr_clk),
		.WR_EN(wr_en),
		.DOUT(dout),
		.EMPTY(empty),
		.FULL(full),
		.RD_DATA_COUNT(rd_data_count),
		.WR_DATA_COUNT(wr_data_count),
		.CLK(),
		.INT_CLK(),
		.BACKUP(),
		.BACKUP_MARKER(),
		.PROG_EMPTY_THRESH(),
		.PROG_EMPTY_THRESH_ASSERT(),
		.PROG_EMPTY_THRESH_NEGATE(),
		.PROG_FULL_THRESH(),
		.PROG_FULL_THRESH_ASSERT(),
		.PROG_FULL_THRESH_NEGATE(),
		.RD_RST(),
		.SRST(),
		.WR_RST(),
		.ALMOST_EMPTY(),
		.ALMOST_FULL(),
		.DATA_COUNT(),
		.OVERFLOW(),
		.PROG_EMPTY(),
		.PROG_FULL(),
		.VALID(),
		.UNDERFLOW(),
		.WR_ACK(),
		.SBITERR(),
		.DBITERR());


// synthesis translate_on

endmodule
module fifo_xlnx_512x36_2clk_18to36(
	rst,
	wr_clk,
	rd_clk,
	din,
	wr_en,
	rd_en,
	dout,
	full,
	almost_full,
	empty,
	prog_full);


input rst;
input wr_clk;
input rd_clk;
input [17 : 0] din;
input wr_en;
input rd_en;
output [35 : 0] dout;
output full;
output almost_full;
output empty;
output prog_full;

// synthesis translate_off

      FIFO_GENERATOR_V6_1 #(
		.C_COMMON_CLOCK(0),
		.C_COUNT_TYPE(0),
		.C_DATA_COUNT_WIDTH(10),
		.C_DEFAULT_VALUE("BlankString"),
		.C_DIN_WIDTH(18),
		.C_DOUT_RST_VAL("0"),
		.C_DOUT_WIDTH(36),
		.C_ENABLE_RLOCS(0),
		.C_ENABLE_RST_SYNC(1),
		.C_ERROR_INJECTION_TYPE(0),
		.C_FAMILY("spartan3"),
		.C_FULL_FLAGS_RST_VAL(0),
		.C_HAS_ALMOST_EMPTY(0),
		.C_HAS_ALMOST_FULL(1),
		.C_HAS_BACKUP(0),
		.C_HAS_DATA_COUNT(0),
		.C_HAS_INT_CLK(0),
		.C_HAS_MEMINIT_FILE(0),
		.C_HAS_OVERFLOW(0),
		.C_HAS_RD_DATA_COUNT(0),
		.C_HAS_RD_RST(0),
		.C_HAS_RST(1),
		.C_HAS_SRST(0),
		.C_HAS_UNDERFLOW(0),
		.C_HAS_VALID(0),
		.C_HAS_WR_ACK(0),
		.C_HAS_WR_DATA_COUNT(0),
		.C_HAS_WR_RST(0),
		.C_IMPLEMENTATION_TYPE(2),
		.C_INIT_WR_PNTR_VAL(0),
		.C_MEMORY_TYPE(1),
		.C_MIF_FILE_NAME("BlankString"),
		.C_MSGON_VAL(1),
		.C_OPTIMIZATION_MODE(0),
		.C_OVERFLOW_LOW(0),
		.C_PRELOAD_LATENCY(0),
		.C_PRELOAD_REGS(1),
		.C_PRIM_FIFO_TYPE("1kx18"),
		.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
		.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
		.C_PROG_EMPTY_TYPE(0),
		.C_PROG_FULL_THRESH_ASSERT_VAL(1015),
		.C_PROG_FULL_THRESH_NEGATE_VAL(1014),
		.C_PROG_FULL_TYPE(1),
		.C_RD_DATA_COUNT_WIDTH(9),
		.C_RD_DEPTH(512),
		.C_RD_FREQ(1),
		.C_RD_PNTR_WIDTH(9),
		.C_UNDERFLOW_LOW(0),
		.C_USE_DOUT_RST(1),
		.C_USE_ECC(0),
		.C_USE_EMBEDDED_REG(0),
		.C_USE_FIFO16_FLAGS(0),
		.C_USE_FWFT_DATA_COUNT(0),
		.C_VALID_LOW(0),
		.C_WR_ACK_LOW(0),
		.C_WR_DATA_COUNT_WIDTH(10),
		.C_WR_DEPTH(1024),
		.C_WR_FREQ(1),
		.C_WR_PNTR_WIDTH(10),
		.C_WR_RESPONSE_LATENCY(1))
	inst (
		.RST(rst),
		.WR_CLK(wr_clk),
		.RD_CLK(rd_clk),
		.DIN(din),
		.WR_EN(wr_en),
		.RD_EN(rd_en),
		.DOUT(dout),
		.FULL(full),
		.ALMOST_FULL(almost_full),
		.EMPTY(empty),
		.PROG_FULL(prog_full),
		.BACKUP(),
		.BACKUP_MARKER(),
		.CLK(),
		.SRST(),
		.WR_RST(),
		.RD_RST(),
		.PROG_EMPTY_THRESH(),
		.PROG_EMPTY_THRESH_ASSERT(),
		.PROG_EMPTY_THRESH_NEGATE(),
		.PROG_FULL_THRESH(),
		.PROG_FULL_THRESH_ASSERT(),
		.PROG_FULL_THRESH_NEGATE(),
		.INT_CLK(),
		.INJECTDBITERR(),
		.INJECTSBITERR(),
		.WR_ACK(),
		.OVERFLOW(),
		.ALMOST_EMPTY(),
		.VALID(),
		.UNDERFLOW(),
		.DATA_COUNT(),
		.RD_DATA_COUNT(),
		.WR_DATA_COUNT(),
		.PROG_EMPTY(),
		.SBITERR(),
		.DBITERR());


// synthesis translate_on

endmodule
module fifo_xlnx_512x36_2clk_36to18(
	rst,
	wr_clk,
	rd_clk,
	din,
	wr_en,
	rd_en,
	dout,
	full,
	empty);


input rst;
input wr_clk;
input rd_clk;
input [35 : 0] din;
input wr_en;
input rd_en;
output [17 : 0] dout;
output full;
output empty;

// synthesis translate_off

      FIFO_GENERATOR_V6_1 #(
		.C_COMMON_CLOCK(0),
		.C_COUNT_TYPE(0),
		.C_DATA_COUNT_WIDTH(9),
		.C_DEFAULT_VALUE("BlankString"),
		.C_DIN_WIDTH(36),
		.C_DOUT_RST_VAL("0"),
		.C_DOUT_WIDTH(18),
		.C_ENABLE_RLOCS(0),
		.C_ENABLE_RST_SYNC(1),
		.C_ERROR_INJECTION_TYPE(0),
		.C_FAMILY("spartan3"),
		.C_FULL_FLAGS_RST_VAL(0),
		.C_HAS_ALMOST_EMPTY(0),
		.C_HAS_ALMOST_FULL(0),
		.C_HAS_BACKUP(0),
		.C_HAS_DATA_COUNT(0),
		.C_HAS_INT_CLK(0),
		.C_HAS_MEMINIT_FILE(0),
		.C_HAS_OVERFLOW(0),
		.C_HAS_RD_DATA_COUNT(0),
		.C_HAS_RD_RST(0),
		.C_HAS_RST(1),
		.C_HAS_SRST(0),
		.C_HAS_UNDERFLOW(0),
		.C_HAS_VALID(0),
		.C_HAS_WR_ACK(0),
		.C_HAS_WR_DATA_COUNT(0),
		.C_HAS_WR_RST(0),
		.C_IMPLEMENTATION_TYPE(2),
		.C_INIT_WR_PNTR_VAL(0),
		.C_MEMORY_TYPE(1),
		.C_MIF_FILE_NAME("BlankString"),
		.C_MSGON_VAL(1),
		.C_OPTIMIZATION_MODE(0),
		.C_OVERFLOW_LOW(0),
		.C_PRELOAD_LATENCY(0),
		.C_PRELOAD_REGS(1),
		.C_PRIM_FIFO_TYPE("512x36"),
		.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
		.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
		.C_PROG_EMPTY_TYPE(0),
		.C_PROG_FULL_THRESH_ASSERT_VAL(509),
		.C_PROG_FULL_THRESH_NEGATE_VAL(508),
		.C_PROG_FULL_TYPE(0),
		.C_RD_DATA_COUNT_WIDTH(10),
		.C_RD_DEPTH(1024),
		.C_RD_FREQ(1),
		.C_RD_PNTR_WIDTH(10),
		.C_UNDERFLOW_LOW(0),
		.C_USE_DOUT_RST(1),
		.C_USE_ECC(0),
		.C_USE_EMBEDDED_REG(0),
		.C_USE_FIFO16_FLAGS(0),
		.C_USE_FWFT_DATA_COUNT(0),
		.C_VALID_LOW(0),
		.C_WR_ACK_LOW(0),
		.C_WR_DATA_COUNT_WIDTH(9),
		.C_WR_DEPTH(512),
		.C_WR_FREQ(1),
		.C_WR_PNTR_WIDTH(9),
		.C_WR_RESPONSE_LATENCY(1))
	inst (
		.RST(rst),
		.WR_CLK(wr_clk),
		.RD_CLK(rd_clk),
		.DIN(din),
		.WR_EN(wr_en),
		.RD_EN(rd_en),
		.DOUT(dout),
		.FULL(full),
		.EMPTY(empty),
		.BACKUP(),
		.BACKUP_MARKER(),
		.CLK(),
		.SRST(),
		.WR_RST(),
		.RD_RST(),
		.PROG_EMPTY_THRESH(),
		.PROG_EMPTY_THRESH_ASSERT(),
		.PROG_EMPTY_THRESH_NEGATE(),
		.PROG_FULL_THRESH(),
		.PROG_FULL_THRESH_ASSERT(),
		.PROG_FULL_THRESH_NEGATE(),
		.INT_CLK(),
		.INJECTDBITERR(),
		.INJECTSBITERR(),
		.ALMOST_FULL(),
		.WR_ACK(),
		.OVERFLOW(),
		.ALMOST_EMPTY(),
		.VALID(),
		.UNDERFLOW(),
		.DATA_COUNT(),
		.RD_DATA_COUNT(),
		.WR_DATA_COUNT(),
		.PROG_FULL(),
		.PROG_EMPTY(),
		.SBITERR(),
		.DBITERR());


// synthesis translate_on

endmodule
module packet_padder36
#(
    parameter RX_IDLE_FLUSH_CYCLES = 65536, //about 1ms at 64MHz clock
    parameter MAX_LUT_LINES32 = 4096 //how many 32bit lines in a LUT
)
(
    input clk, input reset,
    input [35:0] data_i,
    input src_rdy_i,
    output dst_rdy_o,
    output [35:0] data_o,
    output src_rdy_o,
    input dst_rdy_i,
    input rx_dsp_active
);

    //state machine definitions
    localparam STATE_READ_HDR = 0;
    localparam STATE_WRITE_HDR = 1;
    localparam STATE_FORWARD = 2;
    localparam STATE_WRITE_PAD = 3;
    reg [1:0] state;

    //keep track of the outgoing lines
    reg [15:0] line_count;
    wire line_count_done = line_count == 1;
    wire lut_is_empty = line_count == MAX_LUT_LINES32;
    always @(posedge clk) begin
        if (reset) begin
            line_count <= MAX_LUT_LINES32;
        end
        else if (src_rdy_o && dst_rdy_i) begin
            line_count <= (line_count_done)? MAX_LUT_LINES32 : line_count - 1;
        end
    end

    //count the number of cycles since RX data so we can force a flush
    reg [17:0] non_rx_cycles;
    wire idle_timeout = (non_rx_cycles == RX_IDLE_FLUSH_CYCLES);
    always @(posedge clk) begin
        if(reset || state != STATE_READ_HDR) begin
            non_rx_cycles <= 0;
        end
        else if (~idle_timeout) begin
            non_rx_cycles <= non_rx_cycles + 1;
        end
    end

    //flush when we have written data to a LUT and either idle or non active DSP
    wire force_flush = ~lut_is_empty && (idle_timeout || ~rx_dsp_active);

    //the padding state machine
    reg [31:0] vita_hdr;
    reg has_vita_hdr;
    always @(posedge clk) begin
        if (reset) begin
            state <= STATE_READ_HDR;
        end
        else case(state)

        STATE_READ_HDR: begin
            if (src_rdy_i && dst_rdy_o && data_i[32]) begin
                vita_hdr <= data_i[31:0];
                has_vita_hdr <= 1;
                state <= (data_i[15:0] > line_count)? state <= STATE_WRITE_PAD : STATE_WRITE_HDR;
            end
            else if (force_flush) begin
                has_vita_hdr <= 0;
                state <= STATE_WRITE_PAD;
            end
        end

        STATE_WRITE_HDR: begin
            if (src_rdy_o && dst_rdy_i) begin
                state <= STATE_FORWARD;
            end
        end

        STATE_FORWARD: begin
            if (src_rdy_i && dst_rdy_o && data_i[33]) begin
                state <= STATE_READ_HDR;
            end
        end

        STATE_WRITE_PAD: begin
            if (src_rdy_o && dst_rdy_i && line_count_done) begin
                state <= (has_vita_hdr)? STATE_WRITE_HDR : STATE_READ_HDR;
            end
        end

        endcase //state
    end

    //assign outgoing signals
    assign dst_rdy_o = (state == STATE_READ_HDR)? 1 : ((state == STATE_FORWARD)? dst_rdy_i : 0);
    assign src_rdy_o = (state == STATE_WRITE_HDR || state == STATE_WRITE_PAD)? 1 : ((state == STATE_FORWARD )? src_rdy_i : 0);
    assign data_o = (state == STATE_WRITE_HDR)? {4'b0001, vita_hdr} : ((state == STATE_FORWARD)? data_i : 0);

endmodule // packet_padder36
module fifo36_to_gpmc16
#(
    parameter FIFO_SIZE = 9,

    //not ready until minimum xfers of occupancy available
    parameter MIN_OCC16 = 2
)
(
    //input fifo interface
    input fifo_clk, input fifo_rst,
    input [35:0] in_data,
    input in_src_rdy,
    output in_dst_rdy,

    //output interface
    input gpif_clk, input gpif_rst,
    output [15:0] out_data,
    output valid,
    input enable,
    output eof,
    output reg has_data
);

    wire [15:0] fifo_occ;

    always @(posedge gpif_clk)
        has_data <= (fifo_occ >= MIN_OCC16);

    wire [35:0] data_int;
    wire src_rdy_int, dst_rdy_int;

    fifo_2clock_cascade #(.WIDTH(36), .SIZE(6)) fifo_2clk
     (.wclk(fifo_clk), .datain(in_data), .src_rdy_i(in_src_rdy), .dst_rdy_o(in_dst_rdy), .space(),
      .rclk(gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(),
      .arst(fifo_rst | gpif_rst));

    wire [18:0] data19_int;
    wire data19_src_rdy_int, data19_dst_rdy_int;

    fifo36_to_fifo19 #(.LE(1)) f36_to_f19
     (.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
      .f36_datain(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int),
      .f19_dataout(data19_int), .f19_src_rdy_o(data19_src_rdy_int), .f19_dst_rdy_i(data19_dst_rdy_int) );

    wire [17:0] data18_int;
    fifo_cascade #(.WIDTH(18), .SIZE(FIFO_SIZE+1)) occ_ctrl_fifo
     (.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
      .datain(data19_int[17:0]), .src_rdy_i(data19_src_rdy_int), .dst_rdy_o(data19_dst_rdy_int), .space(),
      .dataout(data18_int), .src_rdy_o(valid), .dst_rdy_i(enable), .occupied(fifo_occ));

    assign out_data = data18_int[15:0];
    assign eof = data18_int[17];

endmodule //fifo_to_gpmc16
module gpmc16_to_fifo36
#(
    parameter FIFO_SIZE = 9,

    //not ready until minimum xfers of space available
    parameter MIN_SPACE16 = 128
)
(
    //input interface
    input gpif_clk, input gpif_rst,
    input [15:0] in_data,
    input valid,
    output reg ready,

    //output fifo interface
    input fifo_clk, input fifo_rst,
    output [35:0] out_data,
    output out_src_rdy,
    input out_dst_rdy
);

    wire [35:0] data_int;
    wire src_rdy_int, dst_rdy_int;
    wire [18:0] refr_data;
    wire refr_src_rdy, refr_dst_rdy;

    wire [15:0] fifo_space;

    always @(posedge gpif_clk)
        ready <= (fifo_space >= MIN_SPACE16/2);

   packet_reframer packet_reframer 
     (.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
      .data_i(in_data), .src_rdy_i(valid), .dst_rdy_o(),
      .data_o(refr_data), .src_rdy_o(refr_src_rdy), .dst_rdy_i(refr_dst_rdy));

   fifo19_to_fifo36 #(.LE(1)) f19_to_f36
     (.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
      .f19_datain(refr_data), .f19_src_rdy_i(refr_src_rdy), .f19_dst_rdy_o(refr_dst_rdy),
      .f36_dataout(data_int), .f36_src_rdy_o(src_rdy_int), .f36_dst_rdy_i(dst_rdy_int));

   fifo_2clock_cascade #(.WIDTH(36), .SIZE(FIFO_SIZE)) fifo_2clk
     (.wclk(gpif_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(fifo_space),
      .rclk(fifo_clk), .dataout(out_data), .src_rdy_o(out_src_rdy), .dst_rdy_i(out_dst_rdy), .occupied(),
      .arst(fifo_rst | gpif_rst));

endmodule //fifo_to_gpmc16
module packet_reframer
  (input clk, input reset, input clear,
   input [15:0] data_i,
   input src_rdy_i,
   output dst_rdy_o,
   output [18:0] data_o,
   output src_rdy_o,
   input dst_rdy_i,
   output reg state,
   output eof_out,
   output reg [15:0] length);

   //reg state;
   //reg [15:0] length;
   
   localparam RF_IDLE = 0;
   localparam RF_PKT = 1;
   
   always @(posedge clk)
     if(reset | clear)
       state <= RF_IDLE;
     else
       if(src_rdy_i & dst_rdy_i)
	 case(state)
	   RF_IDLE :
	     begin
		length <= {data_i[14:0],1'b0};
		state <= RF_PKT;
	     end
	   RF_PKT :
	     begin
		if(eof_out) state <= RF_IDLE;
		length <= length - 1;
	     end
	 endcase // case (state)
   
   assign dst_rdy_o = dst_rdy_i; // this is a little pessimistic but ok
   assign src_rdy_o = src_rdy_i;
   
   wire occ_out = 0;
   assign eof_out = (state == RF_PKT) & (length == 2);
   wire sof_out = (state == RF_IDLE);
   assign data_o = {occ_out, eof_out, sof_out, data_i[15:0]};
   
      
endmodule // packet_reframer
module gpif_rd
  (input gpif_clk, input gpif_rst,
   output [15:0] gpif_data, input gpif_rd, input gpif_ep,
   output reg gpif_empty_d, output reg gpif_empty_c,
   output reg gpif_flush,
   
   input sys_clk, input sys_rst,
   input [18:0] data_i, input src_rdy_i, output dst_rdy_o,
   input [18:0] resp_i, input resp_src_rdy_i, output resp_dst_rdy_o,
   output [31:0] debug
   );
   
   wire [18:0] 	 data_o; // occ bit indicates flush
   wire [17:0] 	 resp_o; // no occ bit
   wire 	 final_rdy_data, final_rdy_resp;
   
   // 33/257 Bug Fix
   reg [8:0] 	read_count;
   always @(negedge gpif_clk)
     if(gpif_rst)
       read_count <= 0;
     else if(gpif_rd)
       read_count <= read_count + 1;
     else
       read_count <= 0;

   // Data Path
   wire [18:0] 	data_int;
   wire 	src_rdy_int, dst_rdy_int;
   fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) rd_fifo_2clk
     (.wclk(sys_clk), .datain(data_i[18:0]), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(),
      .rclk(~gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(),
      .arst(sys_rst));

   reg [7:0] 	packet_count;
   wire 	consume_data_line = gpif_rd & ~gpif_ep & ~read_count[8];
   wire 	produce_eop = src_rdy_int & dst_rdy_int & data_int[17];
   wire 	consume_sop = consume_data_line & final_rdy_data & data_o[16];
   wire 	consume_eop = consume_data_line & final_rdy_data & data_o[17];
   
   fifo_cascade #(.WIDTH(19), .SIZE(10)) rd_fifo
     (.clk(~gpif_clk), .reset(gpif_rst), .clear(0),
      .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(),
      .dataout(data_o), .src_rdy_o(final_rdy_data), .dst_rdy_i(consume_data_line), .occupied());

   always @(negedge gpif_clk)
     if(gpif_rst)
       packet_count <= 0;
     else
       if(produce_eop & ~consume_sop)
	 packet_count <= packet_count + 1;
       else if(consume_sop & ~produce_eop)
	 packet_count <= packet_count - 1;

   always @(negedge gpif_clk)
     if(gpif_rst)
       gpif_empty_d <= 1;
     else
       gpif_empty_d <= ~|packet_count;

   // Use occ bit to signal a gpif flush
   always @(negedge gpif_clk)
     if(gpif_rst)
       gpif_flush <= 0;
     else if(consume_eop & data_o[18])
       gpif_flush <= ~gpif_flush;
   
   // Response Path
   wire [15:0] 	resp_fifolevel;
   wire 	consume_resp_line = gpif_rd & gpif_ep & ~read_count[4];

   fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) resp_fifo_2clk
     (.wclk(sys_clk), .datain(resp_i[17:0]), .src_rdy_i(resp_src_rdy_i), .dst_rdy_o(resp_dst_rdy_o), .space(),
      .rclk(~gpif_clk), .dataout(resp_o), 
      .src_rdy_o(final_rdy_resp), .dst_rdy_i(consume_resp_line), .occupied(resp_fifolevel),
      .arst(sys_rst));

   // FIXME -- handle short packets
   
   always @(negedge gpif_clk)
     if(gpif_rst)
       gpif_empty_c <= 1;
     else
       gpif_empty_c <= resp_fifolevel < 16;
   
   // Output Mux
   assign gpif_data = gpif_ep ? resp_o[15:0] : data_o[15:0];

   assign debug = { { 16'd0 },
		    { data_int[17:16], data_o[17:16], packet_count[3:0] },
		    { consume_sop, consume_eop, final_rdy_data, data_o[18], consume_data_line, consume_resp_line, src_rdy_int, dst_rdy_int} };
   
endmodule // gpif_rd
module packet_splitter
  #(parameter FRAME_LEN=256)
   (input clk, input reset, input clear,
    input  [7:0] frames_per_packet,
    input [18:0] data_i,
    input src_rdy_i,
    output dst_rdy_o,
    output [18:0] data_o,
    output src_rdy_o,
    input dst_rdy_i,
    output [31:0] debug0,
    output [31:0] debug1);
   
   reg [1:0] state;
   reg [15:0] length;
   reg [15:0] frame_len;
   reg [7:0]  frame_count;
   
   localparam PS_IDLE = 0;
   localparam PS_FRAME = 1;
   localparam PS_NEW_FRAME = 2;
   localparam PS_PAD = 3;

   wire       eof_i = data_i[17];
   
   always @(posedge clk)
     if(reset | clear)
       begin
	  state <= PS_IDLE;
	  frame_count <= 0;
       end
     else
       case(state)
	 PS_IDLE :
	   if(src_rdy_i & dst_rdy_i)
	     begin
		length <= { data_i[14:0],1'b0};
		frame_len <= FRAME_LEN;
		state <= PS_FRAME;
		frame_count <= 1;
	     end
	 PS_FRAME :
	   if(src_rdy_i & dst_rdy_i)
	     if((frame_len == 2) & ((length == 2) | eof_i))
	       state <= PS_IDLE;
	     else if(frame_len == 2)
	       begin
		  length <= length - 1;
		  state <= PS_NEW_FRAME;
		  frame_count <= frame_count + 1;
	       end
	     else if((length == 2)|eof_i)
	       begin
		  frame_len <= frame_len - 1;
		  state <= PS_PAD;
	       end
	     else
	       begin
		  frame_len <= frame_len - 1;
		  length <= length - 1;
	       end
	 PS_NEW_FRAME :
	   if(src_rdy_i & dst_rdy_i)
	     begin
		frame_len <= FRAME_LEN;
		if((length == 2)|eof_i)
		  state <= PS_PAD;
		else
		  begin
		     state <= PS_FRAME;
		     length <= length - 1;
		  end // else: !if((length == 2)|eof_i)
	     end // if (src_rdy_i & dst_rdy_i)
	 
	 PS_PAD :
	   if(dst_rdy_i)
	     if(frame_len == 2)
	       state <= PS_IDLE;
	     else
	       frame_len <= frame_len - 1;

       endcase // case (state)

   wire next_state_is_idle = dst_rdy_i & (frame_len==2) & 
	( (state==PS_PAD) | ( (state==PS_FRAME) & src_rdy_i & ((length==2)|eof_i) ) );
	  
	 
	
   
   assign dst_rdy_o = dst_rdy_i & (state != PS_PAD);
   assign src_rdy_o = src_rdy_i | (state == PS_PAD);
   
   wire eof_out = (frame_len == 2) & (state != PS_IDLE) & (state != PS_NEW_FRAME);
   wire sof_out = (state == PS_IDLE) | (state == PS_NEW_FRAME);
   wire occ_out = eof_out & next_state_is_idle & (frames_per_packet != frame_count);
   
   wire [15:0] data_out = data_i[15:0];
   assign data_o = {occ_out, eof_out, sof_out, data_out};
   
   assign debug0 = { 8'd0, dst_rdy_o, src_rdy_o, next_state_is_idle, eof_out, sof_out, occ_out, state[1:0], frame_count[7:0], frames_per_packet[7:0] };
   assign debug1 = { length[15:0], frame_len[15:0] };
   
endmodule // packet_splitter
module gpif_wr_tb();
   
   reg sys_clk = 0;
   reg sys_rst = 1;
   reg gpif_clk = 0;
   reg gpif_rst = 1;
      
   reg [15:0] gpif_data;
   reg 	      WR = 0, EP = 0;

   wire       CF, DF;
   
   wire       gpif_full_d, gpif_full_c;
   wire [18:0] data_o, ctrl_o;
   wire        src_rdy, dst_rdy;
   wire        ctrl_src_rdy, ctrl_dst_rdy;

   assign ctrl_dst_rdy = 1;
   assign dst_rdy = 1;
   
   initial $dumpfile("gpif_wr_tb.vcd");
   initial $dumpvars(0,gpif_wr_tb);

   initial #1000 gpif_rst = 0;
   initial #1000 sys_rst = 0;
   always #64 gpif_clk <= ~gpif_clk;
   always #47.9 sys_clk <= ~sys_clk;

   wire [18:0] data_int;
   wire        src_rdy_int, dst_rdy_int;
   
   gpif_wr gpif_write
     (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), 
      .gpif_data(gpif_data), .gpif_wr(WR), .gpif_ep(EP),
      .gpif_full_d(DF), .gpif_full_c(CF),
      
      .sys_clk(sys_clk), .sys_rst(sys_rst),
      .data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int),
      .ctrl_o(ctrl_o), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy) );

   packet_reframer tx_packet_reframer 
     (.clk(sys_clk), .reset(sys_rst), .clear(0),
      .data_i(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int),
      .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));

   always @(posedge sys_clk)
     if(ctrl_src_rdy & ctrl_dst_rdy)
       $display("CTRL: %x",ctrl_o);

   always @(posedge sys_clk)
     if(src_rdy & dst_rdy)
       begin
	  if(data_o[16])
	    $display("<-------- DATA SOF--------->");
	  $display("DATA: %x",data_o);
	  if(data_o[17])
	    $display("<-------- DATA EOF--------->");
       end
   
   initial
     begin
	#10000;
	repeat (1)
	  begin
	     WR <= 1;
	     gpif_data <= 10;  // Length
	     @(posedge gpif_clk);
	     gpif_data <= 16'h00;
	     @(posedge gpif_clk);
	     repeat(254)
	       begin
		  gpif_data <= gpif_data + 1;
		  @(posedge gpif_clk);
	       end
	     WR <= 0;
	     repeat (20)
	       @(posedge gpif_clk);
	     WR <= 1;
	     gpif_data <= 16'h5;
	     @(posedge gpif_clk);
	     repeat(254)
	       begin
		  gpif_data <= gpif_data - 1;
		  @(posedge gpif_clk);
	       end
	  end
     end // initial begin
   
   initial #100000 $finish;
   
     
endmodule // gpif_wr_tb
module gpif_wr
  (input gpif_clk, input gpif_rst,
   input [15:0] gpif_data, input gpif_wr, input gpif_ep,
   output reg gpif_full_d, output reg gpif_full_c,

   input sys_clk, input sys_rst,
   output [18:0] data_o, output src_rdy_o, input dst_rdy_i,
   output [18:0] ctrl_o, output ctrl_src_rdy_o, input ctrl_dst_rdy_i,
   output [31:0] debug );

   reg 		 wr_reg, ep_reg;
   reg [15:0] 	 gpif_data_reg;
   
   always @(posedge gpif_clk)
     begin
	ep_reg <= gpif_ep;
	wr_reg <= gpif_wr;
	gpif_data_reg <= gpif_data;
     end

   reg [9:0] write_count;
   
   always @(posedge gpif_clk)
     if(gpif_rst)
       write_count <= 0;
     else if(wr_reg)
       write_count <= write_count + 1;
     else
       write_count <= 0;

   reg 	     sop;
   wire      eop = (write_count == 255);
   wire      eop_ctrl = (write_count == 15);
   
   always @(posedge gpif_clk)
     sop <= gpif_wr & ~wr_reg;

   // Data Path
   wire [15:0] fifo_space;
   always @(posedge gpif_clk)
     if(gpif_rst)
       gpif_full_d <= 1;
     else
       gpif_full_d <= fifo_space < 256;

   wire [17:0] data_int;
   wire        src_rdy_int, dst_rdy_int;

   fifo_cascade #(.WIDTH(18), .SIZE(10)) wr_fifo
     (.clk(gpif_clk), .reset(gpif_rst), .clear(0),
      .datain({eop,sop,gpif_data_reg}), .src_rdy_i(~ep_reg & wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space),
      .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied());
   
   fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) wr_fifo_2clk
     (.wclk(gpif_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(),
      .rclk(sys_clk), .dataout(data_o[17:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(),
      .arst(sys_rst));
   assign data_o[18] = 1'b0;
   
   // Control Path
   wire [15:0] ctrl_fifo_space;
   always @(posedge gpif_clk)
     if(gpif_rst)
       gpif_full_c <= 1;
     else
       gpif_full_c <= ctrl_fifo_space < 16;
   
   fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) ctrl_fifo_2clk
     (.wclk(gpif_clk), .datain({1'b0,eop_ctrl,sop,gpif_data_reg}), 
      .src_rdy_i(ep_reg & wr_reg & ~write_count[4]), .dst_rdy_o(), .space(ctrl_fifo_space),
      .rclk(sys_clk), .dataout(ctrl_o[18:0]), 
      .src_rdy_o(ctrl_src_rdy_o), .dst_rdy_i(ctrl_dst_rdy_i), .occupied(),
      .arst(sys_rst));

   assign debug = { 16'd0, ep_reg, wr_reg, eop, sop, (~ep_reg & wr_reg & ~write_count[8]), src_rdy_int, dst_rdy_int, write_count[8:0]};
   
endmodule // gpif_wr
module gpif_tb();
   
   reg sys_clk = 0;
   reg sys_rst = 1;
   reg gpif_clk = 0;
   reg gpif_rst = 1;
      
   reg [15:0] gpif_data;
   reg 	      WR = 0, EP = 0;

   wire       CF, DF;
   
   wire       gpif_full_d, gpif_full_c;
   wire [18:0] data_o, ctrl_o, data_splt;
   wire        src_rdy, dst_rdy, src_rdy_splt, dst_rdy_splt;
   wire        ctrl_src_rdy, ctrl_dst_rdy;

   assign ctrl_dst_rdy = 1;
   
   initial $dumpfile("gpif_tb.vcd");
   initial $dumpvars(0,gpif_tb);

   initial #1000 gpif_rst = 0;
   initial #1000 sys_rst = 0;
   always #64 gpif_clk <= ~gpif_clk;
   always #47.9 sys_clk <= ~sys_clk;

   wire [18:0] data_int;
   wire        src_rdy_int, dst_rdy_int;

   assign dst_rdy_splt = 1;
   
   gpif_wr gpif_write
     (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), 
      .gpif_data(gpif_data), .gpif_wr(WR), .gpif_ep(EP),
      .gpif_full_d(DF), .gpif_full_c(CF),
      
      .sys_clk(sys_clk), .sys_rst(sys_rst),
      .data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int),
      .ctrl_o(ctrl_o), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy) );

   packet_reframer tx_packet_reframer 
     (.clk(sys_clk), .reset(sys_rst), .clear(0),
      .data_i(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int),
      .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));

   packet_splitter #(.FRAME_LEN(256)) rx_packet_splitter
     (.clk(sys_clk), .reset(sys_rst), .clear(0),
      .frames_per_packet(2),
      .data_i(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
      .data_o(data_splt), .src_rdy_o(src_rdy_splt), .dst_rdy_i(dst_rdy_splt));

   always @(posedge sys_clk)
     if(ctrl_src_rdy & ctrl_dst_rdy)
       $display("CTRL: %x",ctrl_o);

   always @(posedge sys_clk)
     if(src_rdy_splt & dst_rdy_splt)
       begin
	  if(data_splt[16])
	    $display("<-------- DATA SOF--------->");
	  $display("DATA: %x",data_splt);
	  if(data_splt[17])
	    $display("<-------- DATA EOF--------->");
       end
   
   initial
     begin
	#10000;
	repeat (1)
	  begin
	     @(posedge gpif_clk);
	     
	     WR <= 1;
	     gpif_data <= 256;  // Length
	     @(posedge gpif_clk);
	     gpif_data <= 16'h00;
	     @(posedge gpif_clk);
	     repeat(254)
	       begin
		  gpif_data <= gpif_data + 1;
		  @(posedge gpif_clk);
	       end
	     WR <= 0;

	     while(DF)
	       @(posedge gpif_clk);
	     repeat (16)
	       @(posedge gpif_clk);
	     
	     WR <= 1;
	     repeat(256)
	       begin
		  gpif_data <= gpif_data - 1;
		  @(posedge gpif_clk);
	       end
	     WR <= 0;


/*
	     while(DF)
	       @(posedge gpif_clk);
	     	     
	     repeat (20)
	       @(posedge gpif_clk);
	     WR <= 1;
	     gpif_data <= 16'h5;
	     @(posedge gpif_clk);
	     gpif_data <= 16'h00;
	     @(posedge gpif_clk);
	     repeat(254)
	       begin
		  gpif_data <= gpif_data - 1;
		  @(posedge gpif_clk);
	       end
	     WR <= 0;
 */
	  end
     end // initial begin
   
   initial #200000 $finish;
   
     
endmodule // gpif_tb
module packet_splitter_tb();
   
   reg sys_clk = 0;
   reg sys_rst = 1;
   reg gpif_clk = 0;
   reg gpif_rst = 1;
      
   reg [15:0] gpif_data;
   reg 	      WR = 0, EP = 0;

   wire       CF, DF;
   
   wire       gpif_full_d, gpif_full_c;
   wire [18:0] data_o, ctrl_o, data_splt;
   wire        src_rdy, dst_rdy, src_rdy_splt, dst_rdy_splt;
   wire        ctrl_src_rdy, ctrl_dst_rdy;

   assign ctrl_dst_rdy = 1;
   
   initial $dumpfile("packet_splitter_tb.vcd");
   initial $dumpvars(0,packet_splitter_tb);

   initial #1000 gpif_rst = 0;
   initial #1000 sys_rst = 0;
   always #64 gpif_clk <= ~gpif_clk;
   always #47.9 sys_clk <= ~sys_clk;

   wire [35:0] data_int;
   wire        src_rdy_int, dst_rdy_int;

   assign dst_rdy_splt = 1;

   vita_pkt_gen vita_pkt_gen
     (.clk(sys_clk), .reset(sys_rst) , .clear(0),
      .len(512),.data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int));

   fifo36_to_fifo19 #(.LE(1)) f36_to_f19
     (.clk(sys_clk), .reset(sys_rst), .clear(0),
      .f36_datain(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int),
      .f19_dataout(data_o), .f19_src_rdy_o(src_rdy), .f19_dst_rdy_i(dst_rdy));
   		 
   packet_splitter #(.FRAME_LEN(13)) rx_packet_splitter
     (.clk(sys_clk), .reset(sys_rst), .clear(0),
      .frames_per_packet(4),
      .data_i(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
      .data_o(data_splt), .src_rdy_o(src_rdy_splt), .dst_rdy_i(dst_rdy_splt));

   always @(posedge sys_clk)
     if(ctrl_src_rdy & ctrl_dst_rdy)
       $display("CTRL: %x",ctrl_o);

   always @(posedge sys_clk)
     if(src_rdy_splt & dst_rdy_splt)
       begin
	  if(data_splt[16])
	    $display("<-------- DATA SOF--------->");
	  $display("DATA: %x",data_splt);
	  if(data_splt[17])
	    $display("<-------- DATA EOF--------->");
       end
   
   initial
     begin
	#10000;
	repeat (1)
	  begin
	     @(posedge gpif_clk);
	     
	     WR <= 1;
	     gpif_data <= 256;  // Length
	     @(posedge gpif_clk);
	     gpif_data <= 16'h00;
	     @(posedge gpif_clk);
	     repeat(254)
	       begin
		  gpif_data <= gpif_data + 1;
		  @(posedge gpif_clk);
	       end
	     WR <= 0;

	     while(DF)
	       @(posedge gpif_clk);
	     repeat (16)
	       @(posedge gpif_clk);
	     
	     WR <= 1;
	     repeat(256)
	       begin
		  gpif_data <= gpif_data - 1;
		  @(posedge gpif_clk);
	       end
	     WR <= 0;


/*
	     while(DF)
	       @(posedge gpif_clk);
	     	     
	     repeat (20)
	       @(posedge gpif_clk);
	     WR <= 1;
	     gpif_data <= 16'h5;
	     @(posedge gpif_clk);
	     gpif_data <= 16'h00;
	     @(posedge gpif_clk);
	     repeat(254)
	       begin
		  gpif_data <= gpif_data - 1;
		  @(posedge gpif_clk);
	       end
	     WR <= 0;
 */
	  end
     end // initial begin
   
   initial #200000 $finish;
   
     
endmodule // packet_splitter_tb
module simple_gpio(
  clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o,
  gpio
);

  //
  // Inputs & outputs
  //
  parameter io = 8;            // number of GPIOs

  // 8bit WISHBONE bus slave interface
  input         clk_i;         // clock
  input         rst_i;         // reset (asynchronous active low)
  input         cyc_i;         // cycle
  input         stb_i;         // strobe
  input         adr_i;         // address adr_i[1]
  input         we_i;          // write enable
  input  [ 7:0] dat_i;         // data output
  output [ 7:0] dat_o;         // data input
  output        ack_o;         // normal bus termination

  // GPIO pins
  inout  [io:1] gpio;

  //
  // Module body
  //
  reg [io:1] ctrl, line;                  // ControlRegister, LineRegister
  reg [io:1] lgpio, llgpio;               // LatchedGPIO pins

  //
  // perform parameter checks
  //
  // synopsys translate_off
  initial
  begin
      if(io > 8)
        $display("simple_gpio: max. 8 GPIOs supported.");
  end
  // synopsys translate_on

  //
  // WISHBONE interface

  wire wb_acc = cyc_i & stb_i;            // WISHBONE access
  wire wb_wr  = wb_acc & we_i;            // WISHBONE write access

  always @(posedge clk_i or negedge rst_i)
    if (~rst_i)
      begin
          ctrl <= #1 {io{1'b0}};
          line <= #1 {io{1'b0}};
      end
    else if (wb_wr)
       if ( adr_i )
         line <= #1 dat_i[io-1:0];
       else
         ctrl <= #1 dat_i[io-1:0];


  reg [7:0] dat_o;
  always @(posedge clk_i)
    if ( adr_i )
      dat_o <= #1 { {(8-io){1'b0}}, llgpio};
    else
      dat_o <= #1 { {(8-io){1'b0}}, ctrl};

  reg ack_o;
  always @(posedge clk_i or negedge rst_i)
    if (~rst_i)
      ack_o <= #1 1'b0;
    else
      ack_o <= #1 wb_acc & !ack_o;


  //
  // GPIO section

  // latch GPIO input pins
  always @(posedge clk_i)
    lgpio <= #1 gpio;

  // latch again (reduce meta-stability risc)
  always @(posedge clk_i)
    llgpio <= #1 lgpio;

  // assign GPIO outputs
  integer n;
  reg [io:1] igpio; // temporary internal signal

  always @(ctrl or line)
    for(n=1;n<=io;n=n+1)
      igpio[n] <= ctrl[n] ? line[n] : 1'bz;

  assign gpio = igpio;

endmodule
module aeMB_core (/*AUTOARG*/
   // Outputs
   iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o,
   fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
   // Inputs
   sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i,
   fsl_ack_i, dwb_dat_i, dwb_ack_i
   );
   // Instruction WB address space
   parameter ISIZ = 32;
   // Data WB address space
   parameter DSIZ = 32;
   // Multiplier
   parameter MUL = 1;
   // Barrel Shifter
   parameter BSF = 1;   

   /*AUTOOUTPUT*/
   // Beginning of automatic outputs (from unused autoinst outputs)
   output [DSIZ-1:2]	dwb_adr_o;		// From edk32 of aeMB_edk32.v
   output [31:0]	dwb_dat_o;		// From edk32 of aeMB_edk32.v
   output [3:0]		dwb_sel_o;		// From edk32 of aeMB_edk32.v
   output		dwb_stb_o;		// From edk32 of aeMB_edk32.v
   output		dwb_wre_o;		// From edk32 of aeMB_edk32.v
   output [6:2]		fsl_adr_o;		// From edk32 of aeMB_edk32.v
   output [31:0]	fsl_dat_o;		// From edk32 of aeMB_edk32.v
   output		fsl_stb_o;		// From edk32 of aeMB_edk32.v
   output [1:0]		fsl_tag_o;		// From edk32 of aeMB_edk32.v
   output		fsl_wre_o;		// From edk32 of aeMB_edk32.v
   output [ISIZ-1:2]	iwb_adr_o;		// From edk32 of aeMB_edk32.v
   output		iwb_stb_o;		// From edk32 of aeMB_edk32.v
   // End of automatics
   /*AUTOINPUT*/
   // Beginning of automatic inputs (from unused autoinst inputs)
   input		dwb_ack_i;		// To edk32 of aeMB_edk32.v
   input [31:0]		dwb_dat_i;		// To edk32 of aeMB_edk32.v
   input		fsl_ack_i;		// To edk32 of aeMB_edk32.v
   input [31:0]		fsl_dat_i;		// To edk32 of aeMB_edk32.v
   input		iwb_ack_i;		// To edk32 of aeMB_edk32.v
   input [31:0]		iwb_dat_i;		// To edk32 of aeMB_edk32.v
   input		sys_clk_i;		// To edk32 of aeMB_edk32.v
   input		sys_int_i;		// To edk32 of aeMB_edk32.v
   input		sys_rst_i;		// To edk32 of aeMB_edk32.v
   // End of automatics
   /*AUTOWIRE*/

   // INSTANTIATIONS /////////////////////////////////////////////////////////////////

   /* 
    aeMB_edk32 AUTO_TEMPLATE (
    .dwb_adr_o(dwb_adr_o[DSIZ-1:2]),
    .iwb_adr_o(iwb_adr_o[ISIZ-1:2]),
    );
    */
   
   aeMB_edk32 #(ISIZ, DSIZ, MUL, BSF)
   edk32 (/*AUTOINST*/
	  // Outputs
	  .dwb_adr_o			(dwb_adr_o[DSIZ-1:2]),	 // Templated
	  .dwb_dat_o			(dwb_dat_o[31:0]),
	  .dwb_sel_o			(dwb_sel_o[3:0]),
	  .dwb_stb_o			(dwb_stb_o),
	  .dwb_wre_o			(dwb_wre_o),
	  .fsl_adr_o			(fsl_adr_o[6:2]),
	  .fsl_dat_o			(fsl_dat_o[31:0]),
	  .fsl_stb_o			(fsl_stb_o),
	  .fsl_tag_o			(fsl_tag_o[1:0]),
	  .fsl_wre_o			(fsl_wre_o),
	  .iwb_adr_o			(iwb_adr_o[ISIZ-1:2]),	 // Templated
	  .iwb_stb_o			(iwb_stb_o),
	  // Inputs
	  .dwb_ack_i			(dwb_ack_i),
	  .dwb_dat_i			(dwb_dat_i[31:0]),
	  .fsl_ack_i			(fsl_ack_i),
	  .fsl_dat_i			(fsl_dat_i[31:0]),
	  .iwb_ack_i			(iwb_ack_i),
	  .iwb_dat_i			(iwb_dat_i[31:0]),
	  .sys_int_i			(sys_int_i),
	  .sys_clk_i			(sys_clk_i),
	  .sys_rst_i			(sys_rst_i));
   
   
endmodule // aeMB_core
module aeMB_core_BE
  #(parameter ISIZ=32, parameter DSIZ=32, 
    parameter MUL=0, parameter BSF=0)
    (input sys_clk_i,
     input sys_rst_i,
     // Instruction port
     output [ISIZ-1:0] if_adr,
     input [31:0] if_dat,
     // Data port
     output dwb_we_o,
     output dwb_stb_o,
     output [DSIZ-1:0] dwb_adr_o,
     output [31:0] dwb_dat_o,
     input [31:0] dwb_dat_i,
     input dwb_ack_i,
     output [3:0] dwb_sel_o,
     output dwb_cyc_o,
     
     input sys_int_i, 
     input sys_exc_i);


   wire [ISIZ-1:0] iwb_adr_o;
   wire [31:0] 	   iwb_dat_i;
   wire 	   iwb_ack_i;
   wire 	   iwb_stb_o;
   
   assign dwb_cyc_o = dwb_stb_o;
   assign iwb_ack_i = 1'b1;
   assign if_adr = iwb_adr_o[ISIZ-1:0];
   assign iwb_dat_i = if_dat;

   // Note some "wishbone" instruction fetch signals pruned on external interface
   // but not propogated change deep into aeMB.
   aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ),.MUL(MUL),.BSF(BSF))
     aeMB_edk32 (.sys_clk_i(sys_clk_i), 
		 .sys_rst_i(sys_rst_i),
		 // Instruction Port
		 .iwb_stb_o(iwb_stb_o),
		 .iwb_adr_o(iwb_adr_o[ISIZ-1:2]),
		 .iwb_ack_i(iwb_ack_i),
		 .iwb_dat_i(iwb_dat_i),
		 // Data port
		 .dwb_wre_o(dwb_we_o),
		 .dwb_stb_o(dwb_stb_o),
		 .dwb_adr_o(dwb_adr_o[DSIZ-1:2]),
		 .dwb_ack_i(dwb_ack_i),
		 .dwb_sel_o(dwb_sel_o),
		 .dwb_dat_i(dwb_dat_i),
		 .dwb_dat_o(dwb_dat_o),
	
		 .fsl_wre_o(),
		 .fsl_tag_o(),
		 .fsl_stb_o(),
		 .fsl_dat_o(),
		 .fsl_adr_o(),
		 .fsl_dat_i(32'b0),
		 .fsl_ack_i(1'b0),
		 .sys_int_i(sys_int_i) );
   
   assign  iwb_adr_o[1:0] = 2'b0;
   assign  dwb_adr_o[1:0] = 2'b0;

endmodule // aeMB_core_BE
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);

//parameter Tp=1;

input       Clk;              // Input clock (Host clock)
input       Reset;            // Reset signal
input [7:0] Divider;          // Divider (input clock will be divided by the Divider[7:0])

output      Mdc;              // Output clock
output      MdcEn;            // Enable signal is asserted for one Clk period before Mdc rises.
output      MdcEn_n;          // Enable signal is asserted for one Clk period before Mdc falls.

reg         Mdc;
reg   [7:0] Counter;

wire        CountEq0;
wire  [7:0] CounterPreset;
wire  [7:0] TempDivider;


assign TempDivider[7:0]   = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1;               // We are counting half of period


// Counter counts half period
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    Counter[7:0] <= 8'h1;
  else
    begin
      if(CountEq0)
        begin
          Counter[7:0] <= CounterPreset[7:0];
        end
      else
        Counter[7:0] <= Counter - 8'h1;
    end
end


// Mdc is asserted every other half period
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    Mdc <= 1'b0;
  else
    begin
      if(CountEq0)
        Mdc <= ~Mdc;
    end
end


assign CountEq0 = Counter == 8'h0;
assign MdcEn = CountEq0 & ~Mdc;
assign MdcEn_n = CountEq0 & Mdc;

endmodule
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect, 
                    LatchByte, ShiftedBit, Prsd, LinkFail);


input       Clk;              // Input clock (Host clock)
input       Reset;            // Reset signal
input       MdcEn_n;          // Enable signal is asserted for one Clk period before Mdc falls.
input       Mdi;              // MII input data
input [4:0] Fiad;             // PHY address
input [4:0] Rgad;             // Register address (within the selected PHY)
input [15:0]CtrlData;         // Control data (data to be written to the PHY)
input       WriteOp;          // The current operation is a PHY register write operation
input [3:0] ByteSelect;       // Byte select
input [1:0] LatchByte;        // Byte select for latching (read operation)

output      ShiftedBit;       // Bit shifted out of the shift register
output[15:0]Prsd;             // Read Status Data (data read from the PHY)
output      LinkFail;         // Link Integrity Signal

reg   [7:0] ShiftReg;         // Shift register for shifting the data in and out
reg   [15:0]Prsd;
reg         LinkFail;




// ShiftReg[7:0] :: Shift Register Data
always @ (posedge Clk or posedge Reset) 
begin
  if(Reset)
    begin
      ShiftReg[7:0] <= 8'h0;
      Prsd[15:0] <= 16'h0;
      LinkFail <= 1'b0;
    end
  else
    begin
      if(MdcEn_n)
        begin 
          if(|ByteSelect)
            begin
              case (ByteSelect[3:0])
                4'h1 :    ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
                4'h2 :    ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
                4'h4 :    ShiftReg[7:0] <= CtrlData[15:8];
                4'h8 :    ShiftReg[7:0] <= CtrlData[7:0];
                default : ShiftReg[7:0] <= 8'h0;
              endcase
            end 
          else
            begin
              ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};
              if(LatchByte[0])
                begin
                  Prsd[7:0] <= {ShiftReg[6:0], Mdi};
                  if(Rgad == 5'h01)
                    LinkFail <= ~ShiftReg[1];  // this is bit [2], because it is not shifted yet
                end
              else
                begin
                  if(LatchByte[1])
                    Prsd[15:8] <= {ShiftReg[6:0], Mdi};
                end
            end
        end
    end
end


assign ShiftedBit = ShiftReg[7];


endmodule
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);

input         Clk;                // Host Clock
input         Reset;              // General Reset
input         WriteOp;            // Write Operation Latch (When asserted, write operation is in progress)
input         NoPre;              // No Preamble (no 32-bit preamble)
input         InProgress;         // Operation in progress
input         ShiftedBit;         // This bit is output of the shift register and is connected to the Mdo signal
input   [6:0] BitCounter;         // Bit Counter
input         MdcEn_n;            // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.

output        Mdo;                // MII Management Data Output
output        MdoEn;              // MII Management Data Output Enable

wire          SerialEn;

reg           MdoEn_2d;
reg           MdoEn_d;
reg           MdoEn;

reg           Mdo_2d;
reg           Mdo_d;
reg           Mdo;                // MII Management Data Output



// Generation of the Serial Enable signal (enables the serialization of the data)
assign SerialEn =  WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
                | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));


// Generation of the MdoEn signal
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    begin
      MdoEn_2d <= 1'b0;
      MdoEn_d <= 1'b0;
      MdoEn <= 1'b0;
    end
  else
    begin
      if(MdcEn_n)
        begin
          MdoEn_2d <= SerialEn | InProgress & BitCounter<32;
          MdoEn_d <= MdoEn_2d;
          MdoEn <= MdoEn_d;
        end
    end
end


// Generation of the Mdo signal.
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    begin
      Mdo_2d <= 1'b0;
      Mdo_d <= 1'b0;
      Mdo <= 1'b0;
    end
  else
    begin
      if(MdcEn_n)
        begin
          Mdo_2d <= ~SerialEn & BitCounter<32;
          Mdo_d <= ShiftedBit | Mdo_2d;
          Mdo <= Mdo_d;
        end
    end
end



endmodule
module ram32_2sum (input clock, input write, 
		   input [4:0] wr_addr, input [15:0] wr_data,
		   input [4:0] rd_addr1, input [4:0] rd_addr2,
		   output reg [15:0] sum);
   
   reg [15:0] 			ram_array [0:31];
   wire [16:0] 			sum_int;
   
   always @(posedge clock)
     if(write)
       ram_array[wr_addr] <= #1 wr_data;

   assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2];

   always @(posedge clock)
     sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);

   
endmodule // ram32_2sum
module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data);

   always @(posedge clock)
     case (addr)
       3'd0 : data <= #1 -16'd49;
       3'd1 : data <= #1 16'd165;
       3'd2 : data <= #1 -16'd412;
       3'd3 : data <= #1 16'd873;
       3'd4 : data <= #1 -16'd1681;
       3'd5 : data <= #1 16'd3135;
       3'd6 : data <= #1 -16'd6282;
       3'd7 : data <= #1 16'd20628;
     endcase // case(addr)
      
endmodule // coeff_rom
module ram16_2sum (input clock, input write, 
		   input [3:0] wr_addr, input [15:0] wr_data,
		   input [3:0] rd_addr1, input [3:0] rd_addr2,
                   output reg [15:0] sum);
   
   reg signed [15:0] 	  ram_array [0:15];
   reg signed [15:0] 	  a,b;
   wire signed [16:0] 	  sum_int;
   
   always @(posedge clock)
     if(write)
       ram_array[wr_addr] <= #1 wr_data;
      
   always @(posedge clock)
     begin
	a <= #1 ram_array[rd_addr1];
	b <= #1 ram_array[rd_addr2];
     end
   
   assign sum_int = {a[15],a} + {b[15],b};
   
   always @(posedge clock)
     sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);
     
endmodule // ram16_2sum
module coeff_ram (input clock, input [3:0] rd_addr, output reg [15:0] rd_data);

   always @(posedge clock)
     case (rd_addr)
       4'd0 : rd_data <= #1 -16'd16;
       4'd1 : rd_data <= #1 16'd74;
       4'd2 : rd_data <= #1 -16'd254;
       4'd3 : rd_data <= #1 16'd669;
       4'd4 : rd_data <= #1 -16'd1468;
       4'd5 : rd_data <= #1 16'd2950;
       4'd6 : rd_data <= #1 -16'd6158;
       4'd7 : rd_data <= #1 16'd20585;
       4'd8 : rd_data <= #1 16'd20585;
       4'd9 : rd_data <= #1 -16'd6158;
       4'd10 : rd_data <= #1 16'd2950;
       4'd11 : rd_data <= #1 -16'd1468;
       4'd12 : rd_data <= #1 16'd669;
       4'd13 : rd_data <= #1 -16'd254;
       4'd14 : rd_data <= #1 16'd74;
       4'd15 : rd_data <= #1 -16'd16;
       default : rd_data <= #1 16'd0;
     endcase // case(rd_addr)
   
endmodule // ram
module ram16_2port (input clock, input write, 
		    input [3:0] wr_addr, input [15:0] wr_data,
		    input [3:0] rd_addr1, output reg [15:0] rd_data1,
		    input [3:0] rd_addr2, output reg [15:0] rd_data2);
   
   reg [15:0] 			ram_array [0:31];
   
   always @(posedge clock)
     rd_data1 <= #1 ram_array[rd_addr1];
   
   always @(posedge clock)
     rd_data2 <= #1 ram_array[rd_addr2];
   
   always @(posedge clock)
     if(write)
       ram_array[wr_addr] <= #1 wr_data;
   
endmodule // ram16_2port
module mac (input clock, input reset, input enable, input clear,
	    input signed [15:0] x, input signed [15:0] y,
	    input [7:0] shift, output [15:0] z );

   reg signed [30:0] product;
   reg signed [39:0] z_int;
   reg signed [15:0] z_shift;

   reg enable_d1;
   always @(posedge clock)
     enable_d1 <= #1 enable;
   
   always @(posedge clock)
     if(reset | clear)
       z_int <= #1 40'd0;
     else if(enable_d1)
       z_int <= #1 z_int + {{9{product[30]}},product};

   always @(posedge clock)
     product <= #1 x*y;

   always @*   // FIXME full case? parallel case?
     case(shift)
       //8'd0 : z_shift <= z_int[39:24];
       //8'd1 : z_shift <= z_int[38:23];
       //8'd2 : z_shift <= z_int[37:22];
       //8'd3 : z_shift <= z_int[36:21];
       //8'd4 : z_shift <= z_int[35:20];
       //8'd5 : z_shift <= z_int[34:19];
       8'd6 : z_shift <= z_int[33:18];
       8'd7 : z_shift <= z_int[32:17];
       8'd8 : z_shift <= z_int[31:16];
       8'd9 : z_shift <= z_int[30:15];
       8'd10 : z_shift <= z_int[29:14];
       8'd11 : z_shift <= z_int[28:13];
       //8'd12 : z_shift <= z_int[27:12];
       //8'd13 : z_shift <= z_int[26:11];
       //8'd14 : z_shift <= z_int[25:10];
       //8'd15 : z_shift <= z_int[24:9];
       //8'd16 : z_shift <= z_int[23:8];
       //8'd17 : z_shift <= z_int[22:7];
       //8'd18 : z_shift <= z_int[21:6];
       //8'd19 : z_shift <= z_int[20:5];
       //8'd20 : z_shift <= z_int[19:4];
       //8'd21 : z_shift <= z_int[18:3];
       //8'd22 : z_shift <= z_int[17:2];
       //8'd23 : z_shift <= z_int[16:1];
       //8'd24 : z_shift <= z_int[15:0];
       default : z_shift <= z_int[15:0];
     endcase // case(shift)
   
   // FIXME do we need to saturate?
   //assign z = z_shift;
   assign z = z_int[15:0];
   
endmodule // mac