dakies/OSS_Verilog huggingface dataset:
module bsg_counter_up_down_variable_max_val_p128_init_val_p128_max_step_p128
(
  clk_i,
  reset_i,
  up_i,
  down_i,
  count_o
);

  input [7:0] up_i;
  input [7:0] down_i;
  output [7:0] count_o;
  input clk_i;
  input reset_i;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
  N22,N23,N24,N25,N26;
  reg [7:0] count_o;

  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[7] <= N26;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[6] <= N25;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[5] <= N24;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[4] <= N23;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[3] <= N22;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[2] <= N21;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[1] <= N20;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[0] <= N19;
    end 
  end

  assign { N10, N9, N8, N7, N6, N5, N4, N3 } = count_o - down_i;
  assign { N18, N17, N16, N15, N14, N13, N12, N11 } = { N10, N9, N8, N7, N6, N5, N4, N3 } + up_i;
  assign { N26, N25, N24, N23, N22, N21, N20, N19 } = (N0)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 
                                                      (N1)? { N18, N17, N16, N15, N14, N13, N12, N11 } : 1'b0;
  assign N0 = reset_i;
  assign N1 = N2;
  assign N2 = ~reset_i;

endmodule
module Arbiter_3
(
  io_in_1_ready,
  io_in_1_valid,
  io_in_1_bits_way_en,
  io_in_1_bits_addr,
  io_in_1_bits_wmask,
  io_in_1_bits_data,
  io_in_0_ready,
  io_in_0_valid,
  io_in_0_bits_way_en,
  io_in_0_bits_addr,
  io_in_0_bits_wmask,
  io_in_0_bits_data,
  io_out_ready,
  io_out_valid,
  io_out_bits_way_en,
  io_out_bits_addr,
  io_out_bits_wmask,
  io_out_bits_data,
  io_chosen
);

  input [3:0] io_in_1_bits_way_en;
  input [11:0] io_in_1_bits_addr;
  input [1:0] io_in_1_bits_wmask;
  input [127:0] io_in_1_bits_data;
  input [3:0] io_in_0_bits_way_en;
  input [11:0] io_in_0_bits_addr;
  input [1:0] io_in_0_bits_wmask;
  input [127:0] io_in_0_bits_data;
  output [3:0] io_out_bits_way_en;
  output [11:0] io_out_bits_addr;
  output [1:0] io_out_bits_wmask;
  output [127:0] io_out_bits_data;
  input io_in_1_valid;
  input io_in_0_valid;
  input io_out_ready;
  output io_in_1_ready;
  output io_in_0_ready;
  output io_out_valid;
  output io_chosen;
  wire [3:0] io_out_bits_way_en;
  wire [11:0] io_out_bits_addr;
  wire [1:0] io_out_bits_wmask;
  wire [127:0] io_out_bits_data;
  wire io_in_1_ready,io_in_0_ready,io_out_valid,io_chosen,N0,N1,io_out_ready,T7;
  assign io_in_0_ready = io_out_ready;
  assign io_chosen = ~io_in_0_valid;
  assign io_out_bits_data = (N0)? io_in_1_bits_data : 
                            (N1)? io_in_0_bits_data : 1'b0;
  assign N0 = io_chosen;
  assign N1 = io_in_0_valid;
  assign io_out_bits_wmask = (N0)? io_in_1_bits_wmask : 
                             (N1)? io_in_0_bits_wmask : 1'b0;
  assign io_out_bits_addr = (N0)? io_in_1_bits_addr : 
                            (N1)? io_in_0_bits_addr : 1'b0;
  assign io_out_bits_way_en = (N0)? io_in_1_bits_way_en : 
                              (N1)? io_in_0_bits_way_en : 1'b0;
  assign io_out_valid = (N0)? io_in_1_valid : 
                        (N1)? io_in_0_valid : 1'b0;
  assign io_in_1_ready = T7 & io_out_ready;
  assign T7 = ~io_in_0_valid;

endmodule
module Arbiter_5
(
  io_in_1_ready,
  io_in_1_valid,
  io_in_1_bits_addr,
  io_in_1_bits_tag,
  io_in_1_bits_cmd,
  io_in_1_bits_typ,
  io_in_1_bits_kill,
  io_in_1_bits_phys,
  io_in_1_bits_data,
  io_in_0_ready,
  io_in_0_valid,
  io_in_0_bits_addr,
  io_in_0_bits_tag,
  io_in_0_bits_cmd,
  io_in_0_bits_typ,
  io_in_0_bits_kill,
  io_in_0_bits_phys,
  io_in_0_bits_data,
  io_out_ready,
  io_out_valid,
  io_out_bits_addr,
  io_out_bits_tag,
  io_out_bits_cmd,
  io_out_bits_typ,
  io_out_bits_kill,
  io_out_bits_phys,
  io_out_bits_data,
  io_chosen
);

  input [39:0] io_in_1_bits_addr;
  input [9:0] io_in_1_bits_tag;
  input [4:0] io_in_1_bits_cmd;
  input [2:0] io_in_1_bits_typ;
  input [63:0] io_in_1_bits_data;
  input [39:0] io_in_0_bits_addr;
  input [9:0] io_in_0_bits_tag;
  input [4:0] io_in_0_bits_cmd;
  input [2:0] io_in_0_bits_typ;
  input [63:0] io_in_0_bits_data;
  output [39:0] io_out_bits_addr;
  output [9:0] io_out_bits_tag;
  output [4:0] io_out_bits_cmd;
  output [2:0] io_out_bits_typ;
  output [63:0] io_out_bits_data;
  input io_in_1_valid;
  input io_in_1_bits_kill;
  input io_in_1_bits_phys;
  input io_in_0_valid;
  input io_in_0_bits_kill;
  input io_in_0_bits_phys;
  input io_out_ready;
  output io_in_1_ready;
  output io_in_0_ready;
  output io_out_valid;
  output io_out_bits_kill;
  output io_out_bits_phys;
  output io_chosen;
  wire [39:0] io_out_bits_addr;
  wire [9:0] io_out_bits_tag;
  wire [4:0] io_out_bits_cmd;
  wire [2:0] io_out_bits_typ;
  wire [63:0] io_out_bits_data;
  wire io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_kill,io_out_bits_phys,
  io_chosen,N0,N1,io_out_ready,T10;
  assign io_in_0_ready = io_out_ready;
  assign io_chosen = ~io_in_0_valid;
  assign io_out_bits_data = (N0)? io_in_1_bits_data : 
                            (N1)? io_in_0_bits_data : 1'b0;
  assign N0 = io_chosen;
  assign N1 = io_in_0_valid;
  assign io_out_bits_phys = (N0)? io_in_1_bits_phys : 
                            (N1)? io_in_0_bits_phys : 1'b0;
  assign io_out_bits_kill = (N0)? io_in_1_bits_kill : 
                            (N1)? io_in_0_bits_kill : 1'b0;
  assign io_out_bits_typ = (N0)? io_in_1_bits_typ : 
                           (N1)? io_in_0_bits_typ : 1'b0;
  assign io_out_bits_cmd = (N0)? io_in_1_bits_cmd : 
                           (N1)? io_in_0_bits_cmd : 1'b0;
  assign io_out_bits_tag = (N0)? io_in_1_bits_tag : 
                           (N1)? io_in_0_bits_tag : 1'b0;
  assign io_out_bits_addr = (N0)? io_in_1_bits_addr : 
                            (N1)? io_in_0_bits_addr : 1'b0;
  assign io_out_valid = (N0)? io_in_1_valid : 
                        (N1)? io_in_0_valid : 1'b0;
  assign io_in_1_ready = T10 & io_out_ready;
  assign T10 = ~io_in_0_valid;

endmodule
module RRArbiter_3
(
  clk,
  reset,
  io_in_1_ready,
  io_in_1_valid,
  io_in_1_bits_addr,
  io_in_1_bits_prv,
  io_in_1_bits_store,
  io_in_1_bits_fetch,
  io_in_0_ready,
  io_in_0_valid,
  io_in_0_bits_addr,
  io_in_0_bits_prv,
  io_in_0_bits_store,
  io_in_0_bits_fetch,
  io_out_ready,
  io_out_valid,
  io_out_bits_addr,
  io_out_bits_prv,
  io_out_bits_store,
  io_out_bits_fetch,
  io_chosen
);

  input [26:0] io_in_1_bits_addr;
  input [1:0] io_in_1_bits_prv;
  input [26:0] io_in_0_bits_addr;
  input [1:0] io_in_0_bits_prv;
  output [26:0] io_out_bits_addr;
  output [1:0] io_out_bits_prv;
  input clk;
  input reset;
  input io_in_1_valid;
  input io_in_1_bits_store;
  input io_in_1_bits_fetch;
  input io_in_0_valid;
  input io_in_0_bits_store;
  input io_in_0_bits_fetch;
  input io_out_ready;
  output io_in_1_ready;
  output io_in_0_ready;
  output io_out_valid;
  output io_out_bits_store;
  output io_out_bits_fetch;
  output io_chosen;
  wire [26:0] io_out_bits_addr;
  wire [1:0] io_out_bits_prv;
  wire io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_store,io_out_bits_fetch,
  io_chosen,N0,N1,N2,N3,N4,N5,N6,T1,N7,T2,T4,N8,T12,T19,T13,T14,T17,T15,T16,T18,T21,
  T25,T22,T23,T24,T27,T26,N9,N10,N11,N12,N13,N14,N15;
  reg last_grant;
  assign T18 = N0 & 1'b0;
  assign N0 = ~last_grant;
  assign T19 = N1 & 1'b0;
  assign N1 = ~last_grant;

  always @(posedge clk) begin
    if(N11) begin
      last_grant <= N12;
    end 
  end

  assign N15 = ~io_in_0_valid;
  assign io_chosen = (N2)? 1'b1 : 
                     (N3)? N15 : 1'b0;
  assign N2 = T1;
  assign N3 = N7;
  assign io_out_bits_fetch = (N4)? io_in_1_bits_fetch : 
                             (N5)? io_in_0_bits_fetch : 1'b0;
  assign N4 = io_chosen;
  assign N5 = N8;
  assign io_out_bits_store = (N4)? io_in_1_bits_store : 
                             (N5)? io_in_0_bits_store : 1'b0;
  assign io_out_bits_prv = (N4)? io_in_1_bits_prv : 
                           (N5)? io_in_0_bits_prv : 1'b0;
  assign io_out_bits_addr = (N4)? io_in_1_bits_addr : 
                            (N5)? io_in_0_bits_addr : 1'b0;
  assign io_out_valid = (N4)? io_in_1_valid : 
                        (N5)? io_in_0_valid : 1'b0;
  assign N11 = (N6)? 1'b1 : 
               (N14)? 1'b1 : 
               (N10)? 1'b0 : 1'b0;
  assign N6 = reset;
  assign N12 = (N6)? 1'b0 : 
               (N14)? io_chosen : 1'b0;
  assign N7 = ~T1;
  assign T1 = io_in_1_valid & T2;
  assign T2 = ~last_grant;
  assign T4 = io_out_ready & io_out_valid;
  assign N8 = ~io_chosen;
  assign io_in_0_ready = T12 & io_out_ready;
  assign T12 = T19 | T13;
  assign T13 = ~T14;
  assign T14 = T17 | T15;
  assign T15 = io_in_1_valid & T16;
  assign T16 = ~last_grant;
  assign T17 = io_in_0_valid & T18;
  assign io_in_1_ready = T21 & io_out_ready;
  assign T21 = T25 | T22;
  assign T22 = ~T23;
  assign T23 = T24 | io_in_0_valid;
  assign T24 = T17 | T15;
  assign T25 = T27 & T26;
  assign T26 = ~last_grant;
  assign T27 = ~T17;
  assign N9 = T4 | reset;
  assign N10 = ~N9;
  assign N13 = ~reset;
  assign N14 = T4 & N13;

endmodule
module bsg_counter_clear_up_max_val_p128_init_val_p0
(
  clk_i,
  reset_i,
  clear_i,
  up_i,
  count_o
);

  output [7:0] count_o;
  input clk_i;
  input reset_i;
  input clear_i;
  input up_i;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
  N22,N23,N24,N25,N26,N27,N28,N29;
  reg [7:0] count_o;

  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[7] <= N21;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[6] <= N20;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[5] <= N19;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[4] <= N18;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[3] <= N17;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[2] <= N16;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[1] <= N15;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[0] <= N14;
    end 
  end

  assign { N13, N12, N11, N10, N9, N8, N7, N6 } = { N29, N28, N27, N26, N25, N24, N23, N22 } + up_i;
  assign { N21, N20, N19, N18, N17, N16, N15, N14 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 
                                                      (N1)? { N13, N12, N11, N10, N9, N8, N7, N6 } : 1'b0;
  assign N0 = reset_i;
  assign N1 = N2;
  assign { N29, N28, N27, N26, N25, N24, N23, N22 } = count_o * N4;
  assign N2 = ~reset_i;
  assign N3 = N2;
  assign N4 = ~clear_i;
  assign N5 = N3 & N4;

endmodule
module RRArbiter_2
(
  clk,
  reset,
  io_in_1_ready,
  io_in_1_valid,
  io_in_1_bits_rw,
  io_in_1_bits_addr,
  io_in_1_bits_data,
  io_in_0_ready,
  io_in_0_valid,
  io_in_0_bits_rw,
  io_in_0_bits_addr,
  io_in_0_bits_data,
  io_out_ready,
  io_out_valid,
  io_out_bits_rw,
  io_out_bits_addr,
  io_out_bits_data,
  io_chosen
);

  input [5:0] io_in_1_bits_addr;
  input [63:0] io_in_1_bits_data;
  input [5:0] io_in_0_bits_addr;
  input [63:0] io_in_0_bits_data;
  output [5:0] io_out_bits_addr;
  output [63:0] io_out_bits_data;
  input clk;
  input reset;
  input io_in_1_valid;
  input io_in_1_bits_rw;
  input io_in_0_valid;
  input io_in_0_bits_rw;
  input io_out_ready;
  output io_in_1_ready;
  output io_in_0_ready;
  output io_out_valid;
  output io_out_bits_rw;
  output io_chosen;
  wire [5:0] io_out_bits_addr;
  wire [63:0] io_out_bits_data;
  wire io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_rw,io_chosen,N0,N1,N2,N3,
  N4,N5,N6,T1,N7,T2,T4,N8,T11,T18,T12,T13,T16,T14,T15,T17,T20,T24,T21,T22,T23,T26,
  T25,N9,N10,N11,N12,N13,N14,N15;
  reg last_grant;
  assign T17 = N0 & 1'b0;
  assign N0 = ~last_grant;
  assign T18 = N1 & 1'b0;
  assign N1 = ~last_grant;

  always @(posedge clk) begin
    if(N11) begin
      last_grant <= N12;
    end 
  end

  assign N15 = ~io_in_0_valid;
  assign io_chosen = (N2)? 1'b1 : 
                     (N3)? N15 : 1'b0;
  assign N2 = T1;
  assign N3 = N7;
  assign io_out_bits_data = (N4)? io_in_1_bits_data : 
                            (N5)? io_in_0_bits_data : 1'b0;
  assign N4 = io_chosen;
  assign N5 = N8;
  assign io_out_bits_addr = (N4)? io_in_1_bits_addr : 
                            (N5)? io_in_0_bits_addr : 1'b0;
  assign io_out_bits_rw = (N4)? io_in_1_bits_rw : 
                          (N5)? io_in_0_bits_rw : 1'b0;
  assign io_out_valid = (N4)? io_in_1_valid : 
                        (N5)? io_in_0_valid : 1'b0;
  assign N11 = (N6)? 1'b1 : 
               (N14)? 1'b1 : 
               (N10)? 1'b0 : 1'b0;
  assign N6 = reset;
  assign N12 = (N6)? 1'b0 : 
               (N14)? io_chosen : 1'b0;
  assign N7 = ~T1;
  assign T1 = io_in_1_valid & T2;
  assign T2 = ~last_grant;
  assign T4 = io_out_ready & io_out_valid;
  assign N8 = ~io_chosen;
  assign io_in_0_ready = T11 & io_out_ready;
  assign T11 = T18 | T12;
  assign T12 = ~T13;
  assign T13 = T16 | T14;
  assign T14 = io_in_1_valid & T15;
  assign T15 = ~last_grant;
  assign T16 = io_in_0_valid & T17;
  assign io_in_1_ready = T20 & io_out_ready;
  assign T20 = T24 | T21;
  assign T21 = ~T22;
  assign T22 = T23 | io_in_0_valid;
  assign T23 = T16 | T14;
  assign T24 = T26 & T25;
  assign T25 = ~last_grant;
  assign T26 = ~T16;
  assign N9 = T4 | reset;
  assign N10 = ~N9;
  assign N13 = ~reset;
  assign N14 = T4 & N13;

endmodule
module bsg_mux_one_hot_width_p9_els_p3
(
  data_i,
  sel_one_hot_i,
  data_o
);

  input [26:0] data_i;
  input [2:0] sel_one_hot_i;
  output [8:0] data_o;
  wire [8:0] data_o;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8;
  wire [26:0] data_masked;
  assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
  assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
  assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
  assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
  assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
  assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
  assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
  assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
  assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
  assign data_masked[17] = data_i[17] & sel_one_hot_i[1];
  assign data_masked[16] = data_i[16] & sel_one_hot_i[1];
  assign data_masked[15] = data_i[15] & sel_one_hot_i[1];
  assign data_masked[14] = data_i[14] & sel_one_hot_i[1];
  assign data_masked[13] = data_i[13] & sel_one_hot_i[1];
  assign data_masked[12] = data_i[12] & sel_one_hot_i[1];
  assign data_masked[11] = data_i[11] & sel_one_hot_i[1];
  assign data_masked[10] = data_i[10] & sel_one_hot_i[1];
  assign data_masked[9] = data_i[9] & sel_one_hot_i[1];
  assign data_masked[26] = data_i[26] & sel_one_hot_i[2];
  assign data_masked[25] = data_i[25] & sel_one_hot_i[2];
  assign data_masked[24] = data_i[24] & sel_one_hot_i[2];
  assign data_masked[23] = data_i[23] & sel_one_hot_i[2];
  assign data_masked[22] = data_i[22] & sel_one_hot_i[2];
  assign data_masked[21] = data_i[21] & sel_one_hot_i[2];
  assign data_masked[20] = data_i[20] & sel_one_hot_i[2];
  assign data_masked[19] = data_i[19] & sel_one_hot_i[2];
  assign data_masked[18] = data_i[18] & sel_one_hot_i[2];
  assign data_o[0] = N0 | data_masked[0];
  assign N0 = data_masked[18] | data_masked[9];
  assign data_o[1] = N1 | data_masked[1];
  assign N1 = data_masked[19] | data_masked[10];
  assign data_o[2] = N2 | data_masked[2];
  assign N2 = data_masked[20] | data_masked[11];
  assign data_o[3] = N3 | data_masked[3];
  assign N3 = data_masked[21] | data_masked[12];
  assign data_o[4] = N4 | data_masked[4];
  assign N4 = data_masked[22] | data_masked[13];
  assign data_o[5] = N5 | data_masked[5];
  assign N5 = data_masked[23] | data_masked[14];
  assign data_o[6] = N6 | data_masked[6];
  assign N6 = data_masked[24] | data_masked[15];
  assign data_o[7] = N7 | data_masked[7];
  assign N7 = data_masked[25] | data_masked[16];
  assign data_o[8] = N8 | data_masked[8];
  assign N8 = data_masked[26] | data_masked[17];

endmodule
module cl_state_machine
(
  instruction_i,
  state_i,
  net_pc_write_cmd_idle_i,
  stall_i,
  state_o
);

  input [31:0] instruction_i;
  input [1:0] state_i;
  output [1:0] state_o;
  input net_pc_write_cmd_idle_i;
  input stall_i;
  wire [1:0] state_o;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11;
  assign N6 = N4 & N5;
  assign N7 = state_i[1] | N5;
  assign N9 = state_i[1] & state_i[0];
  assign N10 = N4 | state_i[0];
  assign state_o = (N0)? { 1'b0, net_pc_write_cmd_idle_i } : 
                   (N1)? { 1'b0, 1'b1 } : 
                   (N2)? { 1'b1, 1'b1 } : 
                   (N3)? { 1'b1, 1'b1 } : 1'b0;
  assign N0 = N6;
  assign N1 = N8;
  assign N2 = N9;
  assign N3 = N11;
  assign N4 = ~state_i[1];
  assign N5 = ~state_i[0];
  assign N8 = ~N7;
  assign N11 = ~N10;

endmodule
module bsg_mux_one_hot_width_p1_els_p1
(
  data_i,
  sel_one_hot_i,
  data_o
);

  input [0:0] data_i;
  input [0:0] sel_one_hot_i;
  output [0:0] data_o;
  wire [0:0] data_o;
  assign data_o[0] = data_i[0] & sel_one_hot_i[0];

endmodule
module bsg_counter_up_down_max_val_p200_init_val_p200
(
  clk_i,
  reset_i,
  up_i,
  down_i,
  count_o
);

  output [7:0] count_o;
  input clk_i;
  input reset_i;
  input up_i;
  input down_i;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
  N22,N23,N24,N25,N26;
  reg [7:0] count_o;

  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[7] <= N26;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[6] <= N25;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[5] <= N24;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[4] <= N23;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[3] <= N22;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[2] <= N21;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[1] <= N20;
    end 
  end


  always @(posedge clk_i) begin
    if(1'b1) begin
      count_o[0] <= N19;
    end 
  end

  assign { N10, N9, N8, N7, N6, N5, N4, N3 } = count_o - down_i;
  assign { N18, N17, N16, N15, N14, N13, N12, N11 } = { N10, N9, N8, N7, N6, N5, N4, N3 } + up_i;
  assign { N26, N25, N24, N23, N22, N21, N20, N19 } = (N0)? { 1'b1, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } : 
                                                      (N1)? { N18, N17, N16, N15, N14, N13, N12, N11 } : 1'b0;
  assign N0 = reset_i;
  assign N1 = N2;
  assign N2 = ~reset_i;

endmodule
module bsg_transpose_width_p1_els_p2
(
  i,
  o
);

  input [1:0] i;
  output [1:0] o;
  wire [1:0] o;
  assign o[1] = i[1];
  assign o[0] = i[0];

endmodule
module bsg_xnor_width_p33
(
  a_i,
  b_i,
  o
);

  input [32:0] a_i;
  input [32:0] b_i;
  output [32:0] o;
  wire [32:0] o;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
  N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32;
  assign o[32] = ~N0;
  assign N0 = a_i[32] ^ b_i[32];
  assign o[31] = ~N1;
  assign N1 = a_i[31] ^ b_i[31];
  assign o[30] = ~N2;
  assign N2 = a_i[30] ^ b_i[30];
  assign o[29] = ~N3;
  assign N3 = a_i[29] ^ b_i[29];
  assign o[28] = ~N4;
  assign N4 = a_i[28] ^ b_i[28];
  assign o[27] = ~N5;
  assign N5 = a_i[27] ^ b_i[27];
  assign o[26] = ~N6;
  assign N6 = a_i[26] ^ b_i[26];
  assign o[25] = ~N7;
  assign N7 = a_i[25] ^ b_i[25];
  assign o[24] = ~N8;
  assign N8 = a_i[24] ^ b_i[24];
  assign o[23] = ~N9;
  assign N9 = a_i[23] ^ b_i[23];
  assign o[22] = ~N10;
  assign N10 = a_i[22] ^ b_i[22];
  assign o[21] = ~N11;
  assign N11 = a_i[21] ^ b_i[21];
  assign o[20] = ~N12;
  assign N12 = a_i[20] ^ b_i[20];
  assign o[19] = ~N13;
  assign N13 = a_i[19] ^ b_i[19];
  assign o[18] = ~N14;
  assign N14 = a_i[18] ^ b_i[18];
  assign o[17] = ~N15;
  assign N15 = a_i[17] ^ b_i[17];
  assign o[16] = ~N16;
  assign N16 = a_i[16] ^ b_i[16];
  assign o[15] = ~N17;
  assign N17 = a_i[15] ^ b_i[15];
  assign o[14] = ~N18;
  assign N18 = a_i[14] ^ b_i[14];
  assign o[13] = ~N19;
  assign N19 = a_i[13] ^ b_i[13];
  assign o[12] = ~N20;
  assign N20 = a_i[12] ^ b_i[12];
  assign o[11] = ~N21;
  assign N21 = a_i[11] ^ b_i[11];
  assign o[10] = ~N22;
  assign N22 = a_i[10] ^ b_i[10];
  assign o[9] = ~N23;
  assign N23 = a_i[9] ^ b_i[9];
  assign o[8] = ~N24;
  assign N24 = a_i[8] ^ b_i[8];
  assign o[7] = ~N25;
  assign N25 = a_i[7] ^ b_i[7];
  assign o[6] = ~N26;
  assign N26 = a_i[6] ^ b_i[6];
  assign o[5] = ~N27;
  assign N27 = a_i[5] ^ b_i[5];
  assign o[4] = ~N28;
  assign N28 = a_i[4] ^ b_i[4];
  assign o[3] = ~N29;
  assign N29 = a_i[3] ^ b_i[3];
  assign o[2] = ~N30;
  assign N30 = a_i[2] ^ b_i[2];
  assign o[1] = ~N31;
  assign N31 = a_i[1] ^ b_i[1];
  assign o[0] = ~N32;
  assign N32 = a_i[0] ^ b_i[0];

endmodule
module bsg_scan_2_1_1
(
  i,
  o
);

  input [1:0] i;
  output [1:0] o;
  wire [1:0] o;
  assign o[0] = i[0] | 1'b0;
  assign o[1] = i[1] | i[0];

endmodule
module bsg_mux_one_hot_width_p32_els_p1
(
  data_i,
  sel_one_hot_i,
  data_o
);

  input [31:0] data_i;
  input [0:0] sel_one_hot_i;
  output [31:0] data_o;
  wire [31:0] data_o;
  assign data_o[31] = data_i[31] & sel_one_hot_i[0];
  assign data_o[30] = data_i[30] & sel_one_hot_i[0];
  assign data_o[29] = data_i[29] & sel_one_hot_i[0];
  assign data_o[28] = data_i[28] & sel_one_hot_i[0];
  assign data_o[27] = data_i[27] & sel_one_hot_i[0];
  assign data_o[26] = data_i[26] & sel_one_hot_i[0];
  assign data_o[25] = data_i[25] & sel_one_hot_i[0];
  assign data_o[24] = data_i[24] & sel_one_hot_i[0];
  assign data_o[23] = data_i[23] & sel_one_hot_i[0];
  assign data_o[22] = data_i[22] & sel_one_hot_i[0];
  assign data_o[21] = data_i[21] & sel_one_hot_i[0];
  assign data_o[20] = data_i[20] & sel_one_hot_i[0];
  assign data_o[19] = data_i[19] & sel_one_hot_i[0];
  assign data_o[18] = data_i[18] & sel_one_hot_i[0];
  assign data_o[17] = data_i[17] & sel_one_hot_i[0];
  assign data_o[16] = data_i[16] & sel_one_hot_i[0];
  assign data_o[15] = data_i[15] & sel_one_hot_i[0];
  assign data_o[14] = data_i[14] & sel_one_hot_i[0];
  assign data_o[13] = data_i[13] & sel_one_hot_i[0];
  assign data_o[12] = data_i[12] & sel_one_hot_i[0];
  assign data_o[11] = data_i[11] & sel_one_hot_i[0];
  assign data_o[10] = data_i[10] & sel_one_hot_i[0];
  assign data_o[9] = data_i[9] & sel_one_hot_i[0];
  assign data_o[8] = data_i[8] & sel_one_hot_i[0];
  assign data_o[7] = data_i[7] & sel_one_hot_i[0];
  assign data_o[6] = data_i[6] & sel_one_hot_i[0];
  assign data_o[5] = data_i[5] & sel_one_hot_i[0];
  assign data_o[4] = data_i[4] & sel_one_hot_i[0];
  assign data_o[3] = data_i[3] & sel_one_hot_i[0];
  assign data_o[2] = data_i[2] & sel_one_hot_i[0];
  assign data_o[1] = data_i[1] & sel_one_hot_i[0];
  assign data_o[0] = data_i[0] & sel_one_hot_i[0];

endmodule
module bsg_nor2_width_p33
(
  a_i,
  b_i,
  o
);

  input [32:0] a_i;
  input [32:0] b_i;
  output [32:0] o;
  wire [32:0] o;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
  N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32;
  assign o[32] = ~N0;
  assign N0 = a_i[32] | b_i[32];
  assign o[31] = ~N1;
  assign N1 = a_i[31] | b_i[31];
  assign o[30] = ~N2;
  assign N2 = a_i[30] | b_i[30];
  assign o[29] = ~N3;
  assign N3 = a_i[29] | b_i[29];
  assign o[28] = ~N4;
  assign N4 = a_i[28] | b_i[28];
  assign o[27] = ~N5;
  assign N5 = a_i[27] | b_i[27];
  assign o[26] = ~N6;
  assign N6 = a_i[26] | b_i[26];
  assign o[25] = ~N7;
  assign N7 = a_i[25] | b_i[25];
  assign o[24] = ~N8;
  assign N8 = a_i[24] | b_i[24];
  assign o[23] = ~N9;
  assign N9 = a_i[23] | b_i[23];
  assign o[22] = ~N10;
  assign N10 = a_i[22] | b_i[22];
  assign o[21] = ~N11;
  assign N11 = a_i[21] | b_i[21];
  assign o[20] = ~N12;
  assign N12 = a_i[20] | b_i[20];
  assign o[19] = ~N13;
  assign N13 = a_i[19] | b_i[19];
  assign o[18] = ~N14;
  assign N14 = a_i[18] | b_i[18];
  assign o[17] = ~N15;
  assign N15 = a_i[17] | b_i[17];
  assign o[16] = ~N16;
  assign N16 = a_i[16] | b_i[16];
  assign o[15] = ~N17;
  assign N17 = a_i[15] | b_i[15];
  assign o[14] = ~N18;
  assign N18 = a_i[14] | b_i[14];
  assign o[13] = ~N19;
  assign N19 = a_i[13] | b_i[13];
  assign o[12] = ~N20;
  assign N20 = a_i[12] | b_i[12];
  assign o[11] = ~N21;
  assign N21 = a_i[11] | b_i[11];
  assign o[10] = ~N22;
  assign N22 = a_i[10] | b_i[10];
  assign o[9] = ~N23;
  assign N23 = a_i[9] | b_i[9];
  assign o[8] = ~N24;
  assign N24 = a_i[8] | b_i[8];
  assign o[7] = ~N25;
  assign N25 = a_i[7] | b_i[7];
  assign o[6] = ~N26;
  assign N26 = a_i[6] | b_i[6];
  assign o[5] = ~N27;
  assign N27 = a_i[5] | b_i[5];
  assign o[4] = ~N28;
  assign N28 = a_i[4] | b_i[4];
  assign o[3] = ~N29;
  assign N29 = a_i[3] | b_i[3];
  assign o[2] = ~N30;
  assign N30 = a_i[2] | b_i[2];
  assign o[1] = ~N31;
  assign N31 = a_i[1] | b_i[1];
  assign o[0] = ~N32;
  assign N32 = a_i[0] | b_i[0];

endmodule
module bsg_buf_ctrl_width_p33
(
  i,
  o
);

  output [32:0] o;
  input i;
  wire [32:0] o;
  wire i;
  assign o[0] = i;
  assign o[1] = i;
  assign o[2] = i;
  assign o[3] = i;
  assign o[4] = i;
  assign o[5] = i;
  assign o[6] = i;
  assign o[7] = i;
  assign o[8] = i;
  assign o[9] = i;
  assign o[10] = i;
  assign o[11] = i;
  assign o[12] = i;
  assign o[13] = i;
  assign o[14] = i;
  assign o[15] = i;
  assign o[16] = i;
  assign o[17] = i;
  assign o[18] = i;
  assign o[19] = i;
  assign o[20] = i;
  assign o[21] = i;
  assign o[22] = i;
  assign o[23] = i;
  assign o[24] = i;
  assign o[25] = i;
  assign o[26] = i;
  assign o[27] = i;
  assign o[28] = i;
  assign o[29] = i;
  assign o[30] = i;
  assign o[31] = i;
  assign o[32] = i;

endmodule
module bsg_mux_one_hot_width_p4_els_p2
(
  data_i,
  sel_one_hot_i,
  data_o
);

  input [7:0] data_i;
  input [1:0] sel_one_hot_i;
  output [3:0] data_o;
  wire [3:0] data_o;
  wire [7:0] data_masked;
  assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
  assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
  assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
  assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
  assign data_masked[7] = data_i[7] & sel_one_hot_i[1];
  assign data_masked[6] = data_i[6] & sel_one_hot_i[1];
  assign data_masked[5] = data_i[5] & sel_one_hot_i[1];
  assign data_masked[4] = data_i[4] & sel_one_hot_i[1];
  assign data_o[0] = data_masked[4] | data_masked[0];
  assign data_o[1] = data_masked[5] | data_masked[1];
  assign data_o[2] = data_masked[6] | data_masked[2];
  assign data_o[3] = data_masked[7] | data_masked[3];

endmodule
module bsg_transpose_width_p2_els_p1
(
  i,
  o
);

  input [1:0] i;
  output [1:0] o;
  wire [1:0] o;
  assign o[1] = i[1];
  assign o[0] = i[0];

endmodule
module bsg_mesh_router_dor_decoder_4_5_5_1
(
  clk_i,
  v_i,
  x_dirs_i,
  y_dirs_i,
  my_x_i,
  my_y_i,
  req_o
);

  input [4:0] v_i;
  input [19:0] x_dirs_i;
  input [24:0] y_dirs_i;
  input [3:0] my_x_i;
  input [4:0] my_y_i;
  output [24:0] req_o;
  input clk_i;
  wire [24:0] req_o;
  wire x_eq_4,x_gt_0,NS_req_4__weird_route,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,
  N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32;
  wire [2:0] x_eq,y_gt,y_lt;
  wire [4:0] y_eq;
  wire [4:3] x_gt;
  wire [0:0] x_lt;
  assign req_o[24] = 1'b0;
  assign req_o[18] = 1'b0;
  assign req_o[12] = 1'b0;
  assign req_o[6] = 1'b0;
  assign x_eq[0] = x_dirs_i[3:0] == my_x_i;
  assign y_eq[0] = y_dirs_i[4:0] == my_y_i;
  assign x_gt_0 = x_dirs_i[3:0] > my_x_i;
  assign y_gt[0] = y_dirs_i[4:0] > my_y_i;
  assign x_eq[1] = x_dirs_i[7:4] == my_x_i;
  assign y_eq[1] = y_dirs_i[9:5] == my_y_i;
  assign y_gt[1] = y_dirs_i[9:5] > my_y_i;
  assign x_eq[2] = x_dirs_i[11:8] == my_x_i;
  assign y_eq[2] = y_dirs_i[14:10] == my_y_i;
  assign y_gt[2] = y_dirs_i[14:10] > my_y_i;
  assign y_eq[3] = y_dirs_i[19:15] == my_y_i;
  assign x_gt[3] = x_dirs_i[15:12] > my_x_i;
  assign x_eq_4 = x_dirs_i[19:16] == my_x_i;
  assign y_eq[4] = y_dirs_i[24:20] == my_y_i;
  assign x_gt[4] = x_dirs_i[19:16] > my_x_i;
  assign x_lt[0] = N0 & N1;
  assign N0 = ~x_gt_0;
  assign N1 = ~x_eq[0];
  assign y_lt[0] = N2 & N3;
  assign N2 = ~y_gt[0];
  assign N3 = ~y_eq[0];
  assign y_lt[1] = N4 & N5;
  assign N4 = ~y_gt[1];
  assign N5 = ~y_eq[1];
  assign y_lt[2] = N6 & N7;
  assign N6 = ~y_gt[2];
  assign N7 = ~y_eq[2];
  assign req_o[7] = v_i[1] & N8;
  assign N8 = ~x_eq[1];
  assign req_o[5] = N9 & y_eq[1];
  assign N9 = v_i[1] & x_eq[1];
  assign req_o[9] = N10 & y_gt[1];
  assign N10 = v_i[1] & x_eq[1];
  assign req_o[8] = N11 & y_lt[1];
  assign N11 = v_i[1] & x_eq[1];
  assign req_o[11] = v_i[2] & N12;
  assign N12 = ~x_eq[2];
  assign req_o[10] = N13 & y_eq[2];
  assign N13 = v_i[2] & x_eq[2];
  assign req_o[14] = N14 & y_gt[2];
  assign N14 = v_i[2] & x_eq[2];
  assign req_o[13] = N15 & y_lt[2];
  assign N15 = v_i[2] & x_eq[2];
  assign req_o[19] = N17 & N18;
  assign N17 = v_i[3] & N16;
  assign N16 = ~y_eq[3];
  assign N18 = ~1'b0;
  assign req_o[15] = N19 & N18;
  assign N19 = v_i[3] & y_eq[3];
  assign req_o[16] = N20 & N21;
  assign N20 = v_i[3] & 1'b0;
  assign N21 = ~x_gt[3];
  assign req_o[17] = N22 & x_gt[3];
  assign N22 = v_i[3] & 1'b0;
  assign NS_req_4__weird_route = ~x_eq_4;
  assign req_o[23] = N24 & N25;
  assign N24 = v_i[4] & N23;
  assign N23 = ~y_eq[4];
  assign N25 = ~NS_req_4__weird_route;
  assign req_o[20] = N26 & N25;
  assign N26 = v_i[4] & y_eq[4];
  assign req_o[21] = N27 & N28;
  assign N27 = v_i[4] & NS_req_4__weird_route;
  assign N28 = ~x_gt[4];
  assign req_o[22] = N29 & x_gt[4];
  assign N29 = v_i[4] & NS_req_4__weird_route;
  assign req_o[2] = v_i[0] & x_gt_0;
  assign req_o[1] = v_i[0] & x_lt[0];
  assign req_o[4] = N30 & y_gt[0];
  assign N30 = v_i[0] & x_eq[0];
  assign req_o[3] = N31 & y_lt[0];
  assign N31 = v_i[0] & x_eq[0];
  assign req_o[0] = N32 & y_eq[0];
  assign N32 = v_i[0] & x_eq[0];

endmodule
module bsg_mux_one_hot_width_p10_els_p2
(
  data_i,
  sel_one_hot_i,
  data_o
);

  input [19:0] data_i;
  input [1:0] sel_one_hot_i;
  output [9:0] data_o;
  wire [9:0] data_o;
  wire [19:0] data_masked;
  assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
  assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
  assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
  assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
  assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
  assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
  assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
  assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
  assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
  assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
  assign data_masked[19] = data_i[19] & sel_one_hot_i[1];
  assign data_masked[18] = data_i[18] & sel_one_hot_i[1];
  assign data_masked[17] = data_i[17] & sel_one_hot_i[1];
  assign data_masked[16] = data_i[16] & sel_one_hot_i[1];
  assign data_masked[15] = data_i[15] & sel_one_hot_i[1];
  assign data_masked[14] = data_i[14] & sel_one_hot_i[1];
  assign data_masked[13] = data_i[13] & sel_one_hot_i[1];
  assign data_masked[12] = data_i[12] & sel_one_hot_i[1];
  assign data_masked[11] = data_i[11] & sel_one_hot_i[1];
  assign data_masked[10] = data_i[10] & sel_one_hot_i[1];
  assign data_o[0] = data_masked[10] | data_masked[0];
  assign data_o[1] = data_masked[11] | data_masked[1];
  assign data_o[2] = data_masked[12] | data_masked[2];
  assign data_o[3] = data_masked[13] | data_masked[3];
  assign data_o[4] = data_masked[14] | data_masked[4];
  assign data_o[5] = data_masked[15] | data_masked[5];
  assign data_o[6] = data_masked[16] | data_masked[6];
  assign data_o[7] = data_masked[17] | data_masked[7];
  assign data_o[8] = data_masked[18] | data_masked[8];
  assign data_o[9] = data_masked[19] | data_masked[9];

endmodule
module bsg_circular_ptr_slots_p4_max_add_p1
(
  clk,
  reset_i,
  add_i,
  o
);

  input [0:0] add_i;
  output [1:0] o;
  input clk;
  input reset_i;
  wire N0,N1,N2,N3,N4,N5,N6,N7;
  wire [1:0] genblk1_genblk1_ptr_r_p1;
  reg [1:0] o;

  always @(posedge clk) begin
    if(N7) begin
      o[1] <= N4;
    end 
  end


  always @(posedge clk) begin
    if(N7) begin
      o[0] <= N3;
    end 
  end

  assign genblk1_genblk1_ptr_r_p1 = o + 1'b1;
  assign { N4, N3 } = (N0)? { 1'b0, 1'b0 } : 
                      (N1)? genblk1_genblk1_ptr_r_p1 : 1'b0;
  assign N0 = reset_i;
  assign N1 = N2;
  assign N2 = ~reset_i;
  assign N5 = ~add_i[0];
  assign N6 = N5 & N2;
  assign N7 = ~N6;

endmodule
module bsg_dff_en_width_p1
(
  clock_i,
  data_i,
  en_i,
  data_o
);

  input [0:0] data_i;
  output [0:0] data_o;
  input clock_i;
  input en_i;
  reg [0:0] data_o;

  always @(posedge clock_i) begin
    if(en_i) begin
      data_o[0] <= data_i[0];
    end 
  end


endmodule
module bsg_mux_one_hot_width_p1_els_p2
(
  data_i,
  sel_one_hot_i,
  data_o
);

  input [1:0] data_i;
  input [1:0] sel_one_hot_i;
  output [0:0] data_o;
  wire [0:0] data_o;
  wire [1:0] data_masked;
  assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
  assign data_masked[1] = data_i[1] & sel_one_hot_i[1];
  assign data_o[0] = data_masked[1] | data_masked[0];

endmodule
module bsg_mem_1r1w_synth_width_p9_els_p2_read_write_same_addr_p0_harden_p0
(
  w_clk_i,
  w_reset_i,
  w_v_i,
  w_addr_i,
  w_data_i,
  r_v_i,
  r_addr_i,
  r_data_o
);

  input [0:0] w_addr_i;
  input [8:0] w_data_i;
  input [0:0] r_addr_i;
  output [8:0] r_data_o;
  input w_clk_i;
  input w_reset_i;
  input w_v_i;
  input r_v_i;
  wire [8:0] r_data_o;
  wire N0,N1,N2,N3,N4,N5,N7,N8;
  reg [17:0] mem;
  assign r_data_o[8] = (N3)? mem[8] : 
                       (N0)? mem[17] : 1'b0;
  assign N0 = r_addr_i[0];
  assign r_data_o[7] = (N3)? mem[7] : 
                       (N0)? mem[16] : 1'b0;
  assign r_data_o[6] = (N3)? mem[6] : 
                       (N0)? mem[15] : 1'b0;
  assign r_data_o[5] = (N3)? mem[5] : 
                       (N0)? mem[14] : 1'b0;
  assign r_data_o[4] = (N3)? mem[4] : 
                       (N0)? mem[13] : 1'b0;
  assign r_data_o[3] = (N3)? mem[3] : 
                       (N0)? mem[12] : 1'b0;
  assign r_data_o[2] = (N3)? mem[2] : 
                       (N0)? mem[11] : 1'b0;
  assign r_data_o[1] = (N3)? mem[1] : 
                       (N0)? mem[10] : 1'b0;
  assign r_data_o[0] = (N3)? mem[0] : 
                       (N0)? mem[9] : 1'b0;

  always @(posedge w_clk_i) begin
    if(N8) begin
      mem[17] <= w_data_i[8];
    end 
  end


  always @(posedge w_clk_i) begin
    if(N8) begin
      mem[16] <= w_data_i[7];
    end 
  end


  always @(posedge w_clk_i) begin
    if(N8) begin
      mem[15] <= w_data_i[6];
    end 
  end


  always @(posedge w_clk_i) begin
    if(N8) begin
      mem[14] <= w_data_i[5];
    end 
  end


  always @(posedge w_clk_i) begin
    if(N8) begin
      mem[13] <= w_data_i[4];
    end 
  end


  always @(posedge w_clk_i) begin
    if(N8) begin
      mem[12] <= w_data_i[3];
    end 
  end


  always @(posedge w_clk_i) begin
    if(N8) begin
      mem[11] <= w_data_i[2];
    end 
  end


  always @(posedge w_clk_i) begin
    if(N8) begin
      mem[10] <= w_data_i[1];
    end 
  end


  always @(posedge w_clk_i) begin
    if(N8) begin
      mem[9] <= w_data_i[0];
    end 
  end


  always @(posedge w_clk_i) begin
    if(N7) begin
      mem[8] <= w_data_i[8];
    end 
  end


  always @(posedge w_clk_i) begin
    if(N7) begin
      mem[7] <= w_data_i[7];
    end 
  end


  always @(posedge w_clk_i) begin
    if(N7) begin
      mem[6] <= w_data_i[6];
    end 
  end


  always @(posedge w_clk_i) begin
    if(N7) begin
      mem[5] <= w_data_i[5];
    end 
  end


  always @(posedge w_clk_i) begin
    if(N7) begin
      mem[4] <= w_data_i[4];
    end 
  end


  always @(posedge w_clk_i) begin
    if(N7) begin
      mem[3] <= w_data_i[3];
    end 
  end


  always @(posedge w_clk_i) begin
    if(N7) begin
      mem[2] <= w_data_i[2];
    end 
  end


  always @(posedge w_clk_i) begin
    if(N7) begin
      mem[1] <= w_data_i[1];
    end 
  end


  always @(posedge w_clk_i) begin
    if(N7) begin
      mem[0] <= w_data_i[0];
    end 
  end

  assign N5 = ~w_addr_i[0];
  assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } : 
                      (N2)? { 1'b0, 1'b0 } : 1'b0;
  assign N1 = w_v_i;
  assign N2 = N4;
  assign N3 = ~r_addr_i[0];
  assign N4 = ~w_v_i;

endmodule
module bsg_adder_cin_width_p33
(
  a_i,
  b_i,
  cin_i,
  o
);

  input [32:0] a_i;
  input [32:0] b_i;
  output [32:0] o;
  input cin_i;
  wire [32:0] o;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
  N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32;
  assign { N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4, N3, N2, N1, N0 } = a_i + b_i;
  assign o = { N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4, N3, N2, N1, N0 } + cin_i;

endmodule
module bsg_buf_width_p32
(
  i,
  o
);

  input [31:0] i;
  output [31:0] o;
  wire [31:0] o;
  assign o[31] = i[31];
  assign o[30] = i[30];
  assign o[29] = i[29];
  assign o[28] = i[28];
  assign o[27] = i[27];
  assign o[26] = i[26];
  assign o[25] = i[25];
  assign o[24] = i[24];
  assign o[23] = i[23];
  assign o[22] = i[22];
  assign o[21] = i[21];
  assign o[20] = i[20];
  assign o[19] = i[19];
  assign o[18] = i[18];
  assign o[17] = i[17];
  assign o[16] = i[16];
  assign o[15] = i[15];
  assign o[14] = i[14];
  assign o[13] = i[13];
  assign o[12] = i[12];
  assign o[11] = i[11];
  assign o[10] = i[10];
  assign o[9] = i[9];
  assign o[8] = i[8];
  assign o[7] = i[7];
  assign o[6] = i[6];
  assign o[5] = i[5];
  assign o[4] = i[4];
  assign o[3] = i[3];
  assign o[2] = i[2];
  assign o[1] = i[1];
  assign o[0] = i[0];

endmodule
module bsg_manycore_pkt_encode_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20
(
  clk_i,
  v_i,
  addr_i,
  data_i,
  mask_i,
  we_i,
  my_x_i,
  my_y_i,
  v_o,
  data_o
);

  input [31:0] addr_i;
  input [31:0] data_i;
  input [3:0] mask_i;
  input [3:0] my_x_i;
  input [4:0] my_y_i;
  output [75:0] data_o;
  input clk_i;
  input v_i;
  input we_i;
  output v_o;
  wire [75:0] data_o;
  wire v_o,N0;
  assign data_o[75] = 1'b0;
  assign data_o[74] = addr_i[20];
  assign data_o[73] = addr_i[19];
  assign data_o[72] = addr_i[18];
  assign data_o[71] = addr_i[17];
  assign data_o[70] = addr_i[16];
  assign data_o[69] = addr_i[15];
  assign data_o[68] = addr_i[14];
  assign data_o[67] = addr_i[13];
  assign data_o[66] = addr_i[12];
  assign data_o[65] = addr_i[11];
  assign data_o[64] = addr_i[10];
  assign data_o[63] = addr_i[9];
  assign data_o[62] = addr_i[8];
  assign data_o[61] = addr_i[7];
  assign data_o[60] = addr_i[6];
  assign data_o[59] = addr_i[5];
  assign data_o[58] = addr_i[4];
  assign data_o[57] = addr_i[3];
  assign data_o[56] = addr_i[2];
  assign data_o[8] = addr_i[30];
  assign data_o[7] = addr_i[29];
  assign data_o[6] = addr_i[28];
  assign data_o[5] = addr_i[27];
  assign data_o[4] = addr_i[26];
  assign data_o[3] = addr_i[25];
  assign data_o[2] = addr_i[24];
  assign data_o[1] = addr_i[23];
  assign data_o[0] = addr_i[22];
  assign data_o[53] = mask_i[3];
  assign data_o[52] = mask_i[2];
  assign data_o[51] = mask_i[1];
  assign data_o[50] = mask_i[0];
  assign data_o[49] = data_i[31];
  assign data_o[48] = data_i[30];
  assign data_o[47] = data_i[29];
  assign data_o[46] = data_i[28];
  assign data_o[45] = data_i[27];
  assign data_o[44] = data_i[26];
  assign data_o[43] = data_i[25];
  assign data_o[42] = data_i[24];
  assign data_o[41] = data_i[23];
  assign data_o[40] = data_i[22];
  assign data_o[39] = data_i[21];
  assign data_o[38] = data_i[20];
  assign data_o[37] = data_i[19];
  assign data_o[36] = data_i[18];
  assign data_o[35] = data_i[17];
  assign data_o[34] = data_i[16];
  assign data_o[33] = data_i[15];
  assign data_o[32] = data_i[14];
  assign data_o[31] = data_i[13];
  assign data_o[30] = data_i[12];
  assign data_o[29] = data_i[11];
  assign data_o[28] = data_i[10];
  assign data_o[27] = data_i[9];
  assign data_o[26] = data_i[8];
  assign data_o[25] = data_i[7];
  assign data_o[24] = data_i[6];
  assign data_o[23] = data_i[5];
  assign data_o[22] = data_i[4];
  assign data_o[21] = data_i[3];
  assign data_o[20] = data_i[2];
  assign data_o[19] = data_i[1];
  assign data_o[18] = data_i[0];
  assign data_o[17] = my_y_i[4];
  assign data_o[16] = my_y_i[3];
  assign data_o[15] = my_y_i[2];
  assign data_o[14] = my_y_i[1];
  assign data_o[13] = my_y_i[0];
  assign data_o[12] = my_x_i[3];
  assign data_o[11] = my_x_i[2];
  assign data_o[10] = my_x_i[1];
  assign data_o[9] = my_x_i[0];
  assign data_o[54] = ~data_o[55];
  assign data_o[55] = addr_i[21];
  assign v_o = N0 & v_i;
  assign N0 = addr_i[31] & we_i;

endmodule
module bsg_scan_2_1_0
(
  i,
  o
);

  input [1:0] i;
  output [1:0] o;
  wire [1:0] o;
  assign o[1] = i[1] | 1'b0;
  assign o[0] = i[0] | i[1];

endmodule
module bsg_mux_width_p33_els_p2
(
  data_i,
  sel_i,
  data_o
);

  input [65:0] data_i;
  input [0:0] sel_i;
  output [32:0] data_o;
  wire [32:0] data_o;
  wire N0,N1;
  assign data_o[32] = (N1)? data_i[32] : 
                      (N0)? data_i[65] : 1'b0;
  assign N0 = sel_i[0];
  assign data_o[31] = (N1)? data_i[31] : 
                      (N0)? data_i[64] : 1'b0;
  assign data_o[30] = (N1)? data_i[30] : 
                      (N0)? data_i[63] : 1'b0;
  assign data_o[29] = (N1)? data_i[29] : 
                      (N0)? data_i[62] : 1'b0;
  assign data_o[28] = (N1)? data_i[28] : 
                      (N0)? data_i[61] : 1'b0;
  assign data_o[27] = (N1)? data_i[27] : 
                      (N0)? data_i[60] : 1'b0;
  assign data_o[26] = (N1)? data_i[26] : 
                      (N0)? data_i[59] : 1'b0;
  assign data_o[25] = (N1)? data_i[25] : 
                      (N0)? data_i[58] : 1'b0;
  assign data_o[24] = (N1)? data_i[24] : 
                      (N0)? data_i[57] : 1'b0;
  assign data_o[23] = (N1)? data_i[23] : 
                      (N0)? data_i[56] : 1'b0;
  assign data_o[22] = (N1)? data_i[22] : 
                      (N0)? data_i[55] : 1'b0;
  assign data_o[21] = (N1)? data_i[21] : 
                      (N0)? data_i[54] : 1'b0;
  assign data_o[20] = (N1)? data_i[20] : 
                      (N0)? data_i[53] : 1'b0;
  assign data_o[19] = (N1)? data_i[19] : 
                      (N0)? data_i[52] : 1'b0;
  assign data_o[18] = (N1)? data_i[18] : 
                      (N0)? data_i[51] : 1'b0;
  assign data_o[17] = (N1)? data_i[17] : 
                      (N0)? data_i[50] : 1'b0;
  assign data_o[16] = (N1)? data_i[16] : 
                      (N0)? data_i[49] : 1'b0;
  assign data_o[15] = (N1)? data_i[15] : 
                      (N0)? data_i[48] : 1'b0;
  assign data_o[14] = (N1)? data_i[14] : 
                      (N0)? data_i[47] : 1'b0;
  assign data_o[13] = (N1)? data_i[13] : 
                      (N0)? data_i[46] : 1'b0;
  assign data_o[12] = (N1)? data_i[12] : 
                      (N0)? data_i[45] : 1'b0;
  assign data_o[11] = (N1)? data_i[11] : 
                      (N0)? data_i[44] : 1'b0;
  assign data_o[10] = (N1)? data_i[10] : 
                      (N0)? data_i[43] : 1'b0;
  assign data_o[9] = (N1)? data_i[9] : 
                     (N0)? data_i[42] : 1'b0;
  assign data_o[8] = (N1)? data_i[8] : 
                     (N0)? data_i[41] : 1'b0;
  assign data_o[7] = (N1)? data_i[7] : 
                     (N0)? data_i[40] : 1'b0;
  assign data_o[6] = (N1)? data_i[6] : 
                     (N0)? data_i[39] : 1'b0;
  assign data_o[5] = (N1)? data_i[5] : 
                     (N0)? data_i[38] : 1'b0;
  assign data_o[4] = (N1)? data_i[4] : 
                     (N0)? data_i[37] : 1'b0;
  assign data_o[3] = (N1)? data_i[3] : 
                     (N0)? data_i[36] : 1'b0;
  assign data_o[2] = (N1)? data_i[2] : 
                     (N0)? data_i[35] : 1'b0;
  assign data_o[1] = (N1)? data_i[1] : 
                     (N0)? data_i[34] : 1'b0;
  assign data_o[0] = (N1)? data_i[0] : 
                     (N0)? data_i[33] : 1'b0;
  assign N1 = ~sel_i[0];

endmodule
module bsg_dff_reset_en_width_p10_harden_p1
(
  clock_i,
  reset_i,
  en_i,
  data_i,
  data_o
);

  input [9:0] data_i;
  output [9:0] data_o;
  input clock_i;
  input reset_i;
  input en_i;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15;
  reg [9:0] data_o;

  always @(posedge clock_i) begin
    if(N3) begin
      data_o[9] <= N13;
    end 
  end


  always @(posedge clock_i) begin
    if(N3) begin
      data_o[8] <= N12;
    end 
  end


  always @(posedge clock_i) begin
    if(N3) begin
      data_o[7] <= N11;
    end 
  end


  always @(posedge clock_i) begin
    if(N3) begin
      data_o[6] <= N10;
    end 
  end


  always @(posedge clock_i) begin
    if(N3) begin
      data_o[5] <= N9;
    end 
  end


  always @(posedge clock_i) begin
    if(N3) begin
      data_o[4] <= N8;
    end 
  end


  always @(posedge clock_i) begin
    if(N3) begin
      data_o[3] <= N7;
    end 
  end


  always @(posedge clock_i) begin
    if(N3) begin
      data_o[2] <= N6;
    end 
  end


  always @(posedge clock_i) begin
    if(N3) begin
      data_o[1] <= N5;
    end 
  end


  always @(posedge clock_i) begin
    if(N3) begin
      data_o[0] <= N4;
    end 
  end

  assign N3 = (N0)? 1'b1 : 
              (N15)? 1'b1 : 
              (N2)? 1'b0 : 1'b0;
  assign N0 = reset_i;
  assign { N13, N12, N11, N10, N9, N8, N7, N6, N5, N4 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 
                                                          (N15)? data_i : 1'b0;
  assign N1 = en_i | reset_i;
  assign N2 = ~N1;
  assign N14 = ~reset_i;
  assign N15 = en_i & N14;

endmodule
module data_arrays_0_ext(
  input RW0_clk,
  input [5:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [3:0] RW0_wmask,
  input [31:0] RW0_wdata,
  output [31:0] RW0_rdata
);

  fakeram45_64x32 mem (
    .clk      (RW0_clk   ),
    .rd_out   (RW0_rdata  ),
    .ce_in    (RW0_en    ),
    .we_in    (RW0_wmode     ),
    .w_mask_in({  {8{RW0_wmask[3]}}
                 ,{8{RW0_wmask[2]}}
                 ,{8{RW0_wmask[1]}}
                 ,{8{RW0_wmask[0]}}}
      ),
    .addr_in  (RW0_addr  ),
    .wd_in    (RW0_wdata  )
  );

endmodule
module tag_array_ext(
  input RW0_clk,
  input [1:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [0:0] RW0_wmask,
  input [24:0] RW0_wdata,
  output [24:0] RW0_rdata
);

  reg reg_RW0_ren;
  reg [1:0] reg_RW0_addr;
  reg [24:0] ram [3:0];
  `ifdef RANDOMIZE_MEM_INIT
    integer initvar;
    initial begin
      #`RANDOMIZE_DELAY begin end
      for (initvar = 0; initvar < 4; initvar = initvar+1)
        ram[initvar] = {1 {$random}};
      reg_RW0_addr = {1 {$random}};
    end
  `endif
  integer i;
  always @(posedge RW0_clk)
    reg_RW0_ren <= RW0_en && !RW0_wmode;
  always @(posedge RW0_clk)
    if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
  always @(posedge RW0_clk)
    if (RW0_en && RW0_wmode) begin
      for(i=0;i<1;i=i+1) begin
        if(RW0_wmask[i]) begin
          ram[RW0_addr][i*25 +: 25] <= RW0_wdata[i*25 +: 25];
        end
      end
    end
  `ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [31:0] RW0_random;
  `ifdef RANDOMIZE_MEM_INIT
    initial begin
      #`RANDOMIZE_DELAY begin end
      RW0_random = {$random};
      reg_RW0_ren = RW0_random[0];
    end
  `endif
  always @(posedge RW0_clk) RW0_random <= {$random};
  assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[24:0];
  `else
  assign RW0_rdata = ram[reg_RW0_addr];
  `endif

endmodule
module data_arrays_0_0_ext(
  input RW0_clk,
  input [5:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [0:0] RW0_wmask,
  input [31:0] RW0_wdata,
  output [31:0] RW0_rdata
);


  fakeram45_64x32 mem (
    .clk      (RW0_clk   ),
    .rd_out   (RW0_rdata  ),
    .ce_in    (RW0_en    ),
    .we_in    (RW0_wmode     ),
    .w_mask_in({  {8{RW0_wmask[3]}}
                 ,{8{RW0_wmask[2]}}
                 ,{8{RW0_wmask[1]}}
                 ,{8{RW0_wmask[0]}}}
      ),
    .addr_in  (RW0_addr  ),
    .wd_in    (RW0_wdata  )
  );

endmodule