dakies/OSS_Verilog huggingface dataset:
module io_cmos_nand_x128 (
input         in_p,
input         in_n,
input   [6:0] gray,
output        out_p,
output        out_n
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter   NAND_DELAY = 20;

wire [127:0]  bk;
wire [125:0]  a;
wire [124:0]  b;
wire [125:0]  c;
wire [124:0]  d;

io_cmos_nand_x128_decode xdec (
.gray	    ( gray[6:0]		),
.bk	    ( bk[127:0]		)
);

io_cmos_nand_x6 xnand_x6 [20:0] (
.in_p       ( {a[119],a[113],a[107],a[101],a[95],a[89],a[83],a[77],a[71],a[65],a[59],a[53],a[47],a[41],a[35],a[29],a[23],a[17],a[11],a[5],in_p}       ),
.in_n       ( {c[119],c[113],c[107],c[101],c[95],c[89],c[83],c[77],c[71],c[65],c[59],c[53],c[47],c[41],c[35],c[29],c[23],c[17],c[11],c[5],in_n}       ),
.bk5        ( {1'b0,bk[119],bk[113],bk[107],bk[101],bk[95],bk[89],bk[83],bk[77],bk[71],bk[65],bk[59],bk[53],bk[47],bk[41],bk[35],bk[29],bk[23],bk[17],bk[11],bk[5]} ),
.bk4        ( {bk[124],bk[118],bk[112],bk[106],bk[100],bk[94],bk[88],bk[82],bk[76],bk[70],bk[64],bk[58],bk[52],bk[46],bk[40],bk[34],bk[28],bk[22],bk[16],bk[10],bk[4]} ),
.bk3        ( {bk[123],bk[117],bk[111],bk[105],bk[99],bk[93],bk[87],bk[81],bk[75],bk[69],bk[63],bk[57],bk[51],bk[45],bk[39],bk[33],bk[27],bk[21],bk[15],bk[9],bk[3]}  ),
.bk2        ( {bk[122],bk[116],bk[110],bk[104],bk[98],bk[92],bk[86],bk[80],bk[74],bk[68],bk[62],bk[56],bk[50],bk[44],bk[38],bk[32],bk[26],bk[20],bk[14],bk[8],bk[2]}  ),
.bk1        ( {bk[121],bk[115],bk[109],bk[103],bk[97],bk[91],bk[85],bk[79],bk[73],bk[67],bk[61],bk[55],bk[49],bk[43],bk[37],bk[31],bk[25],bk[19],bk[13],bk[7],bk[1]}  ),
.bk0        ( {bk[120],bk[114],bk[108],bk[102],bk[96],bk[90],bk[84],bk[78],bk[72],bk[66],bk[60],bk[54],bk[48],bk[42],bk[36],bk[30],bk[24],bk[18],bk[12],bk[6],bk[0]}  ),
.ci_p       ( {1'b1,b[119],b[113],b[107],b[101],b[95],b[89],b[83],b[77],b[71],b[65],b[59],b[53],b[47],b[41],b[35],b[29],b[23],b[17],b[11],b[5]}       ),
.ci_n       ( {1'b1,d[119],d[113],d[107],d[101],d[95],d[89],d[83],d[77],d[71],d[65],d[59],d[53],d[47],d[41],d[35],d[29],d[23],d[17],d[11],d[5]}       ),
.out_p      ( {b[119],b[113],b[107],b[101],b[95],b[89],b[83],b[77],b[71],b[65],b[59],b[53],b[47],b[41],b[35],b[29],b[23],b[17],b[11],b[5],out_p}      ),
.out_n      ( {d[119],d[113],d[107],d[101],d[95],d[89],d[83],d[77],d[71],d[65],d[59],d[53],d[47],d[41],d[35],d[29],d[23],d[17],d[11],d[5],out_n}      ),
.co_p       ( {a[125],a[119],a[113],a[107],a[101],a[95],a[89],a[83],a[77],a[71],a[65],a[59],a[53],a[47],a[41],a[35],a[29],a[23],a[17],a[11],a[5]}     ),
.co_n       ( {c[125],c[119],c[113],c[107],c[101],c[95],c[89],c[83],c[77],c[71],c[65],c[59],c[53],c[47],c[41],c[35],c[29],c[23],c[17],c[11],c[5]}     )
);

endmodule
module hdpldadapt_rx_datapath_word_align 
  #(
    parameter DWIDTH = 'd40             // FIFO Input data width 
    )
    (
    input  wire               wr_clk,      	  // clock
    input  wire               wr_rst_n,       	  // async reset
    input  wire               wr_srst_n,       	  // async reset
    input  wire               r_wa_en,            // Word-align enable  
    input  wire [DWIDTH-1:0]  aib_fabric_rx_data_in,         // Write Data In 
    output wire [19:0]	      word_align_testbus,
    output wire		      wa_lock		  // Go to FIFO, status reg
    );
    
 //********************************************************************
// Define Parameters 
//********************************************************************


//********************************************************************
// Define variables 
//********************************************************************

reg		        wm_bit;
reg		        wm_bit_d1;
reg		        wm_bit_d2;
reg		        wm_bit_d3;
reg		        wm_bit_d4;
reg		        wm_bit_d5;
reg			wa_lock_lt;
wire			wa_lock_int;
//********************************************************************
// Main logic 
//********************************************************************



//Word-align
always @(negedge wr_rst_n or posedge wr_clk) begin
   if (wr_rst_n == 1'b0) begin
     wm_bit 	 <= 1'b0;
     wm_bit_d1 <= 1'b0;
     wm_bit_d2 <= 1'b0;
     wm_bit_d3 <= 1'b0;
     wm_bit_d4 <= 1'b0;
     wm_bit_d5 <= 1'b0;
   end
   else if (wr_srst_n == 1'b0) begin
     wm_bit 	 <= 1'b0;
     wm_bit_d1 <= 1'b0;
     wm_bit_d2 <= 1'b0;
     wm_bit_d3 <= 1'b0;
     wm_bit_d4 <= 1'b0;
     wm_bit_d5 <= 1'b0;
   end
   else begin
     wm_bit 	 <= aib_fabric_rx_data_in[39];
     wm_bit_d1 <= wm_bit;
     wm_bit_d2 <= wm_bit_d1;
     wm_bit_d3 <= wm_bit_d2;
     wm_bit_d4 <= wm_bit_d3;
     wm_bit_d5 <= wm_bit_d4;
   end
end

always @(negedge wr_rst_n or posedge wr_clk) begin
   if (wr_rst_n == 1'b0) begin
     wa_lock_lt 	 <= 1'b0;
   end
   else if (wr_srst_n == 1'b0) begin
     wa_lock_lt 	 <= 1'b0;
   end
   else begin
     wa_lock_lt 	 <= wa_lock_int || wa_lock_lt;
   end
end

assign wa_lock_int = wm_bit && ~wm_bit_d1 && wm_bit_d2 && ~wm_bit_d3 && wm_bit_d4 && ~wm_bit_d5 || ~r_wa_en;

assign wa_lock = wa_lock_int || wa_lock_lt;

//assign wa_error = (data_out[39] || ~data_out[79]) && r_wa_en && rd_en_reg;

//always @(negedge wr_rst_n or posedge wr_clk) begin
//   if (wr_rst_n == 1'b0) begin
//     wa_error_cnt <= 1'b0;
//   end
//   else if (wa_error_cnt < 4'b1111 && wa_error) begin
//     wa_error_cnt 	<= wa_error_cnt + 1'b1;
//   end
//end

assign word_align_testbus = {13'd0, wa_lock, wm_bit, wm_bit_d1, wm_bit_d2, wm_bit_d3, wm_bit_d4, wm_bit_d5};
  
  
endmodule
module hdpldadapt_rx_datapath_pulse_stretch
    (
    input  wire         clk,             // clock
    input  wire         rst_n,          // async reset
    input  wire         wr_pfull_raw,        //  input to stretch 
    input  wire         wr_full_raw,         //  input to stretch 
    input  wire         rx_fifo_del_raw,

    input  wire [2:0]   r_stretch_num_stages, // # stages
    
    output  wire        rx_fifo_del,
    output  wire        wr_pfull_stretch,      //  stretched output 
    output  wire        wr_full_stretch        //  stretched output 

     );

   wire [2:0]           num_stages;
   
   assign num_stages = r_stretch_num_stages;
   
   hdpldadapt_cmn_pulse_stretch 
     #(
       .RESET_VAL   (0)    	// Reset Value 
       ) hdpldadapt_cmn_pulse_stretch_fifo_del
     (
      .clk           (clk),
      .rst_n         (rst_n),             
      .num_stages    (num_stages),
      .data_in       (rx_fifo_del_raw),
      .data_out      (rx_fifo_del)                      
      ); 

// Flag pulse-stretch
   hdpldadapt_cmn_pulse_stretch 
     #(
       .RESET_VAL   (0)    	// Reset Value 
       ) hdpldadapt_cmn_pulse_stretch_wr_full
     (
      .clk           (clk),
      .rst_n         (rst_n),             
      .num_stages    (num_stages),
      .data_in       (wr_full_raw),
      .data_out      (wr_full_stretch)                      
      );

   hdpldadapt_cmn_pulse_stretch 
     #(
       .RESET_VAL   (0)    	// Reset Value 
       ) hdpldadapt_cmn_pulse_stretch_wr_pfull
     (
      .clk           (clk),
      .rst_n         (rst_n),             
      .num_stages    (num_stages),
      .data_in       (wr_pfull_raw),
      .data_out      (wr_pfull_stretch)                      
      );
      
endmodule
module hdpldadapt_rx_datapath_fifo_ram
  #(
    parameter DWIDTH = 'd40,             // FIFO Input data width 
    parameter DEPTH  = 'd16              // FIFO Depth 
    )
(
    input  wire              r_double_read,	// Read from 2 consecutive locations
    input  wire		     r_stop_write, // Disable/enable writing when FIFO is full    
    input  wire              wr_clk,     // Write Domain Clock
    input  wire		     wr_rst_n,   // Write Domain Reset 
    input  wire		     wr_full,
    input  wire              wr_en,      // Write Data Enable
    input  wire [DEPTH-1:0] wr_ptr,     // Write Pointer
    input  wire [DWIDTH-1:0] wr_data,    // Write Data In
    input  wire [DEPTH-1:0] rd_ptr,     // Read Pointer
    output reg  [DWIDTH-1:0] rd_data,   // Read Data
    output reg  [DWIDTH-1:0] rd_data2,    // Read Data
    output reg  [DWIDTH-1:0] rd_data_next,   // Read Data
    output reg  [DWIDTH-1:0] rd_data2_next    // Read Data

);

   //********************************************************************
   // Infer Memory or use Dual Port Memory from Quartus/ASIC Memory
   //********************************************************************

   wire 	[DEPTH-1:0]	rd_ptr2;   
   wire 	[DEPTH-1:0]	rd_ptr_next;   
   wire 	[DEPTH-1:0]	rd_ptr2_next;   
   integer		m;
   integer		i, j;
//   reg [DWIDTH-1:0]          fifo_mem [((1<<AWIDTH)-1):0];
   reg [DWIDTH-1:0]          fifo_mem [DEPTH-1:0];
   
   always @(negedge wr_rst_n or posedge wr_clk) begin
      if (~wr_rst_n) begin
         for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1)
            fifo_mem[m] <= 'd0;	
      end 
      else if (wr_en &&  (~wr_full||~r_stop_write)) begin
         for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1) begin
           if (wr_ptr[m]) begin
             fifo_mem[m] <= wr_data;
             end  
         end   
      end
   end

   assign rd_ptr2 = {rd_ptr[DEPTH-2:0], rd_ptr[DEPTH-1]};   

   assign rd_ptr_next = {rd_ptr[DEPTH-3:0], rd_ptr[DEPTH-1:DEPTH-2]};   

   assign rd_ptr2_next = {rd_ptr[DEPTH-4:0], rd_ptr[DEPTH-1:DEPTH-3]};   
   
   always @ *
   begin: data_out 
     rd_data = fifo_mem[0];
     for (i='d0; i<=(DEPTH-1'b1); i=i+1'b1) begin
       if (rd_ptr[i]) begin
         rd_data = fifo_mem[i];
       end       
     end   
      end 
      
      always @ *
      begin: data_out2 
        rd_data2 = fifo_mem[0];
     for (j='d0; j<=(DEPTH-1'b1); j=j+1'b1) begin
          if (rd_ptr2[j]) begin
            rd_data2 = fifo_mem[j];
       end       
     end   
   end 

      always @ *
      begin: data_out_next 
        rd_data_next = fifo_mem[0];
     for (j='d0; j<=(DEPTH-1'b1); j=j+1'b1) begin
          if (rd_ptr_next[j]) begin
            rd_data_next = fifo_mem[j];
       end       
     end   
   end 

      always @ *
      begin: data_out2_next 
        rd_data2_next = fifo_mem[0];
     for (j='d0; j<=(DEPTH-1'b1); j=j+1'b1) begin
          if (rd_ptr2_next[j]) begin
            rd_data2_next = fifo_mem[j];
       end       
     end   
   end 

   
endmodule
module hdpldadapt_rx_async_reserved_update (
// RXCLK_CTL
input   wire            rx_clock_async_rx_osc_clk, 

// RXRST_CTL
input   wire            rx_reset_async_rx_osc_clk_rst_n,

// SR
input  wire    [1:0]    rx_async_hssi_fabric_ssr_reserved,
input  wire             rx_async_hssi_fabric_ssr_load,

// PLD IF
output   wire  [1:0]    pld_rx_ssr_reserved_out 
);

// SLOW SR
hdpldadapt_async_update
    #( .AWIDTH       (2),
       .RESET_VAL    (0)
     ) async_rx_reserved_ssr_out
     ( .clk             (rx_clock_async_rx_osc_clk),
       .rst_n           (rx_reset_async_rx_osc_clk_rst_n),
       .sr_load         (rx_async_hssi_fabric_ssr_load),
       .async_data_in   (rx_async_hssi_fabric_ssr_reserved),
       .async_data_out  (pld_rx_ssr_reserved_out)
     );

endmodule
module hdpldadapt_rx_async_direct (
// AIB IF
input   wire   aib_fabric_pld_8g_rxelecidle,
input   wire   aib_fabric_pld_pma_rxpll_lock,
input   wire   aib_fabric_pld_pma_pfdmode_lock,

// PLD IF
output   wire  pld_pma_pfdmode_lock,
output   wire  pld_8g_rxelecidle,
output   wire  pld_pma_rxpll_lock

);

assign pld_8g_rxelecidle  = aib_fabric_pld_8g_rxelecidle;
assign pld_pma_rxpll_lock = aib_fabric_pld_pma_rxpll_lock;
assign pld_pma_pfdmode_lock          = aib_fabric_pld_pma_pfdmode_lock;

endmodule
module hdpldadapt_rx_chnl_testbus 
    (
    input   wire  [3:0]           r_rx_datapath_tb_sel,  // testbus sel
    input   wire [19:0]           rx_fifo_testbus1, 		// RX FIFO
    input   wire [19:0]           rx_fifo_testbus2, 		// RX FIFO
    input   wire [19:0]           rx_cp_bond_testbus,
    input   wire [19:0]           rx_asn_testbus,
    input   wire [19:0]           deletion_sm_testbus,
    input   wire [19:0]           insertion_sm_testbus,
    input   wire [19:0]           word_align_testbus,
    input   wire [19:0]           rx_hrdrst_testbus,    
    input   wire [19:0]           sr_testbus,    
    input   wire [19:0]           avmm_testbus,
    input   wire [19:0]           tx_chnl_testbus,
    input   wire [19:0]           sr_test_data,
    input   wire [19:0]           sr_parity_error_flag,

    output  reg [19:0]		  rx_chnl_testbus
     );
   
    always @* begin
      case (r_rx_datapath_tb_sel)
        4'b0000: rx_chnl_testbus = rx_fifo_testbus1;
        4'b0001: rx_chnl_testbus = rx_fifo_testbus2;
        4'b0010: rx_chnl_testbus = rx_cp_bond_testbus;
        4'b0011: rx_chnl_testbus = deletion_sm_testbus;
        4'b0100: rx_chnl_testbus = insertion_sm_testbus;
        4'b0101: rx_chnl_testbus = rx_asn_testbus;
        4'b0110: rx_chnl_testbus = word_align_testbus;
        4'b1011: rx_chnl_testbus = rx_hrdrst_testbus;
        4'b1010: rx_chnl_testbus = sr_testbus;        
        4'b1001: rx_chnl_testbus = avmm_testbus;
        4'b1000: rx_chnl_testbus = tx_chnl_testbus;        
        4'b1100: rx_chnl_testbus = sr_test_data;
        4'b1101: rx_chnl_testbus = sr_parity_error_flag;
        default: rx_chnl_testbus = {20{1'b0}};
      endcase // case(r_rx_testbus_sel)
    end // always @ *
         
endmodule // hdpldadapt_rx_chnl_testbus
module hdpldadapt_rx_async_reserved_capture (
// SR
input   wire            rx_async_fabric_hssi_ssr_load,

// RXCLK_CTL
input   wire            rx_clock_async_tx_osc_clk,

// RXRST_CTL
input   wire            rx_reset_async_tx_osc_clk_rst_n,

// PCS_IF
input  wire    [1:0]    pld_rx_ssr_reserved_in,

output   wire  [1:0]    rx_async_fabric_hssi_ssr_reserved 
);

wire [1:0] nc_0;

//generate
//  genvar i;
//    for (i=0; i < 2; i=i+1) begin: hdpldadapt_cmn_async_capture_bit
//    hdpldadapt_cmn_async_capture_bit
//     #(
//       .RESET_VAL   (1),
//       .CLK_FREQ_MHZ(1200),
//       .TOGGLE_TYPE (3),
//       .SYNC_STAGE  (4)
//       )
//      async_rx_reserved_ssr_in
//      (
//          .clk         (rx_clock_async_tx_osc_clk),
//          .rst_n       (rx_reset_async_tx_osc_clk_rst_n),
//          .data_in     (pld_rx_ssr_reserved_in[i]),
//          .unload      (rx_async_fabric_hssi_ssr_load),
//          .data_in_sync_out (nc_0[i]),
//          .data_out    (rx_async_fabric_hssi_ssr_reserved[i])
//      );
//   end
//endgenerate

    hdpldadapt_cmn_async_capture_bit
     #(
       .RESET_VAL   (1),
       .CLK_FREQ_MHZ(1200),
       .TOGGLE_TYPE (3),
       .SYNC_STAGE  (4)
       )
      async_rx_pld_rx_ssr_reserved_in0
      (
          .clk         (rx_clock_async_tx_osc_clk),
          .rst_n       (rx_reset_async_tx_osc_clk_rst_n),
          .data_in     (pld_rx_ssr_reserved_in[0]),
          .unload      (rx_async_fabric_hssi_ssr_load),
          .data_in_sync_out (nc_0[0]),
          .data_out    (rx_async_fabric_hssi_ssr_reserved[0])
      );


    hdpldadapt_cmn_async_capture_bit
     #(
       .RESET_VAL   (0),
       .CLK_FREQ_MHZ(1200),
       .TOGGLE_TYPE (3),
       .SYNC_STAGE  (4)
       )
      async_rx_pld_rx_ssr_reserved_in1
      (
          .clk         (rx_clock_async_tx_osc_clk),
          .rst_n       (rx_reset_async_tx_osc_clk_rst_n),
          .data_in     (pld_rx_ssr_reserved_in[1]),
          .unload      (rx_async_fabric_hssi_ssr_load),
          .data_in_sync_out (nc_0[1]),
          .data_out    (rx_async_fabric_hssi_ssr_reserved[1])
      );

endmodule
module hdpldadapt_sr_async_capture_bus 
   #(
      parameter RESET_VAL     = 1, // 1: Active high; 0: Active low
      parameter DWIDTH           = 2  // Sync Data input 
    )
   (
   // Inputs
   input  wire               clk,      	  // clock
   input  wire               rst_n,       // async reset
   input  wire [DWIDTH-1:0]  data_in,     // data in
   input  wire		     unload,      // unload data out
   input  wire		     r_capt_mode,      // capture mode
   // Outputs
   output reg  [DWIDTH-1:0]  data_out     // data out
   );

//******************************************************************************
// Define regs
//******************************************************************************
reg  [DWIDTH-1:0]		data_in_sync_d0;
reg  [DWIDTH-1:0]		data_in_sync_d1;
wire [DWIDTH-1:0] 		data_in_sync;
reg				sample;

   localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0;  // To eliminate truncating warning


   cdclib_bitsync2
   #(
   .DWIDTH      (DWIDTH),         // Sync Data input
   .RESET_VAL   (reset_value)          // Reset value
   )
   cdclib_bitsync2
      (
      .clk      (clk),
      .rst_n    (rst_n),
      .data_in  (data_in),
      .data_out (data_in_sync)
      );

   always @(negedge rst_n or posedge clk) begin
      if (rst_n == 1'b0) begin
        begin
          data_in_sync_d0 	<= {DWIDTH{reset_value}};
          data_in_sync_d1 	<= {DWIDTH{reset_value}};
        end
     end
     else begin
          data_in_sync_d0 	<= data_in_sync;
          data_in_sync_d1 	<= data_in_sync_d0;
        end
   end        
     
     
     
   always @(negedge rst_n or posedge clk) begin
      if (rst_n == 1'b0) begin
        begin
          sample 		<= 1'b0;
          data_out 		<= {DWIDTH{reset_value}};
        end
     end
     else begin
     // No sample during unload
         if (unload) begin
           sample <= 1'b0;
         end
     // Sample on the first data change after unload      
         else begin  
           if (r_capt_mode) begin
             if (~sample)   
               sample   <= 1'b1;
               data_out <= data_in_sync;
           end
           else begin
             if  (~sample && data_in_sync === data_in_sync_d0 && data_in_sync_d0 == data_in_sync_d1) begin
               sample   <= 1'b1;
               data_out <= data_in_sync_d1;
             end
           end
           
         end  
     end
   end

endmodule
module hdpldadapt_tx_async_reserved_update (
// TXCLK_CTL
input   wire            tx_clock_async_rx_osc_clk,     

// TXRST_CTL
input   wire            tx_reset_async_rx_osc_clk_rst_n,

// SR
input  wire    [2:0]    tx_async_hssi_fabric_ssr_reserved,

input  wire             tx_async_hssi_fabric_ssr_load,      

// PLD_IF
output wire    [2:0]    pld_tx_ssr_reserved_out 
);

// SLOW SR 
hdpldadapt_async_update
    #( .AWIDTH       (3),
       .RESET_VAL    (0)
     ) async_tx_reserved_ssr_out
     ( .clk             (tx_clock_async_rx_osc_clk),
       .rst_n           (tx_reset_async_rx_osc_clk_rst_n),
       .sr_load         (tx_async_hssi_fabric_ssr_load),
       .async_data_in   (tx_async_hssi_fabric_ssr_reserved),
       .async_data_out  (pld_tx_ssr_reserved_out)
     );


endmodule
module hdpldadapt_tx_datapath_word_mark
    (
      input  wire [79:0] data_in,         // Data In
      input  wire        r_wm_en,         // Word mark enable
      output wire [79:0] data_out         // Data Out
    );

//********************************************************************
// Define Parameters 
//********************************************************************


//********************************************************************
// Define variables 
//********************************************************************


//********************************************************************
// Main logic 
//********************************************************************

assign data_out = r_wm_en ? {1'b1, data_in[78:40], 1'b0, data_in[38:0]} : data_in;


endmodule
module hdpldadapt_sr_in_bit
 #(
    parameter RESET_VAL    = 0     // Reset value
  )
(
input wire  sr_load_in,
input wire  sr_shift_in,
input wire  sr_load,
input wire  clk,
input wire  rst_n,

output reg  sr_dataout
);

localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0;

always @(negedge rst_n or posedge clk)
  if (rst_n == 1'b0)
    begin
      sr_dataout <= reset_value;
    end
  else
    begin
      sr_dataout <= sr_load ? sr_load_in : sr_shift_in;
    end


endmodule
module hdpldadapt_fsr_out 
 #(
    parameter NUM_OF_PCS_CHAIN   = 16, 
    parameter NUM_OF_HIP_CHAIN   = 16,
    parameter NUM_OF_PARITY_BIT_FSROUT = 1 
  )
(
input wire                    sr_serial_in,
input wire                    sr_load,
input wire                    clk,
input wire                    rst_n,
input wire                    r_sr_hip_en,
input wire                    r_sr_parity_en,
//input wire  [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0] r_sr_bit,
output wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0] sr_parallel_out
);

localparam NUM_OF_UNUSED_HIP_CHAIN = NUM_OF_HIP_CHAIN - NUM_OF_PARITY_BIT_FSROUT;

wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0]  sr_datain_int;
wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0]  sr_dataout_int;

assign sr_datain_int[0] = sr_serial_in;

generate
  genvar i;
  for (i=0; i < (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN); i=i+1) begin: hdpldadapt_sr_out_bit
       hdpldadapt_sr_out_bit
       #(
           .RESET_VAL (0)
        ) hdpldadapt_sr_out_bit
         (
           // input
           .sr_shift_in  (sr_datain_int[i]),
           .sr_load      (sr_load),
           .clk          (clk),
           .rst_n        (rst_n),
           // output
           .sr_dataout   (sr_dataout_int[i])
         );
  end
endgenerate

generate
  genvar j;
  for (j=1; j < (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN); j=j+1)
  begin: fsr_out_chain_connection
    assign sr_datain_int[j] = sr_dataout_int[j-1];
  end
endgenerate


assign sr_parallel_out = r_sr_hip_en ? sr_dataout_int : !r_sr_parity_en ? ({{NUM_OF_HIP_CHAIN{1'b0}},sr_dataout_int[NUM_OF_PCS_CHAIN-1:0]}) : ({{NUM_OF_UNUSED_HIP_CHAIN{1'b0}}, sr_dataout_int[NUM_OF_PARITY_BIT_FSROUT+NUM_OF_PCS_CHAIN-1:0]}) ;  

endmodule
module hdpldadapt_tx_chnl_testbus 
    (
    input   wire  [2:0]            r_tx_datapath_tb_sel,  // testbus sel
    input   wire [19:0]           tx_fifo_testbus1, 		// RX FIFO
    input   wire [19:0]           tx_fifo_testbus2, 		// RX FIFO
    input   wire [19:0]           frame_gen_testbus1,
    input   wire [19:0]           frame_gen_testbus2,
    input   wire [19:0]		  dv_gen_testbus,    
    input   wire [19:0]           tx_cp_bond_testbus,
    input   wire [19:0]           tx_hrdrst_testbus,    
    
    output  reg [19:0]		  tx_chnl_testbus
     );
   
    always @* begin
      case (r_tx_datapath_tb_sel)
        3'b000: tx_chnl_testbus = frame_gen_testbus1;
        3'b001: tx_chnl_testbus = frame_gen_testbus2;
        3'b010: tx_chnl_testbus = dv_gen_testbus;
        3'b011: tx_chnl_testbus = tx_cp_bond_testbus;
        3'b100: tx_chnl_testbus = tx_fifo_testbus1;
        3'b101: tx_chnl_testbus = tx_fifo_testbus2;
        3'b111: tx_chnl_testbus = tx_hrdrst_testbus;
        default: tx_chnl_testbus = {20{1'b0}};
      endcase // case(r_rx_testbus_sel)
    end // always @ *
         
endmodule // hdpldadapt_tx_chnl_testbus
module hdpldadapt_fsr_in 
 #(
    parameter NUM_OF_PCS_CHAIN   = 16, 
    parameter NUM_OF_HIP_CHAIN   = 16, 
    parameter NUM_OF_PARITY_BIT_FSRIN = 1 
  )
(
input wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0] sr_parallel_in,
//input wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0] r_sr_bit,
input wire                    sr_load,
input wire                    clk,
input wire                    rst_n,
input wire                    r_sr_hip_en,
input wire                    r_sr_parity_en,
output wire                   sr_serial_out
);

wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0]  sr_datain_int;
wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0]  sr_dataout_int;

assign sr_datain_int[0] = sr_dataout_int[0];

generate
  genvar i;
  for (i=0; i < (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN) ; i=i+1) begin: hdpldadapt_sr_in_bit
       hdpldadapt_sr_in_bit
       #(
           .RESET_VAL (0)
        ) hdpldadapt_sr_in_bit
         (
           // input
           .sr_load_in   (sr_parallel_in[i]),
           .sr_shift_in  (sr_datain_int[i]),
           .sr_load      (sr_load),
           .clk          (clk),
           .rst_n        (rst_n),
           // output
           .sr_dataout   (sr_dataout_int[i])
         );
  end
endgenerate

generate
  genvar j;
  for (j=1; j < (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN); j=j+1)
  begin: fsr_in_chain_connection
    assign sr_datain_int[j] = sr_dataout_int[j-1];
  end
endgenerate

assign sr_serial_out = r_sr_hip_en ? sr_dataout_int[NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1] : 
                                     !r_sr_parity_en ? sr_dataout_int[NUM_OF_PCS_CHAIN - 1] : sr_dataout_int[NUM_OF_PCS_CHAIN+NUM_OF_PARITY_BIT_FSRIN-1];

endmodule
module hdpldadapt_async_update 
 #(
    parameter AWIDTH    = 1,    // Async input width
    parameter RESET_VAL = 0     // Reset value
  )
(
input  wire              clk,     
input  wire              rst_n,   
input  wire              sr_load,
input  wire [AWIDTH-1:0] async_data_in, 
output reg  [AWIDTH-1:0] async_data_out 
);

localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0;

always @(negedge rst_n or posedge clk)
  if (rst_n == 1'b0)
    begin
      async_data_out[AWIDTH-1:0] <= {(AWIDTH){reset_value}};
    end
  else
    begin
      async_data_out[AWIDTH-1:0] <= sr_load ? async_data_in[AWIDTH-1:0] : async_data_out[AWIDTH-1:0];
    end


endmodule
module hdpldadapt_sr_out_bit
 #(
    parameter RESET_VAL = 0     // Reset value
  )
(
input wire  sr_shift_in,
input wire  sr_load,
input wire  clk,
input wire  rst_n,

output reg  sr_dataout
);

localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0;

always @(negedge rst_n or posedge clk)
  if (rst_n == 1'b0)
    begin
      sr_dataout <= reset_value;
    end
  else
    begin
      sr_dataout <= (!sr_load) ? sr_shift_in : sr_dataout;
    end


endmodule
module hdpldadapt_sr_async_capture_bit 
   #(
      parameter RESET_VAL     = 0  // 1: Active high; 0: Active low
    )
   (
   // Inputs
   input  wire               clk,      	  // clock
   input  wire               rst_n,       // async reset
   input  wire  	     data_in,     // data in
   input  wire		     unload,      // unload data out
   // Outputs
   output reg   	     data_out     // data out
   );

//******************************************************************************
// Define regs
//******************************************************************************
reg  				data_in_sync_d0;
wire  				data_in_sync;
reg				sample;

localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0;  // To eliminate truncating warning


cdclib_bitsync2
#(
.DWIDTH      (1'b1),         // Sync Data input
.RESET_VAL   (reset_value)   // Reset value
)
cdclib_bitsync2
   (
   .clk      (clk),
   .rst_n    (rst_n),
   .data_in  (data_in),
   .data_out (data_in_sync)
   );
      
      
always @(negedge rst_n or posedge clk) begin
   if (rst_n == 1'b0) begin
     begin
       sample 		<= 1'b0;
       data_out 	<= reset_value;
     end
  end
  else begin
  // No sample during unload
      if (unload) begin
        sample <= 1'b0;
      end
  // Sample on the first data change after unload      
      else if (sample == 1'b0 && data_in_sync !== data_out) begin
        sample   <= 1'b1;
        data_out 		<= data_in_sync;
      end  
  end
end

endmodule
module hdpldadapt_srrst_ctl
(
	input   wire            csr_rdy_dly_in,
	input	wire		sr_clock_reset_rx_osc_clk,
	input	wire		sr_clock_reset_tx_osc_clk,
	input	wire		adapter_scan_rst_n,
	input	wire		adapter_scan_mode_n,
	output	wire		sr_reset_rx_osc_clk_rst_n,
	output	wire		sr_reset_tx_osc_clk_rst_n
);

	wire		int_sr_hrd_rst_n;

assign int_sr_hrd_rst_n = (adapter_scan_mode_n & csr_rdy_dly_in) | (~adapter_scan_mode_n & adapter_scan_rst_n);

cdclib_rst_n_sync cdclib_rst_n_sync_rx_osc_clk
	(
	.rst_n(int_sr_hrd_rst_n),
	.rst_n_bypass(adapter_scan_rst_n),
	.clk (sr_clock_reset_rx_osc_clk),
	.scan_mode_n(adapter_scan_mode_n),
	.rst_n_sync(sr_reset_rx_osc_clk_rst_n)
	);

cdclib_rst_n_sync cdclib_rst_n_sync_tx_osc_clk
	(
	.rst_n(int_sr_hrd_rst_n),
	.rst_n_bypass(adapter_scan_rst_n),
	.clk (sr_clock_reset_tx_osc_clk),
	.scan_mode_n(adapter_scan_mode_n),
	.rst_n_sync(sr_reset_tx_osc_clk_rst_n)
	);

endmodule // hdpldadapt_srrst_ctl
module hdpldadapt_tx_async_reserved_capture (
// SR
input   wire            tx_async_fabric_hssi_ssr_load,

// TXCLK_CTL
input   wire            tx_clock_async_tx_osc_clk,     

// TXRST_CTL
input   wire            tx_reset_async_tx_osc_clk_rst_n,

// PLD_IF 
input  wire    [2:0]    pld_tx_ssr_reserved_in, 

// SR
output  wire    [2:0]   tx_async_fabric_hssi_ssr_reserved 
);

wire [2:0] nc_1;

generate 
  genvar i;
    for (i=0; i < 3; i=i+1) begin: hdpldadapt_cmn_async_capture_bit
    hdpldadapt_cmn_async_capture_bit
     #(
       .RESET_VAL   (1),
       .CLK_FREQ_MHZ(1200),
       .TOGGLE_TYPE (3),
       .SYNC_STAGE  (4)
       )
      async_tx_reserved_ssr_in
      (
          .clk         (tx_clock_async_tx_osc_clk),
          .rst_n       (tx_reset_async_tx_osc_clk_rst_n),
          .data_in     (pld_tx_ssr_reserved_in[i]),
          .unload      (tx_async_fabric_hssi_ssr_load),
          .data_in_sync_out (nc_1[i]),
          .data_out    (tx_async_fabric_hssi_ssr_reserved[i])
      );
   end
endgenerate

endmodule
module hdpldadapt_tx_datapath_pulse_stretch
    (
    input  wire         clk,                   // clock
    input  wire         rst_n,                 // async reset
    input  wire         tx_frame_raw,          // input to stretch
    input  wire         burst_en_exe_raw,   //  input to stretch
    input  wire         wordslip_exe_raw,   //  input to stretch
    input  wire         rd_empty_raw,        //  input to stretch
    input  wire         rd_pempty_raw,       //  input to stretch

    input  wire [2:0]   r_stretch_num_stages,  // # stages sel
    output  wire        tx_frame,              // stretched output
    output  wire        tx_burst_en_exe,       //  stretched output
    output  wire        tx_wordslip_exe,       //  stretched output
    output  wire        rd_empty_stretch,      //  stretched output
    output  wire        rd_pempty_stretch      //  stretched output

    );

   wire [2:0]           num_stages;
   
   assign num_stages = r_stretch_num_stages;

   hdpldadapt_cmn_pulse_stretch 
     #(
       .RESET_VAL   (0)    	// Reset Value 
       ) hdpldadapt_cmn_pulse_stretch_tx_wordslip_exe
     (
      .clk           (clk),
      .rst_n         (rst_n),             
      .num_stages    (num_stages),
      .data_in       (wordslip_exe_raw),
      .data_out      (tx_wordslip_exe)                      
      ); 

   hdpldadapt_cmn_pulse_stretch 
     #(
       .RESET_VAL   (0)    	// Reset Value 
       ) hdpldadapt_cmn_pulse_stretch_tx_burst_en_exe
     (
      .clk           (clk),
      .rst_n         (rst_n),             
      .num_stages    (num_stages),
      .data_in       (burst_en_exe_raw),
      .data_out      (tx_burst_en_exe)                      
      ); 
   
   hdpldadapt_cmn_pulse_stretch 
     #(
       .RESET_VAL   (0)    	// Reset Value 
       ) hdpldadapt_cmn_pulse_stretch_tx_frame_raw
     (
      .clk           (clk),
      .rst_n         (rst_n),             
      .num_stages    (num_stages),
      .data_in       (tx_frame_raw),
      .data_out      (tx_frame)                      
      ); 

// Flag pulse-stretch
   hdpldadapt_cmn_pulse_stretch 
     #(
       .RESET_VAL   (1)    	// Reset Value 
       ) hdpldadapt_cmn_pulse_stretch_rd_empty
     (
      .clk           (clk),
      .rst_n         (rst_n),             
      .num_stages    (num_stages),
      .data_in       (rd_empty_raw),
      .data_out      (rd_empty_stretch)                      
      );

   hdpldadapt_cmn_pulse_stretch 
     #(
       .RESET_VAL   (1)    	// Reset Value 
       ) hdpldadapt_cmn_pulse_stretch_rd_pempty
     (
      .clk           (clk),
      .rst_n         (rst_n),             
      .num_stages    (num_stages),
      .data_in       (rd_pempty_raw),
      .data_out      (rd_pempty_stretch)                      
      );
      
endmodule
module hdpldadapt_tx_datapath_fifo_ram
  #(
    parameter DWIDTH = 'd40,             // FIFO Input data width 
    parameter DEPTH  = 'd16              // FIFO Depth 
    )
(
    input  wire              r_double_write,	// Write to 2 consecutive locations
    input  wire		     r_stop_write, // Disable/enable writing when FIFO is full    
    input  wire		     wr_full,
    input  wire              wr_clk,     // Write Domain Clock
    input  wire		     wr_rst_n,   // Write Domain Reset 
    input  wire              wr_en,      // Write Data Enable
    input  wire [DEPTH-1:0] wr_ptr,     // Write Pointer
    input  wire [DWIDTH-1:0] wr_data,    // Write Data In
    input  wire [DWIDTH-1:0] wr_data2,    // Write Data In
    input  wire [DEPTH-1:0] rd_ptr,     // Read Pointer
    output reg  [DWIDTH-1:0] rd_data   // Read Data

);

   //********************************************************************
   // Infer Memory or use Dual Port Memory from Quartus/ASIC Memory
   //********************************************************************
   
   integer		m;
   integer		i;
//   reg [DWIDTH-1:0]          fifo_mem [((1<<AWIDTH)-1):0];
   reg [DWIDTH-1:0]          fifo_mem [DEPTH-1:0];
   
   always @(negedge wr_rst_n or posedge wr_clk) begin
      if (~wr_rst_n) begin
         for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1)
            fifo_mem[m] <= 'd0;	
      end 
      else if (wr_en && (~wr_full||~r_stop_write)) begin
         for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1) begin
           if (wr_ptr[m]) begin
             fifo_mem[m] <= wr_data;
             if (r_double_write & m < DEPTH-1) // In double write mode, wr_ptr always increments by 2
               fifo_mem[m+1] <= wr_data2;
             end  
         end   
      end
   end
   
// assign rd_data = fifo_mem[rd_ptr];
// Read ptr must be one-hot
always @ *
begin: data_out 
  rd_data = fifo_mem[0];
  for (i='d0; i<=(DEPTH-1'b1); i=i+1'b1) begin
    if (rd_ptr[i]) begin
      rd_data = fifo_mem[i];
    end       
  end   
end 

endmodule
module hdpldadapt_tx_async_direct (
// PLD IF
input  wire            pld_pma_txdetectrx,

// AIB IF
input  wire            aib_fabric_pld_pma_fpll_lc_lock,

// PLD IF
output   wire          pld_pma_fpll_lc_lock,

// AIB IF
output   wire          aib_fabric_pld_pma_txdetectrx
);

assign aib_fabric_pld_pma_txdetectrx = pld_pma_txdetectrx;
assign pld_pma_fpll_lc_lock          = aib_fabric_pld_pma_fpll_lc_lock;

endmodule
module hdpldadapt_sr_sm 
 #(
    parameter NUM_OF_PCS_CHAIN   = 7'd16,
    parameter NUM_OF_HIP_CHAIN   = 7'd16,
    parameter NUM_OF_RESERVED_CHAIN_SSRIN = 7'd5, 
    parameter NUM_OF_PARITY_IN = 7'd1
  )
(
input wire  clk,
input wire  rst_n,
input wire  r_sr_hip_en,
input wire  r_sr_parity_en,
input wire  r_sr_reserbits_in_en, 
input wire  avmm_hrdrst_fabric_osc_transfer_en_sync,

output wire [11:0] sr_sm_testbus,
output reg  sr_loadout
);


localparam SR_LOAD  = 1'b1;
localparam SR_SHIFT = 1'b0; 

reg sr_ns;
reg sr_cs;
reg sr_loadout_comb;

reg sr_counter_expired;
reg sr_count_start_comb;
reg  [6:0] sr_counter;
wire [6:0] sr_counter_target;

assign sr_counter_target = (!r_sr_reserbits_in_en) ? (r_sr_hip_en ? (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1) : !r_sr_parity_en ? (NUM_OF_PCS_CHAIN - 1) : (NUM_OF_PARITY_IN + NUM_OF_PCS_CHAIN - 1) ) :
                                                     (r_sr_hip_en ? (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1) : 
                                                     !r_sr_parity_en ? (NUM_OF_PCS_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1) : (NUM_OF_PARITY_IN + NUM_OF_PCS_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1));

assign sr_sm_testbus = {1'b0, avmm_hrdrst_fabric_osc_transfer_en_sync, sr_cs, sr_counter_expired, sr_count_start_comb, sr_counter[6:0]};

 
always @(*) begin
  sr_ns = sr_cs;
  sr_loadout_comb = 1'b0;
  sr_count_start_comb = 1'b0;
 
  case (sr_cs)
    SR_LOAD: 
      begin
         sr_loadout_comb      = 1'b1;
         sr_count_start_comb  = 1'b0;
         sr_ns                = SR_SHIFT;
      end
    SR_SHIFT:
      begin
         sr_loadout_comb      = 1'b0;
         sr_count_start_comb  = 1'b1;
         if (sr_counter_expired == 1'b1) 
         begin 
             sr_ns      = SR_LOAD;
         end
      end
    default: 
      begin
         sr_loadout_comb     = 1'b1;
         sr_count_start_comb = 1'b0;
         sr_ns               = SR_LOAD;
      end
  endcase
end


always @(negedge rst_n or posedge clk)
  if (rst_n == 1'b0)
    begin
       sr_loadout <= 1'b1;
       sr_cs      <= SR_LOAD;
    end
  else if (avmm_hrdrst_fabric_osc_transfer_en_sync == 1'b0)
    begin
       sr_loadout <= 1'b1;
       sr_cs      <= SR_LOAD;
    end
  else
    begin
       sr_loadout <= sr_loadout_comb;
       sr_cs      <= sr_ns;
    end
    
always @(negedge rst_n or posedge clk)
  if (rst_n == 1'b0)
    begin
      sr_counter <= 7'b000_0000;
      sr_counter_expired <= 1'b0; 
    end
  else
    begin
       if (sr_count_start_comb == 1'b1) begin
           sr_counter <= sr_counter + 7'b000_0001;
           sr_counter_expired <= (sr_counter[6:0] == (sr_counter_target[6:0]-1))? 1'b1: 1'b0;
       end
       else begin
           sr_counter <= 7'b000_0000;
           sr_counter_expired <= 1'b0;
       end
    end

endmodule
module hdpldadapt_ssr_in 
 #(
    parameter NUM_OF_PCS_CHAIN   = 16, 
    parameter NUM_OF_HIP_CHAIN   = 16,
    parameter NUM_OF_RESERVED_CHAIN_SSRIN = 5,
    parameter NUM_OF_PARITY_BIT_SSRIN = 6
  )
(
input wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1):0] sr_parallel_in,
input wire                    sr_load,
input wire                    clk,
input wire                    rst_n,
input wire                    r_sr_hip_en,
input wire                    r_sr_parity_en,
input wire                    r_sr_reserbits_in_en,
output wire                   sr_serial_out
);

wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1):0]  sr_datain_int;
wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1):0]  sr_dataout_int;

assign sr_datain_int[0] = sr_dataout_int[0];

generate
  genvar i; 
  for (i=0; i < (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN); i=i+1) begin: hdpldadapt_sr_in_bit
       hdpldadapt_sr_in_bit 
       #(
           .RESET_VAL (0)
        ) hdpldadapt_sr_in_bit
         (
           // input
           .sr_load_in   (sr_parallel_in[i]),
           .sr_shift_in  (sr_datain_int[i]),
           .sr_load      (sr_load),
           .clk          (clk),
           .rst_n        (rst_n),
           // output
           .sr_dataout   (sr_dataout_int[i])
         );
  end
endgenerate

generate
  genvar j;
  for (j=1; j < (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN); j=j+1)
  begin: ssr_in_chain_connection
    if (j == (NUM_OF_PCS_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN)) begin
        assign sr_datain_int[j] = r_sr_reserbits_in_en ? sr_dataout_int[j-1] : sr_dataout_int[NUM_OF_PCS_CHAIN-1];
    end
    else begin
        assign sr_datain_int[j] = sr_dataout_int[j-1];
    end
  end
endgenerate

assign sr_serial_out = r_sr_hip_en      ? sr_dataout_int[NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1] :
                       r_sr_parity_en       ? sr_dataout_int[NUM_OF_PCS_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN + NUM_OF_PARITY_BIT_SSRIN - 1] :
                       r_sr_reserbits_in_en ? sr_dataout_int[NUM_OF_PCS_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1] : sr_dataout_int[NUM_OF_PCS_CHAIN - 1];

endmodule
module hdpldadapt_cmn_pulse_stretch 
  #(
    parameter RESET_VAL = 'd0   // reset value
    )
  (
    input  wire         clk,         // clock
    input  wire         rst_n,       // async reset
    input  wire [2:0]   num_stages,  // number of stages required
    input  wire         data_in,     // data in
    output  reg         data_out     // stretched data out             
   );

   reg                  data_d1, data_d2, data_d3, data_d4;
   reg                  data_d5, data_d6, data_d7;
   reg                  data_out_comb;

   localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0;  // To eliminate truncating warning
      
   always @* begin
      data_out_comb = data_in;
      
      case (num_stages)
        3'b000: data_out_comb = data_in;
        3'b001: data_out_comb = data_d1 | data_in;
        3'b010: data_out_comb = data_d2 | data_d1 | data_in;
        3'b011: data_out_comb = data_d3 | data_d2 | data_d1 | data_in;
        3'b100: data_out_comb = data_d4 | data_d3 | data_d2 | data_d1 | data_in;
        3'b101: data_out_comb = data_d5 | data_d4 | data_d3 | data_d2 | data_d1 | data_in;
        3'b110: data_out_comb = data_d6 | data_d5 | data_d4 | data_d3 | data_d2 | data_d1 | data_in;
        3'b111: data_out_comb = data_d7 | data_d6 | data_d5 | data_d4 | data_d3 | data_d2 | data_d1 | data_in;
        default: data_out_comb = data_in;
      endcase // case(num_stages)
   end // always @ *

   always @(negedge rst_n or posedge clk) begin
      if (~rst_n) begin
         data_d1 <= reset_value;
         data_d2 <= reset_value;
         data_d3 <= reset_value;
         data_d4 <= reset_value;
         data_d5 <= reset_value;
         data_d6 <= reset_value;
         data_d7 <= reset_value;
         data_out <= reset_value;
      end
      else begin
         data_d1 <= data_in;
         data_d2 <= data_d1;
         data_d3 <= data_d2;
         data_d4 <= data_d3;
         data_d5 <= data_d4;
         data_d6 <= data_d5;
         data_d7 <= data_d6;
         data_out <= data_out_comb;
      end
   end // always @ (negedge rst_n or posedge clk)
      
endmodule // hdpldadapt_cmn_pulse_stretch
module hdpldadapt_cmn_dft_clock_controller (
  user_clk,                               //User clock
  test_clk,                               //Test clock      
  rst_n,				  //Reset (active low)
  clk_sel_n,                              //Mux sel between user or test clock, Active low
  scan_enable,                            //Scan enable control signal, Active high in IP, Active low in top level
  occ_enable,                             //Control signal to enable OCC, Active high in IP, Active low in top level
  atpg_mode,                              //Control signal for test mode, Active high in IP, Active low in top level
  out_clk                                 //Output clock 
);

parameter CONTROL_REGISTER_PRESENT = 0;

input user_clk;
input test_clk;
input rst_n;
input clk_sel_n;
input scan_enable;
input atpg_mode;
input occ_enable;
output out_clk;

wire int_test_clk;
wire int_user_clk; 
wire [1:0] burst_cnt;                     //may required more bus width if more pulse needed. Current is 2 pulses
wire clk_sel;
wire occ_enable_nand;
wire occ_user_clken;
wire occ_rst_n;

//Inversion for the clock selection  control signal
assign clk_sel = ~clk_sel_n;

// Reset logic
assign occ_rst_n = (atpg_mode == 1'b1)? 1'b1 : rst_n;


// clock mux (between user and test clock) - use clock MUX
//altr_hps_ckmux21 altr_ckmux21_inst(
hdpldadapt_cmn_clkmux2 altr_ckmux21_inst(
  .clk_0   (int_user_clk),
  .clk_1   (int_test_clk),
  .clk_sel (clk_sel),
  .clk_o   (out_clk)
);

// scan control registers
hdpldadapt_cmn_occ_test_control_register ctrl_reg (
  .clk   (test_clk),
  .rst_n (occ_rst_n),
  .ctrl  (burst_cnt)
//  .clken (test_clk_en)
);

//test clock enable
generate
if(CONTROL_REGISTER_PRESENT == 1) begin : CONTROL_REG
  reg test_clken /* synopsys preserve_sequential */;
  always @(posedge test_clk)
    test_clken <= test_clken;

  //altr_hps_clkgate altr_clkgate_test_inst(
  hdpldadapt_cmn_occ_clkgate altr_clkgate_test_inst (
     .clk          (test_clk),
     .clk_enable_i (test_clken),
     .clk_o        (int_test_clk)
  );
end
else begin
  assign int_test_clk = test_clk;
end

endgenerate

// user clock enable
//altr_hps_clkgate altr_clkgate_user_inst(
hdpldadapt_cmn_occ_clkgate altr_clkgate_user_inst(
   .clk          (user_clk),
   .clk_enable_i (occ_user_clken),
   .clk_o        (int_user_clk)
);

hdpldadapt_cmn_occ_enable_logic occ_enable_logic_inst(

    .user_clk (user_clk),
    .scan_enable (scan_enable),
    .occ_enable (occ_enable),
    .atpg_mode (atpg_mode),
    .burst_cnt (burst_cnt),
    .occ_user_clken (occ_user_clken)
);

endmodule
module hdpldadapt_cmn_async_capture_bit 
   #(
      parameter RESET_VAL     = 0, // 1: Active high; 0: Active low
      parameter SYNC_STAGE    = 4,
      parameter CLK_FREQ_MHZ  = 1,
      parameter TOGGLE_TYPE  = 1    // Toggle type: 1 --> 5

    )
   (
   // Inputs
   input  wire               clk,      	  // clock
   input  wire               rst_n,       // async reset
   input  wire  	     data_in,     // data in
   input  wire		     unload,      // unload data out
   // Outputs
   output wire               data_in_sync_out,
   output reg   	     data_out     // data out
   );

//******************************************************************************
// Define regs
//******************************************************************************
reg  				data_in_sync_d0;
wire  				data_in_sync;
reg				sample;

localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0;  // To eliminate truncating warning



generate
if (SYNC_STAGE == 2) begin  
cdclib_bitsync2
#(
.DWIDTH      (1'b1),         // Sync Data input
.RESET_VAL   (reset_value),  // Reset value
.CLK_FREQ_MHZ (CLK_FREQ_MHZ), // Freq in MHz 
.TOGGLE_TYPE (TOGGLE_TYPE),
.VID	     (1)
)
cdclib_bitsync2
   (
   .clk      (clk),
   .rst_n    (rst_n),
   .data_in  (data_in),
   .data_out (data_in_sync)
   );
end
else begin
cdclib_bitsync4
#(
.DWIDTH      (1'b1),         // Sync Data input
.RESET_VAL   (reset_value),  // Reset value
.CLK_FREQ_MHZ (CLK_FREQ_MHZ), // Freq in MHz 
.TOGGLE_TYPE (TOGGLE_TYPE),
.VID	     (1)
)
cdclib_bitsync4
   (
   .clk      (clk),
   .rst_n    (rst_n),
   .data_in  (data_in),
   .data_out (data_in_sync)
   );
end
endgenerate
     
assign data_in_sync_out = data_in_sync; 
      
always @(negedge rst_n or posedge clk) begin
   if (rst_n == 1'b0) begin
     begin
       sample 		<= 1'b0;
       data_out 	<= reset_value;
     end
  end
  else begin
  // No sample during unload
      if (unload) begin
        sample <= 1'b0;
      end
  // Sample on the first data change after unload      
      else if (sample == 1'b0 && data_in_sync != data_out) begin
        sample   <= 1'b1;
        data_out 		<= data_in_sync;
      end  
  end
end

endmodule
module hdpldadapt_cmn_clkmux2_cell
(
        output  wire    clkout,
        input   wire    clk2,
        input   wire    clk1,
        input   wire    s
);

      assign clkout = s ? clk1 : clk2;

endmodule // hdpldadapt_cmn_clkmux2_cell