dakies/OSS_Verilog huggingface dataset:
module aludec(
	input wire[5:0] funct,
	input wire[1:0] aluop,
	output reg[2:0] alucontrol
    );
	always @(*) begin
		case (aluop)
			2'b00: alucontrol <= 3'b010;//add (for lw/sw/addi)
			2'b01: alucontrol <= 3'b110;//sub (for beq)
			default : case (funct)
				6'b100000:alucontrol <= 3'b010; //add
				6'b100010:alucontrol <= 3'b110; //sub
				6'b100100:alucontrol <= 3'b000; //and
				6'b100101:alucontrol <= 3'b001; //or
				6'b101010:alucontrol <= 3'b111; //slt
				default:  alucontrol <= 3'b000;
			endcase
		endcase
	
	end
endmodule
module sl2(
	input wire[31:0] a,
	output wire[31:0] y
    );

	assign y = {a[29:0],2'b00};
endmodule
module pc #(parameter WIDTH = 8)(
	input wire clk,rst,en,
	input wire[WIDTH-1:0] d,
	output reg[WIDTH-1:0] q
    );
	always @(posedge clk,posedge rst) begin
		if(rst) begin
			q <= 0;
		end else if(en) begin
			/* code */
			q <= d;
		end
	end
endmodule
module mux3 #(parameter WIDTH = 8)(
	input wire[WIDTH-1:0] d0,d1,d2,
	input wire[1:0] s,
	output wire[WIDTH-1:0] y
    );

	assign y = (s == 2'b00) ? d0 :
				(s == 2'b01) ? d1:
				(s == 2'b10) ? d2: d0;
endmodule
module flopenrc #(parameter WIDTH = 8)(
	input wire clk,rst,en,clear,
	input wire[WIDTH-1:0] d,
	output reg[WIDTH-1:0] q
    );
	always @(posedge clk) begin
		if(rst) begin
			q <= 0;
		end else if(clear) begin
			q <= 0;
		end else if(en) begin
			/* code */
			q <= d;
		end
	end
endmodule
module eqcmp(
	input wire [31:0] a,b,
	output wire y
    );

	assign y = (a == b) ? 1 : 0;
endmodule
module maindec(
	input wire[5:0] op,

	output wire memtoreg,memwrite,
	output wire branch,alusrc,
	output wire regdst,regwrite,
	output wire jump,
	output wire[1:0] aluop
    );
	reg[8:0] controls;
	assign {regwrite,regdst,alusrc,branch,memwrite,memtoreg,jump,aluop} = controls;
	always @(*) begin
		case (op)
			6'b000000:controls <= 9'b110000010;//R-TYRE
			6'b100011:controls <= 9'b101001000;//LW
			6'b101011:controls <= 9'b001010000;//SW
			6'b000100:controls <= 9'b000100001;//BEQ
			6'b001000:controls <= 9'b101000000;//ADDI
			
			6'b000010:controls <= 9'b000000100;//J
			default:  controls <= 9'b000000000;//illegal op
		endcase
	end
endmodule
module hazard(
	//fetch stage
	output wire stallF,
	//decode stage
	input wire[4:0] rsD,rtD,
	input wire branchD,
	output wire forwardaD,forwardbD,
	output wire stallD,
	//execute stage
	input wire[4:0] rsE,rtE,
	input wire[4:0] writeregE,
	input wire regwriteE,
	input wire memtoregE,
	output reg[1:0] forwardaE,forwardbE,
	output wire flushE,
	//mem stage
	input wire[4:0] writeregM,
	input wire regwriteM,
	input wire memtoregM,

	//write back stage
	input wire[4:0] writeregW,
	input wire regwriteW
    );

	wire lwstallD,branchstallD;

	//forwarding sources to D stage (branch equality)
	assign forwardaD = (rsD != 0 & rsD == writeregM & regwriteM);
	assign forwardbD = (rtD != 0 & rtD == writeregM & regwriteM);
	
	//forwarding sources to E stage (ALU)

	always @(*) begin
		forwardaE = 2'b00;
		forwardbE = 2'b00;
		if(rsE != 0) begin
			/* code */
			if(rsE == writeregM & regwriteM) begin
				/* code */
				forwardaE = 2'b10;
			end else if(rsE == writeregW & regwriteW) begin
				/* code */
				forwardaE = 2'b01;
			end
		end
		if(rtE != 0) begin
			/* code */
			if(rtE == writeregM & regwriteM) begin
				/* code */
				forwardbE = 2'b10;
			end else if(rtE == writeregW & regwriteW) begin
				/* code */
				forwardbE = 2'b01;
			end
		end
	end

	//stalls
	assign #1 lwstallD = memtoregE & (rtE == rsD | rtE == rtD);
	assign #1 branchstallD = branchD &
				(regwriteE & 
				(writeregE == rsD | writeregE == rtD) |
				memtoregM &
				(writeregM == rsD | writeregM == rtD));
	assign #1 stallD = lwstallD | branchstallD;
	assign #1 stallF = stallD;
		//stalling D stalls all previous stages
	assign #1 flushE = stallD;
		//stalling D flushes next stage
	// Note: not necessary to stall D stage on store
  	//       if source comes from load;
  	//       instead, another bypass network could
  	//       be added from W to M
endmodule
module mips(
	input wire clk,rst,
	output wire[31:0] pcF,
	input wire[31:0] instrF,
	output wire memwriteM,
	output wire[31:0] aluoutM,writedataM,
	input wire[31:0] readdataM 
    );
	
	wire [5:0] opD,functD;
	wire regdstE,alusrcE,pcsrcD,memtoregE,memtoregM,memtoregW,
			regwriteE,regwriteM,regwriteW;
	wire [2:0] alucontrolE;
	wire flushE,equalD;

	controller c(
		clk,rst,
		//decode stage
		opD,functD,
		pcsrcD,branchD,equalD,jumpD,
		
		//execute stage
		flushE,
		memtoregE,alusrcE,
		regdstE,regwriteE,	
		alucontrolE,

		//mem stage
		memtoregM,memwriteM,
		regwriteM,
		//write back stage
		memtoregW,regwriteW
		);
	datapath dp(
		clk,rst,
		//fetch stage
		pcF,
		instrF,
		//decode stage
		pcsrcD,branchD,
		jumpD,
		equalD,
		opD,functD,
		//execute stage
		memtoregE,
		alusrcE,regdstE,
		regwriteE,
		alucontrolE,
		flushE,
		//mem stage
		memtoregM,
		regwriteM,
		aluoutM,writedataM,
		readdataM,
		//writeback stage
		memtoregW,
		regwriteW
	    );
	
endmodule
module top(
	input wire clk,rst,
	output wire[31:0] writedata,dataadr,
	output wire memwrite
    );

	wire[31:0] pc,instr,readdata;

	mips mips(clk,rst,pc,instr,memwrite,dataadr,writedata,readdata);
	inst_mem imem(~clk,pc[7:2],instr);
	data_mem dmem(~clk,memwrite,dataadr,writedata,readdata);
endmodule
module regfile(
	input wire clk,
	input wire we3,
	input wire[4:0] ra1,ra2,wa3,
	input wire[31:0] wd3,
	output wire[31:0] rd1,rd2
    );

	reg [31:0] rf[31:0];

	always @(negedge clk) begin
		if(we3) begin
			 rf[wa3] <= wd3;
		end
	end

	assign rd1 = (ra1 != 0) ? rf[ra1] : 0;
	assign rd2 = (ra2 != 0) ? rf[ra2] : 0;
endmodule
module flopr #(parameter WIDTH = 8)(
	input wire clk,rst,
	input wire[WIDTH-1:0] d,
	output reg[WIDTH-1:0] q
    );
	always @(posedge clk,posedge rst) begin
		if(rst) begin
			q <= 0;
		end else begin
			q <= d;
		end
	end
endmodule
module alu(
	input wire[31:0] a,b,
	input wire[2:0] op,
	output reg[31:0] y,
	output reg overflow,
	output wire zero
    );

	wire[31:0] s,bout;
	assign bout = op[2] ? ~b : b;
	assign s = a + bout + op[2];
	always @(*) begin
		case (op[1:0])
			2'b00: y <= a & bout;
			2'b01: y <= a | bout;
			2'b10: y <= s;
			2'b11: y <= s[31];
			default : y <= 32'b0;
		endcase	
	end
	assign zero = (y == 32'b0);

	always @(*) begin
		case (op[2:1])
			2'b01:overflow <= a[31] & b[31] & ~s[31] |
							~a[31] & ~b[31] & s[31];
			2'b11:overflow <= ~a[31] & b[31] & s[31] |
							a[31] & ~b[31] & ~s[31];
			default : overflow <= 1'b0;
		endcase	
	end
endmodule
module controller(
	input wire[5:0] op,funct,
	input wire zero,
	output wire memtoreg,memwrite,
	output wire pcsrc,alusrc,
	output wire regdst,regwrite,
	output wire jump,
	output wire[2:0] alucontrol
    );
	wire[1:0] aluop;
	wire branch;

	maindec md(op,memtoreg,memwrite,branch,alusrc,regdst,regwrite,jump,aluop);
	aludec ad(funct,aluop,alucontrol);

	assign pcsrc = branch & zero;
endmodule
module maindec(
	input wire[5:0] op,

	output wire memtoreg,memwrite,
	output wire branch,alusrc,
	output wire regdst,regwrite,
	output wire jump,
	output wire[1:0] aluop
    );
	reg[8:0] controls;
	assign {regwrite,regdst,alusrc,branch,memwrite,memtoreg,jump,aluop} = controls;
	always @(*) begin
		case (op)
			6'b000000:controls <= 9'b110000010;//R-TYRE
			6'b100011:controls <= 9'b101001000;//LW
			6'b101011:controls <= 9'b001010000;//SW
			6'b000100:controls <= 9'b000100001;//BEQ
			6'b001000:controls <= 9'b101000000;//ADDI
			6'b000010:controls <= 9'b000000100;//J
			default:  controls <= 9'b000000000;//illegal op
		endcase
	end
endmodule
module mips(
	input wire clk,rst,
	output wire[31:0] pc,
	input wire[31:0] instr,
	output wire memwrite,
	output wire[31:0] aluout,writedata,
	input wire[31:0] readdata 
    );
	
	wire memtoreg,alusrc,regdst,regwrite,jump,pcsrc,zero,overflow;
	wire[2:0] alucontrol;

	controller c(instr[31:26],instr[5:0],zero,memtoreg,
		memwrite,pcsrc,alusrc,regdst,regwrite,jump,alucontrol);
	datapath dp(clk,rst,memtoreg,pcsrc,alusrc,
		regdst,regwrite,jump,alucontrol,overflow,zero,pc,instr,aluout,writedata,readdata);
	
endmodule
module datapath(
	input wire clk,rst,
	input wire memtoreg,pcsrc,
	input wire alusrc,regdst,
	input wire regwrite,jump,
	input wire[2:0] alucontrol,
	output wire overflow,zero,
	output wire[31:0] pc,
	input wire[31:0] instr,
	output wire[31:0] aluout,writedata,
	input wire[31:0] readdata
    );
	
	wire[4:0] writereg;
	wire[31:0] pcnext,pcnextbr,pcplus4,pcbranch;
	wire[31:0] signimm,signimmsh;
	wire[31:0] srca,srcb;
	wire[31:0] result;

	flopr #(32) pcreg(clk,rst,pcnext,pc);
	adder pcadd1(pc,32'b100,pcplus4);
	sl2 immsh(signimm,signimmsh);
	adder pcadd2(pcplus4,signimmsh,pcbranch);
	mux2 #(32) pcbrmux(pcplus4,pcbranch,pcsrc,pcnextbr);
	mux2 #(32) pcmux(pcnextbr,{pcplus4[31:28],instr[25:0],2'b00},jump,pcnext);

	regfile rf(clk,regwrite,instr[25:21],instr[20:16],writereg,result,srca,writedata);
	mux2 #(5) wrmux(instr[20:16],instr[15:11],regdst,writereg);
	mux2 #(32) resmux(aluout,readdata,memtoreg,result);
	signext se(instr[15:0],signimm);

	mux2 #(32) srcbmux(writedata,signimm,alusrc,srcb);
	alu alu(srca,srcb,alucontrol,aluout,overflow,zero);

endmodule
module top(
	input wire clk,rst,
	output wire[31:0] writedata,dataadr,
	output wire memwrite
    );

	wire[31:0] pc,instr,readdata;

	mips mips(clk,rst,pc,instr,memwrite,dataadr,writedata,readdata);
	inst_mem imem(clk,pc[7:2],instr);
	data_mem dmem(~clk,memwrite,dataadr,writedata,readdata);
endmodule
module regfile(
	input wire clk,
	input wire we3,
	input wire[4:0] ra1,ra2,wa3,
	input wire[31:0] wd3,
	output wire[31:0] rd1,rd2
    );

	reg [31:0] rf[31:0];

	always @(posedge clk) begin
		if(we3) begin
			 rf[wa3] <= wd3;
		end
	end

	assign rd1 = (ra1 != 0) ? rf[ra1] : 0;
	assign rd2 = (ra2 != 0) ? rf[ra2] : 0;
endmodule
module flopr #(parameter WIDTH = 8)(
	input wire clk,rst,
	input wire[WIDTH-1:0] d,
	output reg[WIDTH-1:0] q
    );
	always @(negedge clk,posedge rst) begin
		if(rst) begin
			q <= 0;
		end else begin
			q <= d;
		end
	end
endmodule
module calculate(
    input wire [7:0] num1,
    input wire [2:0] op,
    output [31:0] result
    );
    wire [31:0] num2;
    wire [31:0] Sign_extend;
    
    assign num2 = 32'h00000001;
    assign Sign_extend={{24{1'b0}},num1[7:0]};
    assign result = (op == 3'b000)? Sign_extend + num2:
                    (op == 3'b001)? Sign_extend - num2:
                    (op == 3'b010)? Sign_extend & num2:
                    (op == 3'b011)? Sign_extend | num2:
                    (op == 3'b100)? ~Sign_extend: 32'h00000000;
endmodule
module top(
    input clk,
    input rst,
    input [2:0] op,
    input [7:0] num1,
    output [7:0] ans,
    output [6:0] seg
    );
    wire [31:0] s;
    calculate U1(.num1(num1),.op(op),.result(s));
    
    display U2(.clk(clk),.reset(rst),.s(s),.ans(ans),.seg(seg));
endmodule
module le_tb;
  reg clk;
  reg [31:0] le_a;
  reg [31:0] le_b;
  wire [0:0] le_z;
  integer le_a_file;
  integer le_b_file;
  integer le_z_file;
  integer le_a_count;
  integer le_b_count;
  integer le_z_count;

  le le1 (clk, le_a, le_b, le_z);
  initial
  begin
    le_z_file = $fopen("stim/le_z");
    le_a_file = $fopen("stim/le_a", "r");
    le_b_file = $fopen("stim/le_b", "r");
  end

  initial
  begin
    #50080 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(le_z_file, "%d", le_z);
    #0 le_a_count = $fscanf(le_a_file, "%d\n", le_a);
    #0 le_b_count = $fscanf(le_b_file, "%d\n", le_b);
  end
endmodule
module eq_tb;
  reg clk;
  reg [31:0] eq_a;
  reg [31:0] eq_b;
  wire [0:0] eq_z;
  integer eq_a_file;
  integer eq_b_file;
  integer eq_z_file;
  integer eq_a_count;
  integer eq_b_count;
  integer eq_z_count;

  eq eq1 (clk, eq_a, eq_b, eq_z);
  initial
  begin
    eq_z_file = $fopen("stim/eq_z");
    eq_a_file = $fopen("stim/eq_a", "r");
    eq_b_file = $fopen("stim/eq_b", "r");
  end

  initial
  begin
    #50010 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(eq_z_file, "%d", eq_z);
    #0 eq_a_count = $fscanf(eq_a_file, "%d\n", eq_a);
    #0 eq_b_count = $fscanf(eq_b_file, "%d\n", eq_b);
  end
endmodule
module neg_tb;
  reg clk;
  reg [31:0] neg_a;
  wire [31:0] neg_z;
  integer neg_a_file;
  integer neg_z_file;
  integer neg_a_count;
  integer neg_z_count;

  neg neg1 (clk, neg_a, neg_z);
  initial
  begin
    neg_z_file = $fopen("stim/neg_z");
    neg_a_file = $fopen("stim/neg_a", "r");
  end

  initial
  begin
    #50010 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(neg_z_file, "%d", neg_z);
    #0 neg_a_count = $fscanf(neg_a_file, "%d\n", neg_a);
  end
endmodule
module floor_tb;
  reg clk;
  reg [31:0] floor_a;
  wire [31:0] floor_z;
  integer floor_a_file;
  integer floor_z_file;
  integer floor_a_count;
  integer floor_z_count;

  floor floor1 (clk, floor_a, floor_z);
  initial
  begin
    floor_z_file = $fopen("stim/floor_z");
    floor_a_file = $fopen("stim/floor_a", "r");
  end

  initial
  begin
    #50080 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(floor_z_file, "%d", floor_z);
    #0 floor_a_count = $fscanf(floor_a_file, "%d\n", floor_a);
  end
endmodule
module nearest_tb;
  reg clk;
  reg [31:0] nearest_a;
  wire [31:0] nearest_z;
  integer nearest_a_file;
  integer nearest_z_file;
  integer nearest_a_count;
  integer nearest_z_count;

  nearest nearest1 (clk, nearest_a, nearest_z);
  initial
  begin
    nearest_z_file = $fopen("stim/nearest_z");
    nearest_a_file = $fopen("stim/nearest_a", "r");
  end

  initial
  begin
    #4480 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(nearest_z_file, "%d", nearest_z);
    #0 nearest_a_count = $fscanf(nearest_a_file, "%d\n", nearest_a);
  end
endmodule
module ne_tb;
  reg clk;
  reg [31:0] ne_a;
  reg [31:0] ne_b;
  wire [0:0] ne_z;
  integer ne_a_file;
  integer ne_b_file;
  integer ne_z_file;
  integer ne_a_count;
  integer ne_b_count;
  integer ne_z_count;

  ne ne1 (clk, ne_a, ne_b, ne_z);
  initial
  begin
    ne_z_file = $fopen("stim/ne_z");
    ne_a_file = $fopen("stim/ne_a", "r");
    ne_b_file = $fopen("stim/ne_b", "r");
  end

  initial
  begin
    #50010 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(ne_z_file, "%d", ne_z);
    #0 ne_a_count = $fscanf(ne_a_file, "%d\n", ne_a);
    #0 ne_b_count = $fscanf(ne_b_file, "%d\n", ne_b);
  end
endmodule
module double_add_tb;
  reg clk;
  reg [63:0] double_add_a;
  reg [63:0] double_add_b;
  wire [63:0] double_add_z;
  integer double_add_a_file;
  integer double_add_b_file;
  integer double_add_z_file;
  integer double_add_a_count;
  integer double_add_b_count;
  integer double_add_z_count;

  double_add double_add1 (clk, double_add_a, double_add_b, double_add_z);
  initial
  begin
    double_add_z_file = $fopen("stim/double_add_z");
    double_add_a_file = $fopen("stim/double_add_a", "r");
    double_add_b_file = $fopen("stim/double_add_b", "r");
  end

  initial
  begin
    #10080 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(double_add_z_file, "%d", double_add_z);
    #0 double_add_a_count = $fscanf(double_add_a_file, "%d\n", double_add_a);
    #0 double_add_b_count = $fscanf(double_add_b_file, "%d\n", double_add_b);
  end
endmodule
module lt_tb;
  reg clk;
  reg [31:0] lt_a;
  reg [31:0] lt_b;
  wire [0:0] lt_z;
  integer lt_a_file;
  integer lt_b_file;
  integer lt_z_file;
  integer lt_a_count;
  integer lt_b_count;
  integer lt_z_count;

  lt lt1 (clk, lt_a, lt_b, lt_z);
  initial
  begin
    lt_z_file = $fopen("stim/lt_z");
    lt_a_file = $fopen("stim/lt_a", "r");
    lt_b_file = $fopen("stim/lt_b", "r");
  end

  initial
  begin
    #50080 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(lt_z_file, "%d", lt_z);
    #0 lt_a_count = $fscanf(lt_a_file, "%d\n", lt_a);
    #0 lt_b_count = $fscanf(lt_b_file, "%d\n", lt_b);
  end
endmodule
module double_le_tb;
  reg clk;
  reg [63:0] double_le_a;
  reg [63:0] double_le_b;
  wire [0:0] double_le_z;
  integer double_le_a_file;
  integer double_le_b_file;
  integer double_le_z_file;
  integer double_le_a_count;
  integer double_le_b_count;
  integer double_le_z_count;

  double_le double_le1 (clk, double_le_a, double_le_b, double_le_z);
  initial
  begin
    double_le_z_file = $fopen("stim/double_le_z");
    double_le_a_file = $fopen("stim/double_le_a", "r");
    double_le_b_file = $fopen("stim/double_le_b", "r");
  end

  initial
  begin
    #10080 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(double_le_z_file, "%d", double_le_z);
    #0 double_le_a_count = $fscanf(double_le_a_file, "%d\n", double_le_a);
    #0 double_le_b_count = $fscanf(double_le_b_file, "%d\n", double_le_b);
  end
endmodule
module double_floor_tb;
  reg clk;
  reg [63:0] double_floor_a;
  wire [63:0] double_floor_z;
  integer double_floor_a_file;
  integer double_floor_z_file;
  integer double_floor_a_count;
  integer double_floor_z_count;

  double_floor double_floor1 (clk, double_floor_a, double_floor_z);
  initial
  begin
    double_floor_z_file = $fopen("stim/double_floor_z");
    double_floor_a_file = $fopen("stim/double_floor_a", "r");
  end

  initial
  begin
    #10080 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(double_floor_z_file, "%d", double_floor_z);
    #0 double_floor_a_count = $fscanf(double_floor_a_file, "%d\n", double_floor_a);
  end
endmodule
module unsigned_int_to_double_tb;
  reg clk;
  reg [63:0] unsigned_int_to_double_a;
  wire [63:0] unsigned_int_to_double_z;
  integer unsigned_int_to_double_a_file;
  integer unsigned_int_to_double_z_file;
  integer unsigned_int_to_double_a_count;
  integer unsigned_int_to_double_z_count;

  unsigned_int_to_double unsigned_int_to_double1 (clk, unsigned_int_to_double_a, unsigned_int_to_double_z);
  initial
  begin
    unsigned_int_to_double_z_file = $fopen("stim/unsigned_int_to_double_z");
    unsigned_int_to_double_a_file = $fopen("stim/unsigned_int_to_double_a", "r");
  end

  initial
  begin
    #10060 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(unsigned_int_to_double_z_file, "%d", unsigned_int_to_double_z);
    #0 unsigned_int_to_double_a_count = $fscanf(unsigned_int_to_double_a_file, "%d\n", unsigned_int_to_double_a);
  end
endmodule
module double_ne_tb;
  reg clk;
  reg [63:0] double_ne_a;
  reg [63:0] double_ne_b;
  wire [0:0] double_ne_z;
  integer double_ne_a_file;
  integer double_ne_b_file;
  integer double_ne_z_file;
  integer double_ne_a_count;
  integer double_ne_b_count;
  integer double_ne_z_count;

  double_ne double_ne1 (clk, double_ne_a, double_ne_b, double_ne_z);
  initial
  begin
    double_ne_z_file = $fopen("stim/double_ne_z");
    double_ne_a_file = $fopen("stim/double_ne_a", "r");
    double_ne_b_file = $fopen("stim/double_ne_b", "r");
  end

  initial
  begin
    #10010 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(double_ne_z_file, "%d", double_ne_z);
    #0 double_ne_a_count = $fscanf(double_ne_a_file, "%d\n", double_ne_a);
    #0 double_ne_b_count = $fscanf(double_ne_b_file, "%d\n", double_ne_b);
  end
endmodule
module double_max_tb;
  reg clk;
  reg [63:0] double_max_a;
  reg [63:0] double_max_b;
  wire [63:0] double_max_z;
  integer double_max_a_file;
  integer double_max_b_file;
  integer double_max_z_file;
  integer double_max_a_count;
  integer double_max_b_count;
  integer double_max_z_count;

  double_max double_max1 (clk, double_max_a, double_max_b, double_max_z);
  initial
  begin
    double_max_z_file = $fopen("stim/double_max_z");
    double_max_a_file = $fopen("stim/double_max_a", "r");
    double_max_b_file = $fopen("stim/double_max_b", "r");
  end

  initial
  begin
    #10080 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(double_max_z_file, "%d", double_max_z);
    #0 double_max_a_count = $fscanf(double_max_a_file, "%d\n", double_max_a);
    #0 double_max_b_count = $fscanf(double_max_b_file, "%d\n", double_max_b);
  end
endmodule
module double_gt_tb;
  reg clk;
  reg [63:0] double_gt_a;
  reg [63:0] double_gt_b;
  wire [0:0] double_gt_z;
  integer double_gt_a_file;
  integer double_gt_b_file;
  integer double_gt_z_file;
  integer double_gt_a_count;
  integer double_gt_b_count;
  integer double_gt_z_count;

  double_gt double_gt1 (clk, double_gt_a, double_gt_b, double_gt_z);
  initial
  begin
    double_gt_z_file = $fopen("stim/double_gt_z");
    double_gt_a_file = $fopen("stim/double_gt_a", "r");
    double_gt_b_file = $fopen("stim/double_gt_b", "r");
  end

  initial
  begin
    #10080 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(double_gt_z_file, "%d", double_gt_z);
    #0 double_gt_a_count = $fscanf(double_gt_a_file, "%d\n", double_gt_a);
    #0 double_gt_b_count = $fscanf(double_gt_b_file, "%d\n", double_gt_b);
  end
endmodule
module double_eq_tb;
  reg clk;
  reg [63:0] double_eq_a;
  reg [63:0] double_eq_b;
  wire [0:0] double_eq_z;
  integer double_eq_a_file;
  integer double_eq_b_file;
  integer double_eq_z_file;
  integer double_eq_a_count;
  integer double_eq_b_count;
  integer double_eq_z_count;

  double_eq double_eq1 (clk, double_eq_a, double_eq_b, double_eq_z);
  initial
  begin
    double_eq_z_file = $fopen("stim/double_eq_z");
    double_eq_a_file = $fopen("stim/double_eq_a", "r");
    double_eq_b_file = $fopen("stim/double_eq_b", "r");
  end

  initial
  begin
    #10010 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(double_eq_z_file, "%d", double_eq_z);
    #0 double_eq_a_count = $fscanf(double_eq_a_file, "%d\n", double_eq_a);
    #0 double_eq_b_count = $fscanf(double_eq_b_file, "%d\n", double_eq_b);
  end
endmodule
module int_to_single_tb;
  reg clk;
  reg [31:0] int_to_single_a;
  wire [31:0] int_to_single_z;
  integer int_to_single_a_file;
  integer int_to_single_z_file;
  integer int_to_single_a_count;
  integer int_to_single_z_count;

  int_to_single int_to_single1 (clk, int_to_single_a, int_to_single_z);
  initial
  begin
    int_to_single_z_file = $fopen("stim/int_to_single_z");
    int_to_single_a_file = $fopen("stim/int_to_single_a", "r");
  end

  initial
  begin
    #50060 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(int_to_single_z_file, "%d", int_to_single_z);
    #0 int_to_single_a_count = $fscanf(int_to_single_a_file, "%d\n", int_to_single_a);
  end
endmodule
module double_to_unsigned_int_tb;
  reg clk;
  reg [63:0] double_to_unsigned_int_a;
  wire [63:0] double_to_unsigned_int_z;
  integer double_to_unsigned_int_a_file;
  integer double_to_unsigned_int_z_file;
  integer double_to_unsigned_int_a_count;
  integer double_to_unsigned_int_z_count;

  double_to_unsigned_int double_to_unsigned_int1 (clk, double_to_unsigned_int_a, double_to_unsigned_int_z);
  initial
  begin
    double_to_unsigned_int_z_file = $fopen("stim/double_to_unsigned_int_z");
    double_to_unsigned_int_a_file = $fopen("stim/double_to_unsigned_int_a", "r");
  end

  initial
  begin
    #10020 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(double_to_unsigned_int_z_file, "%d", double_to_unsigned_int_z);
    #0 double_to_unsigned_int_a_count = $fscanf(double_to_unsigned_int_a_file, "%d\n", double_to_unsigned_int_a);
  end
endmodule
module single_to_unsigned_int_tb;
  reg clk;
  reg [31:0] single_to_unsigned_int_a;
  wire [31:0] single_to_unsigned_int_z;
  integer single_to_unsigned_int_a_file;
  integer single_to_unsigned_int_z_file;
  integer single_to_unsigned_int_a_count;
  integer single_to_unsigned_int_z_count;

  single_to_unsigned_int single_to_unsigned_int1 (clk, single_to_unsigned_int_a, single_to_unsigned_int_z);
  initial
  begin
    single_to_unsigned_int_z_file = $fopen("stim/single_to_unsigned_int_z");
    single_to_unsigned_int_a_file = $fopen("stim/single_to_unsigned_int_a", "r");
  end

  initial
  begin
    #50020 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(single_to_unsigned_int_z_file, "%d", single_to_unsigned_int_z);
    #0 single_to_unsigned_int_a_count = $fscanf(single_to_unsigned_int_a_file, "%d\n", single_to_unsigned_int_a);
  end
endmodule
module ge_tb;
  reg clk;
  reg [31:0] ge_a;
  reg [31:0] ge_b;
  wire [0:0] ge_z;
  integer ge_a_file;
  integer ge_b_file;
  integer ge_z_file;
  integer ge_a_count;
  integer ge_b_count;
  integer ge_z_count;

  ge ge1 (clk, ge_a, ge_b, ge_z);
  initial
  begin
    ge_z_file = $fopen("stim/ge_z");
    ge_a_file = $fopen("stim/ge_a", "r");
    ge_b_file = $fopen("stim/ge_b", "r");
  end

  initial
  begin
    #50080 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(ge_z_file, "%d", ge_z);
    #0 ge_a_count = $fscanf(ge_a_file, "%d\n", ge_a);
    #0 ge_b_count = $fscanf(ge_b_file, "%d\n", ge_b);
  end
endmodule
module single_to_int_tb;
  reg clk;
  reg [31:0] single_to_int_a;
  wire [31:0] single_to_int_z;
  integer single_to_int_a_file;
  integer single_to_int_z_file;
  integer single_to_int_a_count;
  integer single_to_int_z_count;

  single_to_int single_to_int1 (clk, single_to_int_a, single_to_int_z);
  initial
  begin
    single_to_int_z_file = $fopen("stim/single_to_int_z");
    single_to_int_a_file = $fopen("stim/single_to_int_a", "r");
  end

  initial
  begin
    #50030 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(single_to_int_z_file, "%d", single_to_int_z);
    #0 single_to_int_a_count = $fscanf(single_to_int_a_file, "%d\n", single_to_int_a);
  end
endmodule
module add_tb;
  reg clk;
  reg [31:0] add_a;
  reg [31:0] add_b;
  wire [31:0] add_z;
  integer add_a_file;
  integer add_b_file;
  integer add_z_file;
  integer add_a_count;
  integer add_b_count;
  integer add_z_count;

  add add1 (clk, add_a, add_b, add_z);
  initial
  begin
    add_z_file = $fopen("stim/add_z");
    add_a_file = $fopen("stim/add_a", "r");
    add_b_file = $fopen("stim/add_b", "r");
  end

  initial
  begin
    #50080 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(add_z_file, "%d", add_z);
    #0 add_a_count = $fscanf(add_a_file, "%d\n", add_a);
    #0 add_b_count = $fscanf(add_b_file, "%d\n", add_b);
  end
endmodule
module double_ge_tb;
  reg clk;
  reg [63:0] double_ge_a;
  reg [63:0] double_ge_b;
  wire [0:0] double_ge_z;
  integer double_ge_a_file;
  integer double_ge_b_file;
  integer double_ge_z_file;
  integer double_ge_a_count;
  integer double_ge_b_count;
  integer double_ge_z_count;

  double_ge double_ge1 (clk, double_ge_a, double_ge_b, double_ge_z);
  initial
  begin
    double_ge_z_file = $fopen("stim/double_ge_z");
    double_ge_a_file = $fopen("stim/double_ge_a", "r");
    double_ge_b_file = $fopen("stim/double_ge_b", "r");
  end

  initial
  begin
    #10080 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(double_ge_z_file, "%d", double_ge_z);
    #0 double_ge_a_count = $fscanf(double_ge_a_file, "%d\n", double_ge_a);
    #0 double_ge_b_count = $fscanf(double_ge_b_file, "%d\n", double_ge_b);
  end
endmodule
module unsigned_int_to_single_tb;
  reg clk;
  reg [31:0] unsigned_int_to_single_a;
  wire [31:0] unsigned_int_to_single_z;
  integer unsigned_int_to_single_a_file;
  integer unsigned_int_to_single_z_file;
  integer unsigned_int_to_single_a_count;
  integer unsigned_int_to_single_z_count;

  unsigned_int_to_single unsigned_int_to_single1 (clk, unsigned_int_to_single_a, unsigned_int_to_single_z);
  initial
  begin
    unsigned_int_to_single_z_file = $fopen("stim/unsigned_int_to_single_z");
    unsigned_int_to_single_a_file = $fopen("stim/unsigned_int_to_single_a", "r");
  end

  initial
  begin
    #50060 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(unsigned_int_to_single_z_file, "%d", unsigned_int_to_single_z);
    #0 unsigned_int_to_single_a_count = $fscanf(unsigned_int_to_single_a_file, "%d\n", unsigned_int_to_single_a);
  end
endmodule
module single_max_tb;
  reg clk;
  reg [31:0] single_max_a;
  reg [31:0] single_max_b;
  wire [31:0] single_max_z;
  integer single_max_a_file;
  integer single_max_b_file;
  integer single_max_z_file;
  integer single_max_a_count;
  integer single_max_b_count;
  integer single_max_z_count;

  single_max single_max1 (clk, single_max_a, single_max_b, single_max_z);
  initial
  begin
    single_max_z_file = $fopen("stim/single_max_z");
    single_max_a_file = $fopen("stim/single_max_a", "r");
    single_max_b_file = $fopen("stim/single_max_b", "r");
  end

  initial
  begin
    #50080 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(single_max_z_file, "%d", single_max_z);
    #0 single_max_a_count = $fscanf(single_max_a_file, "%d\n", single_max_a);
    #0 single_max_b_count = $fscanf(single_max_b_file, "%d\n", single_max_b);
  end
endmodule
module trunc_tb;
  reg clk;
  reg [31:0] trunc_a;
  wire [31:0] trunc_z;
  integer trunc_a_file;
  integer trunc_z_file;
  integer trunc_a_count;
  integer trunc_z_count;

  trunc trunc1 (clk, trunc_a, trunc_z);
  initial
  begin
    trunc_z_file = $fopen("stim/trunc_z");
    trunc_a_file = $fopen("stim/trunc_a", "r");
  end

  initial
  begin
    #50010 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(trunc_z_file, "%d", trunc_z);
    #0 trunc_a_count = $fscanf(trunc_a_file, "%d\n", trunc_a);
  end
endmodule
module abs_tb;
  reg clk;
  reg [31:0] abs_a;
  wire [31:0] abs_z;
  integer abs_a_file;
  integer abs_z_file;
  integer abs_a_count;
  integer abs_z_count;

  abs abs1 (clk, abs_a, abs_z);
  initial
  begin
    abs_z_file = $fopen("stim/abs_z");
    abs_a_file = $fopen("stim/abs_a", "r");
  end

  initial
  begin
    #50010 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(abs_z_file, "%d", abs_z);
    #0 abs_a_count = $fscanf(abs_a_file, "%d\n", abs_a);
  end
endmodule
module dq (clk, q, d);
  input  clk;
  input  [width-1:0] d;
  output [width-1:0] q;
  parameter width=8;
  parameter depth=2;
  integer i;
  reg [width-1:0] delay_line [depth-1:0];
  always @(posedge clk) begin
    delay_line[0] <= d;
    for(i=1; i<depth; i=i+1) begin
      delay_line[i] <= delay_line[i-1];
    end
  end
  assign q = delay_line[depth-1];
endmodule
module double_trunc_tb;
  reg clk;
  reg [63:0] double_trunc_a;
  wire [63:0] double_trunc_z;
  integer double_trunc_a_file;
  integer double_trunc_z_file;
  integer double_trunc_a_count;
  integer double_trunc_z_count;

  double_trunc double_trunc1 (clk, double_trunc_a, double_trunc_z);
  initial
  begin
    double_trunc_z_file = $fopen("stim/double_trunc_z");
    double_trunc_a_file = $fopen("stim/double_trunc_a", "r");
  end

  initial
  begin
    #10010 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(double_trunc_z_file, "%d", double_trunc_z);
    #0 double_trunc_a_count = $fscanf(double_trunc_a_file, "%d\n", double_trunc_a);
  end
endmodule
module double_lt_tb;
  reg clk;
  reg [63:0] double_lt_a;
  reg [63:0] double_lt_b;
  wire [0:0] double_lt_z;
  integer double_lt_a_file;
  integer double_lt_b_file;
  integer double_lt_z_file;
  integer double_lt_a_count;
  integer double_lt_b_count;
  integer double_lt_z_count;

  double_lt double_lt1 (clk, double_lt_a, double_lt_b, double_lt_z);
  initial
  begin
    double_lt_z_file = $fopen("stim/double_lt_z");
    double_lt_a_file = $fopen("stim/double_lt_a", "r");
    double_lt_b_file = $fopen("stim/double_lt_b", "r");
  end

  initial
  begin
    #10080 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(double_lt_z_file, "%d", double_lt_z);
    #0 double_lt_a_count = $fscanf(double_lt_a_file, "%d\n", double_lt_a);
    #0 double_lt_b_count = $fscanf(double_lt_b_file, "%d\n", double_lt_b);
  end
endmodule
module double_to_int_tb;
  reg clk;
  reg [63:0] double_to_int_a;
  wire [63:0] double_to_int_z;
  integer double_to_int_a_file;
  integer double_to_int_z_file;
  integer double_to_int_a_count;
  integer double_to_int_z_count;

  double_to_int double_to_int1 (clk, double_to_int_a, double_to_int_z);
  initial
  begin
    double_to_int_z_file = $fopen("stim/double_to_int_z");
    double_to_int_a_file = $fopen("stim/double_to_int_a", "r");
  end

  initial
  begin
    #10030 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(double_to_int_z_file, "%d", double_to_int_z);
    #0 double_to_int_a_count = $fscanf(double_to_int_a_file, "%d\n", double_to_int_a);
  end
endmodule
module div_tb;
  reg clk;
  reg [31:0] div_a;
  reg [31:0] div_b;
  wire [31:0] div_z;
  integer div_a_file;
  integer div_b_file;
  integer div_z_file;
  integer div_a_count;
  integer div_b_count;
  integer div_z_count;

  div div1 (clk, div_a, div_b, div_z);
  initial
  begin
    div_z_file = $fopen("stim/div_z");
    div_a_file = $fopen("stim/div_a", "r");
    div_b_file = $fopen("stim/div_b", "r");
  end

  initial
  begin
    #50370 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(div_z_file, "%d", div_z);
    #0 div_a_count = $fscanf(div_a_file, "%d\n", div_a);
    #0 div_b_count = $fscanf(div_b_file, "%d\n", div_b);
  end
endmodule
module double_sqrt_tb;
  reg clk;
  reg [63:0] double_sqrt_a;
  wire [63:0] double_sqrt_z;
  integer double_sqrt_a_file;
  integer double_sqrt_z_file;
  integer double_sqrt_a_count;
  integer double_sqrt_z_count;

  double_sqrt double_sqrt1 (clk, double_sqrt_a, double_sqrt_z);
  initial
  begin
    double_sqrt_z_file = $fopen("stim/double_sqrt_z");
    double_sqrt_a_file = $fopen("stim/double_sqrt_a", "r");
  end

  initial
  begin
    #10110 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(double_sqrt_z_file, "%d", double_sqrt_z);
    #0 double_sqrt_a_count = $fscanf(double_sqrt_a_file, "%d\n", double_sqrt_a);
  end
endmodule
module single_min_tb;
  reg clk;
  reg [31:0] single_min_a;
  reg [31:0] single_min_b;
  wire [31:0] single_min_z;
  integer single_min_a_file;
  integer single_min_b_file;
  integer single_min_z_file;
  integer single_min_a_count;
  integer single_min_b_count;
  integer single_min_z_count;

  single_min single_min1 (clk, single_min_a, single_min_b, single_min_z);
  initial
  begin
    single_min_z_file = $fopen("stim/single_min_z");
    single_min_a_file = $fopen("stim/single_min_a", "r");
    single_min_b_file = $fopen("stim/single_min_b", "r");
  end

  initial
  begin
    #50080 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(single_min_z_file, "%d", single_min_z);
    #0 single_min_a_count = $fscanf(single_min_a_file, "%d\n", single_min_a);
    #0 single_min_b_count = $fscanf(single_min_b_file, "%d\n", single_min_b);
  end
endmodule
module ceil_tb;
  reg clk;
  reg [31:0] ceil_a;
  wire [31:0] ceil_z;
  integer ceil_a_file;
  integer ceil_z_file;
  integer ceil_a_count;
  integer ceil_z_count;

  ceil ceil1 (clk, ceil_a, ceil_z);
  initial
  begin
    ceil_z_file = $fopen("stim/ceil_z");
    ceil_a_file = $fopen("stim/ceil_a", "r");
  end

  initial
  begin
    #50080 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(ceil_z_file, "%d", ceil_z);
    #0 ceil_a_count = $fscanf(ceil_a_file, "%d\n", ceil_a);
  end
endmodule
module double_abs_tb;
  reg clk;
  reg [63:0] double_abs_a;
  wire [63:0] double_abs_z;
  integer double_abs_a_file;
  integer double_abs_z_file;
  integer double_abs_a_count;
  integer double_abs_z_count;

  double_abs double_abs1 (clk, double_abs_a, double_abs_z);
  initial
  begin
    double_abs_z_file = $fopen("stim/double_abs_z");
    double_abs_a_file = $fopen("stim/double_abs_a", "r");
  end

  initial
  begin
    #10010 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(double_abs_z_file, "%d", double_abs_z);
    #0 double_abs_a_count = $fscanf(double_abs_a_file, "%d\n", double_abs_a);
  end
endmodule
module double_mul_tb;
  reg clk;
  reg [63:0] double_mul_a;
  reg [63:0] double_mul_b;
  wire [63:0] double_mul_z;
  integer double_mul_a_file;
  integer double_mul_b_file;
  integer double_mul_z_file;
  integer double_mul_a_count;
  integer double_mul_b_count;
  integer double_mul_z_count;

  double_mul double_mul1 (clk, double_mul_a, double_mul_b, double_mul_z);
  initial
  begin
    double_mul_z_file = $fopen("stim/double_mul_z");
    double_mul_a_file = $fopen("stim/double_mul_a", "r");
    double_mul_b_file = $fopen("stim/double_mul_b", "r");
  end

  initial
  begin
    #10220 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(double_mul_z_file, "%d", double_mul_z);
    #0 double_mul_a_count = $fscanf(double_mul_a_file, "%d\n", double_mul_a);
    #0 double_mul_b_count = $fscanf(double_mul_b_file, "%d\n", double_mul_b);
  end
endmodule
module int_to_double_tb;
  reg clk;
  reg [63:0] int_to_double_a;
  wire [63:0] int_to_double_z;
  integer int_to_double_a_file;
  integer int_to_double_z_file;
  integer int_to_double_a_count;
  integer int_to_double_z_count;

  int_to_double int_to_double1 (clk, int_to_double_a, int_to_double_z);
  initial
  begin
    int_to_double_z_file = $fopen("stim/int_to_double_z");
    int_to_double_a_file = $fopen("stim/int_to_double_a", "r");
  end

  initial
  begin
    #10060 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(int_to_double_z_file, "%d", int_to_double_z);
    #0 int_to_double_a_count = $fscanf(int_to_double_a_file, "%d\n", int_to_double_a);
  end
endmodule
module mul_tb;
  reg clk;
  reg [31:0] mul_a;
  reg [31:0] mul_b;
  wire [31:0] mul_z;
  integer mul_a_file;
  integer mul_b_file;
  integer mul_z_file;
  integer mul_a_count;
  integer mul_b_count;
  integer mul_z_count;

  mul mul1 (clk, mul_a, mul_b, mul_z);
  initial
  begin
    mul_z_file = $fopen("stim/mul_z");
    mul_a_file = $fopen("stim/mul_a", "r");
    mul_b_file = $fopen("stim/mul_b", "r");
  end

  initial
  begin
    #50100 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(mul_z_file, "%d", mul_z);
    #0 mul_a_count = $fscanf(mul_a_file, "%d\n", mul_a);
    #0 mul_b_count = $fscanf(mul_b_file, "%d\n", mul_b);
  end
endmodule
module double_neg_tb;
  reg clk;
  reg [63:0] double_neg_a;
  wire [63:0] double_neg_z;
  integer double_neg_a_file;
  integer double_neg_z_file;
  integer double_neg_a_count;
  integer double_neg_z_count;

  double_neg double_neg1 (clk, double_neg_a, double_neg_z);
  initial
  begin
    double_neg_z_file = $fopen("stim/double_neg_z");
    double_neg_a_file = $fopen("stim/double_neg_a", "r");
  end

  initial
  begin
    #10010 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(double_neg_z_file, "%d", double_neg_z);
    #0 double_neg_a_count = $fscanf(double_neg_a_file, "%d\n", double_neg_a);
  end
endmodule
module double_ceil_tb;
  reg clk;
  reg [63:0] double_ceil_a;
  wire [63:0] double_ceil_z;
  integer double_ceil_a_file;
  integer double_ceil_z_file;
  integer double_ceil_a_count;
  integer double_ceil_z_count;

  double_ceil double_ceil1 (clk, double_ceil_a, double_ceil_z);
  initial
  begin
    double_ceil_z_file = $fopen("stim/double_ceil_z");
    double_ceil_a_file = $fopen("stim/double_ceil_a", "r");
  end

  initial
  begin
    #10080 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(double_ceil_z_file, "%d", double_ceil_z);
    #0 double_ceil_a_count = $fscanf(double_ceil_a_file, "%d\n", double_ceil_a);
  end
endmodule
module double_min_tb;
  reg clk;
  reg [63:0] double_min_a;
  reg [63:0] double_min_b;
  wire [63:0] double_min_z;
  integer double_min_a_file;
  integer double_min_b_file;
  integer double_min_z_file;
  integer double_min_a_count;
  integer double_min_b_count;
  integer double_min_z_count;

  double_min double_min1 (clk, double_min_a, double_min_b, double_min_z);
  initial
  begin
    double_min_z_file = $fopen("stim/double_min_z");
    double_min_a_file = $fopen("stim/double_min_a", "r");
    double_min_b_file = $fopen("stim/double_min_b", "r");
  end

  initial
  begin
    #10080 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(double_min_z_file, "%d", double_min_z);
    #0 double_min_a_count = $fscanf(double_min_a_file, "%d\n", double_min_a);
    #0 double_min_b_count = $fscanf(double_min_b_file, "%d\n", double_min_b);
  end
endmodule
module gt_tb;
  reg clk;
  reg [31:0] gt_a;
  reg [31:0] gt_b;
  wire [0:0] gt_z;
  integer gt_a_file;
  integer gt_b_file;
  integer gt_z_file;
  integer gt_a_count;
  integer gt_b_count;
  integer gt_z_count;

  gt gt1 (clk, gt_a, gt_b, gt_z);
  initial
  begin
    gt_z_file = $fopen("stim/gt_z");
    gt_a_file = $fopen("stim/gt_a", "r");
    gt_b_file = $fopen("stim/gt_b", "r");
  end

  initial
  begin
    #50080 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(gt_z_file, "%d", gt_z);
    #0 gt_a_count = $fscanf(gt_a_file, "%d\n", gt_a);
    #0 gt_b_count = $fscanf(gt_b_file, "%d\n", gt_b);
  end
endmodule
module double_div_tb;
  reg clk;
  reg [63:0] double_div_a;
  reg [63:0] double_div_b;
  wire [63:0] double_div_z;
  integer double_div_a_file;
  integer double_div_b_file;
  integer double_div_z_file;
  integer double_div_a_count;
  integer double_div_b_count;
  integer double_div_z_count;

  double_div double_div1 (clk, double_div_a, double_div_b, double_div_z);
  initial
  begin
    double_div_z_file = $fopen("stim/double_div_z");
    double_div_a_file = $fopen("stim/double_div_a", "r");
    double_div_b_file = $fopen("stim/double_div_b", "r");
  end

  initial
  begin
    #10660 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(double_div_z_file, "%d", double_div_z);
    #0 double_div_a_count = $fscanf(double_div_a_file, "%d\n", double_div_a);
    #0 double_div_b_count = $fscanf(double_div_b_file, "%d\n", double_div_b);
  end
endmodule
module sqrt_tb;
  reg clk;
  reg [31:0] sqrt_a;
  wire [31:0] sqrt_z;
  integer sqrt_a_file;
  integer sqrt_z_file;
  integer sqrt_a_count;
  integer sqrt_z_count;

  sqrt sqrt1 (clk, sqrt_a, sqrt_z);
  initial
  begin
    sqrt_z_file = $fopen("stim/sqrt_z");
    sqrt_a_file = $fopen("stim/sqrt_a", "r");
  end

  initial
  begin
    #50110 $finish;
  end

  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  always @ (posedge clk)
  begin
    $fdisplay(sqrt_z_file, "%d", sqrt_z);
    #0 sqrt_a_count = $fscanf(sqrt_a_file, "%d\n", sqrt_a);
  end
endmodule
module to_int(clk, to_int_a, to_int_z);
  input clk;
  input [31:0] to_int_a;
  output [31:0] to_int_z;
  wire [31:0] s_0;
  wire [31:0] s_1;
  wire [31:0] s_2;
  wire [31:0] s_3;
  wire [31:0] s_4;
  wire [31:0] s_5;
  wire [31:0] s_6;
  wire [31:0] s_7;
  wire [31:0] s_8;
  wire [31:0] s_9;
  wire [23:0] s_10;
  wire [0:0] s_11;
  wire [0:0] s_12;
  wire [0:0] s_13;
  wire [0:0] s_14;
  wire [7:0] s_15;
  wire [7:0] s_16;
  wire [31:0] s_17;
  wire [6:0] s_18;
  wire [7:0] s_19;
  wire [22:0] s_20;
  wire [7:0] s_21;
  wire [7:0] s_22;
  wire [7:0] s_23;
  wire [7:0] s_24;
  wire [7:0] s_25;
  wire [7:0] s_26;
  wire [0:0] s_27;
  wire [31:0] s_28;
  wire [0:0] s_29;
  wire [0:0] s_30;
  wire [0:0] s_31;
  wire [0:0] s_32;
  wire [0:0] s_33;
  wire [0:0] s_34;
  wire [0:0] s_35;
  wire [0:0] s_36;
  wire [0:0] s_37;
  wire [0:0] s_38;
  wire [0:0] s_39;
  wire [0:0] s_40;
  wire [7:0] s_41;
  wire [0:0] s_42;
  wire [0:0] s_43;
  wire [7:0] s_44;
  wire [0:0] s_45;
  wire [22:0] s_46;
  wire [0:0] s_47;
  wire [0:0] s_48;
  wire [7:0] s_49;
  wire [0:0] s_50;
  wire [22:0] s_51;

  assign s_0 = s_37?s_1:s_2;
  assign s_1 = 32'd2147483648;
  assign s_2 = s_31?s_3:s_4;
  assign s_3 = 32'd0;
  assign s_4 = s_29?s_5:s_28;
  dq #(32, 1) dq_s_5 (clk, s_5, s_6);
  assign s_6 = -s_7;
  dq #(32, 1) dq_s_7 (clk, s_7, s_8);
  assign s_8 = s_9 >> s_22;
  assign s_9 = {s_10,s_21};
  assign s_10 = {s_11,s_20};
  assign s_11 = s_14?s_12:s_13;
  assign s_12 = 1'd0;
  assign s_13 = 1'd1;
  assign s_14 = s_15 == s_19;
  assign s_15 = s_16 - s_18;
  assign s_16 = s_17[30:23];
  assign s_17 = to_int_a;
  assign s_18 = 7'd127;
  assign s_19 = -8'd127;
  assign s_20 = s_17[22:0];
  assign s_21 = 8'd0;
  assign s_22 = s_23 - s_27;
  assign s_23 = s_24 - s_25;
  assign s_24 = 8'd32;
  assign s_25 = s_14?s_26:s_15;
  assign s_26 = -8'd126;
  assign s_27 = 1'd1;
  dq #(32, 1) dq_s_28 (clk, s_28, s_7);
  dq #(1, 2) dq_s_29 (clk, s_29, s_30);
  assign s_30 = s_17[31];
  dq #(1, 2) dq_s_31 (clk, s_31, s_32);
  assign s_32 = s_33 | s_35;
  assign s_33 = $signed(s_25) < $signed(s_34);
  assign s_34 = 1'd0;
  assign s_35 = s_10 == s_36;
  assign s_36 = 1'd0;
  dq #(1, 2) dq_s_37 (clk, s_37, s_38);
  assign s_38 = s_39 | s_47;
  assign s_39 = s_40 | s_42;
  assign s_40 = $signed(s_25) >= $signed(s_41);
  assign s_41 = 8'd31;
  assign s_42 = s_43 & s_45;
  assign s_43 = s_15 == s_44;
  assign s_44 = 8'd128;
  assign s_45 = s_20 == s_46;
  assign s_46 = 23'd0;
  assign s_47 = s_48 & s_50;
  assign s_48 = s_15 == s_49;
  assign s_49 = 8'd128;
  assign s_50 = s_20 != s_51;
  assign s_51 = 23'd0;
  assign to_int_z = s_0;
endmodule
module dff(input clk, input d, output reg q);
always@ (posedge clk)
q <= d;
endmodule
module OPENROAD_CLKGATE (CK, E, GCK);
  input CK;
  input E;
  output GCK;

`ifdef OPENROAD_CLKGATE

sky130_fd_sc_hd__dlclkp_1 latch (.CLK (CK), .GATE(E), .GCLK(GCK));

`else

assign GCK = CK;

`endif

endmodule
module AND2_HPNW4 (Y, A, B);
	output Y;
	input A, B;

	// Function
	buf (Y, 1'b0);

	// Timing
	specify
		(A => Y) = 0;
		(B => Y) = 0;
	endspecify
endmodule