dakies/OSS_Verilog huggingface dataset:
module q7segIO(
        input [31:0] addr,
        inout [31:0] data,
        input wr,
        input clk
    );
    
reg data_out;
reg [3:0] DCBA0;
reg [3:0] DCBA1;
reg [3:0] DCBA2;
reg [3:0] DCBA3;
reg [3:0] swA;
reg [3:0] swB;
reg [3:0] swOP;

wire seg,dp,an0,an1,an2,an3,num0,num1,num2,num3;

//buffer high impedance
assign data = (wr == 0) ? data_out :32'bz;

//q7seg component
quad7seg q7seg(seg,dp,an0,an1,an2,an3,num0,num1,num2,num3,clk);
 
always @(posedge clk)
begin
    //write
    if(wr) 
        begin
        //map six address
            if(addr == 32'h0000FFF0) begin
                DCBA0 = data;
            end
            else if (addr == 32'h0000FFF4) begin
                DCBA1 = data;
            end
            else if (addr == 32'h0000FFF8) begin
                DCBA2 = data;
            end
            else if (addr == 32'h0000FFFC) begin
                DCBA3 = data;
            end
            else if (addr == 32'h0000FFE0) begin
                swA = data;
            end
            else if (addr == 32'h0000FFE4) begin
                swB = data;
            end
            else if (addr == 32'h0000FFE8) begin
                swOP = data;
            end
        end
    //read
    else if (!wr) 
        begin
        //map six address
            if(addr == 32'h0000FFF0) begin
                data_out = DCBA0;
            end
            else if (addr == 32'h0000FFF4) begin
                data_out = DCBA1;
            end
            else if (addr == 32'h0000FFF8) begin
                data_out = DCBA2;
            end
            else if (addr == 32'h0000FFFC) begin
                data_out = DCBA3;
            end
            else if (addr == 32'h0000FFE0) begin
                data_out = swA;
            end
            else if (addr == 32'h0000FFE4) begin
                data_out = swB;
            end
            else if (addr == 32'h0000FFE8) begin
                data_out = swOP;
            end
        end
end

endmodule
module mockIO(
        output seg,
        output dp,
        output an,
        input wr,
        input clock,
        input [15:0] address,
        inout [31:0] data,
        input [11:0] sw
    );

reg [3:0] DCBA0,DCBA1,DCBA2,DCBA3;
wire [3:0] A,B,OP;
wire [18:0] tclk;
wire targetClk;
wire num0,num1,num2,num3;

reg	[31:0]	data_out;
// Tri-State buffer
assign data=(wr==0) ? data_out:32'bz;

assign tclk[0] = clock;
genvar c;
generate for(c=0;c<18;c=c+1)
begin
    clockDiv fdiv(tclk[c+1],tclk[c]);
end endgenerate
clockDiv fdivTarget(targetClk,tclk[18]);

assign num0 = DCBA0;
assign num1 = DCBA1;
assign num2 = DCBA2;
assign num3 = DCBA3;
assign an = {an3,an2,an1,an0};

quadSevenSeg q7seg(seg,dp,an0,an1,an2,an3,num0,num1,num2,num3,targetClk);

assign A = sw[3:0];
assign B = sw[7:4];
assign OP = sw[11:8];

//decode address 
always @(posedge clock)
begin
    if(wr)
        begin
            if(address == 16'hFFF0) begin 
                DCBA0 = data[3:0];
            end
            else if (address == 16'hFFF4) begin
                DCBA1 = data[3:0];
            end
            else if (address == 16'hFFF8) begin
                DCBA2 = data[3:0];
            end
            else if (address == 16'hFFFC) begin
                DCBA3 = data[3:0];
            end
//            else if (address == 16'hFFE0) begin
//                A = data[3:0];
//            end
//            else if (address == 16'hFFE4) begin
//            end
//            else if (address == 16'hFFE8) begin
//            end
        end
    else if(!wr) 
        begin
            if(address == 16'hFFF0) begin 
                data_out = {28'b0,DCBA0};
            end
            else if (address == 16'hFFF4) begin
                data_out = {28'b0,DCBA1};
            end
            else if (address == 16'hFFF8) begin
                data_out = {28'b0,DCBA2};
            end
            else if (address == 16'hFFFC) begin
                data_out = {28'b0,DCBA3};
            end
            else if (address == 16'hFFE0) begin
                data_out = {28'b0,A};
            end
            else if (address == 16'hFFE4) begin
                data_out = {28'b0,B};
            end
            else if (address == 16'hFFE8) begin
                data_out = {28'b0,OP};
            end
        end
end

    
endmodule
module alu_test();
    wire [31:0] S;
    wire z, Cout;
    reg [31:0] A, B;
    reg Cin;
    reg [2:0] alu_ops;
    
    alu alu(S, z, Cout, A, B, Cin, alu_ops);
    
    initial
    begin
        #0  Cin = 0;
            A = 6;
            B = 5;
            alu_ops = 0;
        
        #20 alu_ops = 1;
        #20 alu_ops = 2;
        #20 alu_ops = 3;
        #20 alu_ops = 4;
        #20 alu_ops = 5;
        #20 alu_ops = 6;
        #20 alu_ops = 7;
        #20 $finish;
    end
endmodule
module adder(S,Cout,A,B,Cin);
parameter WIDTH=31;
output	[WIDTH-1:0]	S;
output				Cout;
input	[WIDTH-1:0]	A;
input	[WIDTH-1:0]	B;
input				Cin;

assign {Cout,S}=A+B+Cin;

endmodule
module extender(data32, data16,ext_ops);
output reg [31:0] data32;
input [15:0] data16;
input [1:0] ext_ops;
    
always@(ext_ops or data16)
begin
    case(ext_ops)
    2'b01: data32 = {{16{data16[15]}},data16};
    2'b10: data32 = {data16,{16{1'b0}}};
    default: data32 = {{16{1'b0}},data16};
    endcase
end
endmodule
module control(	
	sel_pc,
	sel_addpc,
	sel_wr,
	sel_b,
	sel_data,
	reg_wr,
	mem_wr,
	ext_ops,
	alu_ops,
	opcode,
	z_flag,
	reserved
	);
output reg sel_pc;
output reg sel_addpc;
output reg sel_wr;
output reg sel_b;
output reg sel_data;
output reg reg_wr;
output reg mem_wr;
output reg [1:0] ext_ops;
output reg [2:0] alu_ops;
input [5:0] opcode;
input z_flag;
input [2:0] reserved; 

localparam ORI=6'b010000;
localparam ORUI=6'b010001;
/*Change ADD to RTYPE*/
localparam RTYPE=6'b000001;
localparam LW=6'b011000;
localparam SW=6'b011100;
localparam BEQ=6'b100100;
localparam JMP=6'b110000;

// sel_pc
always @(opcode)
begin
	case (opcode)
		JMP : sel_pc=1;
		default : sel_pc=0;
	endcase
end

// sel_addpc
always @(opcode or z_flag)
begin
	case (opcode)
		BEQ : sel_addpc=z_flag;
		default : sel_addpc=0;
	endcase
end

// sel_wr
always @(opcode)
begin
	case (opcode)
		ORI : sel_wr=1;
		ORUI : sel_wr=1;
		LW : sel_wr=1;
		default : sel_wr=0;
	endcase
end

// sel_b
always @(opcode)
begin
	case (opcode)
		ORI : sel_b=1;
		ORUI : sel_b=1;
		LW : sel_b=1;
		SW : sel_b=1;
		default : sel_b=0;
	endcase
end

// sel_data
always @(opcode)
begin
	case (opcode)
		LW : sel_data=1;
		default : sel_data=0;
	endcase
end

// reg_wr
always @(opcode)
begin
	case (opcode)
		ORI : reg_wr=1;
		ORUI : reg_wr=1;
		RTYPE : reg_wr=1;
		LW : reg_wr=1;
		default : reg_wr=0;
	endcase
end

// mem_wr
always @(opcode)
begin
	case (opcode)
		SW : mem_wr=1;
		default : mem_wr=0;
	endcase
end

// ext_ops
always @(opcode)
begin
	case (opcode)
		ORUI : ext_ops=2'b10;
		LW : ext_ops=2'b01;
		SW : ext_ops=2'b01;
		BEQ : ext_ops=2'b01;
		default : ext_ops=2'b00;
	endcase
end

// alu_ops
//add reserved to always -> must detect change in Reserved bit too in order for R-type to work
always @(opcode && reserved)
begin
	case (opcode)
		ORI : alu_ops=3'b010;
		ORUI : alu_ops=3'b010;
		BEQ : alu_ops=3'b001;
		/*RTYPE sens alu_ops accoring to reserved last three bit*/
		RTYPE : alu_ops= reserved;
		default : alu_ops=3'b000;
	endcase
end

endmodule
module mux2_1(out,in0,in1,sel);
parameter WIDTH=32;
output	[WIDTH-1:0]	out;
input	[WIDTH-1:0]	in0;
input	[WIDTH-1:0]	in1;
input				sel;

assign out=sel?in1:in0;

endmodule
module nano_sc_system(
    output wire [6:0]seg,
    output [3:0] an,
    output dp,
    input clk,
    input [11:0] sw
);

wire 	[31:0]	p_address;
wire 	[31:0]	p_data;
wire	[31:0]	d_address;
wire	[31:0]	d_data;
wire mem_wr;
reg nreset = 1;

nanocpu	CPU(p_address, p_data, d_address, d_data, mem_wr, clk, nreset);
rom 	PROGMEM(p_data, p_address[17:2]);
memory 	DATAMEM(d_data, d_address[15:0], mem_wr, clk, sw, seg, an, dp);

endmodule
module rom(data, address);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;

output	[DATA_WIDTH - 1:0]	data;
input	[ADDR_WIDTH - 1:0]	address;

reg	[DATA_WIDTH - 1:0]	mem[0:1 << ADDR_WIDTH];

assign data = mem[address];

initial begin
	$readmemb("prog.list", mem);
end

endmodule
module memory(data, address, wr, clock, sw, seg, an, dp);

parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;

inout [DATA_WIDTH-1:0] data;
input [ADDR_WIDTH-1:0] address;
input wr;
input clock;
input [11:0] sw;
output [6:0] seg;
output [3:0] an;
output dp;

reg [3:0] num0, num1, num2, num3;
wire dp, an0, an1, an2, an3;

//take only 4bit for synthesis
reg	[4:0]	mem[0:1<<ADDR_WIDTH - 1];
reg	[DATA_WIDTH - 1:0]	data_out;

// Tri-State buffer
assign data = (wr == 0) ? data_out : 32'bz;

// ----------------------------------------------------------------------

wire targetClk;
wire [18:0] tclk;
assign tclk[0] = clock;
genvar c;
generate for(c = 0; c < 18; c = c + 1) begin
    clockDiv fdiv(tclk[c+1], tclk[c]);
end endgenerate
clockDiv fdivTarget(targetClk, tclk[18]);

quadSevenSeg quad7seg(seg, dp, an, num0, num1, num2, num3, targetClk);

// ----------------------------------------------------------------------

generate
    begin: init_bram_to_zero
        integer ram_index;
        initial
        for (ram_index = 0; ram_index < ADDR_WIDTH; ram_index = ram_index + 1)
            mem[ram_index] = 0;
    end
endgenerate


always @(address)
begin
    case (address)
        16'hFFF0 : data_out = num0;
        16'hFFF4 : data_out = num1;
        16'hFFF8 : data_out = num2;
        16'hFFFC : data_out = num3;
        16'hFFE0 : data_out = sw[3:0];
        16'hFFE4 : data_out = sw[7:4];
        16'hFFE8 : data_out = sw[11:8];
        default : data_out = mem[address];        
    endcase
end


always @(posedge clock)
begin : MEM_WRITE
    if (wr) begin
	   case (address)
	       16'hFFF0 : num0 = data;
	       16'hFFF4 : num1 = data;
	       16'hFFF8 : num2 = data;
	       16'hFFFC : num3 = data[7:4];
	       default : mem[address] = data;
		endcase
	end
end

endmodule
module regfile(A, B, data, ra, rb, rw, nwr, clock);
output	[31:0]	A;
output	[31:0]	B;
input 	[31:0]	data;
input 	[4:0]	ra, rb, rw;
input			nwr;
input			clock;

reg		[31:0] regs[31:0];

assign A = regs[ra];
assign B = regs[rb];

integer i;

// register are all zero at the start
initial
begin
	for(i=0;i<32;i=i+1)
	begin
		regs[i]=0;
	end
end

always @(posedge clock)
begin
	$display("%10d - A(REG[%d]) -  %h, B(REG[%d]) -  %h\n",$time, ra,A,rb,B);
	if (nwr==0) 
	begin
		regs[rw] = data;
		$display("%10d - REG[%d] <- %h",$time, rw, data);
	end		
end

endmodule
module nanocpu(p_address,p_data,d_address,d_data,mem_wr,clock,nreset);
output 	[31:0]	p_address;
input 	[31:0]	p_data;
output	[31:0]	d_address;
output			mem_wr;
inout	[31:0]	d_data;
input			clock;
input			nreset;

wire	[31:0]	instruction;
// instruction fields
wire	[5:0]	opcode;
wire	[4:0]	rs;
wire	[4:0]	rt;
wire	[4:0]	rd;
wire	[10:0]	reserved;
wire	[15:0]	imm;
wire	[25:0]	addr;
assign {opcode,rs,rt,rd,reserved} = instruction;
assign imm=instruction[15:0];
assign addr=instruction[25:0];

reg	[31:0]	pc = 32'b0;

wire		sel_addpc;
wire		sel_pc;
wire 	[29:0] 	pc_add;
wire		pc_cout;
wire	[29:0] 	pc_add_b;
wire	[29:0]	addr_zeroext;
wire	[29:0]	pc_new;

assign p_address=pc;
assign instruction=p_data;
assign addr_zeroext={{4{1'b0}},addr};

adder	#(.WIDTH(30)) PCADDER(pc_add,pc_cout,pc[31:2],pc_add_b,1'b1);
mux2_1	#(.WIDTH(30)) MUXADDPC(pc_add_b,{30{1'b0}},imm_ext[29:0],sel_addpc);
mux2_1	#(.WIDTH(30)) MUXSELPC(pc_new,pc_add,addr_zeroext,sel_pc);

// PC register
always @(posedge clock)
begin
	if (nreset==0)
	begin
		pc=0;
	end
	else 
	begin
		pc={pc_new, 2'b00};
	end
end

wire	[31:0]	imm_ext;
wire	[1:0]	ext_ops;
extender	EXTENDER(imm_ext, imm, ext_ops);

reg		z_flag;
reg		c_flag;

wire	reg_wr;
wire	sel_wr;
wire	sel_data;
wire	sel_b;
wire	z_new;
wire	c_new;
wire	[2:0]	alu_ops;

wire	[31:0]	A;
wire	[31:0]	B;
wire	[31:0]	data_selected;
wire	[31:0]	data_S;
wire	[31:0]	data_M;
wire	[31:0]	B_selected;
wire	[4:0]	rw;


assign d_address=data_S;
assign data_M=d_data;
assign d_data=(mem_wr==1)?B:32'bz;

mux2_1		#(.WIDTH(5)) MUXRW(rw,rd,rt,sel_wr);
regfile		REGFILE(A, B, data_selected, rs, rt, rw, ~reg_wr, clock);
mux2_1		MUXDATA(data_selected,data_S,data_M,sel_data);
mux2_1		MUXB(B_selected,B,imm_ext,sel_b);
alu		ALU(data_S,z_new,c_new,A,B_selected,c_flag,alu_ops);

control	CONTROLUNIT(
	sel_pc,
	sel_addpc,
	sel_wr,
	sel_b,
	sel_data,
	reg_wr,
	mem_wr,
	ext_ops,
	alu_ops,
	opcode,
	z_new,
	reserved[2:0]
	);

// flag
always @(posedge clock)
begin
	if (nreset==0)
	begin
		z_flag=0;
		c_flag=0;
	end
	else
	begin
		z_flag=z_new;
		c_flag=c_new;
	end
end


endmodule
module alu(S, z, Cout, A, B, Cin, alu_ops);
output reg [31:0] S;
output z;
output reg Cout;
input [31:0] A;
input [31:0] B;
input Cin;
input [2:0] alu_ops;

assign z = ~|S;

always @(A or B or alu_ops)
begin
	case (alu_ops)
    3'b111: begin S = ~B; Cout = 0; end
    3'b110: begin S = ~A; Cout = 0; end
    3'b101: begin S = -A; Cout = 0; end
	3'b100: begin S = A ^ B; Cout = 0; end
	3'b011: begin S = A & B; Cout = 0; end
	3'b010: begin S = A | B; Cout = 0; end
	3'b001: {Cout, S} = A - B;
	default: {Cout, S} = A + B + Cin;
    endcase
end

endmodule
module micropc(mpc,lpc,z,i,l,clock);
output reg	[3:0] mpc;
input		[3:0] lpc;
input	z;
input	i;
input 	l;
input	clock;

reg [3:0] mpc_new;

always @(posedge clock)
begin
	mpc=mpc_new;
end

always @(z or i or l)
begin
	if (z==1)
		mpc_new=4'b0000;
	else if (i==1)
		mpc_new=mpc+1;
	else if (l==1)
		mpc_new=lpc;
end

endmodule
module quadSevenSeg(
    output [6:0] seg,
    output dp,
    output [3:0] an,
    input [3:0] num0,
    input [3:0] num1,
    input [3:0] num2,
    input [3:0] num3,
    input clk
);

reg [1:0] ns;
reg [1:0] ps;
reg [3:0] dispEn;
reg [3:0] hexIn;
wire [6:0] segments;
assign seg = segments;

hexTo7Segment segDecode(segments, hexIn);
assign dp = 1;
assign an = ~dispEn;

initial 
begin
ns = 0; hexIn = 1;
end

always @(posedge clk)
begin
    ps=ns;
end

always @(ps)
begin
    ns=ps+1;
end

always @(ps)
begin
    case(ps)
        2'b00: dispEn=4'b0001;
        2'b01: dispEn=4'b0010;
        2'b10: dispEn=4'b0100;
        2'b11: dispEn=4'b1000;
    endcase 
end

always @(ps)
begin
    case(ps)
        2'b00: hexIn=num0;
        2'b01: hexIn=num1;
        2'b10: hexIn=num2;
        2'b11: hexIn=num3;
    endcase
end

endmodule
module DFlipFlop(q,clock,d);
output q;
input clock,d;
reg q;
always @(posedge clock)
begin
q=d;
end
endmodule
module hexTo7Segment(
    output [6:0] segments,
    input [3:0] hex
);

reg [6:0] segments;


// 7-segment encoding
//      0
//     ---
//  5 |   | 1
//     --- <--6
//  4 |   | 2
//     ---
//      3

   always @(hex)
      case (hex)
          4'b0001 : segments = 7'b1111001;   // 1
          4'b0010 : segments = 7'b0100100;   // 2
          4'b0011 : segments = 7'b0110000;   // 3
          4'b0100 : segments = 7'b0011001;   // 4
          4'b0101 : segments = 7'b0010010;   // 5
          4'b0110 : segments = 7'b0000010;   // 6
          4'b0111 : segments = 7'b1111000;   // 7
          4'b1000 : segments = 7'b0000000;   // 8
          4'b1001 : segments = 7'b0010000;   // 9
          4'b1010 : segments = 7'b0001000;   // A
          4'b1011 : segments = 7'b0000011;   // b
          4'b1100 : segments = 7'b1000110;   // C
          4'b1101 : segments = 7'b0100001;   // d
          4'b1110 : segments = 7'b0000110;   // E
          4'b1111 : segments = 7'b0001110;   // F
          default : segments = 7'b1000000;   // 0
      endcase
      
endmodule
module debouncer(
        input i,
        input clk,
        output reg o
    );

reg ls = 0;

always @(posedge clk)
begin
if(i)
    begin
    if(ls)
        begin
        o = 1;
        ls = i;
        end
    else
        begin
        o = 0;
        ls = i;
        end
    end
else
    begin
    o = 0;
    ls = i;
    end
end
endmodule
module singlePulser(
    input pulse,
    input clk,
    output out
    );

reg [1:0] pstate = 2'b0;
reg [1:0] nstate = 2'b0;
reg out = 0;


always @(posedge clk)
begin
    pstate = nstate;
end

always @(posedge clk)
begin
    case(pstate)
        1'b0: 
            if(pulse) 
            begin
                nstate = 1'b1;
                out = 1;
            end
            else 
            begin
                nstate = 1'b0;
                out = 0;
            end
        2'b1: 
            if(pulse) 
            begin
                nstate = 1'b1;
                out = 0;
            end
            else 
            begin
                nstate = 1'b0;
                out = 0;
            end
    endcase
end
 
endmodule
module inputStabilizer(
        input i,
        input clock,
        output o
    );

wire DFF1Output,DFF0Output;
wire SPin;

clockDiv cd(outClk,clock);
DFlipFlop DFF1(DFF1Output,clock,i);
DFlipFlop DFF0(DFF0Output,clock,DFF1Output);

assign SPin = (DFF1Output && ~DFF0Output);

singlePulser SP2(SPin,clock,o);

endmodule
module clockDiv(
    output clkDiv,
    input clk
);

reg clkDiv;
initial
begin
    clkDiv = 0;
end

always @(posedge clk)
begin
    clkDiv = ~clkDiv;
end

endmodule
module receiver(
    input clk,
    input bit_in,
    output reg received,
    output reg [7:0] data_out
    );
    
    reg last_bit;
    reg receiving = 0;
    reg [7:0] count;
    
    always@(posedge clk) begin
        if (~receiving & last_bit & ~bit_in) 
        begin
            receiving <= 1;
            received <= 0;
            count <= 0;
        end

        last_bit <= bit_in;
      
        if (receiving) count <= count + 1;
        else count <= 0;
        
        case (count)
            8'd24: data_out[0] <= bit_in;
            8'd40: data_out[1] <= bit_in;
            8'd56: data_out[2] <= bit_in;
            8'd72: data_out[3] <= bit_in;
            8'd88: data_out[4] <= bit_in;
            8'd104: data_out[5] <= bit_in;
            8'd120: data_out[6] <= bit_in;
            8'd136: data_out[7] <= bit_in;
            8'd152: begin received <= 1; receiving <= 0; end
        endcase
    end
endmodule
module transmitter(
    input clk,
    input [7:0] data_transmit,
    input ena,
    output reg sent,
    output reg bit_out
);
    reg last_ena;
    reg sending = 0;
    reg [7:0] count;
    reg [7:0] temp;
    
    always@(posedge clk) 
    begin
        if (~sending & ~last_ena & ena) 
        begin
            temp <= data_transmit;
            sending <= 1;
            sent <= 0;
            count <= 0;
        end
        
        last_ena <= ena;
        
        if (sending) count <= count + 1;
        else begin count <= 0; bit_out <= 1; end
        
        case (count)
            8'd8: bit_out <= 0;
            8'd24: bit_out <= temp[0];  
            8'd40: bit_out <= temp[1];
            8'd56: bit_out <= temp[2];
            8'd72: bit_out <= temp[3];
            8'd88: bit_out <= temp[4];
            8'd104: bit_out <= temp[5];
            8'd120: bit_out <= temp[6];
            8'd136: bit_out <= temp[7];
            8'd152: begin sent <= 1; sending <= 0; end
        endcase
    end
endmodule
module baudrate_gen(
    input clk,
    output reg baud
    );
    
    integer counter;
    always @(posedge clk)
    begin
        counter = counter + 1;
        if (counter == 325) begin counter = 0; baud = ~baud; end
    end
endmodule
module vsync(
    input clk,
    input line_clk,
    output reg [15:0] v_val = 0
    );
    
    always @(posedge line_clk)
    begin
        if (v_val == 525) v_val = 0;
        else v_val = v_val + 1;
    end
endmodule
module uartSystem(
    input clk,
    input RsRx,
    output RsTx
    );
    
    reg [7:0]K_UP = 8'h77;            //w
    reg [7:0]K_DOWN = 8'h73;          //s
    reg [7:0]K_RIGHT = 8'h64;         //d
    reg [7:0]K_LEFT = 8'h61;          //a
        
    reg [7:0]K_WHITE = 8'h20;         //SPACE
    reg [7:0]K_MAGENTA = 8'h6d;       //m
    reg [7:0]K_CYAN = 8'h63;          //c
    reg [7:0]K_YELLOW = 8'h79;        //y
    
    reg ena, last_rec;
    reg [7:0] data_in;
    wire [7:0] data_out;
    wire sent, received, baud;
    
    
    baudrate_gen baudrate_gen(clk, baud);
    receiver receiver(baud, RsRx, received, data_out);
    transmitter transmitter(baud, data_in, ena, sent, RsTx);

    always @(posedge baud)
    begin
        if (ena == 1) ena = 0;
        
        if (~last_rec & received) begin
            case (data_out)
                K_UP : data_in = 8'h57;
                K_DOWN : data_in = 8'h53;
                K_RIGHT : data_in = 8'h44;
                K_LEFT : data_in = 8'h41;
                K_WHITE : data_in = 8'h5A;
                K_MAGENTA : data_in = 8'h4D;
                K_CYAN : data_in = 8'h43;
                K_YELLOW : data_in = 8'h59;
                default : data_in = 8'hFF;
            endcase
            if (data_in != 8'hFF) ena = 1;
        end
        last_rec = received;
    end
    
endmodule
module hsync(
    input clk,
    output reg line_clk = 0,
    output reg [15:0] h_val = 0
    );
    
    always @(posedge clk)
    begin
        if (h_val == 800) begin h_val = 0; line_clk = 1; end
        else begin h_val = h_val + 1; line_clk = 0; end
    end
endmodule
module vgaSystem(
    input clk,
    output Hsync,
    output Vsync,
    output [3:0] vgaRed,
    output [3:0] vgaGreen,
    output [3:0] vgaBlue
    );
    
    wire line_clk;
    wire [15:0] h_val, v_val;
    
    hsync hs(clk, line_clk, h_val);
    vsync vs(clk, line_clk, v_val);
    
    assign Hsync = (h_val < 687) ? 1 : 0;
    assign Vsync = (v_val < 511) ? 1 : 0;
    
    assign {vgaRed, vgaGreen, vgaBlue} = ((h_val-367)**2 + (v_val-273)**2 <= 100**2) ? 12'hfff : 12'h000;
endmodule
module system(
    output [6:0] seg,
    output dp,
    output [3:0] an,
    input clk,
    input [15:0]sw,
    input btnU,
    input btnC
    );
    
wire [3:0] num0;
wire [3:0] num1;
wire [3:0] num2;
wire [3:0] num3;

wire targetClk;
wire an0, an1, an2, an3;

assign an = {an3, an2, an1, an0};

wire [18:0] tclk;

assign tclk[0] = clk;

genvar c;

generate for(c = 0; c < 18; c = c + 1)
    begin
        clockDiv fdiv(tclk[c+1], tclk[c]);
    end
endgenerate

clockDiv fdivTarget(targetClk, tclk[10]);

quadSevenSeg q7Seg(seg, dp, an0, an1, an2, an3, num0, num1, num2, num3, targetClk);


singlePulser spu0(up0, sw[1], targetClk);
singlePulser spu1(up1, sw[3], targetClk);
singlePulser spu2(up2, sw[5], targetClk);
singlePulser spu3(up3, sw[7], targetClk);
singlePulser spd0(down0, sw[0], targetClk);
singlePulser spd1(down1, sw[2], targetClk);
singlePulser spd2(down2, sw[4], targetClk);
singlePulser spd3(down3, sw[6], targetClk);

wire c0, c1, c2, c3;
wire b0, b1, b2, b3;

bcd bcd0(num0, c0, b0, up0, down0, btnU|c3, btnC|b3, targetClk);
bcd bcd1(num1, c1, b1, up1|c0, down1|b0, btnU|c3, btnC|b3, targetClk);
bcd bcd2(num2, c2, b2, up2|c1, down2|b1, btnU|c3, btnC|b3, targetClk);
bcd bcd3(num3, c3, b3, up3|c2, down3|b2, btnU|c3, btnC|b3, targetClk);

endmodule
module system(
    output [6:0] seg,
    output dp,
    output [3:0] an,
    input clk
    );
    
wire [3:0] num0;
wire [3:0] num1;
wire [3:0] num2;
wire [3:0] num3;

assign num0 = 4;
assign num1 = 3;
assign num2 = 2;
assign num3 = 1;
   
wire targetClk;
wire an0, an1, an2, an3;

assign an = {an3, an2, an1, an0};

wire [18:0] tclk;

assign tclk[0] = clk;

genvar c;

generate for(c = 0; c < 18; c = c + 1)
    begin
        clockDiv fdiv(tclk[c+1], tclk[c]);
    end
endgenerate

clockDiv fdivTarget(targetClk, tclk[18]);

quadSevenSeg q7Seg(seg, dp, an0, an1, an2, an3, num0, num1, num2, num3, targetClk);

endmodule
module test_i2c_master_wbs_16;

// Parameters
parameter DEFAULT_PRESCALE = 1;
parameter FIXED_PRESCALE = 0;
parameter CMD_FIFO = 1;
parameter CMD_FIFO_DEPTH = 32;
parameter WRITE_FIFO = 1;
parameter WRITE_FIFO_DEPTH = 32;
parameter READ_FIFO = 1;
parameter READ_FIFO_DEPTH = 32;

// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;

reg [2:0] wbs_adr_i = 0;
reg [15:0] wbs_dat_i = 0;
reg wbs_we_i = 0;
reg [1:0] wbs_sel_i = 0;
reg wbs_stb_i = 0;
reg wbs_cyc_i = 0;
reg i2c_scl_i = 1;
reg i2c_sda_i = 1;

// Outputs
wire [15:0] wbs_dat_o;
wire wbs_ack_o;
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_o;
wire i2c_sda_t;

initial begin
    // myhdl integration
    $from_myhdl(
        clk,
        rst,
        current_test,
        wbs_adr_i,
        wbs_dat_i,
        wbs_we_i,
        wbs_sel_i,
        wbs_stb_i,
        wbs_cyc_i,
        i2c_scl_i,
        i2c_sda_i
    );
    $to_myhdl(
        wbs_dat_o,
        wbs_ack_o,
        i2c_scl_o,
        i2c_scl_t,
        i2c_sda_o,
        i2c_sda_t
    );

    // dump file
    $dumpfile("test_i2c_master_wbs_16.lxt");
    $dumpvars(0, test_i2c_master_wbs_16);
end

i2c_master_wbs_16 #(
    .DEFAULT_PRESCALE(DEFAULT_PRESCALE),
    .FIXED_PRESCALE(FIXED_PRESCALE),
    .CMD_FIFO(CMD_FIFO),
    .CMD_FIFO_DEPTH(CMD_FIFO_DEPTH),
    .WRITE_FIFO(WRITE_FIFO),
    .WRITE_FIFO_DEPTH(WRITE_FIFO_DEPTH),
    .READ_FIFO(READ_FIFO),
    .READ_FIFO_DEPTH(READ_FIFO_DEPTH)
)
UUT (
    .clk(clk),
    .rst(rst),
    .wbs_adr_i(wbs_adr_i),
    .wbs_dat_i(wbs_dat_i),
    .wbs_dat_o(wbs_dat_o),
    .wbs_we_i(wbs_we_i),
    .wbs_sel_i(wbs_sel_i),
    .wbs_stb_i(wbs_stb_i),
    .wbs_ack_o(wbs_ack_o),
    .wbs_cyc_i(wbs_cyc_i),
    .i2c_scl_i(i2c_scl_i),
    .i2c_scl_o(i2c_scl_o),
    .i2c_scl_t(i2c_scl_t),
    .i2c_sda_i(i2c_sda_i),
    .i2c_sda_o(i2c_sda_o),
    .i2c_sda_t(i2c_sda_t)
);

endmodule
module test_i2c_master_axil;

// Parameters
parameter DEFAULT_PRESCALE = 1;
parameter FIXED_PRESCALE = 0;
parameter CMD_FIFO = 1;
parameter CMD_FIFO_DEPTH = 32;
parameter WRITE_FIFO = 1;
parameter WRITE_FIFO_DEPTH = 32;
parameter READ_FIFO = 1;
parameter READ_FIFO_DEPTH = 32;

// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;

reg [3:0] s_axil_awaddr = 0;
reg [2:0] s_axil_awprot = 0;
reg s_axil_awvalid = 0;
reg [31:0] s_axil_wdata = 0;
reg [3:0] s_axil_wstrb = 0;
reg s_axil_wvalid = 0;
reg s_axil_bready = 0;
reg [3:0] s_axil_araddr = 0;
reg [2:0] s_axil_arprot = 0;
reg s_axil_arvalid = 0;
reg s_axil_rready = 0;
reg i2c_scl_i = 1;
reg i2c_sda_i = 1;

// Outputs
wire s_axil_awready;
wire s_axil_wready;
wire [1:0] s_axil_bresp;
wire s_axil_bvalid;
wire s_axil_arready;
wire [31:0] s_axil_rdata;
wire [1:0] s_axil_rresp;
wire s_axil_rvalid;
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_o;
wire i2c_sda_t;

initial begin
    // myhdl integration
    $from_myhdl(
        clk,
        rst,
        current_test,
        s_axil_awaddr,
        s_axil_awprot,
        s_axil_awvalid,
        s_axil_wdata,
        s_axil_wstrb,
        s_axil_wvalid,
        s_axil_bready,
        s_axil_araddr,
        s_axil_arprot,
        s_axil_arvalid,
        s_axil_rready,
        i2c_scl_i,
        i2c_sda_i
    );
    $to_myhdl(
        s_axil_awready,
        s_axil_wready,
        s_axil_bresp,
        s_axil_bvalid,
        s_axil_arready,
        s_axil_rdata,
        s_axil_rresp,
        s_axil_rvalid,
        i2c_scl_o,
        i2c_scl_t,
        i2c_sda_o,
        i2c_sda_t
    );

    // dump file
    $dumpfile("test_i2c_master_axil.lxt");
    $dumpvars(0, test_i2c_master_axil);
end

i2c_master_axil #(
    .DEFAULT_PRESCALE(DEFAULT_PRESCALE),
    .FIXED_PRESCALE(FIXED_PRESCALE),
    .CMD_FIFO(CMD_FIFO),
    .CMD_FIFO_DEPTH(CMD_FIFO_DEPTH),
    .WRITE_FIFO(WRITE_FIFO),
    .WRITE_FIFO_DEPTH(WRITE_FIFO_DEPTH),
    .READ_FIFO(READ_FIFO),
    .READ_FIFO_DEPTH(READ_FIFO_DEPTH)
)
UUT (
    .clk(clk),
    .rst(rst),
    .s_axil_awaddr(s_axil_awaddr),
    .s_axil_awprot(s_axil_awprot),
    .s_axil_awvalid(s_axil_awvalid),
    .s_axil_awready(s_axil_awready),
    .s_axil_wdata(s_axil_wdata),
    .s_axil_wstrb(s_axil_wstrb),
    .s_axil_wvalid(s_axil_wvalid),
    .s_axil_wready(s_axil_wready),
    .s_axil_bresp(s_axil_bresp),
    .s_axil_bvalid(s_axil_bvalid),
    .s_axil_bready(s_axil_bready),
    .s_axil_araddr(s_axil_araddr),
    .s_axil_arprot(s_axil_arprot),
    .s_axil_arvalid(s_axil_arvalid),
    .s_axil_arready(s_axil_arready),
    .s_axil_rdata(s_axil_rdata),
    .s_axil_rresp(s_axil_rresp),
    .s_axil_rvalid(s_axil_rvalid),
    .s_axil_rready(s_axil_rready),
    .i2c_scl_i(i2c_scl_i),
    .i2c_scl_o(i2c_scl_o),
    .i2c_scl_t(i2c_scl_t),
    .i2c_sda_i(i2c_sda_i),
    .i2c_sda_o(i2c_sda_o),
    .i2c_sda_t(i2c_sda_t)
);

endmodule
module test_i2c_master_wbs_8;

// Parameters
parameter DEFAULT_PRESCALE = 1;
parameter FIXED_PRESCALE = 0;
parameter CMD_FIFO = 1;
parameter CMD_FIFO_DEPTH = 32;
parameter WRITE_FIFO = 1;
parameter WRITE_FIFO_DEPTH = 32;
parameter READ_FIFO = 1;
parameter READ_FIFO_DEPTH = 32;

// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;

reg [2:0] wbs_adr_i = 0;
reg [7:0] wbs_dat_i = 0;
reg wbs_we_i = 0;
reg wbs_stb_i = 0;
reg wbs_cyc_i = 0;
reg i2c_scl_i = 1;
reg i2c_sda_i = 1;

// Outputs
wire [7:0] wbs_dat_o;
wire wbs_ack_o;
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_o;
wire i2c_sda_t;

initial begin
    // myhdl integration
    $from_myhdl(
        clk,
        rst,
        current_test,
        wbs_adr_i,
        wbs_dat_i,
        wbs_we_i,
        wbs_stb_i,
        wbs_cyc_i,
        i2c_scl_i,
        i2c_sda_i
    );
    $to_myhdl(
        wbs_dat_o,
        wbs_ack_o,
        i2c_scl_o,
        i2c_scl_t,
        i2c_sda_o,
        i2c_sda_t
    );

    // dump file
    $dumpfile("test_i2c_master_wbs_8.lxt");
    $dumpvars(0, test_i2c_master_wbs_8);
end

i2c_master_wbs_8 #(
    .DEFAULT_PRESCALE(DEFAULT_PRESCALE),
    .FIXED_PRESCALE(FIXED_PRESCALE),
    .CMD_FIFO(CMD_FIFO),
    .CMD_FIFO_DEPTH(CMD_FIFO_DEPTH),
    .WRITE_FIFO(WRITE_FIFO),
    .WRITE_FIFO_DEPTH(WRITE_FIFO_DEPTH),
    .READ_FIFO(READ_FIFO),
    .READ_FIFO_DEPTH(READ_FIFO_DEPTH)
)
UUT (
    .clk(clk),
    .rst(rst),
    .wbs_adr_i(wbs_adr_i),
    .wbs_dat_i(wbs_dat_i),
    .wbs_dat_o(wbs_dat_o),
    .wbs_we_i(wbs_we_i),
    .wbs_stb_i(wbs_stb_i),
    .wbs_ack_o(wbs_ack_o),
    .wbs_cyc_i(wbs_cyc_i),
    .i2c_scl_i(i2c_scl_i),
    .i2c_scl_o(i2c_scl_o),
    .i2c_scl_t(i2c_scl_t),
    .i2c_sda_i(i2c_sda_i),
    .i2c_sda_o(i2c_sda_o),
    .i2c_sda_t(i2c_sda_t)
);

endmodule
module and2(
  a,
  b,
  c);

input wire a;
input wire b;
output wire c;

assign c = a & b;

endmodule
module and2_latch(
  a,
  b,
  clk,
  c,
  d);

input wire clk;

input wire a;
input wire b;
output wire c;
output reg d;

assign c = a & b;

always @(posedge clk) begin
  d <= c;
end

endmodule
module routing_test(IN0,IN1,IN2, clk, OUT0,OUT1,OUT2);

input wire IN0,IN1,IN2,clk;

output reg OUT0, OUT1, OUT2;

always @(posedge clk)
	begin

		OUT0  <=  IN0;
		OUT1  <=  IN1;
		OUT2  <=  IN2;

	end



endmodule
module counter(clk, q, rst);

    input clk;
    input rst;
    output [7:0] q;
    reg [7:0] q;

    always @ (posedge clk)
    begin
        if(rst)
			q <= 8'b00000000;
	else
		q <= q + 1;
    end

endmodule
module and2_or2(
  a,
  b,
  c,
  d);

input wire a;
input wire b;
output wire c;
output wire d;

assign c = a & b;
assign d = a | b;

endmodule
module bin2bcd(
     bin,
     bcd
    );

    
    //input ports and their sizes
    input [7:0] bin;
    //output ports and, their size
    output [11:0] bcd;
    //Internal variables
    reg [11 : 0] bcd; 
    reg [3:0] i;   
     
     //Always block - implement the Double Dabble algorithm
     always @(bin)
        begin
            bcd = 0; //initialize bcd to zero.
            for (i = 0; i < 8; i = i+1) //run for 8 iterations
            begin
                bcd = {bcd[10:0],bin[7-i]}; //concatenation
                    
                //if a hex digit of 'bcd' is more than 4, add 3 to it.  
                if(i < 7 && bcd[3:0] > 4) 
                    bcd[3:0] = bcd[3:0] + 3;
                if(i < 7 && bcd[7:4] > 4)
                    bcd[7:4] = bcd[7:4] + 3;
                if(i < 7 && bcd[11:8] > 4)
                    bcd[11:8] = bcd[11:8] + 3;  
            end
        end     
                
endmodule
module io_sky130_fd_sc_hd__dfrtp_1_mem
(

    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    ccff_head,
    prog_clk,
    prog_reset,
    ccff_tail,
    mem_out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input ccff_head;
    input prog_clk;
    input prog_reset;
    output ccff_tail;
    output mem_out;

    wire ccff_head;
    wire ccff_tail;
    wire mem_out;
    wire prog_clk;
    wire prog_reset;

assign ccff_tail = mem_out;
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(ccff_head),
        .RESET_B(prog_reset),
        .Q(mem_out)
    );
endmodule
module mux_tree_tapbuf_size8_mem
(    
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    ccff_head,
    prog_clk,
    prog_reset,
    ccff_tail,
    mem_out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input ccff_head;
    input prog_clk;
    input prog_reset;
    output ccff_tail;
    output [0:3]mem_out;

    wire ccff_head;
    wire ccff_tail;
    wire [0:3]mem_out;
    wire prog_clk;
    wire prog_reset;

assign ccff_tail = mem_out[3];
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(ccff_head),
        .RESET_B(prog_reset),
        .Q(mem_out[0])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[0]),
        .RESET_B(prog_reset),
        .Q(mem_out[1])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[1]),
        .RESET_B(prog_reset),
        .Q(mem_out[2])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[2]),
        .RESET_B(prog_reset),
        .Q(mem_out[3])
    );
endmodule
module mux_tree_tapbuf_size3_mem
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    ccff_head,
    prog_clk,
    prog_reset,
    ccff_tail,
    mem_out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input ccff_head;
    input prog_clk;
    input prog_reset;
    output ccff_tail;
    output [0:1]mem_out;

    wire ccff_head;
    wire ccff_tail;
    wire [0:1]mem_out;
    wire prog_clk;
    wire prog_reset;

assign ccff_tail = mem_out[1];
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
    (
        `ifdef USE_POWER_PINS
        .VPWR(VPWR),
        .VGND(VGND), 
        `endif
        .CLK(prog_clk),
        .D(ccff_head),
        .RESET_B(prog_reset),
        .Q(mem_out[0])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
    (
        `ifdef USE_POWER_PINS
        .VPWR(VPWR),
        .VGND(VGND), 
        `endif
        .CLK(prog_clk),
        .D(mem_out[0]),
        .RESET_B(prog_reset),
        .Q(mem_out[1])
    );
endmodule
module mux_tree_tapbuf_size7_mem
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    ccff_head,
    prog_clk,
    prog_reset,
    ccff_tail,
    mem_out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input ccff_head;
    input prog_clk;
    input prog_reset;
    output ccff_tail;
    output [0:2]mem_out;

    wire ccff_head;
    wire ccff_tail;
    wire [0:2]mem_out;
    wire prog_clk;
    wire prog_reset;

assign ccff_tail = mem_out[2];
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(ccff_head),
        .RESET_B(prog_reset),
        .Q(mem_out[0])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[0]),
        .RESET_B(prog_reset),
        .Q(mem_out[1])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[1]),
        .RESET_B(prog_reset),
        .Q(mem_out[2])
    );
endmodule
module const0
(
    const0
);

    output const0;

    wire \<const0> = 0 ;
    wire const0;

assign const0 = \<const0> ;
endmodule
module const1
(
    const1
);

    output const1;

    wire \<const1> = 1 ;
    wire const1;

assign const1 = \<const1> ;
endmodule
module mux_tree_tapbuf_size9_mem
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    ccff_head,
    prog_clk,
    prog_reset,
    ccff_tail,
    mem_out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input ccff_head;
    input prog_clk;
    input prog_reset;
    output ccff_tail;
    output [0:3]mem_out;

    wire ccff_head;
    wire ccff_tail;
    wire [0:3]mem_out;
    wire prog_clk;
    wire prog_reset;

assign ccff_tail = mem_out[3];
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(ccff_head),
        .RESET_B(prog_reset),
        .Q(mem_out[0])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[0]),
        .RESET_B(prog_reset),
        .Q(mem_out[1])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[1]),
        .RESET_B(prog_reset),
        .Q(mem_out[2])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[2]),
        .RESET_B(prog_reset),
        .Q(mem_out[3])
    );
endmodule
module direct_interc
(
    in,
    out
);

    input in;
    output out;

    wire in;
    wire out;

assign out = in;
endmodule
module mux_tree_tapbuf_size6
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    in,
    sram,
    sram_inv,
    out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input [0:5]in;
    input [0:2]sram;
    input [0:2]sram_inv;
    output out;

    wire const1_0_const1;
    wire [0:5]in;
    wire out;
    wire sky130_fd_sc_hd__mux2_1_0_X;
    wire sky130_fd_sc_hd__mux2_1_1_X;
    wire sky130_fd_sc_hd__mux2_1_2_X;
    wire sky130_fd_sc_hd__mux2_1_3_X;
    wire sky130_fd_sc_hd__mux2_1_4_X;
    wire sky130_fd_sc_hd__mux2_1_5_X;
    wire [0:2]sram;
    wire [0:2]sram_inv;

    const1 const1_0_
    (
        .const1(const1_0_const1)
    );
    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[1]),
        .A1(in[0]),
        .S(sram[0]),
        .X(sky130_fd_sc_hd__mux2_1_0_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l1_in_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[3]),
        .A1(in[2]),
        .S(sram[0]),
        .X(sky130_fd_sc_hd__mux2_1_1_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l1_in_2_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[5]),
        .A1(in[4]),
        .S(sram[0]),
        .X(sky130_fd_sc_hd__mux2_1_2_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(sky130_fd_sc_hd__mux2_1_1_X),
        .A1(sky130_fd_sc_hd__mux2_1_0_X),
        .S(sram[1]),
        .X(sky130_fd_sc_hd__mux2_1_3_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l2_in_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(const1_0_const1),
        .A1(sky130_fd_sc_hd__mux2_1_2_X),
        .S(sram[1]),
        .X(sky130_fd_sc_hd__mux2_1_4_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l3_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(sky130_fd_sc_hd__mux2_1_4_X),
        .A1(sky130_fd_sc_hd__mux2_1_3_X),
        .S(sram[2]),
        .X(sky130_fd_sc_hd__mux2_1_5_X)
    );
    sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A(sky130_fd_sc_hd__mux2_1_5_X),
        .X(out)
    );
endmodule
module mux_tree_tapbuf_size5_mem
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    ccff_head,
    prog_clk,
    prog_reset,
    ccff_tail,
    mem_out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input ccff_head;
    input prog_clk;
    input prog_reset;
    output ccff_tail;
    output [0:2]mem_out;

    wire ccff_head;
    wire ccff_tail;
    wire [0:2]mem_out;
    wire prog_clk;
    wire prog_reset;

assign ccff_tail = mem_out[2];
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(ccff_head),
        .RESET_B(prog_reset),
        .Q(mem_out[0])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[0]),
        .RESET_B(prog_reset),
        .Q(mem_out[1])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[1]),
        .RESET_B(prog_reset),
        .Q(mem_out[2])
    );
endmodule
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    ff_D,
    ff_DI,
    ff_clk,
    ff_reset,
    test_enable,
    ff_Q
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input ff_D;
    input ff_DI;
    input ff_clk;
    input ff_reset;
    input test_enable;
    output ff_Q;

    wire ff_D;
    wire ff_DI;
    wire ff_Q;
    wire ff_clk;
    wire ff_reset;
    wire test_enable;

    sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(ff_clk),
        .D(ff_D),
        .RESET_B(ff_reset),
        .SCD(ff_DI),
        .SCE(test_enable),
        .Q(ff_Q)
    );
endmodule
module mux_tree_tapbuf_size9
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    in,
    sram,
    sram_inv,
    out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input [0:8]in;
    input [0:3]sram;
    input [0:3]sram_inv;
    output out;

    wire const1_0_const1;
    wire [0:8]in;
    wire out;
    wire sky130_fd_sc_hd__mux2_1_0_X;
    wire sky130_fd_sc_hd__mux2_1_1_X;
    wire sky130_fd_sc_hd__mux2_1_2_X;
    wire sky130_fd_sc_hd__mux2_1_3_X;
    wire sky130_fd_sc_hd__mux2_1_4_X;
    wire sky130_fd_sc_hd__mux2_1_5_X;
    wire sky130_fd_sc_hd__mux2_1_6_X;
    wire sky130_fd_sc_hd__mux2_1_7_X;
    wire sky130_fd_sc_hd__mux2_1_8_X;
    wire [0:3]sram;
    wire [0:3]sram_inv;

    const1 const1_0_
    (
        .const1(const1_0_const1)
    );
    sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[1]),
        .A1(in[0]),
        .S(sram[0]),
        .X(sky130_fd_sc_hd__mux2_1_0_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l1_in_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[3]),
        .A1(in[2]),
        .S(sram[0]),
        .X(sky130_fd_sc_hd__mux2_1_1_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(sky130_fd_sc_hd__mux2_1_1_X),
        .A1(sky130_fd_sc_hd__mux2_1_0_X),
        .S(sram[1]),
        .X(sky130_fd_sc_hd__mux2_1_2_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l2_in_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[5]),
        .A1(in[4]),
        .S(sram[1]),
        .X(sky130_fd_sc_hd__mux2_1_3_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l2_in_2_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(in[7]),
        .A1(in[6]),
        .S(sram[1]),
        .X(sky130_fd_sc_hd__mux2_1_4_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l2_in_3_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(const1_0_const1),
        .A1(in[8]),
        .S(sram[1]),
        .X(sky130_fd_sc_hd__mux2_1_5_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l3_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(sky130_fd_sc_hd__mux2_1_3_X),
        .A1(sky130_fd_sc_hd__mux2_1_2_X),
        .S(sram[2]),
        .X(sky130_fd_sc_hd__mux2_1_6_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l3_in_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(sky130_fd_sc_hd__mux2_1_5_X),
        .A1(sky130_fd_sc_hd__mux2_1_4_X),
        .S(sram[2]),
        .X(sky130_fd_sc_hd__mux2_1_7_X)
    );
    sky130_fd_sc_hd__mux2_1 mux_l4_in_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A0(sky130_fd_sc_hd__mux2_1_7_X),
        .A1(sky130_fd_sc_hd__mux2_1_6_X),
        .S(sram[3]),
        .X(sky130_fd_sc_hd__mux2_1_8_X)
    );
    sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.A(sky130_fd_sc_hd__mux2_1_8_X),
        .X(out)
    );
endmodule
module mux_tree_size2_mem
(
    `ifdef USE_POWER_PINS
    VPWR,
    VGND, 
    `endif
    ccff_head,
    prog_clk,
    prog_reset,
    ccff_tail,
    mem_out
);

    `ifdef USE_POWER_PINS
    input VPWR;
    input VGND;
    `endif
    input ccff_head;
    input prog_clk;
    input prog_reset;
    output ccff_tail;
    output [0:1]mem_out;

    wire ccff_head;
    wire ccff_tail;
    wire [0:1]mem_out;
    wire prog_clk;
    wire prog_reset;

assign ccff_tail = mem_out[1];
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(ccff_head),
        .RESET_B(prog_reset),
        .Q(mem_out[0])
    );
    sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
    (
        
 	`ifdef USE_POWER_PINS 
	.VPWR(VPWR), 
	.VGND(VGND),  
	`endif 
	.CLK(prog_clk),
        .D(mem_out[0]),
        .RESET_B(prog_reset),
        .Q(mem_out[1])
    );
endmodule