dakies/OSS_Verilog huggingface dataset:
module uart_tx #
(
    parameter DATA_WIDTH = 8
)
(
    input  wire                   clk,
    input  wire                   rst,

    /*
     * AXI input
     */
    input  wire [DATA_WIDTH-1:0]  input_axis_tdata,
    input  wire                   input_axis_tvalid,
    output wire                   input_axis_tready,

    /*
     * UART interface
     */
    output wire                   txd,

    /*
     * Status
     */
    output wire                   busy,

    /*
     * Configuration
     */
    input  wire [15:0]            prescale
);

reg input_axis_tready_reg = 0;

reg txd_reg = 1;

reg busy_reg = 0;

reg [DATA_WIDTH:0] data_reg = 0;
reg [18:0] prescale_reg = 0;
reg [3:0] bit_cnt = 0;

assign input_axis_tready = input_axis_tready_reg;
assign txd = txd_reg;

assign busy = busy_reg;

always @(posedge clk or posedge rst) begin
    if (rst) begin
        input_axis_tready_reg <= 0;
        txd_reg <= 1;
        prescale_reg <= 0;
        bit_cnt <= 0;
        busy_reg <= 0;
    end else begin
        if (prescale_reg > 0) begin
            input_axis_tready_reg <= 0;
            prescale_reg <= prescale_reg - 1;
        end else if (bit_cnt == 0) begin
            input_axis_tready_reg <= 1;
            busy_reg <= 0;

            if (input_axis_tvalid) begin
                input_axis_tready_reg <= ~input_axis_tready_reg;
                prescale_reg <= (prescale << 3)-1;
                bit_cnt <= DATA_WIDTH+1;
                data_reg <= {1'b1, input_axis_tdata};
                txd_reg <= 0;
                busy_reg <= 1;
            end
        end else begin
            if (bit_cnt > 1) begin
                bit_cnt <= bit_cnt - 1;
                prescale_reg <= (prescale << 3)-1;
                {data_reg, txd_reg} <= {1'b0, data_reg};
            end else if (bit_cnt == 1) begin
                bit_cnt <= bit_cnt - 1;
                prescale_reg <= (prescale << 3);
                txd_reg <= 1;
            end
        end
    end
end

endmodule
module ram16k(input clk,
	      input [13:0] 	addr,
	      input [15:0] 	data_in,
	      output reg [15:0] data_out,
	      input 		we,
	      input 		re);

   reg [15:0] 			RAM [0:8192-1];

   always @(posedge clk)
     if (re) begin
	data_out <= RAM[addr];
     end else if (we) begin
	RAM[addr] <= data_in;
     end

   
endmodule // ram16k
module ram8k_low(input clk,
	         input [11:0]  addr,
	         input [15:0]  data_in,
	         output [15:0] data_out,
	         input         we,
	         input         re);

   wire [15:0]                  data_out_low;
   wire [15:0]                  data_out_high;
   wire                         we_low;
   wire                         re_low;

   wire                         we_high;
   wire                         re_high;

   // Each block is 4048 words; each, in turn,
   //     made of two 2024 word block
   ram4k_low_low r1(.clk(clk),
                    .addr(addr[10:0]),
                    .data_in(data_in),
                    .data_out(data_out_low),
                    .we(we_low),
                    .re(re_low));

   ram4k_low_high r2(.clk(clk),
                     .addr(addr[10:0]),
                     .data_in(data_in),
                     .data_out(data_out_high),
                     .we(we_high),
                     .re(re_high));

   reg                          on_high;
   always @(posedge clk) on_high <= addr[11];
   
   assign data_out = on_high?data_out_high:data_out_low;
   assign we_high   = addr[11]&we;
   assign we_low    = (~addr[11])&we;
   
   assign re_low    = 1;
   assign re_high   = 1;
   
endmodule // ram8k
module ram8k_high(input clk,
	          input [11:0]  addr,
	          input [15:0]  data_in,
	          output [15:0] data_out,
	          input         we,
	          input         re);

   wire [15:0]                  data_out_low;
   wire [15:0]                  data_out_high;
   wire                         we_low;
   wire                         re_low;

   wire                         we_high;
   wire                         re_high;

   // Each block is 4048 words; each, in turn,
   //     made of two 2024 word block
   ram4k_high_low r1(.clk(clk),
                     .addr(addr[10:0]),
                     .data_in(data_in),
                     .data_out(data_out_low),
                     .we(we_low),
                     .re(re_low));
   
   ram4k_high_high r2(.clk(clk),
                      .addr(addr[10:0]),
                      .data_in(data_in),
                      .data_out(data_out_high),
                      .we(we_high),
                      .re(re_high));
   
   reg                          on_high;
   always @(posedge clk) on_high <= addr[11];
   
   assign data_out = on_high?data_out_high:data_out_low;
   assign we_high   = addr[11]&we;
   assign we_low    = (~addr[11])&we;
   
   assign re_low    = 1;
   assign re_high   = 1;
   
endmodule // ram8k
module ram16k(input clk,
	      input [12:0] 	addr,
	      input [15:0] 	data_in,
	      output [15:0] data_out,
	      input 		we,
	      input 		re);

   wire [15:0]                  data_out_low;
   wire [15:0]                  data_out_high;
   wire                         we_low;
   wire                         re_low;

   wire                         we_high;
   wire                         re_high;

   // Each block is 4048 words; each, in turn,
   //     made of two 2024 word block
   ram8k_low r1(.clk(clk),
                .addr(addr[11:0]),
                .data_in(data_in),
                .data_out(data_out_low),
                .we(we_low),
                .re(re_low));
  
   ram8k_high r2(.clk(clk),
                 .addr(addr[11:0]),
                 .data_in(data_in),
                 .data_out(data_out_high),
                 .we(we_high),
                 .re(re_high));

   reg                          on_high;
   always @(posedge clk) on_high <= addr[12];
   
   assign data_out = on_high?data_out_high:data_out_low;
   assign we_high   = addr[12]&we;
   assign we_low    = (~addr[12])&we;
   
   assign re_low    = 1;
   assign re_high   = 1;
   
endmodule // ram16k
module ram16k(input clk,
	      input [12:0] 	addr,
	      input [15:0] 	data_in,
	      output [15:0] data_out,
	      input 		we,
	      input 		re);

   // Only low half is available anyway
   ram8k_low r1(.clk(clk),
                .addr(addr[11:0]),
                .data_in(data_in),
                .data_out(data_out),
                .we(we&(~addr[12])),
                .re(re&(~addr[12])));
endmodule
module tiny1_soc(
                 input  clk,
                 input  rst, // external reset button

                 input  RXD,
                 output TXD,

                 output LED1,
                 output LED2,
                 output LED3,
                 output LED4,
                 output LED5
`ifndef ICESTICK
                 ,output LED6,
                 output LED7,
                 output LED8
`endif
                 );

   
	reg [7:0] resetn_counter = 0;
        wire           resetn = &resetn_counter;
  
	always @(posedge clk) begin
		if (!resetn)
			resetn_counter <= resetn_counter + 1;
	end


   
   wire [7:0]           leds;
   wire [7:0]           rleds;

   outpin led0 (.clk(clk), .we(1'b1), .pin(LED1), .wd(leds[0]), .rd(rleds[0]));
   outpin led1 (.clk(clk), .we(1'b1), .pin(LED2), .wd(leds[1]), .rd(rleds[1]));
   outpin led2 (.clk(clk), .we(1'b1), .pin(LED3), .wd(leds[2]), .rd(rleds[2]));
   outpin led3 (.clk(clk), .we(1'b1), .pin(LED4), .wd(leds[3]), .rd(rleds[3]));
   outpin led4 (.clk(clk), .we(1'b1), .pin(LED5), .wd(leds[4]), .rd(rleds[4]));
`ifndef ICESTICK
   outpin led5 (.clk(clk), .we(1'b1), .pin(LED6), .wd(leds[5]), .rd(rleds[5]));
   outpin led6 (.clk(clk), .we(1'b1), .pin(LED7), .wd(leds[6]), .rd(rleds[6]));
   outpin led7 (.clk(clk), .we(1'b1), .pin(LED8), .wd(leds[7]), .rd(rleds[7]));
`endif
   
   wire [7:0]           uart_din;
   wire                 uart_valid;
   wire                 uart_ready;
   wire                 uart_wr;
   wire                 uart_rd;
   
   wire [7:0]           uart_dout;

   tiny1_cpu cpu(.clk(clk),
                 .rst(resetn),
                 .uart_din(uart_din),
                 .uart_valid(uart_valid),
                 .uart_ready(uart_ready),
                 .uart_out(uart_dout),
                 .uart_rd(uart_rd),
                 .uart_wr(uart_wr),
                 .leds(leds)
                 );
   
   wire                 uart_RXD;
   inpin _rcxd(.clk(clk), .pin(RXD), .rd(uart_RXD));

   wire                 uart_busy;

   assign uart_ready = ~uart_busy;
   
   buart _uart (
                .clk(clk),
                .resetq(1'b1),
                .rx(uart_RXD),
                .tx(TXD),
                .rd(uart_rd),
                .wr(uart_wr),
                .valid(uart_valid),
                .busy(uart_busy),
                .tx_data(uart_dout),
                .rx_data(uart_din));
   
endmodule
module SB_RAM2048x2(
	output [1:0] RDATA,
	input        RCLK, RCLKE, RE,
	input  [10:0] RADDR,
	input         WCLK, WCLKE, WE,
	input  [10:0] WADDR,
	input  [1:0] MASK, WDATA
);
	parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
	parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

  wire [15:0] rd;

  SB_RAM40_4K #(
    .WRITE_MODE(3),
    .READ_MODE(3),
    .INIT_0(INIT_0),
    .INIT_1(INIT_1),
    .INIT_2(INIT_2),
    .INIT_3(INIT_3),
    .INIT_4(INIT_4),
    .INIT_5(INIT_5),
    .INIT_6(INIT_6),
    .INIT_7(INIT_7),
    .INIT_8(INIT_8),
    .INIT_9(INIT_9),
    .INIT_A(INIT_10),
    .INIT_B(INIT_11),
    .INIT_C(INIT_12),
    .INIT_D(INIT_13),
    .INIT_E(INIT_14),
    .INIT_F(INIT_15)
  ) _ram (
    .RDATA(rd),
    .RADDR(RADDR),
    .RCLK(RCLK), .RCLKE(RCLKE), .RE(RE),
    .WCLK(WCLK), .WCLKE(WCLKE), .WE(WE),
    .WADDR(WADDR),
    .MASK(16'h0000), .WDATA({4'b0, WDATA[1], 7'b0, WDATA[0], 3'b0}));

  assign RDATA[0] = rd[3];
  assign RDATA[1] = rd[11];

endmodule
module testbench;


   reg clk = 1;
   always #5 clk = ~clk;


   wire LED1, LED2, LED3, LED4, LED5, LED6, LED7, LED8;

   wire [7:0] LEDS;

   assign LEDS = {LED8, LED7, LED6, LED5, LED4, LED3, LED2, LED1};
   

   wire dummy;
   reg  rdummy;
   always @(posedge clk) rdummy <= dummy;
   
   top soc ( .clk(clk),
	     .LED1(LED1),
	     .LED2(LED2),
	     .LED3(LED3),
	     .LED4(LED4),
	     .LED5(LED5),
	     .LED6(LED6),
	     .LED7(LED7),
	     .LED8(LED8),
             .RXD(1'b0),
             .TXD(dummy),
             .rst(1'b1)
             );
   

   	initial begin
	   $monitor("%x", LEDS);
	   repeat (400000) @(posedge clk);
	   $finish;
	end

endmodule
module toy_icache(input clk,
                  input             reset,

                  input [31:0]      ic_addr,
                  input             ic_rq,
                  output reg        ic_data_out_valid,
                  output reg [31:0] ic_data_out,

                  // memory bus interface
                  input [31:0]      data_in, // bus data in
                  input             data_in_ready, // bus data ready
                  output reg        data_rd, // request data read 
                  output reg [31:0] data_address // output data address
                  );
   always @(posedge clk)
     begin
        data_address <= ic_addr;
        data_rd <= ic_rq;
        ic_data_out <= data_in;
        ic_data_out_valid <= data_in_ready;
     end

endmodule
module vram(input clk,
	    
	    input [12:0]     p1_addr,
	    input [7:0]      p1_data,
	    input 	     p1_we,

	    input [12:0]     p2_addr,
	    output reg [7:0] p2_data);

   reg [7:0] 		 mem[0:(3*2048)-1];

   always @(posedge clk)
     begin
	if (p1_we) begin
	   mem[p1_addr] <= p1_data;
	end
	p2_data <= mem[p2_addr];
     end

endmodule
module vgatop(input clk, // 100MHz clk
	      input        rst,
	      input        clk25mhz,

	      output       hsync,
	      output       vsync,
	      output       rgb,

	      input [12:0] vmem_in_addr,
	      input [7:0]  vmem_in_data,
	      input        vmem_we);


   wire [12:0] 		   vmem_out_addr;
   wire [7:0] 		   vmem_out_data;
   
   vram vram1(.clk(clk),

	      .p1_addr(vmem_in_addr),
	      .p1_data(vmem_in_data),
	      .p1_we(vmem_we),

	      .p2_addr(vmem_out_addr),
	      .p2_data(vmem_out_data)
	      );

   vga vga1(.clk(clk),
	    .rst(rst),
	    .clk25mhz(clk25mhz),
	    
	    .vmem_data(vmem_out_data),
	    .vmem_addr(vmem_out_addr),
	    
	    .hsync(hsync),
	    .vsync(vsync),
	    .rgb(rgb));

endmodule
module toyblockram (input         clk,
                    
                    input [31:0]  addr_a,
                    output [31:0] data_a,
                    input [31:0]  datain_a,
                    input         wr_a,
                    
                    input [31:0]  addr_b,
                    output [31:0] data_b
                    );

   parameter RAM_DEPTH = `RAM_DEPTH;

   reg [31:0] mem [0:RAM_DEPTH-1];
   assign data_a = wr_a?datain_a:mem[addr_a];
   assign data_b = mem[addr_b];

   // Expect 2-port (1rw+1ro) to be inferred
   always @(posedge clk)
     begin
        if (wr_a) begin
           mem[addr_a] <= datain_a;
           `ifdef DEBUG
           $display("STACK: [%x] <- %x",addr_a, datain_a);
           `endif
        end
     end

endmodule // toyblockram
module toyblockram (input         clk,
                    
                    input [31:0]      addr_a,
                    output reg [31:0] data_a,
                    input [31:0]      datain_a,
                    input             wr_a,
                    
                    input [31:0]      addr_b,
                    output reg [31:0] data_b
                    );

   parameter RAM_DEPTH = `RAM_DEPTH;

   (* RAM_STYLE="BLOCK" *)
   reg [31:0] mem [0:RAM_DEPTH-1];
 
   // Expect 2-port (1rw+1ro) to be inferred
   always @(posedge clk)
     begin
        if (wr_a) begin
           mem[addr_a] <= datain_a;
           data_a <= datain_a;
        end else data_a <= mem[addr_a];
        data_b <= mem[addr_b];
     end

endmodule // toyblockram
module hlsblockram (input         clk,
                    
                    input [BITWIDTH-1:0]      readaddr1,
                    output reg [BITWIDTH-1:0] readout1,
                    input [BITWIDTH-1:0]      writeaddr1,
                    input [BITWIDTH-1:0]      writein1,
                    input                     we
                    );
   

   parameter SIZE = 32;
   parameter BITWIDTH = 32;
   
   
   reg [BITWIDTH-1:0] mem [0:SIZE-1];
 
   // Expect 2-port (1ro+1wo) to be inferred
   always @(posedge clk)
     begin
        if (we) begin
           mem[writeaddr1] = writein1;
        end
        readout1 <= mem[readaddr1];
     end

endmodule // toyblockram
module fifo(input             clk,
            input             reset,

            input [31:0]      data_in,
            input             data_in_wr,
            
            output reg [31:0] data_out,
            input             data_out_en,

            output reg        full,
            output reg        empty
            );

   parameter DEBUG = 0;
   

   reg [`BUF_WIDTH :0]        fifo_counter;
   reg [`BUF_WIDTH -1:0]      rd_ptr, wr_ptr;           // pointer to read and write addresses  
   reg [31:0]                 buf_mem[`BUF_SIZE -1 : 0]; //  

   always @(fifo_counter)
     begin
        empty = (fifo_counter==0);
        full = (fifo_counter== `BUF_SIZE);
     end

   always @(posedge clk)
     begin
        if( !reset )
          fifo_counter <= 0;

        else if( (!full && data_in_wr) && 
                 ( !empty && data_out_en ) )
          fifo_counter <= fifo_counter;

        else if( !full && data_in_wr )
          fifo_counter <= fifo_counter + 1;

        else if( !empty && data_out_en )
          fifo_counter <= fifo_counter - 1;
        else
          fifo_counter <= fifo_counter;
     end

   always @( posedge clk)
     begin
        if( !reset )
          data_out <= 0;
        else
          begin
             if( data_out_en && !empty ) begin
                if (DEBUG)
                  $display("FIFO OUT -> [%x]",  buf_mem[rd_ptr]);
                data_out <= buf_mem[rd_ptr];
             end
             else
               data_out <= data_out;
          end
     end

   always @(posedge clk)
     begin
        
        if( data_in_wr && !full ) begin
           if(DEBUG)
             $display("FIFO IN <- [%x]", data_in);
          buf_mem[ wr_ptr ] <= data_in;
        end
        
        else
          buf_mem[ wr_ptr ] <= buf_mem[ wr_ptr ];
     end
   
   always@(posedge clk)
     begin
        if( !reset )
          begin
             wr_ptr <= 0;
             rd_ptr <= 0;
          end
        else
          begin
             if( !full && data_in_wr )    wr_ptr <= wr_ptr + 1;
             else  wr_ptr <= wr_ptr;
             
             if( !empty && data_out_en )   rd_ptr <= rd_ptr + 1;
             else rd_ptr <= rd_ptr;
          end
     end
endmodule
module idivmodhw(input clk,
                 input         reset,

                 input         rq,
                 
                 input [31:0]  dividend,
                 input [31:0]  divisor,

                 output [31:0] div_out,
                 output [31:0] div_mod,
                 output        ack);
   
   reg [31:0]                  div_mod;
   reg [31:0]                  div_out;
   reg                         ack;


   reg signed [31:0]           ndividend;
   reg signed [31:0]           ndivisor;
   reg signed [31:0]           nq;
   
   reg signed [31:0]           nbit;
   reg signed [15:0]           np;

   reg [3:0]                   state;
   
   parameter S_IDLE = 0;
   parameter S_LOOP0 = 1;
   parameter S_POSTLOOP0 = 2;
   parameter S_LOOP1 = 3;
   parameter S_POSTLOOP1 = 4;
   
   always @(posedge clk)
     if(!reset) begin
        ack <= 0;
        div_out <= 0;
        div_mod <= 0;
        ndividend <= 0;
        ndivisor <= 0;
        nbit <= 0;
        state <= S_IDLE;
        nq <= 0;
        np <= 0;
     end else begin // if (!reset)
        case(state)
          S_IDLE: if (rq) begin
             nq <= 0;
             np <= 32'hffffffff;
             ndividend <= dividend;
             ndivisor <= divisor;
             nbit <= 1;
             state <= S_LOOP0;
             ack <= 0;
          end
          S_LOOP0: if (ndivisor < ndividend) begin
             ndivisor <= ndivisor << 1;
             np <= np + 1;
             nbit <= nbit << 1;
          end else state <= S_POSTLOOP0;
          S_POSTLOOP0: begin
             nbit <= nbit >> 1;
             ndivisor <= ndivisor >> 1;
             state <= S_LOOP1;
          end
          S_LOOP1: if (np >= 0) begin
             if (ndividend >= ndivisor) begin
                nq <= nq + nbit;
                ndividend <= ndividend - ndivisor;
             end
             ndivisor <= ndivisor >> 1;
             np <= np - 1;
             nbit <= nbit >> 1;
          end else state <= S_POSTLOOP1;
          S_POSTLOOP1: begin
             if (dividend == divisor) begin
                div_out <= nq + 1;
                div_mod <= 0;
             end else begin
                div_out <= nq;
                div_mod <= ndividend;
             end
             ack <= 1;
             state <= S_IDLE;
          end
        endcase
     end

   

endmodule
module op_submdl_logsinrom (
    //master clock
    input   wire            i_EMUCLK, //emulator master clock

    //clock enable
    input   wire            i_CEN_n, //positive edge clock enable for emulation

    input   wire    [4:0]   i_ADDR,
    output  reg     [45:0]  o_DATA
);

always @(posedge i_EMUCLK) if(!i_CEN_n) begin
    case(i_ADDR)
        5'd0 : o_DATA <= 46'b000110000010010001000100_0010101010101001010010;
        5'd1 : o_DATA <= 46'b000110000011010000010000_0010010001001101000001;
        5'd2 : o_DATA <= 46'b000110000011010000010011_0010001011001101100000;
        5'd3 : o_DATA <= 46'b000111000001000000000011_0010110001001101110010;
        5'd4 : o_DATA <= 46'b000111000001000000110000_0010111010001101101001;
        5'd5 : o_DATA <= 46'b000111000001010000100110_0010000000101101111010;
        5'd6 : o_DATA <= 46'b000111000001010000110110_0010010011001101011010;
        5'd7 : o_DATA <= 46'b000111000001110000010101_0010111000101111111100;

        5'd8 : o_DATA <= 46'b000111000011100000000111_0010101110001101110111;
        5'd9 : o_DATA <= 46'b000111000011100001010011_1000011101011010100110;
        5'd10: o_DATA <= 46'b000111000011110001100001_1000111100001001111010;
        5'd11: o_DATA <= 46'b000111000011110001110011_1001101011001001110111;
        5'd12: o_DATA <= 46'b010010000101000001000101_1001001000111010110111;
        5'd13: o_DATA <= 46'b010010000101010001000100_1001110001111100101010;
        5'd14: o_DATA <= 46'b010010000101010001010110_1101111110100101000110;
        5'd15: o_DATA <= 46'b010010001110000000100001_1001010110101101111001;

        5'd16: o_DATA <= 46'b010010001110010000100010_1011100101001011101111;
        5'd17: o_DATA <= 46'b010010001110110000011101_1010000001011010110001;
        5'd18: o_DATA <= 46'b010011001100100000011110_1010000010111010111111;
        5'd19: o_DATA <= 46'b010011001100110000101101_1110101110110110000001;
        5'd20: o_DATA <= 46'b010011001110100001101011_1011001010001101110001;
        5'd21: o_DATA <= 46'b010011001110110101101011_0101111001010100001111;
        5'd22: o_DATA <= 46'b011100001000000101011100_0101010101010110010111;
        5'd23: o_DATA <= 46'b011100001000010101011111_0111110101010010111011;

        5'd24: o_DATA <= 46'b011100001011010110100010_1100001000010000011001;
        5'd25: o_DATA <= 46'b011101001001100110010001_1110100100010010010010;
        5'd26: o_DATA <= 46'b011101001011101010010110_0101000000110100100011;
        5'd27: o_DATA <= 46'b101000001001101010110101_1101100001110010011010;
        5'd28: o_DATA <= 46'b101000001011111111110010_0111010100010000111001;
        5'd29: o_DATA <= 46'b101001011111010011001000_1100111001010110100000;
        5'd30: o_DATA <= 46'b101101011101001111101101_1110000100110010100001;
        5'd31: o_DATA <= 46'b111001101111000111101110_0111100001110110100111;
    endcase
end

endmodule
module op_submdl_exprom (
    //master clock
    input   wire            i_EMUCLK, //emulator master clock

    //clock enable
    input   wire            i_CEN_n, //positive edge clock enable for emulation

    input   wire    [4:0]   i_ADDR,
    output  reg     [44:0]  o_DATA
);

always @(posedge i_EMUCLK) if(!i_CEN_n) begin
    case(i_ADDR)
        5'd0 : o_DATA <= 45'b110111111000111111010001_011000000100110011101;
        5'd1 : o_DATA <= 45'b110111111000110100111110_000001100001110110011;
        5'd2 : o_DATA <= 45'b110111111000000111101101_011101110100111011010;
        5'd3 : o_DATA <= 45'b110111111000000111000011_011100000010101010110;
        5'd4 : o_DATA <= 45'b110111111000000100001100_010100000010101011011;
        5'd5 : o_DATA <= 45'b110111010010101010111011_011000111100111011101;
        5'd6 : o_DATA <= 45'b110110010110111011110100_111001011000011000000;
        5'd7 : o_DATA <= 45'b110110010110111001001011_010001001100111011110;

        5'd8 : o_DATA <= 45'b110110010110011010001101_011000101000111011010;
        5'd9 : o_DATA <= 45'b110110010110000011100110_011110010100111010100;
        5'd10: o_DATA <= 45'b110110000111000101111001_010110110100110010101;
        5'd11: o_DATA <= 45'b110100001111100110011110_011111110000110011011;
        5'd12: o_DATA <= 45'b110100001111100110000001_001111001101110111101;
        5'd13: o_DATA <= 45'b110100001001111101101111_010110101010101010001;
        5'd14: o_DATA <= 45'b110100001001111101100000_010110001100110010011;
        5'd15: o_DATA <= 45'b110100001001011010110101_011001110000111010101;

        5'd16: o_DATA <= 45'b110100001001011000011010_001001010101110110111;
        5'd17: o_DATA <= 45'b110100001001001001010100_000000111001110110001;
        5'd18: o_DATA <= 45'b110100000001100011101011_000000011101110110011;
        5'd19: o_DATA <= 45'b110100000001100000101100_001011100001111110101;
        5'd20: o_DATA <= 45'b110100000000100100010011_011011000100110010101;
        5'd21: o_DATA <= 45'b011101000100010111011101_000010101001110110101;
        5'd22: o_DATA <= 45'b011001100110011111110010_000010001101111110011;
        5'd23: o_DATA <= 45'b011001100110011100100111_001001100001110110001;

        5'd24: o_DATA <= 45'b001011101110111110101001_001000000001110101010;
        5'd25: o_DATA <= 45'b001011101110101111000110_000000101101110111000;
        5'd26: o_DATA <= 45'b001011101110101001011001_010001001000110011010;
        5'd27: o_DATA <= 45'b001011101110100000110110_010011000100110010000;
        5'd28: o_DATA <= 45'b001011101110000010110000_001010101001110110001;
        5'd29: o_DATA <= 45'b001011101010010001001111_001010001101110111011;
        5'd30: o_DATA <= 45'b001011101010010001000010_011001000100100000000;
        5'd31: o_DATA <= 45'b001011100010110010001100_000000101001110110000;
    endcase
end

endmodule
module reg_submdl_loreg_decoder #(parameter TARGET_ADDR = 8'h00 ) (
    //master clock
    input   wire            i_EMUCLK, //emulator master clock

    //internal clock
    input   wire            i_phi1_NCEN_n, //negative edge clock enable for emulation

    //address to be decoded
    input   wire    [7:0]   i_ADDR,

    input   wire            i_ADDR_LD,
    input   wire            i_DATA_LD,

    output  wire            o_REG_LD
);

reg             loreg_addr_valid;
always @(posedge i_EMUCLK) begin
    if(!i_phi1_NCEN_n) begin
        loreg_addr_valid <= ((TARGET_ADDR == i_ADDR) & i_ADDR_LD) | (loreg_addr_valid & ~i_ADDR_LD);
    end
end

assign  o_REG_LD = loreg_addr_valid & i_DATA_LD;

endmodule
module fm_raw_fifo (
  clk_core,
  rst_x,
  i_check_address,
  o_hit,
  i_wstrobe,
  i_dt,
  o_full,
  i_renable,
  o_dt,
  o_empty,
  o_dnum
);

// set default parameters
parameter WIDTH = 32;
parameter RANGEE = 4;
localparam DEPTH = 1 << RANGEE;
////////////////////////////
// I/O definition
////////////////////////////
input         clk_core;            // system clock
input         rst_x;          // system reset
input  [WIDTH-1:0] i_check_address;
output        o_hit;
input         i_wstrobe;      // write strobe
input  [WIDTH-1:0] i_dt;      // write data
output        o_full;         // write data full
input         i_renable;      // read enable
output [WIDTH-1:0] o_dt;      // read data
output        o_empty;        // read data empty
output [RANGEE:0] o_dnum;      // written data number

/////////////////////////
//  Register definition
/////////////////////////
reg [RANGEE-1:0] rs_write_counter;
reg [RANGEE-1:0] rs_read_counter;
// data registers
reg [WIDTH-1:0] rs_data_buffer[0:DEPTH-1];
reg [DEPTH-1:0] rs_valid;
/////////////////////////
//  wire definition
/////////////////////////
wire             o_full;
wire             o_empty;
wire [WIDTH-1:0] o_dt;
wire [1:0]       w_status;
wire             w_we;
wire             w_re;
// address compare
wire [DEPTH-1:0] w_hit;
/////////////////////////
//  assign statement
/////////////////////////
assign o_full  = (&rs_valid);
assign o_empty = ~(|rs_valid);
assign o_dt = rs_data_buffer[rs_read_counter];
assign o_dnum = 'd0;
assign w_we = !o_full & i_wstrobe;
assign w_re = i_renable & !o_empty;
assign w_status = {w_re,w_we};
assign o_hit = |w_hit;
////////////////////////
// always statement
///////////////////////
  genvar i;
  generate for (i=0;i<DEPTH;i=i+1) begin : gen_loop
    assign w_hit[i] = rs_valid[i] ? (i_check_address == rs_data_buffer[i]) : 1'b0;
  end
  endgenerate
   
  // write side
  always @(posedge clk_core or negedge rst_x) begin
    if (~rst_x) begin
      rs_write_counter <= 'd0;
    end else begin
      if (w_we) begin
        rs_write_counter <= rs_write_counter + 1'b1;
      end
    end
  end

  always @(posedge clk_core) begin
    if (w_we) begin
      rs_data_buffer[rs_write_counter] <= i_dt;
    end
  end

  // read side
  always @(posedge clk_core or negedge rst_x) begin
    if (~rst_x) begin
      rs_read_counter <= 'd0;
    end else begin
      if (w_re) begin
        rs_read_counter <= rs_read_counter + 1'b1;
      end
    end
  end
  // data valid
  always @(posedge clk_core or negedge rst_x) begin
    if (~rst_x) begin
      rs_valid <= {DEPTH{1'b0}};
    end else begin
      case (w_status)
        2'b01: rs_valid[rs_write_counter] <= 1'b1; // write
        2'b10: rs_valid[rs_read_counter]  <= 1'b0; // read
        2'b11: begin
          rs_valid[rs_write_counter] <= 1'b1; // write
          rs_valid[rs_read_counter]  <= 1'b0; // read
        end
        default:  rs_valid <= rs_valid;      // nothing to do 
      endcase
    end
  end

endmodule
module fm_cmn_cinterface (
  clk_core,
  rst_x,
  // bus side port
  i_bstr,
  i_bdata,
  o_back,
  // internal port
  o_istr,
  o_idata,
  i_iack
);
parameter P_WIDTH = 8;

////////////////////////////
// I/O definitions
////////////////////////////
input         i_bstr;         // input strobe
input  [P_WIDTH-1:0]
              i_bdata;        // input data
output        o_back;         // output acknowledge

output        o_istr;         // output strobe
output [P_WIDTH-1:0]
              o_idata;        // output data
input         i_iack;         // input acknowledge

input         clk_core;            // system clock
input         rst_x;          // system reset

/////////////////////////
//  register definition
/////////////////////////
// input register
reg           r_bstr;
reg    [P_WIDTH-1:0]
              r_bdata;
reg           r_back;

/////////////////////////
//  wire definition
/////////////////////////
wire          w_empty;
/////////////////////////
//  assign statement
/////////////////////////
assign o_istr = !w_empty;
assign o_back = r_back;
/////////////////////////
//  always statement
/////////////////////////
always @(posedge clk_core or negedge rst_x) begin
  if (~rst_x) begin
    r_bstr <= 1'b0;
  end else begin
    r_bstr <= i_bstr;
  end
end

always @(posedge clk_core or negedge rst_x) begin
  if (~rst_x) begin
    r_back <= 1'b0;
  end else begin
    r_back <= i_iack;
  end
end

always @(posedge clk_core) begin
  r_bdata <= i_bdata;
end

/////////////////////////
//  module instanciation
/////////////////////////
// input data fifo
fm_cmn_ififo #(P_WIDTH) u_ififo (
//fm_cmn_bififo #(P_WIDTH,3) fifo (
//  .o_dnum(),
  .i_wstrobe(r_bstr),
  .i_dt(r_bdata),
  .o_full(),
  .i_renable(i_iack),
  .o_dt(o_idata),
  .o_empty(w_empty),
  .clk_core(clk_core),
  .rst_x(rst_x)
);

endmodule
module fm_cmn_dinterface (
  clk_core,
  rst_x,
  // bus side port
  i_bstr,
  i_bdata,
  o_back,
  // internal port
  o_istr,
  o_idata,
  i_iack
);

parameter P_WIDTH = 36;
////////////////////////////
// I/O definitions
////////////////////////////
input         i_bstr;         // input strobe
input  [P_WIDTH-1:0]
              i_bdata;        // input data (Write Data + BE)
output        o_back;         // output acknowledge

output        o_istr;         // output strobe
output [P_WIDTH-1:0]
              o_idata;        // output data
input         i_iack;         // input acknowledge

input         clk_core;            // system clock
input         rst_x;          // system reset

/////////////////////////
//  register definition
/////////////////////////
// input register
reg           r_bstr;
reg    [P_WIDTH-1:0]
              r_bdata;
reg           r_back;

/////////////////////////
//  wire definition
/////////////////////////
wire          w_empty;
/////////////////////////
//  assign statement
/////////////////////////
assign o_istr = !w_empty;
assign o_back = r_back;
/////////////////////////
//  always statement
/////////////////////////
always @(posedge clk_core or negedge rst_x) begin
  if (~rst_x) begin
    r_bstr <= 1'b0;
  end else begin
    r_bstr <= i_bstr;
  end
end

always @(posedge clk_core or negedge rst_x) begin
  if (~rst_x) begin
    r_back <= 1'b0;
  end else begin
    r_back <= i_iack;
  end
end

always @(posedge clk_core) begin
  r_bdata <= i_bdata;
end

/////////////////////////
//  module instanciation
/////////////////////////
// input data fifo
fm_cmn_ififo #(P_WIDTH) u_ififo (  // Write Data + BE
//fm_cmn_bfifo #(P_WIDTH,3) fifo (  // Write Data + BE
//  .o_dnum(),
  .i_wstrobe(r_bstr),
  .i_dt(r_bdata),
  .o_full(),
  .i_renable(i_iack),
  .o_dt(o_idata),
  .o_empty(w_empty),
  .clk_core(clk_core),
  .rst_x(rst_x)
);

endmodule
module fm_cmn_dram_01 (
    clk,
    we,
    a,
    dpra,
    di,
    spo,
    dpo
 );

//////////////////////////////////
// parameter
//////////////////////////////////
    parameter P_WIDTH = 32;
    parameter P_RANGE = 2;
    parameter P_DEPTH = 1 << P_RANGE;
//////////////////////////////////
// I/O port definition
//////////////////////////////////
    input                clk;
    input                we;
    input  [P_RANGE-1:0] a;
    input  [P_RANGE-1:0] dpra;
    input  [P_WIDTH-1:0] di;
    output [P_WIDTH-1:0] spo;
    output [P_WIDTH-1:0] dpo;

//////////////////////////////////
// reg 
//////////////////////////////////
    reg [P_WIDTH-1:0] ram [P_DEPTH-1:0];
    reg [P_WIDTH-1:0] spo;
    reg [P_WIDTH-1:0] dpo;

//////////////////////////////////
// always
//////////////////////////////////
    // port A: write-first
    always @(posedge clk) begin
        if (we) begin
            ram[a] <= di;
            spo <= di;
        end else begin
            spo <= ram[a];
        end
    end

    // port B: read-first
    always @(posedge clk) begin
        dpo <= ram[dpra];
    end
endmodule
module fm_rd_split (
    clk_core,
    rst_x,
    i_req,
    i_adrs,
    i_len,
    o_ack,
    // dram if
    o_req,
    o_adrs,
    o_len,
    i_ack
);
`include "polyphony_params.v"
////////////////////////////
// Parameter definition
////////////////////////////
    parameter P_IDLE      = 'd0;
    parameter P_SECOND    = 'd1;
//////////////////////////////////
// I/O port definition
//////////////////////////////////
    input         clk_core;
    input         rst_x;

    input         i_req;
    input [P_IB_ADDR_WIDTH-1:0]
                  i_adrs;
    input [P_IB_LEN_WIDTH-1:0]
                  i_len;  // 32 burst x 10
    output         o_ack;
    // dram if
    output        o_req;
    output [P_IB_ADDR_WIDTH-1:0]
                  o_adrs;
    output [P_IB_LEN_WIDTH-1:0]
                  o_len;  // 16 burst x 10
    input         i_ack;

//////////////////////////////////
// reg
//////////////////////////////////
    reg    r_state;
    reg    [P_IB_LEN_WIDTH-1:0]
           r_len;
//////////////////////////////////
// wire
//////////////////////////////////
   wire    w_a;
   wire    w_size;
   wire [P_IB_LEN_WIDTH-1:0]
           w_len;  // 16 burst x 10
//////////////////////////////////
// assign
//////////////////////////////////
 assign w_len = i_len - 5'h10;
   
 assign o_req = i_req;
 assign o_len = ((r_state == P_IDLE)&w_size) ? 'd16 :
		((r_state == P_SECOND)&w_size) ? w_len :
        i_len;
   
 assign o_ack = ((r_state == P_SECOND) & i_ack) |
                ((r_state == P_IDLE) & !w_size & i_ack);
 assign w_a = (r_state == P_SECOND);
 assign o_adrs = {i_adrs[P_IB_ADDR_WIDTH-1:5],w_a,4'b0};

 assign w_size = (i_len > 5'h10);
always @(posedge clk_core or negedge rst_x) begin
  if (~rst_x) begin
    r_state <= P_IDLE;
  end else begin
    case (r_state)
      P_IDLE: begin
        if (i_req & i_ack)  begin
          if (w_size) r_state <= P_SECOND;
	end
      end
      P_SECOND: begin
        if (i_ack)  r_state <= P_IDLE;
      end
    endcase
  end
end

endmodule
module fm_cmn_bififo (
  clk_core,
  rst_x,
  i_wstrobe,
  i_dt,
  o_full,
  i_renable,
  o_dt,
  o_empty,
  o_dnum
);

// set default parameters
parameter P_WIDTH = 32;
parameter P_RANGE = 8;
parameter P_DEPTH = 1 << P_RANGE;
////////////////////////////
// I/O definition
////////////////////////////
input         clk_core;       // system clock
input         rst_x;          // system reset
input         i_wstrobe;      // write strobe
input  [P_WIDTH-1:0] i_dt;      // write data
output        o_full;         // write data full
input         i_renable;      // read enable
output [P_WIDTH-1:0] o_dt;      // read data
output        o_empty;        // read data empty
output [P_RANGE:0] o_dnum;      // written data number

/////////////////////////
//  Register definition
/////////////////////////
reg [P_RANGE-1:0] r_write_counter;
reg [P_RANGE-1:0] r_read_counter;
reg [P_RANGE:0]   r_status;
reg               r_sel;
/////////////////////////
//  wire definition
/////////////////////////
wire             o_full;
wire             o_empty;
wire [P_WIDTH-1:0] o_dt;
wire [P_WIDTH-1:0] w_dto;
wire [P_WIDTH-1:0] w_dto_th;
wire [1:0]       w_status;
wire             w_we;
wire             w_re;
wire [P_RANGE-1:0] w_read_counter_inc;
wire [P_RANGE-1:0] w_read_counter;
/////////////////////////
//  assign statement
/////////////////////////
assign o_full  = (r_status == P_DEPTH);
assign o_empty = (r_status == 0);
assign o_dnum = r_status;
assign o_dt = (o_empty) ? 'd0 :
              (r_sel) ? w_dto_th : w_dto;
assign w_read_counter_inc = r_read_counter + 1'b1;
assign w_read_counter = (w_re) ? w_read_counter_inc : r_read_counter;
assign w_we = !o_full & i_wstrobe;
assign w_re = i_renable & !o_empty;
assign w_status = {w_re,w_we};
////////////////////////
// always statement
///////////////////////
  // write side
  always @(posedge clk_core or negedge rst_x) begin
    if (~rst_x) begin
      r_write_counter <= 'd0;
    end else begin
      if (w_we) begin
        r_write_counter <= r_write_counter + 1'b1;
      end
    end
  end

  // read side
  always @(posedge clk_core or negedge rst_x) begin
    if (~rst_x) begin
      r_read_counter <= 'd0;
    end else begin
      if (w_re) begin
        r_read_counter <= r_read_counter + 1'b1;
      end
    end
  end

  // ram output select
  always @(posedge clk_core or negedge rst_x) begin
    if (~rst_x) begin
        r_sel <= 1'b0;
    end else begin
        r_sel <= (r_write_counter == w_read_counter) ? 1'b1 : 1'b0;
    end
  end

  // status counter
  always @(posedge clk_core or negedge rst_x) begin
    if (~rst_x) begin
      r_status <= 'd0;
    end else begin
      case (w_status)
        2'b01:  r_status <= r_status + 1'b1; // write
        2'b10:  r_status <= r_status - 1'b1; // read
        default:  r_status <= r_status;      // nothing to do 
      endcase
    end
  end

///////////////////
// module instance
///////////////////
    fm_cmn_bram_01 #(P_WIDTH, P_RANGE) bram_00 (
        .clk(clk_core),
        .we(w_we),
        .a(r_write_counter),
        .dpra(w_read_counter),
        .di(i_dt),
        .spo(w_dto_th),
        .dpo(w_dto)
    );
endmodule
module fm_cmn_bram_01 (
    clk,
    we,
    a,
    dpra,
    di,
    spo,
    dpo
 );

//////////////////////////////////
// parameter
//////////////////////////////////
    parameter P_WIDTH = 32;
    parameter P_RANGE = 2;
    parameter P_DEPTH = 1 << P_RANGE;
//////////////////////////////////
// I/O port definition
//////////////////////////////////
    input                clk;
    input                we;
    input  [P_RANGE-1:0] a;
    input  [P_RANGE-1:0] dpra;
    input  [P_WIDTH-1:0] di;
    output [P_WIDTH-1:0] spo;
    output [P_WIDTH-1:0] dpo;

//////////////////////////////////
// reg 
//////////////////////////////////
    reg [P_WIDTH-1:0] ram [P_DEPTH-1:0];
    reg [P_WIDTH-1:0] spo;
    reg [P_WIDTH-1:0] dpo;

//////////////////////////////////
// always
//////////////////////////////////
    // port A: write-first
    always @(posedge clk) begin
        if (we) begin
            ram[a] <= di;
            spo <= di;
        end else begin
            spo <= ram[a];
        end
    end

    // port B: read-first
    always @(posedge clk) begin
        dpo <= ram[dpra];
    end
   
endmodule
module fm_cmn_bram_02 (
    clka,
    clkb,
    wea,
    addra,
    addrb,
    dia,
    doa,
    dob
 );

//////////////////////////////////
// parameter
//////////////////////////////////
    parameter P_WIDTH = 32;
    parameter P_RANGE = 2;
    parameter P_DEPTH = 1 << P_RANGE;
//////////////////////////////////
// I/O port definition
//////////////////////////////////
    input                clka;
    input                clkb;
    input                wea;
    input  [P_RANGE-1:0] addra;
    input  [P_RANGE-1:0] addrb;
    input  [P_WIDTH-1:0] dia;
    output [P_WIDTH-1:0] doa;
    output [P_WIDTH-1:0] dob;

//////////////////////////////////
// reg 
//////////////////////////////////
    reg [P_WIDTH-1:0] ram [P_DEPTH-1:0];
    reg [P_WIDTH-1:0] doa;
    reg [P_WIDTH-1:0] dob;

//////////////////////////////////
// always
//////////////////////////////////
    // port A: write-first
    always @(posedge clka) begin
        if (wea) begin
            ram[addra] <= dia;
            doa <= dia;
        end else begin
            doa <= ram[addra];
        end
    end

    // port B: read-first
    always @(posedge clkb) begin
        dob <= ram[addrb];
    end
endmodule
module fm_cmn_bram_00 (
    clk,
    we,
    a,
    dpra,
    di,
    spo,
    dpo
 );

//////////////////////////////////
// parameter
//////////////////////////////////
    parameter P_WIDTH = 32;
    parameter P_RANGE = 2;
    parameter P_DEPTH = 1 << P_RANGE;
//////////////////////////////////
// I/O port definition
//////////////////////////////////
    input                clk;
    input                we;
    input  [P_RANGE-1:0] a;
    input  [P_RANGE-1:0] dpra;
    input  [P_WIDTH-1:0] di;
    output [P_WIDTH-1:0] spo;
    output [P_WIDTH-1:0] dpo;

//////////////////////////////////
// reg 
//////////////////////////////////
    reg [P_WIDTH-1:0] ram [P_DEPTH-1:0];
    reg [P_RANGE-1:0] read_a;
    reg [P_RANGE-1:0] read_dpra;

//////////////////////////////////
// assign 
//////////////////////////////////
    assign spo = ram[read_a];
    assign dpo = ram[read_dpra];
//////////////////////////////////
// always
//////////////////////////////////
    always @(posedge clk) begin
        if (we) ram[a] <= di;
        read_a <= a;
        read_dpra <= dpra;
    end

endmodule
module fm_cmn_fifo (
  clk_core,
  rst_x,
  i_wstrobe,
  i_dt,
  o_full,
  i_renable,
  o_dt,
  o_empty,
  o_dnum
);

// set default parameters
parameter WIDTH = 32;
parameter RANGEE = 2;
parameter DEPTH = 1 << RANGEE;
////////////////////////////
// I/O definition
////////////////////////////
input         clk_core;            // system clock
input         rst_x;          // system reset
input         i_wstrobe;      // write strobe
input  [WIDTH-1:0] i_dt;      // write data
output        o_full;         // write data full
input         i_renable;      // read enable
output [WIDTH-1:0] o_dt;      // read data
output        o_empty;        // read data empty
output [RANGEE:0] o_dnum;      // written data number

/////////////////////////
//  Register definition
/////////////////////////
reg [RANGEE-1:0] rs_write_counter;
reg [RANGEE-1:0] rs_read_counter;
// data registers
reg [WIDTH-1:0] rs_data_buffer[0:DEPTH-1];
reg [RANGEE:0] rs_status;
/////////////////////////
//  wire definition
/////////////////////////
wire             o_full;
wire             o_empty;
wire [WIDTH-1:0] o_dt;
wire [1:0]       w_status;
wire             w_we;
wire             w_re;
/////////////////////////
//  assign statement
/////////////////////////
assign o_full  = (rs_status == DEPTH);
assign o_empty = (rs_status == 0);
assign o_dt = rs_data_buffer[rs_read_counter];
assign o_dnum = rs_status;
assign w_we = !o_full & i_wstrobe;
assign w_re = i_renable & !o_empty;
assign w_status = {w_re,w_we};
////////////////////////
// always statement
///////////////////////
  // write side
  always @(posedge clk_core or negedge rst_x) begin
    if (~rst_x) begin
      rs_write_counter <= 'd0;
    end else begin
      if (w_we) begin
        rs_write_counter <= rs_write_counter + 1'b1;
      end
    end
  end

  always @(posedge clk_core) begin
    if (w_we) begin
      rs_data_buffer[rs_write_counter] <= i_dt;
    end
  end

  // read side
  always @(posedge clk_core or negedge rst_x) begin
    if (~rst_x) begin
      rs_read_counter <= 'd0;
    end else begin
      if (w_re) begin
        rs_read_counter <= rs_read_counter + 1'b1;
      end
    end
  end
  // status counter
  always @(posedge clk_core or negedge rst_x) begin
    if (~rst_x) begin
      rs_status <= 'd0;
    end else begin
      case (w_status)
        2'b01:  rs_status <= rs_status + 1'b1; // write
        2'b10:  rs_status <= rs_status - 1'b1; // read
        default:  rs_status <= rs_status;      // nothing to do 
      endcase
    end
  end

endmodule