module soc_system_mm_interconnect_2 (
		output wire [7:0]  hps_0_f2h_axi_slave_awid,                                            //                                           hps_0_f2h_axi_slave.awid
		output wire [31:0] hps_0_f2h_axi_slave_awaddr,                                          //                                                              .awaddr
		output wire [3:0]  hps_0_f2h_axi_slave_awlen,                                           //                                                              .awlen
		output wire [2:0]  hps_0_f2h_axi_slave_awsize,                                          //                                                              .awsize
		output wire [1:0]  hps_0_f2h_axi_slave_awburst,                                         //                                                              .awburst
		output wire [1:0]  hps_0_f2h_axi_slave_awlock,                                          //                                                              .awlock
		output wire [3:0]  hps_0_f2h_axi_slave_awcache,                                         //                                                              .awcache
		output wire [2:0]  hps_0_f2h_axi_slave_awprot,                                          //                                                              .awprot
		output wire [4:0]  hps_0_f2h_axi_slave_awuser,                                          //                                                              .awuser
		output wire        hps_0_f2h_axi_slave_awvalid,                                         //                                                              .awvalid
		input  wire        hps_0_f2h_axi_slave_awready,                                         //                                                              .awready
		output wire [7:0]  hps_0_f2h_axi_slave_wid,                                             //                                                              .wid
		output wire [63:0] hps_0_f2h_axi_slave_wdata,                                           //                                                              .wdata
		output wire [7:0]  hps_0_f2h_axi_slave_wstrb,                                           //                                                              .wstrb
		output wire        hps_0_f2h_axi_slave_wlast,                                           //                                                              .wlast
		output wire        hps_0_f2h_axi_slave_wvalid,                                          //                                                              .wvalid
		input  wire        hps_0_f2h_axi_slave_wready,                                          //                                                              .wready
		input  wire [7:0]  hps_0_f2h_axi_slave_bid,                                             //                                                              .bid
		input  wire [1:0]  hps_0_f2h_axi_slave_bresp,                                           //                                                              .bresp
		input  wire        hps_0_f2h_axi_slave_bvalid,                                          //                                                              .bvalid
		output wire        hps_0_f2h_axi_slave_bready,                                          //                                                              .bready
		output wire [7:0]  hps_0_f2h_axi_slave_arid,                                            //                                                              .arid
		output wire [31:0] hps_0_f2h_axi_slave_araddr,                                          //                                                              .araddr
		output wire [3:0]  hps_0_f2h_axi_slave_arlen,                                           //                                                              .arlen
		output wire [2:0]  hps_0_f2h_axi_slave_arsize,                                          //                                                              .arsize
		output wire [1:0]  hps_0_f2h_axi_slave_arburst,                                         //                                                              .arburst
		output wire [1:0]  hps_0_f2h_axi_slave_arlock,                                          //                                                              .arlock
		output wire [3:0]  hps_0_f2h_axi_slave_arcache,                                         //                                                              .arcache
		output wire [2:0]  hps_0_f2h_axi_slave_arprot,                                          //                                                              .arprot
		output wire [4:0]  hps_0_f2h_axi_slave_aruser,                                          //                                                              .aruser
		output wire        hps_0_f2h_axi_slave_arvalid,                                         //                                                              .arvalid
		input  wire        hps_0_f2h_axi_slave_arready,                                         //                                                              .arready
		input  wire [7:0]  hps_0_f2h_axi_slave_rid,                                             //                                                              .rid
		input  wire [63:0] hps_0_f2h_axi_slave_rdata,                                           //                                                              .rdata
		input  wire [1:0]  hps_0_f2h_axi_slave_rresp,                                           //                                                              .rresp
		input  wire        hps_0_f2h_axi_slave_rlast,                                           //                                                              .rlast
		input  wire        hps_0_f2h_axi_slave_rvalid,                                          //                                                              .rvalid
		output wire        hps_0_f2h_axi_slave_rready,                                          //                                                              .rready
		input  wire        clk_0_clk_clk,                                                       //                                                     clk_0_clk.clk
		input  wire        hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset,    //    hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset.reset
		input  wire        hps_only_master_clk_reset_reset_bridge_in_reset_reset,               //               hps_only_master_clk_reset_reset_bridge_in_reset.reset
		input  wire        hps_only_master_master_translator_reset_reset_bridge_in_reset_reset, // hps_only_master_master_translator_reset_reset_bridge_in_reset.reset
		input  wire [31:0] hps_only_master_master_address,                                      //                                        hps_only_master_master.address
		output wire        hps_only_master_master_waitrequest,                                  //                                                              .waitrequest
		input  wire [3:0]  hps_only_master_master_byteenable,                                   //                                                              .byteenable
		input  wire        hps_only_master_master_read,                                         //                                                              .read
		output wire [31:0] hps_only_master_master_readdata,                                     //                                                              .readdata
		output wire        hps_only_master_master_readdatavalid,                                //                                                              .readdatavalid
		input  wire        hps_only_master_master_write,                                        //                                                              .write
		input  wire [31:0] hps_only_master_master_writedata                                     //                                                              .writedata
	);

	wire          hps_only_master_master_translator_avalon_universal_master_0_waitrequest;   // hps_only_master_master_agent:av_waitrequest -> hps_only_master_master_translator:uav_waitrequest
	wire   [31:0] hps_only_master_master_translator_avalon_universal_master_0_readdata;      // hps_only_master_master_agent:av_readdata -> hps_only_master_master_translator:uav_readdata
	wire          hps_only_master_master_translator_avalon_universal_master_0_debugaccess;   // hps_only_master_master_translator:uav_debugaccess -> hps_only_master_master_agent:av_debugaccess
	wire   [31:0] hps_only_master_master_translator_avalon_universal_master_0_address;       // hps_only_master_master_translator:uav_address -> hps_only_master_master_agent:av_address
	wire          hps_only_master_master_translator_avalon_universal_master_0_read;          // hps_only_master_master_translator:uav_read -> hps_only_master_master_agent:av_read
	wire    [3:0] hps_only_master_master_translator_avalon_universal_master_0_byteenable;    // hps_only_master_master_translator:uav_byteenable -> hps_only_master_master_agent:av_byteenable
	wire          hps_only_master_master_translator_avalon_universal_master_0_readdatavalid; // hps_only_master_master_agent:av_readdatavalid -> hps_only_master_master_translator:uav_readdatavalid
	wire          hps_only_master_master_translator_avalon_universal_master_0_lock;          // hps_only_master_master_translator:uav_lock -> hps_only_master_master_agent:av_lock
	wire          hps_only_master_master_translator_avalon_universal_master_0_write;         // hps_only_master_master_translator:uav_write -> hps_only_master_master_agent:av_write
	wire   [31:0] hps_only_master_master_translator_avalon_universal_master_0_writedata;     // hps_only_master_master_translator:uav_writedata -> hps_only_master_master_agent:av_writedata
	wire    [2:0] hps_only_master_master_translator_avalon_universal_master_0_burstcount;    // hps_only_master_master_translator:uav_burstcount -> hps_only_master_master_agent:av_burstcount
	wire          hps_only_master_master_agent_cp_valid;                                     // hps_only_master_master_agent:cp_valid -> router:sink_valid
	wire  [117:0] hps_only_master_master_agent_cp_data;                                      // hps_only_master_master_agent:cp_data -> router:sink_data
	wire          hps_only_master_master_agent_cp_ready;                                     // router:sink_ready -> hps_only_master_master_agent:cp_ready
	wire          hps_only_master_master_agent_cp_startofpacket;                             // hps_only_master_master_agent:cp_startofpacket -> router:sink_startofpacket
	wire          hps_only_master_master_agent_cp_endofpacket;                               // hps_only_master_master_agent:cp_endofpacket -> router:sink_endofpacket
	wire          hps_0_f2h_axi_slave_agent_write_rp_valid;                                  // hps_0_f2h_axi_slave_agent:write_rp_valid -> router_001:sink_valid
	wire  [153:0] hps_0_f2h_axi_slave_agent_write_rp_data;                                   // hps_0_f2h_axi_slave_agent:write_rp_data -> router_001:sink_data
	wire          hps_0_f2h_axi_slave_agent_write_rp_ready;                                  // router_001:sink_ready -> hps_0_f2h_axi_slave_agent:write_rp_ready
	wire          hps_0_f2h_axi_slave_agent_write_rp_startofpacket;                          // hps_0_f2h_axi_slave_agent:write_rp_startofpacket -> router_001:sink_startofpacket
	wire          hps_0_f2h_axi_slave_agent_write_rp_endofpacket;                            // hps_0_f2h_axi_slave_agent:write_rp_endofpacket -> router_001:sink_endofpacket
	wire          hps_0_f2h_axi_slave_agent_read_rp_valid;                                   // hps_0_f2h_axi_slave_agent:read_rp_valid -> router_002:sink_valid
	wire  [153:0] hps_0_f2h_axi_slave_agent_read_rp_data;                                    // hps_0_f2h_axi_slave_agent:read_rp_data -> router_002:sink_data
	wire          hps_0_f2h_axi_slave_agent_read_rp_ready;                                   // router_002:sink_ready -> hps_0_f2h_axi_slave_agent:read_rp_ready
	wire          hps_0_f2h_axi_slave_agent_read_rp_startofpacket;                           // hps_0_f2h_axi_slave_agent:read_rp_startofpacket -> router_002:sink_startofpacket
	wire          hps_0_f2h_axi_slave_agent_read_rp_endofpacket;                             // hps_0_f2h_axi_slave_agent:read_rp_endofpacket -> router_002:sink_endofpacket
	wire          router_src_valid;                                                          // router:src_valid -> hps_only_master_master_limiter:cmd_sink_valid
	wire  [117:0] router_src_data;                                                           // router:src_data -> hps_only_master_master_limiter:cmd_sink_data
	wire          router_src_ready;                                                          // hps_only_master_master_limiter:cmd_sink_ready -> router:src_ready
	wire    [1:0] router_src_channel;                                                        // router:src_channel -> hps_only_master_master_limiter:cmd_sink_channel
	wire          router_src_startofpacket;                                                  // router:src_startofpacket -> hps_only_master_master_limiter:cmd_sink_startofpacket
	wire          router_src_endofpacket;                                                    // router:src_endofpacket -> hps_only_master_master_limiter:cmd_sink_endofpacket
	wire  [117:0] hps_only_master_master_limiter_cmd_src_data;                               // hps_only_master_master_limiter:cmd_src_data -> cmd_demux:sink_data
	wire          hps_only_master_master_limiter_cmd_src_ready;                              // cmd_demux:sink_ready -> hps_only_master_master_limiter:cmd_src_ready
	wire    [1:0] hps_only_master_master_limiter_cmd_src_channel;                            // hps_only_master_master_limiter:cmd_src_channel -> cmd_demux:sink_channel
	wire          hps_only_master_master_limiter_cmd_src_startofpacket;                      // hps_only_master_master_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
	wire          hps_only_master_master_limiter_cmd_src_endofpacket;                        // hps_only_master_master_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
	wire          rsp_mux_src_valid;                                                         // rsp_mux:src_valid -> hps_only_master_master_limiter:rsp_sink_valid
	wire  [117:0] rsp_mux_src_data;                                                          // rsp_mux:src_data -> hps_only_master_master_limiter:rsp_sink_data
	wire          rsp_mux_src_ready;                                                         // hps_only_master_master_limiter:rsp_sink_ready -> rsp_mux:src_ready
	wire    [1:0] rsp_mux_src_channel;                                                       // rsp_mux:src_channel -> hps_only_master_master_limiter:rsp_sink_channel
	wire          rsp_mux_src_startofpacket;                                                 // rsp_mux:src_startofpacket -> hps_only_master_master_limiter:rsp_sink_startofpacket
	wire          rsp_mux_src_endofpacket;                                                   // rsp_mux:src_endofpacket -> hps_only_master_master_limiter:rsp_sink_endofpacket
	wire          hps_only_master_master_limiter_rsp_src_valid;                              // hps_only_master_master_limiter:rsp_src_valid -> hps_only_master_master_agent:rp_valid
	wire  [117:0] hps_only_master_master_limiter_rsp_src_data;                               // hps_only_master_master_limiter:rsp_src_data -> hps_only_master_master_agent:rp_data
	wire          hps_only_master_master_limiter_rsp_src_ready;                              // hps_only_master_master_agent:rp_ready -> hps_only_master_master_limiter:rsp_src_ready
	wire    [1:0] hps_only_master_master_limiter_rsp_src_channel;                            // hps_only_master_master_limiter:rsp_src_channel -> hps_only_master_master_agent:rp_channel
	wire          hps_only_master_master_limiter_rsp_src_startofpacket;                      // hps_only_master_master_limiter:rsp_src_startofpacket -> hps_only_master_master_agent:rp_startofpacket
	wire          hps_only_master_master_limiter_rsp_src_endofpacket;                        // hps_only_master_master_limiter:rsp_src_endofpacket -> hps_only_master_master_agent:rp_endofpacket
	wire          cmd_demux_src0_valid;                                                      // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire  [117:0] cmd_demux_src0_data;                                                       // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                                      // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire    [1:0] cmd_demux_src0_channel;                                                    // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                              // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_src1_valid;                                                      // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
	wire  [117:0] cmd_demux_src1_data;                                                       // cmd_demux:src1_data -> cmd_mux_001:sink0_data
	wire          cmd_demux_src1_ready;                                                      // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
	wire    [1:0] cmd_demux_src1_channel;                                                    // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
	wire          cmd_demux_src1_startofpacket;                                              // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire          cmd_demux_src1_endofpacket;                                                // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire          rsp_demux_src0_valid;                                                      // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire  [117:0] rsp_demux_src0_data;                                                       // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                                      // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire    [1:0] rsp_demux_src0_channel;                                                    // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                              // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_001_src0_valid;                                                  // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
	wire  [117:0] rsp_demux_001_src0_data;                                                   // rsp_demux_001:src0_data -> rsp_mux:sink1_data
	wire          rsp_demux_001_src0_ready;                                                  // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
	wire    [1:0] rsp_demux_001_src0_channel;                                                // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
	wire          rsp_demux_001_src0_startofpacket;                                          // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
	wire          rsp_demux_001_src0_endofpacket;                                            // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
	wire          cmd_mux_src_valid;                                                         // cmd_mux:src_valid -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_valid
	wire  [117:0] cmd_mux_src_data;                                                          // cmd_mux:src_data -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_data
	wire          cmd_mux_src_ready;                                                         // hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_ready -> cmd_mux:src_ready
	wire    [1:0] cmd_mux_src_channel;                                                       // cmd_mux:src_channel -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_channel
	wire          cmd_mux_src_startofpacket;                                                 // cmd_mux:src_startofpacket -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_startofpacket
	wire          cmd_mux_src_endofpacket;                                                   // cmd_mux:src_endofpacket -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_endofpacket
	wire          hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_valid;                        // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_valid -> hps_0_f2h_axi_slave_agent:write_cp_valid
	wire  [153:0] hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_data;                         // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_data -> hps_0_f2h_axi_slave_agent:write_cp_data
	wire          hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_ready;                        // hps_0_f2h_axi_slave_agent:write_cp_ready -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_ready
	wire    [1:0] hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_channel;                      // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_channel -> hps_0_f2h_axi_slave_agent:write_cp_channel
	wire          hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_startofpacket;                // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_startofpacket -> hps_0_f2h_axi_slave_agent:write_cp_startofpacket
	wire          hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_endofpacket;                  // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_endofpacket -> hps_0_f2h_axi_slave_agent:write_cp_endofpacket
	wire          cmd_mux_001_src_valid;                                                     // cmd_mux_001:src_valid -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_valid
	wire  [117:0] cmd_mux_001_src_data;                                                      // cmd_mux_001:src_data -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_data
	wire          cmd_mux_001_src_ready;                                                     // hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_ready -> cmd_mux_001:src_ready
	wire    [1:0] cmd_mux_001_src_channel;                                                   // cmd_mux_001:src_channel -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_channel
	wire          cmd_mux_001_src_startofpacket;                                             // cmd_mux_001:src_startofpacket -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_startofpacket
	wire          cmd_mux_001_src_endofpacket;                                               // cmd_mux_001:src_endofpacket -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_endofpacket
	wire          hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_valid;                        // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_valid -> hps_0_f2h_axi_slave_agent:read_cp_valid
	wire  [153:0] hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_data;                         // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_data -> hps_0_f2h_axi_slave_agent:read_cp_data
	wire          hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_ready;                        // hps_0_f2h_axi_slave_agent:read_cp_ready -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_ready
	wire    [1:0] hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_channel;                      // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_channel -> hps_0_f2h_axi_slave_agent:read_cp_channel
	wire          hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_startofpacket;                // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_startofpacket -> hps_0_f2h_axi_slave_agent:read_cp_startofpacket
	wire          hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_endofpacket;                  // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_endofpacket -> hps_0_f2h_axi_slave_agent:read_cp_endofpacket
	wire          router_001_src_valid;                                                      // router_001:src_valid -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_valid
	wire  [153:0] router_001_src_data;                                                       // router_001:src_data -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_data
	wire          router_001_src_ready;                                                      // hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_ready -> router_001:src_ready
	wire    [1:0] router_001_src_channel;                                                    // router_001:src_channel -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_channel
	wire          router_001_src_startofpacket;                                              // router_001:src_startofpacket -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_startofpacket
	wire          router_001_src_endofpacket;                                                // router_001:src_endofpacket -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_endofpacket
	wire          hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_valid;                        // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
	wire  [117:0] hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_data;                         // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_data -> rsp_demux:sink_data
	wire          hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_ready;                        // rsp_demux:sink_ready -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_ready
	wire    [1:0] hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_channel;                      // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
	wire          hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_startofpacket;                // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
	wire          hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_endofpacket;                  // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
	wire          router_002_src_valid;                                                      // router_002:src_valid -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_valid
	wire  [153:0] router_002_src_data;                                                       // router_002:src_data -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_data
	wire          router_002_src_ready;                                                      // hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_ready -> router_002:src_ready
	wire    [1:0] router_002_src_channel;                                                    // router_002:src_channel -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_channel
	wire          router_002_src_startofpacket;                                              // router_002:src_startofpacket -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_startofpacket
	wire          router_002_src_endofpacket;                                                // router_002:src_endofpacket -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_endofpacket
	wire          hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_valid;                        // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_valid -> rsp_demux_001:sink_valid
	wire  [117:0] hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_data;                         // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_data -> rsp_demux_001:sink_data
	wire          hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_ready;                        // rsp_demux_001:sink_ready -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_ready
	wire    [1:0] hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_channel;                      // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_channel -> rsp_demux_001:sink_channel
	wire          hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_startofpacket;                // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_startofpacket -> rsp_demux_001:sink_startofpacket
	wire          hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_endofpacket;                  // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_endofpacket -> rsp_demux_001:sink_endofpacket
	wire    [1:0] hps_only_master_master_limiter_cmd_valid_data;                             // hps_only_master_master_limiter:cmd_src_valid -> cmd_demux:sink_valid

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) hps_only_master_master_translator (
		.clk                    (clk_0_clk_clk),                                                             //                       clk.clk
		.reset                  (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset),       //                     reset.reset
		.uav_address            (hps_only_master_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (hps_only_master_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (hps_only_master_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (hps_only_master_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (hps_only_master_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (hps_only_master_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (hps_only_master_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (hps_only_master_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (hps_only_master_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (hps_only_master_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (hps_only_master_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (hps_only_master_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (hps_only_master_master_waitrequest),                                        //                          .waitrequest
		.av_byteenable          (hps_only_master_master_byteenable),                                         //                          .byteenable
		.av_read                (hps_only_master_master_read),                                               //                          .read
		.av_readdata            (hps_only_master_master_readdata),                                           //                          .readdata
		.av_readdatavalid       (hps_only_master_master_readdatavalid),                                      //                          .readdatavalid
		.av_write               (hps_only_master_master_write),                                              //                          .write
		.av_writedata           (hps_only_master_master_writedata),                                          //                          .writedata
		.av_burstcount          (1'b1),                                                                      //               (terminated)
		.av_beginbursttransfer  (1'b0),                                                                      //               (terminated)
		.av_begintransfer       (1'b0),                                                                      //               (terminated)
		.av_chipselect          (1'b0),                                                                      //               (terminated)
		.av_lock                (1'b0),                                                                      //               (terminated)
		.av_debugaccess         (1'b0),                                                                      //               (terminated)
		.uav_clken              (),                                                                          //               (terminated)
		.av_clken               (1'b1),                                                                      //               (terminated)
		.uav_response           (2'b00),                                                                     //               (terminated)
		.av_response            (),                                                                          //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                      //               (terminated)
		.av_writeresponsevalid  ()                                                                           //               (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (117),
		.PKT_ORI_BURST_SIZE_L      (115),
		.PKT_RESPONSE_STATUS_H     (114),
		.PKT_RESPONSE_STATUS_L     (113),
		.PKT_QOS_H                 (102),
		.PKT_QOS_L                 (102),
		.PKT_DATA_SIDEBAND_H       (100),
		.PKT_DATA_SIDEBAND_L       (100),
		.PKT_ADDR_SIDEBAND_H       (99),
		.PKT_ADDR_SIDEBAND_L       (95),
		.PKT_BURST_TYPE_H          (94),
		.PKT_BURST_TYPE_L          (93),
		.PKT_CACHE_H               (112),
		.PKT_CACHE_L               (109),
		.PKT_THREAD_ID_H           (105),
		.PKT_THREAD_ID_L           (105),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (101),
		.PKT_PROTECTION_H          (108),
		.PKT_PROTECTION_L          (106),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (82),
		.PKT_BYTE_CNT_H            (81),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (103),
		.PKT_SRC_ID_L              (103),
		.PKT_DEST_ID_H             (104),
		.PKT_DEST_ID_L             (104),
		.ST_DATA_W                 (118),
		.ST_CHANNEL_W              (2),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (1),
		.ID                        (0),
		.BURSTWRAP_VALUE           (255),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) hps_only_master_master_agent (
		.clk                   (clk_0_clk_clk),                                                             //       clk.clk
		.reset                 (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset),       // clk_reset.reset
		.av_address            (hps_only_master_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (hps_only_master_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (hps_only_master_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (hps_only_master_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (hps_only_master_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (hps_only_master_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (hps_only_master_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (hps_only_master_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (hps_only_master_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (hps_only_master_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (hps_only_master_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (hps_only_master_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (hps_only_master_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (hps_only_master_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (hps_only_master_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (hps_only_master_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (hps_only_master_master_limiter_rsp_src_valid),                              //        rp.valid
		.rp_data               (hps_only_master_master_limiter_rsp_src_data),                               //          .data
		.rp_channel            (hps_only_master_master_limiter_rsp_src_channel),                            //          .channel
		.rp_startofpacket      (hps_only_master_master_limiter_rsp_src_startofpacket),                      //          .startofpacket
		.rp_endofpacket        (hps_only_master_master_limiter_rsp_src_endofpacket),                        //          .endofpacket
		.rp_ready              (hps_only_master_master_limiter_rsp_src_ready),                              //          .ready
		.av_response           (),                                                                          // (terminated)
		.av_writeresponsevalid ()                                                                           // (terminated)
	);

	altera_merlin_axi_slave_ni #(
		.PKT_QOS_H                   (138),
		.PKT_QOS_L                   (138),
		.PKT_THREAD_ID_H             (141),
		.PKT_THREAD_ID_L             (141),
		.PKT_RESPONSE_STATUS_H       (150),
		.PKT_RESPONSE_STATUS_L       (149),
		.PKT_BEGIN_BURST             (137),
		.PKT_CACHE_H                 (148),
		.PKT_CACHE_L                 (145),
		.PKT_DATA_SIDEBAND_H         (136),
		.PKT_DATA_SIDEBAND_L         (136),
		.PKT_ADDR_SIDEBAND_H         (135),
		.PKT_ADDR_SIDEBAND_L         (131),
		.PKT_BURST_TYPE_H            (130),
		.PKT_BURST_TYPE_L            (129),
		.PKT_PROTECTION_H            (144),
		.PKT_PROTECTION_L            (142),
		.PKT_BURST_SIZE_H            (128),
		.PKT_BURST_SIZE_L            (126),
		.PKT_BURSTWRAP_H             (125),
		.PKT_BURSTWRAP_L             (118),
		.PKT_BYTE_CNT_H              (117),
		.PKT_BYTE_CNT_L              (110),
		.PKT_ADDR_H                  (103),
		.PKT_ADDR_L                  (72),
		.PKT_TRANS_EXCLUSIVE         (109),
		.PKT_TRANS_LOCK              (108),
		.PKT_TRANS_COMPRESSED_READ   (104),
		.PKT_TRANS_POSTED            (105),
		.PKT_TRANS_WRITE             (106),
		.PKT_TRANS_READ              (107),
		.PKT_DATA_H                  (63),
		.PKT_DATA_L                  (0),
		.PKT_BYTEEN_H                (71),
		.PKT_BYTEEN_L                (64),
		.PKT_SRC_ID_H                (139),
		.PKT_SRC_ID_L                (139),
		.PKT_DEST_ID_H               (140),
		.PKT_DEST_ID_L               (140),
		.PKT_ORI_BURST_SIZE_L        (151),
		.PKT_ORI_BURST_SIZE_H        (153),
		.ADDR_USER_WIDTH             (5),
		.DATA_USER_WIDTH             (1),
		.ST_DATA_W                   (154),
		.ADDR_WIDTH                  (32),
		.RDATA_WIDTH                 (64),
		.WDATA_WIDTH                 (64),
		.ST_CHANNEL_W                (2),
		.AXI_SLAVE_ID_W              (8),
		.PASS_ID_TO_SLAVE            (0),
		.AXI_VERSION                 ("AXI3"),
		.WRITE_ACCEPTANCE_CAPABILITY (8),
		.READ_ACCEPTANCE_CAPABILITY  (8)
	) hps_0_f2h_axi_slave_agent (
		.aclk                   (clk_0_clk_clk),                                                     //        clock_sink.clk
		.aresetn                (~hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), //        reset_sink.reset_n
		.read_cp_valid          (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_valid),                //           read_cp.valid
		.read_cp_ready          (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_ready),                //                  .ready
		.read_cp_data           (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_data),                 //                  .data
		.read_cp_channel        (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_channel),              //                  .channel
		.read_cp_startofpacket  (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_startofpacket),        //                  .startofpacket
		.read_cp_endofpacket    (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_endofpacket),          //                  .endofpacket
		.write_cp_ready         (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_ready),                //          write_cp.ready
		.write_cp_valid         (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_valid),                //                  .valid
		.write_cp_data          (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_data),                 //                  .data
		.write_cp_channel       (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_channel),              //                  .channel
		.write_cp_startofpacket (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_startofpacket),        //                  .startofpacket
		.write_cp_endofpacket   (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_endofpacket),          //                  .endofpacket
		.read_rp_ready          (hps_0_f2h_axi_slave_agent_read_rp_ready),                           //           read_rp.ready
		.read_rp_valid          (hps_0_f2h_axi_slave_agent_read_rp_valid),                           //                  .valid
		.read_rp_data           (hps_0_f2h_axi_slave_agent_read_rp_data),                            //                  .data
		.read_rp_startofpacket  (hps_0_f2h_axi_slave_agent_read_rp_startofpacket),                   //                  .startofpacket
		.read_rp_endofpacket    (hps_0_f2h_axi_slave_agent_read_rp_endofpacket),                     //                  .endofpacket
		.write_rp_ready         (hps_0_f2h_axi_slave_agent_write_rp_ready),                          //          write_rp.ready
		.write_rp_valid         (hps_0_f2h_axi_slave_agent_write_rp_valid),                          //                  .valid
		.write_rp_data          (hps_0_f2h_axi_slave_agent_write_rp_data),                           //                  .data
		.write_rp_startofpacket (hps_0_f2h_axi_slave_agent_write_rp_startofpacket),                  //                  .startofpacket
		.write_rp_endofpacket   (hps_0_f2h_axi_slave_agent_write_rp_endofpacket),                    //                  .endofpacket
		.awid                   (hps_0_f2h_axi_slave_awid),                                          // altera_axi_master.awid
		.awaddr                 (hps_0_f2h_axi_slave_awaddr),                                        //                  .awaddr
		.awlen                  (hps_0_f2h_axi_slave_awlen),                                         //                  .awlen
		.awsize                 (hps_0_f2h_axi_slave_awsize),                                        //                  .awsize
		.awburst                (hps_0_f2h_axi_slave_awburst),                                       //                  .awburst
		.awlock                 (hps_0_f2h_axi_slave_awlock),                                        //                  .awlock
		.awcache                (hps_0_f2h_axi_slave_awcache),                                       //                  .awcache
		.awprot                 (hps_0_f2h_axi_slave_awprot),                                        //                  .awprot
		.awuser                 (hps_0_f2h_axi_slave_awuser),                                        //                  .awuser
		.awvalid                (hps_0_f2h_axi_slave_awvalid),                                       //                  .awvalid
		.awready                (hps_0_f2h_axi_slave_awready),                                       //                  .awready
		.wid                    (hps_0_f2h_axi_slave_wid),                                           //                  .wid
		.wdata                  (hps_0_f2h_axi_slave_wdata),                                         //                  .wdata
		.wstrb                  (hps_0_f2h_axi_slave_wstrb),                                         //                  .wstrb
		.wlast                  (hps_0_f2h_axi_slave_wlast),                                         //                  .wlast
		.wvalid                 (hps_0_f2h_axi_slave_wvalid),                                        //                  .wvalid
		.wready                 (hps_0_f2h_axi_slave_wready),                                        //                  .wready
		.bid                    (hps_0_f2h_axi_slave_bid),                                           //                  .bid
		.bresp                  (hps_0_f2h_axi_slave_bresp),                                         //                  .bresp
		.bvalid                 (hps_0_f2h_axi_slave_bvalid),                                        //                  .bvalid
		.bready                 (hps_0_f2h_axi_slave_bready),                                        //                  .bready
		.arid                   (hps_0_f2h_axi_slave_arid),                                          //                  .arid
		.araddr                 (hps_0_f2h_axi_slave_araddr),                                        //                  .araddr
		.arlen                  (hps_0_f2h_axi_slave_arlen),                                         //                  .arlen
		.arsize                 (hps_0_f2h_axi_slave_arsize),                                        //                  .arsize
		.arburst                (hps_0_f2h_axi_slave_arburst),                                       //                  .arburst
		.arlock                 (hps_0_f2h_axi_slave_arlock),                                        //                  .arlock
		.arcache                (hps_0_f2h_axi_slave_arcache),                                       //                  .arcache
		.arprot                 (hps_0_f2h_axi_slave_arprot),                                        //                  .arprot
		.aruser                 (hps_0_f2h_axi_slave_aruser),                                        //                  .aruser
		.arvalid                (hps_0_f2h_axi_slave_arvalid),                                       //                  .arvalid
		.arready                (hps_0_f2h_axi_slave_arready),                                       //                  .arready
		.rid                    (hps_0_f2h_axi_slave_rid),                                           //                  .rid
		.rdata                  (hps_0_f2h_axi_slave_rdata),                                         //                  .rdata
		.rresp                  (hps_0_f2h_axi_slave_rresp),                                         //                  .rresp
		.rlast                  (hps_0_f2h_axi_slave_rlast),                                         //                  .rlast
		.rvalid                 (hps_0_f2h_axi_slave_rvalid),                                        //                  .rvalid
		.rready                 (hps_0_f2h_axi_slave_rready)                                         //                  .rready
	);

	soc_system_mm_interconnect_2_router router (
		.sink_ready         (hps_only_master_master_agent_cp_ready),                               //      sink.ready
		.sink_valid         (hps_only_master_master_agent_cp_valid),                               //          .valid
		.sink_data          (hps_only_master_master_agent_cp_data),                                //          .data
		.sink_startofpacket (hps_only_master_master_agent_cp_startofpacket),                       //          .startofpacket
		.sink_endofpacket   (hps_only_master_master_agent_cp_endofpacket),                         //          .endofpacket
		.clk                (clk_0_clk_clk),                                                       //       clk.clk
		.reset              (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_src_ready),                                                    //       src.ready
		.src_valid          (router_src_valid),                                                    //          .valid
		.src_data           (router_src_data),                                                     //          .data
		.src_channel        (router_src_channel),                                                  //          .channel
		.src_startofpacket  (router_src_startofpacket),                                            //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                               //          .endofpacket
	);

	soc_system_mm_interconnect_2_router_001 router_001 (
		.sink_ready         (hps_0_f2h_axi_slave_agent_write_rp_ready),                         //      sink.ready
		.sink_valid         (hps_0_f2h_axi_slave_agent_write_rp_valid),                         //          .valid
		.sink_data          (hps_0_f2h_axi_slave_agent_write_rp_data),                          //          .data
		.sink_startofpacket (hps_0_f2h_axi_slave_agent_write_rp_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (hps_0_f2h_axi_slave_agent_write_rp_endofpacket),                   //          .endofpacket
		.clk                (clk_0_clk_clk),                                                    //       clk.clk
		.reset              (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_001_src_ready),                                             //       src.ready
		.src_valid          (router_001_src_valid),                                             //          .valid
		.src_data           (router_001_src_data),                                              //          .data
		.src_channel        (router_001_src_channel),                                           //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                                     //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                                        //          .endofpacket
	);

	soc_system_mm_interconnect_2_router_001 router_002 (
		.sink_ready         (hps_0_f2h_axi_slave_agent_read_rp_ready),                          //      sink.ready
		.sink_valid         (hps_0_f2h_axi_slave_agent_read_rp_valid),                          //          .valid
		.sink_data          (hps_0_f2h_axi_slave_agent_read_rp_data),                           //          .data
		.sink_startofpacket (hps_0_f2h_axi_slave_agent_read_rp_startofpacket),                  //          .startofpacket
		.sink_endofpacket   (hps_0_f2h_axi_slave_agent_read_rp_endofpacket),                    //          .endofpacket
		.clk                (clk_0_clk_clk),                                                    //       clk.clk
		.reset              (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_002_src_ready),                                             //       src.ready
		.src_valid          (router_002_src_valid),                                             //          .valid
		.src_data           (router_002_src_data),                                              //          .data
		.src_channel        (router_002_src_channel),                                           //          .channel
		.src_startofpacket  (router_002_src_startofpacket),                                     //          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                                        //          .endofpacket
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (104),
		.PKT_DEST_ID_L             (104),
		.PKT_SRC_ID_H              (103),
		.PKT_SRC_ID_L              (103),
		.PKT_BYTE_CNT_H            (81),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.MAX_OUTSTANDING_RESPONSES (16),
		.PIPELINED                 (0),
		.ST_DATA_W                 (118),
		.ST_CHANNEL_W              (2),
		.VALID_WIDTH               (2),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (1),
		.SUPPORTS_POSTED_WRITES    (1),
		.SUPPORTS_NONPOSTED_WRITES (0),
		.REORDER                   (0)
	) hps_only_master_master_limiter (
		.clk                    (clk_0_clk_clk),                                                       //       clk.clk
		.reset                  (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.cmd_sink_ready         (router_src_ready),                                                    //  cmd_sink.ready
		.cmd_sink_valid         (router_src_valid),                                                    //          .valid
		.cmd_sink_data          (router_src_data),                                                     //          .data
		.cmd_sink_channel       (router_src_channel),                                                  //          .channel
		.cmd_sink_startofpacket (router_src_startofpacket),                                            //          .startofpacket
		.cmd_sink_endofpacket   (router_src_endofpacket),                                              //          .endofpacket
		.cmd_src_ready          (hps_only_master_master_limiter_cmd_src_ready),                        //   cmd_src.ready
		.cmd_src_data           (hps_only_master_master_limiter_cmd_src_data),                         //          .data
		.cmd_src_channel        (hps_only_master_master_limiter_cmd_src_channel),                      //          .channel
		.cmd_src_startofpacket  (hps_only_master_master_limiter_cmd_src_startofpacket),                //          .startofpacket
		.cmd_src_endofpacket    (hps_only_master_master_limiter_cmd_src_endofpacket),                  //          .endofpacket
		.rsp_sink_ready         (rsp_mux_src_ready),                                                   //  rsp_sink.ready
		.rsp_sink_valid         (rsp_mux_src_valid),                                                   //          .valid
		.rsp_sink_channel       (rsp_mux_src_channel),                                                 //          .channel
		.rsp_sink_data          (rsp_mux_src_data),                                                    //          .data
		.rsp_sink_startofpacket (rsp_mux_src_startofpacket),                                           //          .startofpacket
		.rsp_sink_endofpacket   (rsp_mux_src_endofpacket),                                             //          .endofpacket
		.rsp_src_ready          (hps_only_master_master_limiter_rsp_src_ready),                        //   rsp_src.ready
		.rsp_src_valid          (hps_only_master_master_limiter_rsp_src_valid),                        //          .valid
		.rsp_src_data           (hps_only_master_master_limiter_rsp_src_data),                         //          .data
		.rsp_src_channel        (hps_only_master_master_limiter_rsp_src_channel),                      //          .channel
		.rsp_src_startofpacket  (hps_only_master_master_limiter_rsp_src_startofpacket),                //          .startofpacket
		.rsp_src_endofpacket    (hps_only_master_master_limiter_rsp_src_endofpacket),                  //          .endofpacket
		.cmd_src_valid          (hps_only_master_master_limiter_cmd_valid_data)                        // cmd_valid.data
	);

	soc_system_mm_interconnect_2_cmd_demux cmd_demux (
		.clk                (clk_0_clk_clk),                                                       //        clk.clk
		.reset              (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), //  clk_reset.reset
		.sink_ready         (hps_only_master_master_limiter_cmd_src_ready),                        //       sink.ready
		.sink_channel       (hps_only_master_master_limiter_cmd_src_channel),                      //           .channel
		.sink_data          (hps_only_master_master_limiter_cmd_src_data),                         //           .data
		.sink_startofpacket (hps_only_master_master_limiter_cmd_src_startofpacket),                //           .startofpacket
		.sink_endofpacket   (hps_only_master_master_limiter_cmd_src_endofpacket),                  //           .endofpacket
		.sink_valid         (hps_only_master_master_limiter_cmd_valid_data),                       // sink_valid.data
		.src0_ready         (cmd_demux_src0_ready),                                                //       src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                                //           .valid
		.src0_data          (cmd_demux_src0_data),                                                 //           .data
		.src0_channel       (cmd_demux_src0_channel),                                              //           .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                                        //           .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket),                                          //           .endofpacket
		.src1_ready         (cmd_demux_src1_ready),                                                //       src1.ready
		.src1_valid         (cmd_demux_src1_valid),                                                //           .valid
		.src1_data          (cmd_demux_src1_data),                                                 //           .data
		.src1_channel       (cmd_demux_src1_channel),                                              //           .channel
		.src1_startofpacket (cmd_demux_src1_startofpacket),                                        //           .startofpacket
		.src1_endofpacket   (cmd_demux_src1_endofpacket)                                           //           .endofpacket
	);

	soc_system_mm_interconnect_2_cmd_mux cmd_mux (
		.clk                 (clk_0_clk_clk),                                                    //       clk.clk
		.reset               (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                                                //       src.ready
		.src_valid           (cmd_mux_src_valid),                                                //          .valid
		.src_data            (cmd_mux_src_data),                                                 //          .data
		.src_channel         (cmd_mux_src_channel),                                              //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                                        //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                                          //          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                                             //     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                                             //          .valid
		.sink0_channel       (cmd_demux_src0_channel),                                           //          .channel
		.sink0_data          (cmd_demux_src0_data),                                              //          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),                                     //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket)                                        //          .endofpacket
	);

	soc_system_mm_interconnect_2_cmd_mux cmd_mux_001 (
		.clk                 (clk_0_clk_clk),                                                    //       clk.clk
		.reset               (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                                            //       src.ready
		.src_valid           (cmd_mux_001_src_valid),                                            //          .valid
		.src_data            (cmd_mux_001_src_data),                                             //          .data
		.src_channel         (cmd_mux_001_src_channel),                                          //          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),                                    //          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),                                      //          .endofpacket
		.sink0_ready         (cmd_demux_src1_ready),                                             //     sink0.ready
		.sink0_valid         (cmd_demux_src1_valid),                                             //          .valid
		.sink0_channel       (cmd_demux_src1_channel),                                           //          .channel
		.sink0_data          (cmd_demux_src1_data),                                              //          .data
		.sink0_startofpacket (cmd_demux_src1_startofpacket),                                     //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src1_endofpacket)                                        //          .endofpacket
	);

	soc_system_mm_interconnect_2_rsp_demux rsp_demux (
		.clk                (clk_0_clk_clk),                                                    //       clk.clk
		.reset              (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_ready),               //      sink.ready
		.sink_channel       (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_channel),             //          .channel
		.sink_data          (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_data),                //          .data
		.sink_startofpacket (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_endofpacket),         //          .endofpacket
		.sink_valid         (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_valid),               //          .valid
		.src0_ready         (rsp_demux_src0_ready),                                             //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                             //          .valid
		.src0_data          (rsp_demux_src0_data),                                              //          .data
		.src0_channel       (rsp_demux_src0_channel),                                           //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                                     //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket)                                        //          .endofpacket
	);

	soc_system_mm_interconnect_2_rsp_demux rsp_demux_001 (
		.clk                (clk_0_clk_clk),                                                    //       clk.clk
		.reset              (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_ready),               //      sink.ready
		.sink_channel       (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_channel),             //          .channel
		.sink_data          (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_data),                //          .data
		.sink_startofpacket (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_endofpacket),         //          .endofpacket
		.sink_valid         (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_valid),               //          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                                         //      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                                         //          .valid
		.src0_data          (rsp_demux_001_src0_data),                                          //          .data
		.src0_channel       (rsp_demux_001_src0_channel),                                       //          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),                                 //          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket)                                    //          .endofpacket
	);

	soc_system_mm_interconnect_2_rsp_mux rsp_mux (
		.clk                 (clk_0_clk_clk),                                                       //       clk.clk
		.reset               (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                                   //       src.ready
		.src_valid           (rsp_mux_src_valid),                                                   //          .valid
		.src_data            (rsp_mux_src_data),                                                    //          .data
		.src_channel         (rsp_mux_src_channel),                                                 //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                                           //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                                             //          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                                                //     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                                                //          .valid
		.sink0_channel       (rsp_demux_src0_channel),                                              //          .channel
		.sink0_data          (rsp_demux_src0_data),                                                 //          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),                                        //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket),                                          //          .endofpacket
		.sink1_ready         (rsp_demux_001_src0_ready),                                            //     sink1.ready
		.sink1_valid         (rsp_demux_001_src0_valid),                                            //          .valid
		.sink1_channel       (rsp_demux_001_src0_channel),                                          //          .channel
		.sink1_data          (rsp_demux_001_src0_data),                                             //          .data
		.sink1_startofpacket (rsp_demux_001_src0_startofpacket),                                    //          .startofpacket
		.sink1_endofpacket   (rsp_demux_001_src0_endofpacket)                                       //          .endofpacket
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (67),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (81),
		.IN_PKT_BYTE_CNT_L             (74),
		.IN_PKT_TRANS_COMPRESSED_READ  (68),
		.IN_PKT_TRANS_WRITE            (70),
		.IN_PKT_BURSTWRAP_H            (89),
		.IN_PKT_BURSTWRAP_L            (82),
		.IN_PKT_BURST_SIZE_H           (92),
		.IN_PKT_BURST_SIZE_L           (90),
		.IN_PKT_RESPONSE_STATUS_H      (114),
		.IN_PKT_RESPONSE_STATUS_L      (113),
		.IN_PKT_TRANS_EXCLUSIVE        (73),
		.IN_PKT_BURST_TYPE_H           (94),
		.IN_PKT_BURST_TYPE_L           (93),
		.IN_PKT_ORI_BURST_SIZE_L       (115),
		.IN_PKT_ORI_BURST_SIZE_H       (117),
		.IN_ST_DATA_W                  (118),
		.OUT_PKT_ADDR_H                (103),
		.OUT_PKT_ADDR_L                (72),
		.OUT_PKT_DATA_H                (63),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (71),
		.OUT_PKT_BYTEEN_L              (64),
		.OUT_PKT_BYTE_CNT_H            (117),
		.OUT_PKT_BYTE_CNT_L            (110),
		.OUT_PKT_TRANS_COMPRESSED_READ (104),
		.OUT_PKT_BURST_SIZE_H          (128),
		.OUT_PKT_BURST_SIZE_L          (126),
		.OUT_PKT_RESPONSE_STATUS_H     (150),
		.OUT_PKT_RESPONSE_STATUS_L     (149),
		.OUT_PKT_TRANS_EXCLUSIVE       (109),
		.OUT_PKT_BURST_TYPE_H          (130),
		.OUT_PKT_BURST_TYPE_L          (129),
		.OUT_PKT_ORI_BURST_SIZE_L      (151),
		.OUT_PKT_ORI_BURST_SIZE_H      (153),
		.OUT_ST_DATA_W                 (154),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (0),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) hps_0_f2h_axi_slave_wr_cmd_width_adapter (
		.clk                  (clk_0_clk_clk),                                                    //       clk.clk
		.reset                (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_valid             (cmd_mux_src_valid),                                                //      sink.valid
		.in_channel           (cmd_mux_src_channel),                                              //          .channel
		.in_startofpacket     (cmd_mux_src_startofpacket),                                        //          .startofpacket
		.in_endofpacket       (cmd_mux_src_endofpacket),                                          //          .endofpacket
		.in_ready             (cmd_mux_src_ready),                                                //          .ready
		.in_data              (cmd_mux_src_data),                                                 //          .data
		.out_endofpacket      (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_endofpacket),         //       src.endofpacket
		.out_data             (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_data),                //          .data
		.out_channel          (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_channel),             //          .channel
		.out_valid            (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_valid),               //          .valid
		.out_ready            (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_ready),               //          .ready
		.out_startofpacket    (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_startofpacket),       //          .startofpacket
		.in_command_size_data (3'b000)                                                            // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (67),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (81),
		.IN_PKT_BYTE_CNT_L             (74),
		.IN_PKT_TRANS_COMPRESSED_READ  (68),
		.IN_PKT_TRANS_WRITE            (70),
		.IN_PKT_BURSTWRAP_H            (89),
		.IN_PKT_BURSTWRAP_L            (82),
		.IN_PKT_BURST_SIZE_H           (92),
		.IN_PKT_BURST_SIZE_L           (90),
		.IN_PKT_RESPONSE_STATUS_H      (114),
		.IN_PKT_RESPONSE_STATUS_L      (113),
		.IN_PKT_TRANS_EXCLUSIVE        (73),
		.IN_PKT_BURST_TYPE_H           (94),
		.IN_PKT_BURST_TYPE_L           (93),
		.IN_PKT_ORI_BURST_SIZE_L       (115),
		.IN_PKT_ORI_BURST_SIZE_H       (117),
		.IN_ST_DATA_W                  (118),
		.OUT_PKT_ADDR_H                (103),
		.OUT_PKT_ADDR_L                (72),
		.OUT_PKT_DATA_H                (63),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (71),
		.OUT_PKT_BYTEEN_L              (64),
		.OUT_PKT_BYTE_CNT_H            (117),
		.OUT_PKT_BYTE_CNT_L            (110),
		.OUT_PKT_TRANS_COMPRESSED_READ (104),
		.OUT_PKT_BURST_SIZE_H          (128),
		.OUT_PKT_BURST_SIZE_L          (126),
		.OUT_PKT_RESPONSE_STATUS_H     (150),
		.OUT_PKT_RESPONSE_STATUS_L     (149),
		.OUT_PKT_TRANS_EXCLUSIVE       (109),
		.OUT_PKT_BURST_TYPE_H          (130),
		.OUT_PKT_BURST_TYPE_L          (129),
		.OUT_PKT_ORI_BURST_SIZE_L      (151),
		.OUT_PKT_ORI_BURST_SIZE_H      (153),
		.OUT_ST_DATA_W                 (154),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (0),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) hps_0_f2h_axi_slave_rd_cmd_width_adapter (
		.clk                  (clk_0_clk_clk),                                                    //       clk.clk
		.reset                (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_valid             (cmd_mux_001_src_valid),                                            //      sink.valid
		.in_channel           (cmd_mux_001_src_channel),                                          //          .channel
		.in_startofpacket     (cmd_mux_001_src_startofpacket),                                    //          .startofpacket
		.in_endofpacket       (cmd_mux_001_src_endofpacket),                                      //          .endofpacket
		.in_ready             (cmd_mux_001_src_ready),                                            //          .ready
		.in_data              (cmd_mux_001_src_data),                                             //          .data
		.out_endofpacket      (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_endofpacket),         //       src.endofpacket
		.out_data             (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_data),                //          .data
		.out_channel          (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_channel),             //          .channel
		.out_valid            (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_valid),               //          .valid
		.out_ready            (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_ready),               //          .ready
		.out_startofpacket    (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_startofpacket),       //          .startofpacket
		.in_command_size_data (3'b000)                                                            // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (103),
		.IN_PKT_ADDR_L                 (72),
		.IN_PKT_DATA_H                 (63),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (71),
		.IN_PKT_BYTEEN_L               (64),
		.IN_PKT_BYTE_CNT_H             (117),
		.IN_PKT_BYTE_CNT_L             (110),
		.IN_PKT_TRANS_COMPRESSED_READ  (104),
		.IN_PKT_TRANS_WRITE            (106),
		.IN_PKT_BURSTWRAP_H            (125),
		.IN_PKT_BURSTWRAP_L            (118),
		.IN_PKT_BURST_SIZE_H           (128),
		.IN_PKT_BURST_SIZE_L           (126),
		.IN_PKT_RESPONSE_STATUS_H      (150),
		.IN_PKT_RESPONSE_STATUS_L      (149),
		.IN_PKT_TRANS_EXCLUSIVE        (109),
		.IN_PKT_BURST_TYPE_H           (130),
		.IN_PKT_BURST_TYPE_L           (129),
		.IN_PKT_ORI_BURST_SIZE_L       (151),
		.IN_PKT_ORI_BURST_SIZE_H       (153),
		.IN_ST_DATA_W                  (154),
		.OUT_PKT_ADDR_H                (67),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (81),
		.OUT_PKT_BYTE_CNT_L            (74),
		.OUT_PKT_TRANS_COMPRESSED_READ (68),
		.OUT_PKT_BURST_SIZE_H          (92),
		.OUT_PKT_BURST_SIZE_L          (90),
		.OUT_PKT_RESPONSE_STATUS_H     (114),
		.OUT_PKT_RESPONSE_STATUS_L     (113),
		.OUT_PKT_TRANS_EXCLUSIVE       (73),
		.OUT_PKT_BURST_TYPE_H          (94),
		.OUT_PKT_BURST_TYPE_L          (93),
		.OUT_PKT_ORI_BURST_SIZE_L      (115),
		.OUT_PKT_ORI_BURST_SIZE_H      (117),
		.OUT_ST_DATA_W                 (118),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (1),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) hps_0_f2h_axi_slave_wr_rsp_width_adapter (
		.clk                  (clk_0_clk_clk),                                                    //       clk.clk
		.reset                (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_valid             (router_001_src_valid),                                             //      sink.valid
		.in_channel           (router_001_src_channel),                                           //          .channel
		.in_startofpacket     (router_001_src_startofpacket),                                     //          .startofpacket
		.in_endofpacket       (router_001_src_endofpacket),                                       //          .endofpacket
		.in_ready             (router_001_src_ready),                                             //          .ready
		.in_data              (router_001_src_data),                                              //          .data
		.out_endofpacket      (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_endofpacket),         //       src.endofpacket
		.out_data             (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_data),                //          .data
		.out_channel          (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_channel),             //          .channel
		.out_valid            (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_valid),               //          .valid
		.out_ready            (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_ready),               //          .ready
		.out_startofpacket    (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_startofpacket),       //          .startofpacket
		.in_command_size_data (3'b000)                                                            // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (103),
		.IN_PKT_ADDR_L                 (72),
		.IN_PKT_DATA_H                 (63),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (71),
		.IN_PKT_BYTEEN_L               (64),
		.IN_PKT_BYTE_CNT_H             (117),
		.IN_PKT_BYTE_CNT_L             (110),
		.IN_PKT_TRANS_COMPRESSED_READ  (104),
		.IN_PKT_TRANS_WRITE            (106),
		.IN_PKT_BURSTWRAP_H            (125),
		.IN_PKT_BURSTWRAP_L            (118),
		.IN_PKT_BURST_SIZE_H           (128),
		.IN_PKT_BURST_SIZE_L           (126),
		.IN_PKT_RESPONSE_STATUS_H      (150),
		.IN_PKT_RESPONSE_STATUS_L      (149),
		.IN_PKT_TRANS_EXCLUSIVE        (109),
		.IN_PKT_BURST_TYPE_H           (130),
		.IN_PKT_BURST_TYPE_L           (129),
		.IN_PKT_ORI_BURST_SIZE_L       (151),
		.IN_PKT_ORI_BURST_SIZE_H       (153),
		.IN_ST_DATA_W                  (154),
		.OUT_PKT_ADDR_H                (67),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (81),
		.OUT_PKT_BYTE_CNT_L            (74),
		.OUT_PKT_TRANS_COMPRESSED_READ (68),
		.OUT_PKT_BURST_SIZE_H          (92),
		.OUT_PKT_BURST_SIZE_L          (90),
		.OUT_PKT_RESPONSE_STATUS_H     (114),
		.OUT_PKT_RESPONSE_STATUS_L     (113),
		.OUT_PKT_TRANS_EXCLUSIVE       (73),
		.OUT_PKT_BURST_TYPE_H          (94),
		.OUT_PKT_BURST_TYPE_L          (93),
		.OUT_PKT_ORI_BURST_SIZE_L      (115),
		.OUT_PKT_ORI_BURST_SIZE_H      (117),
		.OUT_ST_DATA_W                 (118),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (1),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) hps_0_f2h_axi_slave_rd_rsp_width_adapter (
		.clk                  (clk_0_clk_clk),                                                    //       clk.clk
		.reset                (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_valid             (router_002_src_valid),                                             //      sink.valid
		.in_channel           (router_002_src_channel),                                           //          .channel
		.in_startofpacket     (router_002_src_startofpacket),                                     //          .startofpacket
		.in_endofpacket       (router_002_src_endofpacket),                                       //          .endofpacket
		.in_ready             (router_002_src_ready),                                             //          .ready
		.in_data              (router_002_src_data),                                              //          .data
		.out_endofpacket      (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_endofpacket),         //       src.endofpacket
		.out_data             (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_data),                //          .data
		.out_channel          (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_channel),             //          .channel
		.out_valid            (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_valid),               //          .valid
		.out_ready            (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_ready),               //          .ready
		.out_startofpacket    (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_startofpacket),       //          .startofpacket
		.in_command_size_data (3'b000)                                                            // (terminated)
	);

endmodule