dakies/OSS_Verilog huggingface dataset:
module jesd204_scrambler #(
  parameter WIDTH = 32,
  parameter DESCRAMBLE = 0
) (
  input clk,
  input reset,

  input enable,

  input [WIDTH-1:0] data_in,
  output [WIDTH-1:0] data_out
);

reg [14:0] state = 'h7f80;
reg [WIDTH-1:0] swizzle_out;
wire [WIDTH-1:0] swizzle_in;
wire [WIDTH-1:0] feedback;
wire [WIDTH-1+15:0] full_state;

generate
genvar i;
for (i = 0; i < WIDTH / 8; i = i + 1) begin: gen_swizzle
  assign swizzle_in[WIDTH-1-i*8:WIDTH-i*8-8] = data_in[i*8+7:i*8];
  assign data_out[WIDTH-1-i*8:WIDTH-i*8-8] = swizzle_out[i*8+7:i*8];
end
endgenerate

assign full_state = {state,DESCRAMBLE ? swizzle_in : feedback};
assign feedback = full_state[WIDTH-1+15:15] ^ full_state[WIDTH-1+14:14] ^ swizzle_in;

always @(*) begin
  if (enable == 1'b0) begin
    swizzle_out = swizzle_in;
  end else begin
    swizzle_out = feedback;
  end
end

always @(posedge clk) begin
  if (reset == 1'b1) begin
    state <= 'h7f80;
  end else begin
    state <= full_state[14:0];
  end
end

endmodule
module jesd204_scrambler_64b #(
  parameter WIDTH = 64,
  parameter DESCRAMBLE = 0
) (
  input clk,
  input reset,

  input enable,

  input [WIDTH-1:0] data_in,
  output reg [WIDTH-1:0] data_out
);

reg [57:0] state = {1'b1,57'b0};
wire [WIDTH-1:0] feedback;
wire [WIDTH-1+58:0] full_state;

assign full_state = {state,DESCRAMBLE ? data_in : feedback};
assign feedback = full_state[WIDTH-1+58:58] ^ full_state[WIDTH-1:39] ^ data_in;

always @(*) begin
  if (enable == 1'b0) begin
    data_out = data_in;
  end else begin
    data_out = feedback;
  end
end

always @(posedge clk) begin
  if (reset == 1'b1) begin
    state <= {1'b1,57'b0};
  end else begin
    state <= full_state[57:0] ^ {full_state[38:0],19'b0};
  end
end

endmodule
module jesd204_eof_generator #(
  parameter DATA_PATH_WIDTH = 4,
  parameter MAX_OCTETS_PER_FRAME = 256
) (
  input clk,
  input reset,

  input lmfc_edge,

  input [7:0] cfg_octets_per_frame,
  input cfg_generate_eomf,

  output reg [DATA_PATH_WIDTH-1:0] sof,
  output reg [DATA_PATH_WIDTH-1:0] eof,
  output reg eomf
);

localparam CW = MAX_OCTETS_PER_FRAME > 128 ? 8 :
  MAX_OCTETS_PER_FRAME > 64 ? 7 :
  MAX_OCTETS_PER_FRAME > 32 ? 6 :
  MAX_OCTETS_PER_FRAME > 16 ? 5 :
  MAX_OCTETS_PER_FRAME > 8 ? 4 :
  MAX_OCTETS_PER_FRAME > 4 ? 3 :
  MAX_OCTETS_PER_FRAME > 2 ? 2 : 1;
localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 :
  DATA_PATH_WIDTH == 4 ? 2 : 1;

reg lmfc_edge_d1 = 1'b0;

wire beat_counter_sof;
wire beat_counter_eof;
wire small_octets_per_frame;

always @(posedge clk) begin
  if (cfg_generate_eomf == 1'b1) begin
    lmfc_edge_d1 <= lmfc_edge;
  end else begin
    lmfc_edge_d1 <= 1'b0;
  end
  eomf <= lmfc_edge_d1;
end

generate
if (CW > DPW_LOG2) begin
  reg [CW-DPW_LOG2-1:0] beat_counter = 'h00;
  wire [CW-DPW_LOG2-1:0] cfg_beats_per_frame = cfg_octets_per_frame[CW-1:DPW_LOG2];

  assign beat_counter_sof = beat_counter == 'h00;
  assign beat_counter_eof = beat_counter == cfg_beats_per_frame;
  assign small_octets_per_frame = cfg_beats_per_frame == 'h00;

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      beat_counter <= 'h00;
    end else if (beat_counter_eof == 1'b1) begin
      beat_counter <= 'h00;
    end else begin
      beat_counter <= beat_counter + 1'b1;
    end
  end

end else begin
  assign beat_counter_sof = 1'b1;
  assign beat_counter_eof = 1'b1;
  assign small_octets_per_frame = 1'b1;
end
endgenerate

function [1:0] ffs;
input [2:0] x;
begin
  case (x)
  1: ffs = 0;
  2: ffs = 1;
  3: ffs = 0;
  4: ffs = 2;
  5: ffs = 0;
  6: ffs = 1;
  7: ffs = 0;
  default: ffs = 0;
  endcase
end
endfunction

integer i;

/* Only 1, 2 and multiples of 4 are supported atm */
always @(posedge clk) begin
  if (reset == 1'b1) begin
    sof <= {DATA_PATH_WIDTH{1'b0}};
    eof <= {DATA_PATH_WIDTH{1'b0}};
  end else begin
    sof <= {{DATA_PATH_WIDTH-1{1'b0}},beat_counter_sof};
    eof <= {beat_counter_eof,{DATA_PATH_WIDTH-1{1'b0}}};

    if (small_octets_per_frame == 1'b1) begin
      for (i = 1; i < DATA_PATH_WIDTH; i = i + 1) begin
        if (cfg_octets_per_frame[ffs(i)] != 1'b1) begin
          sof[i] <= 1'b1;
          eof[DATA_PATH_WIDTH-1-i] <= 1'b1;
        end
      end
    end else begin
    end
  end
end

endmodule
module jesd204_crc12 #(
  parameter WIDTH = 64
) (
  input clk,
  input reset,

  input init,

  input [WIDTH-1:0] data_in,
  output [11:0] crc12
);

reg [11:0] state = 12'b0;

wire [WIDTH-1:0] feedback;
wire [WIDTH-1+12:0] full_state;

assign full_state = {init ? 12'h0 : state, feedback};
assign feedback = full_state[WIDTH-1+12:12] ^
                  full_state[WIDTH-1:11] ^
                  full_state[WIDTH-1:10] ^
                  full_state[WIDTH-1:9] ^
                  full_state[WIDTH-1:4] ^
                  full_state[WIDTH-1:3] ^
                  data_in;

always @(posedge clk) begin
  if (reset == 1'b1) begin
    state <= 12'b0;
  end else begin
    state <= full_state[11:0] ^
            {full_state[10:0],1'b0} ^
            {full_state[9:0],2'b0} ^
            {full_state[8:0],3'b0} ^
            {full_state[3:0],8'b0} ^
            {full_state[2:0],9'b0};
  end
end

assign crc12 = state;

endmodule
module jesd204_rx_static_config #(
  parameter NUM_LANES = 1,
  parameter NUM_LINKS = 1,
  parameter OCTETS_PER_FRAME = 1,
  parameter FRAMES_PER_MULTIFRAME = 32,
  parameter SCR = 1,
  parameter BUFFER_EARLY_RELEASE = 0,
  parameter LINK_MODE = 1 // 2 - 64B/66B;  1 - 8B/10B
) (
  input clk,

  output [NUM_LANES-1:0] cfg_lanes_disable,
  output [NUM_LINKS-1:0] cfg_links_disable,
  output [7:0] cfg_beats_per_multiframe,
  output [7:0] cfg_octets_per_frame,
  output [7:0] cfg_lmfc_offset,
  output cfg_sysref_oneshot,
  output cfg_sysref_disable,

  output [7:0] cfg_buffer_delay,
  output cfg_buffer_early_release,
  output cfg_disable_scrambler,
  output cfg_disable_char_replacement,
  output [7:0] cfg_frame_align_err_threshold
);

/* Only 4 is supported at the moment for 8b/10b and 8 for 64b */
localparam DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4;

assign cfg_beats_per_multiframe = (FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME / DATA_PATH_WIDTH) - 1;
assign cfg_octets_per_frame = OCTETS_PER_FRAME - 1;
assign cfg_lmfc_offset = 3;
assign cfg_sysref_oneshot = 1'b0;
assign cfg_sysref_disable = 1'b0;
assign cfg_buffer_delay = 'h0;
assign cfg_buffer_early_release = BUFFER_EARLY_RELEASE;
assign cfg_lanes_disable = {NUM_LANES{1'b0}};
assign cfg_links_disable = {NUM_LINKS{1'b0}};
assign cfg_disable_scrambler = SCR ? 1'b0 : 1'b1;
assign cfg_disable_char_replacement = cfg_disable_scrambler;
assign cfg_frame_align_err_threshold = 8'd4;

endmodule
module axi_ad9361_cmos_if #(

  parameter   FPGA_TECHNOLOGY = 0,
  parameter   DAC_IODELAY_ENABLE = 0,
  parameter   CLK_DESKEW = 0,
  parameter   USE_SSI_CLK = 1,

  // Dummy parameters, required keep the code consistency(used on Xilinx)
  parameter   IO_DELAY_GROUP = "dev_if_delay_group",
  parameter   DELAY_REFCLK_FREQUENCY = 0) (

  // physical interface (receive)

  input               rx_clk_in,
  input               rx_frame_in,
  input   [11:0]      rx_data_in,

  // physical interface (transmit)

  output              tx_clk_out,
  output              tx_frame_out,
  output  [11:0]      tx_data_out,

  // ensm control

  output              enable,
  output              txnrx,

  // clock (common to both receive and transmit)

  input               rst,
  input               clk,
  output              l_clk,

  // receive data path interface

  output              adc_valid,
  output  [47:0]      adc_data,
  output              adc_status,
  input               adc_r1_mode,
  input               adc_ddr_edgesel,

  // transmit data path interface

  input               dac_valid,
  input   [47:0]      dac_data,
  input               dac_clksel,
  input               dac_r1_mode,

  // tdd interface

  input               tdd_enable,
  input               tdd_txnrx,
  input               tdd_mode,

  // delay interface

  input               mmcm_rst,
  input               up_clk,
  input               up_rstn,
  input               up_enable,
  input               up_txnrx,
  input   [12:0]      up_adc_dld,
  input   [64:0]      up_adc_dwdata,
  output  [64:0]      up_adc_drdata,
  input   [15:0]      up_dac_dld,
  input   [79:0]      up_dac_dwdata,
  output  [79:0]      up_dac_drdata,
  input               delay_clk,
  input               delay_rst,
  output              delay_locked,

  // drp interface

  input               up_drp_sel,
  input               up_drp_wr,
  input   [11:0]      up_drp_addr,
  input   [31:0]      up_drp_wdata,
  output  [31:0]      up_drp_rdata,
  output              up_drp_ready,
  output              up_drp_locked);

  // cmos is not supported on intel platforms yet.

  assign tx_clk_out = 1'd0;
  assign tx_frame_out = 1'd0;
  assign tx_data_out = 12'd0;
  assign enable = 1'd0;
  assign txnrx = 1'd0;
  assign l_clk = 1'd0;
  assign adc_valid = 1'd0;
  assign adc_data = 48'd0;
  assign adc_status = 1'd0;
  assign up_adc_drdata = 65'd0;
  assign up_dac_drdata = 80'd0;
  assign delay_locked = 1'd0;
  assign up_drp_rdata = 32'd0;
  assign up_drp_ready = 1'd0;
  assign up_drp_locked = 1'd0;

endmodule
module adi_jesd204_glue (
  input in_pll_powerdown,
  output out_pll_powerdown,
  output out_mcgb_rst,
  output out_pll_select_gnd
);

assign out_pll_powerdown = in_pll_powerdown;
assign out_mcgb_rst = in_pll_powerdown;
assign out_pll_select_gnd = 1'b0;

endmodule
module ad_dcfilter #(

  // data path disable

  parameter   DISABLE = 0) (

  // data interface

  input               clk,
  input               valid,
  input       [15:0]  data,
  output reg          valid_out,
  output reg  [15:0]  data_out,

  // control interface

  input           dcfilt_enb,
  input   [15:0]  dcfilt_coeff,
  input   [15:0]  dcfilt_offset);

  // internal registers

  reg             valid_d = 'd0;
  reg     [15:0]  data_d = 'd0;
  reg             valid_2d = 'd0;
  reg     [15:0]  data_2d = 'd0;

  // internal signals

  wire    [47:0]  dc_offset_s;

  always @(posedge clk) begin
    valid_d <= valid;
    if (valid == 1'b1) begin
      data_d <= data + dcfilt_offset;
    end
    valid_2d <= valid_d;
    data_2d  <= data_d;
    valid_out <= valid_2d;
    data_out  <= data_2d;
  end

endmodule
module ad_mul #(

  parameter   A_DATA_WIDTH = 17,
  parameter   B_DATA_WIDTH = 17,
  parameter   DELAY_DATA_WIDTH = 16) (

  // data_p = data_a * data_b;

  input                                     clk,
  input   [               A_DATA_WIDTH-1:0] data_a,
  input   [               B_DATA_WIDTH-1:0] data_b,
  output  [A_DATA_WIDTH + B_DATA_WIDTH-1:0] data_p,

  // delay interface

  input       [(DELAY_DATA_WIDTH-1):0]  ddata_in,
  output  reg [(DELAY_DATA_WIDTH-1):0]  ddata_out);


  // internal registers

  reg     [(DELAY_DATA_WIDTH-1):0]    p1_ddata = 'd0;
  reg     [(DELAY_DATA_WIDTH-1):0]    p2_ddata = 'd0;

  // a/b reg, m-reg, p-reg delay match

  always @(posedge clk) begin
    p1_ddata <= ddata_in;
    p2_ddata <= p1_ddata;
    ddata_out <= p2_ddata;
  end

  lpm_mult #(
    .lpm_type ("lpm_mult"),
    .lpm_widtha (A_DATA_WIDTH),
    .lpm_widthb (B_DATA_WIDTH),
    .lpm_widthp (A_DATA_WIDTH + B_DATA_WIDTH),
    .lpm_representation ("SIGNED"),
    .lpm_pipeline (3))
  i_lpm_mult (
    .clken (1'b1),
    .aclr (1'b0),
    .sclr (1'b0),
    .sum (1'b0),
    .clock (clk),
    .dataa (data_a),
    .datab (data_b),
    .result (data_p));

endmodule
module util_clkdiv #(
  parameter SIM_DEVICE = "CYCLONE5",
  parameter CLOCK_TYPE = "Global Clock") (

  input   clk,
  input   reset,
  output  clk_out,
  output  reset_out
 );

reg enable;
reg reset_d1;

assign reset_out = reset | reset_d1;

always @(posedge clk) begin
  reset_d1 <= reset;
end

always @(posedge clk) begin
  enable <= ~enable;
end

generate if (SIM_DEVICE == "CYCLONE5") begin
	cyclonev_clkena #(
		.clock_type ("Global Clock"),
		.ena_register_mode ("falling edge"),
		.lpm_type ("cyclonev_clkena")
  ) clock_divider_by_2 (
	.ena(enable),
	.enaout(),
	.inclk(clk),
//	.clkselect (2'b0),
	.outclk(clk_out));

end endgenerate

endmodule  // util_clkdiv
module jesd204_glue #(
  parameter WIDTH = 20,
  parameter CONST_WIDTH = 1,
  parameter NUM_OF_LANES = 1,
  parameter LANE_INVERT = 0
) (
  input [WIDTH-1:0] in,
  output [WIDTH-1:0] out,
  output [CONST_WIDTH-1:0] const_out,
  output [NUM_OF_LANES-1:0] polinv
);

/* There really should be a standard component in Qsys that allows to do this */

assign out = in;
assign const_out = {CONST_WIDTH{1'b0}};
assign polinv = LANE_INVERT[NUM_OF_LANES-1:0];

endmodule
module avl_adxcvr_octet_swap #(
  parameter NUM_OF_LANES = 1
) (
  input clk,
  input reset,

  input in_valid,
  output in_ready,
  input [NUM_OF_LANES*32-1:0] in_data,
  input [3:0] in_sof,

  output out_valid,
  input out_ready,
  output [NUM_OF_LANES*32-1:0] out_data,
  output [3:0] out_sof
);

assign in_ready = out_ready;
assign out_valid = in_valid;

generate
  genvar i;
  genvar j;

  for (j = 0; j < 4; j = j + 1) begin: gen_octet
    for (i = 0; i < NUM_OF_LANES; i = i + 1) begin: gen_lane
      assign out_data[i*32+j*8+7:i*32+j*8] = in_data[i*32+(3-j)*8+7:i*32+(3-j)*8];
    end
    assign out_sof[j] = in_sof[3-j];
  end
endgenerate

endmodule
module emesh_readback (/*AUTOARG*/
   // Outputs
   ready_out, access_out, packet_out,
   // Inputs
   nreset, clk, access_in, packet_in, read_data, ready_in
   );
   parameter  AW  = 32;    // address width
   parameter  PW  = 104;   // packet width   
   
   //clk, reset
   input           nreset;      // asynchronous active low reset
   input 	   clk;         // clock
   
   // input transaction
   input 	   access_in;   // register access
   input [PW-1:0]  packet_in;   // data/address
   output 	   ready_out;    // pushback from mesh

   // register/memory data (already pipelined)
   input [63:0]    read_data;   // data from register/memorye

   // output transaction
   output 	   access_out;  // register access
   output [PW-1:0] packet_out;  // data/address
   input 	   ready_in;     // pushback from mesh

   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire [12:0]		ctrlmode_in;		// From p2e of packet2emesh.v
   wire [AW-1:0]	data_in;		// From p2e of packet2emesh.v
   wire [1:0]		datamode_in;		// From p2e of packet2emesh.v
   wire [AW-1:0]	dstaddr_in;		// From p2e of packet2emesh.v
   wire [AW-1:0]	srcaddr_in;		// From p2e of packet2emesh.v
   wire			write_in;		// From p2e of packet2emesh.v
   // End of automatics

   reg [1:0] 		datamode_out;
   reg [4:0] 		ctrlmode_out;
   reg [AW-1:0] 	dstaddr_out; 	
   wire [AW-1:0] 	data_out;
   wire [AW-1:0] 	srcaddr_out;
   reg 			access_out;
   
   //########################################
   //# Parse packet
   //#######################################  

   enoc_unpack #(.AW(AW),
		 .PW(PW))
   p2e (/*AUTOINST*/
	// Outputs
	.write_in			(write_in),
	.datamode_in			(datamode_in[1:0]),
	.ctrlmode_in			(ctrlmode_in[12:0]),
	.dstaddr_in			(dstaddr_in[AW-1:0]),
	.srcaddr_in			(srcaddr_in[AW-1:0]),
	.data_in			(data_in[AW-1:0]),
	// Inputs
	.packet_in			(packet_in[PW-1:0]));
      
   //########################################
   //# Pipeline
   //#######################################   

   //access
   always @ (posedge clk or negedge nreset)
     if(!nreset)
       access_out <= 1'b0;
     else if(ready_in)
       access_out <= access_in & ~write_in;

   //packet
   always @ (posedge clk)
     if(ready_in & access_in & ~write_in)
       begin	  
	  datamode_out[1:0]   <= datamode_in[1:0];
	  ctrlmode_out[4:0]   <= ctrlmode_in[4:0];
	  dstaddr_out[AW-1:0] <= srcaddr_in[AW-1:0]; 
       end

   assign data_out[AW-1:0]    = read_data[31:0];
   assign srcaddr_out[AW-1:0] = read_data[63:32];
   
   //ready signal
   assign ready_out = ready_in;
   
   //########################################
   //# Convert to Packet
   //#######################################  
     
   enoc_pack #(.AW(AW),
	       .PW(PW))
   e2p (.write_out   (1'b1),
	/*AUTOINST*/
	// Outputs
	.packet_out			(packet_out[PW-1:0]),
	// Inputs
	.datamode_out			(datamode_out[1:0]),
	.ctrlmode_out			(ctrlmode_out[12:0]),
	.dstaddr_out			(dstaddr_out[AW-1:0]),
	.data_out			(data_out[AW-1:0]),
	.srcaddr_out			(srcaddr_out[AW-1:0]));
   
   
endmodule // emesh_readback
module emesh_wralign (/*AUTOARG*/
   // Outputs
   data_out,
   // Inputs
   datamode, data_in
   );

   input  [1:0]    datamode;
   input  [63:0]   data_in;
   output [63:0]   data_out;

   wire [3:0] data_size;
      
   assign data_size[0]= (datamode[1:0]==2'b00);//byte
   assign data_size[1]= (datamode[1:0]==2'b01);//short
   assign data_size[2]= (datamode[1:0]==2'b10);//word
   assign data_size[3]= (datamode[1:0]==2'b11);//double

   //B0(0)
   assign data_out[7:0]   = data_in[7:0];

   //B1(16 NAND2S,8 NOR2S)
   assign data_out[15:8]  = {(8){data_size[0]}}      & data_in[7:0]   |
                            {(8){(|data_size[3:1])}} & data_in[15:8] ;
   
   //B2(16 NAND2S,8 NOR2S)
   assign data_out[23:16] = {(8){(|data_size[1:0])}} & data_in[7:0]   |
                            {(8){(|data_size[3:2])}} & data_in[23:16] ; 

   //B3(24 NAND2S,8 NOR3S)
   assign data_out[31:24] = {(8){data_size[0]}}      & data_in[7:0]   |
                            {(8){data_size[1]}}      & data_in[15:8]  |
                            {(8){(|data_size[3:2])}} & data_in[31:24] ; 
   
   //B4(24 NAND2S,8 NOR3S)
   assign data_out[39:32] = {(8){(|data_size[2:0])}} & data_in[7:0]   |
                            {(8){data_size[3]}}      & data_in[39:32] ;

   //B5(24 NAND2S,8 NOR3S)
   assign data_out[47:40] = {(8){data_size[0]}}      & data_in[7:0]   |
                            {(8){(|data_size[2:1])}} & data_in[15:8]  |
                            {(8){data_size[3]}}      & data_in[47:40] ;

   //B6(24 NAND2S,8 NOR3S)
   assign data_out[55:48] = {(8){(|data_size[1:0])}} & data_in[7:0]   |
                            {(8){data_size[2]}}      & data_in[23:16] |
                            {(8){data_size[3]}}      & data_in[55:48] ;
   
   //B7(32 NAND2S,16 NOR2S)
   assign data_out[63:56] = {(8){data_size[0]}}      & data_in[7:0]   |
                            {(8){data_size[1]}}      & data_in[15:8]  |
                            {(8){data_size[2]}}      & data_in[31:24] |
                            {(8){data_size[3]}}      & data_in[63:56] ;

endmodule // memory_wralign
module emesh_rdalign (/*AUTOARG*/
   // Outputs
   data_out,
   // Inputs
   addr, datamode, data_in
   );

   //Inputs
   input [2:0] 	   addr;
   input [1:0] 	   datamode; 	   
   input [63:0]    data_in;

   //Outputs
   output [63:0]   data_out;

   //wires
   wire [3:0]      byte0_sel;
   wire [31:0]     data_mux;
   wire [31:0]     data_aligned;
   wire 	   byte1_sel1;
   wire 	   byte1_sel0;
   wire 	   byte2_en;
   wire 	   byte3_en;
   
   //Shift down high word
   assign data_mux[31:0] = addr[2] ? data_in[63:32] : 
			             data_in[31:0];
      
   //Byte0
   assign    byte0_sel[3] = addr[1:0]==2'b11;
   assign    byte0_sel[2] = addr[1:0]==2'b10;   
   assign    byte0_sel[1] = addr[1:0]==2'b01;
   assign    byte0_sel[0] = addr[1:0]==2'b00;
  
   //Byte1  
   assign    byte1_sel1 = datamode[1:0]==2'b01 & addr[1:0]==2'b10;

   assign    byte1_sel0 = (datamode[1:0]==2'b01 & addr[1:0]==2'b00) |
	                  datamode[1:0]==2'b10                      | 
			  datamode[1:0]==2'b11;
   //Byte2
   assign    byte2_en = datamode[1:0]==2'b10 | 
		        datamode[1:0]==2'b11;
   //Byte3
   assign    byte3_en = datamode[1:0]==2'b10 | 
		        datamode[1:0]==2'b11;
  
   //B0: 32 NANDs,8 NORS
   assign data_aligned[7:0]   = {(8){byte0_sel[3]}} & data_mux[31:24] |
	                        {(8){byte0_sel[2]}} & data_mux[23:16] |
	                        {(8){byte0_sel[1]}} & data_mux[15:8]  |
	                        {(8){byte0_sel[0]}} & data_mux[7:0];
   //B1:
   assign data_aligned[15:8]  = {(8){byte1_sel1}} & data_mux[31:24] |
	                        {(8){byte1_sel0}} & data_mux[15:8];

   //B2: 8 NANDS
   assign data_aligned[23:16] = {(8){byte2_en}} & data_mux[23:16];
   
   //B3: 
   assign data_aligned[31:24] = {(8){byte3_en}} & data_mux[31:24];

   //lower 32 bits
   assign data_out[31:0]      = data_aligned[31:0];

   //Upper 32 bits are pass through
   assign data_out[63:32]     = data_in[63:32];

endmodule // memory_rdalign
module emesh_decode
  (
   //Packet Command
   input [15:0] cmd_in,
   //Write
   output 	cmd_write,
   output 	cmd_write_stop,
   //Read
   output 	cmd_read,
   output 	cmd_atomic_add,
   output 	cmd_atomic_and,
   output 	cmd_atomic_or,
   output 	cmd_atomic_xor,
   output 	cmd_cas,
   //Fields
   output [3:0] cmd_opcode,
   output [3:0] cmd_length,
   output [2:0] cmd_size,
   output [7:0] cmd_user
   );

   //############################################
   // Command Decode
   //############################################

   //Writes
   assign cmd_write        = ~cmd_in[3];
   assign cmd_write_stop   = cmd_in[3:0]==1001;

   //Reads/atomics
   assign cmd_read         = cmd_in[3:0]==1000;
   assign cmd_atomic_cas   = cmd_in[3:0]==1011;
   assign cmd_atomic_add   = cmd_in[3:0]==1100;
   assign cmd_atomic_and   = cmd_in[3:0]==1101;
   assign cmd_atomic_or    = cmd_in[3:0]==1110;
   assign cmd_atomic_xor   = cmd_in[3:0]==1111;

   //Field Decode
   assign cmd_opcode[3:0]  = cmd_in[3:0];
   assign cmd_length[3:0]  = cmd_in[7:4];
   assign cmd_size[2:0]    = cmd_in[10:8];
   assign cmd_user[7:0]    = cmd_in[15:8];

endmodule // enoc_decode
module emesh_if (/*AUTOARG*/
   // Outputs
   cmesh_ready_out, cmesh_access_out, cmesh_packet_out,
   rmesh_ready_out, rmesh_access_out, rmesh_packet_out,
   xmesh_ready_out, xmesh_access_out, xmesh_packet_out,
   emesh_ready_out, emesh_access_out, emesh_packet_out,
   // Inputs
   cmesh_access_in, cmesh_packet_in, cmesh_ready_in, rmesh_access_in,
   rmesh_packet_in, rmesh_ready_in, xmesh_access_in, xmesh_packet_in,
   xmesh_ready_in, emesh_access_in, emesh_packet_in, emesh_ready_in
   );

   parameter AW   = 32;   
   parameter PW   = 2*AW+40; 

   //##Cmesh##    
   input 	   cmesh_access_in;
   input [PW-1:0]  cmesh_packet_in;
   output 	   cmesh_ready_out;
   output 	   cmesh_access_out;
   output [PW-1:0] cmesh_packet_out;
   input 	   cmesh_ready_in;
      
   //##Rmesh## 
   input 	   rmesh_access_in;
   input [PW-1:0]  rmesh_packet_in;
   output 	   rmesh_ready_out;
   output 	   rmesh_access_out;
   output [PW-1:0] rmesh_packet_out;
   input 	   rmesh_ready_in;
   
   //##Xmesh## 
   input 	   xmesh_access_in;
   input [PW-1:0]  xmesh_packet_in;
   output 	   xmesh_ready_out;  
   output 	   xmesh_access_out;
   output [PW-1:0] xmesh_packet_out;
   input 	   xmesh_ready_in;
   
   //##Emesh##
   input 	   emesh_access_in;
   input [PW-1:0]  emesh_packet_in;
   output 	   emesh_ready_out;
   
   //core-->io
   output 	   emesh_access_out;
   output [PW-1:0] emesh_packet_out;
   input 	   emesh_ready_in;
      
   //#####################################################
   //# EMESH-->(RMESH/XMESH/CMESH)
   //#####################################################
      
   assign cmesh_access_out = emesh_access_in & emesh_packet_in[0];

   assign rmesh_access_out = emesh_access_in & ~emesh_packet_in[0];

   //Don't drive on xmesh for now
   assign xmesh_access_out = 1'b0;
      
   //Distribute emesh to xmesh,cmesh, rmesh
   assign cmesh_packet_out[PW-1:0] = emesh_packet_in[PW-1:0];	 
   assign rmesh_packet_out[PW-1:0] = emesh_packet_in[PW-1:0];	 
   assign xmesh_packet_out[PW-1:0] = emesh_packet_in[PW-1:0];


   assign emesh_ready_out = cmesh_ready_in &
			    rmesh_ready_in &
			    xmesh_ready_in;
  	 	 
   //#####################################################
   //# (RMESH/XMESH/CMESH)-->EMESH
   //#####################################################

   assign emesh_access_out = cmesh_access_in &
			     rmesh_access_in &
			     xmesh_access_in;
   

   //TODO: Make round robin?? (Fancify)
   assign emesh_packet_out[PW-1:0] = cmesh_access_in ? cmesh_packet_in[PW-1:0] :
				     rmesh_access_in ? rmesh_packet_in[PW-1:0] :
				                       xmesh_packet_in[PW-1:0];
   
   assign cmesh_ready_out = ~(cmesh_access_in & ~emesh_ready_in);
   

   assign rmesh_ready_out = ~(rmesh_access_in & 
			    (~emesh_ready_in | ~cmesh_ready_in));

   assign xmesh_ready_out = ~(xmesh_access_in & 
			      (~emesh_ready_in | ~cmesh_access_in | ~rmesh_access_in));
   
				     
endmodule // emesh_if
module emesh_monitor
  # (parameter PW       = 104,         // packet width
     parameter FILENAME = "UNDEFINED", // filename
     parameter ENABLE   = 0            // enable block
     )
   (
    //clock and reset
    input 	   clk,
    input 	   nreset,
    //monitors transaction on the wire
    input 	   dut_valid,
    input [PW-1:0] dut_packet,
    input 	   ready_in
    );

   generate
      if(ENABLE)
	begin
	   //core name for trace
	   reg [31:0] 	    ftrace;
	   reg [255:0] 	    tracefile;

	   initial
	     begin
		#10
		  $sformat(tracefile,"%0s_%0h%s",FILENAME);
		ftrace  = $fopen({tracefile}, "w");
	     end

	   always @ (posedge clk)
	     if(nreset & dut_valid & ready_in)
	       if (PW==112) begin: p112
		  $fwrite(ftrace, "%h_%h_%h_%h\n",
			  dut_packet[110:80],
			  dut_packet[79:48],
			  dut_packet[47:16],
			  dut_packet[15:0]);
	       end
	       else if (PW==144) begin: p144
		  $fwrite(ftrace, "%h_%h_%h_%h\n",
			  dut_packet[143:112],
			  dut_packet[111:48],
			  dut_packet[47:16],
			  dut_packet[15:0]);
	       end
	       else if (PW==208) begin: p208
		  $fwrite(ftrace, "%h_%h_%h_%h_%h\n",
			  dut_packet[207:144],
			  dut_packet[143:112],
			  dut_packet[111:48],
			  dut_packet[47:16],
			  dut_packet[15:0]);
	       end

	end
   endgenerate

endmodule // emesh_monitor
module dut(/*AUTOARG*/
   // Outputs
   dut_active, clkout, wait_out, access_out, packet_out,
   // Inputs
   clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
   );

   parameter AW    = 32;
   parameter DW    = 32;
   parameter CW    = 2; 
   parameter IDW   = 12;
   parameter M_IDW = 6;
   parameter S_IDW = 12;
   parameter PW    = 104;     
   parameter N     = 32;
   
   //#######################################
   //# CLOCK AND RESET
   //#######################################
   input            clk1;
   input            clk2;
   input            nreset;
   input [N*N-1:0]  vdd;
   input 	    vss;
   output 	    dut_active;
   output 	    clkout;   

   //#######################################
   //#EMESH INTERFACE 
   //#######################################
   
   //Stimulus Driven Transaction
   input [N-1:0]     access_in;
   input [N*PW-1:0]  packet_in;
   output [N-1:0]    wait_out;

   //DUT driven transactoin
   output [N-1:0]    access_out;
   output [N*PW-1:0] packet_out;
   input [N-1:0]     wait_in;

   /*AUTOINPUT*/ 
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire [AW-1:0]	gpio_dir;		// From gpio of gpio.v
   wire			gpio_irq;		// From gpio of gpio.v
   wire [AW-1:0]	gpio_out;		// From gpio of gpio.v
   // End of automatics

   wire 		clk;
   wire [AW-1:0] 	gpio_in;		// To gpio of gpio.v

   //######################################################################
   //DUT
   //######################################################################

   assign wait_out[N-1:0] = 'b0;
   assign dut_active      = 1'b1;
   assign clkout          = clk1;
   assign clk             = clk1;
   
   /*gpio AUTO_TEMPLATE (
	 .gpio_irq	 (gpio_irq),
         .gpio_\(.*\)    (gpio_\1[AW-1:0]),
    );
    */
   gpio #(.N(AW),
	  .AW(AW))
   gpio (.gpio_in			(gpio_out[AW-1:0]),
	 /*AUTOINST*/
	 // Outputs
	 .wait_out			(wait_out),
	 .access_out			(access_out),
	 .packet_out			(packet_out[PW-1:0]),
	 .gpio_out			(gpio_out[AW-1:0]),	 // Templated
	 .gpio_dir			(gpio_dir[AW-1:0]),	 // Templated
	 .gpio_irq			(gpio_irq),		 // Templated
	 // Inputs
	 .nreset			(nreset),
	 .clk				(clk),
	 .access_in			(access_in),
	 .packet_in			(packet_in[PW-1:0]),
	 .wait_in			(wait_in));
        
endmodule // dut
module dut(/*AUTOARG*/
   // Outputs
   dut_active, wait_out, access_out, packet_out,
   // Inputs
   clk, nreset, vdd, vss, access_in, packet_in, wait_in
   );

   parameter AW    = 32;
   parameter DW    = 32;
   parameter CW    = 2; 
   parameter IDW   = 12;
   parameter M_IDW = 6;
   parameter S_IDW = 12;
   parameter PW    = 104;     
   parameter N     = 1;
   parameter ID    = 12'h810;
   
   //#######################################
   //# CLOCK AND RESET
   //#######################################
   input            clk;
   input            nreset;
   input [N*N-1:0]  vdd;
   input 	    vss;
   output 	    dut_active;
   
   //#######################################
   //#EMESH INTERFACE 
   //#######################################
   
   //Stimulus Driven Transaction
   input [N-1:0]     access_in;
   input [N*PW-1:0]  packet_in;
   output [N-1:0]    wait_out;

   //DUT driven transactoin
   output [N-1:0]    access_out;
   output [N*PW-1:0] packet_out;
   input [N-1:0]     wait_in;


   //TODO: finish readback
   wire [DW-1:0]     mi_dout;
   
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire [3:0]		mi_ctrlmode;		// From e2p of packet2emesh.v
   wire [DW-1:0]	mi_data;		// From e2p of packet2emesh.v
   wire [1:0]		mi_datamode;		// From e2p of packet2emesh.v
   wire [AW-1:0]	mi_dstaddr;		// From e2p of packet2emesh.v
   wire [AW-1:0]	mi_srcaddr;		// From e2p of packet2emesh.v
   wire			mi_write;		// From e2p of packet2emesh.v
   // End of automatics
   
   assign dut_active         = 1'b1;
   assign access_out         = 'b0;
   assign wait_out           = 'b0;
   assign packet_out[PW-1:0] = 'b0;
   
   
   /*packet2emesh AUTO_TEMPLATE (//Stimulus
                            .\(.*\)_out(mi_\1[]),
                             );
    */

   //CONFIG INTERFACE
   packet2emesh e2p (/*AUTOINST*/
		     // Outputs
		     .write_out		(mi_write),		 // Templated
		     .datamode_out	(mi_datamode[1:0]),	 // Templated
		     .ctrlmode_out	(mi_ctrlmode[3:0]),	 // Templated
		     .data_out		(mi_data[DW-1:0]),	 // Templated
		     .dstaddr_out	(mi_dstaddr[AW-1:0]),	 // Templated
		     .srcaddr_out	(mi_srcaddr[AW-1:0]),	 // Templated
		     // Inputs
		     .packet_in		(packet_in[PW-1:0]));

   //TRACE
   etrace #(.ID(ID))
   etrace ( // Outputs
	    .mi_dout		(mi_dout[DW-1:0]),
	    // Inputs
	    .mi_en		(access_in),
	    .mi_we		(mi_write),
	    .mi_addr		(mi_dstaddr[AW-1:0]),
	    .mi_clk		(clk),
	    .mi_din		(mi_data[DW-1:0]),
	    .trace_clk		(clk),
	    .trace_trigger	(1'b1), 
	    .trace_vector	(mi_srcaddr[AW-1:0]),
	    .nreset		(nreset));
     
endmodule // dv_elink
module elink_monitor(/*AUTOARG*/
   // Inputs
   frame, clk, din
   );

   parameter AW = 32;
   parameter PW = 2*AW+40;
   
   input       frame;
   input       clk;
   input [7:0] din;

   reg [3:0]   cycle;
   reg 	       read;
   reg [31:0]  dstaddr;
   reg [31:0]  srcaddr;
   reg [31:0]  data;
   reg [3:0]   ctrlmode;
   reg [1:0]   datamode;
   reg 	       burst;
   reg 	       access;
   reg 	       write;
   wire [103:0] packet;
   
   always @ (posedge clk)
     if(~frame)
       cycle[3:0] <= 'b0;
     else
       cycle[3:0] <=  cycle[3:0]+1'b1;
   
   //Rising edge sampling
   always @ (posedge clk)
     if(frame)
       case (cycle)
	 0:
	   begin
	      read  <= din[7];
	      burst <= din[2];
	   end
	 1:
	   dstaddr[27:20] <= din[7:0];
	 2:
	   dstaddr[11:4]  <= din[7:0];
	 3:
	   data[31:24]    <= din[7:0];
	 4:
	   data[15:8]     <= din[7:0];
	 5:
	   srcaddr[31:24] <= din[7:0];
	 6:
	   srcaddr[15:8]  <= din[7:0];
	 default:
	   ;              	   
       endcase // case (cycle)
   
   //Falling edge sampling
   always @ (negedge clk)
     if(frame)
       case (cycle)
	 1:
	   begin
	      ctrlmode[3:0]  <= din[7:4];
	      dstaddr[31:28] <= din[3:0];
	   end
	 2:
	   dstaddr[19:12] <= din[7:0];
	 3:
	   begin
	      dstaddr[3:0]  <= din[7:4];
	      datamode[1:0] <= din[3:2];
	      write         <= din[1];
	      access        <= din[0];			     
	   end
	 4:
	   data[23:16]     <= din[7:0];
	 5:
	   data[7:0]       <= din[7:0];
	 6:
	   srcaddr[23:16]  <= din[7:0];
	 7:
	   srcaddr[7:0]    <= din[7:0];
	 default: ;              	   
       endcase // case (cycle)
   
   emesh2packet #(.AW(AW))
   e2p (
	// Outputs
	.packet_out			(packet[PW-1:0]),
	// Inputs
	.write_out			(write),
	.datamode_out			(datamode[1:0]),
	.ctrlmode_out			({1'b0,ctrlmode[3:0]}),
	.dstaddr_out			(dstaddr[AW-1:0]),
	.data_out			(data[AW-1:0]),
	.srcaddr_out			(srcaddr[AW-1:0]));

endmodule // elink_monitor
module erx_remap (/*AUTOARG*/
   // Outputs
   emesh_access_out, emesh_packet_out,
   // Inputs
   clk, emesh_access_in, emesh_packet_in, remap_mode, remap_sel,
   remap_pattern, remap_base
   );

   parameter AW = 32;
   parameter DW = 32;
   parameter PW = 104;
   parameter ID = 12'h808;
   
   //Clock/reset
   input          clk;
   
   //Input from arbiter
   input          emesh_access_in;
   input [PW-1:0] emesh_packet_in;
   
   //Configuration
   input [1:0] 	  remap_mode;    //00=none,01=static,02=continuity
   input [11:0]   remap_sel;     //number of bits to remap
   input [11:0]   remap_pattern; //static pattern to map to
   input [31:0]   remap_base;    //remap offset
   
   //Output to TX IO   
   output 	   emesh_access_out;
   output [PW-1:0] emesh_packet_out;

   wire [31:0] 	   static_remap;
   wire [31:0] 	   dynamic_remap;
   wire [31:0] 	   remap_mux;
   wire [31:0] 	   addr_in;
   wire [31:0] 	   addr_out;
   wire 	   remap_en;
   
   reg 		   emesh_access_out;
   reg [PW-1:0]    emesh_packet_out;

   //TODO:FIX!??
   parameter[5:0]  colid = ID[5:0];
   
   //parsing packet
   assign addr_in[31:0]  =  emesh_packet_in[39:8];
 
   
   //simple static remap
   assign static_remap[31:20] = (remap_sel[11:0] & remap_pattern[11:0]) |
			        (~remap_sel[11:0] & addr_in[31:20]);

   assign static_remap[19:0]  = addr_in[19:0];
    
   //more complex compresssed map
   assign dynamic_remap[31:0] = addr_in[31:0]    //input
			     - (colid << 20)     //subtracing elink (start at 0)
			     + remap_base[31:0]  //adding back base
                             - (addr_in[31:26]<<$clog2(colid));
     			     
   //Static, dynamic, or no remap
   assign remap_mux[31:0]  = (addr_in[31:20]==ID)     ? addr_in[31:0] : //for write to mailbox
			     (remap_mode[1:0]==2'b00) ? addr_in[31:0] :
			     (remap_mode[1:0]==2'b01) ? static_remap[31:0] :
	  		                                dynamic_remap[31:0];

   //Access pipeline
   always @ (posedge clk)
       emesh_access_out <= emesh_access_in;

   //Packet Remapping
   always @ (posedge clk)    
       emesh_packet_out[PW-1:0] <= {emesh_packet_in[103:40],
                                    remap_mux[31:0],
                                    emesh_packet_in[7:0]
				    };
   
endmodule // etx_mux
module erx_protocol (/*AUTOARG*/
   // Outputs
   erx_access, erx_packet,
   // Inputs
   clk, test_mode, rx_packet, rx_burst, rx_access
   );

   parameter AW   = 32;
   parameter DW   = 32;
   parameter PW   = 104;
   parameter ID   = 12'h999; //link id
   
   // System reset input
   input           clk;

   //test mode
   input 	   test_mode; //block all traffic in test mode
   
   // Parallel interface, 8 eLink bytes at a time
   
   input [PW-1:0]  rx_packet;
   input 	   rx_burst;
   input 	   rx_access;
   
   // Output to MMU / filter
   output          erx_access;
   output [PW-1:0] erx_packet;

   //wires
   reg [31:0] 	   dstaddr_reg;   
   wire [31:0] 	   dstaddr_next;
   wire [31:0] 	   dstaddr_mux;
   reg 		   erx_access;
   reg [PW-1:0]    erx_packet;
   wire [31:0] 	   rx_addr;
   
   //parsing inputs
   assign        rx_addr[31:0]  = rx_packet[39:8];
   
   //Address generator for bursting
   always @ (posedge clk)
     if(rx_access)
       dstaddr_reg[31:0]    <= dstaddr_mux[31:0];

   assign dstaddr_next[31:0] = dstaddr_reg[31:0] + 4'b1000;
   
   assign dstaddr_mux[31:0]  =  rx_burst ? dstaddr_next[31:0] :
			                   rx_addr[31:0];
                  
   //Pipeline stage and decode  
   
   always @ (posedge clk)
     begin
	  //Write/read request
	  erx_access          <= ~test_mode & rx_access;      	  
	  //Common packet
	  erx_packet[PW-1:0]  <= {rx_packet[PW-1:40],
				  dstaddr_mux[31:0],
				  {1'b0,rx_packet[7:1]} //NOTE: remvoing redundant access packet bit
				  };                    //This is to conform to new format	 
     end
     
endmodule // erx_protocol
module erx_arbiter (/*AUTOARG*/
   // Outputs
   rx_rd_wait, rx_wr_wait, edma_wait, ecfg_wait, rxwr_access,
   rxwr_packet, rxrd_access, rxrd_packet, rxrr_access, rxrr_packet,
   // Inputs
   erx_access, erx_packet, mailbox_wait, edma_access, edma_packet,
   ecfg_access, ecfg_packet, rxwr_wait, rxrd_wait, rxrr_wait
   );

   parameter AW   = 32;
   parameter DW   = 32;
   parameter PW   = 104;
   parameter ID   = 12'h800; //link id
   parameter RFAW = 6;
   
   //Incoming packet (writes)  
   input           erx_access; //from MMU
   input [PW-1:0]  erx_packet;
   output          rx_rd_wait; //for IO
   output          rx_wr_wait; //for IO

   //Pushback from mailbox
   input 	   mailbox_wait;
   
   //From DMA
   input           edma_access;
   input [PW-1:0]  edma_packet;
   output 	   edma_wait;

   //From ETX
   input           ecfg_access;
   input [PW-1:0]  ecfg_packet;
   output 	   ecfg_wait;

   //To Master Write FIFO
   output 	   rxwr_access;
   output [PW-1:0] rxwr_packet;   
   input           rxwr_wait;
   
   //To Master Read FIFO
   output 	   rxrd_access;
   output [PW-1:0] rxrd_packet;   
   input           rxrd_wait;
   
   //To Slave Read Response FIFO
   output 	   rxrr_access;
   output [PW-1:0] rxrr_packet;   
   input           rxrr_wait;

   //####################################
   //Splicing pakets
   //####################################
   wire 	   erx_write;
   wire [AW-1:0]   erx_dstaddr;
   wire 	   erx_read;
   
   packet2emesh #(.AW(AW))
   p2e (// Outputs
	.write_in	(erx_write),
	.datamode_in	(),
	.ctrlmode_in	(),
	.data_in	(),
	.dstaddr_in	(erx_dstaddr[AW-1:0]),
	.srcaddr_in	(),
	// Inputs
	.packet_in	(erx_packet[PW-1:0]));
   
   //#######################################################
   //Read response path (from IO or elink register readback)
   //#######################################################
     
   assign rxrr_access   =  ecfg_access |
			   (erx_access & 
			   (erx_dstaddr[31:20]==ID) &
			    erx_dstaddr[19:16]==`EGROUP_RR);
   
   assign rxrr_packet[PW-1:0] = ecfg_access ? ecfg_packet[PW-1:0] :	    
                                              erx_packet[PW-1:0];

   //####################################
   //Write Path (from IO through MMU)
   //####################################

   assign rxwr_access         = erx_access   & 
				erx_write    &
				~(erx_dstaddr[31:20]==ID);
   
   assign rxwr_packet[PW-1:0] = erx_packet[PW-1:0];
         
   //########################################
   //Read Request Path (from IO through MMU) 
   //########################################

   assign erx_read            = erx_access & ~erx_write;
   
   assign rxrd_access         = erx_read | edma_access;
   
   assign rxrd_packet[PW-1:0] = erx_read ? erx_packet[PW-1:0] : 
				            edma_packet[PW-1:0];
   
   //####################################
   //Wait Signals
   //####################################   
   assign ecfg_wait     = rxrr_wait;

   assign edma_wait     = rxrd_wait | erx_read;
   
   assign rx_rd_wait    = rxrd_wait;

   assign rx_wr_wait    = ecfg_access  |
			  mailbox_wait |
			  rxwr_wait    | 
			  rxrr_wait;
   
endmodule // erx_arbiter
module etx_remap (/*AUTOARG*/
   // Outputs
   emesh_access_out, emesh_packet_out,
   // Inputs
   clk, nreset, emesh_access_in, emesh_packet_in, remap_en, etx_wait
   );

   parameter AW = 32;
   parameter DW = 32;
   parameter PW = 104;
   
   //Clock
   input          clk;
   input 	  nreset;
   
   //Input from arbiter
   input          emesh_access_in;
   input [PW-1:0] emesh_packet_in;
   input 	  remap_en;             //enable tx remap (static)
   
   //Output to TX IO   
   output 	   emesh_access_out;
   output [PW-1:0] emesh_packet_out;

   //Wait signals from protocol block
   input 	   etx_wait;

   wire [31:0] 	   addr_in;
   wire [31:0] 	   addr_remap;
   wire [31:0] 	   addr_out;
   wire 	   write_in;
   
   reg 		   emesh_access_out;
   reg [PW-1:0]    emesh_packet_out;

   packet2emesh #(.AW(AW))
   p2e (// Outputs
	.write_in	(write_in),
	.datamode_in	(),
	.ctrlmode_in	(),
	.data_in	(),
	.dstaddr_in	(addr_in[31:0]),
	.srcaddr_in	(),
	// Inputs
	.packet_in	(emesh_packet_in[PW-1:0]));
         
   assign addr_remap[31:0] = {addr_in[29:18],         //ID
			      addr_in[17:16],         //SPECIAL GROUP
                             {(2){(|addr_in[17:16])}},//ZERO IF NOT SPECIAL
			     addr_in[15:0]
			     };
   			     

   assign addr_out[31:0] = remap_en ? addr_remap[31:0] :
                	              addr_in[31:0];
        		

   //stall read/write access appropriately
   always @ (posedge clk)
     if(!nreset)
       emesh_access_out    <= 1'b0;
     else if(~etx_wait)
       emesh_access_out  <= emesh_access_in;

   always @ (posedge clk)     
     if(~etx_wait)
       emesh_packet_out[PW-1:0] <= {emesh_packet_in[PW-1:40],
				    addr_out[31:0],
				    emesh_packet_in[7:0]
				   };	   
endmodule // etx_remap
module mtx # ( parameter PW         = 104,               // fifo width
	       parameter AW         = 32,               // fifo width
	       parameter IOW        = 8,                 // I./O data width
	       parameter FIFO_DEPTH = 16,                // fifo depth  
	       parameter TARGET     = "GENERIC"         // fifo target
	      )
   (// reset, clk, cfg
    input 	     clk, // main core clock   
    input 	     io_clk, // clock for tx logic
    input 	     nreset, // async active low reset
    input 	     tx_en, // transmit enable   
    input 	     ddr_mode, // configure mio in ddr mode
    input 	     lsbfirst, // send bits lsb first
    input 	     emode, //emesh mode
    input [1:0]      iowidth,//input width
    // status
    output 	     tx_empty, // tx fifo is empty
    output 	     tx_full, // tx fifo is full (should never happen!) 
    output 	     tx_prog_full,// tx is getting full (stop sending!)    
    // data to transmit
    input 	     access_in, // fifo data valid
    input [PW-1:0]   packet_in, // fifo packet  
    output 	     wait_out, // wait pushback for fifo    
    // IO interface (90 deg clock supplied outside this block)
    output 	     tx_access, // access signal for IO
    output [IOW-1:0] tx_packet, // packet for IO
    input 	     tx_wait     // pushback from IO
    );

   //###############
   //# LOCAL WIRES
   //###############

   // End of automatics
   /*AUTOINPUT*/
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire [63:0]		io_packet;		// From mtx_fifo of mtx_fifo.v
   wire [7:0]		io_valid;		// From mtx_fifo of mtx_fifo.v
   wire			io_wait;		// From mtx_io of mtx_io.v
   // End of automatics

   //########################################
   //# Synchronization FIFO
   //########################################

   mtx_fifo #(.PW(PW),
	      .AW(AW),
	      .FIFO_DEPTH(FIFO_DEPTH),
	      .TARGET(TARGET))   
   mtx_fifo (/*AUTOINST*/
	     // Outputs
	     .wait_out			(wait_out),
	     .io_packet			(io_packet[63:0]),
	     .io_valid			(io_valid[7:0]),
	     // Inputs
	     .clk			(clk),
	     .io_clk			(io_clk),
	     .nreset			(nreset),
	     .tx_en			(tx_en),
	     .emode			(emode),
	     .access_in			(access_in),
	     .packet_in			(packet_in[PW-1:0]),
	     .io_wait			(io_wait));
   
   //########################################
   //# IO Logic (DDR, shift register)
   //########################################
 
   mtx_io #(.IOW(IOW))
   mtx_io (/*AUTOINST*/
	   // Outputs
	   .tx_packet			(tx_packet[IOW-1:0]),
	   .tx_access			(tx_access),
	   .io_wait			(io_wait),
	   // Inputs
	   .nreset			(nreset),
	   .io_clk			(io_clk),
	   .ddr_mode			(ddr_mode),
	   .iowidth			(iowidth[1:0]),
	   .tx_wait			(tx_wait),
	   .io_valid			(io_valid[7:0]),
	   .io_packet			(io_packet[IOW-1:0]));
   
endmodule // mtx
module mrx # ( parameter PW         = 104,               // fifo width
	       parameter AW         = 32,               // fifo width
	       parameter IOW        = 8,                 // I./O data width
	       parameter FIFO_DEPTH = 16,                // fifo depth  
	       parameter TARGET     = "GENERIC"         // fifo target
	       )
   (//reset, clk, cfg
    input 	    clk, // main core clock   
    input 	    nreset, // async active low reset
    input 	    ddr_mode,
    input [1:0]     iowidth,
    input 	    amode, // To mrx_fifo of mrx_fifo.v
    input [4:0]     ctrlmode, // To mrx_fifo of mrx_fifo.v
    input [1:0]     datamode, // To mrx_fifo of mrx_fifo.v
    input [AW-1:0]  dstaddr, // To mrx_fifo of mrx_fifo.v
    input 	    emode, // To mrx_fifo of mrx_fifo.v
    //status
    output 	    rx_empty, // rx fifo is empty
    output 	    rx_full, // rx fifo is full (should never happen!) 
    output 	    rx_prog_full,// rx is getting full (stop sending!)
    //IO interface
    input 	    rx_clk, // clock from IO
    input 	    rx_access, // access signal for IO
    input [IOW-1:0] rx_packet, // packet from IO
    output 	    rx_wait, // pushback for IO
    // data 
    output 	    access_out, // fifo data valid
    output [PW-1:0] packet_out, // fifo packet
    input 	    wait_in     // wait pushback for fifo
    );
   
   /*AUTOOUTPUT*/
   /*AUTOINPUT*/
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire			io_access;		// From mrx_io of mrx_io.v
   wire [63:0]		io_packet;		// From mrx_io of mrx_io.v
   wire [7:0]		io_valid;		// From mrx_io of mrx_io.v
   // End of automatics

   //########################################
   //# Synchronization FIFO
   //########################################

   mrx_fifo #(.PW(PW),
	      .AW(AW),
	      .FIFO_DEPTH(FIFO_DEPTH),
	      .TARGET(TARGET))  
   mrx_fifo (/*AUTOINST*/
	     // Outputs
	     .rx_wait			(rx_wait),
	     .access_out		(access_out),
	     .packet_out		(packet_out[PW-1:0]),
	     // Inputs
	     .clk			(clk),
	     .nreset			(nreset),
	     .emode			(emode),
	     .ctrlmode			(ctrlmode[4:0]),
	     .amode			(amode),
	     .dstaddr			(dstaddr[AW-1:0]),
	     .datamode			(datamode[1:0]),
	     .io_access			(io_access),
	     .io_valid			(io_valid[7:0]),
	     .io_packet			(io_packet[63:0]),
	     .rx_clk			(rx_clk),
	     .wait_in			(wait_in));
   
   
   //########################################
   //# FAST IO (DDR)
   //########################################
   
   mrx_io #(.IOW(IOW))
   mrx_io (
	   /*AUTOINST*/
	   // Outputs
	   .io_access			(io_access),
	   .io_valid			(io_valid[7:0]),
	   .io_packet			(io_packet[63:0]),
	   // Inputs
	   .nreset			(nreset),
	   .ddr_mode			(ddr_mode),
	   .iowidth			(iowidth[1:0]),
	   .rx_clk			(rx_clk),
	   .rx_packet			(rx_packet[IOW-1:0]),
	   .rx_access			(rx_access));
  
endmodule // ctx