module or1200_tt_cm2(
		clk_i_cml_1,
		
	// RISC Internal Interface
	clk, rst, du_stall,
	spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
	intr
);


input clk_i_cml_1;
reg  du_stall_cml_1;
reg  spr_write_cml_1;
reg [ 31 : 0 ] spr_addr_cml_1;
reg [ 31 : 0 ] spr_dat_i_cml_1;
reg [ 31 : 0 ] ttmr_cml_1;
reg [ 31 : 0 ] ttcr_cml_1;



//
// RISC Internal Interface
//
input		clk;		// Clock
input		rst;		// Reset
input		du_stall;	// DU stall
input		spr_cs;		// SPR CS
input		spr_write;	// SPR Write
input	[31:0]	spr_addr;	// SPR Address
input	[31:0]	spr_dat_i;	// SPR Write Data
output	[31:0]	spr_dat_o;	// SPR Read Data
output		intr;		// Interrupt output

`ifdef OR1200_TT_IMPLEMENTED

//
// TT Mode Register bits (or no register)
//
`ifdef OR1200_TT_TTMR
reg	[31:0]	ttmr;	// TTMR bits
`else
wire	[31:0]	ttmr;	// No TTMR register
`endif

//
// TT Count Register bits (or no register)
//
`ifdef OR1200_TT_TTCR
reg	[31:0]	ttcr;	// TTCR bits
`else
wire	[31:0]	ttcr;	// No TTCR register
`endif

//
// Internal wires & regs
//
wire		ttmr_sel;	// TTMR select
wire		ttcr_sel;	// TTCR select
wire		match;		// Asserted when TTMR[TP]
				// is equal to TTCR[27:0]
wire		restart;	// Restart counter when asserted
wire		stop;		// Stop counter when asserted
reg	[31:0] 	spr_dat_o;	// SPR data out

//
// TT registers address decoder
//

// SynEDA CoreMultiplier
// assignment(s): ttmr_sel
// replace(s): spr_addr
assign ttmr_sel = (spr_cs && (spr_addr_cml_1[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTMR)) ? 1'b1 : 1'b0;

// SynEDA CoreMultiplier
// assignment(s): ttcr_sel
// replace(s): spr_addr
assign ttcr_sel = (spr_cs && (spr_addr_cml_1[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTCR)) ? 1'b1 : 1'b0;

//
// Write to TTMR or update of TTMR[IP] bit
//
`ifdef OR1200_TT_TTMR

// SynEDA CoreMultiplier
// assignment(s): ttmr
// replace(s): spr_write, spr_dat_i, ttmr
always @(posedge clk or posedge rst)
	if (rst)
		ttmr <= 32'b0;
	else begin  ttmr <= ttmr_cml_1; if (ttmr_sel && spr_write_cml_1)
		ttmr <= #1 spr_dat_i_cml_1;
	else if (ttmr_cml_1[`OR1200_TT_TTMR_IE])
		ttmr[`OR1200_TT_TTMR_IP] <= #1 ttmr_cml_1[`OR1200_TT_TTMR_IP] | (match & ttmr_cml_1[`OR1200_TT_TTMR_IE]); end
`else
assign ttmr = {2'b11, 30'b0};	// TTMR[M] = 0x3
`endif

//
// Write to or increment of TTCR
//
`ifdef OR1200_TT_TTCR

// SynEDA CoreMultiplier
// assignment(s): ttcr
// replace(s): spr_write, spr_dat_i, ttcr
always @(posedge clk or posedge rst)
	if (rst)
		ttcr <= 32'b0;
	else begin  ttcr <= ttcr_cml_1; if (restart)
		ttcr <= #1 32'b0;
	else if (ttcr_sel && spr_write_cml_1)
		ttcr <= #1 spr_dat_i_cml_1;
	else if (!stop)
		ttcr <= #1 ttcr_cml_1 + 32'd1; end
`else
assign ttcr = 32'b0;
`endif

//
// Read TT registers
//

// SynEDA CoreMultiplier
// assignment(s): spr_dat_o
// replace(s): spr_addr, ttmr, ttcr
always @(spr_addr_cml_1 or ttmr_cml_1 or ttcr_cml_1)
	case (spr_addr_cml_1[`OR1200_TTOFS_BITS])	// synopsys parallel_case
`ifdef OR1200_TT_READREGS
		`OR1200_TT_OFS_TTMR: spr_dat_o = ttmr_cml_1;
`endif
		default: spr_dat_o = ttcr_cml_1;
	endcase

//
// A match when TTMR[TP] is equal to TTCR[27:0]
//

// SynEDA CoreMultiplier
// assignment(s): match
// replace(s): ttmr, ttcr
assign match = (ttmr_cml_1[`OR1200_TT_TTMR_TP] == ttcr_cml_1[27:0]) ? 1'b1 : 1'b0;

//
// Restart when match and TTMR[M]==0x1
//

// SynEDA CoreMultiplier
// assignment(s): restart
// replace(s): ttmr
assign restart = match && (ttmr_cml_1[`OR1200_TT_TTMR_M] == 2'b01);

//
// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 or when RISC is stalled by debug unit
//

// SynEDA CoreMultiplier
// assignment(s): stop
// replace(s): du_stall, ttmr
assign stop = match & (ttmr_cml_1[`OR1200_TT_TTMR_M] == 2'b10) | (ttmr_cml_1[`OR1200_TT_TTMR_M] == 2'b00) | du_stall_cml_1;

//
// Generate an interrupt request
//
assign intr = ttmr[`OR1200_TT_TTMR_IP];

`else

//
// When TT is not implemented, drive all outputs as would when TT is disabled
//
assign intr = 1'b0;

//
// Read TT registers
//
`ifdef OR1200_TT_READREGS
assign spr_dat_o = 32'b0;
`endif

`endif


always @ (posedge clk_i_cml_1) begin
du_stall_cml_1 <= du_stall;
spr_write_cml_1 <= spr_write;
spr_addr_cml_1 <= spr_addr;
spr_dat_i_cml_1 <= spr_dat_i;
ttmr_cml_1 <= ttmr;
ttcr_cml_1 <= ttcr;
end
endmodule