dakies/OSS_Verilog huggingface dataset:
module aibcr3_clkbuf ( out, vcc_pl, vss_pl, in );

output  out;

inout  vcc_pl, vss_pl;

input  in;

// List of primary aliased buses


//FIXIT in CASE 405142:
assign out = ~in;

/*
sa_invg8_ulvt xinv1_1_ ( .vssesa(vss_pl), .vccesa(vcc_pl), .out(out),
     .in(in));
sa_invg8_ulvt xinv1_0_ ( .vssesa(vss_pl), .vccesa(vcc_pl), .out(out),
     .in(in));
*/
endmodule
module aibcr3aux_osc_dly ( clkout, q, scan_out, clk, rstb, scan_clk,
     scan_in, scan_mode_n, scan_rst_n, scan_shift_n, vcc_aibcr3aux,
     vss_aibcr3aux );

output  clkout, q, scan_out;

input  clk, rstb, scan_clk, scan_in, scan_mode_n, scan_rst_n,
     scan_shift_n, vcc_aibcr3aux, vss_aibcr3aux;

wire net060, scan_rst_n, net059, rstb, net28, scan_clk, se_n, scan_shift_n, scanmodn, scan_mode_n, cdn, net30, net27, clk, cp, clkout;

wire net45;
wire net46;
wire net32;
wire net31;
wire net34;
wire net33;
wire net35;
wire net36;
wire net42;
wire net41;
wire net44;
wire net43;
wire net39;
wire net40;
wire net38;
wire net37;

// specify 
//     specparam CDS_LIBNAME  = "aibcr3aux_lib";
//     specparam CDS_CELLNAME = "aibcr3aux_osc_dly";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

aibcr3aux_osc_ff x12 ( .cdn(vss_aibcr3aux), .vbb(vss_aibcr3aux),
     .vss(vss_aibcr3aux), .vdd(vcc_aibcr3aux), .vpp(vcc_aibcr3aux),
     .q(net45), .so(net46), .cp(vss_aibcr3aux), .d(vss_aibcr3aux),
     .se_n(vss_aibcr3aux), .si(vss_aibcr3aux));
aibcr3aux_osc_ff x11 ( .vbb(vss_aibcr3aux), .vss(vss_aibcr3aux),
     .vdd(vcc_aibcr3aux), .vpp(vcc_aibcr3aux), .q(q), .so(scan_out),
     .cdn(cdn), .cp(cp), .d(net32), .se_n(se_n), .si(net31));
aibcr3aux_osc_dly_unit x10 ( .vbb(vss_aibcr3aux), .vss(vss_aibcr3aux),
     .vdd(vcc_aibcr3aux), .vpp(vcc_aibcr3aux), .q(net32), .so(net31),
     .cdn(cdn), .cp(cp), .d(net34), .se_n(se_n), .si(net33));
aibcr3aux_osc_dly_unit x9 ( .vbb(vss_aibcr3aux), .vss(vss_aibcr3aux),
     .vdd(vcc_aibcr3aux), .vpp(vcc_aibcr3aux), .q(net34), .so(net33),
     .cdn(cdn), .cp(cp), .d(net35), .se_n(se_n), .si(net36));
aibcr3aux_osc_dly_unit x5 ( .vbb(vss_aibcr3aux), .vss(vss_aibcr3aux),
     .vdd(vcc_aibcr3aux), .vpp(vcc_aibcr3aux), .q(net42), .so(net41),
     .cdn(cdn), .cp(cp), .d(net44), .se_n(se_n), .si(net43));
aibcr3aux_osc_dly_unit x6 ( .vbb(vss_aibcr3aux), .vss(vss_aibcr3aux),
     .vdd(vcc_aibcr3aux), .vpp(vcc_aibcr3aux), .q(net39), .so(net40),
     .cdn(cdn), .cp(cp), .d(net42), .se_n(se_n), .si(net41));
aibcr3aux_osc_dly_unit x7 ( .vbb(vss_aibcr3aux), .vss(vss_aibcr3aux),
     .vdd(vcc_aibcr3aux), .vpp(vcc_aibcr3aux), .q(net38), .so(net37),
     .cdn(cdn), .cp(cp), .d(net39), .se_n(se_n), .si(net40));
aibcr3aux_osc_dly_unit x8 ( .vbb(vss_aibcr3aux), .vss(vss_aibcr3aux),
     .vdd(vcc_aibcr3aux), .vpp(vcc_aibcr3aux), .q(net35), .so(net36),
     .cdn(cdn), .cp(cp), .d(net38), .se_n(se_n), .si(net37));
aibcr3aux_osc_dly_unit x0 ( .cdn(cdn), .vbb(vss_aibcr3aux),
     .vss(vss_aibcr3aux), .vdd(vcc_aibcr3aux), .vpp(vcc_aibcr3aux),
     .q(net44), .so(net43), .cp(cp), .d(vcc_aibcr3aux), .se_n(se_n),
     .si(scan_in));
assign net060 = scan_rst_n;
assign net059 = rstb;
assign net28 = scan_clk;
assign se_n = scan_shift_n;
assign scanmodn = scan_mode_n;
assign cdn = scanmodn ? net059 : net060;
assign net30 = scanmodn ? net27 : net28;
assign net27 = ~clk;
assign cp = net30;
assign clkout = ~cp;

endmodule
module aibcr3aux_osc_monitor ( out_divby16, out_divby32, out_divby64,
     scan_out, vcc_aibcr3aux, vss_aibcr3aux, clkin, por, scan_clk,
     scan_in, scan_mode_n, scan_rst_n, scan_shift_n );

output  out_divby16, out_divby32, out_divby64, scan_out;

inout  vcc_aibcr3aux, vss_aibcr3aux;

input  clkin, por, scan_clk, scan_in, scan_mode_n, scan_rst_n,
     scan_shift_n;

wire s0;
wire net30;
wire net31;
wire divby8;

// specify 
//     specparam CDS_LIBNAME  = "aibcr3aux_lib";
//     specparam CDS_CELLNAME = "aibcr3aux_osc_monitor";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

aibcr3aux_osc_divby8 xdiv8_1 ( .scan_shift_n(scan_shift_n),
     .scan_out(s0), .scan_clk(scan_clk), .scan_in(scan_in),
     .scan_mode_n(scan_mode_n), .scan_rst_n(scan_rst_n),
     .vss_aibcr3aux(vss_aibcr3aux), .vcc_aibcr3aux(vcc_aibcr3aux),
     .out_divby2(net30), .out_divby4(net31), .out_divby8(divby8),
     .clkin(clkin), .por(por));
aibcr3aux_osc_divby8 xdiv8_2 ( .scan_shift_n(scan_shift_n),
     .scan_out(scan_out), .scan_clk(scan_clk), .scan_in(s0),
     .scan_mode_n(scan_mode_n), .scan_rst_n(scan_rst_n),
     .vss_aibcr3aux(vss_aibcr3aux), .vcc_aibcr3aux(vcc_aibcr3aux),
     .out_divby2(out_divby16), .out_divby4(out_divby32),
     .out_divby8(out_divby64), .clkin(divby8), .por(por));

endmodule
module aibcr3aux_outclkdly
#(
 parameter PERIOD = 500
)
(
output clkout,

input  clkin, clkinb, csr_dly_ovrden, ib50u_ring, ib50uc, vcc_aibcr3aux,
     vssl_aibcr3aux,

input [9:0]  iosc_fuse_trim,
input [3:0]  csr_dly_ovrd

//wire net033 , vssl , nbias , vbias , net032 , nocon0
);



assign #PERIOD clkout =  clkin;

endmodule
module aibcr3aux_lvshift_1p8 ( out1p8, vccl_aibcr3aux, vcca_aibcr3aux, vssl_aibcr3aux, in);

output  out1p8;

input  vccl_aibcr3aux, vcca_aibcr3aux, vssl_aibcr3aux;

input  in;
reg out1p8;
//wire NET58 , in_shift , in_shiftb , inb , in_sw , NET59 ;
//no vccl_aibcr3aux, vcca_aibcr3aux and vssl_aibcr3aux tracking as of now.
always @ (in, vccl_aibcr3aux, vcca_aibcr3aux)
begin
	if (vccl_aibcr3aux == 1'b0 && vcca_aibcr3aux == 1'b0) 
	begin
		out1p8 = 1'b0;		
	end
	else if (vccl_aibcr3aux == 1'b0 && vcca_aibcr3aux == 1'b1)
	begin
		out1p8 = 1'b1;
	end
	else if (vccl_aibcr3aux == 1'b1 && vcca_aibcr3aux == 1'b0)
	begin
		out1p8 = 1'b0;
	end
	else if (vccl_aibcr3aux == 1'b1 && vcca_aibcr3aux == 1'b1)
	begin
		out1p8 = in;
	end
	else
	begin
		out1p8 = 1'bx;
	end	
end
endmodule
module aibcr3aux_osc_clkmux ( out, vcc_aibcraux, vss_aibcraux, ina, inb,
     sel );

output  out;

inout  vcc_aibcraux, vss_aibcraux;

input  ina, inb, sel;

wire net66, ina, net64, net010, net65, sel, inb, out;


// specify 
//     specparam CDS_LIBNAME  = "aibcraux_lib";
//     specparam CDS_CELLNAME = "aibcraux_osc_clkmux";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign net66 = ~(ina & net64);
assign net010 = ~(net66 & net65);
assign net65 = ~(sel & inb);
assign net64 = ~sel;
assign out = net010;

endmodule
module aibcr3pnr_redundancy ( //input of input mux
idata0_in1, idata0_in0, idata1_in1, idata1_in0, 
idataselb_in1, idataselb_in0, iddren_in1, iddren_in0,
irxen_in1, irxen_in0, itxen_in1, itxen_in0, indrv_in1, indrv_in0, ipdrv_in1, ipdrv_in0, async_dat_in1, async_dat_in0, 
//Output of input mux
idata0_out, idata1_out, idataselb_out, iddren_out,
irxen_out, itxen_out, indrv_out, ipdrv_out, async_dat_out,

//input of output mux
odat0_in1, odat0_in0, odat1_in1, odat1_in0, odat_async_in1, odat_async_in0,

//Output of output mux
odat0_out, odat1_out, odat_async_out,

//Mux selection signal
shift_en	//Removed VCCL & VSS port

);

//Power Supply
//input  vccl, vssl;

//Mux selection signal
input shift_en;

//input of input mux
input idata0_in1, idata0_in0; 
input idata1_in1, idata1_in0;
input idataselb_in1, idataselb_in0;
input iddren_in1, iddren_in0;
input [2:0] irxen_in1, irxen_in0;
input itxen_in1, itxen_in0; 
input [1:0] indrv_in1, indrv_in0; 
input [1:0] ipdrv_in1, ipdrv_in0;
input async_dat_in1, async_dat_in0;

//output of input mux
output idata0_out; 
output idata1_out;
output idataselb_out;
output iddren_out;
output [2:0] irxen_out;
output itxen_out; 
output [1:0] indrv_out; 
output [1:0] ipdrv_out;
output async_dat_out;


//input of output mux
input odat0_in1, odat0_in0; 
input odat1_in1, odat1_in0;
input odat_async_in1, odat_async_in0;

//output of output mux
output odat0_out; 
output odat1_out;
output odat_async_out;

// Buses in the design


//input mux
assign idata0_out = shift_en? idata0_in1 : idata0_in0;
assign idata1_out = shift_en? idata1_in1 : idata1_in0;
assign idataselb_out = shift_en? idataselb_in1 : idataselb_in0 ;
assign iddren_out = shift_en? iddren_in1 : iddren_in0;
assign irxen_out[2] = shift_en? irxen_in1[2] : irxen_in0[2];
assign irxen_out[1] = shift_en? irxen_in1[1] : irxen_in0[1];
assign irxen_out[0] = shift_en? irxen_in1[0] : irxen_in0[0];
assign itxen_out = shift_en? itxen_in1 : itxen_in0;
assign indrv_out[1] = shift_en? indrv_in1[1] : indrv_in0[1];
assign indrv_out[0] = shift_en? indrv_in1[0] : indrv_in0[0];
assign ipdrv_out[1] = shift_en? ipdrv_in1[1] : ipdrv_in0[1];
assign ipdrv_out[0] = shift_en? ipdrv_in1[0] : ipdrv_in0[0];

//Change to CKMUX
//assign async_dat_out = shift_en? async_dat_in1 : async_dat_in0;

/* hdstdmacrot20_ckmux21 async_dat_out_ckmux (
						.clk_0(async_dat_in0),
						.clk_1(async_dat_in1),
						.clk_sel(shift_en),
						.clk_o(async_dat_out)
				);
*/

c3lib_mux2_ctn async_dat_out_ckmux (

						.ck0      (async_dat_in0),
						.ck1      (async_dat_in1),
						.s0       (shift_en),
						.ck_out   (async_dat_out)
				);

//output mux
assign odat0_out = shift_en? odat0_in1 : odat0_in0;
assign odat1_out = shift_en? odat1_in1 : odat1_in0;

//Change to CKMUX
//assign odat_async_out = shift_en? odat_async_in1 : odat_async_in0;

/* hdstdmacrot20_ckmux21 odat_async_out_ckmux (
						.clk_0(odat_async_in0),
						.clk_1(odat_async_in1),
						.clk_sel(shift_en),
						.clk_o(odat_async_out)
				);
*/

c3lib_mux2_ctn odat_async_out_ckmux (

						.ck0      (odat_async_in0),
						.ck1      (odat_async_in1),
						.s0       (shift_en),
						.ck_out   (odat_async_out)
				);

endmodule
module aibcr3pnr_half_cycle_code_gen 
#(
parameter FF_DELAY     = 200
)
(
   input  wire          clk,                     //reference clock from pll
   input  wire          reset_n,                 //output for dll reset
   input  wire  [10:0]  pvt_ref_binary,          //output binary pvt value for delay chain; changed from [9:0] to [10:0]
   input  wire          rb_half_code,   	 //select between original or half cycle codes
   output reg   [10:0]  pvt_ref_half_binary 	 //half cycle code (binary) for delay chain; change from [9:0] to [10:0]
);

`ifdef TIMESCALE_EN
  timeunit 1ps;
  timeprecision 1ps;
`endif

wire [7:0]  coarse_bin;                           // change from [6:0] to [7:0]
wire [2:0]  fint_bin, fint_bin_inc;
wire [2:0]  fine_bin;
wire [8:0]  coarse_divided_bin;                   // change from [7:0] to [8:0]
wire [3:0]  fine_divided_bin, coarse_frac_bin;

                        assign  coarse_divided_bin[8:0] = {1'b0,pvt_ref_binary[10:3]}; // changed from pvt_ref_binary[9:3] to [10:3]
                        assign  fine_divided_bin[3:0] = {1'b0,pvt_ref_binary[2:0]};
                        assign  coarse_frac_bin[3:0] = {coarse_divided_bin[0],3'b000};
                        assign  fint_bin[2:0] = coarse_frac_bin[3:1] + fine_divided_bin[3:1];
                        assign  fint_bin_inc[2:0] = ((fine_divided_bin[0] >= 1'd1) && (fint_bin < 3'd7)) ? fint_bin[2:0] + 3'b001 : fint_bin[2:0];

        assign coarse_bin = coarse_divided_bin[8:1]; // change from [7:1] to [8:1]
        assign fine_bin = fint_bin_inc;

        always @(posedge clk or negedge reset_n)
                begin
                        if(~reset_n) begin
				pvt_ref_half_binary <= #FF_DELAY 11'b000_0000_0000;
			end
			else case (rb_half_code)
				1'b0 : pvt_ref_half_binary <= #FF_DELAY pvt_ref_binary;
				1'b1 : pvt_ref_half_binary <= #FF_DELAY {coarse_bin,fine_bin};
				default : pvt_ref_half_binary <= #FF_DELAY {coarse_bin,fine_bin};
			endcase
		end 

endmodule // aibcr3pnr_half_cycle_code_gen
module aibcr3pnr_dll_ctrl (
   input  wire         clk,                     //reference clock from pll
   input  wire         reinit,                  //initialization enable
   input  wire         entest,                  //test enable
   input  wire         ndllrst_in,              //reset from core
   input  wire         rb_dll_en,               //dll enable
   input  wire         rb_dll_rst_en,           //dll reset enable
   input  wire         atpg_en_n,               //atpg
   input  wire         test_clr_n,              //test clear
   output wire         dll_reset_n             //output for dll reset
);

`ifdef TIMESCALE_EN
  timeunit 1ps;
  timeprecision 1ps;
`endif

wire         eni;
wire         dll_rst;

////////////////////////////////////////////////////////////////////
//                                                                //
//  reset and preset                                              //
//                                                                //
////////////////////////////////////////////////////////////////////

assign dll_rst = (rb_dll_rst_en) ?  ~ndllrst_in : 1'b0;                 //core reset at "1" if core_reset enabled
assign eni = ~entest & rb_dll_en & (~reinit) & (~dll_rst);              //dll enable and non-test
//hd_dpcmn_rst_n_sync unrst  ( .rst_n(eni), .rst_n_bypass(test_clr_n), .clk(clk),  .scan_mode_n(atpg_en_n), .rst_n_sync(dll_reset_n) ); 
aibcr3pnr_rstsync unrst ( .rst_n(eni), .rst_n_bypass(test_clr_n), .clk(clk),  .scan_mode_n(atpg_en_n), .rst_n_sync(dll_reset_n) ); 

endmodule // aibcr3pnr_dll_ctrl
module aibcr3_2to4dec ( nsel_out0b, nsel_out1b, nsel_out2b, nsel_out3b,
     psel_out0, psel_out1, psel_out2, psel_out3, vccl, vssl, enable,
     nsel_in, psel_in );

output  nsel_out0b, nsel_out1b, nsel_out2b, nsel_out3b, psel_out0,
     psel_out1, psel_out2, psel_out3;

inout  vccl, vssl;

input  enable;

input [1:0]  nsel_in;
input [1:0]  psel_in;

wire nsel_out2b, enable, nsel_out3b, pserl_out3b, nsel1_en, psel0_en, psel0_enb, nsel_out0b, psel_out1, psel_out1b, nsel0_en, nsel0_enb, psel_out2, pserl_out2b, psel_out3, psel_out0, nsel_out1b;


// specify 
//     specparam CDS_LIBNAME  = "aibcr_lib";
//     specparam CDS_CELLNAME = "aibcr_2to4dec";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign nsel_out2b = !(nsel_in[1] & enable);
assign nsel_out3b = !(enable & nsel_in[0] & nsel_in[1]);
assign pserl_out3b = !(enable & psel_in[0] & psel_in[1]);
assign nsel1_en = !nsel_out2b;
assign psel0_en = !psel0_enb;
assign nsel_out0b = !enable;
assign psel_out1 = !psel_out1b;
assign nsel0_en = !nsel0_enb;
assign psel_out2 = !pserl_out2b;
assign psel_out3 = !pserl_out3b;
assign psel_out0 = enable;
assign psel_out1b = !(psel0_en | psel_out2);
assign nsel_out1b = !(nsel0_en | nsel1_en);
assign pserl_out2b = !(psel_in[1] & enable);
assign nsel0_enb = !(nsel_in[0] & enable);
assign psel0_enb = !(psel_in[0] & enable);

endmodule
module aibcr3_svt16_scdffsdn_cust ( Q, scQ, CK, 
     D, SDN, SE, SI );

output  Q, scQ;

input  SDN, CK, D, SE, SI;

wire Q, net023, se_n, SI, D;
reg  scQ;

assign se_n = !SE;
assign Q = scQ;
assign net023 = se_n ? D : SI;

always@(posedge CK or negedge SDN) begin
        if (!SDN) begin
                scQ <= 1'b1;
        end
        else begin
                scQ <= net023;
        end
end

endmodule
module aibcr3_dll_ibkmux ( SO_OUT, grey, igray, CK, RSTb,
     SE, code_valid, si, sm_grey, sm_igray );

output  SO_OUT;

input  CK, RSTb, SE, code_valid, si;

output [2:0]  igray;
output [6:0]  grey;

input [6:0]  sm_grey;
input [2:0]  sm_igray;

wire code_valid_buf;
wire code_valid_sync;

assign tieHi = 1'b1;

assign net0101 = code_valid_buf? sm_grey[6]  : grey[6];
assign net0100 = code_valid_buf? sm_grey[5]  : grey[5];
assign net104  = code_valid_buf? sm_grey[4]  : grey[4];
assign net107  = code_valid_buf? sm_grey[3]  : grey[3];
assign net106  = code_valid_buf? sm_grey[2]  : grey[2];
assign net108  = code_valid_buf? sm_grey[1]  : grey[1];
assign net109  = code_valid_buf? sm_grey[0]  : grey[0];
assign net0104 = code_valid_buf? sm_igray[2] : igray[2];
assign net0103 = code_valid_buf? sm_igray[1] : igray[1];
assign net0102 = code_valid_buf? sm_igray[0] : igray[0];

assign code_valid_buf = code_valid_sync;
assign SO0            = code_valid_sync;

aibcr3_svt16_scdffcdn_cust x25 ( igray[2], SO_OUT, RSTb,
     CK, net0104, SE, SO9);
aibcr3_svt16_scdffcdn_cust x23 ( igray[1], SO9, RSTb, CK,
     net0103, SE, SO8);
aibcr3_svt16_scdffcdn_cust x21 ( igray[0], SO8, RSTb, CK,
     net0102, SE, SO7);
aibcr3_svt16_scdffcdn_cust x19 ( grey[6], SO7, RSTb, CK,
     net0101, SE, SO6);
aibcr3_svt16_scdffcdn_cust x17 ( grey[5], SO6, RSTb, CK,
     net0100, SE, SO5);
aibcr3_svt16_scdffcdn_cust x7 ( grey[4], SO5, RSTb, CK,
     net104, SE, SO4);
aibcr3_svt16_scdffcdn_cust x6 ( grey[2], SO3, RSTb, CK,
     net106, SE, SO2);
aibcr3_svt16_scdffcdn_cust x4 ( grey[3], SO4, RSTb, CK,
     net107, SE, SO3);
aibcr3_svt16_scdffcdn_cust x2 ( grey[1], SO2, RSTb, CK,
     net108, SE, SO1);
aibcr3_svt16_scdffcdn_cust I316 ( grey[0], SO1, RSTb, CK,
     net109, SE, SO0);

aibcr3_ulvt16_2xarstsyncdff1_b2  I99 ( 
     .Q(code_valid_sync), .CLR_N(RSTb), .CK(CK), 
     .SE(SE), .D(code_valid), .SI(si));

endmodule
module aibcr3_dll_lock_dly ( SOoutd, dcc_done, dll_lock_reg, 
      RSTb, clk_dcd, dll_lock_mux, rb_cont_cal, scan_in,
     scan_shift_n );

output  SOoutd, dcc_done, dll_lock_reg;


input  RSTb, clk_dcd, dll_lock_mux, rb_cont_cal, scan_in, scan_shift_n;

wire net50; 

assign tieHI = 1'b1;
assign tieLO = 1'b0;
assign net079 = net50;
assign SE = !scan_shift_n;
assign dll_lock_reg = rb_cont_cal? tieLO : net079;


aibcr3_svt16_scdffcdn_cust I17 ( net53, net50,   RSTb,
     dll_lock_mux, tieHI, SE, scan_in);
aibcr3_svt16_scdffcdn_cust I13 ( net61, net60,   RSTb,
     clk_dcd, net53, SE, net50);
aibcr3_svt16_scdffcdn_cust I14 ( net69, net68,   RSTb,
     clk_dcd, net61, SE, net60);
aibcr3_svt16_scdffcdn_cust I4 ( net59, net54,   RSTb,
     clk_dcd, net42, SE, net45);
aibcr3_svt16_scdffcdn_cust I2 ( net67, net64,   RSTb,
     clk_dcd, net59, SE, net54);
aibcr3_svt16_scdffcdn_cust I1 ( net77, net74,   RSTb,
     clk_dcd, net67, SE, net64);
aibcr3_svt16_scdffcdn_cust I316 ( dcc_done, SOoutd,   RSTb,
     clk_dcd, net77, SE, net74);
aibcr3_svt16_scdffcdn_cust I15 ( net76, net75,   RSTb,
     clk_dcd, net69, SE, net68);
aibcr3_svt16_scdffcdn_cust I16 ( net42, net45,   RSTb,
     clk_dcd, net76, SE, net75);

endmodule
module aibcr3_dll_dlyline64 ( a63, dlyout, b63, bk, dlyin, CLKIN, iSE, RSTb, iSI, SOOUT
     );

output  a63, dlyout, SOOUT;

input  b63, dlyin, CLKIN, iSE, RSTb, iSI;

input [63:0]  bk;

wire [62:0]  a;
wire [62:0]  b;
wire [62:0]  so;


aibcr3_dlycell_dll UD00 [63:0] (
.in_p       ( {a[62:0],dlyin}    ),
.bk         ( bk[63:0]           ),
.ci_p       ( {b63,b[62:0]}      ),
.out_p      ( {b[62:0], dlyout}  ),
.co_p       ( {a63,a[62:0]}      ),
.ck         ( CLKIN              ),
.si         ( {so[62:0],iSI}     ),
.SE         ( iSE                ),
.RSTb       ( RSTb               ),
.so         ( {SOOUT,so[62:0]}   )
);

endmodule
module aibcr3_ulvt16_dffcdn_cust ( 
	input wire CK,
	input wire CDN,
	input wire D,
	output reg Q
);

always@(posedge CK or negedge CDN) begin
	if (!CDN) begin
		Q <= 1'b0;
	end
	else begin
		Q <= D;
	end
end
endmodule
module aibcr3_ulvt16_dffsdn_cust ( 
	input wire CK,
	input wire SDN,
	input wire D,
	output reg Q
);

always@(posedge CK or negedge SDN) begin
	if (!SDN) begin
		Q <= 1'b1;
	end
	else begin
		Q <= D;
	end
end
endmodule
module aibcr3_clktree_avmm 
#(
parameter SKEW_DELAY     = 60   //min:20ps; typ :60ps; max:100ps
)
(
   input  wire         clkin,                   //clock source
   output wire 	       lstrbclk_l_0, 	        //buffered clock
   output wire         lstrbclk_l_1,            //buffered clock
   output wire         lstrbclk_l_2,            //buffered clock
   output wire         lstrbclk_l_3,            //buffered clock
   output wire         lstrbclk_l_4,            //buffered clock
   output wire         lstrbclk_l_5,            //buffered clock
   output wire         lstrbclk_l_6,            //buffered clock
   output wire         lstrbclk_l_7,            //buffered clock
   output wire         lstrbclk_r_0,            //buffered clock
   output wire         lstrbclk_r_1,            //buffered clock
   output wire         lstrbclk_r_2,            //buffered clock
   output wire         lstrbclk_r_3,            //buffered clock
   output wire         lstrbclk_r_4,            //buffered clock
   output wire         lstrbclk_r_5,            //buffered clock
   output wire         lstrbclk_r_6,            //buffered clock
   output wire         lstrbclk_r_7,            //buffered clock
   output wire         lstrbclk_rep, 	        //replica for DLL
   output wire         lstrbclk_mimic0,         //mimic path for load matching
   output wire         lstrbclk_mimic1,         //mimic path for load matching   
   output wire         lstrbclk_mimic2          //mimic path for load matching
);

`ifdef TIMESCALE_EN
  timeunit 1ps;
  timeprecision 1ps;
`endif
  
                assign #SKEW_DELAY lstrbclk_l_0 = clkin;
                assign #SKEW_DELAY lstrbclk_l_1 = clkin;
                assign #SKEW_DELAY lstrbclk_l_2 = clkin;
                assign #SKEW_DELAY lstrbclk_l_3 = clkin;
                assign #SKEW_DELAY lstrbclk_l_4 = clkin;
                assign #SKEW_DELAY lstrbclk_l_5 = clkin;
                assign #SKEW_DELAY lstrbclk_l_6 = clkin;
                assign #SKEW_DELAY lstrbclk_l_7 = clkin;
                assign #SKEW_DELAY lstrbclk_r_0 = clkin;
                assign #SKEW_DELAY lstrbclk_r_1 = clkin;
                assign #SKEW_DELAY lstrbclk_r_2 = clkin;
                assign #SKEW_DELAY lstrbclk_r_3 = clkin;
                assign #SKEW_DELAY lstrbclk_r_4 = clkin;
                assign #SKEW_DELAY lstrbclk_r_5 = clkin;
                assign #SKEW_DELAY lstrbclk_r_6 = clkin;
                assign #SKEW_DELAY lstrbclk_r_7 = clkin;
                assign #SKEW_DELAY lstrbclk_rep = clkin;
                assign #SKEW_DELAY lstrbclk_mimic0 = clkin;
                assign #SKEW_DELAY lstrbclk_mimic1 = clkin;
                assign #SKEW_DELAY lstrbclk_mimic2 = clkin;

endmodule // aibcr_clktree_avmm
module aibcr3_str_ioload ( in, vcc, vssl );

input  in, vcc, vssl;

// Buses in the design

wire  net5;


// specify 
//     specparam CDS_LIBNAME  = "aibcr_lib";
//     specparam CDS_CELLNAME = "aibcr_str_ioload";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign net5 = ~in ;

endmodule
module aibcr3_rambit_buf ( sig_out, sig_in, vcc, vssl );

output  sig_out;

input  sig_in, vcc, vssl;

wire sig_out, sig_in;


// specify 
//     specparam CDS_LIBNAME  = "aibcr_lib";
//     specparam CDS_CELLNAME = "aibcr_rambit_buf";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign sig_out = sig_in;

endmodule
module aibcr3_clktree_mimic 
#(
parameter SKEW_DELAY     = 60   //min:20ps; typ :60ps; max:100ps
)
(
   input  wire         clkin,                   //clock source
   output wire 	       lstrbclk_l_0, 	        //buffered clock
   output wire         lstrbclk_l_1,            //buffered clock
   output wire         lstrbclk_l_2,            //buffered clock
   output wire         lstrbclk_l_3,            //buffered clock
   output wire         lstrbclk_l_4,            //buffered clock
   output wire         lstrbclk_l_5,            //buffered clock
   output wire         lstrbclk_l_6,            //buffered clock
   output wire         lstrbclk_l_7,            //buffered clock
   output wire         lstrbclk_l_8,            //buffered clock
   output wire         lstrbclk_l_9,            //buffered clock
   output wire         lstrbclk_l_10,           //buffered clock
   output wire         lstrbclk_l_11,           //buffered clock
   output wire         lstrbclk_rep, 	        //replica for DLL
   output wire         lstrbclk_mimic0         //mimic path for load matching
);

`ifdef TIMESCALE_EN
  timeunit 1ps;
  timeprecision 1ps;
`endif
  
                assign #SKEW_DELAY lstrbclk_l_0 = clkin;
                assign #SKEW_DELAY lstrbclk_l_1 = clkin;
                assign #SKEW_DELAY lstrbclk_l_2 = clkin;
                assign #SKEW_DELAY lstrbclk_l_3 = clkin;
                assign #SKEW_DELAY lstrbclk_l_4 = clkin;
                assign #SKEW_DELAY lstrbclk_l_5 = clkin;
                assign #SKEW_DELAY lstrbclk_l_6 = clkin;
                assign #SKEW_DELAY lstrbclk_l_7 = clkin;
                assign #SKEW_DELAY lstrbclk_l_8 = clkin;
                assign #SKEW_DELAY lstrbclk_l_9 = clkin;
                assign #SKEW_DELAY lstrbclk_l_10 = clkin;
                assign #SKEW_DELAY lstrbclk_l_11 = clkin;
                assign #SKEW_DELAY lstrbclk_rep = clkin;
                assign #SKEW_DELAY lstrbclk_mimic0 = clkin;

endmodule // aibcr_clktree_mimic
module aibcr3_io_cmos_8ph_interpolator (
input         nfrzdrv,
input         fout_p,
input         fout_n,
input   [2:0] gray,
output        out_p,
output        out_n,
output        osc_out_p,
output        osc_out_n
);

`ifdef TIMESCALE_EN
		timeunit 1ps; 
		timeprecision 1ps; 
`endif

parameter   NAND_DELAY = 20;

wire         a_in_p;
wire         b_in_p;
wire         c_in_p;
wire         a_in_n;
wire         b_in_n;
wire         c_in_n;
wire         x_p;
wire         x_n;
wire         x_pb;
wire         x_nb;
wire  [6:0]  sn;
reg   [6:0]  sp;

assign #(0 * NAND_DELAY) a_in_p = nfrzdrv? fout_p : 1'b0;
assign #(2 * NAND_DELAY) b_in_p = nfrzdrv? fout_p : 1'b0;
assign #(4 * NAND_DELAY) c_in_p = nfrzdrv? fout_p : 1'b0;

assign #(0 * NAND_DELAY) a_in_n = nfrzdrv? fout_n : 1'b1;
assign #(2 * NAND_DELAY) b_in_n = nfrzdrv? fout_n : 1'b1;
assign #(4 * NAND_DELAY) c_in_n = nfrzdrv? fout_n : 1'b1;

always @(*)
  case (gray[2:0])
    3'b000 :  sp[6:0] = 7'b000_0000;
    3'b001 :  sp[6:0] = 7'b000_0001;
    3'b011 :  sp[6:0] = 7'b000_0011;
    3'b010 :  sp[6:0] = 7'b000_0111;
    3'b110 :  sp[6:0] = 7'b000_1111;
    3'b111 :  sp[6:0] = 7'b001_1111;
    3'b101 :  sp[6:0] = 7'b011_1111;
    3'b100 :  sp[6:0] = 7'b111_1111;
  endcase

assign sn[6:0] = ~sp[6:0];

aibcr3_io_ip8phs x8phs_n (
.c_in     ( {c_in_n, b_in_n, a_in_n} ),
.sp       ( sp[6:0]                ),
.sn       ( sn[6:0]                ),
.c_out    ( x_n                    )
);

aibcr3_io_ip8phs x8phs_p (
.c_in     ( {c_in_p, b_in_p, a_in_p} ),
.sp       ( sp[6:0]                ),
.sn       ( sn[6:0]                ),
.c_out    ( x_p                    )
);

//cross couple
assign x_pb = ~x_p;
assign x_nb = ~x_n;
assign out_p = ~x_pb;
assign out_n = ~x_nb;
assign osc_out_p = ~x_pb;
assign osc_out_n = ~x_nb;

`ifdef LEC
assign x_p = ~x_n;
assign x_n = ~x_p;
`endif

endmodule
module aibcr3_buffx1 ( oclk, oclkb, oclkn, odat0, odat1, odat_async,
     pd_data, iopad, async_dat, clkdr, iclkin_dist,
     iclkn, idat0, idat1, idataselb, iddren, ilaunch_clk, ilpbk_dat,
     ilpbk_en, indrv, ipadrstb, ipdrv, irstb, irxen, istrbclk, itxen,
     por_aib_vcc1, por_aib_vcchssi, test_weakpd, test_weakpu,
     testmode_en);

output  oclk, oclkb, oclkn, odat0, odat1, odat_async, pd_data;

inout  iopad;

input  async_dat, clkdr, iclkin_dist, iclkn, idat0, idat1, idataselb,
     iddren, ilaunch_clk, ilpbk_dat, ilpbk_en, ipadrstb, irstb,
     istrbclk, itxen, por_aib_vcc1, por_aib_vcchssi, test_weakpd,
     test_weakpu, testmode_en;

input [1:0]  ipdrv;
input [1:0]  indrv;
input [2:0]  irxen;

// Buses in the design

wire  [1:0]  ipdrv_buf;

wire  [1:0]  indrv_buf;


aibcr3_analog x0 ( oclkb, oclk, rx_idat, odat_async, 
     iopad, clkbuf_en, datbuf_en, iclkn, indrv_buf[1:0],
     ipdrv_buf[1:0], itx_en_buf, por_aib_vcc1, por_aib_vcchssi, tx_dat,
     weak_pulldownen, weak_pullupenb);
aibcr3_digital x1 ( clkbuf_en, datbuf_en, indrv_buf[1:0],
     ipdrv_buf[1:0], itx_en_buf, odat0, odat1, pd_data, net18, net17,
     net16, tx_dat, weak_pulldownen, weak_pullupenb, 
     async_dat, clkdr, iclkin_dist, idat0, idat1, idataselb, iddren,
     ilaunch_clk, ilpbk_dat, ilpbk_en, indrv[1:0], ipadrstb,
     ipdrv[1:0], irstb, irxen[2:0], istrbclk, itxen, rx_idat,
     test_weakpd, test_weakpu, testmode_en);

/*
rm5xa  R0 ( .PLUS(iopad), .MINUS(oclkn));
*/

assign oclkn = iopad;

endmodule
module aibcr3_data_buf ( sig_out, sig_in, vcc, vssl );

output  sig_out;

input  sig_in, vcc, vssl;

wire sig_out, sig_in;


// specify 
//     specparam CDS_LIBNAME  = "aibcr_lib";
//     specparam CDS_CELLNAME = "aibcr_data_buf";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign sig_out = sig_in;

endmodule
module aibcr3_preclkbuf ( out, vcc_pl, vss_pl, in );

output  out;

inout  vcc_pl, vss_pl;

input  in;


// specify 
//     specparam CDS_LIBNAME  = "aibcr_lib";
//     specparam CDS_CELLNAME = "aibcr_preclkbuf";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify


//sa_invg8_ulvt xinv1 ( .vssesa(vss_pl), .vccesa(vcc_pl), .out(out),     .in(in));
assign out = !in;

endmodule
module aibcr3_dcc_dlyline64 ( a63, dlyout, b63, bk, dlyin
     );

output  a63, dlyout;

input  b63, dlyin;

input [63:0]  bk;

wire [62:0]  a;
wire [62:0]  b;

aibcr3_dlycell_dcc UD00 [63:0] (
.in_p       ( {a[62:0],dlyin}    ),
.bk         ( bk[63:0]           ),
.ci_p       ( {b63,b[62:0]}      ),
.out_p      ( {b[62:0], dlyout}  ),
.co_p       ( {a63,a[62:0]}      )
);

endmodule
module aibcr3_red_custom_dig ( anlg_rstb_out, anlg_rstb,
     prev_io_shift_en, shift_en );

output  anlg_rstb_out;

input  anlg_rstb, prev_io_shift_en, shift_en;

wire anlg_rst_nd_out;
wire io_disable_b;

assign anlg_rstb_out = !anlg_rst_nd_out;
assign prev_io_shenb = !prev_io_shift_en;
assign anlg_rst_nd_out = !(io_disable_b & anlg_rstb);
assign io_disable_b = !(prev_io_shenb & shift_en);


endmodule
module aibcr3_dcc_dll ( clk_dcc, dcc_done, odll_dll2core, odll_lock,
     pvt_ref_half_gry, scan_out, clk_dcd, clk_pll,
     csr_reg, idll_core2dll, idll_entest, nfrzdrv, nrst,
     pipeline_global_en, rb_clkdiv, rb_cont_cal, rb_dcc_byp,
     rb_half_code, rb_selflock, reinit, scan_clk_in, scan_in,
     scan_mode_n, scan_rst_n, scan_shift_n, test_clk_pll_en_n );

output  clk_dcc, dcc_done, odll_lock, scan_out;


input  clk_dcd, clk_pll, idll_entest, nfrzdrv, nrst,
     pipeline_global_en, rb_cont_cal, rb_dcc_byp, rb_half_code,
     rb_selflock, reinit, scan_clk_in, scan_in, scan_mode_n,
     scan_rst_n, scan_shift_n, test_clk_pll_en_n;

output [12:0]  odll_dll2core;
output [10:0]  pvt_ref_half_gry;

input [2:0]  idll_core2dll;
input [2:0]  rb_clkdiv;
input [51:0]  csr_reg;

// Buses in the design

wire  [2:0]  i_gray;

wire  [10:0]  pvt_ref_gry;

wire  [7:0]  f_gray;

wire  [6:0]  gate_shf;

wire dll_phdet_reset_n;
wire launch;

aibcr3_dll_custom I0 ( clk_dcc, dcc_done, so_dll_custom, t_down, t_up,
       clk_dcd, odll_lock, dll_phdet_reset_n, f_gray[7:0],
     i_gray[2:0], launch, measure, nfrzdrv, nrst,
     pvt_ref_half_gry[10:0], rb_cont_cal, rb_dcc_byp, scan_clk_in,
     scan_in, scan_mode_n, scan_rst_n, scan_shift_n);

aibcr3pnr_dll_pnr I1 ( .dll_core(odll_dll2core[12:0]), .dll_lock(odll_lock),
     .dll_phdet_reset_n(dll_phdet_reset_n), .f_gray(f_gray[7:0]), .gate_shf(gate_shf[6:0]), .i_gray(i_gray[2:0]),
     .launch (launch), .measure(measure), .pvt_ref_gry(pvt_ref_gry[10:0]), .pvt_ref_half_gry(pvt_ref_half_gry[10:0]),
     .scan_out(scan_out), .clk_pll(clk_pll), .core_dll(idll_core2dll[2:0]), .csr_reg(csr_reg[51:0]), .entest(idll_entest),
     .pipeline_global_en(pipeline_global_en), .rb_clkdiv(rb_clkdiv[2:0]), .rb_half_code(rb_half_code), .rb_selflock(rb_selflock),
     .reinit(reinit), .scan_clk_in(scan_clk_in), .scan_in(so_dll_custom), .scan_mode_n(scan_mode_n), .scan_rst_n(scan_rst_n),
     .scan_shift_n(scan_shift_n), .t_down(t_down), .t_up(t_up), .test_clk_pll_en_n(test_clk_pll_en_n));

endmodule
module aibcr3_nd2d0_custom (zn, a1, a2, vcc_regphy, vss_io );

  output zn;
  input a2;
  input a1;
  input vss_io;
  input vcc_regphy;

  assign zn = ~(a1 && a2) ;

endmodule
module aibcr3_anaio_esd (osc_extrref);

  inout osc_extrref;

endmodule
module aibcr3_str_ff ( Q, so , CDN, CP,
     D, code_valid, se_n, si );

output  Q, so;

input  CDN, CP, D, code_valid, se_n, si;

wire Q, so, net030, code_valid, D, net023, se_n, si;

assign Q = so;
assign net030 = code_valid ? D : so;
assign net023 = se_n ? net030 : si;
 aibcr3_ff_r xff0 ( .Q(so), .CDN(CDN), .CP(CP),      .D(net023));

endmodule
module aibcr3_clktree_avmm_mimic 
#(
parameter SKEW_DELAY     = 60   //min:20ps; typ :60ps; max:100ps
)
(
   input  wire         clkin,                   //clock source
   output wire 	       lstrbclk_l_0, 	        //buffered clock
   output wire         lstrbclk_l_1,            //buffered clock
   output wire         lstrbclk_l_2,            //buffered clock
   output wire         lstrbclk_l_3,            //buffered clock
   output wire         lstrbclk_l_4,            //buffered clock
   output wire         lstrbclk_l_5,            //buffered clock
   output wire         lstrbclk_l_6,            //buffered clock
   output wire         lstrbclk_l_7,            //buffered clock
   output wire         lstrbclk_rep, 	        //replica for DLL
   output wire         lstrbclk_mimic0         //mimic path for load matching
);

`ifdef TIMESCALE_EN
  timeunit 1ps;
  timeprecision 1ps;
`endif
  
                assign #SKEW_DELAY lstrbclk_l_0 = clkin;
                assign #SKEW_DELAY lstrbclk_l_1 = clkin;
                assign #SKEW_DELAY lstrbclk_l_2 = clkin;
                assign #SKEW_DELAY lstrbclk_l_3 = clkin;
                assign #SKEW_DELAY lstrbclk_l_4 = clkin;
                assign #SKEW_DELAY lstrbclk_l_5 = clkin;
                assign #SKEW_DELAY lstrbclk_l_6 = clkin;
                assign #SKEW_DELAY lstrbclk_l_7 = clkin;
                assign #SKEW_DELAY lstrbclk_rep = clkin;
                assign #SKEW_DELAY lstrbclk_mimic0 = clkin;

endmodule // aibcr_clktree_avmm_mimic
module aibcr3_dlycell_dcc_rep ( co_p, out_p, bk, ci_p, in_p );

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

output  co_p, out_p;

input  bk, ci_p, in_p;

wire bkbl;

parameter   BUF_DELAY = 20;

assign net0150 = ~in_p;
assign bkb     = ! bk;
assign net0173 = ! (net0150 & bk);
assign net0174 = ! (net0150 & bkb);
assign bkl     = ! (net0173 & bkbl);
assign bkbl    = ! (net0174 & bkl);

assign #BUF_DELAY co_p = bkl? in_p : 1'b0;
assign #BUF_DELAY out_p = bkl? ci_p : in_p;

endmodule
module aibcr3_cmos_nand_x1 (
input  bk, ci_p, ck, in_p, nrst, se_n, si, code_valid,
output  co_p, out_p, so
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

wire bk_sync;


parameter   NAND_DELAY = 15; //min: 5ps; typ: 7ps; max: 15ps

reg    tp;

aibcr3_str_ff xreg0 ( .se_n(se_n), .so(so), .si(si), .CDN(nrst), .CP(ck), .D(bk), .code_valid(code_valid), .Q(bk_sync));

assign #NAND_DELAY co_p  = ~(in_p & bk_sync);

always @(*)
  if (~in_p)    tp <= #NAND_DELAY 1'b1;
  else if (~bk_sync) tp <= #NAND_DELAY 1'b0;

assign #NAND_DELAY out_p = ~(tp & ci_p);

endmodule
module aibcr3_ff_rp ( 
	input wire CP,
	input wire CDN,
	input wire SDN,
	input wire D,
	output reg Q
);

always@(posedge CP or negedge CDN or negedge SDN) begin
	if (!CDN) begin
		Q <= 1'b0;
	end
	else if (!SDN) begin
		Q <= 1'b1;
	end
	else begin
		Q <= D;
	end
end
endmodule
module aibcr3_dcc_top_dummy ( clk_dcc, dcc_done, clk_dcd, dcc_req,
     vcc_aibcr, vcc_io, vss_aibcr );

output  clk_dcc, dcc_done;

input  clk_dcd, dcc_req, vcc_aibcr, vcc_io, vss_aibcr;

wire clk_dcc, clk_dcd;


// specify 
//     specparam CDS_LIBNAME  = "aibcr_lib";
//     specparam CDS_CELLNAME = "aibcr_dcc_top_dummy";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

// aibcr3_sync_2ff  xsync0 (      .SE(vss_aibcr), .D(vcc_aibcr),  .Q(dcc_done),     .CP(clk_dcc),  .SI(vss_aibcr), .CDN(dcc_req));


assign tie_LO = 1'b0;
assign tie_HI = 1'b1;

aibcr3_ulvt16_2xarstsyncdff1_b2 x1 ( .SE (tie_LO), .SI (tie_LO), .Q(dcc_done), .D (tie_HI), .CK (clk_dcc), .CLR_N (dcc_req));

assign clk_dcc = clk_dcd;


endmodule
module aibcr3_clkmux2 ( oclk_out, mux_sel, oclk_in0, oclk_in1, vcc, vssl
     );

output  oclk_out;

input  mux_sel, oclk_in0, oclk_in1, vcc, vssl;

 

assign oclk_out = mux_sel ?  oclk_in1 : oclk_in0 ;



endmodule
module aibcr3_dcc_crsdlyline ( SOOUT, bk, crsDLY, CLK,
     CLKIN, PDb, SE, SI, gry );

output  SOOUT, crsDLY;

input  CLK, CLKIN, PDb, SE, SI;

output [255:0]  bk;

input [10:3]  gry;

// Buses in the design

wire  [0:4]  net0118;

wire  [0:5]  net0119;

wire  [0:4]  net0120;

wire  [6:0]  cgry;

wire  [6:0]  bgry;

wire  [6:0]  dgry;

wire  [6:0]  agry;

wire         gry9b;
wire         gry10b;
wire	     SO_crc;
wire         net082;
wire         net096;
wire         net0108;

// scan out pin
assign SOOUT = SO_crc;

// 4x delay line, each containing 64 delay cells
aibcr3_dcc_dlyline64 I10 ( net14, net18, net14,
     bk[255:192], net15);
aibcr3_dcc_dlyline64 I9 ( net15, net17, net18,
     bk[191:128], net16);
aibcr3_dcc_dlyline64 I1 ( net16, dly64, net17, bk[127:64],
     clk64);
aibcr3_dcc_dlyline64 I8 ( clk64, crsDLY, dly64, bk[63:0],
     CLK);

// 4x gray to thermometer code conversion
aibcr3_dcc_gry2thm64 I6 ( net097, bk[63:0], net0128, RSTb,
     agry[6:0], SE, SI);
aibcr3_dcc_gry2thm64 I5 ( net0101, bk[127:64], net0126,
     RSTb, bgry[6:0], SE, net097);
aibcr3_dcc_gry2thm64 I3 ( net0103, bk[191:128], net0124,
     RSTb, cgry[6:0], SE, net0101);
aibcr3_dcc_gry2thm64 I15 ( SO_crc, bk[255:192], net0122,
     RSTb, dgry[6:0], SE, net0103);

// combinatorial logic
assign agry[5:0] = gry[8:3];
assign ENDbar = ~cgry[6];
assign ENCbar = ~bgry[6];
assign agry[6] = ~(gry9b & gry10b);
assign ENBbar = ~agry[6];
//assign tie_HI = 1'b1;
assign net0122 = CLKIN;
assign net0124 = CLKIN;
assign net0128 = CLKIN;
assign net0126 = CLKIN;
assign RSTb    = PDb;
assign bgry[5] = ~(gry[8] | ENBbar);
assign dgry[4:0] = ~(net0120[0:4] | {ENDbar,ENDbar,ENDbar,ENDbar,ENDbar} );
assign dgry[5] = ~(gry[8] | ENDbar);
assign cgry[5:0] = ~(net0119[0:5] | {ENCbar,ENCbar,ENCbar,ENCbar,ENCbar,ENCbar});
assign bgry[4:0] = ~(net0118[0:4] | {ENBbar,ENBbar,ENBbar,ENBbar,ENBbar});
assign gry9b = ~gry[9];
assign gry10b = ~gry[10];
assign net0120[0:4] = ~gry[7:3];
assign net082 = ~( gry[3] | gry[4] | gry[5] );
assign net0108 = ~( gry[6] | gry[7] | gry[8] );
assign net096 = ~( net082 & net0108 );
assign dgry[6] = ~( net096 | gry[9] | gry10b );
assign net0119[0:5] = ~gry[8:3];
assign bgry[6] = gry[10];
assign cgry[6] = ~ ( gry[9] | gry10b );
assign net0118[0:4] = ~gry[7:3];


endmodule
module aibcr3_red_custom_dig2 ( iclkin_dist_aib, ilaunch_clk_aib,
     istrbclk_aib, oclk_out, oclkb_out, clkdr_in,
     iclkin_dist_in0, iclkin_dist_in1, ilaunch_clk_in0,
     ilaunch_clk_in1, istrbclk_in0, istrbclk_in1, jtag_clksel,
     oclk_aib, oclk_in1, oclkb_aib, oclkb_in1, shift_en );

output  iclkin_dist_aib, ilaunch_clk_aib, istrbclk_aib, oclk_out,
     oclkb_out;


input  clkdr_in, iclkin_dist_in0, iclkin_dist_in1, ilaunch_clk_in0,
     ilaunch_clk_in1, istrbclk_in0, istrbclk_in1, jtag_clksel,
     oclk_aib, oclk_in1, oclkb_aib, oclkb_in1, shift_en;

wire jtag_clksel_buf;
wire ilaunch_clk_mux;
wire iclkin_dist_muxb;
wire net190;
wire jtag_clksel_b;

assign shift_enbuf = shift_en;
assign lclk_s0     = ~ (shift_enbuf | jtag_clksel_buf);
assign oclkb_mux   = shift_enbuf ? oclkb_in1 : oclkb_aib;
assign oclk_mux    = shift_enbuf ? oclk_in1  : oclk_aib ;  
assign istrbclk_mux = shift_enbuf ? istrbclk_in1 : istrbclk_in0;
assign iclkin_dist_mux = shift_enbuf ? iclkin_dist_in1 : iclkin_dist_in0;
assign oclk_muxb = ~ oclk_mux;
assign oclk_out  = ~ oclk_muxb;
assign oclkb_muxb= ~ oclkb_mux;
assign oclkb_out = ~ oclkb_muxb;
assign istrbclk_muxb = ~ istrbclk_mux;
assign ilaunch_clk_muxb = ~ ilaunch_clk_mux;
assign ilaunch_clk_aib  = ~ ilaunch_clk_muxb;
assign iclkin_dist_aib  = ~ iclkin_dist_muxb;
assign iclkin_dist_muxb = ~ iclkin_dist_mux;
assign istrbclk_aib = ~ istrbclk_muxb;
assign lclk_s1 = ~ net190;
assign jtag_clksel_buf = ~ jtag_clksel_b ;
assign jtag_clksel_b   = ~ jtag_clksel ;
assign net184 = ~ ( clkdr_in & jtag_clksel_buf );
assign net183 = ~ ( ilaunch_clk_in1 & lclk_s1 );
assign net189 = ~ ( ilaunch_clk_in0 & lclk_s0 );
assign net190 = ~ ( shift_enbuf     & jtag_clksel_b );
assign ilaunch_clk_mux = ~ ( net189 & net183 & net184 );


endmodule
module aibcr3_rxdat_mimic (
	input wire odat_in,
	input wire vcc_aibcr,
	input wire vss_aibcr,
	output wire odat_out
);

	assign odat_out = odat_in;

endmodule
module aibcr3_svt16_scdffcdn_cust ( Q, scQ, 
     CDN, CK, D, SE, SI );

output  Q, scQ;

input  CDN, CK, D, SE, SI;

wire Q, net023, se_n, SI, D;
reg  scQ;

assign se_n = !SE;
assign Q = scQ;
assign net023 = se_n ? D : SI;

always@(posedge CK or negedge CDN) begin
        if (!CDN) begin
                scQ <= 1'b0;
        end
        else begin
                scQ <= net023;
        end
end

endmodule
module aibcr3_digital ( clkbuf_en, datbuf_en, indrv_buf, ipdrv_buf,
     itx_en_buf, odat0, odat1, pd_dataout, rx_disable, sync_datbuf_en0,
     sync_datbuf_en1, tx_dat, weak_pulldownen, weak_pullupenb, 
      async_data, clkdr, iclkin_dist, idat0, idat1,
     idataselb, iddrctrl, ilaunch_clk, ilpbk_dat, ilpbk_en, indrv,
     ipadrstb, ipdrv, irstb, irxen, istrbclk, itx_en, rx_idat,
     test_weakpd, test_weakpu, testmode_en 
);

output  clkbuf_en, datbuf_en, itx_en_buf, odat0, odat1, pd_dataout,
     rx_disable, sync_datbuf_en0, sync_datbuf_en1, tx_dat,
     weak_pulldownen, weak_pullupenb;


input  async_data, clkdr, iclkin_dist, idat0, idat1, idataselb,
     iddrctrl, ilaunch_clk, ilpbk_dat, ilpbk_en, ipadrstb, irstb,
     istrbclk, itx_en, rx_idat, test_weakpd, test_weakpu, testmode_en;


output [1:0]  ipdrv_buf;
output [1:0]  indrv_buf;

input [1:0]  ipdrv;
input [1:0]  indrv;
input [2:0]  irxen;


aibcr3_rxdig x3 ( clkbuf_en, datbuf_en, odat0, odat1, rx_disable,
     pd_dataout, sync_datbuf_en0, sync_datbuf_en1,
     iclkin_dist, ipadrstb, irstb, irxen[2:0], istrbclk, rx_idat);
aibcr3_txdig x1 ( indrv_buf[1:0], ipdrv_buf[1:0], itx_en_buf, tx_dat,
     weak_pulldownen, weak_pullupenb, async_data, clkdr,
     idat0, idat1, idataselb, iddrctrl, ilaunch_clk, ilpbk_dat,
     ilpbk_en, indrv[1:0], ipadrstb, ipdrv[1:0], irstb, itx_en,
     rx_disable, test_weakpd, test_weakpu, testmode_en);

endmodule
module aibcr3_quadph_code_gen 
#(
parameter FF_DELAY     = 200
)
(
   input  wire         clk,                     //reference clock from pll
   input  wire         reset_n,                 //output for dll reset
   input  wire  [9:0]  pvt_ref_binary,          //output binary pvt value for delay chain
   input  wire         rb_quad_code,   		//select between original or quadrature codes
   output reg   [9:0]  pvt_ref_quad_binary 	//quadrature code (binary) for delay chain
);

`ifdef TIMESCALE_EN
  timeunit 1ps;
  timeprecision 1ps;
`endif

wire [6:0]  coarse_bin;
reg [2:0]  fint_bin;
wire [2:0]  fine_bin;
reg [8:0]  coarse_divided_bin;
reg [4:0]  fine_divided_bin, coarse_frac_bin;

          always @(*)
                begin
                        if(~reset_n) begin
                                coarse_divided_bin = 9'b0_0000_0000;
                                fine_divided_bin = 5'b0_0000;
                                coarse_frac_bin = 5'b0_0000;
                                fint_bin = 3'b000;
                        end
                        else  begin
                                coarse_divided_bin = {2'b00,pvt_ref_binary[9:3]};
                                fine_divided_bin = {2'b00,pvt_ref_binary[2:0]};
//                                coarse_frac_bin = {1'b0,coarse_divided_bin[1:0],2'b00};  //****need to finalize what's the ratio between coarse/fine steps. current coding assumes 20ps/5ps=4
                                coarse_frac_bin = {coarse_divided_bin[1:0],3'b000};
                                fint_bin = coarse_frac_bin[4:2] + fine_divided_bin[4:2];
                                         if ((fine_divided_bin[1:0] >= 2'd2)) begin
                                                fint_bin = fint_bin + 3'b001;
                                         end
                                         else begin
                                                fint_bin = fint_bin;
                                         end
                         end
                end

        assign coarse_bin = coarse_divided_bin[8:2];
 	assign fine_bin = fint_bin;

        always @(posedge clk or negedge reset_n)
                begin
                        if(~reset_n) begin
				pvt_ref_quad_binary <= #FF_DELAY 10'b00_0000_0000;
			end
			else case (rb_quad_code)
				1'b0 : pvt_ref_quad_binary <= #FF_DELAY pvt_ref_binary;
				1'b1 : pvt_ref_quad_binary <= #FF_DELAY {coarse_bin,fine_bin};
				default : pvt_ref_quad_binary <= #FF_DELAY {coarse_bin,fine_bin};
			endcase
		end 

endmodule // aibcr_quadph_code_gen
module aibcr3_txdat_mimic (
	input wire idat_in,
	input wire vcc_aibcr,
	input wire vss_aibcr,
	output wire idat_out
);

	assign idat_out = idat_in;

endmodule
module aibcr3_io_nand_x128_delay_line (
input         nfrzdrv,
input         in_p,
input         in_n,
input         osc_mode,           // Mux control for the x64 ring oscillator
input         osc_in_p,           // input for the x64 ring oscillator
input         osc_in_n,           // input for the x64 ring oscillator
output        osc_out_p,          // output for the x64 ring oscillator
output        osc_out_n,          // output for the x64 ring oscillator
input   [6:0] f_gray,
input   [2:0] i_gray,
output        out_p,
output        out_n
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter   NAND_DELAY         = 20;

wire         fout_p;
wire         fout_n;
wire         x128_in_p;
wire         x128_in_n;

//---------------------------------------------------------------------------------------------------------------------------------------------
//  input mux
//---------------------------------------------------------------------------------------------------------------------------------------------

assign x128_in_p  = osc_mode ? osc_in_p : in_p;
assign x128_in_n  = osc_mode ? osc_in_n : in_n;

aibcr3_io_cmos_nand_x128 #(
.NAND_DELAY  ( NAND_DELAY   )
) xnand128 (
.in_p        ( x128_in_p    ),
.in_n        ( x128_in_n    ),
.gray        ( f_gray[6:0]  ),
.out_p       ( fout_p       ),
.out_n       ( fout_n       )
);

aibcr3_io_cmos_8ph_interpolator xinterp (
.nfrzdrv    ( nfrzdrv     ),
.fout_p     ( fout_p      ),
.fout_n     ( fout_n      ),
.gray       ( i_gray[2:0] ),
.out_p      ( out_p       ),
.out_n      ( out_n       ),
.osc_out_p  ( osc_out_p   ),
.osc_out_n  ( osc_out_n   )

);

endmodule
module aibcr3_dlycell_dcc ( co_p, out_p, bk, ci_p, in_p );

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

output  co_p, out_p;

input  bk, ci_p, in_p;

wire bkbl;

parameter   BUF_DELAY = 20;

assign net0150 = ~in_p;
assign bkb     = ! bk;
assign net0173 = ! (net0150 & bk);
assign net0174 = ! (net0150 & bkb);
assign bkl     = ! (net0173 & bkbl);
assign bkbl    = ! (net0174 & bkl);

assign #BUF_DELAY co_p = bkl? in_p : 1'b0;
assign #BUF_DELAY out_p = bkl? ci_p : in_p;

endmodule
module aibcr3_ulvt16_2xarstsyncdff1_b2 (CLR_N, CK, D, SE, SI, Q);
    input CLR_N, CK, D, SE, SI;
    output reg Q;
    wire data;
    reg flop_0;

        assign data = SE ?  SI : D ; 
	
	always @(posedge CK or negedge CLR_N)
		if (!CLR_N) {Q,flop_0} <= 0;
		else if (CLR_N) {Q,flop_0} <= {flop_0,data};
		else {Q,flop_0} <= 0;
endmodule
module aibcr3_aliasv (ra, rb);
 inout rb, ra;
 wire w;
  assign ra = w;
  assign rb = w;
endmodule
module aibcr3_ff_r ( 
	input wire CP,
	input wire CDN,
	input wire D,
	output reg Q
);

always@(posedge CP or negedge CDN) begin
	if (!CDN) begin
		Q <= 1'b0;
	end
	else begin
		Q <= D;
	end
end
endmodule
module aibcr3_io_cmos_nand_x128 (
input         in_p,
input         in_n,
input   [6:0] gray,
output        out_p,
output        out_n 
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter   NAND_DELAY = 20;

wire   [5:0]  b_gray;
wire          a63;
wire          b63;
wire          c63;
wire          d63;
wire          a63dum;
wire          c63dum;


assign b_gray[5] =  ~gray[5] & gray[6];
assign b_gray[4] =   gray[4] & gray[6];
assign b_gray[3] =   gray[3] & gray[6];
assign b_gray[2] =   gray[2] & gray[6];
assign b_gray[1] =   gray[1] & gray[6];
assign b_gray[0] =   gray[0] & gray[6];

aibcr3_io_cmos_nand_x64 xnand64a (
.b63        ( b63                 ),
.d63        ( d63                 ),
.in_p       ( in_p                ),
.in_n       ( in_n                ),
.gray       ( gray[6:0]           ),
.a63        ( a63                 ),
.c63        ( c63                 ),
.out_p      ( out_p               ),
.out_n      ( out_n               )
);

aibcr3_io_cmos_nand_x64 xnand64b (
.b63        ( 1'b1                ),
.d63        ( 1'b1                ),
.in_p       ( a63                 ),
.in_n       ( c63                 ),
.gray       ( {1'b0, b_gray[5:0]} ),
.a63        ( a63dum              ),
.c63        ( c63dum              ),
.out_p      ( b63                 ),
.out_n      ( d63                 )
);

endmodule