module or1200_ic_fsm_cm4(
		clk_i_cml_1,
		clk_i_cml_2,
		clk_i_cml_3,
		
	// Clock and reset
	clk, rst,

	// Internal i/f to top level IC
	ic_en, icqmem_cycstb_i, icqmem_ci_i,
	tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
	icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,
	burst, tag_we
);


input clk_i_cml_1;
input clk_i_cml_2;
input clk_i_cml_3;
reg  ic_en_cml_3;
reg  ic_en_cml_2;
reg  ic_en_cml_1;
reg  icqmem_ci_i_cml_1;
reg  tagcomp_miss_cml_3;
reg  tagcomp_miss_cml_2;
reg  biudata_valid_cml_3;
reg  biudata_valid_cml_2;
reg  biudata_valid_cml_1;
reg  biudata_error_cml_3;
reg  biudata_error_cml_2;
reg  biudata_error_cml_1;
reg  biu_read_cml_3;
reg [ 31 : 0 ] saved_addr_r_cml_3;
reg [ 31 : 0 ] saved_addr_r_cml_2;
reg [ 31 : 0 ] saved_addr_r_cml_1;
reg [ 1 : 0 ] state_cml_3;
reg [ 1 : 0 ] state_cml_2;
reg [ 1 : 0 ] state_cml_1;
reg [ 2 : 0 ] cnt_cml_3;
reg [ 2 : 0 ] cnt_cml_2;
reg [ 2 : 0 ] cnt_cml_1;
reg  hitmiss_eval_cml_3;
reg  hitmiss_eval_cml_2;
reg  hitmiss_eval_cml_1;
reg  load_cml_3;
reg  load_cml_2;
reg  load_cml_1;
reg  cache_inhibit_cml_3;
reg  cache_inhibit_cml_2;
reg  cache_inhibit_cml_1;



//
// I/O
//
input				clk;
input				rst;
input				ic_en;
input				icqmem_cycstb_i;
input				icqmem_ci_i;
input				tagcomp_miss;
input				biudata_valid;
input				biudata_error;
input	[31:0]			start_addr;
output	[31:0]			saved_addr;
output	[3:0]			icram_we;
output				biu_read;
output				first_hit_ack;
output				first_miss_ack;
output				first_miss_err;
output				burst;
output				tag_we;

//
// Internal wires and regs
//
reg	[31:0]			saved_addr_r;
reg	[1:0]			state;
reg	[2:0]			cnt;
reg				hitmiss_eval;
reg				load;
reg				cache_inhibit;

//
// Generate of ICRAM write enables
//

// SynEDA CoreMultiplier
// assignment(s): icram_we
// replace(s): biudata_valid, biu_read, cache_inhibit
assign icram_we = {4{biu_read_cml_3 & biudata_valid_cml_3 & !cache_inhibit_cml_3}};


// SynEDA CoreMultiplier
// assignment(s): tag_we
// replace(s): biudata_valid, biu_read, cache_inhibit
assign tag_we = biu_read_cml_3 & biudata_valid_cml_3 & !cache_inhibit_cml_3;

//
// BIU read and write
//

// SynEDA CoreMultiplier
// assignment(s): biu_read
// replace(s): tagcomp_miss, hitmiss_eval, load
assign biu_read = (hitmiss_eval_cml_2 & tagcomp_miss_cml_2) | (!hitmiss_eval_cml_2 & load_cml_2);

//assign saved_addr = hitmiss_eval ? start_addr : saved_addr_r;
assign saved_addr = saved_addr_r;

//
// Assert for cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//

// SynEDA CoreMultiplier
// assignment(s): first_hit_ack
// replace(s): icqmem_ci_i, state, hitmiss_eval, cache_inhibit
assign first_hit_ack = (state_cml_1 == `OR1200_ICFSM_CFETCH) & hitmiss_eval_cml_1 & !tagcomp_miss & !cache_inhibit_cml_1 & !icqmem_ci_i_cml_1;
assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;

//
// Assert burst when doing reload of complete cache line
//

// SynEDA CoreMultiplier
// assignment(s): burst
// replace(s): tagcomp_miss, state, cache_inhibit
assign burst = (state_cml_3 == `OR1200_ICFSM_CFETCH) & tagcomp_miss_cml_3 & !cache_inhibit_cml_3
		| (state_cml_3 == `OR1200_ICFSM_LREFILL3);

//
// Main IC FSM
//

// SynEDA CoreMultiplier
// assignment(s): saved_addr_r, state, cnt, hitmiss_eval, load, cache_inhibit
// replace(s): ic_en, tagcomp_miss, biudata_valid, biudata_error, saved_addr_r, state, cnt, hitmiss_eval, cache_inhibit, load
always @(posedge clk or posedge rst) begin
	if (rst) begin
		state <= #1 `OR1200_ICFSM_IDLE;
		saved_addr_r <= #1 32'b0;
		hitmiss_eval <= #1 1'b0;
		load <= #1 1'b0;
		cnt <= #1 3'b000;
		cache_inhibit <= #1 1'b0;
	end
	else begin  cache_inhibit <= cache_inhibit_cml_3; load <= load_cml_3; hitmiss_eval <= hitmiss_eval_cml_3; cnt <= cnt_cml_3; state <= state_cml_3; saved_addr_r <= saved_addr_r_cml_3;
	case (state_cml_3)	// synopsys parallel_case
		`OR1200_ICFSM_IDLE :
			if (ic_en_cml_3 & icqmem_cycstb_i) begin		// fetch
				state <= #1 `OR1200_ICFSM_CFETCH;
				saved_addr_r <= #1 start_addr;
				hitmiss_eval <= #1 1'b1;
				load <= #1 1'b1;
				cache_inhibit <= #1 1'b0;
			end
			else begin							// idle
				hitmiss_eval <= #1 1'b0;
				load <= #1 1'b0;
				cache_inhibit <= #1 1'b0;
			end
		`OR1200_ICFSM_CFETCH: begin	// fetch
			if (icqmem_cycstb_i & icqmem_ci_i)
				cache_inhibit <= #1 1'b1;
			if (hitmiss_eval_cml_3)
				saved_addr_r[31:13] <= #1 start_addr[31:13];
			if ((!ic_en_cml_3) ||
			    (hitmiss_eval_cml_3 & !icqmem_cycstb_i) ||	// fetch aborted (usually caused by IMMU)
			    (biudata_error_cml_3) ||						// fetch terminated with an error
			    (cache_inhibit_cml_3 & biudata_valid_cml_3)) begin	// fetch from cache-inhibited page
				state <= #1 `OR1200_ICFSM_IDLE;
				hitmiss_eval <= #1 1'b0;
				load <= #1 1'b0;
				cache_inhibit <= #1 1'b0;
			end
			else if (tagcomp_miss_cml_3 & biudata_valid_cml_3) begin	// fetch missed, finish current external fetch and refill
				state <= #1 `OR1200_ICFSM_LREFILL3;
				saved_addr_r[3:2] <= #1 saved_addr_r_cml_3[3:2] + 1'd1;
				hitmiss_eval <= #1 1'b0;
				cnt <= #1 `OR1200_ICLS-2;
				cache_inhibit <= #1 1'b0;
			end
			else if (!tagcomp_miss_cml_3 & !icqmem_ci_i) begin	// fetch hit, finish immediately
				saved_addr_r <= #1 start_addr;
				cache_inhibit <= #1 1'b0;
			end
			else if (!icqmem_cycstb_i) begin	// fetch aborted (usually caused by exception)
				state <= #1 `OR1200_ICFSM_IDLE;
				hitmiss_eval <= #1 1'b0;
				load <= #1 1'b0;
				cache_inhibit <= #1 1'b0;
			end
			else						// fetch in-progress
				hitmiss_eval <= #1 1'b0;
		end
		`OR1200_ICFSM_LREFILL3 : begin
			if (biudata_valid_cml_3 && (|cnt_cml_3)) begin		// refill ack, more fetchs to come
				cnt <= #1 cnt_cml_3 - 3'd1;
				saved_addr_r[3:2] <= #1 saved_addr_r_cml_3[3:2] + 1'd1;
			end
			else if (biudata_valid_cml_3) begin			// last fetch of line refill
				state <= #1 `OR1200_ICFSM_IDLE;
				saved_addr_r <= #1 start_addr;
				hitmiss_eval <= #1 1'b0;
				load <= #1 1'b0;
			end
		end
		default:
			state <= #1 `OR1200_ICFSM_IDLE;
	endcase end
end


always @ (posedge clk_i_cml_1) begin
ic_en_cml_1 <= ic_en;
icqmem_ci_i_cml_1 <= icqmem_ci_i;
biudata_valid_cml_1 <= biudata_valid;
biudata_error_cml_1 <= biudata_error;
saved_addr_r_cml_1 <= saved_addr_r;
state_cml_1 <= state;
cnt_cml_1 <= cnt;
hitmiss_eval_cml_1 <= hitmiss_eval;
load_cml_1 <= load;
cache_inhibit_cml_1 <= cache_inhibit;
end
always @ (posedge clk_i_cml_2) begin
ic_en_cml_2 <= ic_en_cml_1;
tagcomp_miss_cml_2 <= tagcomp_miss;
biudata_valid_cml_2 <= biudata_valid_cml_1;
biudata_error_cml_2 <= biudata_error_cml_1;
saved_addr_r_cml_2 <= saved_addr_r_cml_1;
state_cml_2 <= state_cml_1;
cnt_cml_2 <= cnt_cml_1;
hitmiss_eval_cml_2 <= hitmiss_eval_cml_1;
load_cml_2 <= load_cml_1;
cache_inhibit_cml_2 <= cache_inhibit_cml_1;
end
always @ (posedge clk_i_cml_3) begin
ic_en_cml_3 <= ic_en_cml_2;
tagcomp_miss_cml_3 <= tagcomp_miss_cml_2;
biudata_valid_cml_3 <= biudata_valid_cml_2;
biudata_error_cml_3 <= biudata_error_cml_2;
biu_read_cml_3 <= biu_read;
saved_addr_r_cml_3 <= saved_addr_r_cml_2;
state_cml_3 <= state_cml_2;
cnt_cml_3 <= cnt_cml_2;
hitmiss_eval_cml_3 <= hitmiss_eval_cml_2;
load_cml_3 <= load_cml_2;
cache_inhibit_cml_3 <= cache_inhibit_cml_2;
end
endmodule