dakies/OSS_Verilog huggingface dataset:
module ghrd_10as066n2_button_pio (
		input  wire        clk,        //                 clk.clk
		input  wire [3:0]  in_port,    // external_connection.export
		output wire        irq,        //                 irq.irq
		input  wire        reset_n,    //               reset.reset_n
		input  wire [1:0]  address,    //                  s1.address
		input  wire        write_n,    //                    .write_n
		input  wire [31:0] writedata,  //                    .writedata
		input  wire        chipselect, //                    .chipselect
		output wire [31:0] readdata    //                    .readdata
	);

	ghrd_10as066n2_button_pio_altera_avalon_pio_171_3t26uui button_pio (
		.clk        (clk),        //   input,   width = 1,                 clk.clk
		.reset_n    (reset_n),    //   input,   width = 1,               reset.reset_n
		.address    (address),    //   input,   width = 2,                  s1.address
		.write_n    (write_n),    //   input,   width = 1,                    .write_n
		.writedata  (writedata),  //   input,  width = 32,                    .writedata
		.chipselect (chipselect), //   input,   width = 1,                    .chipselect
		.readdata   (readdata),   //  output,  width = 32,                    .readdata
		.in_port    (in_port),    //   input,   width = 4, external_connection.export
		.irq        (irq)         //  output,   width = 1,                 irq.irq
	);

endmodule
module ghrd_10as066n2_f2sdram2_m (
		input  wire        clk_clk,              //          clk.clk
		input  wire        clk_reset_reset,      //    clk_reset.reset
		output wire [31:0] master_address,       //       master.address
		input  wire [31:0] master_readdata,      //             .readdata
		output wire        master_read,          //             .read
		output wire        master_write,         //             .write
		output wire [31:0] master_writedata,     //             .writedata
		input  wire        master_waitrequest,   //             .waitrequest
		input  wire        master_readdatavalid, //             .readdatavalid
		output wire [3:0]  master_byteenable,    //             .byteenable
		output wire        master_reset_reset    // master_reset.reset
	);

	ghrd_10as066n2_f2sdram2_m_altera_jtag_avalon_master_171_wqhllki #(
		.USE_PLI     (0),
		.PLI_PORT    (50000),
		.FIFO_DEPTHS (2)
	) f2sdram2_m (
		.clk_clk              (clk_clk),              //   input,   width = 1,          clk.clk
		.clk_reset_reset      (clk_reset_reset),      //   input,   width = 1,    clk_reset.reset
		.master_address       (master_address),       //  output,  width = 32,       master.address
		.master_readdata      (master_readdata),      //   input,  width = 32,             .readdata
		.master_read          (master_read),          //  output,   width = 1,             .read
		.master_write         (master_write),         //  output,   width = 1,             .write
		.master_writedata     (master_writedata),     //  output,  width = 32,             .writedata
		.master_waitrequest   (master_waitrequest),   //   input,   width = 1,             .waitrequest
		.master_readdatavalid (master_readdatavalid), //   input,   width = 1,             .readdatavalid
		.master_byteenable    (master_byteenable),    //  output,   width = 4,             .byteenable
		.master_reset_reset   (master_reset_reset)    //  output,   width = 1, master_reset.reset
	);

endmodule
module ghrd_10as066n2_sys_id (
		input  wire        clock,    //           clk.clk
		output wire [31:0] readdata, // control_slave.readdata
		input  wire        address,  //              .address
		input  wire        reset_n   //         reset.reset_n
	);

	altera_avalon_sysid_qsys #(
		.ID_VALUE  (-1073195008),
		.TIMESTAMP (1509046992)
	) sys_id (
		.clock    (clock),    //   input,   width = 1,           clk.clk
		.reset_n  (reset_n),  //   input,   width = 1,         reset.reset_n
		.readdata (readdata), //  output,  width = 32, control_slave.readdata
		.address  (address)   //   input,   width = 1,              .address
	);

endmodule
module ghrd_10as066n2_hps_m (
		input  wire        clk_clk,              //          clk.clk
		input  wire        clk_reset_reset,      //    clk_reset.reset
		output wire [31:0] master_address,       //       master.address
		input  wire [31:0] master_readdata,      //             .readdata
		output wire        master_read,          //             .read
		output wire        master_write,         //             .write
		output wire [31:0] master_writedata,     //             .writedata
		input  wire        master_waitrequest,   //             .waitrequest
		input  wire        master_readdatavalid, //             .readdatavalid
		output wire [3:0]  master_byteenable,    //             .byteenable
		output wire        master_reset_reset    // master_reset.reset
	);

	ghrd_10as066n2_hps_m_altera_jtag_avalon_master_171_wqhllki #(
		.USE_PLI     (0),
		.PLI_PORT    (50000),
		.FIFO_DEPTHS (2)
	) hps_m (
		.clk_clk              (clk_clk),              //   input,   width = 1,          clk.clk
		.clk_reset_reset      (clk_reset_reset),      //   input,   width = 1,    clk_reset.reset
		.master_address       (master_address),       //  output,  width = 32,       master.address
		.master_readdata      (master_readdata),      //   input,  width = 32,             .readdata
		.master_read          (master_read),          //  output,   width = 1,             .read
		.master_write         (master_write),         //  output,   width = 1,             .write
		.master_writedata     (master_writedata),     //  output,  width = 32,             .writedata
		.master_waitrequest   (master_waitrequest),   //   input,   width = 1,             .waitrequest
		.master_readdatavalid (master_readdatavalid), //   input,   width = 1,             .readdatavalid
		.master_byteenable    (master_byteenable),    //  output,   width = 4,             .byteenable
		.master_reset_reset   (master_reset_reset)    //  output,   width = 1, master_reset.reset
	);

endmodule
module ghrd_10as066n2_fpga_m (
		input  wire        clk_clk,              //          clk.clk
		input  wire        clk_reset_reset,      //    clk_reset.reset
		output wire [31:0] master_address,       //       master.address
		input  wire [31:0] master_readdata,      //             .readdata
		output wire        master_read,          //             .read
		output wire        master_write,         //             .write
		output wire [31:0] master_writedata,     //             .writedata
		input  wire        master_waitrequest,   //             .waitrequest
		input  wire        master_readdatavalid, //             .readdatavalid
		output wire [3:0]  master_byteenable,    //             .byteenable
		output wire        master_reset_reset    // master_reset.reset
	);

	ghrd_10as066n2_fpga_m_altera_jtag_avalon_master_171_wqhllki #(
		.USE_PLI     (0),
		.PLI_PORT    (50000),
		.FIFO_DEPTHS (2)
	) fpga_m (
		.clk_clk              (clk_clk),              //   input,   width = 1,          clk.clk
		.clk_reset_reset      (clk_reset_reset),      //   input,   width = 1,    clk_reset.reset
		.master_address       (master_address),       //  output,  width = 32,       master.address
		.master_readdata      (master_readdata),      //   input,  width = 32,             .readdata
		.master_read          (master_read),          //  output,   width = 1,             .read
		.master_write         (master_write),         //  output,   width = 1,             .write
		.master_writedata     (master_writedata),     //  output,  width = 32,             .writedata
		.master_waitrequest   (master_waitrequest),   //   input,   width = 1,             .waitrequest
		.master_readdatavalid (master_readdatavalid), //   input,   width = 1,             .readdatavalid
		.master_byteenable    (master_byteenable),    //  output,   width = 4,             .byteenable
		.master_reset_reset   (master_reset_reset)    //  output,   width = 1, master_reset.reset
	);

endmodule
module ghrd_10as066n2_ocm_0 (
		input  wire        clk,        //   clk1.clk
		input  wire        reset,      // reset1.reset
		input  wire        reset_req,  //       .reset_req
		input  wire [17:0] address,    //     s1.address
		input  wire        clken,      //       .clken
		input  wire        chipselect, //       .chipselect
		input  wire        write,      //       .write
		output wire [7:0]  readdata,   //       .readdata
		input  wire [7:0]  writedata   //       .writedata
	);

	ghrd_10as066n2_ocm_0_altera_avalon_onchip_memory2_171_ehvj5ii ocm_0 (
		.clk        (clk),        //   input,   width = 1,   clk1.clk
		.address    (address),    //   input,  width = 18,     s1.address
		.clken      (clken),      //   input,   width = 1,       .clken
		.chipselect (chipselect), //   input,   width = 1,       .chipselect
		.write      (write),      //   input,   width = 1,       .write
		.readdata   (readdata),   //  output,   width = 8,       .readdata
		.writedata  (writedata),  //   input,   width = 8,       .writedata
		.reset      (reset),      //   input,   width = 1, reset1.reset
		.reset_req  (reset_req),  //   input,   width = 1,       .reset_req
		.freeze     (1'b0)        // (terminated),                     
	);

endmodule
module ghrd_10as066n2_ocm_0_altera_avalon_onchip_memory2_171_ehvj5ii (
                                                                       // inputs:
                                                                        address,
                                                                        chipselect,
                                                                        clk,
                                                                        clken,
                                                                        freeze,
                                                                        reset,
                                                                        reset_req,
                                                                        write,
                                                                        writedata,

                                                                       // outputs:
                                                                        readdata
                                                                     )
;

  parameter INIT_FILE = "ghrd_10as066n2_ocm_0_ocm_0.hex";


  output  [  7: 0] readdata;
  input   [ 17: 0] address;
  input            chipselect;
  input            clk;
  input            clken;
  input            freeze;
  input            reset;
  input            reset_req;
  input            write;
  input   [  7: 0] writedata;


wire             clocken0;
wire    [  7: 0] readdata;
wire             wren;
  assign wren = chipselect & write & clken;
  assign clocken0 = clken & ~reset_req;
  altsyncram the_altsyncram
    (
      .address_a (address),
      .clock0 (clk),
      .clocken0 (clocken0),
      .data_a (writedata),
      .q_a (readdata),
      .wren_a (wren)
    );

  defparam the_altsyncram.byte_size = 8,
           the_altsyncram.init_file = INIT_FILE,
           the_altsyncram.lpm_type = "altsyncram",
           the_altsyncram.maximum_depth = 262144,
           the_altsyncram.numwords_a = 262144,
           the_altsyncram.operation_mode = "SINGLE_PORT",
           the_altsyncram.outdata_reg_a = "UNREGISTERED",
           the_altsyncram.ram_block_type = "AUTO",
           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
           the_altsyncram.read_during_write_mode_port_a = "DONT_CARE",
           the_altsyncram.width_a = 8,
           the_altsyncram.widthad_a = 18;

  //s1, which is an e_avalon_slave
  //s2, which is an e_avalon_slave

endmodule
module ghrd_10as066n2_rst_bdg (
		input  wire  clk,       //       clk.clk
		input  wire  in_reset,  //  in_reset.reset
		output wire  out_reset  // out_reset.reset
	);

	assign out_reset = in_reset;

endmodule
module ghrd_10as066n2_dipsw_pio (
		input  wire        clk,        //                 clk.clk
		input  wire [3:0]  in_port,    // external_connection.export
		output wire        irq,        //                 irq.irq
		input  wire        reset_n,    //               reset.reset_n
		input  wire [1:0]  address,    //                  s1.address
		input  wire        write_n,    //                    .write_n
		input  wire [31:0] writedata,  //                    .writedata
		input  wire        chipselect, //                    .chipselect
		output wire [31:0] readdata    //                    .readdata
	);

	ghrd_10as066n2_dipsw_pio_altera_avalon_pio_171_67u3hiq dipsw_pio (
		.clk        (clk),        //   input,   width = 1,                 clk.clk
		.reset_n    (reset_n),    //   input,   width = 1,               reset.reset_n
		.address    (address),    //   input,   width = 2,                  s1.address
		.write_n    (write_n),    //   input,   width = 1,                    .write_n
		.writedata  (writedata),  //   input,  width = 32,                    .writedata
		.chipselect (chipselect), //   input,   width = 1,                    .chipselect
		.readdata   (readdata),   //  output,  width = 32,                    .readdata
		.in_port    (in_port),    //   input,   width = 4, external_connection.export
		.irq        (irq)         //  output,   width = 1,                 irq.irq
	);

endmodule
module ghrd_10as066n2_ILC (
		input  wire [5:0]  avmm_addr,   // avalon_slave.address
		input  wire [31:0] avmm_wrdata, //             .writedata
		input  wire        avmm_write,  //             .write
		input  wire        avmm_read,   //             .read
		output wire [31:0] avmm_rddata, //             .readdata
		input  wire        clk,         //          clk.clk
		input  wire [1:0]  irq,         //          irq.irq
		input  wire        reset_n      //      reset_n.reset_n
	);

	interrupt_latency_counter #(
		.INTR_TYPE    (0),
		.CLOCK_RATE   (100000000),
		.IRQ_PORT_CNT (2)
	) ilc (
		.reset_n     (reset_n),     //   input,   width = 1,      reset_n.reset_n
		.clk         (clk),         //   input,   width = 1,          clk.clk
		.irq         (irq),         //   input,   width = 2,          irq.irq
		.avmm_addr   (avmm_addr),   //   input,   width = 6, avalon_slave.address
		.avmm_wrdata (avmm_wrdata), //   input,  width = 32,             .writedata
		.avmm_write  (avmm_write),  //   input,   width = 1,             .write
		.avmm_read   (avmm_read),   //   input,   width = 1,             .read
		.avmm_rddata (avmm_rddata)  //  output,  width = 32,             .readdata
	);

endmodule
module ghrd_10as066n2_f2sdram0_m (
		input  wire        clk_clk,              //          clk.clk
		input  wire        clk_reset_reset,      //    clk_reset.reset
		output wire [31:0] master_address,       //       master.address
		input  wire [31:0] master_readdata,      //             .readdata
		output wire        master_read,          //             .read
		output wire        master_write,         //             .write
		output wire [31:0] master_writedata,     //             .writedata
		input  wire        master_waitrequest,   //             .waitrequest
		input  wire        master_readdatavalid, //             .readdatavalid
		output wire [3:0]  master_byteenable,    //             .byteenable
		output wire        master_reset_reset    // master_reset.reset
	);

	ghrd_10as066n2_f2sdram0_m_altera_jtag_avalon_master_171_wqhllki #(
		.USE_PLI     (0),
		.PLI_PORT    (50000),
		.FIFO_DEPTHS (2)
	) f2sdram0_m (
		.clk_clk              (clk_clk),              //   input,   width = 1,          clk.clk
		.clk_reset_reset      (clk_reset_reset),      //   input,   width = 1,    clk_reset.reset
		.master_address       (master_address),       //  output,  width = 32,       master.address
		.master_readdata      (master_readdata),      //   input,  width = 32,             .readdata
		.master_read          (master_read),          //  output,   width = 1,             .read
		.master_write         (master_write),         //  output,   width = 1,             .write
		.master_writedata     (master_writedata),     //  output,  width = 32,             .writedata
		.master_waitrequest   (master_waitrequest),   //   input,   width = 1,             .waitrequest
		.master_readdatavalid (master_readdatavalid), //   input,   width = 1,             .readdatavalid
		.master_byteenable    (master_byteenable),    //  output,   width = 4,             .byteenable
		.master_reset_reset   (master_reset_reset)    //  output,   width = 1, master_reset.reset
	);

endmodule
module altera_up_video_ascii_rom_128 (
	// Inputs
	clk,
	clk_en,

	character,
	x_coordinate,
	y_coordinate,
	
	// Bidirectionals

	// Outputs
	character_data
);


/*****************************************************************************
 *                           Parameter Declarations                          *
 *****************************************************************************/


/*****************************************************************************
 *                             Port Declarations                             *
 *****************************************************************************/
// Inputs
input						clk;
input						clk_en;

input			[ 6: 0]	character;
input			[ 2: 0]	x_coordinate;
input			[ 2: 0]	y_coordinate;

// Bidirectionals

// Outputs
output reg				character_data;

/*****************************************************************************
 *                           Constant Declarations                           *
 *****************************************************************************/

/*****************************************************************************
 *                 Internal Wires and Registers Declarations                 *
 *****************************************************************************/
// Internal Wires
wire			[12: 0]	character_address;

// Internal Registers
reg						rom [8191:0];

// State Machine Registers

/*****************************************************************************
 *                         Finite State Machine(s)                           *
 *****************************************************************************/


/*****************************************************************************
 *                             Sequential Logic                              *
 *****************************************************************************/

initial
begin
	$readmemb("altera_up_video_ascii_rom_128.txt", rom);
end
always @ (posedge clk)
begin
	if (clk_en)
		character_data <= rom[character_address];
end

/*****************************************************************************
 *                            Combinational Logic                            *
 *****************************************************************************/

assign character_address = {character, y_coordinate, x_coordinate};

/*****************************************************************************
 *                              Internal Modules                             *
 *****************************************************************************/


endmodule
module Computer_System_SDRAM_test_component_ram_module (
                                                         // inputs:
                                                          data,
                                                          rdaddress,
                                                          rdclken,
                                                          wraddress,
                                                          wrclock,
                                                          wren,

                                                         // outputs:
                                                          q
                                                       )
;

  output  [ 15: 0] q;
  input   [ 15: 0] data;
  input   [ 24: 0] rdaddress;
  input            rdclken;
  input   [ 24: 0] wraddress;
  input            wrclock;
  input            wren;


reg     [ 15: 0] mem_array [33554431: 0];
wire    [ 15: 0] q;
reg     [ 24: 0] read_address;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  always @(rdaddress)
    begin
      read_address = rdaddress;
    end


  // Data read is asynchronous.
  assign q = mem_array[read_address];

initial
    $readmemh("Computer_System_SDRAM_test_component.dat", mem_array);
  always @(posedge wrclock)
    begin
      // Write data
      if (wren)
          mem_array[wraddress] <= data;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on
//synthesis read_comments_as_HDL on
//  always @(rdaddress)
//    begin
//      read_address = rdaddress;
//    end
//
//
//  lpm_ram_dp lpm_ram_dp_component
//    (
//      .data (data),
//      .q (q),
//      .rdaddress (read_address),
//      .rdclken (rdclken),
//      .wraddress (wraddress),
//      .wrclock (wrclock),
//      .wren (wren)
//    );
//
//  defparam lpm_ram_dp_component.lpm_file = "UNUSED",
//           lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
//           lpm_ram_dp_component.lpm_indata = "REGISTERED",
//           lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
//           lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
//           lpm_ram_dp_component.lpm_width = 16,
//           lpm_ram_dp_component.lpm_widthad = 25,
//           lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
//           lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off

endmodule
module  Computer_System_System_PLL_sys_pll(

	// interface 'refclk'
	input wire refclk,

	// interface 'reset'
	input wire rst,

	// interface 'outclk0'
	output wire outclk_0,

	// interface 'outclk1'
	output wire outclk_1,

	// interface 'locked'
	output wire locked
);

	altera_pll #(
		.fractional_vco_multiplier("false"),
		.reference_clock_frequency("50.0 MHz"),
		.operation_mode("direct"),
		.number_of_clocks(2),
		.output_clock_frequency0("100.000000 MHz"),
		.phase_shift0("0 ps"),
		.duty_cycle0(50),
		.output_clock_frequency1("100.000000 MHz"),
		.phase_shift1("-3000 ps"),
		.duty_cycle1(50),
		.output_clock_frequency2("0 MHz"),
		.phase_shift2("0 ps"),
		.duty_cycle2(50),
		.output_clock_frequency3("0 MHz"),
		.phase_shift3("0 ps"),
		.duty_cycle3(50),
		.output_clock_frequency4("0 MHz"),
		.phase_shift4("0 ps"),
		.duty_cycle4(50),
		.output_clock_frequency5("0 MHz"),
		.phase_shift5("0 ps"),
		.duty_cycle5(50),
		.output_clock_frequency6("0 MHz"),
		.phase_shift6("0 ps"),
		.duty_cycle6(50),
		.output_clock_frequency7("0 MHz"),
		.phase_shift7("0 ps"),
		.duty_cycle7(50),
		.output_clock_frequency8("0 MHz"),
		.phase_shift8("0 ps"),
		.duty_cycle8(50),
		.output_clock_frequency9("0 MHz"),
		.phase_shift9("0 ps"),
		.duty_cycle9(50),
		.output_clock_frequency10("0 MHz"),
		.phase_shift10("0 ps"),
		.duty_cycle10(50),
		.output_clock_frequency11("0 MHz"),
		.phase_shift11("0 ps"),
		.duty_cycle11(50),
		.output_clock_frequency12("0 MHz"),
		.phase_shift12("0 ps"),
		.duty_cycle12(50),
		.output_clock_frequency13("0 MHz"),
		.phase_shift13("0 ps"),
		.duty_cycle13(50),
		.output_clock_frequency14("0 MHz"),
		.phase_shift14("0 ps"),
		.duty_cycle14(50),
		.output_clock_frequency15("0 MHz"),
		.phase_shift15("0 ps"),
		.duty_cycle15(50),
		.output_clock_frequency16("0 MHz"),
		.phase_shift16("0 ps"),
		.duty_cycle16(50),
		.output_clock_frequency17("0 MHz"),
		.phase_shift17("0 ps"),
		.duty_cycle17(50),
		.pll_type("General"),
		.pll_subtype("General")
	) altera_pll_i (
		.rst	(rst),
		.outclk	({outclk_1, outclk_0}),
		.locked	(locked),
		.fboutclk	( ),
		.fbclk	(1'b0),
		.refclk	(refclk)
	);
endmodule
module altera_up_video_alpha_blender_simple (
	// Inputs
	background_data,
	foreground_data,

	// Bidirectionals

	// Outputs
	new_red,
	new_green,
	new_blue
);

/*****************************************************************************
 *                           Parameter Declarations                          *
 *****************************************************************************/


/*****************************************************************************
 *                             Port Declarations                             *
 *****************************************************************************/
// Inputs
input			[29: 0]	background_data;
input			[39: 0]	foreground_data;

// Bidirectionals

// Outputs
output		[ 9: 0]	new_red;
output		[ 9: 0]	new_green;
output		[ 9: 0]	new_blue;

/*****************************************************************************
 *                           Constant Declarations                           *
 *****************************************************************************/


/*****************************************************************************
 *                 Internal Wires and Registers Declarations                 *
 *****************************************************************************/
// Internal Wires

// Internal Registers

// State Machine Registers

/*****************************************************************************
 *                         Finite State Machine(s)                           *
 *****************************************************************************/


/*****************************************************************************
 *                             Sequential Logic                              *
 *****************************************************************************/
// Output Registers

// Internal Registers

/*****************************************************************************
 *                            Combinational Logic                            *
 *****************************************************************************/
// Output Assignments
assign new_red		= 
		(({10{foreground_data[39]}} & foreground_data[29:20]) |
		({10{~foreground_data[39]}} & background_data[29:20]));
assign new_green	= 
		(({10{foreground_data[39]}} & foreground_data[19:10]) |
		({10{~foreground_data[39]}} & background_data[19:10]));
assign new_blue		= 
		(({10{foreground_data[39]}} & foreground_data[ 9: 0]) |
		({10{~foreground_data[39]}} & background_data[ 9: 0]));

// Internal Assignments

/*****************************************************************************
 *                              Internal Modules                             *
 *****************************************************************************/


endmodule
module Computer_System_LEDs (
                              // inputs:
                               address,
                               chipselect,
                               clk,
                               reset_n,
                               write_n,
                               writedata,

                              // outputs:
                               out_port,
                               readdata
                            )
;

  output  [  9: 0] out_port;
  output  [ 31: 0] readdata;
  input   [  1: 0] address;
  input            chipselect;
  input            clk;
  input            reset_n;
  input            write_n;
  input   [ 31: 0] writedata;


wire             clk_en;
reg     [  9: 0] data_out;
wire    [  9: 0] out_port;
wire    [  9: 0] read_mux_out;
wire    [ 31: 0] readdata;
  assign clk_en = 1;
  //s1, which is an e_avalon_slave
  assign read_mux_out = {10 {(address == 0)}} & data_out;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_out <= 0;
      else if (chipselect && ~write_n && (address == 0))
          data_out <= writedata[9 : 0];
    end


  assign readdata = {32'b0 | read_mux_out};
  assign out_port = data_out;

endmodule
module Computer_System_Video_In_Subsystem_Edge_Detection_Subsystem_Edge_Detection_Router_Controller (
                                                                                                      // inputs:
                                                                                                       address,
                                                                                                       chipselect,
                                                                                                       clk,
                                                                                                       reset_n,
                                                                                                       write_n,
                                                                                                       writedata,

                                                                                                      // outputs:
                                                                                                       out_port,
                                                                                                       readdata
                                                                                                    )
;

  output           out_port;
  output  [ 31: 0] readdata;
  input   [  1: 0] address;
  input            chipselect;
  input            clk;
  input            reset_n;
  input            write_n;
  input   [ 31: 0] writedata;


wire             clk_en;
reg              data_out;
wire             out_port;
wire             read_mux_out;
wire    [ 31: 0] readdata;
  assign clk_en = 1;
  //s1, which is an e_avalon_slave
  assign read_mux_out = {1 {(address == 0)}} & data_out;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_out <= 0;
      else if (chipselect && ~write_n && (address == 0))
          data_out <= writedata;
    end


  assign readdata = {32'b0 | read_mux_out};
  assign out_port = data_out;

endmodule
module  Computer_System_VGA_Subsystem_VGA_PLL_video_pll(

	// interface 'refclk'
	input wire refclk,

	// interface 'reset'
	input wire rst,

	// interface 'outclk0'
	output wire outclk_0,

	// interface 'outclk1'
	output wire outclk_1,

	// interface 'outclk2'
	output wire outclk_2,

	// interface 'locked'
	output wire locked
);

	altera_pll #(
		.fractional_vco_multiplier("false"),
		.reference_clock_frequency("50.0 MHz"),
		.operation_mode("direct"),
		.number_of_clocks(3),
		.output_clock_frequency0("25.000000 MHz"),
		.phase_shift0("0 ps"),
		.duty_cycle0(50),
		.output_clock_frequency1("25.000000 MHz"),
		.phase_shift1("0 ps"),
		.duty_cycle1(50),
		.output_clock_frequency2("33.000000 MHz"),
		.phase_shift2("0 ps"),
		.duty_cycle2(50),
		.output_clock_frequency3("0 MHz"),
		.phase_shift3("0 ps"),
		.duty_cycle3(50),
		.output_clock_frequency4("0 MHz"),
		.phase_shift4("0 ps"),
		.duty_cycle4(50),
		.output_clock_frequency5("0 MHz"),
		.phase_shift5("0 ps"),
		.duty_cycle5(50),
		.output_clock_frequency6("0 MHz"),
		.phase_shift6("0 ps"),
		.duty_cycle6(50),
		.output_clock_frequency7("0 MHz"),
		.phase_shift7("0 ps"),
		.duty_cycle7(50),
		.output_clock_frequency8("0 MHz"),
		.phase_shift8("0 ps"),
		.duty_cycle8(50),
		.output_clock_frequency9("0 MHz"),
		.phase_shift9("0 ps"),
		.duty_cycle9(50),
		.output_clock_frequency10("0 MHz"),
		.phase_shift10("0 ps"),
		.duty_cycle10(50),
		.output_clock_frequency11("0 MHz"),
		.phase_shift11("0 ps"),
		.duty_cycle11(50),
		.output_clock_frequency12("0 MHz"),
		.phase_shift12("0 ps"),
		.duty_cycle12(50),
		.output_clock_frequency13("0 MHz"),
		.phase_shift13("0 ps"),
		.duty_cycle13(50),
		.output_clock_frequency14("0 MHz"),
		.phase_shift14("0 ps"),
		.duty_cycle14(50),
		.output_clock_frequency15("0 MHz"),
		.phase_shift15("0 ps"),
		.duty_cycle15(50),
		.output_clock_frequency16("0 MHz"),
		.phase_shift16("0 ps"),
		.duty_cycle16(50),
		.output_clock_frequency17("0 MHz"),
		.phase_shift17("0 ps"),
		.duty_cycle17(50),
		.pll_type("General"),
		.pll_subtype("General")
	) altera_pll_i (
		.rst	(rst),
		.outclk	({outclk_2, outclk_1, outclk_0}),
		.locked	(locked),
		.fboutclk	( ),
		.fbclk	(1'b0),
		.refclk	(refclk)
	);
endmodule
module Computer_System_VGA_Subsystem_VGA_PLL (
		input  wire  ref_clk_clk,        //      ref_clk.clk
		input  wire  ref_reset_reset,    //    ref_reset.reset
		output wire  vga_clk_clk,        //      vga_clk.clk
		output wire  reset_source_reset  // reset_source.reset
	);

	wire    video_pll_locked_export; // video_pll:locked -> reset_from_locked:locked

	Computer_System_VGA_Subsystem_VGA_PLL_video_pll video_pll (
		.refclk   (ref_clk_clk),             //  refclk.clk
		.rst      (ref_reset_reset),         //   reset.reset
		.outclk_0 (),                        // outclk0.clk
		.outclk_1 (vga_clk_clk),             // outclk1.clk
		.outclk_2 (),                        // outclk2.clk
		.locked   (video_pll_locked_export)  //  locked.export
	);

	altera_up_avalon_reset_from_locked_signal reset_from_locked (
		.reset  (reset_source_reset),      // reset_source.reset
		.locked (video_pll_locked_export)  //       locked.export
	);

endmodule
module Computer_System_System_PLL (
		input  wire  ref_clk_clk,        //      ref_clk.clk
		input  wire  ref_reset_reset,    //    ref_reset.reset
		output wire  sys_clk_clk,        //      sys_clk.clk
		output wire  sdram_clk_clk,      //    sdram_clk.clk
		output wire  reset_source_reset  // reset_source.reset
	);

	wire    sys_pll_locked_export; // sys_pll:locked -> reset_from_locked:locked

	Computer_System_System_PLL_sys_pll sys_pll (
		.refclk   (ref_clk_clk),           //  refclk.clk
		.rst      (ref_reset_reset),       //   reset.reset
		.outclk_0 (sys_clk_clk),           // outclk0.clk
		.outclk_1 (sdram_clk_clk),         // outclk1.clk
		.locked   (sys_pll_locked_export)  //  locked.export
	);

	altera_up_avalon_reset_from_locked_signal reset_from_locked (
		.reset  (reset_source_reset),    // reset_source.reset
		.locked (sys_pll_locked_export)  //       locked.export
	);

endmodule
module altera_up_edge_detection_pixel_info_shift_register (
	clken,
	clock,
	shiftin,
	shiftout,
	taps);

	parameter SIZE = 3628; // Shift reg size

	input	  clken;
	input	  clock;
	input	[1:0]  shiftin;
	output	[1:0]  shiftout;
	output	[1:0]  taps;

	wire [1:0] sub_wire0;
	wire [1:0] sub_wire1;
	wire [1:0] taps = sub_wire0[1:0];
	wire [1:0] shiftout = sub_wire1[1:0];

	altshift_taps	altshift_taps_component (
				.clken (clken),
				.clock (clock),
				.shiftin (shiftin),
				.taps (sub_wire0),
				.shiftout (sub_wire1));
	defparam
		altshift_taps_component.lpm_type = "altshift_taps",
		altshift_taps_component.number_of_taps = 1,
		altshift_taps_component.tap_distance = SIZE,
		altshift_taps_component.width = 2;


endmodule
module altera_up_avalon_reset_from_locked_signal (
	// Inputs
	locked,

	// Bidirectional

	// Outputs
	reset
);

/*****************************************************************************
 *                           Parameter Declarations                          *
 *****************************************************************************/


/*****************************************************************************
 *                             Port Declarations                             *
 *****************************************************************************/
// Inputs
input						locked;

// Bidirectionals

// Outputs
output					reset;

/*****************************************************************************
 *                           Constant Declarations                           *
 *****************************************************************************/


/*****************************************************************************
 *                 Internal Wires and Registers Declarations                 *
 *****************************************************************************/
// Internal Wires

// Internal Registers

// State Machine Registers

/*****************************************************************************
 *                         Finite State Machine(s)                           *
 *****************************************************************************/


/*****************************************************************************
 *                             Sequential Logic                              *
 *****************************************************************************/

// Output Registers

// Internal Registers

/*****************************************************************************
 *                            Combinational Logic                            *
 *****************************************************************************/

assign reset	= ~locked;

/*****************************************************************************
 *                              Internal Modules                             *
 *****************************************************************************/


endmodule
module altera_up_video_dual_clock_fifo (
	// Inputs
	wrclk,
	wrreq,
	data,
	
	rdclk,
	rdreq,

	// Outputs	
	wrusedw,
	wrfull,

	q,
	rdusedw,
	rdempty
);

parameter DW = 18;

input				wrclk;
input				wrreq;
input	[(DW-1):0]  data;

input	 			rdclk;
input				rdreq;

output	[6:0]		wrusedw;
output				wrfull;

output	[(DW-1):0]	q;
output	[6:0]		rdusedw;
output				rdempty;

dcfifo	dcfifo_component (
	// Inputs
	.wrclk		(wrclk),
	.wrreq		(wrreq),
	.data		(data),
				
	.rdclk		(rdclk),
	.rdreq		(rdreq),

	// Outputs
	.wrusedw	(wrusedw),
	.wrfull		(wrfull),

	.q			(q),
	.rdusedw	(rdusedw),
	.rdempty	(rdempty)
	// synopsys translate_off
	,
	.aclr		(),
	.rdfull		(),
	.wrempty	()
	// synopsys translate_on
);
defparam
	dcfifo_component.intended_device_family	= "Cyclone II",
	dcfifo_component.lpm_hint				= "MAXIMIZE_SPEED=5,",
	dcfifo_component.lpm_numwords			= 1024,
	dcfifo_component.lpm_showahead			= "ON",
	dcfifo_component.lpm_type				= "dcfifo",
	dcfifo_component.lpm_width				= DW,
	dcfifo_component.lpm_widthu				= 10,
	dcfifo_component.overflow_checking		= "ON",
	dcfifo_component.rdsync_delaypipe		= 4,
	dcfifo_component.underflow_checking		= "ON",
	dcfifo_component.use_eab				= "ON",
	dcfifo_component.wrsync_delaypipe		= 4;

endmodule
module Computer_System_Slider_Switches (
                                         // inputs:
                                          address,
                                          clk,
                                          in_port,
                                          reset_n,

                                         // outputs:
                                          readdata
                                       )
;

  output  [ 31: 0] readdata;
  input   [  1: 0] address;
  input            clk;
  input   [  9: 0] in_port;
  input            reset_n;


wire             clk_en;
wire    [  9: 0] data_in;
wire    [  9: 0] read_mux_out;
reg     [ 31: 0] readdata;
  assign clk_en = 1;
  //s1, which is an e_avalon_slave
  assign read_mux_out = {10 {(address == 0)}} & data_in;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          readdata <= 0;
      else if (clk_en)
          readdata <= {32'b0 | read_mux_out};
    end


  assign data_in = in_port;

endmodule
module altera_up_edge_detection_data_shift_register (
	clken,
	clock,
	shiftin,
	shiftout,
	taps);

	parameter DW	= 10;
	parameter SIZE	= 720;

	input	  clken;
	input	  clock;
	input	[DW:1]  shiftin;
	output	[DW:1]  shiftout;
	output	[DW:1]  taps;

	wire [DW:1] sub_wire0;
	wire [DW:1] sub_wire1;
	wire [DW:1] taps = sub_wire0[DW:1];
	wire [DW:1] shiftout = sub_wire1[DW:1];

	altshift_taps	altshift_taps_component (
				.clken (clken),
				.clock (clock),
				.shiftin (shiftin),
				.taps (sub_wire0),
				.shiftout (sub_wire1));
	defparam
		altshift_taps_component.lpm_type = "altshift_taps",
		altshift_taps_component.number_of_taps = 1,
		altshift_taps_component.tap_distance = SIZE,
		altshift_taps_component.width = DW;


endmodule
module Computer_System_SysID (
               // inputs:
                address,
                clock,
                reset_n,

               // outputs:
                readdata
             )
;

  output  [ 31: 0] readdata;
  input            address;
  input            clock;
  input            reset_n;

  wire    [ 31: 0] readdata;
  //control_slave, which is an e_avalon_slave
  assign readdata = address ? 1494562059 : 0;

endmodule
module altera_up_video_dual_clock_fifo (
	// Inputs
	wrclk,
	wrreq,
	data,
	
	rdclk,
	rdreq,

	// Outputs	
	wrusedw,
	wrfull,

	q,
	rdusedw,
	rdempty
);

parameter DW = 18;

input				wrclk;
input				wrreq;
input	[(DW-1):0]  data;

input	 			rdclk;
input				rdreq;

output	[6:0]		wrusedw;
output				wrfull;

output	[(DW-1):0]	q;
output	[6:0]		rdusedw;
output				rdempty;

dcfifo	dcfifo_component (
	// Inputs
	.wrclk		(wrclk),
	.wrreq		(wrreq),
	.data		(data),
				
	.rdclk		(rdclk),
	.rdreq		(rdreq),

	// Outputs
	.wrusedw	(wrusedw),
	.wrfull		(wrfull),

	.q			(q),
	.rdusedw	(rdusedw),
	.rdempty	(rdempty)
	// synopsys translate_off
	,
	.aclr		(),
	.rdfull		(),
	.wrempty	()
	// synopsys translate_on
);
defparam
	dcfifo_component.intended_device_family	= "Cyclone II",
	dcfifo_component.lpm_hint				= "MAXIMIZE_SPEED=5,",
	dcfifo_component.lpm_numwords			= 128,
	dcfifo_component.lpm_showahead			= "ON",
	dcfifo_component.lpm_type				= "dcfifo",
	dcfifo_component.lpm_width				= DW,
	dcfifo_component.lpm_widthu				= 7,
	dcfifo_component.overflow_checking		= "ON",
	dcfifo_component.rdsync_delaypipe		= 4,
	dcfifo_component.underflow_checking		= "ON",
	dcfifo_component.use_eab				= "ON",
	dcfifo_component.wrsync_delaypipe		= 4;

endmodule
module Computer_System_SysID (
               // inputs:
                address,
                clock,
                reset_n,

               // outputs:
                readdata
             )
;

  output  [ 31: 0] readdata;
  input            address;
  input            clock;
  input            reset_n;

  wire    [ 31: 0] readdata;
  //control_slave, which is an e_avalon_slave
  assign readdata = address ? 1493960014 : 0;

endmodule
module designware_divmod(clock, reset, dividend, divisor, quot_out, rem_out);

parameter DIVIDEND_BIT_WIDTH = 16;
parameter DIVISOR_BIT_WIDTH = 16;
parameter SIGNED = 0;		            // 0 means unsigned, 1 means two's complement signed numbers
parameter IS_DIV = 1;		            // 0 means mod, 1 means div
parameter NUM_STAGES = 2;	          // number of pipeline stages, the latency of the multiply is num_stages - 1

input clock, reset;			//note reset is active low
  input [DIVIDEND_BIT_WIDTH-1:0] dividend;
  input [DIVISOR_BIT_WIDTH-1:0] divisor;
  output [DIVIDEND_BIT_WIDTH-1:0] quot_out, rem_out;

wire divide_by_0; //left floating intentionally (assumes we don't need this signal)

//computes dividend / divisor, assumes asynchronous reset
DW_div_pipe #(
  .a_width(DIVIDEND_BIT_WIDTH),
  .b_width(DIVISOR_BIT_WIDTH),
  .tc_mode(SIGNED),
  .rem_mode(IS_DIV),
  .num_stages(NUM_STAGES),
  .stall_mode(1'b0),
  .rst_mode(1)) div_pipe_inst (
    .clk(clock),
    .rst_n(reset),
    .en(1'b1),
    .a(dividend),
    .b(divisor),
    .quotient(quot_out),
    .remainder(rem_out),
    .divide_by_0(divide_by_0)
  );

endmodule
module designware_mult (clock, reset, in0, in1, out);

parameter IN0_BIT_WIDTH = 16;
parameter IN1_BIT_WIDTH = 16;
parameter OUT_BIT_WIDTH = 16;
parameter SIGNED = 0;		//0 means unsigned, 1 means two's complement signed numbers
parameter NUM_STAGES = 2;	//number of pipeline stages, the latency of the multiply is num_stages - 1

input clock, reset;			//note reset is active low
  input [IN0_BIT_WIDTH-1:0] in0;
  input [IN1_BIT_WIDTH-1:0] in1;
  output [OUT_BIT_WIDTH-1:0] out;

//assumes asynchronous reset
DW_mult_pipe #(.a_width(IN0_BIT_WIDTH), .b_width(IN1_BIT_WIDTH), .num_stages(NUM_STAGES), .stall_mode(1'b0), .rst_mode(1)) mult_pipe_inst (.clk(clock), .rst_n(reset), .en(1'b1), .tc(SIGNED), .a(in0), .b(in1), .product(out));

endmodule
module lab3_user_logic # (
	parameter LED_WIDTH = 8
	)
	(
    input S_AXI_ACLK,
    input slv_reg_wren,
    input [2:0] axi_awaddr,
    input [31:0] S_AXI_WDATA,
    input S_AXI_ARESETN,
    output reg [LED_WIDTH-1:0] LED
    );
      
  always @( posedge S_AXI_ACLK )
  begin
    if ( S_AXI_ARESETN == 1'b0 )
        LED <= 4'b0;
    else 
      if (slv_reg_wren && (axi_awaddr == 3'h0))
          LED <= S_AXI_WDATA[LED_WIDTH-1:0];
      end
endmodule
module div_umc_notsuper (  a, x);

	input wire a;
	output wire x;

	not (x, a);

endmodule // div_umc_notsuper
module div_umc_nor (  a, b, x);

	input wire a;
	input wire b;
	output wire x;

	nor (x, a, b);

endmodule // div_umc_nor
module div_umc_dlatch (  d, en, nq, q);

	input wire d;
	input wire en;
	output wire nq;
	output wire q;

	reg dout; 
	always @(d or en) begin
		if (en == 1'b1 && (d == 1'b0 || d == 1'b1))
			dout <= d;   // Use non-blocking
	end

	assign q = dout;
	assign nq = ~dout;

	initial dout <= 1'b0;

endmodule // div_umc_dlatch
module div_umc_not (  a, x);

	input wire a;
	output wire x;

	not (x, a);

endmodule // div_umc_not
module div_umc_mux (  sel, a0, a1, x);

	input wire sel;
	input wire a0;
	input wire a1;
	output wire x;

	assign x = sel ? a1 : a0;

endmodule // div_umc_mux
module CPU (CLK, M2, TST, nRST, nIRQ, nNMI, D, A, RnW, nOE1, nOE2, OUT, AUX1, AUX2);
	input CLK;
	output M2;
	input TST;
	input nRST;
	input nIRQ;
	input nNMI;
	inout [7:0] D;
	output [15:0] A;
	output RnW;
	output nOE1;
	output nOE2;
	output [2:0] OUT;
	output AUX1;
	output AUX2;
endmodule // CPU
module PPU (CLK, nRST, nINT, nDBE, CPU_RnW, CPU_D, RS, EXT, nRD, nWR, AD, A, ALE, VIDEO);
	input CLK;
	input nRST;
	output nINT;
	inout [3:0] EXT;
	// CPU I/F
	input nDBE;
	input CPU_RnW;
	inout [7:0] CPU_D;
	input [2:0] RS;
	// VRAM I/F
	output nRD;
	output nWR;
	inout [7:0] AD;
	output [13:8] A;
	output ALE;
	output VIDEO;
endmodule // PPU
module CIC (CLK_IN, DATA_OUT, DATA_IN, SEED, LOCK_KEY, RST, CIC_RST, nHOST_RST);
	input CLK_IN;
	output DATA_OUT;
	input DATA_IN;
	input SEED;
	input LOCK_KEY;
	input RST;
	input CIC_RST;
	output nHOST_RST;
endmodule // CIC
module CartPort (SYSTEM_CLK, M2, CIC_TO_MB, CIC_TO_CART, CIC_CLK, CIC_RST, 
	CPU_D, CPU_A, CPU_RnW, nROMSEL, EXP, nIRQ, 
	PPU_D, PPU_A, PPU_nA13, VRAM_A10, VRAM_nCE, PPU_nRD, PPU_nWR);

	input SYSTEM_CLK; 		// NES Board specific ⚠️
	input M2;
	output CIC_TO_MB; 		// NES Board specific ⚠️
	input CIC_TO_CART; 		// NES Board specific ⚠️
	input CIC_CLK;			// NES Board specific ⚠️
	output CIC_RST;			// NES Board specific ⚠️

	// CPU Part
	inout [7:0] CPU_D;
	input [14:0] CPU_A; 	// not using A15
	input CPU_RnW;
	input nROMSEL;
	input [9:0] EXP;		// NES Board specific ⚠️
	output nIRQ;

	// PPU Part
	// If you've been doing NES/Famicom for a long time, you've long known that the cartridge controls the VRAM access for the PPU. For everyone else, welcome to the world of Alien.
	inout [7:0] PPU_D;
	input [13:0] PPU_A;
	input PPU_nA13;
	output VRAM_A10;
	output VRAM_nCE;
	input PPU_nRD;
	input PPU_nWR;

endmodule // CartPort
module CtrlPort (CUP, OUT0, D0, D3, D4);
	input CUP;
	input OUT0;
	inout D0;
	inout D3;
	inout D4;
endmodule // CtrlPort
module ExpPort (CIC_CLK, AUDIO_IN, AUDIO_OUT, VIDEO, nNMI, nIRQ, A15, EXP, P1_D, P2_D, nOE1, nOE2, OUT, D);
	input CIC_CLK;
	input AUDIO_IN;
	output AUDIO_OUT;
	output VIDEO;
	output nNMI;
	output nIRQ;
	input A15;
	inout [9:0] EXP;
	output [4:0] P1_D; 		// $4016
	output [4:0] P2_D;		// $4017
	input nOE1;
	input nOE2;
	input [2:0] OUT;
	inout [7:0] D;
endmodule // ExpPort
module RAM (A, D, nCS, nWE, nOE);
	input [10:0] A;
	input [7:0] D;
	input nCS;
	input nWE;
	input nOE;
endmodule // RAM
module LS368 (nG1, nG2, A, nY);
	input nG1; 			// 0: Tristates 5,6
	input nG2; 			// 0: Tristates 1,2,3,4
	input [5:0] A; 		// A1-A6 actually
	output [5:0] nY; 	// nY1-nY6 actually
endmodule // LS368
module LS139 (First_nE, First_A, First_nY, Second_nE, Second_A, Second_nY);
	input First_nE;
	input [1:0] First_A;
	output [3:0] First_nY;
	input Second_nE;
	input [1:0] Second_A;
	output [3:0] Second_nY;
endmodule // LS139
module LS373 (nOE, Q, D, LE);
	input nOE; 			// 3-state output enable input (active LOW)
	output [7:0] Q; 	// 3-state latch outputs
	input [7:0] D;		// data inputs
	input LE;			// latch enable input (active HIGH)
endmodule // LS373
module AudioMix (AUX1, AUX2, FromEXP, ToExp, AUDIO_Out);
	input AUX1;
	input AUX2;
	input FromEXP;
	output ToExp;
	output AUDIO_Out;
	// There's some kind of magic going on, we don't care.
endmodule // AudioMix
module VideoMix (FromPPU, FromEXP, VIDEO_Out);
	input FromPPU;
	input FromEXP;
	output VIDEO_Out;
	// There's some kind of magic going on, we don't care.
endmodule // VideoMix