dakies/OSS_Verilog huggingface dataset:
module or1200_gmultp2_32x32_cm3 (
		clk_i_cml_1,
		clk_i_cml_2,
		 X, Y, CLK, RST, P );


input clk_i_cml_1;
input clk_i_cml_2;
reg [ 32 - 1 : 0 ] X_cml_2;
reg [ 64 - 1 : 0 ] p0_cml_2;
reg [ 64 - 1 : 0 ] p0_cml_1;
reg [ 64 - 1 : 0 ] p1_cml_2;
reg [ 64 - 1 : 0 ] p1_cml_1;



input   [`OR1200_W-1:0]  X;
input   [`OR1200_W-1:0]  Y;
input           CLK;
input           RST;
output  [`OR1200_WW-1:0]  P;

reg     [`OR1200_WW-1:0]  p0;
reg     [`OR1200_WW-1:0]  p1;
integer 		  xi;
integer 		  yi;

//
// Conversion unsigned to signed
//

// SynEDA CoreMultiplier
// assignment(s): xi
// replace(s): X
always @(X_cml_2)
	xi <= X_cml_2;

//
// Conversion unsigned to signed
//
always @(Y)
	yi <= Y;

//
// First multiply stage
//


// SynEDA CoreMultiplier
// assignment(s): p0
// replace(s): p0
always @(posedge CLK) begin  p0 <= p0_cml_2; 
                p0 <= #1 xi * yi; end


//
// Second multiply stage
//

// SynEDA CoreMultiplier
// assignment(s): p1
// replace(s): p0, p1
always @(posedge CLK or posedge RST)
        if (RST)
                p1 <= `OR1200_WW'b0;
        else begin  p1 <= p1_cml_2;
                p1 <= #1 p0_cml_2; end


// SynEDA CoreMultiplier
// assignment(s): P
// replace(s): p1
assign P = p1_cml_2;


always @ (posedge clk_i_cml_1) begin
p0_cml_1 <= p0;
p1_cml_1 <= p1;
end
always @ (posedge clk_i_cml_2) begin
X_cml_2 <= X;
p0_cml_2 <= p0_cml_1;
p1_cml_2 <= p1_cml_1;
end
endmodule
module or1200_gmultp2_32x32_cm3 (
		clk_i_cml_1,
		clk_i_cml_2,
		 X, Y, CLK, RST, P );


input clk_i_cml_1;
input clk_i_cml_2;
reg [ 32 - 1 : 0 ] X_cml_2;
reg [ 64 - 1 : 0 ] p0_cml_2;
reg [ 64 - 1 : 0 ] p0_cml_1;
reg [ 64 - 1 : 0 ] p1_cml_2;
reg [ 64 - 1 : 0 ] p1_cml_1;



input   [`OR1200_W-1:0]  X;
input   [`OR1200_W-1:0]  Y;
input           CLK;
input           RST;
output  [`OR1200_WW-1:0]  P;

reg     [`OR1200_WW-1:0]  p0;
reg     [`OR1200_WW-1:0]  p1;
integer 		  xi;
integer 		  yi;

//
// Conversion unsigned to signed
//

// SynEDA CoreMultiplier
// assignment(s): xi
// replace(s): X
always @(X)
	xi <= X_cml_2;

//
// Conversion unsigned to signed
//
always @(Y)
	yi <= Y;

//
// First multiply stage
//


// SynEDA CoreMultiplier
// assignment(s): p0
// replace(s): p0
always @(posedge CLK) 
                p0 <= #1 xi * yi; 


//
// Second multiply stage
//

// SynEDA CoreMultiplier
// assignment(s): p1
// replace(s): p0, p1
always @(posedge CLK) 
                p1 <= #1 p0_cml_2; 


// SynEDA CoreMultiplier
// assignment(s): P
// replace(s): p1
assign P = p1_cml_2;


always @ (posedge CLK) begin
p0_cml_1 <= p0;
p1_cml_1 <= p1;
end
always @ (posedge CLK) begin
X_cml_2 <= X;
p0_cml_2 <= p0_cml_1;
p1_cml_2 <= p1_cml_1;
end
endmodule
module or1200_reg2mem_cm3(
		clk_i_cml_1,
		clk_i_cml_2,
		addr, lsu_op, regdata, memdata);


input clk_i_cml_1;
input clk_i_cml_2;
reg [ 1 : 0 ] addr_cml_2;
reg [ 4 - 1 : 0 ] lsu_op_cml_2;
reg [ 4 - 1 : 0 ] lsu_op_cml_1;
reg [ 32 - 1 : 0 ] regdata_cml_2;
reg [ 32 - 1 : 0 ] regdata_cml_1;



parameter width = `OR1200_OPERAND_WIDTH;

//
// I/O
//
input	[1:0]			addr;
input	[`OR1200_LSUOP_WIDTH-1:0]	lsu_op;
input	[width-1:0]		regdata;
output	[width-1:0]		memdata;

//
// Internal regs and wires
//
reg	[7:0]			memdata_hh;
reg	[7:0]			memdata_hl;
reg	[7:0]			memdata_lh;
reg	[7:0]			memdata_ll;

assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll};

//
// Mux to memdata[31:24]
//

// SynEDA CoreMultiplier
// assignment(s): memdata_hh
// replace(s): addr, lsu_op, regdata
always @(lsu_op_cml_2 or addr_cml_2 or regdata_cml_2) begin
	casex({lsu_op_cml_2, addr_cml_2[1:0]})	// synopsys parallel_case
		{`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata_cml_2[7:0];
		{`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata_cml_2[15:8];
		default : memdata_hh = regdata_cml_2[31:24];
	endcase
end

//
// Mux to memdata[23:16]
//

// SynEDA CoreMultiplier
// assignment(s): memdata_hl
// replace(s): addr, lsu_op, regdata
always @(lsu_op_cml_2 or addr_cml_2 or regdata_cml_2) begin
	casex({lsu_op_cml_2, addr_cml_2[1:0]})	// synopsys parallel_case
		{`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata_cml_2[23:16];
		default : memdata_hl = regdata_cml_2[7:0];
	endcase
end

//
// Mux to memdata[15:8]
//

// SynEDA CoreMultiplier
// assignment(s): memdata_lh
// replace(s): addr, lsu_op, regdata
always @(lsu_op_cml_2 or addr_cml_2 or regdata_cml_2) begin
	casex({lsu_op_cml_2, addr_cml_2[1:0]})	// synopsys parallel_case
		{`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata_cml_2[7:0];
		default : memdata_lh = regdata_cml_2[15:8];
	endcase
end

//
// Mux to memdata[7:0]
//

// SynEDA CoreMultiplier
// assignment(s): memdata_ll
// replace(s): regdata
always @(regdata_cml_2)
	memdata_ll = regdata_cml_2[7:0];


always @ (posedge clk_i_cml_1) begin
lsu_op_cml_1 <= lsu_op;
regdata_cml_1 <= regdata;
end
always @ (posedge clk_i_cml_2) begin
addr_cml_2 <= addr;
lsu_op_cml_2 <= lsu_op_cml_1;
regdata_cml_2 <= regdata_cml_1;
end
endmodule
module or1200_wbmux_cm3(
		clk_i_cml_1,
		clk_i_cml_2,
		
	// Clock and reset
	clk, rst,

	// Internal i/f
	wb_freeze, rfwb_op,
	muxin_a, muxin_b, muxin_c, muxin_d,
	muxout, muxreg, muxreg_valid
);


input clk_i_cml_1;
input clk_i_cml_2;
reg  wb_freeze_cml_2;
reg [ 3 - 1 : 0 ] rfwb_op_cml_2;
reg [ 3 - 1 : 0 ] rfwb_op_cml_1;
reg [ 32 - 1 : 0 ] muxin_d_cml_1;
reg [ 32 - 1 : 0 ] muxout_cml_2;
reg [ 32 - 1 : 0 ] muxreg_cml_2;
reg [ 32 - 1 : 0 ] muxreg_cml_1;
reg  muxreg_valid_cml_2;
reg  muxreg_valid_cml_1;



parameter width = `OR1200_OPERAND_WIDTH;

//
// I/O
//

//
// Clock and reset
//
input				clk;
input				rst;

//
// Internal i/f
//
input				wb_freeze;
input	[`OR1200_RFWBOP_WIDTH-1:0]	rfwb_op;
input	[width-1:0]		muxin_a;
input	[width-1:0]		muxin_b;
input	[width-1:0]		muxin_c;
input	[width-1:0]		muxin_d;
output	[width-1:0]		muxout;
output	[width-1:0]		muxreg;
output				muxreg_valid;

//
// Internal wires and regs
//
reg	[width-1:0]		muxout;
reg	[width-1:0]		muxreg;
reg				muxreg_valid;

//
// Registered output from the write-back multiplexer
//

// SynEDA CoreMultiplier
// assignment(s): muxreg, muxreg_valid
// replace(s): wb_freeze, muxout, muxreg, rfwb_op, muxreg_valid
always @(posedge clk or posedge rst) begin
	if (rst) begin
		muxreg <= #1 32'd0;
		muxreg_valid <= #1 1'b0;
	end
	else begin  muxreg_valid <= muxreg_valid_cml_2; muxreg <= muxreg_cml_2; if (!wb_freeze_cml_2) begin
		muxreg <= #1 muxout_cml_2;
		muxreg_valid <= #1 rfwb_op_cml_2[0];
	end end
end

//
// Write-back multiplexer
//

// SynEDA CoreMultiplier
// assignment(s): muxout
// replace(s): rfwb_op, muxin_d
always @(muxin_a or muxin_b or muxin_c or muxin_d_cml_1 or rfwb_op_cml_1) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
	case(rfwb_op_cml_1[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
`else
	case(rfwb_op_cml_1[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
`endif
		2'b00: muxout = muxin_a;
		2'b01: begin
			muxout = muxin_b;
`ifdef OR1200_VERBOSE
// synopsys translate_off
			$display("  WBMUX: muxin_b %h", muxin_b);
// synopsys translate_on
`endif
		end
		2'b10: begin
			muxout = muxin_c;
`ifdef OR1200_VERBOSE
// synopsys translate_off
			$display("  WBMUX: muxin_c %h", muxin_c);
// synopsys translate_on
`endif
		end
		2'b11: begin
			muxout = muxin_d_cml_1 + 32'h8;
`ifdef OR1200_VERBOSE
// synopsys translate_off
			$display("  WBMUX: muxin_d %h", muxin_d + 4'h8);
// synopsys translate_on
`endif
		end
	endcase
end


always @ (posedge clk_i_cml_1) begin
rfwb_op_cml_1 <= rfwb_op;
muxin_d_cml_1 <= muxin_d;
muxreg_cml_1 <= muxreg;
muxreg_valid_cml_1 <= muxreg_valid;
end
always @ (posedge clk_i_cml_2) begin
wb_freeze_cml_2 <= wb_freeze;
rfwb_op_cml_2 <= rfwb_op_cml_1;
muxout_cml_2 <= muxout;
muxreg_cml_2 <= muxreg_cml_1;
muxreg_valid_cml_2 <= muxreg_valid_cml_1;
end
endmodule
module ic_tag_blk_cm4(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [10 : 0] addra;
input [19 : 0] dina;
input clkb;
input [10 : 0] addrb;
output [19 : 0] doutb;

`ifdef BLK_MEM_GEN

// synthesis translate_off

      BLK_MEM_GEN_V3_1 #(
		.C_ADDRA_WIDTH(11),
		.C_ADDRB_WIDTH(11),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(9),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(2048),
		.C_READ_DEPTH_B(2048),
		.C_READ_WIDTH_A(20),
		.C_READ_WIDTH_B(20),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(0),
		.C_USE_BYTE_WEB(0),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(1),
		.C_WEB_WIDTH(1),
		.C_WRITE_DEPTH_A(2048),
		.C_WRITE_DEPTH_B(2048),
		.C_WRITE_MODE_A("READ_FIRST"),
		.C_WRITE_MODE_B("READ_FIRST"),
		.C_WRITE_WIDTH_A(20),
		.C_WRITE_WIDTH_B(20),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.CLKB(clkb),
		.ADDRB(addrb),
		.DOUTB(doutb),
		.RSTA(),
		.REGCEA(),
		.DOUTA(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.DINB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

`else

reg	[10:0]	addrb_reg;		// RAM address register

always @(posedge clka)
		addrb_reg <= #1 addrb;


//
// Generic RAM's registers and wires
//
reg	[19:0]	mem [(1<<11)-1:0];	// RAM content

//
// Data output drivers
//
assign doutb = mem[addrb_reg];

//
// RAM write
//
always @(posedge clka)
	if (ena && wea)
		mem[addra] <= #1 dina;

`endif

endmodule
module dtlb_mr_sub_cm4(
		clk_i_cml_1,
		clk_i_cml_2,
		clk_i_cml_3,
		cmls,
		
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clk_i_cml_1;
input clk_i_cml_2;
input clk_i_cml_3;
input [1:0] cmls;




input clka;
input ena;
input [0 : 0] wea;
input [5 : 0] addra;
input [13 : 0] dina;
input clkb;
input [5 : 0] addrb;
output [13 : 0] doutb;

wire ena_wire;
wire [0 : 0] wea_wire;
wire [5 : 0] addra_wire;
wire [13 : 0] dina_wire;
wire [5 : 0] addrb_wire;

assign ena_wire = ena;
assign wea_wire = wea;
assign addra_wire = addra;
assign dina_wire = dina;
assign addrb_wire = addrb;

dtlb_mr_blk_cm4 dtlb_mr_blki(
	.clka(clka),
	.ena(ena_wire),
	.wea(wea_wire),
	.addra({cmls, addra_wire}),
	.dina(dina_wire),
	.clkb(clkb),
	.addrb({cmls, addrb_wire}),
	.doutb(doutb));

endmodule
module ic_ram_blk_cm4(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [12 : 0] addra;
input [31 : 0] dina;
input clkb;
input [12 : 0] addrb;
output [31 : 0] doutb;

`ifdef BLK_MEM_GEN

// synthesis translate_off

      BLK_MEM_GEN_V3_1 #(
		.C_ADDRA_WIDTH(13),
		.C_ADDRB_WIDTH(13),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(9),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(8192),
		.C_READ_DEPTH_B(8192),
		.C_READ_WIDTH_A(32),
		.C_READ_WIDTH_B(32),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(0),
		.C_USE_BYTE_WEB(0),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(1),
		.C_WEB_WIDTH(1),
		.C_WRITE_DEPTH_A(8192),
		.C_WRITE_DEPTH_B(8192),
		.C_WRITE_MODE_A("READ_FIRST"),
		.C_WRITE_MODE_B("READ_FIRST"),
		.C_WRITE_WIDTH_A(32),
		.C_WRITE_WIDTH_B(32),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.CLKB(clkb),
		.ADDRB(addrb),
		.DOUTB(doutb),
		.RSTA(),
		.REGCEA(),
		.DOUTA(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.DINB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

`else

reg	[12:0]	addrb_reg;		// RAM address register

always @(posedge clka)
		addrb_reg <= #1 addrb;

//
// Generic RAM's registers and wires
//
reg	[31:0]	mem [(1<<13)-1:0];	// RAM content

//
// Data output drivers
//
assign doutb = mem[addrb_reg];

//
// RAM write
//
always @(posedge clka)
	if (ena && wea)
		mem[addra] <= #1 dina;

`endif

endmodule
module dtlb_tr_sub_cm4(
		clk_i_cml_1,
		clk_i_cml_2,
		clk_i_cml_3,
		cmls,
		
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clk_i_cml_1;
input clk_i_cml_2;
input clk_i_cml_3;
input [1:0] cmls;




input clka;
input ena;
input [0 : 0] wea;
input [5 : 0] addra;
input [23 : 0] dina;
input clkb;
input [5 : 0] addrb;
output [23 : 0] doutb;

wire ena_wire;
wire [0 : 0] wea_wire;
wire [5 : 0] addra_wire;
wire [23 : 0] dina_wire;
wire [5 : 0] addrb_wire;

assign ena_wire = ena;
assign wea_wire = wea;
assign addra_wire = addra;
assign dina_wire = dina;
assign addrb_wire = addrb;

dtlb_tr_blk_cm4 dtlb_tr_blki(
	.clka(clka),
	.ena(ena_wire),
	.wea(wea_wire),
	.addra({cmls, addra_wire}),
	.dina(dina_wire),
	.clkb(clkb),
	.addrb({cmls, addrb_wire}),
	.doutb(doutb));

endmodule
module rf_dist_cm4(
	a,
	d,
	dpra,
	clk,
	we,
	spo,
	dpo);


input [6 : 0] a;
input [31 : 0] d;
input [6 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;

// synthesis translate_off

      DIST_MEM_GEN_V4_1 #(
		.C_ADDR_WIDTH(7),
		.C_DEFAULT_DATA("0"),
		.C_DEPTH(128),
		.C_HAS_CLK(1),
		.C_HAS_D(1),
		.C_HAS_DPO(1),
		.C_HAS_DPRA(1),
		.C_HAS_I_CE(0),
		.C_HAS_QDPO(0),
		.C_HAS_QDPO_CE(0),
		.C_HAS_QDPO_CLK(0),
		.C_HAS_QDPO_RST(0),
		.C_HAS_QDPO_SRST(0),
		.C_HAS_QSPO(0),
		.C_HAS_QSPO_CE(0),
		.C_HAS_QSPO_RST(0),
		.C_HAS_QSPO_SRST(0),
		.C_HAS_SPO(1),
		.C_HAS_SPRA(0),
		.C_HAS_WE(1),
		.C_MEM_INIT_FILE("rf_dist_cm4.mif"),
		.C_MEM_TYPE(2),
		.C_PARSER_TYPE(1),
		.C_PIPELINE_STAGES(0),
		.C_QCE_JOINED(0),
		.C_QUALIFY_WE(0),
		.C_READ_MIF(1),
		.C_REG_A_D_INPUTS(0),
		.C_REG_DPRA_INPUT(0),
		.C_SYNC_ENABLE(1),
		.C_WIDTH(32))
	inst (
		.A(a),
		.D(d),
		.DPRA(dpra),
		.CLK(clk),
		.WE(we),
		.SPO(spo),
		.DPO(dpo),
		.SPRA(),
		.I_CE(),
		.QSPO_CE(),
		.QDPO_CE(),
		.QDPO_CLK(),
		.QSPO_RST(),
		.QDPO_RST(),
		.QSPO_SRST(),
		.QDPO_SRST(),
		.QSPO(),
		.QDPO());


// synthesis translate_on


endmodule
module ic_tag_sub_cm4(
		clk_i_cml_1,
		clk_i_cml_2,
		clk_i_cml_3,
		cmls,
		
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clk_i_cml_1;
input clk_i_cml_2;
input clk_i_cml_3;
input [1:0] cmls;




input clka;
input ena;
input [0 : 0] wea;
input [8 : 0] addra;
input [19 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [19 : 0] doutb;

ic_tag_blk_cm4 ic_tag_blki(
	.clka(clka),
	.ena(ena),
	.wea(wea),
	.addra({cmls, addra}),
	.dina(dina),
	.clkb(clkb),
	.addrb({cmls, addrb}),
	.doutb(doutb));

endmodule
module itlb_mr_blk_cm4(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [7 : 0] addra;
input [13 : 0] dina;
input clkb;
input [7 : 0] addrb;
output [13 : 0] doutb;

`ifdef BLK_MEM_GEN

// synthesis translate_off

      BLK_MEM_GEN_V3_1 #(
		.C_ADDRA_WIDTH(8),
		.C_ADDRB_WIDTH(8),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(9),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(256),
		.C_READ_DEPTH_B(256),
		.C_READ_WIDTH_A(14),
		.C_READ_WIDTH_B(14),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(0),
		.C_USE_BYTE_WEB(0),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(1),
		.C_WEB_WIDTH(1),
		.C_WRITE_DEPTH_A(256),
		.C_WRITE_DEPTH_B(256),
		.C_WRITE_MODE_A("READ_FIRST"),
		.C_WRITE_MODE_B("READ_FIRST"),
		.C_WRITE_WIDTH_A(14),
		.C_WRITE_WIDTH_B(14),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.CLKB(clkb),
		.ADDRB(addrb),
		.DOUTB(doutb),
		.RSTA(),
		.REGCEA(),
		.DOUTA(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.DINB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

`else

reg	[7:0]	addrb_reg;		// RAM address register

always @(posedge clka)
		addrb_reg <= #1 addrb;


//
// Generic RAM's registers and wires
//
reg	[13:0]	mem [(1<<8)-1:0];	// RAM content

//
// Data output drivers
//
assign doutb = mem[addrb_reg];

//
// RAM write
//
always @(posedge clka)
	if (ena && wea)
		mem[addra] <= #1 dina;

`endif

endmodule
module itlb_tr_sub_cm4(
		clk_i_cml_1,
		clk_i_cml_2,
		clk_i_cml_3,
		cmls,
		
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clk_i_cml_1;
input clk_i_cml_2;
input clk_i_cml_3;
input [1:0] cmls;




input clka;
input ena;
input [0 : 0] wea;
input [5 : 0] addra;
input [21 : 0] dina;
input clkb;
input [5 : 0] addrb;
output [21 : 0] doutb;

wire ena_wire;
wire [0 : 0] wea_wire;
wire [5 : 0] addra_wire;
wire [21 : 0] dina_wire;
wire [5 : 0] addrb_wire;

assign ena_wire = ena;
assign wea_wire = wea;
assign addra_wire = addra;
assign dina_wire = dina;
assign addrb_wire = addrb;

itlb_tr_blk_cm4 itlb_tr_blki(
	.clka(clka),
	.ena(ena_wire),
	.wea(wea_wire),
	.addra({cmls, addra_wire}),
	.dina(dina_wire),
	.clkb(clkb),
	.addrb({cmls, addrb_wire}),
	.doutb(doutb));

endmodule
module itlb_mr_sub_cm4(
		clk_i_cml_1,
		clk_i_cml_2,
		clk_i_cml_3,
		cmls,
		
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clk_i_cml_1;
input clk_i_cml_2;
input clk_i_cml_3;
input [1:0] cmls;




input clka;
input ena;
input [0 : 0] wea;
input [5 : 0] addra;
input [13 : 0] dina;
input clkb;
input [5 : 0] addrb;
output [13 : 0] doutb;

wire ena_wire;
wire [0 : 0] wea_wire;
wire [5 : 0] addra_wire;
wire [13 : 0] dina_wire;
wire [5 : 0] addrb_wire;

assign ena_wire = ena;
assign wea_wire = wea;
assign addra_wire = addra;
assign dina_wire = dina;
assign addrb_wire = addrb;

itlb_mr_blk_cm4 itlb_mr_blki(
	.clka(clka),
	.ena(ena_wire),
	.wea(wea_wire),
	.addra({cmls, addra_wire}),
	.dina(dina_wire),
	.clkb(clkb),
	.addrb({cmls, addrb_wire}),
	.doutb(doutb));

endmodule
module ic_ram_sub_cm4(
		clk_i_cml_1,
		clk_i_cml_2,
		clk_i_cml_3,
		cmls,
		
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clk_i_cml_1;
input clk_i_cml_2;
input clk_i_cml_3;
input [1:0] cmls;





input clka;
input ena;
input [0 : 0] wea;
input [10 : 0] addra;
input [31 : 0] dina;
input clkb;
input [10 : 0] addrb;
output [31 : 0] doutb;

wire ena_wire;
wire [0 : 0] wea_wire;
wire [10 : 0] addra_wire;
wire [31 : 0] dina_wire;
wire [10 : 0] addrb_wire;

assign ena_wire = ena;
assign wea_wire = wea;
assign addra_wire = addra;
assign dina_wire = dina;
assign addrb_wire = addrb;

ic_ram_blk_cm4 ic_ram_blki(
	.clka(clka),
	.ena(ena_wire),
	.wea(wea_wire),
	.addra({cmls, addra_wire}),
	.dina(dina_wire),
	.clkb(clkb),
	.addrb({cmls, addrb_wire}),
	.doutb(doutb));

endmodule
module rf_dist_cm4(
	a,
	d,
	dpra,
	clk,
	we,
	spo,
	dpo);


input [6 : 0] a;
input [31 : 0] d;
input [6 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;

reg	[31:0]		mem [127:0];
integer i;

initial begin
	for (i = 0; i < 128; i = i + 1) begin
		mem[i] <= 32'h0;
	end
end

//
// Write port
//
always @(posedge clk)
	if (we) mem[a] <= #1 d;

//
// Read port A
//

assign spo = mem[a];
assign dpo = mem[dpra];

endmodule
module dc_tag_blk_cm4(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [10 : 0] addra;
input [19 : 0] dina;
input clkb;
input [10 : 0] addrb;
output [19 : 0] doutb;

`ifdef BLK_MEM_GEN

// synthesis translate_off

      BLK_MEM_GEN_V3_1 #(
		.C_ADDRA_WIDTH(11),
		.C_ADDRB_WIDTH(11),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(9),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(2048),
		.C_READ_DEPTH_B(2048),
		.C_READ_WIDTH_A(20),
		.C_READ_WIDTH_B(20),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(0),
		.C_USE_BYTE_WEB(0),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(1),
		.C_WEB_WIDTH(1),
		.C_WRITE_DEPTH_A(2048),
		.C_WRITE_DEPTH_B(2048),
		.C_WRITE_MODE_A("READ_FIRST"),
		.C_WRITE_MODE_B("READ_FIRST"),
		.C_WRITE_WIDTH_A(20),
		.C_WRITE_WIDTH_B(20),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.CLKB(clkb),
		.ADDRB(addrb),
		.DOUTB(doutb),
		.RSTA(),
		.REGCEA(),
		.DOUTA(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.DINB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

`else

reg	[10:0]	addrb_reg;		// RAM address register

always @(posedge clka)
		addrb_reg <= #1 addrb;

//
// Generic RAM's registers and wires
//
reg	[19:0]	mem [(1<<11)-1:0];	// RAM content

//
// Data output drivers
//
assign doutb = mem[addrb_reg];

//
// RAM write
//
always @(posedge clka)
	if (ena && wea)
		mem[addra] <= #1 dina;

`endif

endmodule
module dc_tag_sub_cm4(
		clk_i_cml_1,
		clk_i_cml_2,
		clk_i_cml_3,
		cmls,
		
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clk_i_cml_1;
input clk_i_cml_2;
input clk_i_cml_3;
input [1:0] cmls;

reg [ 8 : 0 ] addra_cml_3;
reg [ 8 : 0 ] addrb_cml_3;



input clka;
input ena;
input [0 : 0] wea;
input [8 : 0] addra;
input [19 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [19 : 0] doutb;

dc_tag_blk_cm4 dc_tag_blki(
	.clka(clka),
	.ena(ena),
	.wea(wea),
	.addra({cmls, addra_cml_3}),
	.dina(dina),
	.clkb(clk),
	.addrb({cmls, addrb_cml_3}),
	.doutb(doutb));

always @ (posedge clk_i_cml_3) begin
addra_cml_3 <= addra;
addrb_cml_3 <= addrb;
end

endmodule
module dc_ram_blk_cm4(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [3 : 0] wea;
input [12 : 0] addra;
input [31 : 0] dina;
input clkb;
input [12 : 0] addrb;
output [31 : 0] doutb;

`ifdef BLK_MEM_GEN

// synthesis translate_off

      BLK_MEM_GEN_V3_1 #(
		.C_ADDRA_WIDTH(13),
		.C_ADDRB_WIDTH(13),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(8),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(1),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(8192),
		.C_READ_DEPTH_B(8192),
		.C_READ_WIDTH_A(32),
		.C_READ_WIDTH_B(32),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(1),
		.C_USE_BYTE_WEB(1),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(4),
		.C_WEB_WIDTH(4),
		.C_WRITE_DEPTH_A(8192),
		.C_WRITE_DEPTH_B(8192),
		.C_WRITE_MODE_A("READ_FIRST"),
		.C_WRITE_MODE_B("READ_FIRST"),
		.C_WRITE_WIDTH_A(32),
		.C_WRITE_WIDTH_B(32),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.CLKB(clkb),
		.ADDRB(addrb),
		.DOUTB(doutb),
		.RSTA(),
		.REGCEA(),
		.DOUTA(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.DINB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

`else

//
// Generic RAM's registers and wires
//
reg     [31:0]        mem [(1<<13)-1:0];              // RAM content

reg	[12:0]	addrb_reg;		// RAM address register


always @(posedge clkb)
	addrb_reg <= #1 addrb;
                                                                                                                                                                                                    
//
// Data output drivers
//
wire [31 : 0] doutb_int;
assign doutb_int = mem[addrb_reg];

reg [31 : 0] doutb;
always @(posedge clkb)
	doutb <= #1 doutb_int;
                                                                                                                                                                                                     
                                                                                                                                                                                                 

always @(posedge clka)
	begin
        if (ena && wea[0])
                mem[addra][7:0] <= #1 dina[7:0];
        if (ena && wea[1])
                mem[addra][15:8] <= #1 dina[15:8];
        if (ena && wea[2])
                mem[addra][23:16] <= #1 dina[23:16];
       if (ena && wea[3])
                mem[addra][31:24] <= #1 dina[31:24];
	end

`endif

endmodule
module dtlb_mr_blk_cm4(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [7 : 0] addra;
input [13 : 0] dina;
input clkb;
input [7 : 0] addrb;
output [13 : 0] doutb;

`ifdef BLK_MEM_GEN

// synthesis translate_off

      BLK_MEM_GEN_V3_1 #(
		.C_ADDRA_WIDTH(8),
		.C_ADDRB_WIDTH(8),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(9),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(256),
		.C_READ_DEPTH_B(256),
		.C_READ_WIDTH_A(14),
		.C_READ_WIDTH_B(14),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(0),
		.C_USE_BYTE_WEB(0),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(1),
		.C_WEB_WIDTH(1),
		.C_WRITE_DEPTH_A(256),
		.C_WRITE_DEPTH_B(256),
		.C_WRITE_MODE_A("READ_FIRST"),
		.C_WRITE_MODE_B("READ_FIRST"),
		.C_WRITE_WIDTH_A(14),
		.C_WRITE_WIDTH_B(14),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.CLKB(clkb),
		.ADDRB(addrb),
		.DOUTB(doutb),
		.RSTA(),
		.REGCEA(),
		.DOUTA(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.DINB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

`else

reg	[7:0]	addrb_reg;		// RAM address register

always @(posedge clkb)
		addrb_reg <= #1 addrb;


//
// Generic RAM's registers and wires
//
reg	[13:0]	mem [(1<<8)-1:0];	// RAM content

//
// Data output drivers
//
assign doutb = mem[addrb_reg];

//
// RAM write
//
always @(posedge clka)
	if (ena && wea)
		mem[addra] <= #1 dina;

`endif

endmodule
module itlb_tr_blk_cm4(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [7 : 0] addra;
input [21 : 0] dina;
input clkb;
input [7 : 0] addrb;
output [21 : 0] doutb;

`ifdef BLK_MEM_GEN

// synthesis translate_off

      BLK_MEM_GEN_V3_1 #(
		.C_ADDRA_WIDTH(8),
		.C_ADDRB_WIDTH(8),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(9),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(256),
		.C_READ_DEPTH_B(256),
		.C_READ_WIDTH_A(22),
		.C_READ_WIDTH_B(22),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(0),
		.C_USE_BYTE_WEB(0),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(1),
		.C_WEB_WIDTH(1),
		.C_WRITE_DEPTH_A(256),
		.C_WRITE_DEPTH_B(256),
		.C_WRITE_MODE_A("READ_FIRST"),
		.C_WRITE_MODE_B("READ_FIRST"),
		.C_WRITE_WIDTH_A(22),
		.C_WRITE_WIDTH_B(22),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.CLKB(clkb),
		.ADDRB(addrb),
		.DOUTB(doutb),
		.RSTA(),
		.REGCEA(),
		.DOUTA(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.DINB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

`else

reg	[7:0]	addrb_reg;		// RAM address register

always @(posedge clka)
		addrb_reg <= #1 addrb;

//
// Generic RAM's registers and wires
//
reg	[21:0]	mem [(1<<8)-1:0];	// RAM content

//
// Data output drivers
//
assign doutb = mem[addrb_reg];

//
// RAM write
//
always @(posedge clka)
	if (ena && wea)
		mem[addra] <= #1 dina;

`endif

endmodule
module rf_sub_cm4_24(
		clk_i_cml_3,
		cmls,
		
	a,
	d,
	dpra,
	clk,
	we,
	spo,
	dpo);


input clk_i_cml_3;
input [1:0] cmls;

reg [ 4 : 0 ] a_cml_3;



input [4 : 0] a;
input [31 : 0] d;
input [4 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;

rf_dist_cm4 rf_disti(
	.a({cmls, a_cml_3}),
	.d(d),
	.dpra({cmls, dpra}),
	.clk(clk),
	.we(we),
	.spo(spo),
	.dpo(dpo));

always @ (posedge clk_i_cml_3) begin
a_cml_3 <= a;
end

endmodule
module rf_sub_cm4_22(
		clk_i_cml_3,
		cmls,
		
	a,
	d,
	dpra,
	clk,
	we,
	spo,
	dpo);


input clk_i_cml_3;
input [1:0] cmls;

reg [ 4 : 0 ] a_cml_3;



input [4 : 0] a;
input [31 : 0] d;
input [4 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;

rf_dist_cm4 rf_disti(
	.a({cmls, a_cml_3}),
	.d(d),
	.dpra({cmls, dpra}),
	.clk(clk),
	.we(we),
	.spo(spo),
	.dpo(dpo));

always @ (posedge clk_i_cml_3) begin
a_cml_3 <= a;
end

endmodule
module rf_sub_cm4(
		cmls,
		
	a,
	d,
	dpra,
	clk,
	we,
	spo,
	dpo);


input [1:0] cmls;



input [4 : 0] a;
input [31 : 0] d;
input [4 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;

rf_dist_cm4 rf_disti(
	.a({cmls, a}),
	.d(d),
	.dpra({cmls, dpra}),
	.clk(clk),
	.we(we),
	.spo(spo),
	.dpo(dpo));

endmodule
module dtlb_tr_blk_cm4(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [7 : 0] addra;
input [23 : 0] dina;
input clkb;
input [7 : 0] addrb;
output [23 : 0] doutb;

`ifdef BLK_MEM_GEN

// synthesis translate_off

      BLK_MEM_GEN_V3_1 #(
		.C_ADDRA_WIDTH(8),
		.C_ADDRB_WIDTH(8),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(9),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(256),
		.C_READ_DEPTH_B(256),
		.C_READ_WIDTH_A(24),
		.C_READ_WIDTH_B(24),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(0),
		.C_USE_BYTE_WEB(0),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(1),
		.C_WEB_WIDTH(1),
		.C_WRITE_DEPTH_A(256),
		.C_WRITE_DEPTH_B(256),
		.C_WRITE_MODE_A("READ_FIRST"),
		.C_WRITE_MODE_B("READ_FIRST"),
		.C_WRITE_WIDTH_A(24),
		.C_WRITE_WIDTH_B(24),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.CLKB(clkb),
		.ADDRB(addrb),
		.DOUTB(doutb),
		.RSTA(),
		.REGCEA(),
		.DOUTA(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.DINB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

`else

reg	[7:0]	addrb_reg;		// RAM address register

always @(posedge clkb)
		addrb_reg <= #1 addrb;


//
// Generic RAM's registers and wires
//
reg	[23:0]	mem [(1<<8)-1:0];	// RAM content

//
// Data output drivers
//
assign doutb = mem[addrb_reg];

//
// RAM write
//
always @(posedge clka)
	if (ena && wea)
		mem[addra] <= #1 dina;

`endif

endmodule
module dc_ram_sub_cm4(
		clk_i_cml_1,
		clk_i_cml_2,
		clk_i_cml_3,
		cmls,
		
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clk_i_cml_1;
input clk_i_cml_2;
input clk_i_cml_3;
input [1:0] cmls;

reg [ 10 : 0] addra_cml_3;
reg [ 10 : 0] addrb_cml_3;



input clka;
input ena;
input [3 : 0] wea;
input [10 : 0] addra;
input [31 : 0] dina;
input clkb;
input [10 : 0] addrb;
output [31 : 0] doutb;

wire ena_wire;
wire [3 : 0] wea_wire;
wire [10 : 0] addra_wire;
wire [31 : 0] dina_wire;
wire [10 : 0] addrb_wire;

assign ena_wire = ena;
assign wea_wire = wea;
assign addra_wire = addra;
assign dina_wire = dina;
assign addrb_wire = addrb;

dc_ram_blk_cm4 dc_ram_blki(
	.clka(clka),
	.ena(ena_wire),
	//.regcea(1'b1),
	.wea(wea_wire),
	.addra({cmls, addra_cml_3}),
	.dina(dina_wire),
	.clkb(clkb),
	.addrb({cmls, addrb_cml_3}),
	.doutb(doutb));


always @ (posedge clk_i_cml_3) begin
addra_cml_3 <= addra;
addrb_cml_3 <= addrb;
end

endmodule
module dtlb_mr_sub_cm2(
		clk_i_cml_1,
		cmls,
		
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clk_i_cml_1;
input cmls;




input clka;
input ena;
input [0 : 0] wea;
input [5 : 0] addra;
input [13 : 0] dina;
input clkb;
input [5 : 0] addrb;
output [13 : 0] doutb;

wire ena_wire;
wire [0 : 0] wea_wire;
wire [5 : 0] addra_wire;
wire [13 : 0] dina_wire;
wire [5 : 0] addrb_wire;

assign ena_wire = ena;
assign wea_wire = wea;
assign addra_wire = addra;
assign dina_wire = dina;
assign addrb_wire = addrb;

dtlb_mr_blk_cm2 dtlb_mr_blki(
	.clka(clka),
	.ena(ena_wire),
	.wea(wea_wire),
	.addra({cmls, addra_wire}),
	.dina(dina_wire),
	.clkb(clkb),
	.addrb({cmls, addrb_wire}),
	.doutb(doutb));

endmodule
module dtlb_tr_sub_cm2(
		clk_i_cml_1,
		cmls,
		
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clk_i_cml_1;
input cmls;




input clka;
input ena;
input [0 : 0] wea;
input [5 : 0] addra;
input [23 : 0] dina;
input clkb;
input [5 : 0] addrb;
output [23 : 0] doutb;

wire ena_wire;
wire [0 : 0] wea_wire;
wire [5 : 0] addra_wire;
wire [23 : 0] dina_wire;
wire [5 : 0] addrb_wire;

assign ena_wire = ena;
assign wea_wire = wea;
assign addra_wire = addra;
assign dina_wire = dina;
assign addrb_wire = addrb;

dtlb_tr_blk_cm2 dtlb_tr_blki(
	.clka(clka),
	.ena(ena_wire),
	.wea(wea_wire),
	.addra({cmls, addra_wire}),
	.dina(dina_wire),
	.clkb(clkb),
	.addrb({cmls, addrb_wire}),
	.doutb(doutb));

endmodule
module dc_tag_blk_cm2(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [9 : 0] addra;
input [19 : 0] dina;
input clkb;
input [9 : 0] addrb;
output [19 : 0] doutb;

`ifdef BLK_MEM_GEN

// synthesis translate_off

      BLK_MEM_GEN_V3_1 #(
		.C_ADDRA_WIDTH(10),
		.C_ADDRB_WIDTH(10),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(9),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(1024),
		.C_READ_DEPTH_B(1024),
		.C_READ_WIDTH_A(20),
		.C_READ_WIDTH_B(20),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(0),
		.C_USE_BYTE_WEB(0),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(1),
		.C_WEB_WIDTH(1),
		.C_WRITE_DEPTH_A(1024),
		.C_WRITE_DEPTH_B(1024),
		.C_WRITE_MODE_A("READ_FIRST"),
		.C_WRITE_MODE_B("READ_FIRST"),
		.C_WRITE_WIDTH_A(20),
		.C_WRITE_WIDTH_B(20),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.CLKB(clkb),
		.ADDRB(addrb),
		.DOUTB(doutb),
		.RSTA(),
		.REGCEA(),
		.DOUTA(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.DINB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

`else

reg	[9:0]	addrb_reg;		// RAM address register

always @(posedge clka)
		addrb_reg <= #1 addrb;

//
// Generic RAM's registers and wires
//
reg	[19:0]	mem [(1<<10)-1:0];	// RAM content

//
// Data output drivers
//
assign doutb = mem[addrb_reg];

//
// RAM write
//
always @(posedge clka)
	if (ena && wea)
		mem[addra] <= #1 dina;

`endif

endmodule
module ic_tag_sub_cm2(
		clk_i_cml_1,
		cmls,
		
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clk_i_cml_1;
input cmls;




input clka;
input ena;
input [0 : 0] wea;
input [8 : 0] addra;
input [19 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [19 : 0] doutb;

ic_tag_blk_cm2 ic_tag_blki(
	.clka(clka),
	.ena(ena),
	.wea(wea),
	.addra({cmls, addra}),
	.dina(dina),
	.clkb(clkb),
	.addrb({cmls, addrb}),
	.doutb(doutb));

endmodule
module itlb_tr_sub_cm2(
		clk_i_cml_1,
		cmls,
		
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clk_i_cml_1;
input cmls;




input clka;
input ena;
input [0 : 0] wea;
input [5 : 0] addra;
input [21 : 0] dina;
input clkb;
input [5 : 0] addrb;
output [21 : 0] doutb;

wire ena_wire;
wire [0 : 0] wea_wire;
wire [5 : 0] addra_wire;
wire [21 : 0] dina_wire;
wire [5 : 0] addrb_wire;

assign ena_wire = ena;
assign wea_wire = wea;
assign addra_wire = addra;
assign dina_wire = dina;
assign addrb_wire = addrb;

itlb_tr_blk_cm2 itlb_tr_blki(
	.clka(clka),
	.ena(ena_wire),
	.wea(wea_wire),
	.addra({cmls, addra_wire}),
	.dina(dina_wire),
	.clkb(clkb),
	.addrb({cmls, addrb_wire}),
	.doutb(doutb));

endmodule
module rf_dist_cm2(
	a,
	d,
	dpra,
	clk,
	we,
	spo,
	dpo);


input [5 : 0] a;
input [31 : 0] d;
input [5 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;

// synthesis translate_off

      DIST_MEM_GEN_V4_1 #(
		.C_ADDR_WIDTH(6),
		.C_DEFAULT_DATA("0"),
		.C_DEPTH(64),
		.C_HAS_CLK(1),
		.C_HAS_D(1),
		.C_HAS_DPO(1),
		.C_HAS_DPRA(1),
		.C_HAS_I_CE(0),
		.C_HAS_QDPO(0),
		.C_HAS_QDPO_CE(0),
		.C_HAS_QDPO_CLK(0),
		.C_HAS_QDPO_RST(0),
		.C_HAS_QDPO_SRST(0),
		.C_HAS_QSPO(0),
		.C_HAS_QSPO_CE(0),
		.C_HAS_QSPO_RST(0),
		.C_HAS_QSPO_SRST(0),
		.C_HAS_SPO(1),
		.C_HAS_SPRA(0),
		.C_HAS_WE(1),
		.C_MEM_INIT_FILE("rf_dist_cm2.mif"),
		.C_MEM_TYPE(2),
		.C_PARSER_TYPE(1),
		.C_PIPELINE_STAGES(0),
		.C_QCE_JOINED(0),
		.C_QUALIFY_WE(0),
		.C_READ_MIF(1),
		.C_REG_A_D_INPUTS(0),
		.C_REG_DPRA_INPUT(0),
		.C_SYNC_ENABLE(1),
		.C_WIDTH(32))
	inst (
		.A(a),
		.D(d),
		.DPRA(dpra),
		.CLK(clk),
		.WE(we),
		.SPO(spo),
		.DPO(dpo),
		.SPRA(),
		.I_CE(),
		.QSPO_CE(),
		.QDPO_CE(),
		.QDPO_CLK(),
		.QSPO_RST(),
		.QDPO_RST(),
		.QSPO_SRST(),
		.QDPO_SRST(),
		.QSPO(),
		.QDPO());


// synthesis translate_on


endmodule
module itlb_mr_sub_cm2(
		clk_i_cml_1,
		cmls,
		
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clk_i_cml_1;
input cmls;




input clka;
input ena;
input [0 : 0] wea;
input [5 : 0] addra;
input [13 : 0] dina;
input clkb;
input [5 : 0] addrb;
output [13 : 0] doutb;

wire ena_wire;
wire [0 : 0] wea_wire;
wire [5 : 0] addra_wire;
wire [13 : 0] dina_wire;
wire [5 : 0] addrb_wire;

assign ena_wire = ena;
assign wea_wire = wea;
assign addra_wire = addra;
assign dina_wire = dina;
assign addrb_wire = addrb;

itlb_mr_blk_cm2 itlb_mr_blki(
	.clka(clka),
	.ena(ena_wire),
	.wea(wea_wire),
	.addra({cmls, addra_wire}),
	.dina(dina_wire),
	.clkb(clkb),
	.addrb({cmls, addrb_wire}),
	.doutb(doutb));

endmodule
module ic_ram_sub_cm2(
		clk_i_cml_1,
		cmls,
		
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clk_i_cml_1;
input cmls;




input clka;
input ena;
input [0 : 0] wea;
input [10 : 0] addra;
input [31 : 0] dina;
input clkb;
input [10 : 0] addrb;
output [31 : 0] doutb;

wire ena_wire;
wire [0 : 0] wea_wire;
wire [10 : 0] addra_wire;
wire [31 : 0] dina_wire;
wire [10 : 0] addrb_wire;

assign ena_wire = ena;
assign wea_wire = wea;
assign addra_wire = addra;
assign dina_wire = dina;
assign addrb_wire = addrb;

ic_ram_blk_cm2 ic_ram_blki(
	.clka(clka),
	.ena(ena_wire),
	.wea(wea_wire),
	.addra({cmls, addra_wire}),
	.dina(dina_wire),
	.clkb(clkb),
	.addrb({cmls, addrb_wire}),
	.doutb(doutb));

endmodule
module rf_dist_cm2(
	a,
	d,
	dpra,
	clk,
	we,
	spo,
	dpo);


input [5 : 0] a;
input [31 : 0] d;
input [5 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;

reg	[31:0]		mem [63:0];
integer i;

initial begin
	for (i = 0; i < 64; i = i + 1) begin
		mem[i] <= 32'h0;
	end
end

//
// Write port
//
always @(posedge clk)
	if (we) mem[a] <= #1 d;

//
// Read port A
//

assign spo = mem[a];
assign dpo = mem[dpra];

endmodule
module dc_tag_sub_cm2(
		clk_i_cml_1,
		cmls,
		
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clk_i_cml_1;
input cmls;




input clka;
input ena;
input [0 : 0] wea;
input [8 : 0] addra;
input [19 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [19 : 0] doutb;

dc_tag_blk_cm2 dc_tag_blki(
	.clka(clka),
	.ena(ena),
	.wea(wea),
	.addra({cmls, addra}),
	.dina(dina),
	.clkb(clk),
	.addrb({cmls, addrb}),
	.doutb(doutb));

endmodule
module dtlb_tr_blk_cm2(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [6 : 0] addra;
input [23 : 0] dina;
input clkb;
input [6 : 0] addrb;
output [23 : 0] doutb;

`ifdef BLK_MEM_GEN

// synthesis translate_off

      BLK_MEM_GEN_V3_1 #(
		.C_ADDRA_WIDTH(7),
		.C_ADDRB_WIDTH(7),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(9),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(128),
		.C_READ_DEPTH_B(128),
		.C_READ_WIDTH_A(24),
		.C_READ_WIDTH_B(24),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(0),
		.C_USE_BYTE_WEB(0),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(1),
		.C_WEB_WIDTH(1),
		.C_WRITE_DEPTH_A(128),
		.C_WRITE_DEPTH_B(128),
		.C_WRITE_MODE_A("READ_FIRST"),
		.C_WRITE_MODE_B("READ_FIRST"),
		.C_WRITE_WIDTH_A(24),
		.C_WRITE_WIDTH_B(24),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.CLKB(clkb),
		.ADDRB(addrb),
		.DOUTB(doutb),
		.RSTA(),
		.REGCEA(),
		.DOUTA(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.DINB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

`else

reg	[6:0]	addrb_reg;		// RAM address register

always @(posedge clkb)
		addrb_reg <= #1 addrb;


//
// Generic RAM's registers and wires
//
reg	[23:0]	mem [(1<<7)-1:0];	// RAM content

//
// Data output drivers
//
assign doutb = mem[addrb_reg];

//
// RAM write
//
always @(posedge clka)
	if (ena && wea)
		mem[addra] <= #1 dina;

`endif

endmodule
module ic_tag_blk_cm2(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [9 : 0] addra;
input [19 : 0] dina;
input clkb;
input [9 : 0] addrb;
output [19 : 0] doutb;

`ifdef BLK_MEM_GEN

// synthesis translate_off

      BLK_MEM_GEN_V3_1 #(
		.C_ADDRA_WIDTH(10),
		.C_ADDRB_WIDTH(10),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(9),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(1024),
		.C_READ_DEPTH_B(1024),
		.C_READ_WIDTH_A(20),
		.C_READ_WIDTH_B(20),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(0),
		.C_USE_BYTE_WEB(0),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(1),
		.C_WEB_WIDTH(1),
		.C_WRITE_DEPTH_A(1024),
		.C_WRITE_DEPTH_B(1024),
		.C_WRITE_MODE_A("READ_FIRST"),
		.C_WRITE_MODE_B("READ_FIRST"),
		.C_WRITE_WIDTH_A(20),
		.C_WRITE_WIDTH_B(20),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.CLKB(clkb),
		.ADDRB(addrb),
		.DOUTB(doutb),
		.RSTA(),
		.REGCEA(),
		.DOUTA(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.DINB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

`else

reg	[9:0]	addrb_reg;		// RAM address register

always @(posedge clka)
		addrb_reg <= #1 addrb;


//
// Generic RAM's registers and wires
//
reg	[19:0]	mem [(1<<10)-1:0];	// RAM content

//
// Data output drivers
//
assign doutb = mem[addrb_reg];

//
// RAM write
//
always @(posedge clka)
	if (ena && wea)
		mem[addra] <= #1 dina;

`endif


endmodule