dakies/OSS_Verilog huggingface dataset:
module debug_regs (    
    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output reg wbs_ack_o,
    output reg [31:0] wbs_dat_o);

    reg [31:0] debug_reg_1;
    reg [31:0] debug_reg_2;

    // write
    always @(posedge wb_clk_i or posedge wb_rst_i) begin
        if (wb_rst_i) begin
            debug_reg_1 <=0;
            debug_reg_2 <=0;
            wbs_dat_o   <=0;
            wbs_ack_o   <=0;
        end else if (wbs_cyc_i && wbs_stb_i && wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'hC||wbs_adr_i[3:0]==4'h8))begin // write
            // write to reg1
            debug_reg_1[7:0]    <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[0])?  wbs_dat_i[7:0]   :debug_reg_1[7:0];
            debug_reg_1[15:8]   <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[1])?  wbs_dat_i[15:8]  :debug_reg_1[15:8];
            debug_reg_1[23:16]  <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[2])?  wbs_dat_i[23:16] :debug_reg_1[23:16];
            debug_reg_1[31:24]  <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[3])?  wbs_dat_i[31:24] :debug_reg_1[31:24];
            // write to reg2
            debug_reg_2[7:0]    <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[0])?  wbs_dat_i[7:0]   :debug_reg_2[7:0];
            debug_reg_2[15:8]   <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[1])?  wbs_dat_i[15:8]  :debug_reg_2[15:8];
            debug_reg_2[23:16]  <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[2])?  wbs_dat_i[23:16] :debug_reg_2[23:16];
            debug_reg_2[31:24]  <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[3])?  wbs_dat_i[31:24] :debug_reg_2[31:24];
            wbs_ack_o <= 1;
        end else if (wbs_cyc_i && wbs_stb_i && !wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'hC||wbs_adr_i[3:0]==4'h8)) begin // read 
            wbs_dat_o <= ((wbs_adr_i[3:0]==4'hC)) ? debug_reg_2 : debug_reg_1; 
            wbs_ack_o <= 1;
        end else begin 
            wbs_ack_o <= 0;
            wbs_dat_o <= 0;
        end
    end
endmodule
module simple_por(
`ifdef USE_POWER_PINS
    inout vdd3v3,
    inout vdd1v8,
    inout vss3v3,
    inout vss1v8,
`endif
    output porb_h,
    output porb_l,
    output por_l
);

    wire mid;
    reg inode;

    // This is a behavioral model!  Actual circuit is a resitor dumping
    // current (slowly) from vdd3v3 onto a capacitor, and this fed into
    // two schmitt triggers for strong hysteresis/glitch tolerance.

    initial begin
	inode <= 1'b0; 
    end 

    // Emulate current source on capacitor as a 500ns delay either up or
    // down.  Note that this is sped way up for verilog simulation;  the
    // actual circuit is set to a 15ms delay.

    `ifdef USE_POWER_PINS
        always @(posedge vdd3v3) begin
    `else
        initial begin
    `endif
	#500 inode <= 1'b1;
    end

    `ifdef USE_POWER_PINS
        always @(negedge vdd3v3) begin
        #500 inode <= 1'b0;
        end
    `endif

    // Instantiate two shmitt trigger buffers in series

    sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (
`ifdef USE_POWER_PINS
	.VPWR(vdd3v3),
	.VGND(vss3v3),
	.VPB(vdd3v3),
	.VNB(vss3v3),
`endif
	.A(inode),
	.X(mid)
    );

    sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (
`ifdef USE_POWER_PINS
	.VPWR(vdd3v3),
	.VGND(vss3v3),
	.VPB(vdd3v3),
	.VNB(vss3v3),
`endif
	.A(mid),
	.X(porb_h)
    );

    sky130_fd_sc_hvl__lsbufhv2lv_1 porb_level (
`ifdef USE_POWER_PINS
	.VPWR(vdd3v3),
	.VPB(vdd3v3),
	.LVPWR(vdd1v8),
	.VNB(vss3v3),
	.VGND(vss3v3),
`endif
	.A(porb_h),
	.X(porb_l)
    );

    // since this is behavioral anyway, but this should be
    // replaced by a proper inverter
    assign por_l = ~porb_l;
endmodule
module constant_block (one,
    zero,
    vccd,
    vssd);
 output one;
 output zero;
 input vccd;
 input vssd;

 wire one_unbuf;
 wire zero_unbuf;

 sky130_fd_sc_hd__buf_16 const_one_buf (.A(one_unbuf),
    .VGND(vssd),
    .VNB(vssd),
    .VPB(vccd),
    .VPWR(vccd),
    .X(one));
 sky130_fd_sc_hd__conb_1 const_source (.VGND(vssd),
    .VNB(vssd),
    .VPB(vccd),
    .VPWR(vccd),
    .HI(one_unbuf),
    .LO(zero_unbuf));
 sky130_fd_sc_hd__buf_16 const_zero_buf (.A(zero_unbuf),
    .VGND(vssd),
    .VNB(vssd),
    .VPB(vccd),
    .VPWR(vccd),
    .X(zero));
 sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_0 (.VGND(vssd),
    .VPWR(vccd));
 sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1 (.VGND(vssd),
    .VPWR(vccd));
 sky130_fd_sc_hd__fill_2 FILLER_0_0 (.VGND(vssd),
    .VNB(vssd),
    .VPB(vccd),
    .VPWR(vccd));
 sky130_fd_sc_hd__fill_2 FILLER_0_24 (.VGND(vssd),
    .VNB(vssd),
    .VPB(vccd),
    .VPWR(vccd));
 sky130_fd_sc_hd__fill_1 FILLER_0_27 (.VGND(vssd),
    .VNB(vssd),
    .VPB(vccd),
    .VPWR(vccd));
 sky130_fd_sc_hd__fill_4 FILLER_1_0 (.VGND(vssd),
    .VNB(vssd),
    .VPB(vccd),
    .VPWR(vccd));
 sky130_fd_sc_hd__fill_1 FILLER_1_4 (.VGND(vssd),
    .VNB(vssd),
    .VPB(vccd),
    .VPWR(vccd));
 sky130_fd_sc_hd__fill_8 FILLER_1_8 (.VGND(vssd),
    .VNB(vssd),
    .VPB(vccd),
    .VPWR(vccd));
 sky130_fd_sc_hd__fill_8 FILLER_1_16 (.VGND(vssd),
    .VNB(vssd),
    .VPB(vccd),
    .VPWR(vccd));
 sky130_fd_sc_hd__fill_4 FILLER_1_24 (.VGND(vssd),
    .VNB(vssd),
    .VPB(vccd),
    .VPWR(vccd));
 sky130_fd_sc_hd__fill_2 FILLER_2_0 (.VGND(vssd),
    .VNB(vssd),
    .VPB(vccd),
    .VPWR(vccd));
 sky130_fd_sc_hd__fill_2 FILLER_2_24 (.VGND(vssd),
    .VNB(vssd),
    .VPB(vccd),
    .VPWR(vccd));
 sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(vssd),
    .VNB(vssd),
    .VPB(vccd),
    .VPWR(vccd));
endmodule
module Sync_W2R #(

	parameter ADDR_WIDTH = 4
	
)(

// Inputs 
	input  wire 				 R_CLK,					// Read side Clock
	input  wire 				 R_rst_n,				// Active-Low reset Signal
	input  wire [ADDR_WIDTH : 0] W_ptr,					// Write Pointer that needs be synchronized
	
	
// Outputs	
	output reg [ADDR_WIDTH : 0] Rq2_wptr				// Synchronnized write pointer

);

	// Output of the 1st stage flipflop
	reg [ADDR_WIDTH : 0] Rq1_wptr;
	
	
	// Double FlipFlop synchronizer Behavior
	always @(posedge R_CLK or negedge R_rst_n)
	begin
	
		if(!R_rst_n)
		begin
		
			Rq1_wptr <= 5'b0;
			Rq2_wptr <= 5'b0;
			
		end
		
		else 
		begin
		
			Rq1_wptr <= W_ptr;
			Rq2_wptr <= Rq1_wptr;
		
		end
	end
	
endmodule
module FIFO_Write_Pointer #(

	parameter ADDR_WIDTH = 4
	
)(

	input  wire 					 W_CLK, 
	input  wire 					 W_rst_n,
	input  wire 					 W_inc,
	input  wire [ADDR_WIDTH     : 0] Wq2_rptr,						// Synchronized Read pointer  
	
	output reg 						 W_Full,
	output reg  [ADDR_WIDTH     : 0] W_ptr,							// Binary write pointer that needs to be converted to Gray one		
	output      [ADDR_WIDTH - 1 : 0] W_Addr
	
);

	reg  [ADDR_WIDTH: 0] Binary_W_ptr;								// Binary Value of the Write Pointer 
	wire [ADDR_WIDTH: 0] Gray_W_ptr , Binary_W_ptr_next;			// Gray Value of the Write Pointer
	wire 				 FULL_VALUE;
	
	always @(posedge W_CLK or negedge W_rst_n)
	begin
	
		if (!W_rst_n)
		begin
		
			W_Full       <= 1'b0;
			W_ptr 		 <= 4'b0000;
			Binary_W_ptr <= 4'b0000;
			
			
		end
		
		else
		begin
			W_Full       <= FULL_VALUE;
			W_ptr 		 <= Gray_W_ptr;
			Binary_W_ptr <= Binary_W_ptr_next;
		end
	end
	
	assign FULL_VALUE        = (Gray_W_ptr[ADDR_WIDTH]!= Wq2_rptr[ADDR_WIDTH])&&                           // MSB of Write Pointer differs from MSB of the Read Pointer
							   (Gray_W_ptr[ADDR_WIDTH-1]!= Wq2_rptr[ADDR_WIDTH - 1]) &&                    
							   (Gray_W_ptr[ADDR_WIDTH-2 : 0] == Wq2_rptr[ADDR_WIDTH - 2 : 0]);
							   
	assign W_Addr 			 = Binary_W_ptr[ADDR_WIDTH - 1 : 0];					// Binary Memory Address
	assign Binary_W_ptr_next = Binary_W_ptr + (W_inc & !W_Full);					
	assign Gray_W_ptr 	     = (Binary_W_ptr_next >> 1) ^ Binary_W_ptr_next;		// Binary to Gray Conversion
	
	
	

endmodule
module Sync_R2W #(

	parameter ADDR_WIDTH = 4
	
)(

// Inputs 
	input  wire 				 W_CLK,					// Write side Clock
	input  wire 				 W_rst_n,				// Active-Low reset Signal
	input  wire [ADDR_WIDTH : 0] R_ptr,					// Read Pointer that needs be synchronized
	
	
// Outputs	
	output reg [ADDR_WIDTH : 0] Wq2_rptr				// Synchronnized read pointer

);

	// Output of the 1st stage flipflop
	reg [ADDR_WIDTH : 0] Wq1_rptr;
	
	
	// Double FlipFlop synchronizer Behavior
	always @(posedge W_CLK or negedge W_rst_n)
	begin
	
		if(!W_rst_n)
		begin
		
			Wq1_rptr <= 5'b0;
			Wq2_rptr <= 5'b0;
			
		end
		
		else 
		begin
		
			Wq1_rptr <= R_ptr;
			Wq2_rptr <= Wq1_rptr;
		
		end
		
	end
	
endmodule
module FIFO_R_Pointer #(

	parameter ADDR_WIDTH = 4

)(

//////////////////
// 	  INPUTs 	//
//////////////////
	input  wire 		      R_CLK,
	input  wire 		      R_rst_n,
	input  wire 		      R_inc,
	input  wire [ADDR_WIDTH  : 0] Rq2_wptr,						// Synchronized Write Pointer (synchronized to Read CLK) 


//////////////////
// 	 OUTPUTs	//
//////////////////
	output reg 			 R_empty,
	output reg  [ADDR_WIDTH     : 0] R_ptr,
	output wire [ADDR_WIDTH - 1 : 0] R_Addr
	
);

//------------------------------
// Internal Registers and Wires
//------------------------------

	reg  [ADDR_WIDTH : 0] Binary_R_ptr;
	wire [ADDR_WIDTH : 0] Gray_R_ptr, Binary_R_ptr_next;
	wire 				  Empty_Value;
	
	
//---------------------------------------------------------------------------
// FIFO is Empty when the next rptr == synchronized write pointer or on reset
//---------------------------------------------------------------------------
	
	assign Empty_Value = (Gray_R_ptr == Rq2_wptr);



//---------------------------------------------------------------
// Behavioral Modelling of Read Pointer
//---------------------------------------------------------------	
	always @(posedge R_CLK or negedge R_rst_n)
	begin 
	
		if (!R_rst_n)
		begin
		
			R_empty      <= 1'b1;
			R_ptr 		 <= 4'b0000;
			Binary_R_ptr <= 4'b0000;
			
		end
		
		else
		begin
			
			R_empty 	 <= Empty_Value;
			R_ptr 		 <= Gray_R_ptr;
			Binary_R_ptr <= Binary_R_ptr_next;
	
		end
	end
	

assign R_Addr            = Binary_R_ptr[ADDR_WIDTH - 1 : 0];							// Binary Memory read address
assign Gray_R_ptr 		 = (Binary_R_ptr_next >> 1) ^ Binary_R_ptr_next;				// Converting the Read Pointer from Binary to Gray
assign Binary_R_ptr_next = Binary_R_ptr + (R_inc & ~R_empty);							// Counting the value of the binary read pointer 

endmodule
module ASYNC_FIFO_RAM #(

	parameter ADDR_WIDTH = 4,						// Address Width
	parameter DATA_WIDTH = 8						// Data Width

)(

// INPUTs
	input  wire			 W_CLK,					// Write Side Clock
	input  wire 			 W_CLK_en,				// Write Enable 
	input  wire [DATA_WIDTH - 1 : 0] W_Data,				// Data to be written into the Memory
	input  wire [ADDR_WIDTH - 1 : 0] W_Addr,				// Write Pointer Address
	input  wire [ADDR_WIDTH - 1 : 0] R_Addr,				// Read Pointer Address
	
// Outputs
	output wire [DATA_WIDTH - 1 : 0] R_Data					// Data to be read form the Memory

);


// FIFO_DEPTH is multiple of power 2
	localparam FIFO_DEPTH = 1 << ADDR_WIDTH;
 
// Memory Packed Array  
	reg [DATA_WIDTH - 1 : 0] MEM [ 0 : FIFO_DEPTH - 1];			// 2-D Memory Width * Depth
	
	
// Writing Operation
	always @(posedge W_CLK)
	begin
	
		if(W_CLK_en)
			begin
				MEM[W_Addr] <= W_Data;
			end
	end
	
// Asynchronous Read
	assign R_Data = MEM[R_Addr]; 


endmodule
module FIFO_TOP #(

	parameter ADDR_WIDTH = 4,				// Address Width
	parameter DATA_WIDTH = 8				// Data Width
)(

/////////////////
// Input Ports //
/////////////////
	input  wire 			 W_CLK,
	input  wire 			 R_CLK,
	input  wire 			 W_rst_n,
	input  wire 			 R_rst_n,
	input  wire 			 W_inc,
	input  wire 			 R_inc,
	input  wire [DATA_WIDTH - 1 : 0] W_Data,


//////////////////
// Output Ports //
//////////////////
	output wire                      Full,
	output wire                      Empty,
	output wire [DATA_WIDTH - 1 : 0] R_Data


);




//-----------------
// Internal Wires
//-----------------
	wire [ADDR_WIDTH - 1 : 0] W_Addr, R_Addr;
	wire [ADDR_WIDTH     : 0] W_ptr, R_ptr, Wq2_rptr, Rq2_wptr;




//---------------------------------------------------------------
// 		Internal Modules Connections
//---------------------------------------------------------------



///////////////////////////////
//     1. Write Pointer	     //
///////////////////////////////

FIFO_Write_Pointer #(.ADDR_WIDTH(ADDR_WIDTH)) FIFO_Write_Pointer_F1(

	.W_CLK(W_CLK), 
	.W_rst_n(W_rst_n),
	.W_inc(W_inc),
	.Wq2_rptr(Wq2_rptr),						 
	
	.W_Full(Full),
	.W_ptr(W_ptr),								
	.W_Addr(W_Addr)
	
);




///////////////////////////////
//	2. Read Pointer      //
///////////////////////////////

FIFO_R_Pointer #(.ADDR_WIDTH(ADDR_WIDTH)) FIFO_R_Pointer_F2(

	.R_CLK(R_CLK),
	.R_rst_n(R_rst_n),
	.R_inc(R_inc),
	.Rq2_wptr(Rq2_wptr),
	
	.R_empty(Empty),
	.R_ptr(R_ptr),
	.R_Addr(R_Addr)
	
);


///////////////////////////////
// 	3. FIFO Memory       //
///////////////////////////////

ASYNC_FIFO_RAM #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH) )  ASYNC_FIFO_RAM_F3(

	.W_CLK(W_CLK),					
	.W_CLK_en(W_inc & ~Full),				
	.W_Data(W_Data),				
	.W_Addr(W_Addr),				
	.R_Addr(R_Addr),				
	
	.R_Data(R_Data)					

);

//////////////////////////////////////////////////////////////
//        4. Read Pointer Synchronizer to Write Clk         //
//////////////////////////////////////////////////////////////
Sync_R2W #(.ADDR_WIDTH(ADDR_WIDTH)) Sync_R2W_F4(

	.W_CLK(W_CLK),					
	.W_rst_n(W_rst_n),				
	.R_ptr(R_ptr),					
	
	.Wq2_rptr(Wq2_rptr)				

);


//////////////////////////////////////////////////////////////
//        4. Write Pointer Synchronizer to Read Clk         //
//////////////////////////////////////////////////////////////

Sync_W2R #(.ADDR_WIDTH(ADDR_WIDTH)) Sync_W2R_F5(
 
	.R_CLK(R_CLK),					
	.R_rst_n(R_rst_n),				
	.W_ptr(W_ptr),					
	
	.Rq2_wptr(Rq2_wptr)				
	
);

endmodule
module MUX_2X1 (

	input  wire in0,
	input  wire in1,
	input  wire sel,
	output wire out
 
);

assign out = (sel==1) ? in1 : in0;

endmodule
module Sync_R2W ( W_CLK, W_rst_n, R_ptr, Wq2_rptr );
  input [4:0] R_ptr;
  output [4:0] Wq2_rptr;
  input W_CLK, W_rst_n;

  wire   [4:0] Wq1_rptr;

  DFFRQX2M \Wq2_rptr_reg[1]  ( .D(Wq1_rptr[1]), .CK(W_CLK), .RN(W_rst_n), .Q(
        Wq2_rptr[1]) );
  DFFRQX2M \Wq2_rptr_reg[0]  ( .D(Wq1_rptr[0]), .CK(W_CLK), .RN(W_rst_n), .Q(
        Wq2_rptr[0]) );
  DFFRQX2M \Wq2_rptr_reg[4]  ( .D(Wq1_rptr[4]), .CK(W_CLK), .RN(W_rst_n), .Q(
        Wq2_rptr[4]) );
  DFFRQX2M \Wq2_rptr_reg[2]  ( .D(Wq1_rptr[2]), .CK(W_CLK), .RN(W_rst_n), .Q(
        Wq2_rptr[2]) );
  DFFRQX2M \Wq2_rptr_reg[3]  ( .D(Wq1_rptr[3]), .CK(W_CLK), .RN(W_rst_n), .Q(
        Wq2_rptr[3]) );
  DFFRQX2M \Wq1_rptr_reg[4]  ( .D(R_ptr[4]), .CK(W_CLK), .RN(W_rst_n), .Q(
        Wq1_rptr[4]) );
  DFFRQX2M \Wq1_rptr_reg[3]  ( .D(R_ptr[3]), .CK(W_CLK), .RN(W_rst_n), .Q(
        Wq1_rptr[3]) );
  DFFRQX2M \Wq1_rptr_reg[2]  ( .D(R_ptr[2]), .CK(W_CLK), .RN(W_rst_n), .Q(
        Wq1_rptr[2]) );
  DFFRQX2M \Wq1_rptr_reg[1]  ( .D(R_ptr[1]), .CK(W_CLK), .RN(W_rst_n), .Q(
        Wq1_rptr[1]) );
  DFFRQX2M \Wq1_rptr_reg[0]  ( .D(R_ptr[0]), .CK(W_CLK), .RN(W_rst_n), .Q(
        Wq1_rptr[0]) );
endmodule
module Sync_W2R ( R_CLK, R_rst_n, W_ptr, Rq2_wptr );
  input [4:0] W_ptr;
  output [4:0] Rq2_wptr;
  input R_CLK, R_rst_n;

  wire   [4:0] Rq1_wptr;

  DFFRQX2M \Rq2_wptr_reg[2]  ( .D(Rq1_wptr[2]), .CK(R_CLK), .RN(R_rst_n), .Q(
        Rq2_wptr[2]) );
  DFFRQX2M \Rq2_wptr_reg[4]  ( .D(Rq1_wptr[4]), .CK(R_CLK), .RN(R_rst_n), .Q(
        Rq2_wptr[4]) );
  DFFRQX2M \Rq2_wptr_reg[3]  ( .D(Rq1_wptr[3]), .CK(R_CLK), .RN(R_rst_n), .Q(
        Rq2_wptr[3]) );
  DFFRQX2M \Rq2_wptr_reg[1]  ( .D(Rq1_wptr[1]), .CK(R_CLK), .RN(R_rst_n), .Q(
        Rq2_wptr[1]) );
  DFFRQX2M \Rq2_wptr_reg[0]  ( .D(Rq1_wptr[0]), .CK(R_CLK), .RN(R_rst_n), .Q(
        Rq2_wptr[0]) );
  DFFRQX2M \Rq1_wptr_reg[4]  ( .D(W_ptr[4]), .CK(R_CLK), .RN(R_rst_n), .Q(
        Rq1_wptr[4]) );
  DFFRQX2M \Rq1_wptr_reg[3]  ( .D(W_ptr[3]), .CK(R_CLK), .RN(R_rst_n), .Q(
        Rq1_wptr[3]) );
  DFFRQX2M \Rq1_wptr_reg[2]  ( .D(W_ptr[2]), .CK(R_CLK), .RN(R_rst_n), .Q(
        Rq1_wptr[2]) );
  DFFRQX2M \Rq1_wptr_reg[1]  ( .D(W_ptr[1]), .CK(R_CLK), .RN(R_rst_n), .Q(
        Rq1_wptr[1]) );
  DFFRQX2M \Rq1_wptr_reg[0]  ( .D(W_ptr[0]), .CK(R_CLK), .RN(R_rst_n), .Q(
        Rq1_wptr[0]) );
endmodule
module FIFO_TOP ( W_CLK, R_CLK, W_rst_n, R_rst_n, W_inc, R_inc, W_Data, Full, 
        Empty, R_Data );
  input [7:0] W_Data;
  output [7:0] R_Data;
  input W_CLK, R_CLK, W_rst_n, R_rst_n, W_inc, R_inc;
  output Full, Empty;
  wire   n14, n15, n16, n17, n18, n19, n20, n21, _0_net_, n1, n2, n6, n12, n13
;
  wire   [4:0] Wq2_rptr;
  wire   [4:0] W_ptr;
  wire   [3:0] W_Addr;
  wire   [4:0] Rq2_wptr;
  wire   [4:0] R_ptr;
  wire   [3:0] R_Addr;

  FIFO_Write_Pointer FIFO_Write_Pointer_F1 ( .W_CLK(W_CLK), .W_rst_n(W_rst_n), 
        .W_inc(W_inc), .Wq2_rptr(Wq2_rptr), .W_Full(Full), .W_ptr(W_ptr), 
        .W_Addr(W_Addr) );
  FIFO_R_Pointer FIFO_R_Pointer_F2 ( .R_CLK(R_CLK), .R_rst_n(R_rst_n), .R_inc(
        R_inc), .Rq2_wptr(Rq2_wptr), .R_empty(Empty), .R_ptr(R_ptr), .R_Addr(
        R_Addr) );
  ASYNC_FIFO_RAM ASYNC_FIFO_RAM_F3 ( .W_CLK(W_CLK), .W_CLK_en(_0_net_), 
        .W_Data(W_Data), .W_Addr(W_Addr), .R_Addr({R_Addr[3:2], n13, n12}), 
        .R_Data({n14, n15, n16, n17, n18, n19, n20, n21}) );
  Sync_R2W Sync_R2W_F4 ( .W_CLK(W_CLK), .W_rst_n(W_rst_n), .R_ptr(R_ptr), 
        .Wq2_rptr(Wq2_rptr) );
  Sync_W2R Sync_W2R_F5 ( .R_CLK(R_CLK), .R_rst_n(R_rst_n), .W_ptr(W_ptr), 
        .Rq2_wptr(Rq2_wptr) );
  CLKBUFX32M U2 ( .A(n14), .Y(R_Data[7]) );
  CLKINVX2M U3 ( .A(n17), .Y(n6) );
  CLKBUFX32M U4 ( .A(R_Addr[1]), .Y(n13) );
  CLKBUFX32M U5 ( .A(R_Addr[0]), .Y(n12) );
  CLKINVX32M U6 ( .A(n1), .Y(_0_net_) );
  NAND2X12M U7 ( .A(W_inc), .B(n2), .Y(n1) );
  CLKINVX40M U8 ( .A(Full), .Y(n2) );
  CLKBUFX32M U9 ( .A(n15), .Y(R_Data[6]) );
  CLKINVX32M U10 ( .A(n6), .Y(R_Data[4]) );
  CLKBUFX32M U11 ( .A(n21), .Y(R_Data[0]) );
  CLKBUFX32M U12 ( .A(n19), .Y(R_Data[2]) );
  CLKBUFX32M U13 ( .A(n16), .Y(R_Data[5]) );
  CLKBUFX32M U14 ( .A(n20), .Y(R_Data[1]) );
  CLKBUFX32M U15 ( .A(n18), .Y(R_Data[3]) );
endmodule
module M65C02_IntHndlr #(
    parameter pIRQ_Vector = 16'hFFFE,
    parameter pBRK_Vector = 16'hFFFE,
    parameter pRST_Vector = 16'hFFFC,
    parameter pNMI_Vector = 16'hFFFA,
    parameter pBRK        = 3'b010
)(
    input   Rst,
    input   Clk,
    
    input   nNMI,
    input   nIRQ,
    input   [2:0] Mode,
    
    input   IRQ_Msk,
    input   IntSvc,
    
    output  reg Int,
    output  reg [15:0] Vector,
    
    output  reg NMI,
    output  reg IRQ,
    output  reg Brk
);

////////////////////////////////////////////////////////////////////////////////
//
//  Local Declarations
//

wire    RE_NMI;
wire    CE_NMI;
reg     nIRQ_IFD;
     

//  Perform falling edge detection on the external non-maskable interrupt input

fedet   FE3 (
            .rst(Rst), 
            .clk(Clk), 
            .din(nNMI), 
            .pls(RE_NMI)
        );

//  Capture and hold the rising edge pulse for NMI in NMI FF until serviced by
//      the processor.

assign CE_NMI = (Rst | IntSvc | RE_NMI);
always @(posedge Clk) NMI <= #1 ((CE_NMI) ? RE_NMI : 0);

//  Synchronize external IRQ input to Clk

always @(posedge Clk or posedge Rst)
begin
    if(Rst) begin
        nIRQ_IFD <= #1 1;
        IRQ      <= #1 0;
    end else begin
        nIRQ_IFD <= #1 nIRQ;
        IRQ      <= #1 ~nIRQ_IFD;
    end
end

//assign Brk    = (Mode == pBRK);
//assign Int    = (NMI | (~IRQ_Msk & IRQ));
//
//always @(*) Vector = ((Int) ? ((NMI) ? pNMI_Vector
//                                     : pIRQ_Vector)
//                            : ((Brk) ? pBRK_Vector
//                                     : pRST_Vector));

always @(posedge Clk or posedge Rst)
begin
    if(Rst) begin
        Brk    <= #1 0;
        Int    <= #1 0;
        Vector <= #1 pRST_Vector;
    end else begin
        Brk    <= #1 (Mode == pBRK);
        Int    <= #1 (NMI | (~IRQ_Msk & IRQ));
        Vector <= #1 ((Int) ? ((NMI) ? pNMI_Vector
                                     : pIRQ_Vector)
                            : ((Brk) ? pBRK_Vector
                                     : pRST_Vector));
    end
end
                       
endmodule
module M65C02_RAM #(
    parameter pAddrSize = 10,
    parameter pDataSize = 8,
    parameter pFileName = "M65C02_RAM.txt"
)(
    input   Clk,
    
    input   ZP,                         // Emulate LUT-based Asynchronous RAM
    input   Ext,                        // Emulate BRAM-based Pipelined SyncSRAM
    
    input   WE,
    input   [(pAddrSize - 1):0] AI,
    input   [(pDataSize - 1):0] DI,
    output  [(pDataSize - 1):0] DO
);

localparam pRAM_Max = ((2**pAddrSize) - 1);

reg     [(pDataSize - 1):0] RAM [pRAM_Max:0];

reg     rWE;
reg     [(pAddrSize - 1):0] rAI;
reg     [(pDataSize - 1):0] rDI, rDO;

wire    W;
wire    [(pAddrSize - 1):0] A;
wire    [(pDataSize - 1):0] D;

always @(posedge Clk)
begin
    {rWE, rAI, rDI} <= #1 {WE, AI, DI};
end

assign W = ((ZP) ? WE : rWE);
assign A = ((ZP) ? AI : rAI);
assign D = ((ZP) ? DI : rDI);

initial
    $readmemh(pFileName, RAM, 0, pRAM_Max);

always @(posedge Clk)
begin
    if(W)
        RAM[A] <= #1 D;
end

always @(posedge Clk)
begin
    rDO <= #1 RAM[A];
end

assign DO = ((Ext) ? rDO : RAM[A]);

endmodule
module M65C02_BIN(
    input   En,                 // ALU Enable

    input   [7:0] A,            // Adder Input A
    input   [7:0] B,            // Adder Input B
    input   Ci,                 // Adder Carry In
    
    output  reg [8:0] Out,      // Adder Sum <= A + B + Ci
    output  reg OV,             // Adder Overflow
    output  reg Valid           // Adder Outputs Valid
);

///////////////////////////////////////////////////////////////////////////////
//
//  Declarations
//

reg     [7:0] S;        // Intermediate Binary Sum: S <= A + B + Ci
reg     C6, C7;         // Sum Carry Out from Bitx 

///////////////////////////////////////////////////////////////////////////////
//
//  Implementation
//

//  Adder First Stage - Combinatorial; Binary Sums and Carries

always @(*)
begin
    // Binary Addition and Generate C6 and C7 Carries
    {C6, S[6:0]} <= ({1'b0, A[6:0]} + {1'b0, B[6:0]} + {7'b0, Ci});
    {C7,   S[7]} <= ({1'b0,   A[7]} + {1'b0,   B[7]} + {1'b0, C6});
end

always @(*)
begin
    Out   <= ((En) ? {C7, S}   : 0);
    OV    <= ((En) ? (C7 ^ C6) : 0);
    Valid <= En;
end

endmodule
module fedet(rst, clk, din, pls);

///////////////////////////////////////////////////////////////////////////////
//
//  Module Port Declarations
//
    
    input   rst;
    input   clk;
    input   din;
    output  pls;

///////////////////////////////////////////////////////////////////////////////
//
//  Module Level Declarations
//

    reg [2:0] QSync;
    
///////////////////////////////////////////////////////////////////////////////
//
//  Implementation
//

always @(posedge clk or posedge rst) begin
    if(rst)
        #1 QSync <= 3'b011;
    else 
        #1 QSync <= {~QSync[0] & QSync[1], QSync[0], din};
end

assign pls = QSync[2];

endmodule
module dc_ram_blk(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [3 : 0] wea;
input [10 : 0] addra;
input [31 : 0] dina;
input clkb;
input [10 : 0] addrb;
output [31 : 0] doutb;

`ifdef BLK_MEM_GEN

// synthesis translate_off

      BLK_MEM_GEN_V3_1 #(
		.C_ADDRA_WIDTH(11),
		.C_ADDRB_WIDTH(11),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(8),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(2048),
		.C_READ_DEPTH_B(2048),
		.C_READ_WIDTH_A(32),
		.C_READ_WIDTH_B(32),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(1),
		.C_USE_BYTE_WEB(1),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(4),
		.C_WEB_WIDTH(4),
		.C_WRITE_DEPTH_A(2048),
		.C_WRITE_DEPTH_B(2048),
		.C_WRITE_MODE_A("READ_FIRST"),
		.C_WRITE_MODE_B("READ_FIRST"),
		.C_WRITE_WIDTH_A(32),
		.C_WRITE_WIDTH_B(32),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.CLKB(clkb),
		.ADDRB(addrb),
		.DOUTB(doutb),
		.RSTA(),
		.REGCEA(),
		.DOUTA(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.DINB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

`else

//
// Generic RAM's registers and wires
//
reg     [31:0]        mem [(1<<11)-1:0];              // RAM content

reg	[10:0]	addrb_reg;		// RAM address register


always @(posedge clkb)
	addrb_reg <= #1 addrb;
                                                                                                                                                                                                    
//
// Data output drivers
//
assign doutb = mem[addrb_reg];

always @(posedge clka)
	begin
        if (ena && wea[0])
                mem[addra][7:0] <= #1 dina[7:0];
        if (ena && wea[1])
                mem[addra][15:8] <= #1 dina[15:8];
        if (ena && wea[2])
                mem[addra][23:16] <= #1 dina[23:16];
       if (ena && wea[3])
                mem[addra][31:24] <= #1 dina[31:24];
	end

`endif

endmodule
module dtlb_mr_sub(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [5 : 0] addra;
input [13 : 0] dina;
input clkb;
input [5 : 0] addrb;
output [13 : 0] doutb;

wire ena_wire;
wire [0 : 0] wea_wire;
wire [5 : 0] addra_wire;
wire [13 : 0] dina_wire;
wire [5 : 0] addrb_wire;

assign ena_wire = ena;
assign wea_wire = wea;
assign addra_wire = addra;
assign dina_wire = dina;
assign addrb_wire = addrb;

dtlb_mr_blk dtlb_mr_blki(
	.clka(clka),
	.ena(ena_wire),
	.wea(wea_wire),
	.addra(addra_wire),
	.dina(dina_wire),
	.clkb(clkb),
	.addrb(addrb_wire),
	.doutb(doutb));

endmodule
module dtlb_tr_blk(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [5 : 0] addra;
input [23 : 0] dina;
input clkb;
input [5 : 0] addrb;
output [23 : 0] doutb;

`ifdef BLK_MEM_GEN

// synthesis translate_off

      BLK_MEM_GEN_V3_1 #(
		.C_ADDRA_WIDTH(6),
		.C_ADDRB_WIDTH(6),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(9),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(64),
		.C_READ_DEPTH_B(64),
		.C_READ_WIDTH_A(24),
		.C_READ_WIDTH_B(24),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(0),
		.C_USE_BYTE_WEB(0),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(1),
		.C_WEB_WIDTH(1),
		.C_WRITE_DEPTH_A(64),
		.C_WRITE_DEPTH_B(64),
		.C_WRITE_MODE_A("READ_FIRST"),
		.C_WRITE_MODE_B("READ_FIRST"),
		.C_WRITE_WIDTH_A(24),
		.C_WRITE_WIDTH_B(24),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.CLKB(clkb),
		.ADDRB(addrb),
		.DOUTB(doutb),
		.RSTA(),
		.REGCEA(),
		.DOUTA(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.DINB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

`else

reg	[5:0]	addrb_reg;		// RAM address register

always @(posedge clkb)
		addrb_reg <= #1 addrb;


//
// Generic RAM's registers and wires
//
reg	[23:0]	mem [(1<<6)-1:0];	// RAM content

//
// Data output drivers
//
assign doutb = mem[addrb_reg];

//
// RAM write
//
always @(posedge clka)
	if (ena && wea)
		mem[addra] <= #1 dina;

`endif

endmodule
module or1200_gmultp2_32x32 ( X, Y, CLK, RST, P );

input   [`OR1200_W-1:0]  X;
input   [`OR1200_W-1:0]  Y;
input           CLK;
input           RST;
output  [`OR1200_WW-1:0]  P;

reg     [`OR1200_WW-1:0]  p0;
reg     [`OR1200_WW-1:0]  p1;
integer 		  xi;
integer 		  yi;

//
// Conversion unsigned to signed
//
always @(X)
	xi <= X;

//
// Conversion unsigned to signed
//
always @(Y)
	yi <= Y;

//
// First multiply stage
//

always @(posedge CLK) 
               p0 <= #1 xi * yi;


//
// Second multiply stage
//
always @(posedge CLK or posedge RST)
        if (RST)
                p1 <= `OR1200_WW'b0;
        else
                p1 <= #1 p0;

assign P = p1;

endmodule
module ic_tag_blk(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [8 : 0] addra;
input [19 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [19 : 0] doutb;

`ifdef BLK_MEM_GEN

// synthesis translate_off

      BLK_MEM_GEN_V3_1 #(
		.C_ADDRA_WIDTH(9),
		.C_ADDRB_WIDTH(9),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(9),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(512),
		.C_READ_DEPTH_B(512),
		.C_READ_WIDTH_A(20),
		.C_READ_WIDTH_B(20),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(0),
		.C_USE_BYTE_WEB(0),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(1),
		.C_WEB_WIDTH(1),
		.C_WRITE_DEPTH_A(512),
		.C_WRITE_DEPTH_B(512),
		.C_WRITE_MODE_A("READ_FIRST"),
		.C_WRITE_MODE_B("READ_FIRST"),
		.C_WRITE_WIDTH_A(20),
		.C_WRITE_WIDTH_B(20),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.CLKB(clkb),
		.ADDRB(addrb),
		.DOUTB(doutb),
		.RSTA(),
		.REGCEA(),
		.DOUTA(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.DINB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

`else

reg	[8:0]	addrb_reg;		// RAM address register

always @(posedge clka)
		addrb_reg <= #1 addrb;


//
// Generic RAM's registers and wires
//
reg	[19:0]	mem [(1<<9)-1:0];	// RAM content

//
// Data output drivers
//
assign doutb = mem[addrb_reg];

//
// RAM write
//
always @(posedge clka)
	if (ena && wea)
		mem[addra] <= #1 dina;

`endif

endmodule
module dtlb_mr_blk(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [5 : 0] addra;
input [13 : 0] dina;
input clkb;
input [5 : 0] addrb;
output [13 : 0] doutb;

`ifdef BLK_MEM_GEN

// synthesis translate_off

      BLK_MEM_GEN_V3_1 #(
		.C_ADDRA_WIDTH(6),
		.C_ADDRB_WIDTH(6),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(9),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(64),
		.C_READ_DEPTH_B(64),
		.C_READ_WIDTH_A(14),
		.C_READ_WIDTH_B(14),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(0),
		.C_USE_BYTE_WEB(0),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(1),
		.C_WEB_WIDTH(1),
		.C_WRITE_DEPTH_A(64),
		.C_WRITE_DEPTH_B(64),
		.C_WRITE_MODE_A("READ_FIRST"),
		.C_WRITE_MODE_B("READ_FIRST"),
		.C_WRITE_WIDTH_A(14),
		.C_WRITE_WIDTH_B(14),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.CLKB(clkb),
		.ADDRB(addrb),
		.DOUTB(doutb),
		.RSTA(),
		.REGCEA(),
		.DOUTA(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.DINB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

`else

reg	[5:0]	addrb_reg;		// RAM address register

always @(posedge clkb)
		addrb_reg <= #1 addrb;


//
// Generic RAM's registers and wires
//
reg	[13:0]	mem [(1<<6)-1:0];	// RAM content

//
// Data output drivers
//
assign doutb = mem[addrb_reg];

//
// RAM write
//
always @(posedge clka)
	if (ena && wea)
		mem[addra] <= #1 dina;

`endif

endmodule
module dtlb_tr_sub(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [5 : 0] addra;
input [23 : 0] dina;
input clkb;
input [5 : 0] addrb;
output [23 : 0] doutb;

wire ena_wire;
wire [0 : 0] wea_wire;
wire [5 : 0] addra_wire;
wire [23 : 0] dina_wire;
wire [5 : 0] addrb_wire;

assign ena_wire = ena;
assign wea_wire = wea;
assign addra_wire = addra;
assign dina_wire = dina;
assign addrb_wire = addrb;

dtlb_tr_blk dtlb_tr_blki(
	.clka(clka),
	.ena(ena_wire),
	.wea(wea_wire),
	.addra(addra_wire),
	.dina(dina_wire),
	.clkb(clkb),
	.addrb(addrb_wire),
	.doutb(doutb));

endmodule
module rf_dist(
	a,
	d,
	dpra,
	clk,
	we,
	spo,
	dpo);


input [4 : 0] a;
input [31 : 0] d;
input [4 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;

// synthesis translate_off

      DIST_MEM_GEN_V4_1 #(
		.C_ADDR_WIDTH(5),
		.C_DEFAULT_DATA("0"),
		.C_DEPTH(32),
		.C_HAS_CLK(1),
		.C_HAS_D(1),
		.C_HAS_DPO(1),
		.C_HAS_DPRA(1),
		.C_HAS_I_CE(0),
		.C_HAS_QDPO(0),
		.C_HAS_QDPO_CE(0),
		.C_HAS_QDPO_CLK(0),
		.C_HAS_QDPO_RST(0),
		.C_HAS_QDPO_SRST(0),
		.C_HAS_QSPO(0),
		.C_HAS_QSPO_CE(0),
		.C_HAS_QSPO_RST(0),
		.C_HAS_QSPO_SRST(0),
		.C_HAS_SPO(1),
		.C_HAS_SPRA(0),
		.C_HAS_WE(1),
		.C_MEM_INIT_FILE("rf_dist.mif"),
		.C_MEM_TYPE(2),
		.C_PARSER_TYPE(1),
		.C_PIPELINE_STAGES(0),
		.C_QCE_JOINED(0),
		.C_QUALIFY_WE(0),
		.C_READ_MIF(1),
		.C_REG_A_D_INPUTS(0),
		.C_REG_DPRA_INPUT(0),
		.C_SYNC_ENABLE(1),
		.C_WIDTH(32))
	inst (
		.A(a),
		.D(d),
		.DPRA(dpra),
		.CLK(clk),
		.WE(we),
		.SPO(spo),
		.DPO(dpo),
		.SPRA(),
		.I_CE(),
		.QSPO_CE(),
		.QDPO_CE(),
		.QDPO_CLK(),
		.QSPO_RST(),
		.QDPO_RST(),
		.QSPO_SRST(),
		.QDPO_SRST(),
		.QSPO(),
		.QDPO());


// synthesis translate_on


endmodule
module ic_tag_sub(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [8 : 0] addra;
input [19 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [19 : 0] doutb;

ic_tag_blk ic_tag_blki(
	.clka(clka),
	.ena(ena),
	.wea(wea),
	.addra(addra),
	.dina(dina),
	.clkb(clkb),
	.addrb(addrb),
	.doutb(doutb));

endmodule
module itlb_tr_sub(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [5 : 0] addra;
input [21 : 0] dina;
input clkb;
input [5 : 0] addrb;
output [21 : 0] doutb;

wire ena_wire;
wire [0 : 0] wea_wire;
wire [5 : 0] addra_wire;
wire [21 : 0] dina_wire;
wire [5 : 0] addrb_wire;

assign ena_wire = ena;
assign wea_wire = wea;
assign addra_wire = addra;
assign dina_wire = dina;
assign addrb_wire = addrb;

itlb_tr_blk itlb_tr_blki(
	.clka(clka),
	.ena(ena_wire),
	.wea(wea_wire),
	.addra(addra_wire),
	.dina(dina_wire),
	.clkb(clkb),
	.addrb(addrb_wire),
	.doutb(doutb));

endmodule
module itlb_mr_sub(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [5 : 0] addra;
input [13 : 0] dina;
input clkb;
input [5 : 0] addrb;
output [13 : 0] doutb;

wire ena_wire;
wire [0 : 0] wea_wire;
wire [5 : 0] addra_wire;
wire [13 : 0] dina_wire;
wire [5 : 0] addrb_wire;

assign ena_wire = ena;
assign wea_wire = wea;
assign addra_wire = addra;
assign dina_wire = dina;
assign addrb_wire = addrb;

itlb_mr_blk itlb_mr_blki(
	.clka(clka),
	.ena(ena_wire),
	.wea(wea_wire),
	.addra(addra_wire),
	.dina(dina_wire),
	.clkb(clkb),
	.addrb(addrb_wire),
	.doutb(doutb));

endmodule
module or1200_freeze(
	// Clock and reset
	clk, rst,

	// Internal i/f
	multicycle, flushpipe, extend_flush, lsu_stall, if_stall,
	lsu_unstall, du_stall, mac_stall, 
	force_dslot_fetch, abort_ex,
	genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze,
	icpu_ack_i, icpu_err_i
);

//
// I/O
//
input				clk;
input				rst;
input	[`OR1200_MULTICYCLE_WIDTH-1:0]	multicycle;
input				flushpipe;
input				extend_flush;
input				lsu_stall;
input				if_stall;
input				lsu_unstall;
input				force_dslot_fetch;
input				abort_ex;
input				du_stall;
input				mac_stall;
output				genpc_freeze;
output				if_freeze;
output				id_freeze;
output				ex_freeze;
output				wb_freeze;
input				icpu_ack_i;
input				icpu_err_i;

//
// Internal wires and regs
//
wire				multicycle_freeze;
reg	[`OR1200_MULTICYCLE_WIDTH-1:0]	multicycle_cnt;
reg				flushpipe_r;

//
// Pipeline freeze
//
// Rules how to create freeze signals:
// 1. Not overwriting pipeline stages:
// Freze signals at the beginning of pipeline (such as if_freeze) can be asserted more
// often than freeze signals at the of pipeline (such as wb_freeze). In other words, wb_freeze must never
// be asserted when ex_freeze is not. ex_freeze must never be asserted when id_freeze is not etc.
//
// 2. Inserting NOPs in the middle of pipeline only if supported:
// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.
// This way NOP is asserted from stage ID into EX stage.
//
//assign genpc_freeze = du_stall | flushpipe_r | lsu_stall;
assign genpc_freeze = du_stall | flushpipe_r;
assign if_freeze = id_freeze | extend_flush;
//assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~flushpipe | du_stall;
assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) | du_stall | mac_stall;
assign ex_freeze = wb_freeze;
//assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) & ~flushpipe | du_stall | mac_stall;
assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) | du_stall | mac_stall | abort_ex;

//
// registered flushpipe
//
always @(posedge clk or posedge rst)
	if (rst)
		flushpipe_r <= #1 1'b0;
	else if (icpu_ack_i | icpu_err_i)
//	else if (!if_stall)
		flushpipe_r <= #1 flushpipe;
	else if (!flushpipe)
		flushpipe_r <= #1 1'b0;
		
//
// Multicycle freeze
//
assign multicycle_freeze = |multicycle_cnt;

//
// Multicycle counter
//
always @(posedge clk or posedge rst)
	if (rst)
		multicycle_cnt <= #1 2'b00;
	else if (|multicycle_cnt)
		multicycle_cnt <= #1 multicycle_cnt - 2'd1;
	else if (|multicycle & !ex_freeze)
		multicycle_cnt <= #1 multicycle;

endmodule
module ic_ram_sub(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);



input clka;
input ena;
input [0 : 0] wea;
input [10 : 0] addra;
input [31 : 0] dina;
input clkb;
input [10 : 0] addrb;
output [31 : 0] doutb;

wire ena_wire;
wire [0 : 0] wea_wire;
wire [10 : 0] addra_wire;
wire [31 : 0] dina_wire;
wire [10 : 0] addrb_wire;

assign ena_wire = ena;
assign wea_wire = wea;
assign addra_wire = addra;
assign dina_wire = dina;
assign addrb_wire = addrb;

ic_ram_blk ic_ram_blki(
	.clka(clka),
	.ena(ena_wire),
	.wea(wea_wire),
	.addra(addra_wire),
	.dina(dina_wire),
	.clkb(clkb),
	.addrb(addrb_wire),
	.doutb(doutb));

endmodule
module ic_ram_blk(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [10 : 0] addra;
input [31 : 0] dina;
input clkb;
input [10 : 0] addrb;
output [31 : 0] doutb;

`ifdef BLK_MEM_GEN

// synthesis translate_off

      BLK_MEM_GEN_V3_1 #(
		.C_ADDRA_WIDTH(11),
		.C_ADDRB_WIDTH(11),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(9),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(2048),
		.C_READ_DEPTH_B(2048),
		.C_READ_WIDTH_A(32),
		.C_READ_WIDTH_B(32),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(0),
		.C_USE_BYTE_WEB(0),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(1),
		.C_WEB_WIDTH(1),
		.C_WRITE_DEPTH_A(2048),
		.C_WRITE_DEPTH_B(2048),
		.C_WRITE_MODE_A("READ_FIRST"),
		.C_WRITE_MODE_B("READ_FIRST"),
		.C_WRITE_WIDTH_A(32),
		.C_WRITE_WIDTH_B(32),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.CLKB(clkb),
		.ADDRB(addrb),
		.DOUTB(doutb),
		.RSTA(),
		.REGCEA(),
		.DOUTA(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.DINB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

`else

reg	[10:0]	addrb_reg;		// RAM address register

always @(posedge clka)
		addrb_reg <= #1 addrb;

//
// Generic RAM's registers and wires
//
reg	[31:0]	mem [(1<<11)-1:0];	// RAM content

//
// Data output drivers
//
assign doutb = mem[addrb_reg];

//
// RAM write
//
always @(posedge clka)
	if (ena && wea)
		mem[addra] <= #1 dina;

`endif

endmodule
module or1200_reg2mem(addr, lsu_op, regdata, memdata);

parameter width = `OR1200_OPERAND_WIDTH;

//
// I/O
//
input	[1:0]			addr;
input	[`OR1200_LSUOP_WIDTH-1:0]	lsu_op;
input	[width-1:0]		regdata;
output	[width-1:0]		memdata;

//
// Internal regs and wires
//
reg	[7:0]			memdata_hh;
reg	[7:0]			memdata_hl;
reg	[7:0]			memdata_lh;
reg	[7:0]			memdata_ll;

assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll};

//
// Mux to memdata[31:24]
//
always @(lsu_op or addr or regdata) begin
	casex({lsu_op, addr[1:0]})	// synopsys parallel_case
		{`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0];
		{`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8];
		default : memdata_hh = regdata[31:24];
	endcase
end

//
// Mux to memdata[23:16]
//
always @(lsu_op or addr or regdata) begin
	casex({lsu_op, addr[1:0]})	// synopsys parallel_case
		{`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16];
		default : memdata_hl = regdata[7:0];
	endcase
end

//
// Mux to memdata[15:8]
//
always @(lsu_op or addr or regdata) begin
	casex({lsu_op, addr[1:0]})	// synopsys parallel_case
		{`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0];
		default : memdata_lh = regdata[15:8];
	endcase
end

//
// Mux to memdata[7:0]
//
always @(regdata)
	memdata_ll = regdata[7:0];

endmodule
module or1200_operandmuxes(
	// Clock and reset
	clk, rst,

	// Internal i/f
	id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
	simm, sel_a, sel_b, operand_a, operand_b, muxed_b
);

parameter width = `OR1200_OPERAND_WIDTH;

//
// I/O
//
input				clk;
input				rst;
input				id_freeze;
input				ex_freeze;
input	[width-1:0]		rf_dataa;
input	[width-1:0]		rf_datab;
input	[width-1:0]		ex_forw;
input	[width-1:0]		wb_forw;
input	[width-1:0]		simm;
input	[`OR1200_SEL_WIDTH-1:0]	sel_a;
input	[`OR1200_SEL_WIDTH-1:0]	sel_b;
output	[width-1:0]		operand_a;
output	[width-1:0]		operand_b;
output	[width-1:0]		muxed_b;

//
// Internal wires and regs
//
reg	[width-1:0]		operand_a;
reg	[width-1:0]		operand_b;
reg	[width-1:0]		muxed_a;
reg	[width-1:0]		muxed_b;
reg				saved_a;
reg				saved_b;

//
// Operand A register
//
always @(posedge clk or posedge rst) begin
	if (rst) begin
		operand_a <= #1 32'd0;
		saved_a <= #1 1'b0;
	end else if (!ex_freeze && id_freeze && !saved_a) begin
		operand_a <= #1 muxed_a;
		saved_a <= #1 1'b1;
	end else if (!ex_freeze && !saved_a) begin
		operand_a <= #1 muxed_a;
	end else if (!ex_freeze && !id_freeze)
		saved_a <= #1 1'b0;
end

//
// Operand B register
//
always @(posedge clk or posedge rst) begin
	if (rst) begin
		operand_b <= #1 32'd0;
		saved_b <= #1 1'b0;
	end else if (!ex_freeze && id_freeze && !saved_b) begin
		operand_b <= #1 muxed_b;
		saved_b <= #1 1'b1;
	end else if (!ex_freeze && !saved_b) begin
		operand_b <= #1 muxed_b;
	end else if (!ex_freeze && !id_freeze)
		saved_b <= #1 1'b0;
end

//
// Forwarding logic for operand A register
//
always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
	casex (sel_a)	// synopsys parallel_case infer_mux
`else
	casex (sel_a)	// synopsys parallel_case
`endif
		`OR1200_SEL_EX_FORW:
			muxed_a = ex_forw;
		`OR1200_SEL_WB_FORW:
			muxed_a = wb_forw;
		default:
			muxed_a = rf_dataa;
	endcase
end

//
// Forwarding logic for operand B register
//
always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
	casex (sel_b)	// synopsys parallel_case infer_mux
`else
	casex (sel_b)	// synopsys parallel_case
`endif
		`OR1200_SEL_IMM:
			muxed_b = simm;
		`OR1200_SEL_EX_FORW:
			muxed_b = ex_forw;
		`OR1200_SEL_WB_FORW:
			muxed_b = wb_forw;
		default:
			muxed_b = rf_datab;
	endcase
end

endmodule
module dc_tag_blk(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [8 : 0] addra;
input [19 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [19 : 0] doutb;

`ifdef BLK_MEM_GEN

// synthesis translate_off

      BLK_MEM_GEN_V3_1 #(
		.C_ADDRA_WIDTH(9),
		.C_ADDRB_WIDTH(9),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(9),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(512),
		.C_READ_DEPTH_B(512),
		.C_READ_WIDTH_A(20),
		.C_READ_WIDTH_B(20),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(0),
		.C_USE_BYTE_WEB(0),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(1),
		.C_WEB_WIDTH(1),
		.C_WRITE_DEPTH_A(512),
		.C_WRITE_DEPTH_B(512),
		.C_WRITE_MODE_A("READ_FIRST"),
		.C_WRITE_MODE_B("READ_FIRST"),
		.C_WRITE_WIDTH_A(20),
		.C_WRITE_WIDTH_B(20),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.CLKB(clkb),
		.ADDRB(addrb),
		.DOUTB(doutb),
		.RSTA(),
		.REGCEA(),
		.DOUTA(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.DINB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

`else

reg	[8:0]	addrb_reg;		// RAM address register

always @(posedge clka)
		addrb_reg <= #1 addrb;

//
// Generic RAM's registers and wires
//
reg	[19:0]	mem [(1<<9)-1:0];	// RAM content

//
// Data output drivers
//
assign doutb = mem[addrb_reg];

//
// RAM write
//
always @(posedge clka)
	if (ena && wea)
		mem[addra] <= #1 dina;

`endif


endmodule
module dc_tag_sub(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [8 : 0] addra;
input [19 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [19 : 0] doutb;

dc_tag_blk dc_tag_blki(
	.clka(clka),
	.ena(ena),
	.wea(wea),
	.addra(addra),
	.dina(dina),
	.clkb(clk),
	.addrb(addrb),
	.doutb(doutb));

endmodule