dakies/OSS_Verilog huggingface dataset:
module ct_rtu_compare_iid(
  x_iid0,
  x_iid0_older,
  x_iid1
);

// &Ports; @25
input   [6:0]  x_iid0;          
input   [6:0]  x_iid1;          
output         x_iid0_older;    

// &Regs; @26

// &Wires; @27
wire           iid0_5_0_larger; 
wire    [5:0]  iid0_larger;     
wire           iid1_5_0_larger; 
wire    [5:0]  iid1_larger;     
wire           iid_msb_mismatch; 
wire    [6:0]  x_iid0;          
wire           x_iid0_older;    
wire    [6:0]  x_iid1;          


//==========================================================
//            Compare order of two 7 bits IIDs
//==========================================================
assign iid_msb_mismatch = x_iid0[6] ^ x_iid1[6];

assign iid0_larger[5] = x_iid0[5] && !x_iid1[5];
assign iid0_larger[4] = x_iid0[4] && !x_iid1[4];
assign iid0_larger[3] = x_iid0[3] && !x_iid1[3];
assign iid0_larger[2] = x_iid0[2] && !x_iid1[2];
assign iid0_larger[1] = x_iid0[1] && !x_iid1[1];
assign iid0_larger[0] = x_iid0[0] && !x_iid1[0];

assign iid1_larger[5] = !x_iid0[5] && x_iid1[5];
assign iid1_larger[4] = !x_iid0[4] && x_iid1[4];
assign iid1_larger[3] = !x_iid0[3] && x_iid1[3];
assign iid1_larger[2] = !x_iid0[2] && x_iid1[2];
assign iid1_larger[1] = !x_iid0[1] && x_iid1[1];
assign iid1_larger[0] = !x_iid0[0] && x_iid1[0];

assign iid0_5_0_larger =
     iid0_larger[5]
  || iid0_larger[4] && !iid1_larger[5]
  || iid0_larger[3] && !(|iid1_larger[5:4])
  || iid0_larger[2] && !(|iid1_larger[5:3])
  || iid0_larger[1] && !(|iid1_larger[5:2])
  || iid0_larger[0] && !(|iid1_larger[5:1]);

assign iid1_5_0_larger =
     iid1_larger[5]
  || iid1_larger[4] && !iid0_larger[5]
  || iid1_larger[3] && !(|iid0_larger[5:4])
  || iid1_larger[2] && !(|iid0_larger[5:3])
  || iid1_larger[1] && !(|iid0_larger[5:2])
  || iid1_larger[0] && !(|iid0_larger[5:1]);

assign x_iid0_older = !iid_msb_mismatch && iid1_5_0_larger
                  || iid_msb_mismatch && iid0_5_0_larger;

// &ModuleEnd; @67
endmodule
module ct_rtu_encode_64(
  x_num,
  x_num_expand
);

// &Ports; @25
input   [63:0]  x_num_expand; 
output  [5 :0]  x_num;       

// &Regs; @26

// &Wires; @27
wire    [5 :0]  x_num;       
wire    [63:0]  x_num_expand; 


//==========================================================
//  encode 64 bits one-hot number to 6 bits binary number
//==========================================================
assign x_num[5:0] =
           {6{x_num_expand[0]}}  & 6'd0
         | {6{x_num_expand[1]}}  & 6'd1
         | {6{x_num_expand[2]}}  & 6'd2
         | {6{x_num_expand[3]}}  & 6'd3
         | {6{x_num_expand[4]}}  & 6'd4
         | {6{x_num_expand[5]}}  & 6'd5
         | {6{x_num_expand[6]}}  & 6'd6
         | {6{x_num_expand[7]}}  & 6'd7
         | {6{x_num_expand[8]}}  & 6'd8
         | {6{x_num_expand[9]}}  & 6'd9
         | {6{x_num_expand[10]}} & 6'd10
         | {6{x_num_expand[11]}} & 6'd11
         | {6{x_num_expand[12]}} & 6'd12
         | {6{x_num_expand[13]}} & 6'd13
         | {6{x_num_expand[14]}} & 6'd14
         | {6{x_num_expand[15]}} & 6'd15
         | {6{x_num_expand[16]}} & 6'd16
         | {6{x_num_expand[17]}} & 6'd17
         | {6{x_num_expand[18]}} & 6'd18
         | {6{x_num_expand[19]}} & 6'd19
         | {6{x_num_expand[20]}} & 6'd20
         | {6{x_num_expand[21]}} & 6'd21
         | {6{x_num_expand[22]}} & 6'd22
         | {6{x_num_expand[23]}} & 6'd23
         | {6{x_num_expand[24]}} & 6'd24
         | {6{x_num_expand[25]}} & 6'd25
         | {6{x_num_expand[26]}} & 6'd26
         | {6{x_num_expand[27]}} & 6'd27
         | {6{x_num_expand[28]}} & 6'd28
         | {6{x_num_expand[29]}} & 6'd29
         | {6{x_num_expand[30]}} & 6'd30
         | {6{x_num_expand[31]}} & 6'd31
         | {6{x_num_expand[32]}} & 6'd32
         | {6{x_num_expand[33]}} & 6'd33
         | {6{x_num_expand[34]}} & 6'd34
         | {6{x_num_expand[35]}} & 6'd35
         | {6{x_num_expand[36]}} & 6'd36
         | {6{x_num_expand[37]}} & 6'd37
         | {6{x_num_expand[38]}} & 6'd38
         | {6{x_num_expand[39]}} & 6'd39
         | {6{x_num_expand[40]}} & 6'd40
         | {6{x_num_expand[41]}} & 6'd41
         | {6{x_num_expand[42]}} & 6'd42
         | {6{x_num_expand[43]}} & 6'd43
         | {6{x_num_expand[44]}} & 6'd44
         | {6{x_num_expand[45]}} & 6'd45
         | {6{x_num_expand[46]}} & 6'd46
         | {6{x_num_expand[47]}} & 6'd47
         | {6{x_num_expand[48]}} & 6'd48
         | {6{x_num_expand[49]}} & 6'd49
         | {6{x_num_expand[50]}} & 6'd50
         | {6{x_num_expand[51]}} & 6'd51
         | {6{x_num_expand[52]}} & 6'd52
         | {6{x_num_expand[53]}} & 6'd53
         | {6{x_num_expand[54]}} & 6'd54
         | {6{x_num_expand[55]}} & 6'd55
         | {6{x_num_expand[56]}} & 6'd56
         | {6{x_num_expand[57]}} & 6'd57
         | {6{x_num_expand[58]}} & 6'd58
         | {6{x_num_expand[59]}} & 6'd59
         | {6{x_num_expand[60]}} & 6'd60
         | {6{x_num_expand[61]}} & 6'd61
         | {6{x_num_expand[62]}} & 6'd62
         | {6{x_num_expand[63]}} & 6'd63;

// &ModuleEnd; @98
endmodule
module ct_rtu_encode_8(
  x_num,
  x_num_expand
);

// &Ports; @25
input   [7:0]  x_num_expand; 
output  [2:0]  x_num;       

// &Regs; @26

// &Wires; @27
wire    [2:0]  x_num;       
wire    [7:0]  x_num_expand; 


//==========================================================
//  encode 8 bits one-hot number to 3 bits binary number
//==========================================================
assign x_num[2:0] =
           {3{x_num_expand[0]}} & 3'd0
         | {3{x_num_expand[1]}} & 3'd1
         | {3{x_num_expand[2]}} & 3'd2
         | {3{x_num_expand[3]}} & 3'd3
         | {3{x_num_expand[4]}} & 3'd4
         | {3{x_num_expand[5]}} & 3'd5
         | {3{x_num_expand[6]}} & 3'd6
         | {3{x_num_expand[7]}} & 3'd7;

// &ModuleEnd; @42
endmodule
module ct_mmu_sysmap_hit(
  addr_ge_bottom_x,
  addr_ge_upaddr_x,
  sysmap_comp_hit_x,
  sysmap_mmu_hit_x
);

// &Ports; @27
input        addr_ge_bottom_x; 
input        sysmap_comp_hit_x; 
output       addr_ge_upaddr_x; 
output       sysmap_mmu_hit_x; 

// &Regs; @28

// &Wires; @29
wire         addr_ge_bottom_x; 
wire         addr_ge_upaddr_x; 
wire         addr_ls_top;      
wire         sysmap_comp_hit_x; 
wire         sysmap_mmu_hit_x; 



assign addr_ls_top      = sysmap_comp_hit_x;

assign addr_ge_upaddr_x = !addr_ls_top;
assign sysmap_mmu_hit_x = addr_ge_bottom_x && addr_ls_top;

// &ModuleEnd; @37
endmodule
module_en,
  local_en,
  external_en,
  pad_yy_icg_scan_en,
  clk_out
);

input  clk_in;
input  global_en;
input  module_en;
input  local_en;
input  external_en;
input  pad_yy_icg_scan_en;
output clk_out;

wire   clk_en_bf_latch;
wire   SE;

assign clk_en_bf_latch = (global_en && (module_en || local_en)) || external_en ;

// SE driven from primary input, held constant
assign SE	       = pad_yy_icg_scan_en;

// //   &Connect(    .clk_in           (clk_in), @50
// //                .SE               (SE), @51
// //                .external_en      (clk_en_bf_latch), @52
// //                .clk_out          (clk_out) @53
// //                ) ; @54
assign clk_out = clk_in;

endmodule
module ct_clk_top(
  biu_xx_dbg_wakeup,
  biu_xx_int_wakeup,
  biu_xx_normal_work,
  biu_xx_pmp_sel,
  biu_xx_snoop_vld,
  coreclk,
  cp0_xx_core_icg_en,
  forever_coreclk,
  had_xx_clk_en,
  pll_core_clk
);

// &Ports; @23
input        biu_xx_dbg_wakeup; 
input        biu_xx_int_wakeup; 
input        biu_xx_normal_work; 
input        biu_xx_pmp_sel;    
input        biu_xx_snoop_vld;  
input        cp0_xx_core_icg_en; 
input        had_xx_clk_en;     
input        pll_core_clk;      
output       coreclk;           
output       forever_coreclk;   

// &Regs; @24

// &Wires; @25
wire         biu_xx_dbg_wakeup; 
wire         biu_xx_int_wakeup; 
wire         biu_xx_normal_work; 
wire         biu_xx_pmp_sel;    
wire         biu_xx_snoop_vld;  
wire         core_clk_en;       
wire         cp0_xx_core_icg_en; 
wire         forever_coreclk;   
wire         had_xx_clk_en;     
wire         pll_core_clk;      


// &Force("output", "forever_coreclk"); @27

assign forever_coreclk = pll_core_clk;
//==============================================================================
//      global ICG for core 
//==============================================================================
assign core_clk_en = biu_xx_normal_work |
                     biu_xx_int_wakeup | 
                     biu_xx_dbg_wakeup | 
                     biu_xx_snoop_vld |
                     had_xx_clk_en | 
                     biu_xx_pmp_sel |
                     cp0_xx_core_icg_en ;
// &Force("nonport","core_clk_en"); @41
// &Force("output","coreclk"); @42
BUFGCE core_clk_buf
(.O   (coreclk),
 .I   (forever_coreclk),
 .CE  (core_clk_en)
);
// &Instance("gated_clk_cell", "x_core_gated_clk"); @49
// &Connect(.clk_in      (forever_coreclk     ), @50
//          .external_en (1'b0                ), @51
//          .global_en   (1'b1                ), @52
//          .module_en   (1'b0                ), @53
//          .local_en    (core_clk_en         ), @54
//          .clk_out     (coreclk             )); @55

// &ModuleEnd; @58
endmodule
module ct_biu_csr_req_arbiter(
  biu_cp0_cmplt,
  biu_cp0_rdata,
  biu_csr_cmplt,
  biu_csr_op,
  biu_csr_rdata,
  biu_csr_sel,
  biu_csr_wdata,
  biu_hpcp_cmplt,
  biu_hpcp_rdata,
  cp0_biu_op,
  cp0_biu_sel,
  cp0_biu_wdata,
  hpcp_biu_op,
  hpcp_biu_sel,
  hpcp_biu_wdata
);

// &Ports; @23
input            biu_csr_cmplt; 
input   [127:0]  biu_csr_rdata; 
input   [15 :0]  cp0_biu_op;    
input            cp0_biu_sel;   
input   [63 :0]  cp0_biu_wdata; 
input   [15 :0]  hpcp_biu_op;   
input            hpcp_biu_sel;  
input   [63 :0]  hpcp_biu_wdata; 
output           biu_cp0_cmplt; 
output  [127:0]  biu_cp0_rdata; 
output  [15 :0]  biu_csr_op;    
output           biu_csr_sel;   
output  [63 :0]  biu_csr_wdata; 
output           biu_hpcp_cmplt; 
output  [127:0]  biu_hpcp_rdata; 

// &Regs; @24
reg     [15 :0]  biu_csr_op;    
reg              biu_csr_sel;   
reg     [63 :0]  biu_csr_wdata; 

// &Wires; @25
wire             biu_cp0_cmplt; 
wire    [127:0]  biu_cp0_rdata; 
wire             biu_csr_cmplt; 
wire    [127:0]  biu_csr_rdata; 
wire             biu_hpcp_cmplt; 
wire    [127:0]  biu_hpcp_rdata; 
wire    [15 :0]  cp0_biu_op;    
wire             cp0_biu_sel;   
wire    [63 :0]  cp0_biu_wdata; 
wire    [15 :0]  hpcp_biu_op;   
wire             hpcp_biu_sel;  
wire    [63 :0]  hpcp_biu_wdata; 


// &CombBeg; @27
always @( hpcp_biu_op[15:0]
       or hpcp_biu_wdata[63:0]
       or cp0_biu_wdata[63:0]
       or cp0_biu_op[15:0]
       or cp0_biu_sel
       or hpcp_biu_sel)
begin
  if(cp0_biu_sel)
  begin
    biu_csr_sel         = 1'b1;
    biu_csr_op[15:0]    = cp0_biu_op[15:0];
    biu_csr_wdata[63:0] = cp0_biu_wdata[63:0];
  end
  else
  begin
    biu_csr_sel         = hpcp_biu_sel;
    biu_csr_op[15:0]    = hpcp_biu_op[15:0];
    biu_csr_wdata[63:0] = hpcp_biu_wdata[63:0];
  end
// &CombEnd; @40
end

assign biu_cp0_cmplt         = biu_csr_cmplt && cp0_biu_sel;
assign biu_cp0_rdata[127:0]  = biu_csr_rdata[127:0];
assign biu_hpcp_cmplt        = biu_csr_cmplt;
assign biu_hpcp_rdata[127:0] = biu_csr_rdata[127:0];

// &ModuleEnd; @47
endmodule
module sync_level2pulse(
  clk,
  rst_b,
  sync_in,
  sync_out,
  sync_ack
);


input          clk;
input          rst_b;
input          sync_in;
output         sync_out;
output         sync_ack;

reg            sync_ff;

wire           clk;
wire           rst_b;
wire           sync_in;
wire           sync_out;
wire           sync_ack;

wire           sync_out_level;

sync_level2level x_sync_level2level (
  .clk      (clk),
  .rst_b    (rst_b),
  .sync_in  (sync_in),
  .sync_out (sync_out_level)
);

always @ (posedge clk or negedge rst_b)
begin
  if (!rst_b)
    sync_ff <= 1'b0;
  else
    sync_ff <= sync_out_level;
end

assign sync_out = sync_out_level & ~sync_ff;
assign sync_ack = sync_out_level;

endmodule
module compressor_42(p0,p1,p2,p3,cin,s,ca,cout);
parameter B_SIZE = 8;
  
input  [B_SIZE-1:0] p0;
input  [B_SIZE-1:0] p1;
input  [B_SIZE-1:0] p2;
input  [B_SIZE-1:0] p3;
input  [B_SIZE-1:0] cin;
output [B_SIZE-1:0] s;
output [B_SIZE-1:0] ca;
output [B_SIZE-1:0] cout;

wire   [B_SIZE-1:0]  xor0;
wire   [B_SIZE-1:0]  xor1;
wire   [B_SIZE-1:0]  xor2;
wire   [B_SIZE-1:0]  s;
wire   [B_SIZE-1:0]  ca;
wire   [B_SIZE-1:0]  cout;

assign xor0[B_SIZE-1:0] = p0[B_SIZE-1:0] ^ p1[B_SIZE-1:0];
assign xor1[B_SIZE-1:0] = p2[B_SIZE-1:0] ^ p3[B_SIZE-1:0];
assign xor2[B_SIZE-1:0] = xor1[B_SIZE-1:0] ^ xor0[B_SIZE-1:0];

//cout is used for input cin
assign cout[B_SIZE-1:0] = xor0[B_SIZE-1:0] & p2[B_SIZE-1:0]
                        | (~xor0[B_SIZE-1:0] & p0[B_SIZE-1:0]);
assign s[B_SIZE-1:0]    = xor2[B_SIZE-1:0] ^ cin[B_SIZE-1:0];
assign ca[B_SIZE-1:0]   = xor2[B_SIZE-1:0] & cin[B_SIZE-1:0]
                        | ~xor2[B_SIZE-1:0] & p3[B_SIZE-1:0];

endmodule
module booth_code(
A,       // mulitplicand
code,    // booth code
product, // partial product
h,      
sn       // partial_sign
);
parameter B_SIZE = 53;

input  [B_SIZE-1:0] A;
input  [ 2:0] code;
output [B_SIZE:0] product;
output [ 1:0] h;
output        sn;

reg    [B_SIZE:0] product;
reg    [ 1:0] h;
reg           sn;

wire A_sign;

assign A_sign = A[B_SIZE-1]; 

always @(A[B_SIZE-1:0]
      or code[2:0]
      or A_sign) 
begin
  case(code[2:0])
    3'b000 : product[B_SIZE:0] = {B_SIZE+1{1'b0}};
    3'b001 : product[B_SIZE:0] = { A_sign       , A[B_SIZE-1:0]};
    3'b010 : product[B_SIZE:0] = { A_sign       , A[B_SIZE-1:0]};
    3'b011 : product[B_SIZE:0] = { A[B_SIZE-1:0],1'b0          };
    3'b100 : product[B_SIZE:0] = {~A[B_SIZE-1:0],1'b1          };
    3'b101 : product[B_SIZE:0] = { ~A_sign      ,~A[B_SIZE-1:0]};
    3'b110 : product[B_SIZE:0] = { ~A_sign      ,~A[B_SIZE-1:0]};
    3'b111 : product[B_SIZE:0] = {B_SIZE+1{1'b0}};
    default: product[B_SIZE:0] = {B_SIZE+1{1'bx}};
  endcase
end

always @(code[2:0]
      or A_sign)
begin
  case(code[2:0])
    3'b000 : sn =  1'b1;
    3'b001 : sn = ~A_sign;
    3'b010 : sn = ~A_sign;
    3'b011 : sn = ~A_sign;
    3'b100 : sn =  A_sign;
    3'b101 : sn =  A_sign;
    3'b110 : sn =  A_sign;
    3'b111 : sn =  1'b1;
  endcase
end

always @(code[2:0]) 
begin
  case(code[2:0])
    3'b000 : h[1:0] = 2'b00;
    3'b001 : h[1:0] = 2'b00;
    3'b010 : h[1:0] = 2'b00;
    3'b011 : h[1:0] = 2'b00;
    3'b100 : h[1:0] = 2'b01;
    3'b101 : h[1:0] = 2'b01;
    3'b110 : h[1:0] = 2'b01;
    3'b111 : h[1:0] = 2'b00;
    default: h[1:0] = {2{1'bx}};
  endcase
end

endmodule
module booth_code_v1(
A,       // mulitplicand
code,    // booth code
product, // partial product
h,      
sn       // partial_sign
);
parameter B_SIZE = 53;

input  [B_SIZE-1:0] A;
input  [ 2:0] code;
output [B_SIZE:0] product;
output [ 1:0] h;
output        sn;

reg    [B_SIZE:0] product;
reg    [ 1:0] h;
reg           sn;


always @(A[B_SIZE-1:0]
      or code[2:0]) 
begin
  case(code[2:0])
    3'b000 : product[B_SIZE:0] = {B_SIZE+1{1'b0}};
    3'b001 : product[B_SIZE:0] = { 1'b0         , A[B_SIZE-1:0]};
    3'b010 : product[B_SIZE:0] = { 1'b0         , A[B_SIZE-1:0]};
    3'b011 : product[B_SIZE:0] = { A[B_SIZE-1:0],1'b0          };
    3'b100 : product[B_SIZE:0] = {~A[B_SIZE-1:0],1'b1          };
    3'b101 : product[B_SIZE:0] = { 1'b1         ,~A[B_SIZE-1:0]};
    3'b110 : product[B_SIZE:0] = { 1'b1         ,~A[B_SIZE-1:0]};
    3'b111 : product[B_SIZE:0] = {B_SIZE+1{1'b0}};
    default: product[B_SIZE:0] = {B_SIZE+1{1'bx}};
  endcase
end

always @* begin
  case(code[2:0])
    3'b000 : sn = 1'b1;
    3'b001 : sn = 1'b1;
    3'b010 : sn = 1'b1; 
    3'b011 : sn = 1'b1;
    3'b100 : sn = 1'b0;
    3'b101 : sn = 1'b0;
    3'b110 : sn = 1'b0;
    3'b111 : sn = 1'b1;
  endcase
end

always @(code[2:0]) 
begin
  case(code[2:0])
    3'b000 : h[1:0] = 2'b00;
    3'b001 : h[1:0] = 2'b00;
    3'b010 : h[1:0] = 2'b00;
    3'b011 : h[1:0] = 2'b00;
    3'b100 : h[1:0] = 2'b01;
    3'b101 : h[1:0] = 2'b01;
    3'b110 : h[1:0] = 2'b01;
    3'b111 : h[1:0] = 2'b00;
    default: h[1:0] = {2{1'bx}};
  endcase
end

endmodule
module compressor_32(a,b,c,s,ca);
parameter B_SIZE = 8;
input  [B_SIZE-1:0] a;
input  [B_SIZE-1:0] b;
input  [B_SIZE-1:0] c;
output [B_SIZE-1:0] s;
output [B_SIZE-1:0] ca;

wire [B_SIZE-1:0] s;
wire [B_SIZE-1:0]ca;

assign s[B_SIZE-1:0]  = a[B_SIZE-1:0]^b[B_SIZE-1:0]^c[B_SIZE-1:0];
assign ca[B_SIZE-1:0] = (a[B_SIZE-1:0]&b[B_SIZE-1:0])
                      | (c[B_SIZE-1:0]&b[B_SIZE-1:0])
                      | (a[B_SIZE-1:0]&c[B_SIZE-1:0]);

//reg   [B_SIZE-1:0]s,ca;
//integer i;
//always @(a[B_SIZE-1:0]
//      or b[B_SIZE-1:0]
//      or c[B_SIZE-1:0]) 
//begin
//  for(i= 0;i<B_SIZE;i=i+1) begin
//    {ca[i],s[i]} =  a[i] + b[i] +  c[i];
//  end
//end
endmodule
module ct_fadd_onehot_sel_h(
  data_in,
  onehot,
  result
);

// &Ports; @23
input   [11:0]  data_in; 
input   [11:0]  onehot;  
output  [11:0]  result;  

// &Regs; @24
reg     [11:0]  result_h; 

// &Wires; @25
wire    [11:0]  data_in; 
wire    [11:0]  onehot;  
wire    [11:0]  result;  


// &Force("bus","data_in",11,0); @27
// &CombBeg; @28
always @( onehot[11:0]
       or data_in[11:0])
begin
case(onehot[11:0])
  12'h800 : result_h[11:0] = data_in[11:0];
  12'h400 : result_h[11:0] = {data_in[10:0],1'b0};
  12'h200 : result_h[11:0] = {data_in[9:0],2'b0};
  12'h100 : result_h[11:0] = {data_in[8:0],2'b0,1'b0};
  12'h080 : result_h[11:0] = {data_in[7:0],2'b0,2'b0};
  12'h040 : result_h[11:0] = {data_in[6:0],2'b0,3'b0};
  12'h020 : result_h[11:0] = {data_in[5:0],2'b0,4'b0};
  12'h010 : result_h[11:0] = {data_in[4:0],2'b0,5'b0};
  12'h008 : result_h[11:0] = {data_in[3:0],2'b0,6'b0};
  12'h004 : result_h[11:0] = {data_in[2:0],2'b0,7'b0};
  12'h002 : result_h[11:0] = {data_in[1:0],2'b0,8'b0};
  12'h001 : result_h[11:0] = {data_in[0],2'b0,9'b0};
  12'h000 : result_h[11:0] = 12'b0;
  default               : result_h[11:0] = {12{1'bx}};
endcase
// &CombEnd; @45
end
assign result[11:0] = result_h[11:0];

// &ModuleEnd; @48
endmodule
module ct_vfalu_dp_pipe6(
  dp_vfalu_ex1_pipex_sel,
  fadd_ereg_ex3_forward_r_vld,
  fadd_ereg_ex3_result,
  fadd_forward_r_vld,
  fadd_forward_result,
  fadd_mfvr_cmp_result,
  fspu_forward_r_vld,
  fspu_forward_result,
  fspu_mfvr_data,
  pipex_dp_ex1_vfalu_mfvr_data,
  pipex_dp_ex3_vfalu_ereg_data,
  pipex_dp_ex3_vfalu_freg_data
);

// &Ports; @23
input   [2 :0]  dp_vfalu_ex1_pipex_sel;      
input           fadd_ereg_ex3_forward_r_vld; 
input   [4 :0]  fadd_ereg_ex3_result;        
input           fadd_forward_r_vld;          
input   [63:0]  fadd_forward_result;         
input   [63:0]  fadd_mfvr_cmp_result;        
input           fspu_forward_r_vld;          
input   [63:0]  fspu_forward_result;         
input   [63:0]  fspu_mfvr_data;              
output  [63:0]  pipex_dp_ex1_vfalu_mfvr_data; 
output  [4 :0]  pipex_dp_ex3_vfalu_ereg_data; 
output  [63:0]  pipex_dp_ex3_vfalu_freg_data; 

// &Regs; @24
reg     [63:0]  pipex_dp_ex3_vfalu_freg_data; 

// &Wires; @25
wire    [2 :0]  dp_vfalu_ex1_pipex_sel;      
wire            fadd_ereg_ex3_forward_r_vld; 
wire    [4 :0]  fadd_ereg_ex3_result;        
wire            fadd_forward_r_vld;          
wire    [63:0]  fadd_forward_result;         
wire    [63:0]  fadd_mfvr_cmp_result;        
wire            fspu_forward_r_vld;          
wire    [63:0]  fspu_forward_result;         
wire    [63:0]  fspu_mfvr_data;              
wire    [63:0]  pipex_dp_ex1_vfalu_mfvr_data; 
wire    [4 :0]  pipex_dp_ex3_vfalu_ereg_data; 


//assign pipex_dp_ex3_vfalu_expt_vec[4:0]    = 5'd30;
// &Force("output","pipex_dp_ex3_vfalu_ereg_data"); @28
assign pipex_dp_ex3_vfalu_ereg_data[4:0]   = {5{fadd_ereg_ex3_forward_r_vld}} & fadd_ereg_ex3_result[4:0];
assign pipex_dp_ex1_vfalu_mfvr_data[63:0]  = {64{dp_vfalu_ex1_pipex_sel[1]}} & fadd_mfvr_cmp_result[63:0] |
                                             {64{dp_vfalu_ex1_pipex_sel[0]}} & fspu_mfvr_data[63:0];
// &Force("bus","dp_vfalu_ex1_pipex_sel",2,0);                                           @32
// &CombBeg; @34
// &CombEnd; @40
// &CombBeg; @42
// &CombEnd; @48
// &CombBeg; @56
always @( fspu_forward_result[63:0]
       or fspu_forward_r_vld
       or fadd_forward_r_vld
       or fadd_forward_result[63:0])
begin
case({fadd_forward_r_vld,fspu_forward_r_vld})
  2'b10   : pipex_dp_ex3_vfalu_freg_data[63:0] = fadd_forward_result[63:0];
  2'b01   : pipex_dp_ex3_vfalu_freg_data[63:0] = fspu_forward_result[63:0];
  default : pipex_dp_ex3_vfalu_freg_data[63:0] = {64{1'bx}};
endcase
// &CombEnd;   @62
end

// &ModuleEnd; @65
endmodule
module ct_fcnvt_dtoh_sh(
  dtos_sh_cnt,
  dtos_sh_f_v,
  dtos_sh_f_x,
  dtos_sh_src
);

// &Ports; @17
input   [10:0]  dtos_sh_cnt; 
input   [51:0]  dtos_sh_src; 
output  [10:0]  dtos_sh_f_v; 
output  [53:0]  dtos_sh_f_x; 

// &Regs; @18
reg     [10:0]  dtos_sh_f_v; 
reg     [53:0]  dtos_sh_f_x; 

// &Wires; @19
wire    [10:0]  dtos_sh_cnt; 
wire    [51:0]  dtos_sh_src; 



// &CombBeg; @22
always @( dtos_sh_cnt[10:0]
       or dtos_sh_src[51:0])
begin
case(dtos_sh_cnt[10:0])
  11'h3f0: begin //-15
  dtos_sh_f_v[10:0] = {2'b1,dtos_sh_src[51:43]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[42:0],11'b0};
  end
  11'h3ef: begin //-16
  dtos_sh_f_v[10:0] = {3'b1,dtos_sh_src[51:44]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[43:0],10'b0};
  end
  11'h3ee: begin //-17
  dtos_sh_f_v[10:0] = {4'b1,dtos_sh_src[51:45]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[44:0],9'b0};
  end
  11'h3ed: begin //-18
  dtos_sh_f_v[10:0] = {5'b1,dtos_sh_src[51:46]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[45:0],8'b0};
  end
  11'h3ec: begin //-19
  dtos_sh_f_v[10:0] = {6'b1,dtos_sh_src[51:47]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[46:0],7'b0};
  end
  11'h3eb: begin //-20
  dtos_sh_f_v[10:0] = {7'b1,dtos_sh_src[51:48]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[47:0],6'b0};
  end
  11'h3ea: begin //-21
  dtos_sh_f_v[10:0] = {8'b1,dtos_sh_src[51:49]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[48:0],5'b0};
  end
  11'h3e9: begin //-22
  dtos_sh_f_v[10:0] = {9'b1,dtos_sh_src[51:50]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[49:0],4'b0};
  end
  11'h3e8: begin //-135
  dtos_sh_f_v[10:0] = {10'b1,dtos_sh_src[51]};
  dtos_sh_f_x[53:0] = {dtos_sh_src[50:0],3'b0};
  end
  11'h3e7: begin //-136
  dtos_sh_f_v[10:0] = {11'b1};
  dtos_sh_f_x[53:0] = {dtos_sh_src[51:0],2'b0};
  end
  11'h3e6: begin //-137
  dtos_sh_f_v[10:0] = 11'b0;
  dtos_sh_f_x[53:0] = {1'b1,dtos_sh_src[51:0],1'b0};
  end
  11'h3e5: begin //-138
  dtos_sh_f_v[10:0] = 11'b0;
  dtos_sh_f_x[53:0] = {2'b1,dtos_sh_src[51:0]};
  end
  default: begin
  dtos_sh_f_v[10:0] = 11'b0;
  dtos_sh_f_x[53:0] = {3'b1,51'b0};
  end
endcase
// &CombEnd; @77
end


// &ModuleEnd; @80
endmodule
module ct_fcnvt_stoh_sh(
  stoh_sh_cnt,
  stoh_sh_f_v,
  stoh_sh_f_x,
  stoh_sh_src
);

// &Ports; @17
input   [7 :0]  stoh_sh_cnt; 
input   [22:0]  stoh_sh_src; 
output  [10:0]  stoh_sh_f_v; 
output  [24:0]  stoh_sh_f_x; 

// &Regs; @18
reg     [10:0]  stoh_sh_f_v; 
reg     [24:0]  stoh_sh_f_x; 

// &Wires; @19
wire    [7 :0]  stoh_sh_cnt; 
wire    [22:0]  stoh_sh_src; 



// &CombBeg; @22
always @( stoh_sh_src[22:0]
       or stoh_sh_cnt[7:0])
begin
case(stoh_sh_cnt[7:0])
  8'h70: begin //-15
  stoh_sh_f_v[10:0] = {2'b1,stoh_sh_src[22:14]};
  stoh_sh_f_x[24:0] = {stoh_sh_src[13:0],11'b0};
  end
  8'h6f: begin //-16
  stoh_sh_f_v[10:0] = {3'b1,stoh_sh_src[22:15]};
  stoh_sh_f_x[24:0] = {stoh_sh_src[14:0],10'b0};
  end
  8'h6e: begin //-17
  stoh_sh_f_v[10:0] = {4'b1,stoh_sh_src[22:16]};
  stoh_sh_f_x[24:0] = {stoh_sh_src[15:0],9'b0};
  end
  8'h6d: begin //-18
  stoh_sh_f_v[10:0] = {5'b1,stoh_sh_src[22:17]};
  stoh_sh_f_x[24:0] = {stoh_sh_src[16:0],8'b0};
  end
  8'h6c: begin //-19
  stoh_sh_f_v[10:0] = {6'b1,stoh_sh_src[22:18]};
  stoh_sh_f_x[24:0] = {stoh_sh_src[17:0],7'b0};
  end
  8'h6b: begin //-20
  stoh_sh_f_v[10:0] = {7'b1,stoh_sh_src[22:19]};
  stoh_sh_f_x[24:0] = {stoh_sh_src[18:0],6'b0};
  end
  8'h6a: begin //-21
  stoh_sh_f_v[10:0] = {8'b1,stoh_sh_src[22:20]};
  stoh_sh_f_x[24:0] = {stoh_sh_src[19:0],5'b0};
  end
  8'h69: begin //-22
  stoh_sh_f_v[10:0] = {9'b1,stoh_sh_src[22:21]};
  stoh_sh_f_x[24:0] = {stoh_sh_src[20:0],4'b0};
  end
  8'h68: begin //-23
  stoh_sh_f_v[10:0] = {10'b1,stoh_sh_src[22]};
  stoh_sh_f_x[24:0] = {stoh_sh_src[21:0],3'b0};
  end
  8'h67: begin //-24
  stoh_sh_f_v[10:0] = {11'b1};
  stoh_sh_f_x[24:0] = {stoh_sh_src[22:0],2'b0};
  end
  8'h66: begin //-25
  stoh_sh_f_v[10:0] = 11'b0;
  stoh_sh_f_x[24:0] = {1'b1,stoh_sh_src[22:0],1'b0};
  end
  8'h65: begin //-26
  stoh_sh_f_v[10:0] = 11'b0;
  stoh_sh_f_x[24:0] = {2'b1,stoh_sh_src[22:0]};
  end
  default: begin
  stoh_sh_f_v[10:0] = 11'b0;
  stoh_sh_f_x[24:0] = {3'b1,22'b0};
  end
endcase
// &CombEnd; @77
end


// &ModuleEnd; @80
endmodule
module ct_fcnvt_htos_sh(
  htos_sh_cnt,
  htos_sh_f_v,
  htos_sh_src
);

// &Ports; @23
input   [9 :0]  htos_sh_src; 
output  [5 :0]  htos_sh_cnt; 
output  [10:0]  htos_sh_f_v; 

// &Regs; @24
reg     [5 :0]  htos_sh_cnt; 
reg     [10:0]  htos_sh_f_v; 

// &Wires; @25
wire    [9 :0]  htos_sh_src; 


// &CombBeg; @27
always @( htos_sh_src[9:0])
begin
casez(htos_sh_src[9:0])
  10'b1?????????: begin
    htos_sh_f_v[10:0] = {htos_sh_src[9:0],1'b0};
    htos_sh_cnt[5:0]  = 6'h31; //-15:
  end
  10'b01????????: begin
    htos_sh_f_v[10:0] = {htos_sh_src[8:0],2'b0};
    htos_sh_cnt[5:0]  = 6'h30; //-16
  end
  10'b001???????: begin
    htos_sh_f_v[10:0] = {htos_sh_src[7:0],3'b0};
    htos_sh_cnt[5:0]  = 6'h2f; //-17
  end
  10'b0001??????: begin
    htos_sh_f_v[10:0] = {htos_sh_src[6:0],4'b0};
    htos_sh_cnt[5:0]  = 6'h2e; //-18
  end
  10'b00001?????: begin
    htos_sh_f_v[10:0] = {htos_sh_src[5:0],5'b0};
    htos_sh_cnt[5:0]  = 6'h2d; //-19
  end
  10'b000001????: begin
    htos_sh_f_v[10:0] = {htos_sh_src[4:0],6'b0};
    htos_sh_cnt[5:0]  = 6'h2c; //-20
  end
  10'b0000001???: begin
    htos_sh_f_v[10:0] = {htos_sh_src[3:0],7'b0};
    htos_sh_cnt[5:0]  = 6'h2b; //-9
  end
  10'b00000001??: begin
    htos_sh_f_v[10:0] = {htos_sh_src[2:0],8'b0};
    htos_sh_cnt[5:0]  = 6'h2a; //-155
  end
  10'b000000001?: begin
    htos_sh_f_v[10:0] = {htos_sh_src[1:0],9'b0};
    htos_sh_cnt[5:0]  = 6'h29; //-155
  end
  10'b0000000001: begin
    htos_sh_f_v[10:0] = {htos_sh_src[0],10'b0};
    htos_sh_cnt[5:0]  = 6'h28; //-156
  end
  default: begin
    htos_sh_f_v[10:0] = 11'b0;
    htos_sh_cnt[5:0]  = 6'h0;
  end
endcase
// &CombEnd; @74
end


// &ModuleEnd; @77
endmodule
module ct_ifu_bht_sel_array(
  bht_sel_array_cen_b,
  bht_sel_array_clk_en,
  bht_sel_array_din,
  bht_sel_array_gwen,
  bht_sel_array_index,
  bht_sel_bwen,
  bht_sel_data_out,
  cp0_ifu_icg_en,
  cp0_yy_clk_en,
  forever_cpuclk,
  pad_yy_icg_scan_en
);

// &Ports; @23
input           bht_sel_array_cen_b; 
input           bht_sel_array_clk_en; 
input   [15:0]  bht_sel_array_din;   
input           bht_sel_array_gwen;  
input   [6 :0]  bht_sel_array_index; 
input   [15:0]  bht_sel_bwen;        
input           cp0_ifu_icg_en;      
input           cp0_yy_clk_en;       
input           forever_cpuclk;      
input           pad_yy_icg_scan_en;  
output  [15:0]  bht_sel_data_out;    

// &Regs; @24

// &Wires; @25
wire            bht_sel_array_cen_b; 
wire            bht_sel_array_clk_en; 
wire    [15:0]  bht_sel_array_din;   
wire            bht_sel_array_gwen;  
wire    [6 :0]  bht_sel_array_index; 
wire    [15:0]  bht_sel_bwen;        
wire            bht_sel_clk;         
wire    [15:0]  bht_sel_data_out;    
wire            bht_sel_en;          
wire            cp0_ifu_icg_en;      
wire            cp0_yy_clk_en;       
wire            forever_cpuclk;      
wire            pad_yy_icg_scan_en;  


//Gate Clk
// &Instance("gated_clk_cell", "x_bht_sel_clk"); @28
gated_clk_cell  x_bht_sel_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (bht_sel_clk       ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (bht_sel_en        ),
  .module_en          (cp0_ifu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);

// &Connect(.clk_in(forever_cpuclk), @29
//          .external_en(1'b0), @30
//          .global_en(cp0_yy_clk_en), @31
//          .module_en(cp0_ifu_icg_en), @32
//          .local_en(bht_sel_en), @33
//          .clk_out(bht_sel_clk) @34
//         ); @35

assign bht_sel_en = bht_sel_array_clk_en;

//Instance Logic
// &Instance("ct_spsram_128x16", "x_ct_spsram_128x16"); @40
ct_spsram_128x16  x_ct_spsram_128x16 (
  .A                   (bht_sel_array_index),
  .CEN                 (bht_sel_array_cen_b),
  .CLK                 (bht_sel_clk        ),
  .D                   (bht_sel_array_din  ),
  .GWEN                (bht_sel_array_gwen ),
  .Q                   (bht_sel_data_out   ),
  .WEN                 (bht_sel_bwen       )
);

// &Connect( @41
//          .CLK    (bht_sel_clk        ), @42
//          .Q      (bht_sel_data_out   ), @43
//          .CEN    (bht_sel_array_cen_b), @44
//          .WEN    (bht_sel_bwen       ), @45
//          .D      (bht_sel_array_din  ), @46
//          .A      (bht_sel_array_index), @47
//          .GWEN   (bht_sel_array_gwen ) @48
//        ); @49

// &ModuleEnd; @51
endmodule
module ct_ifu_bht_pre_array(
  bht_pre_array_clk_en,
  bht_pre_data_out,
  bht_pred_array_cen_b,
  bht_pred_array_din,
  bht_pred_array_gwen,
  bht_pred_array_index,
  bht_pred_bwen,
  cp0_ifu_icg_en,
  cp0_yy_clk_en,
  forever_cpuclk,
  pad_yy_icg_scan_en
);

// &Ports; @23
input           bht_pre_array_clk_en; 
input           bht_pred_array_cen_b; 
input   [63:0]  bht_pred_array_din;  
input           bht_pred_array_gwen; 
input   [9 :0]  bht_pred_array_index; 
input   [63:0]  bht_pred_bwen;       
input           cp0_ifu_icg_en;      
input           cp0_yy_clk_en;       
input           forever_cpuclk;      
input           pad_yy_icg_scan_en;  
output  [63:0]  bht_pre_data_out;    

// &Regs; @24

// &Wires; @25
wire            bht_pre_array_clk_en; 
wire            bht_pre_clk;         
wire    [63:0]  bht_pre_data_out;    
wire            bht_pre_en;          
wire            bht_pred_array_cen_b; 
wire    [63:0]  bht_pred_array_din;  
wire            bht_pred_array_gwen; 
wire    [9 :0]  bht_pred_array_index; 
wire    [63:0]  bht_pred_bwen;       
wire            cp0_ifu_icg_en;      
wire            cp0_yy_clk_en;       
wire            forever_cpuclk;      
wire            pad_yy_icg_scan_en;  


//Gate Clk
// &Instance("gated_clk_cell", "x_bht_pre_clk"); @28
gated_clk_cell  x_bht_pre_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (bht_pre_clk       ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (bht_pre_en        ),
  .module_en          (cp0_ifu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);

// &Connect(.clk_in(forever_cpuclk), @29
//          .external_en(1'b0), @30
//          .global_en(cp0_yy_clk_en), @31
//          .module_en(cp0_ifu_icg_en), @32
//          .local_en(bht_pre_en), @33
//          .clk_out(bht_pre_clk) @34
//         ); @35

assign bht_pre_en = bht_pre_array_clk_en;

//Instance Logic
// &Instance("ct_spsram_1024x64", "x_ct_spsram_1024x64"); @40
ct_spsram_1024x64  x_ct_spsram_1024x64 (
  .A                    (bht_pred_array_index),
  .CEN                  (bht_pred_array_cen_b),
  .CLK                  (bht_pre_clk         ),
  .D                    (bht_pred_array_din  ),
  .GWEN                 (bht_pred_array_gwen ),
  .Q                    (bht_pre_data_out    ),
  .WEN                  (bht_pred_bwen       )
);

// &Connect( @41
//          .CLK    (bht_pre_clk         ), @42
//          .Q      (bht_pre_data_out    ), @43
//          .CEN    (bht_pred_array_cen_b), @44
//          .WEN    (bht_pred_bwen       ), @45
//          .D      (bht_pred_array_din  ), @46
//          .A      (bht_pred_array_index), @47
//          .GWEN   (bht_pred_array_gwen ) @48
//        ); @49

// &ModuleEnd; @51
endmodule
module ct_ifu_ind_btb_array(
  cp0_ifu_icg_en,
  cp0_yy_clk_en,
  forever_cpuclk,
  ind_btb_cen_b,
  ind_btb_clk_en,
  ind_btb_data_in,
  ind_btb_dout,
  ind_btb_index,
  ind_btb_wen_b,
  pad_yy_icg_scan_en
);

// &Ports; @23
input           cp0_ifu_icg_en;    
input           cp0_yy_clk_en;     
input           forever_cpuclk;    
input           ind_btb_cen_b;     
input           ind_btb_clk_en;    
input   [22:0]  ind_btb_data_in;   
input   [7 :0]  ind_btb_index;     
input           ind_btb_wen_b;     
input           pad_yy_icg_scan_en; 
output  [22:0]  ind_btb_dout;      

// &Regs; @24

// &Wires; @25
wire            cp0_ifu_icg_en;    
wire            cp0_yy_clk_en;     
wire            forever_cpuclk;    
wire    [22:0]  ind_btb_bwen;      
wire            ind_btb_cen_b;     
wire            ind_btb_clk;       
wire            ind_btb_clk_en;    
wire    [22:0]  ind_btb_data_in;   
wire    [22:0]  ind_btb_dout;      
wire    [7 :0]  ind_btb_index;     
wire            ind_btb_local_en;  
wire            ind_btb_wen_b;     
wire            pad_yy_icg_scan_en; 


//Gate Clk
// &Instance("gated_clk_cell", "x_ind_btb_clk"); @28
gated_clk_cell  x_ind_btb_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ind_btb_clk       ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (ind_btb_local_en  ),
  .module_en          (cp0_ifu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);

// &Connect(.clk_in(forever_cpuclk), @29
//          .external_en(1'b0), @30
//          .global_en(cp0_yy_clk_en), @31
//          .module_en(cp0_ifu_icg_en), @32
//          .local_en(ind_btb_local_en), @33
//          .clk_out(ind_btb_clk) @34
//         ); @35

assign ind_btb_local_en   = ind_btb_clk_en;
assign ind_btb_bwen[22:0] = {23{ind_btb_wen_b}};
//Instance Logic
// &Instance("ct_spsram_256x23", "x_ct_spsram_256x23"); @40
ct_spsram_256x23  x_ct_spsram_256x23 (
  .A               (ind_btb_index  ),
  .CEN             (ind_btb_cen_b  ),
  .CLK             (ind_btb_clk    ),
  .D               (ind_btb_data_in),
  .GWEN            (ind_btb_wen_b  ),
  .Q               (ind_btb_dout   ),
  .WEN             (ind_btb_bwen   )
);

// &Connect( @41
//          .CLK    (ind_btb_clk    ), @42
//          .Q      (ind_btb_dout   ), @43
//          .CEN    (ind_btb_cen_b  ), @44
//          .WEN    (ind_btb_bwen   ), @45
//          .D      (ind_btb_data_in), @46
//          .A      (ind_btb_index  ), @47
//          .GWEN   (ind_btb_wen_b  ) @48
//        ); @49

// &ModuleEnd; @51
endmodule
module ct_rmu_top_dummy(
  apb_clk,
  apbrst_b,
  penable,
  perr_rmr,
  prdata_rmr,
  pready_rmr,
  psel_rmr
);

// &Ports; @3
input           apb_clk;   
input           apbrst_b;  
input           penable;   
input           psel_rmr;  
output          perr_rmr;  
output  [31:0]  prdata_rmr; 
output          pready_rmr; 

// &Regs; @4
reg             perr_rmr;  
reg             pready_rmr; 

// &Wires; @5
wire            acc_err;   
wire            apb_clk;   
wire            apbrst_b;  
wire    [31:0]  data_out;  
wire            penable;   
wire    [31:0]  prdata_rmr; 
wire            priv_err;  
wire            psel_rmr;  


always @(posedge apb_clk or negedge apbrst_b)
begin
  if(~apbrst_b)
    pready_rmr <= 1'b0;
  else if (psel_rmr & !penable)
    pready_rmr <= 1'b1;
  else 
    pready_rmr <= 1'b0;
end

always @(posedge apb_clk or negedge apbrst_b)
begin
  if(~apbrst_b)
    perr_rmr <= 1'b0;
  else if (psel_rmr & !penable & (acc_err | priv_err))
    perr_rmr <= 1'b1;
  else
    perr_rmr <= 1'b0;
end

assign prdata_rmr[31:0] = data_out[31:0];

assign acc_err  = 1'b1;
assign priv_err = 1'b1;

assign data_out[31:0] = 32'b0;

// &ModuleEnd; @34
endmodule
module ct_prio(
  clk,
  rst_b,
  valid,
  clr,
  sel
);
parameter NUM =2;

input            clk;
input            rst_b;
input  [NUM-1:0] valid;
input            clr;
output [NUM-1:0] sel;

reg    [NUM-1:0] prio [NUM-1:0];
reg    [NUM-1:0] unused [NUM-1:0];
wire   [NUM-1:0] sel;
wire   [NUM-1:0] clr_bus;

assign clr_bus[NUM-1:0] = {NUM{clr}} & sel[NUM-1:0];

genvar i;
generate
for(i=0; i<NUM; i=i+1) begin:PRIO_MATRIX_GEN
always@(posedge clk or negedge rst_b)
begin
  if (!rst_b)
    {prio[i][NUM-1:0], unused[i][NUM-1:0]} <= {{NUM{1'b0}}, {NUM{1'b1}}} << i;
  else if(|clr_bus[NUM-1:0]) begin
    prio[i][NUM-1:0] <= (clr_bus[NUM-1:0] == ({{(NUM-1){1'b0}},1'b1}<<i)) 
                      ? ~clr_bus[NUM-1:0] 
                      : prio[i][NUM-1:0] &~clr_bus[NUM-1:0];
  end
end
end
endgenerate

generate
for(i=0; i<NUM; i=i+1) begin: SEL_GEN
assign sel[i] = valid[i] && !(|(valid[NUM-1:0] & prio[i][NUM-1:0]));
end
endgenerate

endmodule
module ct_piu_other_io_dummy(
  l2cif_piu_read_data_vld,
  perr_l2pmp_x,
  piu_l2cif_read_data,
  piu_l2cif_read_data_ecc,
  piu_l2cif_read_index,
  piu_l2cif_read_req,
  piu_l2cif_read_tag,
  piu_l2cif_read_tag_ecc,
  piu_l2cif_read_way,
  piu_regs_op,
  piu_regs_sel,
  piu_regs_wdata,
  piu_xx_regs_no_op,
  pready_l2pmp_x,
  psel_l2pmp_x,
  regs_piu_cmplt,
  x_prdata_l2pmp
);

// &Ports; @2
input           l2cif_piu_read_data_vld; 
input           psel_l2pmp_x;           
input           regs_piu_cmplt;         
output          perr_l2pmp_x;           
output          piu_l2cif_read_data;    
output          piu_l2cif_read_data_ecc; 
output  [20:0]  piu_l2cif_read_index;   
output          piu_l2cif_read_req;     
output          piu_l2cif_read_tag;     
output          piu_l2cif_read_tag_ecc; 
output  [3 :0]  piu_l2cif_read_way;     
output  [15:0]  piu_regs_op;            
output          piu_regs_sel;           
output  [63:0]  piu_regs_wdata;         
output          piu_xx_regs_no_op;      
output          pready_l2pmp_x;         
output  [31:0]  x_prdata_l2pmp;         

// &Regs; @3

// &Wires; @4
wire            perr_l2pmp_x;           
wire            piu_l2cif_read_data;    
wire            piu_l2cif_read_data_ecc; 
wire    [20:0]  piu_l2cif_read_index;   
wire            piu_l2cif_read_req;     
wire            piu_l2cif_read_tag;     
wire            piu_l2cif_read_tag_ecc; 
wire    [3 :0]  piu_l2cif_read_way;     
wire    [15:0]  piu_regs_op;            
wire            piu_regs_sel;           
wire    [63:0]  piu_regs_wdata;         
wire            piu_xx_regs_no_op;      
wire            pready_l2pmp_x;         
wire    [31:0]  x_prdata_l2pmp;         


assign piu_regs_sel               = 1'b0;
assign piu_regs_op[15:0]          = 16'b0;
assign piu_regs_wdata[63:0]       = 64'b0;
assign piu_xx_regs_no_op          = 1'b1;

assign piu_l2cif_read_req         = 1'b0; 
assign piu_l2cif_read_tag         = 1'b0; 
assign piu_l2cif_read_data        = 1'b0; 
assign piu_l2cif_read_tag_ecc     = 1'b0;
assign piu_l2cif_read_data_ecc    = 1'b0;
assign piu_l2cif_read_way[3:0]    = 4'b0;
assign piu_l2cif_read_index[20:0] = 21'b0;

// &Force("input", "regs_piu_cmplt"); @19
// &Force("input", "l2cif_piu_read_data_vld"); @20

assign perr_l2pmp_x         = 1'b0;
assign pready_l2pmp_x       = 1'b1;
assign x_prdata_l2pmp[31:0] = 32'b0;

// &Force("input", "psel_l2pmp_x"); @26

// &ModuleEnd; @28
endmodule
module ct_ebiu_lowpower(
  clk_en,
  cpurst_b,
  ebiu_pad_cactive,
  ebiu_pad_csysack,
  ebiu_read_channel_no_op,
  ebiu_snoop_channel_no_op,
  ebiu_write_channel_no_op,
  ebiu_xx_no_op,
  forever_cpuclk,
  pad_ebiu_csysreq
);

// &Ports; @24
input        clk_en;                  
input        cpurst_b;                
input        ebiu_read_channel_no_op; 
input        ebiu_snoop_channel_no_op; 
input        ebiu_write_channel_no_op; 
input        forever_cpuclk;          
input        pad_ebiu_csysreq;        
output       ebiu_pad_cactive;        
output       ebiu_pad_csysack;        
output       ebiu_xx_no_op;           

// &Regs; @25
reg          ebiu_pad_csysack;        

// &Wires; @26
wire         clk_en;                  
wire         cpurst_b;                
wire         ebiu_pad_cactive;        
wire         ebiu_read_channel_no_op; 
wire         ebiu_snoop_channel_no_op; 
wire         ebiu_write_channel_no_op; 
wire         ebiu_xx_no_op;           
wire         forever_cpuclk;          
wire         pad_ebiu_csysreq;        


//==========================================================
//  EBIU no_op
//==========================================================
assign ebiu_xx_no_op = ebiu_write_channel_no_op & ebiu_snoop_channel_no_op & ebiu_read_channel_no_op;

//==========================================================
// low power handshake with interconnect clock controller 
//==========================================================
assign ebiu_pad_cactive = 1'b1;

always@(posedge forever_cpuclk or negedge cpurst_b)
begin
  if(~cpurst_b)
    ebiu_pad_csysack <= 1'b1;
  else if(clk_en)
  begin
    if(~pad_ebiu_csysreq)
      ebiu_pad_csysack <= 1'b0;
    else
      ebiu_pad_csysack <= 1'b1;
  end
end


// &ModuleEnd; @52
endmodule
module ct_ciu_snb_dp_sel_8(
  entry16_age_vect,
  entry17_age_vect,
  entry18_age_vect,
  entry19_age_vect,
  entry20_age_vect,
  entry21_age_vect,
  entry22_age_vect,
  entry23_age_vect,
  req_vld,
  sel
);

// &Ports; @19
input   [23:0]  entry16_age_vect; 
input   [23:0]  entry17_age_vect; 
input   [23:0]  entry18_age_vect; 
input   [23:0]  entry19_age_vect; 
input   [23:0]  entry20_age_vect; 
input   [23:0]  entry21_age_vect; 
input   [23:0]  entry22_age_vect; 
input   [23:0]  entry23_age_vect; 
input   [7 :0]  req_vld;         
output  [7 :0]  sel;             

// &Regs; @20

// &Wires; @21
wire    [23:0]  entry16_age_vect; 
wire    [23:0]  entry17_age_vect; 
wire    [23:0]  entry18_age_vect; 
wire    [23:0]  entry19_age_vect; 
wire    [23:0]  entry20_age_vect; 
wire    [23:0]  entry21_age_vect; 
wire    [23:0]  entry22_age_vect; 
wire    [23:0]  entry23_age_vect; 
wire    [7 :0]  req_vld;         
wire    [7 :0]  sel;             


// &Force("bus", "entry16_age_vect", 23,0); @23
// &Force("bus", "entry17_age_vect", 23,0); @24
// &Force("bus", "entry18_age_vect", 23,0); @25
// &Force("bus", "entry19_age_vect", 23,0); @26
// &Force("bus", "entry20_age_vect", 23,0); @27
// &Force("bus", "entry21_age_vect", 23,0); @28
// &Force("bus", "entry22_age_vect", 23,0); @29
// &Force("bus", "entry23_age_vect", 23,0); @30

parameter DEPTH = 8;

assign sel[0] = req_vld[0] && !(|(req_vld[DEPTH-1:0] & entry16_age_vect[23:16]));
assign sel[1] = req_vld[1] && !(|(req_vld[DEPTH-1:0] & entry17_age_vect[23:16]));
assign sel[2] = req_vld[2] && !(|(req_vld[DEPTH-1:0] & entry18_age_vect[23:16]));
assign sel[3] = req_vld[3] && !(|(req_vld[DEPTH-1:0] & entry19_age_vect[23:16]));
assign sel[4] = req_vld[4] && !(|(req_vld[DEPTH-1:0] & entry20_age_vect[23:16]));
assign sel[5] = req_vld[5] && !(|(req_vld[DEPTH-1:0] & entry21_age_vect[23:16]));
assign sel[6] = req_vld[6] && !(|(req_vld[DEPTH-1:0] & entry22_age_vect[23:16]));
assign sel[7] = req_vld[7] && !(|(req_vld[DEPTH-1:0] & entry23_age_vect[23:16]));

// &ModuleEnd; @43
endmodule
module ct_ciu_ncq_gm(
  ciu_icg_en,
  cpurst_b,
  forever_cpuclk,
  gm_aw_req,
  gm_ctrl_clk,
  gm_set_vld_gate_x,
  gm_set_vld_x,
  gm_success_x,
  gm_vld_x,
  pad_yy_icg_scan_en,
  raq_pop_bus,
  waq_pop_bus,
  waq_pop_en
);

// &Ports; @24
input           ciu_icg_en;        
input           cpurst_b;          
input           forever_cpuclk;    
input           gm_aw_req;         
input           gm_ctrl_clk;       
input           gm_set_vld_gate_x; 
input           gm_set_vld_x;      
input           pad_yy_icg_scan_en; 
input   [73:0]  raq_pop_bus;       
input   [73:0]  waq_pop_bus;       
input           waq_pop_en;        
output          gm_success_x;      
output          gm_vld_x;          

// &Regs; @25
reg     [73:0]  gm_cont;           
reg             gm_exclusive;      

// &Wires; @26
wire            ciu_icg_en;        
wire            cpurst_b;          
wire            forever_cpuclk;    
wire            gm_aw_req;         
wire            gm_clk;            
wire            gm_clr_vld;        
wire            gm_ctrl_clk;       
wire            gm_set_vld_gate_x; 
wire            gm_set_vld_x;      
wire            gm_success_x;      
wire            gm_vld_x;          
wire            pad_yy_icg_scan_en; 
wire    [73:0]  raq_pop_bus;       
wire    [73:0]  waq_pop_bus;       
wire            waq_pop_en;        


parameter ADDRW   = 40;
parameter LOCK    = 10;
parameter ADDR_0  = 34;
parameter ADDRH   = 73; //ADDRW -1 + ADDR_0;
parameter GMWIDTH = 74; //ADDRW + ADDR_0;

assign gm_clr_vld = gm_aw_req && waq_pop_en &&
                   (waq_pop_bus[ADDRH:ADDR_0] == gm_cont[ADDRH:ADDR_0]);

assign gm_success_x = gm_aw_req && waq_pop_bus[LOCK] &&
                      gm_exclusive &&
                     (gm_cont[GMWIDTH-1:0] == waq_pop_bus[GMWIDTH-1:0]);
                   

always @(posedge gm_ctrl_clk or negedge cpurst_b)
begin
  if (!cpurst_b)
    gm_exclusive <= 1'b0;
  else if (gm_clr_vld)
    gm_exclusive <= 1'b0;
  else if (gm_set_vld_x)
    gm_exclusive <= 1'b1;
end

assign gm_vld_x = gm_exclusive;

always @(posedge gm_clk or negedge cpurst_b)
begin
  if (!cpurst_b)
    gm_cont[GMWIDTH-1:0] <= {GMWIDTH{1'b0}};
  else if (gm_set_vld_x)
    gm_cont[GMWIDTH-1:0] <= raq_pop_bus[GMWIDTH-1:0];
end

// &Instance("gated_clk_cell", "x_ncq_gm_gated_clk"); @62
gated_clk_cell  x_ncq_gm_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (gm_clk            ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (gm_set_vld_gate_x ),
  .module_en          (ciu_icg_en        ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);

// &Connect(.clk_in      (forever_cpuclk), @63
//          .external_en (1'b0), @64
//          .global_en   (1'b1), @65
//          .module_en (ciu_icg_en       ), @66
//          .local_en    (gm_set_vld_gate_x), @67
//          .clk_out     (gm_clk)); @68

// &ModuleEnd; @70
endmodule
module ct_idu_is_aiq_lch_rdy_2(
  cpurst_b,
  vld,
  x_create_dp_en,
  x_create_entry,
  x_create_lch_rdy,
  x_read_lch_rdy,
  y_clk,
  y_create0_dp_en,
  y_create0_src_match,
  y_create1_dp_en,
  y_create1_src_match
);

// &Ports; @25
input          cpurst_b;           
input          vld;                
input          x_create_dp_en;     
input   [1:0]  x_create_entry;     
input   [1:0]  x_create_lch_rdy;   
input          y_clk;              
input          y_create0_dp_en;    
input   [1:0]  y_create0_src_match; 
input          y_create1_dp_en;    
input   [1:0]  y_create1_src_match; 
output  [1:0]  x_read_lch_rdy;     

// &Regs; @26
reg     [1:0]  lch_rdy;            
reg     [1:0]  x_read_lch_rdy;     

// &Wires; @27
wire           cpurst_b;           
wire           lch_rdy_create0_en; 
wire           lch_rdy_create1_en; 
wire           vld;                
wire           x_create_dp_en;     
wire    [1:0]  x_create_entry;     
wire    [1:0]  x_create_lch_rdy;   
wire           y_clk;              
wire           y_create0_dp_en;    
wire    [1:0]  y_create0_src_match; 
wire           y_create1_dp_en;    
wire    [1:0]  y_create1_src_match; 



parameter WIDTH = 2;
//==========================================================
//                     Preg Register
//==========================================================
assign lch_rdy_create0_en = y_create0_dp_en && x_create_entry[0];
assign lch_rdy_create1_en = y_create1_dp_en && x_create_entry[1];

always @(posedge y_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    lch_rdy[WIDTH-1:0] <= {WIDTH{1'b0}};
  else if(x_create_dp_en)
    lch_rdy[WIDTH-1:0] <= x_create_lch_rdy[WIDTH-1:0];
  else if(vld && lch_rdy_create0_en)
    lch_rdy[WIDTH-1:0] <= y_create0_src_match[WIDTH-1:0];
  else if(vld && lch_rdy_create1_en)
    lch_rdy[WIDTH-1:0] <= y_create1_src_match[WIDTH-1:0];
  else
    lch_rdy[WIDTH-1:0] <= lch_rdy[WIDTH-1:0];
end

//==========================================================
//                      Read Port
//==========================================================
// &CombBeg; @54
always @( y_create0_src_match[1:0]
       or lch_rdy_create1_en
       or lch_rdy[1:0]
       or lch_rdy_create0_en
       or y_create1_src_match[1:0])
begin
  case({lch_rdy_create1_en,lch_rdy_create0_en})
    2'b01  : x_read_lch_rdy[WIDTH-1:0] = y_create0_src_match[WIDTH-1:0];
    2'b10  : x_read_lch_rdy[WIDTH-1:0] = y_create1_src_match[WIDTH-1:0];
    default: x_read_lch_rdy[WIDTH-1:0] = lch_rdy[WIDTH-1:0];
  endcase
// &CombEnd; @60
end

// &ModuleEnd; @62
endmodule