module M_rv32i_cpu__cpu (
in_mem_rdata,
out_mem_addr,
out_mem_wenable,
out_mem_wdata,
in_run,
out_done,
reset,
out_clock,
clock
);
input  [32-1:0] in_mem_rdata;
output  [12-1:0] out_mem_addr;
output  [4-1:0] out_mem_wenable;
output  [32-1:0] out_mem_wdata;
input in_run;
output out_done;
input reset;
output out_clock;
input clock;
assign out_clock = clock;
wire  [2:0] _w_exec_op;
wire  [4:0] _w_exec_write_rd;
wire  [0:0] _w_exec_no_rd;
wire  [0:0] _w_exec_jump;
wire  [0:0] _w_exec_load;
wire  [0:0] _w_exec_store;
wire signed [31:0] _w_exec_val;
wire  [0:0] _w_exec_storeVal;
wire  [0:0] _w_exec_working;
wire  [31:0] _w_exec_n;
wire  [0:0] _w_exec_storeAddr;
wire  [0:0] _w_exec_intop;
wire signed [31:0] _w_exec_r;
wire signed [31:0] _w_mem_xregsA_rdata;
wire signed [31:0] _w_mem_xregsB_rdata;
reg  [0:0] _t_xregsA_wenable;
reg signed [31:0] _t_xregsA_wdata;
reg  [4:0] _t_xregsA_addr;
reg  [0:0] _t_xregsB_wenable;
reg signed [31:0] _t_xregsB_wdata;
reg  [4:0] _t_xregsB_addr;
reg signed [31:0] _t_loaded;
reg  [4-1:0] _t_mem_wenable;
reg  [32-1:0] _t_mem_wdata;
wire  [11:0] _w_next_pc;
wire  [31:0] _w___block_1_aligned;
wire signed [31:0] _w___block_16_write_back;

reg  [31:0] _d_instr = 0;
reg  [31:0] _q_instr = 0;
reg  [11:0] _d_pc;
reg  [11:0] _q_pc;
reg  [12-1:0] _d_mem_addr;
reg  [12-1:0] _q_mem_addr;
reg  [0:0] _d_exec_trigger,_q_exec_trigger;
reg  [6:0] _d_index,_q_index = 64;
assign out_mem_addr = _d_mem_addr;
assign out_mem_wenable = _t_mem_wenable;
assign out_mem_wdata = _t_mem_wdata;
assign out_done = (_q_index == 64);
M_execute__cpu_exec exec (
.in_instr(_q_instr),
.in_pc(_q_pc),
.in_xa(_w_mem_xregsA_rdata),
.in_xb(_w_mem_xregsB_rdata),
.in_trigger(_d_exec_trigger),
.out_op(_w_exec_op),
.out_write_rd(_w_exec_write_rd),
.out_no_rd(_w_exec_no_rd),
.out_jump(_w_exec_jump),
.out_load(_w_exec_load),
.out_store(_w_exec_store),
.out_val(_w_exec_val),
.out_storeVal(_w_exec_storeVal),
.out_working(_w_exec_working),
.out_n(_w_exec_n),
.out_storeAddr(_w_exec_storeAddr),
.out_intop(_w_exec_intop),
.out_r(_w_exec_r),
.reset(reset),
.clock(clock));

M_rv32i_cpu__cpu_mem_xregsA __mem__xregsA(
.clock(clock),
.in_xregsA_wenable(_t_xregsA_wenable),
.in_xregsA_wdata(_t_xregsA_wdata),
.in_xregsA_addr(_t_xregsA_addr),
.out_xregsA_rdata(_w_mem_xregsA_rdata)
);
M_rv32i_cpu__cpu_mem_xregsB __mem__xregsB(
.clock(clock),
.in_xregsB_wenable(_t_xregsB_wenable),
.in_xregsB_wdata(_t_xregsB_wdata),
.in_xregsB_addr(_t_xregsB_addr),
.out_xregsB_rdata(_w_mem_xregsB_rdata)
);

assign _w_next_pc = _q_pc+1;
assign _w___block_1_aligned = in_mem_rdata>>{_w_exec_n[0+:2],3'b000};
assign _w___block_16_write_back = (_w_exec_jump ? (_w_next_pc<<2):32'b0)|(_w_exec_storeAddr ? _w_exec_n[0+:14]:32'b0)|(_w_exec_storeVal ? _w_exec_val:32'b0)|(_w_exec_load ? _t_loaded:32'b0)|(_w_exec_intop ? _w_exec_r:32'b0);

`ifdef FORMAL
initial begin
assume(reset);
end
assume property($initstate || (in_run || out_done));
`endif
always @* begin
_d_instr = _q_instr;
_d_pc = _q_pc;
_d_mem_addr = _q_mem_addr;
_d_exec_trigger = _q_exec_trigger;
_d_index = _q_index;
_t_xregsA_wdata = 0;
_t_xregsA_addr = 0;
_t_xregsB_wenable = 0;
_t_xregsB_wdata = 0;
_t_xregsB_addr = 0;
// _always_pre
// __block_1
  case (_w_exec_op[0+:2])
  2'b00: begin
// __block_3_case
// __block_4
_t_loaded = {{24{(~_w_exec_op[2+:1])&_w___block_1_aligned[7+:1]}},_w___block_1_aligned[0+:8]};
// __block_5
  end
  2'b01: begin
// __block_6_case
// __block_7
_t_loaded = {{16{(~_w_exec_op[2+:1])&_w___block_1_aligned[15+:1]}},_w___block_1_aligned[0+:16]};
// __block_8
  end
  2'b10: begin
// __block_9_case
// __block_10
_t_loaded = _w___block_1_aligned;
// __block_11
  end
  default: begin
// __block_12_case
// __block_13
_t_loaded = {32{1'bx}};
// __block_14
  end
endcase
// __block_2
_t_mem_wdata = _w_mem_xregsB_rdata<<{_w_exec_n[0+:2],3'b000};
_t_mem_wenable = 4'b0000;
_d_exec_trigger = 0;
_t_xregsA_wenable = 0;
// __block_15
(* parallel_case, full_case *)
case (1'b1)
_q_index[0]: begin
// _top
_d_index = 2;
end
_q_index[1]: begin
// __while__block_18
if (1) begin
// __block_19
// __block_21
_d_instr = in_mem_rdata;
_d_pc = _q_mem_addr;
_d_index = 8;
end else begin
_d_index = 4;
end
end
_q_index[3]: begin
// __block_22
_d_exec_trigger = 1;
_d_index = 16;
end
_q_index[2]: begin
// __block_20
_d_index = 64;
end
_q_index[4]: begin
// __while__block_23
if (1) begin
// __block_24
// __block_26
if (_w_exec_load|_w_exec_store) begin
// __block_27
// __block_29
_d_mem_addr = _w_exec_n>>2;
_t_mem_wenable = ({4{_w_exec_store}}&{{2{_w_exec_op[0+:2]==2'b10}},_w_exec_op[0+:1]|_w_exec_op[1+:1],1'b1})<<_w_exec_n[0+:2];
_d_index = 32;
end else begin
// __block_28
// __block_33
_t_xregsA_wenable = ~_w_exec_no_rd;
_d_mem_addr = _w_exec_jump ? (_w_exec_n>>2):_w_next_pc;
if (_w_exec_working==0) begin
// __block_34
// __block_36
_d_index = 2;
end else begin
// __block_35
_d_index = 16;
end
end
end else begin
_d_index = 2;
end
end
_q_index[5]: begin
// __block_30
_t_xregsA_wenable = ~_w_exec_no_rd;
_d_mem_addr = _w_next_pc;
_d_index = 2;
end
_q_index[6]: begin // end of 
end
default: begin 
_d_index = {3{1'bx}};
`ifdef FORMAL
assume(0);
`endif
 end
endcase
// _always_post
// __block_16
_t_xregsA_wdata = _w___block_16_write_back;
_t_xregsB_wdata = _w___block_16_write_back;
_t_xregsB_wenable = _t_xregsA_wenable;
_t_xregsA_addr = _t_xregsA_wenable ? _w_exec_write_rd:_d_instr[15+:5];
_t_xregsB_addr = _t_xregsA_wenable ? _w_exec_write_rd:_d_instr[20+:5];
// __block_17
end

always @(posedge clock) begin
_q_instr <= _d_instr;
_q_pc <= _d_pc;
_q_mem_addr <= (reset | ~in_run) ? 0 : _d_mem_addr;
_q_index <= reset ? 64 : ( ~in_run ? 1 : _d_index);
_q_exec_trigger <= _d_exec_trigger;
end

endmodule