dakies/OSS_Verilog huggingface dataset:
module ct_idu_is_aiq_lch_rdy_3(
  cpurst_b,
  vld,
  x_create_dp_en,
  x_create_entry,
  x_create_lch_rdy,
  x_read_lch_rdy,
  y_clk,
  y_create0_dp_en,
  y_create0_src_match,
  y_create1_dp_en,
  y_create1_src_match
);

// &Ports; @25
input          cpurst_b;           
input          vld;                
input          x_create_dp_en;     
input   [1:0]  x_create_entry;     
input   [2:0]  x_create_lch_rdy;   
input          y_clk;              
input          y_create0_dp_en;    
input   [2:0]  y_create0_src_match; 
input          y_create1_dp_en;    
input   [2:0]  y_create1_src_match; 
output  [2:0]  x_read_lch_rdy;     

// &Regs; @26
reg     [2:0]  lch_rdy;            
reg     [2:0]  x_read_lch_rdy;     

// &Wires; @27
wire           cpurst_b;           
wire           lch_rdy_create0_en; 
wire           lch_rdy_create1_en; 
wire           vld;                
wire           x_create_dp_en;     
wire    [1:0]  x_create_entry;     
wire    [2:0]  x_create_lch_rdy;   
wire           y_clk;              
wire           y_create0_dp_en;    
wire    [2:0]  y_create0_src_match; 
wire           y_create1_dp_en;    
wire    [2:0]  y_create1_src_match; 



parameter WIDTH = 3;
//==========================================================
//                     Preg Register
//==========================================================
assign lch_rdy_create0_en = y_create0_dp_en && x_create_entry[0];
assign lch_rdy_create1_en = y_create1_dp_en && x_create_entry[1];

always @(posedge y_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    lch_rdy[WIDTH-1:0] <= {WIDTH{1'b0}};
  else if(x_create_dp_en)
    lch_rdy[WIDTH-1:0] <= x_create_lch_rdy[WIDTH-1:0];
  else if(vld && lch_rdy_create0_en)
    lch_rdy[WIDTH-1:0] <= y_create0_src_match[WIDTH-1:0];
  else if(vld && lch_rdy_create1_en)
    lch_rdy[WIDTH-1:0] <= y_create1_src_match[WIDTH-1:0];
  else
    lch_rdy[WIDTH-1:0] <= lch_rdy[WIDTH-1:0];
end

//==========================================================
//                      Read Port
//==========================================================
// &CombBeg; @54
always @( y_create0_src_match[2:0]
       or lch_rdy[2:0]
       or y_create1_src_match[2:0]
       or lch_rdy_create1_en
       or lch_rdy_create0_en)
begin
  case({lch_rdy_create1_en,lch_rdy_create0_en})
    2'b01  : x_read_lch_rdy[WIDTH-1:0] = y_create0_src_match[WIDTH-1:0];
    2'b10  : x_read_lch_rdy[WIDTH-1:0] = y_create1_src_match[WIDTH-1:0];
    default: x_read_lch_rdy[WIDTH-1:0] = lch_rdy[WIDTH-1:0];
  endcase
// &CombEnd; @60
end

// &ModuleEnd; @62
endmodule
module ct_idu_is_aiq_lch_rdy_1(
  cpurst_b,
  vld,
  x_create_dp_en,
  x_create_entry,
  x_create_lch_rdy,
  x_read_lch_rdy,
  y_clk,
  y_create0_dp_en,
  y_create0_src_match,
  y_create1_dp_en,
  y_create1_src_match
);

// &Ports; @25
input          cpurst_b;           
input          vld;                
input          x_create_dp_en;     
input   [1:0]  x_create_entry;     
input          x_create_lch_rdy;   
input          y_clk;              
input          y_create0_dp_en;    
input          y_create0_src_match; 
input          y_create1_dp_en;    
input          y_create1_src_match; 
output         x_read_lch_rdy;     

// &Regs; @26
reg            lch_rdy;            
reg            x_read_lch_rdy;     

// &Wires; @27
wire           cpurst_b;           
wire           lch_rdy_create0_en; 
wire           lch_rdy_create1_en; 
wire           vld;                
wire           x_create_dp_en;     
wire    [1:0]  x_create_entry;     
wire           x_create_lch_rdy;   
wire           y_clk;              
wire           y_create0_dp_en;    
wire           y_create0_src_match; 
wire           y_create1_dp_en;    
wire           y_create1_src_match; 



//==========================================================
//                     Preg Register
//==========================================================
assign lch_rdy_create0_en = y_create0_dp_en && x_create_entry[0];
assign lch_rdy_create1_en = y_create1_dp_en && x_create_entry[1];

always @(posedge y_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    lch_rdy <= 1'b0;
  else if(x_create_dp_en)
    lch_rdy <= x_create_lch_rdy;
  else if(vld && lch_rdy_create0_en)
    lch_rdy <= y_create0_src_match;
  else if(vld && lch_rdy_create1_en)
    lch_rdy <= y_create1_src_match;
  else
    lch_rdy <= lch_rdy;
end

//==========================================================
//                      Read Port
//==========================================================
// &CombBeg; @53
always @( y_create1_src_match
       or lch_rdy_create1_en
       or y_create0_src_match
       or lch_rdy
       or lch_rdy_create0_en)
begin
  case({lch_rdy_create1_en,lch_rdy_create0_en})
    2'b01  : x_read_lch_rdy = y_create0_src_match;
    2'b10  : x_read_lch_rdy = y_create1_src_match;
    default: x_read_lch_rdy = lch_rdy;
  endcase
// &CombEnd; @59
end

// &ModuleEnd; @61
endmodule
module ct_hpcp_event(
  cp0_hpcp_icg_en,
  cpurst_b,
  eventx_clk_en,
  eventx_value,
  eventx_wen,
  forever_cpuclk,
  hpcp_wdata,
  pad_yy_icg_scan_en
);

// &Ports; @23
input           cp0_hpcp_icg_en;   
input           cpurst_b;          
input           eventx_clk_en;     
input           eventx_wen;        
input           forever_cpuclk;    
input   [63:0]  hpcp_wdata;        
input           pad_yy_icg_scan_en; 
output  [63:0]  eventx_value;      

// &Regs; @24
reg     [5 :0]  value;             

// &Wires @25
wire            cp0_hpcp_icg_en;   
wire            cpurst_b;          
wire            eventx_clk;        
wire            eventx_clk_en;     
wire    [63:0]  eventx_value;      
wire            eventx_wen;        
wire            forever_cpuclk;    
wire    [63:0]  hpcp_wdata;        
wire            pad_yy_icg_scan_en; 
wire            value_mask;        


//define total counter num
parameter HPMCNT_NUM   = 42;
parameter HPMEVT_WIDTH = 6;

// &Force("bus","hpcp_wdata",63,0); @31
//==========================================================
//                 Instance of Gated Cell  
//========================================================== 
// &Instance("gated_clk_cell", "x_gated_clk"); @35
gated_clk_cell  x_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (eventx_clk        ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (eventx_clk_en     ),
  .module_en          (cp0_hpcp_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);

// &Connect(.clk_in      (forever_cpuclk), @36
//          .external_en (1'b0), @37
//          .global_en   (1'b1), @38
//          .module_en   (cp0_hpcp_icg_en), @39
//          .local_en    (eventx_clk_en), @40
//          .clk_out     (eventx_clk)); @41

//==========================================================
//                 Implementation of counter  
//==========================================================
always @(posedge eventx_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    value[HPMEVT_WIDTH-1:0] <= {HPMEVT_WIDTH{1'b0}};
  else if(eventx_wen)
    value[HPMEVT_WIDTH-1:0] <= hpcp_wdata[HPMEVT_WIDTH-1:0] & {HPMEVT_WIDTH{value_mask}} ;
  else
    value[HPMEVT_WIDTH-1:0] <= value[HPMEVT_WIDTH-1:0];
end

assign value_mask = (!(|hpcp_wdata[63:HPMEVT_WIDTH])) 
                 && (hpcp_wdata[HPMEVT_WIDTH-1:0] <= HPMCNT_NUM);

//output
assign eventx_value[63:0] = {{64-HPMEVT_WIDTH{1'b0}},value[HPMEVT_WIDTH-1:0]};

// &ModuleEnd; @62
endmodule
module ct_hpcp_cntof_reg(
  cntof_wen_x,
  cntof_x,
  counter_overflow_x,
  cpurst_b,
  hpcp_clk,
  hpcp_wdata_x,
  l2cnt_cmplt_ff
);

// &Ports; @23
input        cntof_wen_x;       
input        counter_overflow_x; 
input        cpurst_b;          
input        hpcp_clk;          
input        hpcp_wdata_x;      
input        l2cnt_cmplt_ff;    
output       cntof_x;           

// &Regs; @24
reg          cntof_x;           

// &Wires @25
wire         cntof_wen_x;       
wire         counter_overflow_x; 
wire         cpurst_b;          
wire         hpcp_clk;          
wire         hpcp_wdata_x;      
wire         l2cnt_cmplt_ff;    


always @(posedge hpcp_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
      cntof_x <= 1'b0;
  else if(cntof_wen_x && l2cnt_cmplt_ff) 
      cntof_x <= hpcp_wdata_x;
  else
      cntof_x <= cntof_x | counter_overflow_x;
end

// &Force("output","cntof_x"); @37
// &ModuleEnd; @38
endmodule
module ct_hpcp_cntinten_reg(
  cntinten_wen_x,
  cntinten_x,
  cpurst_b,
  hpcp_clk,
  hpcp_wdata_x
);

// &Ports; @23
input        cntinten_wen_x; 
input        cpurst_b;      
input        hpcp_clk;      
input        hpcp_wdata_x;  
output       cntinten_x;    

// &Regs; @24
reg          cntinten_x;    

// &Wires @25
wire         cntinten_wen_x; 
wire         cpurst_b;      
wire         hpcp_clk;      
wire         hpcp_wdata_x;  


always @(posedge hpcp_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
      cntinten_x <= 1'b0;
  else if(cntinten_wen_x) 
      cntinten_x <= hpcp_wdata_x;
  else
      cntinten_x <= cntinten_x;
end

// &Force("output","cntinten_x"); @37
// &ModuleEnd; @38
endmodule
module ct_lsu_rot_data(
  data_in,
  data_settle_out,
  rot_sel
);

// &Ports; @24
input   [127:0]  data_in;        
input   [7  :0]  rot_sel;        
output  [127:0]  data_settle_out; 

// &Regs; @25
reg     [63 :0]  data_settle;    

// &Wires; @26
wire    [63 :0]  data;           
wire    [127:0]  data_in;        
wire    [63 :0]  data_rot0;      
wire    [63 :0]  data_rot1;      
wire    [63 :0]  data_rot2;      
wire    [63 :0]  data_rot3;      
wire    [63 :0]  data_rot4;      
wire    [63 :0]  data_rot5;      
wire    [63 :0]  data_rot6;      
wire    [63 :0]  data_rot7;      
wire    [127:0]  data_settle_out; 
wire    [7  :0]  rot_sel;        


// &CombBeg; @48
// &CombEnd; @68
assign data[63:0]       = data_in[63:0]
                          | data_in[127:64];

assign data_rot0[63:0]  = data[63:0];
assign data_rot1[63:0]  = {data[7:0],data[63:8]};
assign data_rot2[63:0]  = {data[15:0],data[63:16]};
assign data_rot3[63:0]  = {data[23:0],data[63:24]};
assign data_rot4[63:0]  = {data[31:0],data[63:32]};
assign data_rot5[63:0]  = {data[39:0],data[63:40]};
assign data_rot6[63:0]  = {data[47:0],data[63:48]};
assign data_rot7[63:0]  = {data[55:0],data[63:56]};

// &CombBeg; @85
always @( data_rot5[63:0]
       or rot_sel[7:0]
       or data_rot0[63:0]
       or data_rot3[63:0]
       or data_rot6[63:0]
       or data_rot4[63:0]
       or data_rot1[63:0]
       or data_rot7[63:0]
       or data_rot2[63:0])
begin
case(rot_sel[7:0])
  8'h01:data_settle[63:0] = data_rot0[63:0];
  8'h02:data_settle[63:0] = data_rot1[63:0];
  8'h04:data_settle[63:0] = data_rot2[63:0];
  8'h08:data_settle[63:0] = data_rot3[63:0];
  8'h10:data_settle[63:0] = data_rot4[63:0];
  8'h20:data_settle[63:0] = data_rot5[63:0];
  8'h40:data_settle[63:0] = data_rot6[63:0];
  8'h80:data_settle[63:0] = data_rot7[63:0];
  default: data_settle[63:0] = {64{1'bx}};
endcase
// &CombEnd; @97
end

assign data_settle_out[127:0] = {64'b0,data_settle[63:0]};

// &ModuleEnd; @102
endmodule
module ct_lsu_dcache_tag_array(
  forever_cpuclk,
  pad_yy_icg_scan_en,
  tag_din,
  tag_dout,
  tag_gateclk_en,
  tag_gwen_b,
  tag_idx,
  tag_sel_b,
  tag_wen_b,
  cp0_lsu_icg_en
);
input           forever_cpuclk;      
input           pad_yy_icg_scan_en; 
input   [51:0]  tag_din;             
input           tag_gateclk_en;      
input           tag_gwen_b;          
input   [8 :0]  tag_idx;             
input           tag_sel_b;           
input   [1 :0]  tag_wen_b;
input           cp0_lsu_icg_en;           
output  [51:0]  tag_dout;            

wire            forever_cpuclk;      
wire            pad_yy_icg_scan_en; 
wire            tag_clk;             
wire            tag_clk_en;          
wire    [51:0]  tag_din;             
wire    [51:0]  tag_dout;            
wire            tag_gateclk_en;      
wire            tag_gwen_b;          
wire    [8 :0]  tag_idx;             
wire            tag_sel_b;           
wire    [1 :0]  tag_wen_b;           
wire    [51:0]  tag_wen_b_all; 
wire            cp0_lsu_icg_en;       

//==========================================================
//                 Instance of Gated Cell
//==========================================================
assign tag_clk_en = tag_gateclk_en;
// &Instance("gated_clk_cell", "x_dcache_tag_gated_clk"); @79
gated_clk_cell  x_dcache_tag_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (tag_clk           ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (tag_clk_en        ),
  .module_en          (cp0_lsu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);

// &Connect(.clk_in        (forever_cpuclk     ), @80
//          .external_en   (1'b0               ), @81
//          .global_en     (1'b1               ), @82
//          .module_en     (cp0_lsu_icg_en     ), @83
//          .local_en      (tag_clk_en         ), @84
//          .clk_out       (tag_clk            )); @85

//==========================================================
//              Instance dcache array
//==========================================================

// &Force("bus","tag_idx","8","0"); @91
assign tag_wen_b_all[51:0]  = {{26{tag_wen_b[1]}},
                              {26{tag_wen_b[0]}}};


//csky vperl_off
`ifdef DCACHE_32K
ct_spsram_256x52  x_ct_spsram_256x52 (
  `ifdef MEM_CFG_IN
  .mem_cfg_in     (mem_cfg_in  ),
  `endif
  .A             (tag_idx[7:0] ),
  .CEN           (tag_sel_b    ),
  .CLK           (tag_clk      ),
  .D             (tag_din      ),
  .GWEN          (tag_gwen_b   ),
  .Q             (tag_dout     ),
  .WEN           (tag_wen_b_all)
);
`endif//DCACHE_32K

`ifdef DCACHE_64K
ct_spsram_512x52  x_ct_spsram_512x52 (
  `ifdef MEM_CFG_IN
  .mem_cfg_in     (mem_cfg_in  ),
  `endif
  .A             (tag_idx[8:0] ),
  .CEN           (tag_sel_b    ),
  .CLK           (tag_clk      ),
  .D             (tag_din      ),
  .GWEN          (tag_gwen_b   ),
  .Q             (tag_dout     ),
  .WEN           (tag_wen_b_all)
);
`endif//DCACHE_64K
//csky vperl_on

// &ModuleEnd; @128
endmodule
module ct_lsu_dcache_dirty_array(
  dirty_din,
  dirty_dout,
  dirty_gateclk_en,
  dirty_gwen_b,
  dirty_idx,
  dirty_sel_b,
  dirty_wen_b,
  forever_cpuclk,
  pad_yy_icg_scan_en,
  cp0_lsu_icg_en
);
input   [6:0]  dirty_din;
input          dirty_gateclk_en;    
input          dirty_gwen_b;        
input   [8:0]  dirty_idx;           
input          dirty_sel_b;
input   [6:0]  dirty_wen_b;
input          forever_cpuclk;      
input          pad_yy_icg_scan_en;
input          cp0_lsu_icg_en;
output  [6:0]  dirty_dout;

wire           dirty_clk;           
wire           dirty_clk_en;
wire    [6:0]  dirty_din;           
wire    [6:0]  dirty_dout;
wire           dirty_gateclk_en;    
wire           dirty_gwen_b;        
wire    [8:0]  dirty_idx;           
wire           dirty_sel_b;
wire    [6:0]  dirty_wen_b;
wire           forever_cpuclk;      
wire           pad_yy_icg_scan_en; 
wire           cp0_lsu_icg_en;  

//==========================================================
//                 Instance of Gated Cell
//==========================================================
assign dirty_clk_en = dirty_gateclk_en;
// &Instance("gated_clk_cell", "x_dcache_dirty_gated_clk"); @103
gated_clk_cell  x_dcache_dirty_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (dirty_clk         ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (dirty_clk_en      ),
  .module_en          (cp0_lsu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);

// &Connect(.clk_in        (forever_cpuclk     ), @104
//          .external_en   (1'b0               ), @105
//          .global_en     (1'b1               ), @106
//          .module_en     (cp0_lsu_icg_en     ), @107
//          .local_en      (dirty_clk_en         ), @108
//          .clk_out       (dirty_clk            )); @109

//==========================================================
//              Instance dcache array
//==========================================================

// &Force("bus","dirty_idx","8","0"); @115

//csky vperl_off
`ifdef DCACHE_32K
ct_spsram_256x7  x_ct_spsram_256x7 (
  `ifdef MEM_CFG_IN
  .mem_cfg_in     (mem_cfg_in    ),
  `endif
  .A              (dirty_idx[7:0]),
  .CEN            (dirty_sel_b   ),
  .CLK            (dirty_clk     ),
  .D              (dirty_din     ),
  .GWEN           (dirty_gwen_b  ),
  .Q              (dirty_dout    ),
  .WEN            (dirty_wen_b   )
);
`endif//DCACHE_32K

`ifdef DCACHE_64K
ct_spsram_512x7  x_ct_spsram_512x7 (
  `ifdef MEM_CFG_IN
  .mem_cfg_in     (mem_cfg_in    ),
  `endif
  .A              (dirty_idx[8:0]),
  .CEN            (dirty_sel_b   ),
  .CLK            (dirty_clk     ),
  .D              (dirty_din     ),
  .GWEN           (dirty_gwen_b  ),
  .Q              (dirty_dout    ),
  .WEN            (dirty_wen_b   )
);
`endif//DCACHE_64K
//csky vperl_on

// &ModuleEnd; @183
endmodule
module ct_lsu_snoop_resp(
  biu_ctcq_cr_ready,
  biu_lsu_cd_ready,
  biu_lsu_cr_ready,
  biu_lsu_cr_resp_acept,
  biu_sdb_cd_ready,
  biu_snq_cr_ready,
  ctcq_biu_cr_resp,
  ctcq_biu_cr_valid,
  lsu_biu_cd_data,
  lsu_biu_cd_last,
  lsu_biu_cd_valid,
  lsu_biu_cr_resp,
  lsu_biu_cr_valid,
  sdb_biu_cd_data,
  sdb_biu_cd_last,
  sdb_biu_cd_valid,
  snq_biu_cr_resp,
  snq_biu_cr_valid
);

// &Ports; @23
input            biu_lsu_cd_ready;     
input            biu_lsu_cr_ready;     
input   [4  :0]  ctcq_biu_cr_resp;     
input            ctcq_biu_cr_valid;    
input   [127:0]  sdb_biu_cd_data;      
input            sdb_biu_cd_last;      
input            sdb_biu_cd_valid;     
input   [4  :0]  snq_biu_cr_resp;      
input            snq_biu_cr_valid;     
output           biu_ctcq_cr_ready;    
output           biu_lsu_cr_resp_acept; 
output           biu_sdb_cd_ready;     
output           biu_snq_cr_ready;     
output  [127:0]  lsu_biu_cd_data;      
output           lsu_biu_cd_last;      
output           lsu_biu_cd_valid;     
output  [4  :0]  lsu_biu_cr_resp;      
output           lsu_biu_cr_valid;     

// &Regs; @24

// &Wires; @25
wire             biu_ctcq_cr_ready;    
wire             biu_lsu_cd_ready;     
wire             biu_lsu_cr_ready;     
wire             biu_lsu_cr_resp_acept; 
wire             biu_sdb_cd_ready;     
wire             biu_snq_cr_ready;     
wire    [4  :0]  ctcq_biu_cr_resp;     
wire             ctcq_biu_cr_valid;    
wire    [127:0]  lsu_biu_cd_data;      
wire             lsu_biu_cd_last;      
wire             lsu_biu_cd_valid;     
wire    [4  :0]  lsu_biu_cr_resp;      
wire             lsu_biu_cr_valid;     
wire    [127:0]  sdb_biu_cd_data;      
wire             sdb_biu_cd_last;      
wire             sdb_biu_cd_valid;     
wire    [4  :0]  snq_biu_cr_resp;      
wire             snq_biu_cr_valid;     


//cr channel
// &Force("output","lsu_biu_cr_valid"); @28
assign lsu_biu_cr_valid     = snq_biu_cr_valid || ctcq_biu_cr_valid;
assign lsu_biu_cr_resp[4:0] = (snq_biu_cr_resp[4:0]  & {5{snq_biu_cr_valid}})
                            | (ctcq_biu_cr_resp[4:0] & {5{ctcq_biu_cr_valid}});

assign biu_snq_cr_ready  = biu_lsu_cr_ready;
assign biu_ctcq_cr_ready = biu_lsu_cr_ready;

assign biu_lsu_cr_resp_acept  = lsu_biu_cr_valid && biu_lsu_cr_ready;

//cd channel
assign lsu_biu_cd_valid       = sdb_biu_cd_valid;
assign lsu_biu_cd_data[127:0] = sdb_biu_cd_data[127:0];
assign lsu_biu_cd_last        = sdb_biu_cd_last;

assign biu_sdb_cd_ready = biu_lsu_cd_ready;


// &ModuleEnd; @49
endmodule
module ct_lsu_dcache_ld_tag_array(
  forever_cpuclk,
  pad_yy_icg_scan_en,
  tag_din,
  tag_dout,
  tag_gateclk_en,
  tag_gwen_b,
  tag_idx,
  tag_sel_b,
  tag_wen_b,
  cp0_lsu_icg_en
);
input           forever_cpuclk;      
input           pad_yy_icg_scan_en;
input   [53:0]  tag_din;
input           tag_gateclk_en;      
input           tag_gwen_b;          
input   [8 :0]  tag_idx;             
input           tag_sel_b;           
input   [1 :0]  tag_wen_b;
input           cp0_lsu_icg_en;
output  [53:0]  tag_dout;

wire            forever_cpuclk;      
wire            ld_tag_clk;          
wire            ld_tag_clk_en;       
wire            pad_yy_icg_scan_en;
wire    [53:0]  tag_din;             
wire    [53:0]  tag_dout;
wire            tag_gateclk_en;      
wire            tag_gwen_b;          
wire    [8 :0]  tag_idx;             
wire            tag_sel_b;           
wire    [1 :0]  tag_wen_b;
wire    [53:0]  tag_wen_b_all;
wire            cp0_lsu_icg_en;        

//==========================================================
//                 Instance of Gated Cell
//==========================================================
assign ld_tag_clk_en = tag_gateclk_en;
// &Instance("gated_clk_cell", "x_dcache_ld_tag_gated_clk"); @100
gated_clk_cell  x_dcache_ld_tag_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (ld_tag_clk        ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (ld_tag_clk_en     ),
  .module_en          (cp0_lsu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);

// &Connect(.clk_in        (forever_cpuclk     ), @101
//          .external_en   (1'b0               ), @102
//          .global_en     (1'b1               ), @103
//          .module_en     (cp0_lsu_icg_en     ), @104
//          .local_en      (ld_tag_clk_en         ), @105
//          .clk_out       (ld_tag_clk            )); @106

//==========================================================
//              Instance dcache array
//==========================================================
assign tag_wen_b_all[53:0]  = {{27{tag_wen_b[1]}},
                              {27{tag_wen_b[0]}}};

//csky vperl_off
`ifdef DCACHE_32K
ct_spsram_256x54  x_ct_spsram_256x54 (
  `ifdef MEM_CFG_IN
  .mem_cfg_in     (mem_cfg_in  ),
  `endif
  .A             (tag_idx[7:0] ),
  .CEN           (tag_sel_b    ),
  .CLK           (ld_tag_clk   ),
  .D             (tag_din      ),
  .GWEN          (tag_gwen_b   ),
  .Q             (tag_dout     ),
  .WEN           (tag_wen_b_all)
);
`endif//DCACHE_32K
`ifdef DCACHE_64K
ct_spsram_512x54  x_ct_spsram_512x54 (
  `ifdef MEM_CFG_IN
  .mem_cfg_in     (mem_cfg_in  ),
  `endif
  .A             (tag_idx[8:0] ),
  .CEN           (tag_sel_b    ),
  .CLK           (ld_tag_clk   ),
  .D             (tag_din      ),
  .GWEN          (tag_gwen_b   ),
  .Q             (tag_dout     ),
  .WEN           (tag_wen_b_all)
);
`endif//DCACHE_64K
//csky vperl_on

endmodule
module ct_lsu_idfifo_entry(
  cpurst_b,
  idfifo_clk,
  idfifo_create_id,
  idfifo_entry_create_vld_x,
  idfifo_entry_id_v
);

// &Ports; @24
input          cpurst_b;                 
input          idfifo_clk;               
input   [2:0]  idfifo_create_id;         
input          idfifo_entry_create_vld_x; 
output  [2:0]  idfifo_entry_id_v;        

// &Regs; @25
reg     [2:0]  idfifo_entry_id;          

// &Wires; @26
wire           cpurst_b;                 
wire           idfifo_clk;               
wire    [2:0]  idfifo_create_id;         
wire           idfifo_entry_create_vld;  
wire           idfifo_entry_create_vld_x; 
wire    [2:0]  idfifo_entry_id_v;        


//==========================================================
//                 Register
//==========================================================
always @(posedge idfifo_clk or negedge cpurst_b)
begin
  if (!cpurst_b)
    idfifo_entry_id[2:0]  <= 3'b0;
  else if(idfifo_entry_create_vld)
    idfifo_entry_id[2:0]  <= idfifo_create_id[2:0];
end

//==========================================================
//                 Generate interface
//==========================================================
//------------------input-----------------------------------
assign idfifo_entry_create_vld  = idfifo_entry_create_vld_x;
//------------------output----------------------------------
assign idfifo_entry_id_v[2:0]   = idfifo_entry_id[2:0];

// &ModuleEnd; @47
endmodule
module ct_had_io(
  had_pad_jtg_tdo,
  had_pad_jtg_tdo_en,
  io_serial_tdi,
  io_sm_tap_en,
  pad_had_jtg_tdi,
  serial_io_tdo,
  sm_io_tdo_en
);

// &Ports; @24
input        pad_had_jtg_tdi;   
input        serial_io_tdo;     
input        sm_io_tdo_en;      
output       had_pad_jtg_tdo;   
output       had_pad_jtg_tdo_en; 
output       io_serial_tdi;     
output       io_sm_tap_en;      

// &Regs; @25

// &Wires; @26
wire         had_pad_jtg_tdo;   
wire         had_pad_jtg_tdo_en; 
wire         io_serial_tdi;     
wire         io_sm_tap_en;      
wire         pad_had_jtg_tdi;   
wire         serial_io_tdo;     
wire         sm_io_tdo_en;      


//===============================================================
// JTAG_2 and JTAG_5 interface signals
//===============================================================
//                                |     __
//    pad_had_jtg_tdi ----------->|----|  \
//                                |    |   |----> io_serial_tdi
//  pad_had_jtg_tms_i ----------->|----|__/
//                                |     |
//  pad_had_jtag2_sel ----------->|-----+
//                                |
//    had_pad_jtg_tdo <-----------|--+
//                                |  |----------- serial_io_tdo
//  had_pad_jtg_tms_o <-----------|--+
//                                |
// had_pad_jtg_tdo_en <-----------|-------------- sm_io_tdo_en
//                                |
// had_pad_jtg_tms_oe <-----------|-------------- sm_io_tms_oe
//                                |
//===============================================================
assign io_serial_tdi = pad_had_jtg_tdi;
assign had_pad_jtg_tdo = serial_io_tdo;
assign had_pad_jtg_tdo_en = sm_io_tdo_en;

assign io_sm_tap_en = 1'b1;



// &ModuleEnd; @77
endmodule
module ct_had_sync_3flop(
  clk1,
  clk2,
  rst1_b,
  rst2_b,
  sync_in,
  sync_out
);

// &Ports; @25
input        clk1;         
input        clk2;         
input        rst1_b;       
input        rst2_b;       
input        sync_in;      
output       sync_out;     

// &Regs; @26
reg          sync_ff1_clk1; 
reg          sync_ff2_clk1; 
reg          sync_ff3_clk1; 
reg          sync_ff4_clk1; 
reg          sync_ff_clk2; 

// &Wires; @27
wire         clk1;         
wire         clk2;         
wire         rst1_b;       
wire         rst2_b;       
wire         sync_in;      
wire         sync_out;     


//==============================================================================
// sync logic from clk2 to clk1
// step 1. flop once in clk2 domain
// step 2. flop twice in clk1 domain
// result: a pulse signal in clk1 domain
// constraint: slow clock --> fast clock
//==============================================================================

always @(posedge clk2 or negedge rst2_b)
begin
  if (!rst2_b)
    sync_ff_clk2 <= 1'b0;
  else
    sync_ff_clk2 <= sync_in;
end

always @(posedge clk1 or negedge rst1_b)
begin
  if (!rst1_b) begin
    sync_ff1_clk1 <= 1'b0;
    sync_ff2_clk1 <= 1'b0;
    sync_ff3_clk1 <= 1'b0;
  end
  else begin
    sync_ff1_clk1 <= sync_ff_clk2;
    sync_ff2_clk1 <= sync_ff1_clk1;
    sync_ff3_clk1 <= sync_ff2_clk1;
  end   
end

// generates a pulse signal in clk1 domain
always @(posedge clk1 or negedge rst1_b)
begin
  if (!rst1_b)
    sync_ff4_clk1 <= 1'b0;
  else
    sync_ff4_clk1 <= sync_ff3_clk1;
end

assign sync_out = !sync_ff4_clk1 && sync_ff3_clk1;

// &ModuleEnd; @70
endmodule
module ct_vfmau_lza_42(
  lza_p0,
  lza_p1,
  lza_precod,
  lza_vld
);

// &Ports; @24
input   [3:0]  lza_precod; 
output         lza_p0;    
output         lza_p1;    
output         lza_vld;   

// &Regs; @25

// &Wires; @26
wire           lza_p0;    
wire           lza_p1;    
wire    [3:0]  lza_precod; 
wire           lza_vld;   


assign lza_vld = |lza_precod[3:0];
assign lza_p0  = !lza_precod[3] && (lza_precod[2] || !lza_precod[1]);
assign lza_p1  = !(lza_precod[2] || lza_precod[3]);

// &ModuleEnd; @32
endmodule
module ct_vfmau_lza_32(
  lza_p0,
  lza_p1,
  lza_precod,
  lza_vld
);

// &Ports; @24
input   [2:0]  lza_precod; 
output         lza_p0;    
output         lza_p1;    
output         lza_vld;   

// &Regs; @25

// &Wires; @26
wire           lza_p0;    
wire           lza_p1;    
wire    [2:0]  lza_precod; 
wire           lza_vld;   


assign lza_vld = |lza_precod[2:0];
assign lza_p0  = !lza_precod[2] && lza_precod[1];
assign lza_p1  = !lza_precod[2] && !lza_precod[1];

// &ModuleEnd; @32
endmodule
module ct_vfmau_ff1_10bit(
  ff1_data,
  ff1_result
);

// &Ports; @24
input   [9:0]  ff1_data;  
output  [3:0]  ff1_result; 

// &Regs; @25
reg     [3:0]  ff1_result; 

// &Wires; @26
wire    [9:0]  ff1_data;  


// &CombBeg; @28
always @( ff1_data[9:0])
begin
casez(ff1_data[9:0])
  10'b1?????????: ff1_result[3:0] = 4'd1;
  10'b01????????: ff1_result[3:0] = 4'd2;
  10'b001???????: ff1_result[3:0] = 4'd3;
  10'b0001??????: ff1_result[3:0] = 4'd4;
  10'b00001?????: ff1_result[3:0] = 4'd5;
  10'b000001????: ff1_result[3:0] = 4'd6;
  10'b0000001???: ff1_result[3:0] = 4'd7;
  10'b00000001??: ff1_result[3:0] = 4'd8;
  10'b000000001?: ff1_result[3:0] = 4'd9;
  10'b0000000001: ff1_result[3:0] = 4'd10;
  default       : ff1_result[3:0] = {4{1'bx}};
endcase
// &CombEnd; @42
end

// &ModuleEnd; @44
endmodule
module fifo_counter(
  counter_done,
  counter_en,
  counter_load,
  cpu_clk,
  cpu_rst_b
);


input           counter_en;   
input   [31:0]  counter_load; 
input           cpu_clk;      
input           cpu_rst_b;    
output          counter_done; 


reg     [31:0]  counter;      
reg             counter_en_ff; 


wire            counter_done; 
wire            counter_en;   
wire    [31:0]  counter_load; 
wire            cpu_clk;      
wire            cpu_rst_b;    
wire            load_cnt_en;  


always @(posedge cpu_clk or negedge cpu_rst_b)
begin
  if(!cpu_rst_b)
  begin
    counter_en_ff <= 1'b0;
  end
  else
  begin
    counter_en_ff <=counter_en ;
  end
end

assign load_cnt_en= (counter_en && !counter_en_ff);


always @(posedge cpu_clk or negedge cpu_rst_b)
begin
  if(!cpu_rst_b)
  begin
    counter[31:0] <= 32'h0;
  end
  else if (load_cnt_en)
  begin
    counter[31:0] <= counter_load[31:0];
  end
  else if (counter_done)
    counter[31:0] <= 32'b0;
  else 
    counter[31:0] <= counter[31:0] -1'b1;
 end

assign counter_done = (counter[31:0] == 32'b0) ;


endmodule
module clk_gen(
  clkrst_b,
  i_pad_clk,
  clk_en,
  psel,
  penable,
  prdata,
  pwdata,
  pwrite,

  gate_en0,
  gate_en1,

  pad_biu_clkratio,
  per_clk,
  cpu_clk
);


input           clkrst_b;        
input           i_pad_clk;       
input           penable;         
input           psel;            
input   [2 :0]  pwdata;          
input           pwrite;         
input           gate_en0;      
input           gate_en1;      
output          clk_en;          
output  [2 :0]  pad_biu_clkratio; 
output          per_clk;         
output          cpu_clk;         
output  [31:0]  prdata;          


wire    [31:0]  prdata;          


wire            clk_en;          
wire            clkrst_b;        
wire            i_pad_clk;       
wire    [2 :0]  pad_biu_clkratio; 
wire            penable;         
wire            per_clk;         
wire            cpu_clk;         
wire            psel;            
wire    [2 :0]  pwdata;          
wire            pwrite;          

// configure parameter for system clock dividor
// 0 not support
//
// default 1:1. all case can run in this configuration
// 1 = 1:1
//
// some case may run fail
// 2 = 2:1
// 3 = 3:1
// 4 = 4:1
// 5 = 5:1
//........
// 7 = 7:1
parameter  CLK_RATIO = 3'd1;


reg [2:0]  cnt; 
reg        cnt_zero; 
wire       sys_clk;
always @(posedge i_pad_clk or negedge clkrst_b)
begin
  if(!clkrst_b)
    cnt[2:0] <= 3'b0;
  else if(cnt == (CLK_RATIO - 1))
    cnt[2:0] <= 3'b0;
  else
    cnt[2:0] <= cnt[2:0] + 3'd1;
end

always @(posedge i_pad_clk or negedge clkrst_b)
begin
  if(!clkrst_b)
    cnt_zero <=  1'b1;
  else if(cnt == (CLK_RATIO - 1))
    cnt_zero <=  1'b1;
  else
    cnt_zero <=  1'b0;
end


assign sys_clk = (CLK_RATIO == 1) ?  i_pad_clk
                                 :  cnt_zero;

assign clk_en  = (CLK_RATIO == 1) ? 1'b1
               : (CLK_RATIO == 2) ? cnt_zero
                                  : (cnt == CLK_RATIO - 2);

assign  prdata[31:0]          = {29'b0,CLK_RATIO};
assign  pad_biu_clkratio[2:0] = CLK_RATIO;

reg [3:0] div_cnt;
reg       slow_clk; 
always @(posedge i_pad_clk or negedge clkrst_b) begin
  if (!clkrst_b) begin
    div_cnt     <= 4'hf;
    slow_clk    <= 1'b0;
  end
  else begin
    if(div_cnt != 4'h0) begin
      div_cnt   <= div_cnt - 1;
      slow_clk  <= slow_clk;
    end
    else begin
      div_cnt   <= 4'hf;
      slow_clk  <= ~slow_clk;
    end
  end
end

assign per_clk = sys_clk;
assign cpu_clk = gate_en0 ? slow_clk : (gate_en1 ? 1'b0 : i_pad_clk);
// assign cpu_clk = i_pad_clk;

endmodule
module BUFGCE(
  I,
  CE,
  O 
);

input  I;
input  CE;
output O;

wire clk_in;
wire external_en;

assign clk_in = I;
assign external_en = CE;

reg    clk_en_af_latch;
always @(clk_in or external_en)
begin
  if(!clk_in)
    clk_en_af_latch <= external_en;
end

reg clk_en ;
always @ (clk_en_af_latch )
begin
    clk_en <= clk_en_af_latch;
end
assign O = clk_in && clk_en ;

endmodule
module RCOSC_1MHZ ( 
  CLKOUT );

/* synthesis syn_black_box */
/* synthesis syn_noprune=1 */

output CLKOUT;

endmodule
module RCOSC_25_50MHZ ( 
  CLKOUT );

/* synthesis syn_black_box */
/* synthesis syn_noprune=1 */

output CLKOUT;

parameter FREQUENCY = 50.0;

endmodule
module XTLOSC ( 
  CLKOUT,
  XTL );

/* synthesis syn_black_box */
/* synthesis syn_noprune=1 */
/* synthesis black_box_pad_pin ="XTL" */

output CLKOUT;
input XTL;

parameter MODE = 'h3;
parameter FREQUENCY = 20.0;

endmodule
module RCOSC_1MHZ_FAB ( 
  CLKOUT,
  A );

/* synthesis syn_black_box */
/* synthesis syn_noprune=1 */

output CLKOUT;
input A;

endmodule
module RCOSC_25_50MHZ_FAB ( 
  CLKOUT,
  A );

/* synthesis syn_black_box */
/* synthesis syn_noprune=1 */

output CLKOUT;
input A;

endmodule
module XTLOSC_FAB ( 
  CLKOUT,
  A );

/* synthesis syn_black_box */
/* synthesis syn_noprune=1 */

output CLKOUT;
input A;

endmodule
module RCOSC_1MHZ ( 
  CLKOUT );

/* synthesis black_box */

output CLKOUT;

endmodule
module RCOSC_25_50MHZ ( 
  CLKOUT );

/* synthesis black_box */

output CLKOUT;

parameter FREQUENCY = 50.0;

endmodule
module XTLOSC ( 
  CLKOUT,
  XTL );

/* synthesis black_box */
/* synthesis black_box black_box_pad ="XTL" */

output CLKOUT;
input XTL;

parameter MODE = 'h3;
parameter FREQUENCY = 20.0;

endmodule
module RCOSC_1MHZ_FAB ( 
  CLKOUT,
  A );

/* synthesis black_box */

output CLKOUT;
input A;

endmodule
module RCOSC_25_50MHZ_FAB ( 
  CLKOUT,
  A );

/* synthesis black_box */

output CLKOUT;
input A;

endmodule
module XTLOSC_FAB ( 
  CLKOUT,
  A );

/* synthesis black_box */

output CLKOUT;
input A;

endmodule
module ccc1(
    // Inputs
    RCOSC_25_50MHZ,
    // Outputs
    GL0,
    LOCK
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input  RCOSC_25_50MHZ;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output GL0;
output LOCK;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire   GL0_net_0;
wire   LOCK_net_0;
wire   RCOSC_25_50MHZ;
wire   GL0_net_1;
wire   LOCK_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire   GND_net;
wire   [7:2]PADDR_const_net_0;
wire   [7:0]PWDATA_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net            = 1'b0;
assign PADDR_const_net_0  = 6'h00;
assign PWDATA_const_net_0 = 8'h00;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign GL0_net_1  = GL0_net_0;
assign GL0        = GL0_net_1;
assign LOCK_net_1 = LOCK_net_0;
assign LOCK       = LOCK_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------ccc1_ccc1_0_FCCC   -   Actel:SgCore:FCCC:2.0.201
ccc1_ccc1_0_FCCC ccc1_0(
        // Inputs
        .RCOSC_25_50MHZ ( RCOSC_25_50MHZ ),
        // Outputs
        .GL0            ( GL0_net_0 ),
        .LOCK           ( LOCK_net_0 ) 
        );


endmodule
module osc1(
    // Outputs
    RCOSC_25_50MHZ_CCC
);

//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output RCOSC_25_50MHZ_CCC;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire   RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;
wire   RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire   GND_net;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net = 1'b0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC_net_0 = RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;
assign RCOSC_25_50MHZ_CCC                              = RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC_net_0;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------osc1_osc1_0_OSC   -   Actel:SgCore:OSC:2.0.101
osc1_osc1_0_OSC osc1_0(
        // Inputs
        .XTL                ( GND_net ), // tied to 1'b0 from definition
        // Outputs
        .RCOSC_25_50MHZ_CCC ( RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC ),
        .RCOSC_25_50MHZ_O2F (  ),
        .RCOSC_1MHZ_CCC     (  ),
        .RCOSC_1MHZ_O2F     (  ),
        .XTLOSC_CCC         (  ),
        .XTLOSC_O2F         (  ) 
        );


endmodule
module ccc1_ccc1_0_FCCC(
       RCOSC_25_50MHZ,
       LOCK,
       GL0
    );
input  RCOSC_25_50MHZ;
output LOCK;
output GL0;

    wire gnd_net, vcc_net, GL0_net;
    
    VCC vcc_inst (.Y(vcc_net));
    GND gnd_inst (.Y(gnd_net));
    CLKINT GL0_INST (.A(GL0_net), .Y(GL0));
    CCC #( .INIT(210'h0000407F90000044D74000718C6318C2318C1DEC0404040403818)
        , .VCOFREQUENCY(912.000) )  CCC_INST (.Y0(), .Y1(), .Y2(), .Y3(
        ), .PRDATA({nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7}), .LOCK(
        LOCK), .BUSY(), .CLK0(vcc_net), .CLK1(vcc_net), .CLK2(vcc_net), 
        .CLK3(vcc_net), .NGMUX0_SEL(gnd_net), .NGMUX1_SEL(gnd_net), 
        .NGMUX2_SEL(gnd_net), .NGMUX3_SEL(gnd_net), .NGMUX0_HOLD_N(
        vcc_net), .NGMUX1_HOLD_N(vcc_net), .NGMUX2_HOLD_N(vcc_net), 
        .NGMUX3_HOLD_N(vcc_net), .NGMUX0_ARST_N(vcc_net), 
        .NGMUX1_ARST_N(vcc_net), .NGMUX2_ARST_N(vcc_net), 
        .NGMUX3_ARST_N(vcc_net), .PLL_BYPASS_N(vcc_net), .PLL_ARST_N(
        vcc_net), .PLL_POWERDOWN_N(vcc_net), .GPD0_ARST_N(vcc_net), 
        .GPD1_ARST_N(vcc_net), .GPD2_ARST_N(vcc_net), .GPD3_ARST_N(
        vcc_net), .PRESET_N(gnd_net), .PCLK(vcc_net), .PSEL(vcc_net), 
        .PENABLE(vcc_net), .PWRITE(vcc_net), .PADDR({vcc_net, vcc_net, 
        vcc_net, vcc_net, vcc_net, vcc_net}), .PWDATA({vcc_net, 
        vcc_net, vcc_net, vcc_net, vcc_net, vcc_net, vcc_net, vcc_net})
        , .CLK0_PAD(gnd_net), .CLK1_PAD(gnd_net), .CLK2_PAD(gnd_net), 
        .CLK3_PAD(gnd_net), .GL0(GL0_net), .GL1(), .GL2(), .GL3(), 
        .RCOSC_25_50MHZ(RCOSC_25_50MHZ), .RCOSC_1MHZ(gnd_net), .XTLOSC(
        gnd_net));
    
endmodule
module osc1_osc1_0_OSC(
       XTL,
       RCOSC_25_50MHZ_CCC,
       RCOSC_25_50MHZ_O2F,
       RCOSC_1MHZ_CCC,
       RCOSC_1MHZ_O2F,
       XTLOSC_CCC,
       XTLOSC_O2F
    );
input  XTL;
output RCOSC_25_50MHZ_CCC;
output RCOSC_25_50MHZ_O2F;
output RCOSC_1MHZ_CCC;
output RCOSC_1MHZ_O2F;
output XTLOSC_CCC;
output XTLOSC_O2F;

    
    RCOSC_25_50MHZ #( .FREQUENCY(50.0) )  I_RCOSC_25_50MHZ (.CLKOUT(
        RCOSC_25_50MHZ_CCC));
    
endmodule
module nexys_video_clock_gen
  (input wire  i_clk,
   output wire o_clk,
   output reg  o_rst);

   wire   clkfb;
   wire   locked;
   reg 	  locked_r;

   PLLE2_BASE
     #(.BANDWIDTH("OPTIMIZED"),
       .CLKFBOUT_MULT(16),
       .CLKIN1_PERIOD(10.0), //100MHz
       .CLKOUT0_DIVIDE(100),
       .DIVCLK_DIVIDE(1),
       .STARTUP_WAIT("FALSE"))
   PLLE2_BASE_inst
     (.CLKOUT0(o_clk),
      .CLKOUT1(),
      .CLKOUT2(),
      .CLKOUT3(),
      .CLKOUT4(),
      .CLKOUT5(),
      .CLKFBOUT(clkfb),
      .LOCKED(locked),
      .CLKIN1(i_clk),
      .PWRDWN(1'b0),
      .RST(1'b0),
      .CLKFBIN(clkfb));

   always @(posedge o_clk) begin
      locked_r <= locked;
      o_rst  <= !locked_r;
   end

endmodule
module corescore_ebaz4205
(
 input wire  i_clk,
 output wire o_uart_tx);

   wire      clk;
   wire      rst;

   ebaz4205_clock_gen clock_gen
     (.i_clk (i_clk),
      .o_clk (clk),
      .o_rst (rst));

   parameter memfile_emitter = "emitter.hex";

   wire [7:0]  tdata;
   wire        tlast;
   wire        tvalid;
   wire        tready;

   corescorecore corescorecore
     (.i_clk     (clk),
      .i_rst     (rst),
      .o_tdata   (tdata),
      .o_tlast   (tlast),
      .o_tvalid  (tvalid),
      .i_tready  (tready));

   emitter #(.memfile (memfile_emitter)) emitter
     (.i_clk     (clk),
      .i_rst     (rst),
      .i_tdata   (tdata),
      .i_tlast   (tlast),
      .i_tvalid  (tvalid),
      .o_tready  (tready),
      .o_uart_tx (o_uart_tx));

endmodule
module corescore_vu19p
(
 input wire  CLK_100MHZ_P,
 input wire  CLK_100MHZ_N,
 output wire UART_TXD);

   wire      i_clk;
   wire      clk;
   wire      rst;

   IBUFGDS ibufds(
      .I (CLK_100MHZ_P),
      .IB(CLK_100MHZ_N),
      .O (i_clk));

   corescore_vu19p_clock_gen
   clock_gen
     (.i_clk (i_clk),
      .o_clk (clk),
      .o_rst (rst));

   parameter memfile_emitter = "emitter.hex";

   wire [7:0]  tdata;
   wire        tlast;
   wire        tvalid;
   wire        tready;

   corescorecore corescorecore
     (.i_clk     (clk),
      .i_rst     (rst),
      .o_tdata   (tdata),
      .o_tlast   (tlast),
      .o_tvalid  (tvalid),
      .i_tready  (tready));

   emitter #(.memfile (memfile_emitter)) emitter
     (.i_clk     (clk),
      .i_rst     (rst),
      .i_tdata   (tdata),
      .i_tlast   (tlast),
      .i_tvalid  (tvalid),
      .o_tready  (tready),
      .o_uart_tx (UART_TXD));

endmodule
module axis2wb
  (
   input wire 	     i_clk,
   input wire 	     i_rst,
   input wire [0:0]  i_wb_sel,
   input wire 	     i_wb_stb,
   output wire [9:0] o_wb_rdt,
   output reg 	     o_wb_ack,
   input wire [7:0]  i_tdata,
   input wire 	     i_tlast,
   input wire 	     i_tvalid,
   output wire 	     o_tready);

   always @(posedge i_clk) begin
      o_wb_ack <= i_wb_stb & !o_wb_ack;
      if (i_rst)
	o_wb_ack <= 1'b0;
   end

   assign o_tready = i_wb_sel[0] & o_wb_ack;
   assign o_wb_rdt = {i_tvalid, i_tlast, i_tdata};

endmodule
module de5_net_clock_gen (
    input wire  i_clk,
    input wire  i_rst,
    output wire o_clk,
    output wire o_rst
  );

  wire        locked;
  reg [9:0]   r;

  assign o_rst = r[9];

  always @(posedge o_clk) begin
    if (locked)
      r <= {r[8:0], 1'b0};
    else
      r <= 10'b1111111111;
  end

  wire   clk;
  assign o_clk = clk;

  altera_pll #(
    .reference_clock_frequency("50.0 MHz"),
    .operation_mode("direct"),
    .output_clock_frequency0("16.000000 MHz")
  ) altera_pll_i (
    .rst(i_rst),
    .outclk({clk}),
    .locked(locked),
    .fboutclk(),
    .fbclk(1'b0),
    .refclk(i_clk)
  );

endmodule
module corescore_genesys2
(
 input wire  i_clk_p,
 input wire  i_clk_n,
 output wire o_uart_tx);

   wire      i_clk;
   wire      clk;
   wire      rst;

   IBUFDS ibufds
     (.I  (i_clk_p),
      .IB (i_clk_n),
      .O  (i_clk));

   genesys2_clock_gen
   clock_gen
     (.i_clk (i_clk),
      .o_clk (clk),
      .o_rst (rst));

   parameter memfile_emitter = "emitter.hex";

   wire [7:0]  tdata;
   wire        tlast;
   wire        tvalid;
   wire        tready;

   corescorecore corescorecore
     (.i_clk     (clk),
      .i_rst     (rst),
      .o_tdata   (tdata),
      .o_tlast   (tlast),
      .o_tvalid  (tvalid),
      .i_tready  (tready));

   emitter #(.memfile (memfile_emitter)) emitter
     (.i_clk     (clk),
      .i_rst     (rst),
      .i_tdata   (tdata),
      .i_tlast   (tlast),
      .i_tvalid  (tvalid),
      .o_tready  (tready),
      .o_uart_tx (o_uart_tx));

endmodule
module corescore_alhambra_II
  (
   input i_clk,
   output wire locked_led,
   output wire o_uart_tx);

   wire        clk;
   wire        locked;

   //Mirror locked PLL to LED
   assign locked_led = locked;

  //Create a 16MHz clock from 12MHz using PLL
  pll pll48
    (.clock_in  (i_clk),
     .clock_out (clk),
     .locked    (locked));

   reg 	     rst = 1'b1;

   always @(posedge clk)
     rst <= !locked;

   parameter memfile_emitter = "emitter.hex";

   wire [7:0]  tdata;
   wire        tlast;
   wire        tvalid;
   wire        tready;

   corescorecore corescorecore
     (.i_clk     (clk),
      .i_rst     (rst),
      .o_tdata   (tdata),
      .o_tlast   (tlast),
      .o_tvalid  (tvalid),
      .i_tready  (tready));

   emitter #(.memfile (memfile_emitter)) emitter
     (.i_clk     (clk),
      .i_rst     (rst),
      .i_tdata   (tdata),
      .i_tlast   (tlast),
      .i_tvalid  (tvalid),
      .o_tready  (tready),
      .o_uart_tx (o_uart_tx));

endmodule
module corescore_deca
(
 input wire  i_clk,
 input wire  i_rst_n,
 output wire q,
 output wire uart_txd);

   wire      clk;
   wire      rst;

   //Mirror UART output to LED
   assign q = uart_txd;

   de0_nano_clock_gen clock_gen
     (.i_clk (i_clk),
      .i_rst (!i_rst_n),
      .o_clk (clk),
      .o_rst (rst));

   parameter memfile_emitter = "emitter.hex";

   wire [7:0]  tdata;
   wire        tlast;
   wire        tvalid;
   wire        tready;

   corescorecore corescorecore
     (.i_clk     (clk),
      .i_rst     (rst),
      .o_tdata   (tdata),
      .o_tlast   (tlast),
      .o_tvalid  (tvalid),
      .i_tready  (tready));

   emitter #(.memfile (memfile_emitter)) emitter
     (.i_clk     (clk),
      .i_rst     (rst),
      .i_tdata   (tdata),
      .i_tlast   (tlast),
      .i_tvalid  (tvalid),
      .o_tready  (tready),
      .o_uart_tx (uart_txd));

endmodule
module arty_a7_clock_gen
  (input wire  i_clk,
   output wire o_clk,
   output reg  o_rst);

   wire   clkfb;
   wire   locked;
   reg 	  locked_r;

   PLLE2_BASE
     #(.BANDWIDTH("OPTIMIZED"),
       .CLKFBOUT_MULT(16),
       .CLKIN1_PERIOD(10.0), //100MHz
       .CLKOUT0_DIVIDE(100),
       .DIVCLK_DIVIDE(1),
       .STARTUP_WAIT("FALSE"))
   PLLE2_BASE_inst
     (.CLKOUT0(o_clk),
      .CLKOUT1(),
      .CLKOUT2(),
      .CLKOUT3(),
      .CLKOUT4(),
      .CLKOUT5(),
      .CLKFBOUT(clkfb),
      .LOCKED(locked),
      .CLKIN1(i_clk),
      .PWRDWN(1'b0),
      .RST(1'b0),
      .CLKFBIN(clkfb));

   always @(posedge o_clk) begin
      locked_r <= locked;
      o_rst  <= !locked_r;
   end

endmodule
module corescore_ulx3s
(input wire i_clk,
 input wire btn0,
 output wire wifi_gpio0,
 output wire o_uart_tx,
 output wire q);

   wire      clk;
   wire      rst;

   assign q = o_uart_tx;
   assign wifi_gpio0 = btn0;

   corescore_ulx3s_clock_gen clock_gen
     (.i_clk (i_clk),
      .i_rst (!btn0),
      .o_clk (clk),
      .o_rst (rst));

   parameter memfile_emitter = "emitter.hex";

   wire [7:0]  tdata;
   wire        tlast;
   wire        tvalid;
   wire        tready;

   corescorecore corescorecore
     (.i_clk     (clk),
      .i_rst     (rst),
      .o_tdata   (tdata),
      .o_tlast   (tlast),
      .o_tvalid  (tvalid),
      .i_tready  (tready));

   emitter #(.memfile (memfile_emitter)) emitter
     (.i_clk     (clk),
      .i_rst     (rst),
      .i_tdata   (tdata),
      .i_tlast   (tlast),
      .i_tvalid  (tvalid),
      .o_tready  (tready),
      .o_uart_tx (o_uart_tx));

endmodule