dakies/OSS_Verilog huggingface dataset:
module clk_mux(
// Inputs
input clk1, // Clock 1 input
input clk2, // Clock 2 input
input s,    // Clock selection: 1 - clkout = clk1
            //                  0 - clkout = clk2
// Outputs
output clkout // Clock output 
);

// Clock mux
assign clkout = s ? clk1 : clk2;

endmodule // clk_mux
module clk_or2_cel(
output clkout, // OR output
input  clk1, // clock 1
input  clk2  // clock 2
);

assign clkout = clk1 | clk2;

endmodule // clk_or2_cel
module clk_den_flop(
input      clk, // clock
input      d,   // data input
input      den, // data enable
input      rb,  // Active low reset
output reg o    // data output
);

// Flop with data enable
always @(posedge clk or negedge rb)
  begin: o_register
    if(!rb)
      o <= 1'b0;
    else if(den)
      o <= d;
  end // block: o_register

endmodule // clk_den_flop
module dmux_cell(
output o,  // Output
input  d1, // Data 1
input  d2, // Data 2
input  s   // Data selection
);

// mux
assign o = s ? d1 : d2;

endmodule // dmux_cell
module clk_and3_cel(
output clkout, // AND output
input  clk1, // clock 1
input  clk2,  // clock 2
input  clk3  // clock 3
);

assign clkout = clk1 & clk2 & clk3;

endmodule // clk_and3_cel
module aib_bit_sync
  #(
    parameter DWIDTH = 1'b1,    // Sync Data input
    parameter [DWIDTH-1:0] RESET_VAL = {DWIDTH{1'b0}}  // Reset value
    )
    (
    input  wire              clk,     // clock
    input  wire              rst_n,   // async reset
    input  wire [DWIDTH-1:0] data_in, // data in
    output wire [DWIDTH-1:0] data_out // data out
     );

   reg [DWIDTH-1:0]  dff2;
   reg [DWIDTH-1:0]  dff1;

   always @(posedge clk or negedge rst_n)
      if (!rst_n) begin
         dff2     <= RESET_VAL; 
         dff1     <= RESET_VAL; 
      end
      else begin
         dff2     <= dff1;
         dff1     <= data_in;
      end

   assign data_out = dff2;


endmodule // aib_bit_sync
module aib_cdc_data_mux #(
parameter DWIDTH = 'd80   // Data bus width
)
(
// Inputs
input  [DWIDTH-1:0] dmux_in0, // Data input for dmux_sel = 1
input  [DWIDTH-1:0] dmux_in1, // Data input for dmux_sel = 0
input               dmux_sel, // Data selection
// Outputs
output [DWIDTH-1:0] dmux_out // Data mux output
);

genvar i;
generate
  for(i = 0; i < DWIDTH; i = i + 1)
    begin: dmux_out_gen
      dmux_cell dmux_cell(
      .d1 (dmux_in0[i]),  // Data selected when selection = 1
      .d2 (dmux_in1[i]),  // Data selected when selection = 0
      .s  (dmux_sel),     // Data selection
      .o  ( dmux_out[i])  // MUX output data
      );
    end
endgenerate

endmodule // aib_cdc_data_mux
module aib_rst_sync
  (
    input  clk,       // Destination clock of reset to be synced
    input  i_rst_n,   // Asynchronous reset input
    input  scan_mode, // Scan bypass for reset
    output sync_rst_n // Synchronized reset output
   
   );

wire prescan_sync_rst_n;

aib_bit_sync 
  #(.DWIDTH(1), .RESET_VAL(0)  ) 
i_sync_rst_n
  (
   .clk           (clk               ),
   .rst_n         (i_rst_n           ), 
   .data_in       (1'b1              ),
   .data_out      (prescan_sync_rst_n) 
   );

// Scan mux
dmux_cell rst_dmux_out(
.o  (sync_rst_n),         // Output
.d1 (i_rst_n),            // Data 1 (s=1)
.d2 (prescan_sync_rst_n), // Data 2 (s=0)
.s  (scan_mode)           // Data selection
);

endmodule // aib_rst_sync
module aib_fifo_and_sel #(
parameter DWIDTH = 80
)
(
output [DWIDTH-1:0] fifo_out_sel, // FIFO output ANDed with read enable
input               fifo_rd_en,   // FIFO read enable
input  [DWIDTH-1:0] fifo_rd_in    // FIFO data in write domain
);

// AND logic selects the asynchronous bus only when data is stable
assign fifo_out_sel = fifo_rd_in[DWIDTH-1:0] & {DWIDTH{fifo_rd_en}};

endmodule // aib_fifo_and_sel
module aib_bus_sync
  #(
    parameter                 DWIDTH =  1'b1,          // Data bus width
    parameter [DWIDTH-1:0] RESET_VAL = {DWIDTH{1'h0}}  // Reset value
    )
    (
    // Inputs
    input               src_clk,    // source clock
    input               dest_clk,   // destination clock
    input               src_rst_n,  // source async reset
    input               dest_rst_n, // destination async reset
    input  [DWIDTH-1:0] src_data,   // Source data input
    // Outputs
    output  reg[DWIDTH-1:0] dest_data_ff // destination data output
     );

wire src_req_sync;  // Data request in destination domain
wire if_ready;      // Indicates CDC interface ready
wire dest_ack_sync; // Destination acknowledge
wire dest_sample;   // Destination signal to sample source data

reg              src_req_ff;  // Source data request register
reg [DWIDTH-1:0] src_data_ff; // Source data register
reg              dest_ack_ff; // Destination acknowledge register

//------------------------------------------------------------------------------
//                             Source Domain Logic 
//------------------------------------------------------------------------------

// Data sample request
always @(posedge src_clk or negedge src_rst_n)
  begin: src_req_register
    if(!src_rst_n)
      src_req_ff <= 1'b0;
    else if(if_ready)
      src_req_ff <= ~src_req_ff;
  end // block: src_req_register

// Source data register
always @(posedge src_clk or negedge src_rst_n)
  begin: src_data_register
    if(!src_rst_n)
      src_data_ff[DWIDTH-1:0] <= RESET_VAL;
    else if(if_ready)
      src_data_ff[DWIDTH-1:0] <= src_data[DWIDTH-1:0];
  end // block: src_data_register

// Interace ready indication
assign if_ready = ~(src_req_ff ^ dest_ack_sync);

// Destination acknowledge synchronization
aib_bit_sync sync_ack_i(
// Inputs
.clk     (src_clk),     // clock
.rst_n   (src_rst_n),   // async reset
.data_in (dest_ack_ff), // data in
// Outputs
.data_out (dest_ack_sync) // data out
);

//------------------------------------------------------------------------------
//                             Source Domain Logic 
//------------------------------------------------------------------------------

// Source request synchronization
aib_bit_sync sync_req_i(
// Inputs
.clk     (dest_clk),   // clock
.rst_n   (dest_rst_n), // async reset
.data_in (src_req_ff), // data in
// Outputs
.data_out (src_req_sync)// data out
);

// Source acknowledge
always @(posedge dest_clk or negedge dest_rst_n)
  begin: dest_ack_register
    if(!dest_rst_n)
      dest_ack_ff <= 1'b0;
    else
      dest_ack_ff <= src_req_sync;
  end // block: dest_ack_register

// samples data in destination domain
assign dest_sample = src_req_sync ^ dest_ack_ff;


// Destination data
always @(posedge dest_clk or negedge dest_rst_n)
  begin: dest_data_register
    if(!dest_rst_n)
      dest_data_ff[DWIDTH-1:0] <= RESET_VAL;
    else if(dest_sample)
      dest_data_ff[DWIDTH-1:0] <= src_data_ff[DWIDTH-1:0];
  end // block: dest_data_register


endmodule // aib_bus_sync
module aib_bs_clk_gating(
// Inputs
input jtag_clk,          // JTAG clock
input jtag_capture_dr,   // Capture data register
input jtag_tx_scanen_in, // JTAG TX scan enable
input i_scan_mode,       // Scan mode
// Outputs
output tx_jtag_clk_g,    // JATG clock gated for transmit shift register
output rx_jtag_clk_g     // JATG clock gated for receive shift register
);

wire rx_jtag_clk_en; // RX JTAG clock enable

// RX JTAG clock enable
assign rx_jtag_clk_en = jtag_tx_scanen_in | jtag_capture_dr;

// TX JTAG clock gate
clk_gate_cel clk_gate_tx_jtag(
.clkout (tx_jtag_clk_g),     // Clock gated
.clk    (jtag_clk),          // Clock input
.en     (jtag_tx_scanen_in), // Clock enable
.te     (i_scan_mode)        // Test enable
); // TX JTAG clock gate

// RX JTAG clock gate
clk_gate_cel clk_gate_rx_jtag(
.clkout (rx_jtag_clk_g),    // Clock gated
.clk    (jtag_clk),         // Clock input
.en     (rx_jtag_clk_en),   // Clock enable
.te     (i_scan_mode)       // Test enable
); // RX JTAG clock gate

endmodule
module aib_fifo_rdata_buf #(
parameter DWIDTH  = 80  // FIFO Input data width
)
(
// Output
output reg [DWIDTH-1:0] fifo_rdata_ff, 
// Input
input [DWIDTH-1:0] fifo_rdata,
input            rd_clk,
input            rd_rst_n
);


always @(posedge rd_clk or negedge rd_rst_n)
  begin
    if(!rd_rst_n)
      fifo_rdata_ff <= {DWIDTH{1'b0}};
    else
      fifo_rdata_ff <= fifo_rdata;
  end

endmodule // aib_fifo_rdata_buf
module aib_bscan (
   input   odat_asyn_aib,       //async data RX from AIB 
   input   async_data_adap,     //async data TX from HSSI Adapter
   input   tx_async_en_adap,    // TX asynchronous enable from Adapter
   input   jtag_tx_scanen_in,   //JTAG shift DR, active high
   input   tx_jtag_clk_g,       // Gated clock for TX shift register
   input   rx_jtag_clk_g,       // Gated clock for RX shift register
   input   jtag_tx_scan_in,     //JTAG TX data scan in
   input   jtag_mode_in,        //JTAG mode select
   input   jtag_rstb_en,        //reset_en from TAP
   input   jtag_rstb,           //reset signal from TAP
   input   jtag_intest,         //intest from TAP

   output   jtag_rx_scan_out,   //JTAG TX scan chain output
   output   tx_async_en_aib,    // TX asynchronous enable to AIB pad
   output   odat_asyn_adap,     //async data RX to HSSI Adapter
   output   async_data_aib      //async data TX to AIB
);

reg [1:0]   tx_reg;
reg         rx_reg;
reg         rx_nreg;
wire [1:0]  tx_shift;  
wire [1:0]  tx_intst;  
wire        rx_shift; 

assign jtag_rx_scan_out = rx_nreg;

clk_mux async_data_aib_ckmux(
// Inputs
.clk1   (tx_reg[1]),        // s=1
.clk2   (async_data_adap),  // s=0
.s      (jtag_mode_in),
// Outputs
.clkout (async_data_aib)
);

assign tx_async_en_aib = jtag_mode_in ? tx_reg[0] : tx_async_en_adap;

clk_mux odat_asyn_adap_ckmux(
// Inputs
.clk1   (rx_reg),        // s=1
.clk2   (odat_asyn_aib), // s=0
.s      (jtag_intest),
// Outputs
.clkout (odat_asyn_adap)
);

assign tx_shift[0] = (jtag_tx_scanen_in) ? tx_reg[1] : tx_intst[0];

clk_mux tx_shift_4_ckmux(
// Inputs
.clk1   (jtag_tx_scan_in),  // s=1
.clk2   (tx_intst[1]),      // s=0
.s      (jtag_tx_scanen_in),
// Outputs
.clkout (tx_shift[1])
);

assign tx_intst[0] = (jtag_intest) ? tx_async_en_adap : tx_reg[0];

clk_mux tx_intst_4_ckmux(
// Inputs
.clk1   (async_data_adap), // s=1
.clk2   (tx_reg[1]),       // s=0
.s      (jtag_intest),
// Outputs
.clkout (tx_intst[1])
);

always @(posedge tx_jtag_clk_g)
  begin
    tx_reg <= tx_shift;
  end

clk_mux rx_shift_0_ckmux(
// Inputs
.clk1   (tx_reg[0]),          // s=1
.clk2   (odat_asyn_adap),  // s=0
.s      (jtag_tx_scanen_in),
// Outputs
.clkout (rx_shift)
);

always @(posedge rx_jtag_clk_g)
  begin
    rx_reg <= rx_shift;
  end

always @(negedge rx_jtag_clk_g)
  begin
    rx_nreg <= rx_reg;
  end

endmodule
module rx_offset_cal_fsm #(parameter DATAWIDTH = 44)
		    (
		     input sys_clk,
		     input rst_n,
		     input rx_offset_ovrd_sel,
		     input rx_offset_cal_done_ovrd,
		     input [4:0]rx_offset_cal_code_ovrd,
		     input start_cal,
		     input [(2*DATAWIDTH)-1:0]ana_rxdata,
   		     input       scan_mode,         // Scan mode
   		     input       clk_div_ld,        // Clock divider enable from avalon interface
   		     input       clk_div_1_onehot,  // Onehot enable for clock divided by 1
   		     input       clk_div_2_onehot,  // Onehot enable for clock divided by 2
   		     input       clk_div_4_onehot,  // Onehot enable for clock divided by 4
   		     input       clk_div_8_onehot,  // Onehot enable for clock divided by 8
		     output wire cal_done,
		     output wire [(2*DATAWIDTH)-1:0][4:0]offs_cal_code,
		     output wire rxoffset_clk_div_ld_ack_ff
		    );

wire [(2*DATAWIDTH)-1:0]      cal_done_int;
wire                          sys_div_clk;
wire [(2*DATAWIDTH)-1:0][4:0] offs_cal_code_intr;
wire [(2*DATAWIDTH)-1:0][4:0] offs_cal_code_pre;

genvar i;
//Data Muxing b/w Register Data and internal logic data

generate
  for(i=0;i<(2*DATAWIDTH);i=i+1)
    begin: offs_cal_code_pre_gen
      assign offs_cal_code_pre[i] = rx_offset_ovrd_sel ? rx_offset_cal_code_ovrd[4:0] : offs_cal_code_intr[i];
    end
endgenerate // block: offs_cal_code_pre_gen

generate
  for(i=0;i<(2*DATAWIDTH);i=i+1)
    begin: offs_cal_code_gen
      assign offs_cal_code[i][4:0] = scan_mode ? 5'h0 : offs_cal_code_pre[i];
    end // block: offs_cal_code_gen
endgenerate

assign cal_done = rx_offset_ovrd_sel ? rx_offset_cal_done_ovrd : (&cal_done_int);

//==============================
//Clock Divider for Div-1,2,4,8
//==============================
aib_clk_div_roffcal i_aib_clk_div_roffcal(
.rst_n(rst_n),
.clk(sys_clk),
.scan_mode(scan_mode),
.clk_div_ld(clk_div_ld),
.clk_div_1_onehot(clk_div_1_onehot),
.clk_div_2_onehot(clk_div_2_onehot),
.clk_div_4_onehot(clk_div_4_onehot),
.clk_div_8_onehot(clk_div_8_onehot),
.clk_out(sys_div_clk),
.clk_div_ld_ack_ff(rxoffset_clk_div_ld_ack_ff)
);

/*======================================
==========Instantiation of Offset_cal===
========================================*/

generate
 for(i=0;i<88;i=i+1)
  begin: offset_cal_inst_gen
   offset_cal i_offset_cal(
		.sys_clk(sys_div_clk),
		.rst_n(rst_n),
		.start_cal(start_cal),
		.cal_data(ana_rxdata[i]),
		.cal_done(cal_done_int[i]),
		.offs_cal_code(offs_cal_code_intr[i][4:0])
   );
  end // block: offset_cal_inst_gen
endgenerate

endmodule
module offset_cal(
		  input sys_clk,
		  input rst_n,
		  input start_cal,
		  input cal_data,
		  output reg cal_done,
		  output reg [4:0]offs_cal_code 
		);

parameter START      = 3'b000,
          UP_COUNT   = 3'b001,
          COUNT_ROLL = 3'b010,
          DOWN_COUNT = 3'b011,
	  STOP       = 3'b100;

reg [2:0] offset_curst, offset_nxst;
reg [4:0] edge_detect_up_value, edge_detect_down_value;
reg [1:0] comp_data;
reg [5:0] sum;

always@(posedge sys_clk or negedge rst_n)
 begin
  if(!rst_n)
   offset_curst[2:0] <= 3'b000;
  else
   offset_curst[2:0] <= offset_nxst[2:0];
 end

always@(posedge sys_clk or negedge rst_n)
  if(!rst_n)
   begin
    edge_detect_up_value   <= 5'b0_0000;
    edge_detect_down_value <= 5'b0_0000;
    cal_done               <= 1'b0;
    offs_cal_code          <= 4'b0000;
   end
  else
   begin
    case(offset_curst)
     START      : begin
		   offs_cal_code <= 5'b0_0000;
		   comp_data     <= 2'b00;
		   sum           <= 5'b0_0000;
	          end
     UP_COUNT   : begin
		   comp_data <= {comp_data[0], cal_data};
     		   if(comp_data[0] != comp_data[1])
		    edge_detect_up_value[4:0] <= offs_cal_code[4:0]-1'b1;
		   else
		    edge_detect_up_value[4:0] <= edge_detect_up_value[4:0];

		    offs_cal_code <= offs_cal_code + 1'b1;
		  end
     COUNT_ROLL : begin
		   offs_cal_code <= 5'd31;
 		  end
     DOWN_COUNT : begin
		   comp_data <= {comp_data[0], cal_data};
     		   if(comp_data[0] != comp_data[1])
		    edge_detect_down_value[4:0] <= offs_cal_code[4:0]+1'b1;
		   else
		    edge_detect_down_value[4:0] <= edge_detect_down_value[4:0];
		   if(offs_cal_code == 5'b0_0000)
		    offs_cal_code <= 5'b0_0000;
		   else
		    offs_cal_code <= offs_cal_code - 1'b1;
		  end
     STOP       : begin
		   sum           <= edge_detect_up_value + edge_detect_down_value;
		   offs_cal_code <= sum >> 1;
		   cal_done      <= 1'b1;
		  end
     default    : begin
		   offs_cal_code <= 5'b0_0000;
		   comp_data     <= 2'b00;
		   sum           <= 5'b0_0000;
   	          end
    endcase
   end

 always@(*)
  begin
   offset_nxst = 3'b000;
    case(offset_curst)
     START      : begin
		   if(start_cal)
		    offset_nxst = UP_COUNT;
		   else
		    offset_nxst = START;
   	          end
     UP_COUNT   : begin
		   if(offs_cal_code == 5'd31)
		    offset_nxst = COUNT_ROLL;
		   else
		    offset_nxst = UP_COUNT;
	          end
     COUNT_ROLL : begin
		   if(offs_cal_code == 5'd31)
		    offset_nxst = DOWN_COUNT;
		   else
		    offset_nxst = COUNT_ROLL;
 		  end
     DOWN_COUNT : begin
		   if(offs_cal_code == 5'd0)
		    offset_nxst  = STOP;
		   else
		    offset_nxst  = DOWN_COUNT;
		  end
     STOP       : begin
		   if(!start_cal)
		    offset_nxst  = START;
		   else
		    offset_nxst  = STOP;
		   end
     default    : begin
		   if(start_cal)
		    offset_nxst = UP_COUNT;
		   else
		    offset_nxst = START;
   	          end
    endcase
  end

endmodule
module aib_dll_ctrl_logic(
		    	  input      [2:0] freq_range_sel,
		    	  output reg [2:0] trim_ctrl_bits
		         );

always@(*)
 begin
  case(freq_range_sel)
   3'b000 : trim_ctrl_bits = 3'b100;
   3'b001 : trim_ctrl_bits = 3'b101;
   3'b010 : trim_ctrl_bits = 3'b110;
   3'b011 : trim_ctrl_bits = 3'b111;
   3'b100 : trim_ctrl_bits = 3'b000;
   3'b101 : trim_ctrl_bits = 3'b001;
   3'b110 : trim_ctrl_bits = 3'b010;
   3'b111 : trim_ctrl_bits = 3'b011;
  endcase
 end

//========================Frequency LUT======================================
//Freq_range_sel(GHz)  Min    Max        Trim bits(Current trim and cap trim)
//	3'b000         3.2     2.6        3'b100
//	3'b001         2.6     2.1        3'b101
//	3'b010         2.1     1.7        3'b110
//	3'b011         1.7     1.4        3'b111
//	3'b100         1.4     1.1        3'b000
//	3'b101         1.1     0.85       3'b001
//	3'b110         0.85    0.65       3'b010
//	3'b111         0.65    0.50       3'b011
//========================Frequency LUT======================================


endmodule
module aib_redundancy_logic(
        input  idata_in0_even,        
        input  idata_in1_even,        
        output wire data_out_even,    

        input  idata_in0_odd,         
        input  idata_in1_odd,         
        output wire data_out_odd,     

        input async_in0,              
        input async_in1,              
        output wire async_out,        

        input tx_en0,                 
        input tx_en1,                 
        output wire tx_en_out,        

        input rx_en0,                 
        input rx_en1,                 
        output wire rx_en_out,        

        input async_tx_en0,           
        input async_tx_en1,           
        output wire async_tx_en_out,  

        input async_rx_en0,
        input async_rx_en1,
        output wire async_rx_en_out,

        input sdr_mode_en0,
        input sdr_mode_en1,
        output wire sdr_mode_en_out,

        input  wkpu_en_in0,
        input  wkpu_en_in1,
        output wkpu_en_out,

        input  wkpd_en_in0,
        input  wkpd_en_in1,
        output wkpd_en_out,

        input shift_en
        );

assign data_out_even = shift_en ? idata_in1_even  : idata_in0_even;
assign data_out_odd  = shift_en ? idata_in1_odd   : idata_in0_odd ;

assign async_out     = shift_en ? async_in1       : async_in0 ;

assign tx_en_out     = shift_en ? tx_en1 : tx_en0 ;
assign rx_en_out     = shift_en ? rx_en1 : rx_en0 ;

assign async_tx_en_out     = shift_en ? async_tx_en1 : async_tx_en0 ;
assign async_rx_en_out     = shift_en ? async_rx_en1 : async_rx_en0 ;

assign sdr_mode_en_out     = shift_en ? sdr_mode_en1 : sdr_mode_en0 ;

assign wkpu_en_out = shift_en ? wkpu_en_in1 : wkpu_en_in0;
assign wkpd_en_out = shift_en ? wkpd_en_in1 : wkpd_en_in0;

endmodule
module aib_rx_dbi (
   // Inputs
   input  wire        rst_n,    // Asynchronous reset
   input  wire        clk,      // Clock
   input  wire [79:0] data_in,  // Data input before DBI logic
   input  wire        dbi_en,   // Data inversion enable
   // Outputs
   output wire [79:0] data_out  // Output data after DBI logic
   );

wire [3 :0] dbi_calc;     // Bits 79, 78, 39 and 38 used on DBI calculation
wire [37:0] dbi_dat_lo;   // Low word with DB calculation - bits from 37-0
wire [37:0] dbi_dat_hi;   // High word with DB calculation - bits from 77-40
reg  [79:0] dbi_data_out; // Register data after DBI calculation

// DBI output mux selects data accoding to DBI enable
assign data_out = dbi_en? dbi_data_out : data_in;

// Data bits 79, 78, 39 and 38 used on DBI calculation
assign dbi_calc = {data_in[79], data_in[78], data_in[39], data_in[38]};

// Calculation of DBI low word and DBI high word
genvar j; // Generate index
generate
for (j=0; j<19; j=j+1)
  begin:data_out_gen
    assign dbi_dat_lo[2*j]   = data_in[2*j]     ^dbi_calc[0];
    assign dbi_dat_lo[2*j+1] = data_in[2*j+1]   ^dbi_calc[1];
    assign dbi_dat_hi[2*j]   = data_in[2*j+40]  ^dbi_calc[2];
    assign dbi_dat_hi[2*j+1] = data_in[2*j+1+40]^dbi_calc[3];
  end // block data_out_gen
endgenerate

// Output register to latch DBI calculation
always @(posedge clk or negedge rst_n)
  begin: dbi_data_out_register
    if (!rst_n)
      begin
        dbi_data_out <= 80'h0;
      end
    else
      begin
        dbi_data_out <= {dbi_calc[3:2], dbi_dat_hi, dbi_calc[1:0], dbi_dat_lo};
      end
  end // block: dbi_data_out_register

endmodule // aib_rx_dbi
module aib_adapter_rxchnl(
   // Outputs
output wire [319:0] rx_adapt_dout, // FIFO mode data output
output wire [79:0]  data_out,   // Register mode data output
output wire         align_done, // Word Mark alignment done
   // Inputs
input        atpg_mode,      // Scan enabled
input        m_gen2_mode,    // Generation 2.0 mode
input        rxrd_fifo_rstn, // RX FIFO read reset
input        rxwr_rstn,      // RX write reset
input        rxwr_fifo_rstn, // RX FIFO write reset
input [79:0] din,            // Data input from io buffer
input        rxfifo_rd_clk,  // Read clock
input        rxfifo_wrclk,   // FIFO write clock
input [1:0]  r_rx_fifo_mode, // FIFO mode register
input [4:0]  rx_align_threshold, // RX FIFO WAM threshold
input [3:0]  r_rx_phcomp_rd_delay, // Phase compensation register
input        r_rx_wa_en,      // RX word aligment enable
input        rx_wa_mode_sync, // Rx word alignment mode bit
input        r_rxswap_en,     // RX swapping enable
input [4:0]  r_rx_mkbit,      // Selection of Rx word mark bit
input        r_rx_dbi_en      // Enable for Rx data bus inversion
   );

// Wires
wire [79:0]  dbi_dout;             // Output of data bus inversion
wire [79:0]  rx_fifo_data_out_sel; // Swapped data or input data to FIFO
wire [319:0] rx_fifo_data_out;     // Output from FIFO registered

// FIFO data output
assign rx_adapt_dout =  {rx_fifo_data_out[319:80], rx_fifo_data_out_sel};

// Data output after DBI logic
assign data_out   =  dbi_dout;

// Data after swapping logic.
// Swapping is used only for FIFO 2x with generation 1
assign rx_fifo_data_out_sel[79:0] =
  ((r_rx_fifo_mode==2'b01) & r_rxswap_en & ~m_gen2_mode) ?
    {rx_fifo_data_out[79],
     rx_fifo_data_out[38:0],
     rx_fifo_data_out[39],
     rx_fifo_data_out[78:40]} :
     rx_fifo_data_out[79:0];

// DBI logic
aib_rx_dbi rx_dbi (
 // Inputs
 .rst_n(rxwr_rstn),    // Async reset
 .clk(rxfifo_wrclk),   // FIFO write clock
 .data_in(din),        // Data input
 .dbi_en(r_rx_dbi_en), // Data bus inversion
 // Outputs
 .data_out(dbi_dout)   // Data bus inversion output
);

// RX FIFO data path logic
aib_adapt_rx_fifo aib_adapt_rx_fifo(
// Outputs
.fifo_dout         (rx_fifo_data_out), // FIFO data output registered
.align_done        (align_done),       // Word mark alignment done
// Inputs
.wr_rst_n          (rxwr_fifo_rstn), // Rx FIFO write reset   
.wr_clk            (rxfifo_wrclk),   // Rx FIFO write clock
.fifo_din          (dbi_dout),       // FIFO input
.rd_rst_n          (rxrd_fifo_rstn), // Rx FIFO read reset
.rd_clk            (rxfifo_rd_clk),   // FIFO Read clock
.scan_en           (atpg_mode),      // Scan enable
.m_gen2_mode       (m_gen2_mode),    // Generation mode
.r_fifo_mode       (r_rx_fifo_mode[1:0]),  // RX FIFO mode configuration
.rx_align_threshold (rx_align_threshold[4:0]), // RX FIFO WAM threshold
.r_phcomp_rd_delay (r_rx_phcomp_rd_delay[3:0]), // RX FIFO phase compensation
.r_mkbit           (r_rx_mkbit[4:0]),      // RX Mark bits
.rx_wa_mode_sync   (rx_wa_mode_sync),      // Word alignment mode bit
.r_wa_en           (r_rx_wa_en)            // Word alignment enable
);

endmodule // aib_adapter_rxchnl
module aib_adapter_txchnl(
   // Outputs
   output wire [79:0] dout, // AIB Data output
   // Inputs
   input              atpg_mode,      // Scan enable
   input              txwr_fifo_rstn, // Tx write fifo reset
   input              txrd_rstn,      // Tx read reset
   input              txrd_fifo_rstn, // Tx read fifo reset
   input              m_gen2_mode,    // AIB Generation 2.0 indication
   input              txfifo_wr_clk,  // Write clock
   input              tx_clk_adapter, // TX DLL clock to adapter
   input [319:0]      tx_adapt_din,   // FIFO mode data input
   input [79:0]       data_in,        // Register mode data input
   input              r_tx_dbi_en,    // Enable for tx data bus inversion
   input [1:0]        r_tx_fifo_mode, // TX FIFO mode register
   input [3:0]        r_tx_phcomp_rd_delay, // TX phase compensation register
   input              r_txswap_en,    // TX swapping enable
   input              r_tx_wm_en,     // Tx word mark enable
   input  [4:0]       r_tx_mkbit      // Selection of word mark bit
   );

wire [79:0]  fifo_dout;      // Output data from FIFO
wire [79:0]  merge_dout;     // Output slection based on operation mode
wire [79:0]  data_in_f_sel;  // Swapped data or input data to FIFO 

//Mux for bypass mode data and fifo data
assign merge_dout[79:0]= (r_tx_fifo_mode == 2'b11) ?
                          data_in[79:0] :
                          fifo_dout[79:0];

//Data bus inversion logic (DBI)
aib_tx_dbi txdbi 
  (
    .rst_n(txrd_rstn),     // Async, reset
    .clk(tx_clk_adapter),    // Near side forwarded clock
    .dbi_en(r_tx_dbi_en),  // DBI enable
    .data_in(merge_dout),  // Data to be inverted by DBI logic
    .data_out(dout)        // Data after DBI logic

  );
 
// Swapping logic used only in Gen 1 mode and 2xFIFO    
assign data_in_f_sel[79:0] =
     ((r_tx_fifo_mode == 2'b01) & r_txswap_en & ~m_gen2_mode)  ? 
       {tx_adapt_din[79],
        tx_adapt_din[38:0],
        tx_adapt_din[39],
        tx_adapt_din[78:40]} :
        tx_adapt_din[79:0];

// TX FIFO data path logic
aib_adapt_tx_fifo aib_adapt_tx_fifo (
  // Outputs
  .fifo_dout   (fifo_dout[79:0]), // FIFO data output
  // Inputs
  .data_in  ({tx_adapt_din[319:80], data_in_f_sel[79:0]}), // FIFO data input
  .r_fifo_mode        (r_tx_fifo_mode[1:0]),  // FIFO mode register
  .r_phcomp_rd_delay  (r_tx_phcomp_rd_delay[3:0]), // Tx phase compensation 
  .m_gen2_mode        (m_gen2_mode),          // Generation 2.0 mode
  .r_wm_en            (r_tx_wm_en),           // Tx swapping 
  .r_mkbit            (r_tx_mkbit[4:0]),      // Tx Mark bits
  .scan_en            (atpg_mode),            // Scan enable
  .wr_clk             (txfifo_wr_clk),        // Tx write clock
  .wr_rst_n           (txwr_fifo_rstn),       // Tx FIFO write reset
  .rd_clk             (tx_clk_adapter),       // TX DLL clock to adapter
  .rd_rst_n           (txrd_fifo_rstn)        // Tx FIFO read reset
);

endmodule // aib_adapter_txchnl
module aib_adapttxdp_fifo_ram
  #(
    parameter DWIDTH = 'd80,             // FIFO Input data width 
    parameter DEPTH  = 'd16              // FIFO Depth 
    )
(
    input  wire                wr_clk,     // Write Domain Clock
    input  wire                wr_en,      // write enable
    input  wire		       wr_rst_n,   // Write Domain Reset 
    input  wire [DEPTH-1:0]    wr_ptr,     // Write Pointer
    input  wire [DWIDTH*4-1:0] wr_data,    // Write Data In
    input  wire [DEPTH-1:0]    rd_ptr,     // Read Pointer
    output reg  [DWIDTH*4-1:0] rd_data   // Read Data

);

   //********************************************************************
   // Infer Memory or use Dual Port Memory from Quartus/ASIC Memory
   //********************************************************************
   
   integer		m;
   integer		i;
   reg [DWIDTH*4-1:0]   fifo_mem [DEPTH-1:0];
   
   always @(negedge wr_rst_n or posedge wr_clk) begin
      if (~wr_rst_n) begin
         for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1)
            fifo_mem[m] <= 'd0;	
      end 
      else if (wr_en) begin
         for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1) begin
           if (wr_ptr[m]) begin
             fifo_mem[m] <= wr_data;
           end  
         end   
      end
   end
   
//assign rd_data = fifo_mem[rd_ptr];

  always @ *
    begin: data_out 
      rd_data = fifo_mem[0];
      for (i='d0; i<=(DEPTH-1'b1); i=i+1'b1) begin
        if (rd_ptr[i]) begin
          rd_data = fifo_mem[i];
      end       
    end   
  end 


endmodule
module aib_aux_channel 
   (
    // AIB IO Bidirectional 
    inout wire          iopad_dev_dect,
    inout wire          iopad_dev_dectrdcy,
    inout wire          iopad_dev_por,
    inout wire          iopad_dev_porrdcy,

    input               m_por_ovrd, //Master onlhy input, it overrides the por signal. For slave, it is tied to "0"
    input               m_device_detect_ovrd, //Slave only input, it overrides the device_detect signal. For Master, it is tied to "0"
    output wire         por_ms,
    output wire         m_device_detect,
    input               por_sl,
//  output wire         osc_clk,
    input               ms_nsl, //"1", this is a Master. "0", this is a Slave
    input               irstb // Output buffer tri-state enable
    );

/*
aib_aliasd aliaspor ( .sig_red(iopad_dev_porrdcy), .sig_in(iopad_dev_por));
aib_aliasd aliasdet ( .sig_red(iopad_dev_dectrdcy), .sig_in(iopad_dev_dect));
*/
   wire device_detect_oe;
   wire device_detect_ie;
   
   wire por_oe;
   wire por_ie;

   wire device_detect_sl_main;

   wire por_ms_main;

   assign m_device_detect = device_detect_sl_main | m_device_detect_ovrd;

   assign por_ms = por_ms_main & m_por_ovrd;
   
   assign device_detect_oe = (ms_nsl == 1'b1) ? 1'b1 : 1'b0;
   assign device_detect_ie = !device_detect_oe;

   assign por_oe = (ms_nsl == 1'b1) ? 1'b0 : 1'b1;
   assign por_ie = !por_oe;

	   aib_io_buffer u_device_detect 
	     (
	      // Tx Path
	      .ilaunch_clk (1'b0),
	      .irstb       (irstb),
	      .idat0       (1'b1),
	      .idat1       (1'b1),
	      .async_data  (1'b1),
	      .oclkn       (),

	      // Rx Path
	      .iclkn       (1'b0),
	      .inclk       (1'b0),
	      .inclk_dist  (1'b0),
	      .oclk        (),
	      .oclk_b      (),
	      .odat0       (),
	      .odat1       (),
	      .odat_async  (device_detect_sl_main),

	      // Bidirectional Data 
	      .io_pad      (iopad_dev_dect),

	      // I/O configuration
	      .async       (1'b1),
	      .ddren       (1'b0),
	      .txen        (device_detect_oe),
	      .rxen        (device_detect_ie),
	      .weaken      (device_detect_ie),
	      .weakdir     (1'b0)
	      );

	   aib_io_buffer u_device_por 
	     (
	      // Tx Path
	      .ilaunch_clk (1'b0),
	      .irstb       (irstb),
	      .idat0       (por_sl),
	      .idat1       (por_sl),
	      .async_data  (por_sl),
	      .oclkn       (),

	      // Rx Path
	      .iclkn       (1'b0),
	      .inclk       (1'b0),
	      .inclk_dist  (1'b0),
	      .oclk        (),
	      .oclk_b      (),
	      .odat0       (),
	      .odat1       (),
	      .odat_async  (por_ms_main),

	      // Bidirectional Data 
	      .io_pad      (iopad_dev_por),

	      // I/O configuration
	      .async       (1'b1),
	      .ddren       (1'b0),
	      .txen        (por_oe),
	      .rxen        (por_ie),
	      .weaken      (por_ie),
	      .weakdir     (1'b1)
	      );


endmodule // aib_aux_channel
module aib_adaptrxdbi_rxdp (

   input  wire                  rst_n,
   input  wire                  clk,
   input  wire [79:0]		data_in,	
   input  wire                  dbi_en,		

   output wire [79:0]		data_out	 
   );

   wire [3:0] dbi_calc;
   reg  [79:0] last_din, dbi_data_out;
   wire [37:0] dbi_dat_lo, dbi_dat_hi;

   assign data_out = dbi_en? dbi_data_out : data_in;
   assign dbi_calc = {data_in[79], data_in[78], data_in[39], data_in[38]};

   genvar j;
   generate
   for (j=0; j<19; j=j+1) begin:data_out_gen
      assign dbi_dat_lo[2*j]   = data_in[2*j]     ^dbi_calc[0];
      assign dbi_dat_lo[2*j+1] = data_in[2*j+1]   ^dbi_calc[1];
      assign dbi_dat_hi[2*j]   = data_in[2*j+40]  ^dbi_calc[2];
      assign dbi_dat_hi[2*j+1] = data_in[2*j+1+40]^dbi_calc[3];
   end
   endgenerate

   always @(posedge clk or negedge rst_n)
   begin
    if (!rst_n)
     begin
      dbi_data_out <= 80'h0;
     end
    else
      dbi_data_out <= {dbi_calc[3:2], dbi_dat_hi, 
                       dbi_calc[1:0], dbi_dat_lo}; 
   end


endmodule
module aib_adaptrxdp_fifo_ram
  #(
    parameter DWIDTH = 'd80,             // FIFO Input data width 
    parameter DEPTH  = 'd16              // FIFO Depth 
    )
(
    input  wire                wr_clk,     // Write Domain Clock
    input  wire		       wr_rst_n,   // Write Domain Reset 
    input  wire                wr_en,      // Write Data Enable
    input  wire [DEPTH-1:0]    wr_ptr,     // Write Pointer
    input  wire [DWIDTH*4-1:0] wr_data,    // Write Data In
    input  wire [DEPTH-1:0]    rd_ptr,     // Read Pointer
    output reg  [DWIDTH*4-1:0] rd_data   // Read Data

);

   //********************************************************************
   // Infer Memory or use Dual Port Memory from Quartus/ASIC Memory
   //********************************************************************

   wire 	[DEPTH-1:0]	rd_ptr2;   
   integer		m;
   integer		i, j;
   reg [DWIDTH*4-1:0]   fifo_mem [DEPTH-1:0];
   
   always @(negedge wr_rst_n or posedge wr_clk) begin
      if (~wr_rst_n) begin
         for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1)
            fifo_mem[m] <= 'd0;	
      end 
      else if (wr_en) begin
         for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1) begin
           if (wr_ptr[m]) begin
             fifo_mem[m] <= wr_data;
             end  
         end   
      end
   end

   
   always @ *
   begin: data_out 
     rd_data = fifo_mem[0];
     for (i='d0; i<=(DEPTH-1'b1); i=i+1'b1) begin
       if (rd_ptr[i]) begin
         rd_data = fifo_mem[i];
       end       
     end   
   end 
      
   
endmodule
module ao486_rst_controller
  (
   input wire        clk_sys,
   input wire        rst,
   output reg        ao486_rst,

   input wire [1:0]  address,
   input wire        write,
   input wire [31:0] writedata
   );

    always @(posedge clk_sys) begin
        if(rst) begin
            ao486_rst <= 1;
        end else begin
            if(write && writedata[0] == 1'b0 && address == 4'b0000)
              ao486_rst <= 0;
            else if(write && writedata[0] == 1'b1 && address == 4'b0000)
              ao486_rst <= 1;
        end
    end
endmodule
module simple_biclk_bidir_ram
  #(parameter width = 1,
    parameter widthad = 1)

    (
     input                  clk,

     input [widthad-1:0]    address_a,
     input                  wren_a,
     input [width-1:0]      data_a,
     output reg [width-1:0] q_a,

     input                  clk2,
     input [widthad-1:0]    address_b,
     output reg [width-1:0] q_b
     );

    reg [width-1:0]         mem [(2**widthad)-1:0];

    always @(posedge clk) begin
        if(wren_a) mem[address_a] <= data_a;

        q_a <= mem[address_a];
    end

    always @(posedge clk2) begin
        q_b <= mem[address_b];
    end

endmodule
module to_driver_sd_avs(
                        input wire         clk_sys,
                        input wire         rst,
                        input wire         ao486_rst,

                        // input hdd_avalon_master
                        input wire [31:0]  hdd_avalon_master_address,
                        input wire         hdd_avalon_master_read,
                        output wire [31:0] hdd_avalon_master_readdata,
                        input wire         hdd_avalon_master_write,
                        input wire [31:0]  hdd_avalon_master_writedata,
                        output wire        hdd_avalon_master_waitrequest,
                        output reg         hdd_avalon_master_readdatavalid,

                        // input bios_loader
                        input wire [31:0]  bios_loader_address,
                        input wire         bios_loader_read,
                        output wire [31:0] bios_loader_readdata,
                        input wire         bios_loader_write,
                        input wire [31:0]  bios_loader_writedata,
                        output wire        bios_loader_waitrequest,
                        input wire [3:0]   bios_loader_byteenable,

                        // output driver_sd_avs
                        output wire [1:0]  driver_sd_avs_address,
                        output wire        driver_sd_avs_read,
                        input wire [31:0]  driver_sd_avs_readdata,
                        output wire        driver_sd_avs_write,
                        output wire [31:0] driver_sd_avs_writedata
                        );

    assign driver_sd_avs_address   = (~ao486_rst) ? hdd_avalon_master_address[3:2] : bios_loader_address[3:2];
    assign driver_sd_avs_read      = (~ao486_rst) ? hdd_avalon_master_read : bios_loader_read && bios_loader_address[31:4] == 28'h0;
    assign driver_sd_avs_write     = (~ao486_rst) ? hdd_avalon_master_write : bios_loader_write && bios_loader_address[31:4] == 28'h0;
    assign driver_sd_avs_writedata = (~ao486_rst) ? hdd_avalon_master_writedata : bios_loader_writedata;

    assign hdd_avalon_master_readdata = (~ao486_rst) ? driver_sd_avs_readdata : 0;
    assign hdd_avalon_master_waitrequest = 0;
    always @(posedge clk_sys) hdd_avalon_master_readdatavalid <= (~ao486_rst) ? driver_sd_avs_read : 0;

    assign bios_loader_readdata = (~ao486_rst) ? 0 : driver_sd_avs_readdata;
    assign bios_loader_waitrequest = 0;

endmodule
module GEN( input wire  CLK_IN,
            input wire  RST_X_IN,
            output wire CLK_OUT,
            output wire VGA_CLK_OUT,
            output wire RST_X_OUT
            );

    wire                LOCKED, VLOCKED, CLK_IBUF;
    wire                RST_X_BUF;

    clk_wiz_0 clkgen(CLK_IN, CLK_OUT, VGA_CLK_OUT, LOCKED);
    RSTGEN rstgen(CLK_OUT, (RST_X_IN & LOCKED), RST_X_OUT);
endmodule
module RSTGEN(CLK, RST_X_I, RST_X_O);
    input  CLK, RST_X_I;
    output RST_X_O;

    reg [23:0] cnt;
    assign RST_X_O = cnt[23];

    always @(posedge CLK or negedge RST_X_I) begin
        if      (!RST_X_I) cnt <= 0;
        else if (~RST_X_O) cnt <= (cnt + 1'b1);
    end
endmodule
module clk_wiz_0
  (
   // Clock in ports
   input  clk_in1,
   // Clock out ports
   output clk_out1,
   output clk_out2,
   // Status and control signals
   output locked
   );

    clk_wiz_0_clk_wiz inst
      (
       // Clock in ports
       .clk_in1(clk_in1),
       // Clock out ports
       .clk_out1(clk_out1),
       .clk_out2(clk_out2),
       // Status and control signals
       .locked(locked)
       );

endmodule
module RSTGEN(CLK, RST_X_I, RST_X_O);
    input  CLK, RST_X_I;
    output RST_X_O;

    reg [7:0] cnt;
    assign RST_X_O = cnt[7];

    always @(posedge CLK or negedge RST_X_I) begin
        if      (!RST_X_I) cnt <= 0;
        else if (~RST_X_O) cnt <= (cnt + 1'b1);
    end
endmodule
module clk_wiz_0 (
	inclk0,
	c0,
	c1,
	locked);

	input	  inclk0;
	output	  c0;
	output	  c1;
	output	  locked;

endmodule
module mig(ddr2_dq, ddr2_dqs_n, ddr2_dqs_p, ddr2_addr, ddr2_ba, ddr2_ras_n, ddr2_cas_n, ddr2_we_n, ddr2_ck_p, ddr2_ck_n, ddr2_cke, ddr2_cs_n, ddr2_dm, ddr2_odt, sys_clk_i, app_addr, app_cmd, app_en, app_wdf_data, app_wdf_end, app_wdf_mask, app_wdf_wren, app_rd_data, app_rd_data_end, app_rd_data_valid, app_rdy, app_wdf_rdy, app_sr_req, app_ref_req, app_zq_req, app_sr_active, app_ref_ack, app_zq_ack, ui_clk, ui_clk_sync_rst, init_calib_complete, device_temp_i, sys_rst)
/* synthesis syn_black_box black_box_pad_pin="ddr2_dq[15:0],ddr2_dqs_n[1:0],ddr2_dqs_p[1:0],ddr2_addr[12:0],ddr2_ba[2:0],ddr2_ras_n,ddr2_cas_n,ddr2_we_n,ddr2_ck_p[0:0],ddr2_ck_n[0:0],ddr2_cke[0:0],ddr2_cs_n[0:0],ddr2_dm[1:0],ddr2_odt[0:0],sys_clk_i,app_addr[26:0],app_cmd[2:0],app_en,app_wdf_data[127:0],app_wdf_end,app_wdf_mask[15:0],app_wdf_wren,app_rd_data[127:0],app_rd_data_end,app_rd_data_valid,app_rdy,app_wdf_rdy,app_sr_req,app_ref_req,app_zq_req,app_sr_active,app_ref_ack,app_zq_ack,ui_clk,ui_clk_sync_rst,init_calib_complete,device_temp_i[11:0],sys_rst" */;
  inout [15:0]ddr2_dq;
  inout [1:0]ddr2_dqs_n;
  inout [1:0]ddr2_dqs_p;
  output [12:0]ddr2_addr;
  output [2:0]ddr2_ba;
  output ddr2_ras_n;
  output ddr2_cas_n;
  output ddr2_we_n;
  output [0:0]ddr2_ck_p;
  output [0:0]ddr2_ck_n;
  output [0:0]ddr2_cke;
  output [0:0]ddr2_cs_n;
  output [1:0]ddr2_dm;
  output [0:0]ddr2_odt;
  input sys_clk_i;
  input [26:0]app_addr;
  input [2:0]app_cmd;
  input app_en;
  input [127:0]app_wdf_data;
  input app_wdf_end;
  input [15:0]app_wdf_mask;
  input app_wdf_wren;
  output [127:0]app_rd_data;
  output app_rd_data_end;
  output app_rd_data_valid;
  output app_rdy;
  output app_wdf_rdy;
  input app_sr_req;
  input app_ref_req;
  input app_zq_req;
  output app_sr_active;
  output app_ref_ack;
  output app_zq_ack;
  output ui_clk;
  output ui_clk_sync_rst;
  output init_calib_complete;
  input [11:0]device_temp_i;
  input sys_rst;
endmodule
module mig_7series_v2_0_data_prbs_gen #
  (
    parameter TCQ           = 100,

    parameter EYE_TEST   = "FALSE",
    parameter PRBS_WIDTH = 32,                                                                       // "SEQUENTIAL_BUrst_i"
    parameter SEED_WIDTH = 32    
   )
  (
   input           clk_i,
   input           clk_en,
   input           rst_i,
   input           prbs_seed_init,  // when high the prbs_x_seed will be loaded
   input [PRBS_WIDTH - 1:0]  prbs_seed_i,
   
   output  [PRBS_WIDTH - 1:0]  prbs_o     // generated address
  );
  
reg [PRBS_WIDTH - 1 :0] prbs;  
reg [PRBS_WIDTH :1] lfsr_q;
integer i;



always @ (posedge clk_i)
begin
   if (prbs_seed_init && EYE_TEST == "FALSE"  || rst_i )  //reset it to a known good state to prevent it locks up
//   if (rst_i )  //reset it to a known good state to prevent it locks up

      begin
        lfsr_q[4:1] <= #TCQ   prbs_seed_i[3:0] | 4'h5;
       // lfsr_q[PRBS_WIDTH-1:4] <= #TCQ  prbs_seed_i[PRBS_WIDTH-1:4] ;
         
        lfsr_q[PRBS_WIDTH:5] <= #TCQ  prbs_seed_i[PRBS_WIDTH-1:4] ;
      end
   else   if (clk_en) begin
     
        lfsr_q[32:9] <= #TCQ  lfsr_q[31:8];
        lfsr_q[8]    <= #TCQ  lfsr_q[32] ^ lfsr_q[7];
        lfsr_q[7]    <= #TCQ  lfsr_q[32] ^ lfsr_q[6];
        lfsr_q[6:4]  <= #TCQ  lfsr_q[5:3];
        
        lfsr_q[3]    <= #TCQ  lfsr_q[32] ^ lfsr_q[2];
        lfsr_q[2]    <= #TCQ  lfsr_q[1] ;
        lfsr_q[1]    <= #TCQ  lfsr_q[32];
       
        
         end
end
 
always @ (lfsr_q[PRBS_WIDTH:1]) begin
       prbs = lfsr_q[PRBS_WIDTH:1];
end

assign prbs_o = prbs;

endmodule
module mig_7series_v2_0_tg_status #(
   parameter TCQ           = 100,  

   parameter DWIDTH = 32
    )
    (
      
   
   input                            clk_i  ,        
   input                            rst_i ,
   input                            manual_clear_error,
   input                            data_error_i ,  
   input [DWIDTH-1:0]               cmp_data_i,     
   input [DWIDTH-1:0]               rd_data_i ,     
   input [31:0]                     cmp_addr_i ,    
   input [5:0]                      cmp_bl_i ,      
   input                            mcb_cmd_full_i ,
   input                            mcb_wr_full_i,  
   input                            mcb_rd_empty_i, 
   output reg [64 + (2*DWIDTH - 1):0]   error_status,   
   output                           error                  
  );

reg data_error_r;
reg error_set;
assign  error = error_set;

always @ (posedge clk_i)
    data_error_r <= #TCQ  data_error_i;

always @ (posedge clk_i)
begin

if (rst_i || manual_clear_error) begin
   error_status <= #TCQ  'b0;
   error_set    <= #TCQ  1'b0;
end
else begin
  // latch the first error only
  if (data_error_i && ~data_error_r && ~error_set ) begin
     error_status[31:0]  <= #TCQ  cmp_addr_i;
     error_status[37:32] <= #TCQ  cmp_bl_i;
     error_status[40] <= #TCQ  mcb_cmd_full_i;
     error_status[41] <= #TCQ  mcb_wr_full_i;
     error_status[42] <= #TCQ  mcb_rd_empty_i;
     error_set <= #TCQ  1'b1;
     error_status[64 + (DWIDTH - 1)  :64]           <= #TCQ  cmp_data_i;
     error_status[64 + (2*DWIDTH - 1):64 + DWIDTH]  <= #TCQ  rd_data_i;
   
  end

  error_status[39:38]  <= #TCQ  'b0;    // reserved
  error_status[63:43] <= #TCQ  'b0;    // reserved


end end
    
endmodule
module mig_7series_v2_0_round_robin_arb
  #(
    parameter TCQ = 100,
    parameter WIDTH = 3
   )
   (
    /*AUTOARG*/
  // Outputs
  grant_ns, grant_r,
  // Inputs
  clk, rst, req, disable_grant, current_master, upd_last_master
  );

  input clk;
  input rst;

  input [WIDTH-1:0] req;

  wire [WIDTH-1:0] last_master_ns;

  reg [WIDTH*2-1:0] dbl_last_master_ns;
  always @(/*AS*/last_master_ns)
    dbl_last_master_ns = {last_master_ns, last_master_ns};
  reg [WIDTH*2-1:0] dbl_req;
  always @(/*AS*/req) dbl_req = {req, req};

  reg [WIDTH-1:0] inhibit = {WIDTH{1'b0}};

  genvar i;
  genvar j;
  generate
    for (i = 0; i < WIDTH; i = i + 1) begin : channel
      wire [WIDTH-1:1] inh_group;
      for (j = 0; j < (WIDTH-1); j = j + 1) begin : last_master
          assign inh_group[j+1] =
                  dbl_last_master_ns[i+j] && |dbl_req[i+WIDTH-1:i+j+1];
      end
      always @(/*AS*/inh_group) inhibit[i] = |inh_group;
    end
  endgenerate

  input disable_grant;
  output wire [WIDTH-1:0] grant_ns;
  assign grant_ns = req & ~inhibit & {WIDTH{~disable_grant}};

  output reg [WIDTH-1:0] grant_r;
  always @(posedge clk) grant_r <= #TCQ grant_ns;

  input [WIDTH-1:0] current_master;
  input upd_last_master;
  reg [WIDTH-1:0] last_master_r;
  localparam ONE = 1 << (WIDTH - 1); //Changed form '1' to fix the CR #544024
                                     //A '1' in the LSB of the last_master_r 
                                     //signal gives a low priority to req[0]
                                     //after reset. To avoid this made MSB as
                                     //'1' at reset.
  assign last_master_ns = rst
                            ? ONE[0+:WIDTH]
                            : upd_last_master
                                ? current_master
                                : last_master_r;
  always @(posedge clk) last_master_r <= #TCQ last_master_ns;

`ifdef MC_SVA
  grant_is_one_hot_zero:
    assert property (@(posedge clk) (rst || $onehot0(grant_ns)));
  last_master_r_is_one_hot:
    assert property (@(posedge clk) (rst || $onehot(last_master_r)));
`endif

endmodule
module mig_7series_v2_0_clk_ibuf #
  (
   parameter SYSCLK_TYPE      = "DIFFERENTIAL",
                                // input clock type
   parameter DIFF_TERM_SYSCLK = "TRUE"
                                // Differential Termination
   )
  (
   // Clock inputs
   input  sys_clk_p,          // System clock diff input
   input  sys_clk_n,
   input  sys_clk_i,
   output mmcm_clk
   );

   (* KEEP = "TRUE" *) wire sys_clk_ibufg /* synthesis syn_keep = 1 */;

  generate
    if (SYSCLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk

      //***********************************************************************
      // Differential input clock input buffers
      //***********************************************************************

      IBUFGDS #
        (
         .DIFF_TERM    (DIFF_TERM_SYSCLK),
         .IBUF_LOW_PWR ("FALSE")
         )
        u_ibufg_sys_clk
          (
           .I  (sys_clk_p),
           .IB (sys_clk_n),
           .O  (sys_clk_ibufg)
           );

    end else if (SYSCLK_TYPE == "SINGLE_ENDED") begin: se_input_clk

      //***********************************************************************
      // SINGLE_ENDED input clock input buffers
      //***********************************************************************

      IBUFG #
        (
         .IBUF_LOW_PWR ("FALSE")
         )
        u_ibufg_sys_clk
          (
           .I  (sys_clk_i),
           .O  (sys_clk_ibufg)
           );
    end else if (SYSCLK_TYPE == "NO_BUFFER") begin: internal_clk

      //***********************************************************************
      // System clock is driven from FPGA internal clock (clock from fabric)
      //***********************************************************************
      assign sys_clk_ibufg = sys_clk_i;
   end
  endgenerate

  assign mmcm_clk = sys_clk_ibufg;

endmodule