dakies/OSS_Verilog huggingface dataset:
module aibnd_dcc_clkrst ( clk_coding, nrst, nrst_coding, scan_out,
     vcc_pl, vss_pl, clk, dcc_dft_nrst, dcc_dft_nrst_coding, dcc_done,
     dcc_req, dll_lock, rb_dcc_dft, rb_dcc_en, scan_clk_in, scan_in,
     scan_mode_n, scan_rst_n );

output  clk_coding, nrst, nrst_coding, scan_out;

inout  vcc_pl, vss_pl;

input  clk, dcc_dft_nrst, dcc_dft_nrst_coding, dcc_done, dcc_req,
     dll_lock, rb_dcc_dft, rb_dcc_en, scan_clk_in, scan_in,
     scan_mode_n, scan_rst_n;

wire net052, dcc_req, rb_dcc_en, net054, rb_dcc_dft, dcc_dft_nrst_coding, net051, nrst, dcc_dft_nrst, net021, dccen_dccreq, clkdiv_4_mux, scan_mode_n, clkdiv_4, scan_clk_in, dll_lock_mux, dll_lock, nrst_mux, scan_rst_n, clk_mux, clk, clkdiv_2_mux, clkdiv_2, dccen_dccreq_mux, clkdiv_8_mux, clkdiv_8, nrst_coding, clk_coding_mux, clk_coding_premux, net056, clkdiv_16, net050, net037, net026, clk_coding, net036, dcc_done; // Conversion Sript Generated



assign net052 = !(dcc_req & rb_dcc_en);
assign net054 = rb_dcc_dft ? dcc_dft_nrst_coding : net051;
assign nrst = rb_dcc_dft ? dcc_dft_nrst : net021;
assign dccen_dccreq = !net052;
assign clkdiv_4_mux = scan_mode_n ? clkdiv_4 : scan_clk_in;
assign dll_lock_mux = scan_mode_n ? dll_lock : scan_clk_in;
assign nrst_mux = scan_mode_n ? nrst : scan_rst_n;
assign clk_mux = scan_mode_n ? clk : scan_clk_in;
assign clkdiv_2_mux = scan_mode_n ? clkdiv_2 : scan_clk_in;
assign dccen_dccreq_mux = scan_mode_n ? dccen_dccreq : scan_rst_n;
assign clkdiv_8_mux = scan_mode_n ? clkdiv_8 : scan_clk_in;
assign nrst_coding = scan_mode_n ? net054 : scan_rst_n;
assign clk_coding_mux = scan_mode_n ? clk_coding_premux : scan_clk_in;
assign net056 = !clkdiv_16;
assign net050 = !clkdiv_8;
assign net037 = !clkdiv_2;
assign net026 = !clkdiv_4;
assign clk_coding = clk_coding_mux;
assign net036 = !(dcc_req & dll_lock & rb_dcc_en);
assign net021 = !(net036 | dcc_done);
aibnd_dcc_ff xreg0 ( .so(so1), .se_n(scan_mode_n), .si(so0),
     .q(clkdiv_2), .vcc_pl(vcc_pl), .rb(nrst_mux), .clk(clk_mux),
     .d(net037), .vss_pl(vss_pl));
aibnd_dcc_ff xreg2 ( .so(so3), .se_n(scan_mode_n), .si(so2),
     .q(clkdiv_8), .vcc_pl(vcc_pl), .rb(nrst_mux), .clk(clkdiv_4_mux),
     .d(net050), .vss_pl(vss_pl));
aibnd_dcc_ff xreg3 ( .so(so4), .se_n(scan_mode_n), .si(so3),
     .q(clkdiv_16), .vcc_pl(vcc_pl), .rb(nrst_mux), .clk(clkdiv_8_mux),
     .d(net056), .vss_pl(vss_pl));
aibnd_dcc_ff xreg4 ( .so(scan_out), .se_n(scan_mode_n), .si(so4),
     .q(clk_coding_premux), .vcc_pl(vcc_pl), .rb(nrst_mux),
     .clk(clk_mux), .d(clkdiv_16), .vss_pl(vss_pl));
aibnd_dcc_ff x134 ( .so(so0), .se_n(scan_mode_n), .si(scan_in),
     .q(net051), .vcc_pl(vcc_pl), .rb(dccen_dccreq_mux),
     .clk(dll_lock_mux), .d(vcc_pl), .vss_pl(vss_pl));
aibnd_dcc_ff xreg1 ( .so(so2), .se_n(scan_mode_n), .si(so1),
     .q(clkdiv_4), .vcc_pl(vcc_pl), .rb(nrst_mux), .clk(clkdiv_2_mux),
     .d(net026), .vss_pl(vss_pl));

endmodule
module aibnd_red_clkmux3 ( clkout, clk1, clk2, clk3, s1, s2, s3,
     vccl_aibnd, vssl_aibnd );

output  clkout;

input  clk1, clk2, clk3, s1, s2, s3, vccl_aibnd, vssl_aibnd;

reg clkout;

// List of primary aliased buses

/*
specify 
    specparam CDS_LIBNAME  = "aibnd_lib";
    specparam CDS_CELLNAME = "aibnd_red_clkmux3";
    specparam CDS_VIEWNAME = "schematic";
endspecify
*/

always @ ( s1 or s2 or s3 or clk1 or clk2 or clk3 )
	case ( {s3,s2,s1} )
		3'b001 : clkout = clk1 ;
		3'b010 : clkout = clk2 ;
		3'b100 : clkout = clk3 ;
		default : clkout = 1'bx ;
	endcase
endmodule
module aibnd_rxanlg ( oclkn, oclkp, odat, odat_async, iopad, vccl_aibnd,
     vssl_aibnd, clk_en, data_en, iclkn );

output  oclkn, oclkp, odat, odat_async;

inout  iopad;
input vccl_aibnd, vssl_aibnd;
input  clk_en, data_en, iclkn;

wire clk_enb, clk_en_buf, preoclkpb, preoclkpbb, preoclkpbbb, preoclkp, oclkpb;
wire preoclknb, preoclknbb, preoclknbbb, preoclkn, oclknb;
wire data_enb, data_en_buf, preodatb, preodatbb, preodatbbb, preodat, odatb, preodatn, odat_inv_b, odat_inv;
//specify 
//    specparam CDS_LIBNAME  = "aibnd_lib";
//    specparam CDS_CELLNAME = "aibnd_rxanlg";
//    specparam CDS_VIEWNAME = "schematic";
//endspecify
assign clk_enb = ~clk_en;
assign clk_en_buf = ~clk_enb;

assign preoclkpb = ~iopad;
assign preoclkpbb = ~preoclkpb;
assign preoclkpbbb = ~preoclkpbb;
assign preoclkp = ~preoclkpbbb;
assign oclkpb = ~(preoclkp & clk_en_buf); 
assign oclkp = ~oclkpb;
//assign oclkp = (clk_en_buf == 1'b1) ? iopad : ((clk_en_buf == 1'b0)? 1'b0: 1'bx);

assign preoclknb = ~iclkn;
assign preoclknbb = ~preoclknb;
assign preoclknbbb = ~preoclknbb;
assign preoclkn = ~ preoclknbbb;
assign oclknb = ~(clk_enb | preoclkn);
assign oclkn = ~oclknb;
//assign oclkn = (clk_enb == 1'b0) ? iclkn : ((clk_enb == 1'b1)? 1'b1: 1'bx);
// REMARK: oclkp and oclkn should be mutually exclusive when clk_en = 1 or 0; Need assertion to check.
// Need to gate VCCL power supply in future.
assign data_enb = ~data_en;
assign data_en_buf = ~data_enb;
assign preodatb = ~iopad;
assign preodatbb = ~preodatb;
assign preodatbbb = ~preodatbb;
assign preodat = ~preodatbbb;
assign odatb = ~( preodat & data_en_buf);
assign odat = ~odatb;
//assign odat = (data_en_buf == 1'b1)? iopad : (data_en_buf == 1'b0)? 1'b0: 1'bx;
//Need to gate VCCL power supply in future.

assign preodatn = preodatbbb;
assign odat_inv_b = ~(preodatn | data_enb);
assign odat_inv = ~odat_inv_b;
assign odat_async = ~odat_inv;
//assign odat_async = (data_enb == 1'b0)? iopad : (data_enb == 1'b1)? 1'b0:1'bx;
//Need to gate VCCL power supply in future
endmodule
module aibnd_nand2 ( clkout, clk, en, vccl_aibnd, vssl_aibnd );

output  clkout;

input  clk, en, vccl_aibnd, vssl_aibnd;

// List of primary aliased buses

/*
specify 
    specparam CDS_LIBNAME  = "aibnd_lib";
    specparam CDS_CELLNAME = "aibnd_nand2";
    specparam CDS_VIEWNAME = "schematic";
endspecify
*/

assign clkout = ~(clk & en) ; 



endmodule
module aibnd_dcc_4b_b2tc ( therm, thermb, vcc_pl, vss_pl, q0, q1, q2,
     q3, rb_dcc_manual, rb_dcc_manual_mode );


inout  vcc_pl, vss_pl;

input  q0, q1, q2, q3, rb_dcc_manual_mode;

output [14:0]  thermb;
output [14:0]  therm;

input [3:0]  rb_dcc_manual;

wire b0b, b1b, b2b, b3b, net045, net046, net057, net058, net088, net089, b3, rb_dcc_manual_mode, q3, b1, q1, b0, q0, b2, q2, net086, net066, net087, net067, net072, net042, net075; // Conversion Sript Generated


assign therm[14] = !(b0b | b1b | b2b | b3b );
assign therm[3] = !(b2b & b3b);
assign therm[5] = !(net045 & b3b);
assign therm[6] = !(net046 & b3b);
assign therm[12] = !(net057 & net058);
assign therm[10] = !(net088 & net089);
assign b3 = rb_dcc_manual_mode ? rb_dcc_manual[3] : q3;
assign b1 = rb_dcc_manual_mode ? rb_dcc_manual[1] : q1;
assign b0 = rb_dcc_manual_mode ? rb_dcc_manual[0] : q0;
assign b2 = rb_dcc_manual_mode ? rb_dcc_manual[2] : q2;
assign b3b = !b3;
assign therm[7] = !thermb[7];
assign thermb[7] = !b3;
assign thermb[8] = !therm[8];
assign thermb[9] = !therm[9];
assign b0b = !b0;
assign b1b = !b1;
assign thermb[10] = !therm[10];
assign b2b = !b2;
assign thermb[0] = !therm[0];
assign thermb[1] = !therm[1];
assign thermb[2] = !therm[2];
assign thermb[3] = !therm[3];
assign thermb[4] = !therm[4];
assign thermb[5] = !therm[5];
assign thermb[6] = !therm[6];
assign net086 = !net066;
assign thermb[11] = !therm[11];
assign thermb[12] = !therm[12];
assign net087 = !net067;
assign thermb[13] = !therm[13];
assign thermb[14] = !therm[14];
assign therm[0] = !(b0b & b1b & b2b & b2b);
assign net089 = !(b2 & b3);
assign net045 = !(b1 & b2);
assign net072 = !(b0 & b1);
assign net042 = !(b1 & b2);
assign net075 = !(b0 & b2);
assign net067 = !(b1b & b2b);
assign therm[1] = !(b1b & b2b & b3b);
assign net057 = !(b0 & b2 & b3);
assign net066 = !(b0b & b1b & b2b);
assign net046 = !(b0 & b1 & b2);
assign therm[2] = !(net072 & b2b & b3b);
assign therm[4] = !(net075 & net042 & b3b);
assign net088 = !(b0 & b1 & b3);
assign net058 = !(b1 & b2 & b3);
assign therm[8] = !(net086 | b3b);
assign therm[9] = !(net087 | b3b);
assign therm[11] = !(b2b | b3b);
assign therm[13] = !(b1b | b2b | b3b);

endmodule
module aibnd_str_ff ( q, so, clk, code_valid, d, rb, se_n, si );

output  q, so;

input  clk, code_valid, d, rb, se_n, si;

wire so, q, net010, code_valid, d, net011, se_n, si; // Conversion Sript Generated

assign vcc_aibnd = 1'b1;
assign vss_aibnd = 1'b0;

// specify 
//     specparam CDS_LIBNAME  = "aibnd_lib";
//     specparam CDS_CELLNAME = "aibnd_str_ff";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign q = so;
aibnd_ff_r  xreg0 ( .o(so), .d(net011), .clk(clk) /*`ifndef INTCNOPWR , .vss(vss_aibnd) , .vcc(vcc_aibnd) `endif*/ , .rb(rb));
assign net010 = code_valid ? d : so;
assign net011 = se_n ? net010 : si;

endmodule
module aibnd_dcc_ff ( q, so, clk, d, rb, se_n, si, vcc_aibnd, vss_aibnd
     );

output  q, so;

input  clk, d, rb, se_n, si, vcc_aibnd, vss_aibnd;

wire so, q, net011, se_n, d, si; // Conversion Sript Generated


// specify 
//     specparam CDS_LIBNAME  = "aibnd_lib";
//     specparam CDS_CELLNAME = "aibnd_dcc_ff";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign so = q;
aibnd_ff_r  xreg0 ( .o(q), .d(net011), .clk(clk) /*`ifndef INTCNOPWR , .vss(vss_aibnd) , .vcc(vcc_aibnd) `endif*/ , .rb(rb));
assign net011 = se_n ? d : si;

endmodule
module aibnd_red_clkmux2 ( clkout, clk1, clk2, s, vccl_aibnd,
     vssl_aibnd );

output  clkout;

input  clk1, clk2, s, vccl_aibnd, vssl_aibnd;

// List of primary aliased buses

/*
specify 
    specparam CDS_LIBNAME  = "aibnd_lib";
    specparam CDS_CELLNAME = "aibnd_red_clkmux2";
    specparam CDS_VIEWNAME = "schematic";
endspecify
*/

assign clkout = s ?  clk1 : clk2 ;


endmodule
module aibnd_clktree_avmm_pcs 
#(
parameter SKEW_DELAY     = 60   //min:20ps; typ :60ps; max:100ps
)
(
   input  wire         clkin,                   //clock source
   output wire 	       lstrbclk_l_0, 	        //buffered clock
   output wire         lstrbclk_l_1,            //buffered clock
   output wire         lstrbclk_l_2,            //buffered clock
   output wire         lstrbclk_l_3,            //buffered clock
   output wire         lstrbclk_l_4,            //buffered clock
   output wire         lstrbclk_l_5,            //buffered clock
   output wire         lstrbclk_l_6,            //buffered clock
   output wire         lstrbclk_l_7,            //buffered clock
   output wire         lstrbclk_r_0,            //buffered clock
   output wire         lstrbclk_r_1,            //buffered clock
   output wire         lstrbclk_r_2,            //buffered clock
   output wire         lstrbclk_r_3,            //buffered clock
   output wire         lstrbclk_r_4,            //buffered clock
   output wire         lstrbclk_r_5,            //buffered clock
   output wire         lstrbclk_r_6,            //buffered clock
   output wire         lstrbclk_r_7,            //buffered clock
   output wire         lstrbclk_rep, 	        //replica for DLL
   output wire         lstrbclk_mimic0,         //mimic path for load matching
   output wire         lstrbclk_mimic1,         //mimic path for load matching   
   output wire         lstrbclk_mimic2          //mimic path for load matching
);

`ifdef TIMESCALE_EN
  timeunit 1ps;
  timeprecision 1ps;
`endif
  
                assign #SKEW_DELAY lstrbclk_l_0 = clkin;
                assign #SKEW_DELAY lstrbclk_l_1 = clkin;
                assign #SKEW_DELAY lstrbclk_l_2 = clkin;
                assign #SKEW_DELAY lstrbclk_l_3 = clkin;
                assign #SKEW_DELAY lstrbclk_l_4 = clkin;
                assign #SKEW_DELAY lstrbclk_l_5 = clkin;
                assign #SKEW_DELAY lstrbclk_l_6 = clkin;
                assign #SKEW_DELAY lstrbclk_l_7 = clkin;
                assign #SKEW_DELAY lstrbclk_r_0 = clkin;
                assign #SKEW_DELAY lstrbclk_r_1 = clkin;
                assign #SKEW_DELAY lstrbclk_r_2 = clkin;
                assign #SKEW_DELAY lstrbclk_r_3 = clkin;
                assign #SKEW_DELAY lstrbclk_r_4 = clkin;
                assign #SKEW_DELAY lstrbclk_r_5 = clkin;
                assign #SKEW_DELAY lstrbclk_r_6 = clkin;
                assign #SKEW_DELAY lstrbclk_r_7 = clkin;
                assign #SKEW_DELAY lstrbclk_rep = clkin;
                assign #SKEW_DELAY lstrbclk_mimic0 = clkin;
                assign #SKEW_DELAY lstrbclk_mimic1 = clkin;
                assign #SKEW_DELAY lstrbclk_mimic2 = clkin;

endmodule // aibnd_clktree_avmm_pcs
module aibnd_signal_buf ( sig_out, sig_in, vccl_aibnd, vssl_aibnd );

output  sig_out;

input  sig_in, vccl_aibnd, vssl_aibnd;

wire sig_in, sig_out; // Conversion Sript Generated


// specify 
//     specparam CDS_LIBNAME  = "aibnd_lib";
//     specparam CDS_CELLNAME = "aibnd_signal_buf";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign sig_out = sig_in;

endmodule
module aibnd_ff_rp ( 
	input wire clk,
	input wire rb,
	input wire psb,
	input wire d,
	//input wire vss,
	//input wire vcc,
	output reg o
);

always@(posedge clk or negedge rb or negedge psb) begin
	if (!rb) begin
		o <= 1'b0;
	end
	else if (!psb) begin
		o <= 1'b1;
	end
	else begin
		o <= d;
	end
end
endmodule
module aibnd_sync_ff ( q, so, clk, d, rb, se_n, si, vcc_aibnd,
     vss_aibnd );

output  q, so;

input  clk, d, rb, se_n, si, vcc_aibnd, vss_aibnd;


// specify 
//     specparam CDS_LIBNAME  = "aibnd_lib";
//     specparam CDS_CELLNAME = "aibnd_sync_ff";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

aibnd_2ff_scan  xsync0 ( .d(d), .clk(clk), .o(net016) /*`ifndef INTCNOPWR , .vcc(vcc_aibnd) `endif*/ ,     .rb(rb), .si(si) /*`ifndef INTCNOPWR , .vss(vss_aibnd) `endif*/ , .so(so0), .ssb(se_n));
aibnd_2ff_scan  xsync1 ( .d(net016), .clk(clk), .o(q) /*`ifndef INTCNOPWR , .vcc(vcc_aibnd) `endif*/ ,     .rb(rb), .si(so0) /*`ifndef INTCNOPWR , .vss(vss_aibnd) `endif*/ , .so(so), .ssb(se_n));

endmodule
module aibnd_dcc_fine_dly_x1 ( sp,sn , dout, vcc_regphy, vss_io );

  input sp,sn;
  output dout;
  input vss_io;
  input vcc_regphy;


  assign dout = 1'bz ;

endmodule
module aibnd_dcc_dly ( clkn_dly, clkn_mindly, clkp_dly, clkp_mindly,
     clk_dcd, dll_lock_reg, gray, launch, measure, nfrzdrv, vcc_aibnd,
     vss_aibnd );

output  clkn_dly, clkn_mindly, clkp_dly, clkp_mindly;

input  clk_dcd, dll_lock_reg, launch, measure, nfrzdrv, vcc_aibnd,
     vss_aibnd;

input [9:0]  gray;

wire clkn_dly, net048, clkn_mindly, net050, clkp_mindly, net049, clkp_dly, net047, net033, measure, vss_aibnd, net028, launch, net025, net024, net022, net023; // Conversion Sript Generated


// specify 
//     specparam CDS_LIBNAME  = "aibnd_lib";
//     specparam CDS_CELLNAME = "aibnd_dcc_dly";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

io_nand_delay_line_min  xdelay_min ( //.vcc_io(vcc_aibnd),
     //.vcc_regphy(vcc_aibnd), .vss_io(vss_aibnd), 
     .out_n(net023),
     .out_p(net022), .in_n(clk_split_mindly_n),
     .in_p(clk_split_mindly_p), .nfrzdrv(nfrzdrv));
assign clkn_dly = !net048;
assign clkn_mindly = !net050;
assign clkp_mindly = !net049;
assign clkp_dly = !net047;
io_nand_x128_delay_line  xdelay_line ( .f_gray(gray[9:3]),
     //.vcc_io(vcc_aibnd), .vcc_regphy(vcc_aibnd), .vss_io(vss_aibnd),
     .osc_out_n(net060), .osc_out_p(net061), .out_n(net025),
     .out_p(net024), .i_gray(gray[2:0]), .in_n(clk_split_dlyline_n),
     .in_p(clk_split_dlyline_p), .nfrzdrv(nfrzdrv),
     .osc_in_n(vcc_aibnd), .osc_in_p(vss_aibnd), .osc_mode(vss_aibnd));
io_split_align  xsplit0 ( //.vcc_io(vcc_aibnd), .vss_io(vss_aibnd),
     .dout_n(clk_split_mindly_n), .dout_p(clk_split_mindly_p),
     .din(clkin_mindly));
io_split_align  xsplit1 ( //.vcc_io(vcc_aibnd), .vss_io(vss_aibnd),
     .dout_n(clk_split_dlyline_n), .dout_p(clk_split_dlyline_p),
     .din(clkin_dlyline));
aibnd_dcc_mux xmux11 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd),
     .clk0(launch), .s(dll_lock_reg), .clkout(clkin_dlyline),
     .clk1(clk_dcd));
aibnd_dcc_mux xmux10 ( .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd),
     .clk0(measure), .s(dll_lock_reg), .clkout(clkin_mindly),
     .clk1(clk_dcd));
assign net033 = !(measure & vss_aibnd);
assign net028 = !(launch & vss_aibnd);
assign net048 = !net025;
assign net047 = !net024;
assign net049 = !net022;
assign net050 = !net023;

endmodule
module aibnd_inv ( clkout, clk, vccl_aibnd, vssl_aibnd );

output  clkout;

input  clk, vccl_aibnd, vssl_aibnd;

// List of primary aliased buses

/*
specify 
    specparam CDS_LIBNAME  = "aibnd_lib";
    specparam CDS_CELLNAME = "aibnd_inv";
    specparam CDS_VIEWNAME = "schematic";
endspecify
*/

assign clkout = ~clk ; 

endmodule
module aibnd_rxdig ( clkbuf_en, datbuf_en, odat0, odat1, rx_disable,
     rx_idat_buf, sync_datbuf_en0, sync_datbuf_en1, iclkin_dist,
     ipadrstb, irstb, irxen, istrbclk, rx_idat, vccl_aibnd, vssl_aibnd
     );

output  clkbuf_en, datbuf_en, odat0, odat1, rx_disable, rx_idat_buf,
     sync_datbuf_en0, sync_datbuf_en1;

input  iclkin_dist, ipadrstb, irstb, istrbclk, rx_idat, vccl_aibnd,
     vssl_aibnd;

input [2:0]  irxen;

wire irxen1_b, rst, iclkin_dist, iclkin_distb, iclkin_dist_buf, istrbclkb, istrbclk_buf, istrbclk, ipadrstb, irxen0, irxen0_b, irxen1, irxen2, irxen2_b, sdr_mode, clkbuf_en, sync_datbuf_en1, asyn_data_en, rx_disable, sync_datbuf_en0, pre_databuf_en_out, pre_databuf_en, datbuf_en, odat1_int, odat1, odat0_int, odat0, gt_sync_datbuf_en1, irstb, gt_sync_datbuf_en0, rx_idat, rx_idat_buf; // Conversion Sript Generated



assign irxen1_b = !(irxen[1] | rst);
assign iclkin_distb = !iclkin_dist;
assign iclkin_dist_buf = !iclkin_distb;
assign istrbclk_buf = !istrbclkb;
assign istrbclkb = !istrbclk;
aibnd_latch  lyn0 ( .clk(istrbclk_buf), .rb(gt_sync_datbuf_en0) /*`ifndef INTCNOPWR , .vcc(vccl_aibnd) , .vss(vssl_aibnd) `endif*/ , .d(idat0_sync1),     .o(idat0_latch));
aibnd_ff_r  fyn0 ( .o(odat0_int), .d(idat0_latch),     .clk(iclkin_dist_buf) /*`ifndef INTCNOPWR , .vss(vssl_aibnd) , .vcc(vccl_aibnd) `endif*/ ,     .rb(gt_sync_datbuf_en0));
aibnd_ff_r  fyn1 ( .o(odat1_int), .d(idat1_sync),     .clk(iclkin_dist_buf) /*`ifndef INTCNOPWR , .vss(vssl_aibnd) , .vcc(vccl_aibnd) `endif*/ ,     .rb(gt_sync_datbuf_en1));
assign rst = !ipadrstb;
assign irxen0 = !irxen0_b;
assign irxen1 = !irxen1_b;
assign irxen2 = !irxen2_b;
assign sdr_mode = irxen0_b & irxen1_b & irxen2;
assign clkbuf_en = irxen0 & irxen1 & irxen2_b;
assign sync_datbuf_en1 = irxen0 & irxen1_b & irxen2_b;
assign asyn_data_en = irxen0_b & irxen1_b & irxen2_b;
assign rx_disable = irxen0_b & irxen1 & irxen2_b;
assign sync_datbuf_en0 = sync_datbuf_en1 | sdr_mode;
//KSCHIA hack. WW21. Disconnect clkbuf_en to vss.
//assign pre_databuf_en_out = pre_databuf_en | clkbuf_en;
assign pre_databuf_en_out = pre_databuf_en | 1'b0;
assign pre_databuf_en = sync_datbuf_en1 | asyn_data_en;
assign datbuf_en = pre_databuf_en_out | sdr_mode;
assign odat1 = odat1_int;
assign odat0 = odat0_int;
assign gt_sync_datbuf_en1 = irstb & sync_datbuf_en1;
assign gt_sync_datbuf_en0 = irstb & sync_datbuf_en0;
assign irxen2_b = !(irxen[2] & ipadrstb);
assign irxen0_b = !(irxen[0] & ipadrstb);

//TWTAN : Update the RTL to match with the timing fix , adding inverter before , after fyn3 datapath .
//TWTAN : revert the change to invert the data before/after fyn3 . No invertion before/after fyn3 now
//wire idat_sync1_inv, rx_idat_buf_inv;
//assign idat1_sync = !idat_sync1_inv;
//assign rx_idat_buf_inv = !rx_idat_buf;

aibnd_ff_r  fyn3 ( .o(idat1_sync), .d(rx_idat_buf),     .clk(istrbclk_buf) /*`ifndef INTCNOPWR , .vss(vssl_aibnd) , .vcc(vccl_aibnd) `endif*/ ,     .rb(gt_sync_datbuf_en1));
aibnd_ff_r  fyn2 ( .o(idat0_sync1), .d(rx_idat_buf),     .clk(istrbclkb) /*`ifndef INTCNOPWR , .vss(vssl_aibnd) , .vcc(vccl_aibnd) `endif*/ ,     .rb(gt_sync_datbuf_en0));
assign rx_idat_buf = rx_idat;

endmodule
module aibnd_rambit_buf ( sig_out, sig_in, vccl_aibnd, vssl_aibnd );

output  sig_out;

input  sig_in, vccl_aibnd, vssl_aibnd;

wire sig_out, sig_in; // Conversion Sript Generated


// specify 
//     specparam CDS_LIBNAME  = "aibnd_lib";
//     specparam CDS_CELLNAME = "aibnd_rambit_buf";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign sig_out = sig_in;

endmodule
module aibnd_clktree_avmm_mimic 
#(
parameter SKEW_DELAY     = 60   //min:20ps; typ :60ps; max:100ps
)
(
   input  wire         clkin,                   //clock source
   output wire 	       lstrbclk_l_0, 	        //buffered clock
   output wire         lstrbclk_l_1,            //buffered clock
   output wire         lstrbclk_l_2,            //buffered clock
   output wire         lstrbclk_l_3,            //buffered clock
   output wire         lstrbclk_l_4,            //buffered clock
   output wire         lstrbclk_l_5,            //buffered clock
   output wire         lstrbclk_l_6,            //buffered clock
   output wire         lstrbclk_l_7,            //buffered clock
   output wire         lstrbclk_rep, 	        //replica for DLL
   output wire         lstrbclk_mimic0         //mimic path for load matching
);

`ifdef TIMESCALE_EN
  timeunit 1ps;
  timeprecision 1ps;
`endif
  
                assign #SKEW_DELAY lstrbclk_l_0 = clkin;
                assign #SKEW_DELAY lstrbclk_l_1 = clkin;
                assign #SKEW_DELAY lstrbclk_l_2 = clkin;
                assign #SKEW_DELAY lstrbclk_l_3 = clkin;
                assign #SKEW_DELAY lstrbclk_l_4 = clkin;
                assign #SKEW_DELAY lstrbclk_l_5 = clkin;
                assign #SKEW_DELAY lstrbclk_l_6 = clkin;
                assign #SKEW_DELAY lstrbclk_l_7 = clkin;
                assign #SKEW_DELAY lstrbclk_rep = clkin;
                assign #SKEW_DELAY lstrbclk_mimic0 = clkin;

endmodule // aibnd_clktree_avmm_mimic
module aibnd_clktree_mimic 
#(
parameter SKEW_DELAY     = 60   //min:20ps; typ :60ps; max:100ps
)
(
   input  wire         clkin,                   //clock source
   output wire 	       lstrbclk_l_0, 	        //buffered clock
   output wire         lstrbclk_l_1,            //buffered clock
   output wire         lstrbclk_l_2,            //buffered clock
   output wire         lstrbclk_l_3,            //buffered clock
   output wire         lstrbclk_l_4,            //buffered clock
   output wire         lstrbclk_l_5,            //buffered clock
   output wire         lstrbclk_l_6,            //buffered clock
   output wire         lstrbclk_l_7,            //buffered clock
   output wire         lstrbclk_l_8,            //buffered clock
   output wire         lstrbclk_l_9,            //buffered clock
   output wire         lstrbclk_l_10,           //buffered clock
   output wire         lstrbclk_l_11,           //buffered clock
   output wire         lstrbclk_rep, 	        //replica for DLL
   output wire         lstrbclk_mimic0         //mimic path for load matching
);

`ifdef TIMESCALE_EN
  timeunit 1ps;
  timeprecision 1ps;
`endif
  
                assign #SKEW_DELAY lstrbclk_l_0 = clkin;
                assign #SKEW_DELAY lstrbclk_l_1 = clkin;
                assign #SKEW_DELAY lstrbclk_l_2 = clkin;
                assign #SKEW_DELAY lstrbclk_l_3 = clkin;
                assign #SKEW_DELAY lstrbclk_l_4 = clkin;
                assign #SKEW_DELAY lstrbclk_l_5 = clkin;
                assign #SKEW_DELAY lstrbclk_l_6 = clkin;
                assign #SKEW_DELAY lstrbclk_l_7 = clkin;
                assign #SKEW_DELAY lstrbclk_l_8 = clkin;
                assign #SKEW_DELAY lstrbclk_l_9 = clkin;
                assign #SKEW_DELAY lstrbclk_l_10 = clkin;
                assign #SKEW_DELAY lstrbclk_l_11 = clkin;
                assign #SKEW_DELAY lstrbclk_rep = clkin;
                assign #SKEW_DELAY lstrbclk_mimic0 = clkin;

endmodule // aibnd_clktree_mimic
module aibnd_dcc_dll ( clk_dcc, dcc_done, odll_dll2core, odll_lock,
     pvt_ref_half_gry, scan_out, clk_dcd, clk_pll, csr_reg,
     idll_core2dll, idll_entest, nfrzdrv, nrst, pipeline_global_en,
     rb_clkdiv, rb_cont_cal, rb_dcc_byp, rb_half_code, rb_selflock,
     reinit, scan_clk_in, scan_in, scan_mode_n, scan_rst_n,
     scan_shift_n, test_clk_pll_en_n, vcc_aibnd, vss_aibnd );

output  clk_dcc, dcc_done, odll_lock, scan_out;

input  clk_dcd, clk_pll, idll_entest, nfrzdrv, nrst,
     pipeline_global_en, rb_cont_cal, rb_dcc_byp, rb_half_code,
     rb_selflock, reinit, scan_clk_in, scan_in, scan_mode_n,
     scan_rst_n, scan_shift_n, test_clk_pll_en_n, vcc_aibnd, vss_aibnd;

output [9:0]  pvt_ref_half_gry;
output [12:0]  odll_dll2core;

input [51:0]  csr_reg;
input [2:0]  rb_clkdiv;
input [2:0]  idll_core2dll;

// Buses in the design

wire  [6:0]  f_gray;

wire  [0:6]  net43;

wire  [9:0]  pvt_ref_gry;

wire  [2:0]  i_gray;


// specify 
//     specparam CDS_LIBNAME  = "aibnd_lib";
//     specparam CDS_CELLNAME = "aibnd_dcc_dll";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

aibnd_dll_custom xdll_custom ( .scan_shift_n(scan_shift_n),
     .rb_cont_cal(rb_cont_cal), .vss_aibnd(vss_aibnd),
     .vcc_aibnd(vcc_aibnd), .dcc_done(dcc_done), .clk_dcd(clk_dcd),
     .rb_dcc_byp(rb_dcc_byp), .scan_out(so_dll_custom),
     .scan_rst_n(scan_rst_n), .scan_mode_n(scan_mode_n),
     .scan_clk_in(scan_clk_in), .dll_lock(odll_lock),
     .scan_in(scan_in), .pvt_ref_half_gry(pvt_ref_half_gry[9:0]),
     .clk_dcc(clk_dcc), .nrst(nrst), .launch(launch),
     .measure(measure), .nfrzdrv(nfrzdrv), .t_down(t_down),
     .t_up(t_up), .dll_reset_n(dll_phdet_reset_n),
     .f_gray(f_gray[6:0]), .i_gray(i_gray[2:0]));
aibndpnr_dll_pnr  xdll_pnr ( .scan_shift_n(scan_shift_n),
     .rb_clkdiv(rb_clkdiv[2:0]), .gate_shf(net43[0:6]),
     .scan_in(so_dll_custom), .scan_rst_n(scan_rst_n),
     .scan_clk_in(scan_clk_in), .scan_mode_n(scan_mode_n),
     .scan_out(scan_out), .pipeline_global_en(pipeline_global_en),
     .dll_lock(odll_lock), .rb_half_code(rb_half_code),
     .pvt_ref_half_gry(pvt_ref_half_gry[9:0]), //.vcc_io(vcc_aibnd),
     //.vss_io(vss_aibnd), 
     .pvt_ref_gry(pvt_ref_gry[9:0]),
     .dll_core(odll_dll2core[12:0]), .i_gray(i_gray[2:0]),
     .f_gray(f_gray[6:0]), .core_dll(idll_core2dll[2:0]),
     .test_clk_pll_en_n(test_clk_pll_en_n),
     .dll_phdet_reset_n(dll_phdet_reset_n), .measure(measure),
     .launch(launch), .t_down(t_down), .t_up(t_up),
     .entest(idll_entest), .reinit(reinit), .csr_reg(csr_reg[51:0]),
     .rb_selflock(rb_selflock), .clk_pll(clk_pll));

endmodule
module aibnd_txanlg ( txpadout, vccl_aibnd, vssl_aibnd, din, ndrv_enb, pdrv_en,
     weak_pulldownen, weak_pullupenb );

inout  txpadout;

input  din, weak_pulldownen, weak_pullupenb;
input vccl_aibnd, vssl_aibnd;
input [15:0]  ndrv_enb;
input [15:0]  pdrv_en;

// Buses in the design

wire  [15:0]  ngin;

wire  [15:0]  pgin;


wire txpadout;

//specify 
//    specparam CDS_LIBNAME  = "aibnd_lib";
//    specparam CDS_CELLNAME = "aibnd_txanlg";
//    specparam CDS_VIEWNAME = "schematic";
//endspecify

//need to gate txpadout with vccl and vssl in future
// wek_pulldownen Vs. (pdrv_en and ndrv_enb) are mutually exclusive in txdig. No X check.
// weak_pulldownen = 1 and weak_pullupenb =1 is weak pulldown.
// weak_pulldownen = 0 and weak_pullupenb =0 is weak pull up.
//Other condition is high Z.
assign (weak0, weak1) txpadout = ((weak_pulldownen & weak_pullupenb) == 1'b1) ? 1'b0: (((weak_pulldownen | weak_pullupenb) == 1'b0)? 1'b1: 1'bz);
assign txpadout = (|pdrv_en & din)? 1'b1: 1'bz;
assign txpadout = (~&ndrv_enb & ~din)? 1'b0: 1'bz;
endmodule
module aibnd_preclkbuf ( clkout, vccl, vssl, clkin );

output  clkout;

inout  vccl, vssl;

input  clkin;

wire clkin, clkout; // Conversion Sript Generated



assign clkout = !clkin;

endmodule
module aibnd_io_dly_interpolator_rep (
input         nfrzdrv,
input         fout_p,
input         fout_n,
input   [2:0] gray,
output        out_p,
output        out_n,
output        osc_out_p,
output        osc_out_n
);

`ifdef TIMESCALE_EN
		timeunit 1ps; 
		timeprecision 1ps; 
`endif

parameter   NAND_DELAY = 20;

wire         a_in_p;
wire         b_in_p;
wire         c_in_p;
wire         a_in_n;
wire         b_in_n;
wire         c_in_n;
wire         out_pb;
wire         out_nb;
wire         x_p;
wire         x_n;
wire         x_pb;
wire         x_nb;
wire  [6:0]  sn;
reg   [6:0]  sp;

io_dly_interpclk xio_dly_interpclk (
.nfrzdrv	(nfrzdrv	),
.fout_p		(fout_p		),
.fout_n		(fout_n		),
.a_in_p		(a_in_p		),
.b_in_p		(b_in_p		),
.c_in_p		(c_in_p		),
.a_in_n		(a_in_n		),
.b_in_n		(b_in_n		),
.c_in_n		(c_in_n		)
);

always @(*)
  case (gray[2:0])
    3'b000 :  sp[6:0] = 7'b000_0000;
    3'b001 :  sp[6:0] = 7'b000_0001;
    3'b011 :  sp[6:0] = 7'b000_0011;
    3'b010 :  sp[6:0] = 7'b000_0111;
    3'b110 :  sp[6:0] = 7'b000_1111;
    3'b111 :  sp[6:0] = 7'b001_1111;
    3'b101 :  sp[6:0] = 7'b011_1111;
    3'b100 :  sp[6:0] = 7'b111_1111;
  endcase

assign sn[6:0] = ~sp[6:0];

io_ip8phs_3in xio_ip8phs_3in_n (
.a_in     ( a_in_n 		   ),
.b_in     ( b_in_n		   ),
.c_in     ( c_in_n		   ),
.svcc     ( 1'b1		   ),
.sp       ( sp[6:0]                ),
.sn       ( sn[6:0]                ),
.clk_outb ( out_nb                 )
);

io_ip8phs_3in xio_ip8phs_3in_p (
.a_in     ( a_in_p 		   ),
.b_in     ( b_in_p		   ),
.c_in     ( c_in_p		   ),
.svcc     ( 1'b1		   ),
.sp       ( sp[6:0]                ),
.sn       ( sn[6:0]                ),
.clk_outb ( out_pb                 )
);

assign x_p = ~out_pb;
assign x_n = ~out_nb;
//cross couple
assign x_pb = ~x_p;
assign x_nb = ~x_n;
assign out_p = ~x_pb;
assign out_n = ~x_nb;
assign osc_out_p = ~x_pb;
assign osc_out_n = ~x_nb;

/*
`ifdef LEC
assign x_p = ~x_n;
assign x_n = ~x_p;
`endif
*/

endmodule
module aibnd_clktree_avmm 
#(
parameter SKEW_DELAY     = 60   //min:20ps; typ :60ps; max:100ps
)
(
   input  wire         clkin,                   //clock source
   output wire 	       lstrbclk_l_0, 	        //buffered clock
   output wire         lstrbclk_l_1,            //buffered clock
   output wire         lstrbclk_l_2,            //buffered clock
   output wire         lstrbclk_l_3,            //buffered clock
   output wire         lstrbclk_l_4,            //buffered clock
   output wire         lstrbclk_l_5,            //buffered clock
   output wire         lstrbclk_l_6,            //buffered clock
   output wire         lstrbclk_l_7,            //buffered clock
   output wire         lstrbclk_r_0,            //buffered clock
   output wire         lstrbclk_r_1,            //buffered clock
   output wire         lstrbclk_r_2,            //buffered clock
   output wire         lstrbclk_r_3,            //buffered clock
   output wire         lstrbclk_r_4,            //buffered clock
   output wire         lstrbclk_r_5,            //buffered clock
   output wire         lstrbclk_r_6,            //buffered clock
   output wire         lstrbclk_r_7,            //buffered clock
   output wire         lstrbclk_rep, 	        //replica for DLL
   output wire         lstrbclk_mimic0,         //mimic path for load matching
   output wire         lstrbclk_mimic1,         //mimic path for load matching   
   output wire         lstrbclk_mimic2          //mimic path for load matching
);

`ifdef TIMESCALE_EN
  timeunit 1ps;
  timeprecision 1ps;
`endif
  
                assign #SKEW_DELAY lstrbclk_l_0 = clkin;
                assign #SKEW_DELAY lstrbclk_l_1 = clkin;
                assign #SKEW_DELAY lstrbclk_l_2 = clkin;
                assign #SKEW_DELAY lstrbclk_l_3 = clkin;
                assign #SKEW_DELAY lstrbclk_l_4 = clkin;
                assign #SKEW_DELAY lstrbclk_l_5 = clkin;
                assign #SKEW_DELAY lstrbclk_l_6 = clkin;
                assign #SKEW_DELAY lstrbclk_l_7 = clkin;
                assign #SKEW_DELAY lstrbclk_r_0 = clkin;
                assign #SKEW_DELAY lstrbclk_r_1 = clkin;
                assign #SKEW_DELAY lstrbclk_r_2 = clkin;
                assign #SKEW_DELAY lstrbclk_r_3 = clkin;
                assign #SKEW_DELAY lstrbclk_r_4 = clkin;
                assign #SKEW_DELAY lstrbclk_r_5 = clkin;
                assign #SKEW_DELAY lstrbclk_r_6 = clkin;
                assign #SKEW_DELAY lstrbclk_r_7 = clkin;
                assign #SKEW_DELAY lstrbclk_rep = clkin;
                assign #SKEW_DELAY lstrbclk_mimic0 = clkin;
                assign #SKEW_DELAY lstrbclk_mimic1 = clkin;
                assign #SKEW_DELAY lstrbclk_mimic2 = clkin;

endmodule // aibnd_clktree_avmm
module aibnd_dcc_4bdncnt ( full, q0, q1, q2, q3, vcc_pl, vss_pl, clk,
     dir, hold, nrst );

output  full, q0, q1, q2, q3;

inout  vcc_pl, vss_pl;

input  clk, dir, hold, nrst;

wire net066, q1, q0b, net035, q3, q0, net071, net042, q2, net063, net070, net039, net057, net034, q1b, net036, net092, net089, net065, net064, net090, net040, net062, q3b, q2b, ck, dir, clk, hld, holdb, net087, net059, net017, full, hold, net072, net060, net018, net099, net091; // Conversion Sript Generated


assign net066 = !(q1 & q0b);
assign net035 = !(q3 & q0);
assign net071 = !(q3 & q1);
assign net042 = !(q2 & q0);
assign net063 = !(q1 & q0);
assign net070 = !(q3 & q2);
assign net039 = !(q2 & q1);
assign net057 = !(net070 & net035 & net071);
assign net034 = !(q2 & q1b & q0b);
assign net036 = !(q3 & q1b & q0b);
assign net092 = !(net063 & net034 & net036);
assign net089 = !(net066 & net065 & net064);
assign net064 = !(q3 & q1b & q0b);
assign net090 = !(net042 & net039 & net040);
assign net065 = !(q2 & q1b & q0b);
aibnd_dcc_ff_pst x104 ( .q(net017), .vcc_pl(vcc_pl), .rb(nrst),
     .clk(ck), .d(net091), .vss_pl(vss_pl));
aibnd_dcc_ff_pst x106 ( .q(net087), .vcc_pl(vcc_pl), .rb(nrst),
     .clk(ck), .d(net018), .vss_pl(vss_pl));
aibnd_dcc_ff_pst x105 ( .q(net072), .vcc_pl(vcc_pl), .rb(nrst),
     .clk(ck), .d(net099), .vss_pl(vss_pl));
aibnd_dcc_ff_pst x103 ( .q(net059), .vcc_pl(vcc_pl), .rb(nrst),
     .clk(ck), .d(net060), .vss_pl(vss_pl));
assign net062 = !(q3b & q2b & q1b & q1b);
assign net040 = !(q3 & q2b & q1b & q1b);
assign ck = !(dir & clk);
assign hld = !(dir & holdb);
assign q0b = !net087;
assign q3b = !net059;
assign q2b = !net017;
assign full = !net062;
assign holdb = !hold;
assign q1b = !net072;
assign q3 = !q3b;
assign q2 = !q2b;
assign q0 = !q0b;
assign q1 = !q1b;
assign net060 = hld ? q3 : net057;
assign net018 = hld ? q0 : net089;
assign net099 = hld ? q1 : net092;
assign net091 = hld ? q2 : net090;

endmodule
module aibnd_aliasv ( .PLUS(w), .MINUS(w) );

	inout   w;
	wire    w;

endmodule
module aibnd_d8xsesdd1 ( iopad, vccl_aibnd, vssl_aibnd );

inout  iopad;

input  vccl_aibnd, vssl_aibnd;

/*
specify 
    specparam CDS_LIBNAME  = "aibnd_lib";
    specparam CDS_CELLNAME = "aibnd_d8xsesdd1";
    specparam CDS_VIEWNAME = "schematic";
endspecify
*/



endmodule
module aibnd_data_buf ( sig_out, sig_in, vccl_aibnd, vssl_aibnd );

output  sig_out;

input  sig_in, vccl_aibnd, vssl_aibnd;

wire sig_in, sig_out; // Conversion Sript Generated


// specify 
//     specparam CDS_LIBNAME  = "aibnd_lib";
//     specparam CDS_CELLNAME = "aibnd_data_buf";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign sig_out = sig_in;

endmodule
module aibnd_d8xsesdd2 ( iopad, vccl_aibnd, vssl_aibnd );

inout  iopad;

input  vccl_aibnd, vssl_aibnd;

/*
specify 
    specparam CDS_LIBNAME  = "aibnd_lib";
    specparam CDS_CELLNAME = "aibnd_d8xsesdd2";
    specparam CDS_VIEWNAME = "schematic";
endspecify
*/



endmodule
module aibnd_triinv_dig_str ( dat_out, dat_in, en, enb);

output  dat_out;

input  dat_in, en, enb;

assign vccl_aibnd = 1'b1;
assign vssl_aibnd = 1'b0;

//specify 
//    specparam CDS_LIBNAME  = "aibnd_lib";
//    specparam CDS_CELLNAME = "aibnd_triinv_dig_str";
//    specparam CDS_VIEWNAME = "schematic";
//endspecify

assign dat_out = ((en == 1'b1) & (enb == 1'b0))? ~dat_in : 1'bz;

endmodule
module aibnd_fine_dly_x1 ( sp,sn , dout); // vcc_regphy, vss_io );

  input sp,sn;
  output dout;
//  input vss_io;
//  input vcc_regphy;


  assign dout = 1'bz ;

endmodule
module aibnd_dcc_mux ( clkout, clk0, clk1, s, vcc_aibnd, vss_aibnd );

output  clkout;

input  clk0, clk1, s, vcc_aibnd, vss_aibnd;

wire net011, s, net013, clk1, net012, clk0, clkout; // Conversion Sript Generated


// specify 
//     specparam CDS_LIBNAME  = "aibnd_lib";
//     specparam CDS_CELLNAME = "aibnd_dcc_mux";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign net011 = !s;
assign net013 = !(clk1 & s);
assign net012 = !(clk0 & net011);
assign clkout = !(net012 & net013);

endmodule
module aibnd_cmos_nand_x6 ( co_p, out_p, so, bk0, bk1, bk2,
     bk3, bk4, bk5, ci_p, ck, code_valid, in_p, nrst, se_n, si,
     vcc_aibnd, vss_aibnd );

output  co_p, out_p, so;

input  bk0, bk1, bk2, bk3, bk4, bk5, ci_p, ck, code_valid, in_p, nrst,
     se_n, si, vcc_aibnd, vss_aibnd;


// specify 
//     specparam CDS_LIBNAME  = "aibnd_lib";
//     specparam CDS_CELLNAME = "aibnd_cmos_nand_x6";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

aibnd_cmos_nand_x1  xd00 ( .code_valid(code_valid), .ck(ck), .so(so0),
     .si(si), .se_n(se_n), .nrst(nrst), //.vcc_io(vcc_aibnd),
     .in_p(in_p), .bk(bk0), //.vss_io(vss_aibnd), 
     .co_p(a0), .ci_p(b0),
     .out_p(out_p));
aibnd_cmos_nand_x1  xd01 ( .code_valid(code_valid), .ck(ck), .so(so1),
     .si(so0), .se_n(se_n), .nrst(nrst), //.vcc_io(vcc_aibnd), 
     .in_p(a0), .bk(bk1), //.vss_io(vss_aibnd), 
     .co_p(a1), .ci_p(b1), .out_p(b0));
aibnd_cmos_nand_x1  xd02 ( .code_valid(code_valid), .ck(ck), .so(so2),
     .si(so1), .se_n(se_n), .nrst(nrst), //.vcc_io(vcc_aibnd), 
     .in_p(a1), .bk(bk2), //.vss_io(vss_aibnd), 
     .co_p(a2), .ci_p(b2), .out_p(b1));
aibnd_cmos_nand_x1  xd03 ( .code_valid(code_valid), .ck(ck), .so(so3),
     .si(so2), .se_n(se_n), .nrst(nrst), //.vcc_io(vcc_aibnd), 
     .in_p(a2), .bk(bk3), //.vss_io(vss_aibnd), 
     .co_p(a3), .ci_p(b3), .out_p(b2));
aibnd_cmos_nand_x1  xd04 ( .code_valid(code_valid), .ck(ck), .so(so4),
     .si(so3), .se_n(se_n), .nrst(nrst), //.vcc_io(vcc_aibnd), 
     .in_p(a3), .bk(bk4), //.vss_io(vss_aibnd), 
     .co_p(a4), .ci_p(b4), .out_p(b3));
aibnd_cmos_nand_x1  xd05 ( .code_valid(code_valid), .ck(ck), .so(so),
     .si(so4), .se_n(se_n), .nrst(nrst), //.vcc_io(vcc_aibnd), 
     .in_p(a4), .bk(bk5), //.vss_io(vss_aibnd), 
     .co_p(co_p), .ci_p(ci_p), .out_p(b4));

endmodule
module aibnd_dll_phdet ( t_down, t_up, dll_reset_n, i_del_p, phase_clk,
     vcc_io, vss_io );

output  t_down, t_up;

input  dll_reset_n, i_del_p, phase_clk, vcc_io, vss_io;

wire net034, t_down, net021, t_up; // Conversion Sript Generated


// specify 
//     specparam CDS_LIBNAME  = "aibnd_lib";
//     specparam CDS_CELLNAME = "aibnd_dll_phdet";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign t_down = net034;
assign t_up = net021;
aibnd_ff_r  xsampling_dn ( .o(net034), .d(phase_clk), .clk(i_del_p) /*`ifndef INTCNOPWR , .vss(vss_io) , .vcc(vcc_io) `endif*/ , .rb(dll_reset_n));
aibnd_ff_r  xsampling_up ( .o(net021), .d(i_del_p), .clk(phase_clk) /*`ifndef INTCNOPWR , .vss(vss_io) , .vcc(vcc_io) `endif*/ , .rb(dll_reset_n));

endmodule
module aibnd_str_ioload ( inp);

input  inp;

// Buses in the design

wire    net07;

assign vcc_aibnd = 1'b1;
assign vss_aibnd = 1'b0;


//specify 
//    specparam CDS_LIBNAME  = "aibnd_lib";
//    specparam CDS_CELLNAME = "aibnd_str_ioload";
//    specparam CDS_VIEWNAME = "schematic";
//endspecify

assign net07 = ~inp ;

endmodule
module aibnd_ff_r ( 
	input wire clk,
	input wire rb,
	input wire d,
	//input wire vss,
	//input wire vcc,
	output reg o
);

always@(posedge clk or negedge rb) begin
	if (!rb) begin
		o <= 1'b0;
	end
	else begin
		o <= d;
	end
end
endmodule
module aibnd_digital ( clkbuf_en, datbuf_en, ndrv_sel0, ndrv_sel1,
     ndrv_sel2, ndrv_sel3, odat0, odat1, pd_dataout, pdrv_sel0,
     pdrv_sel1, pdrv_sel2, pdrv_sel3, rx_disable, sync_datbuf_en0,
     sync_datbuf_en1, tx_dat, weak_pulld_en, weak_pullu_enb,
     async_data, clkdr, iclkin_dist, idat0, idat1, idataselb, iddrctrl,
     ilaunch_clk, ilpbk_dat, ilpbk_en, indrv, ipadrstb, ipdrv, irstb,
     irxen, istrbclk, itx_en, rx_idat, test_weakpd, test_weakpu,
     testmode_en, vccl_aibnd, vssl_aibnd );

output  clkbuf_en, datbuf_en, ndrv_sel0, ndrv_sel1, ndrv_sel2,
     ndrv_sel3, odat0, odat1, pd_dataout, pdrv_sel0, pdrv_sel1,
     pdrv_sel2, pdrv_sel3, rx_disable, sync_datbuf_en0,
     sync_datbuf_en1, tx_dat, weak_pulld_en, weak_pullu_enb;

input  async_data, clkdr, iclkin_dist, idat0, idat1, idataselb,
     iddrctrl, ilaunch_clk, ilpbk_dat, ilpbk_en, ipadrstb, irstb,
     istrbclk, itx_en, rx_idat, test_weakpd, test_weakpu, testmode_en,
     vccl_aibnd, vssl_aibnd;

input [1:0]  indrv;
input [1:0]  ipdrv;
input [2:0]  irxen;



aibnd_txdig xtxdig ( .vssl_aibnd(vssl_aibnd), .vccl_aibnd(vccl_aibnd),
     .ipadrstb(ipadrstb), .testmode_en(testmode_en), .clkdr(clkdr),
     .ndrv_sel0b(ndrv_sel0), .test_weakpd(test_weakpd),
     .test_weakpu(test_weakpu), .ndrv_sel1b(ndrv_sel1),
     .ndrv_sel2b(ndrv_sel2), .ndrv_sel3b(ndrv_sel3),
     .weak_pullu_enb(weak_pullu_enb), .async_data(async_data),
     .weak_pulld_en(weak_pulld_en), .rx_enb(rx_disable),
     .idataselb(idataselb), .iddrctrl(iddrctrl), .itx_en(itx_en),
     .irstb(irstb), .ilpbk_en(ilpbk_en), .pdrv_sel0(pdrv_sel0),
     .pdrv_sel1(pdrv_sel1), .pdrv_sel2(pdrv_sel2),
     .pdrv_sel3(pdrv_sel3), .tx_dat_out(tx_dat), .idat0(idat0),
     .idat1(idat1), .ilaunch_clk(ilaunch_clk), .ilpbk_dat(ilpbk_dat),
     .indrv(indrv[1:0]), .ipdrv(ipdrv[1:0]));
aibnd_rxdig xrxdig ( .ipadrstb(ipadrstb), .vccl_aibnd(vccl_aibnd),
     .vssl_aibnd(vssl_aibnd), .datbuf_en(datbuf_en),
     .rx_idat_buf(pd_dataout), .rx_idat(rx_idat),
     .clkbuf_en(clkbuf_en), .rx_disable(rx_disable),
     .sync_datbuf_en0(sync_datbuf_en0),
     .sync_datbuf_en1(sync_datbuf_en1), .irxen(irxen[2:0]),
     .odat0(odat0), .odat1(odat1), .iclkin_dist(iclkin_dist),
     .irstb(irstb), .istrbclk(istrbclk));

endmodule
module aibnd_hgy_latch (
	input wire set,
	input wire preset,
	input wire clk,
	input wire d,
	output reg q
);

always@(*) begin
	if (set && !preset) begin
		q <= 0;
	end
	else if (!set && preset) begin
		q <= 1;
	end
	else begin
		if (clk)
			q <= d;
	end
end	
endmodule
module aibnd_str_preclkbuf ( clkout, clkin, vcc_aibnd, vss_aibnd );

output  clkout;

input  clkin, vcc_aibnd, vss_aibnd;

wire clkin, clkout; // Conversion Sript Generated


// specify 
//     specparam CDS_LIBNAME  = "aibnd_lib";
//     specparam CDS_CELLNAME = "aibnd_str_preclkbuf";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign clkout = !clkin;

endmodule
module aibnd_dcc_dly_rep ( clkrep0, clkrep1, idat0, idat1, rb_dcc_byp,
     vcc_aibnd, vss_aibnd );

output  clkrep0, clkrep1;

input  idat0, idat1, rb_dcc_byp, vcc_aibnd, vss_aibnd;

/*
specify 
    specparam CDS_LIBNAME  = "aibnd_lib";
    specparam CDS_CELLNAME = "aibnd_dcc_dly_rep";
    specparam CDS_VIEWNAME = "schematic";
endspecify
*/

/*
d04gbf00nd0b0 xbuf2 ( .vss(vss_aibnd), .vcc(vcc_aibnd),
     .clk(rb_dcc_byp), .clkout(dcc_byp_buf));
d04inn00ld0o7 xinv3 ( .o1(clkrep1), .a(net22), .vcc(vcc_aibnd),
     .vss(vss_aibnd));
d04inn00ld0o7 xinv1 ( .o1(clkrep0), .a(net050), .vcc(vcc_aibnd),
     .vss(vss_aibnd));
*/
wire dcc_byp_buf , idat0_buf , idat1_buf,net22 , net050; 
assign dcc_byp_buf = rb_dcc_byp;
assign clkrep1 = ~net22;
assign clkrep0 = ~net050;

aibnd_io_nand_delay_line_min_rep xdelay_min (
     .out_n(idat0_dly), .out_p(idat1_dly), .in_n(idat0_buf),
     .in_p(idat1_buf), .nfrzdrv(vcc_aibnd));
aibnd_dcc_mux xmux4 ( .clk0(idat1_mux0), .s(vss_aibnd),
     .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), .clkout(idat1_mux1),
     .clk1(vss_aibnd));
aibnd_dcc_mux xmux3 ( .clk0(idat1_dly), .s(vss_aibnd),
     .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), .clkout(idat1_mux0),
     .clk1(vss_aibnd));
aibnd_dcc_mux xmux1 ( .clk0(idat0_mux0), .s(vss_aibnd),
     .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), .clkout(idat0_mux1),
     .clk1(vss_aibnd));
aibnd_dcc_mux xmux0 ( .clk0(idat0_dly), .s(vss_aibnd),
     .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), .clkout(idat0_mux0),
     .clk1(vss_aibnd));
aibnd_dcc_mux xmux5 ( .clk0(idat1_mux1), .s(dcc_byp_buf),
     .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), .clkout(idat1_mux2),
     .clk1(idat1));
aibnd_dcc_mux xmux2 ( .clk0(idat0_mux1), .s(dcc_byp_buf),
     .vcc_aibnd(vcc_aibnd), .vss_aibnd(vss_aibnd), .clkout(idat0_mux2),
     .clk1(idat0));
/*
d04gbf00ld0d0 xbuf0 ( .vss(vss_aibnd), .vcc(vcc_aibnd), .clk(idat0),
     .clkout(idat0_buf));
d04gbf00ld0d0 xbuf1 ( .vss(vss_aibnd), .vcc(vcc_aibnd), .clk(idat1),
     .clkout(idat1_buf));
d04inn00ld0c5 xinv2 ( .o1(net22), .a(idat1_mux2), .vcc(vcc_aibnd),
     .vss(vss_aibnd));
d04inn00ld0c5 xinv0 ( .o1(net050), .a(idat0_mux2), .vcc(vcc_aibnd),
     .vss(vss_aibnd));
*/
assign idat0_buf = idat0 ;
assign idat1_buf = idat1 ;
assign net22 = ~idat1_mux2;
assign net050 = ~idat0_mux2;


endmodule
module aibnd_dcc_5bupcnt ( full, q0, q1, q2, q3, q4, scan_out, vcc_pl,
     vss_pl, clk, dir, hold_state, nrst, scan_clk_in, scan_in,
     scan_mode_n );

output  full, q0, q1, q2, q3, q4, scan_out;

inout  vcc_pl, vss_pl;

input  clk, dir, hold_state, nrst, scan_clk_in, scan_in, scan_mode_n;

wire net041, q2b, net016, full, net069, net040, net090, net039, net048, net024, q4, q3, net043, net078, q3b, net038, net020, q1, q0, net084, q4b, net032, net057, net034, q0b, net089, net068, net063, q1b, net031, net037, net076, q2, net092, net036, ck_mux, scan_mode_n, ck, scan_clk_in, net056, dir, clk, hld, holdb, net087, net081, net059, net017, hold_state, net072, net061, net060, net018, net099, net091; // Conversion Sript Generated



assign net041 = !(q2b | net016);
assign full = !(net069 | net040);
assign net090 = !(net039 & net048);
assign net024 = !(q4 & q3);
assign net043 = !(net078 & q3b);
assign net038 = !(q3 & net020);
assign net040 = !(q1 & q0);
assign net084 = !(q4b & net032);
assign net057 = !(net043 & net038);
assign net034 = !(q1 & q0b);
assign net089 = !(q0 & net068);
assign net063 = !(q1b & q0);
assign net031 = !net057;
assign net020 = !net037;
assign net016 = !net076;
assign net039 = !net041;
assign net069 = !(q4 & q3 & q2);
assign net092 = !(net063 & net034 & net036);
assign net076 = !(net024 & q1 & q0);
assign net048 = !(q2b & q1 & q0);
assign ck_mux = scan_mode_n ? ck : scan_clk_in;
assign net032 = !(q3 & q2 & q1 & q1);
assign net037 = !(q4b & q2 & q1 & q1);
assign net036 = !(q4 & q3 & q2 & q2);
assign net078 = !(q3b & q2 & q1 & q1);
assign net068 = !(q4 & q3 & q2 & q2);
assign net056 = !(dir & clk);
assign hld = !(dir & holdb);
assign q0b = !net087;
assign q4b = !net081;
assign q3b = !net059;
assign q2b = !net017;
assign holdb = !hold_state;
assign ck = !net056;
assign q1b = !net072;
assign q4 = !q4b;
assign q3 = !q3b;
assign q2 = !q2b;
assign q0 = !q0b;
assign q1 = !q1b;
aibnd_dcc_ff x102 ( .so(so3), .se_n(scan_mode_n), .si(so2), .q(net059),
     .vcc_pl(vcc_pl), .rb(nrst), .clk(ck_mux), .d(net060),
     .vss_pl(vss_pl));
aibnd_dcc_ff x103 ( .so(scan_out), .se_n(scan_mode_n), .si(so3),
     .q(net081), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck_mux), .d(net061),
     .vss_pl(vss_pl));
aibnd_dcc_ff xreg2 ( .so(so2), .se_n(scan_mode_n), .si(so1),
     .q(net017), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck_mux), .d(net091),
     .vss_pl(vss_pl));
aibnd_dcc_ff xreg0 ( .so(so0), .se_n(scan_mode_n), .si(scan_in),
     .q(net087), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck_mux), .d(net018),
     .vss_pl(vss_pl));
aibnd_dcc_ff xreg1 ( .so(so1), .se_n(scan_mode_n), .si(so0),
     .q(net072), .vcc_pl(vcc_pl), .rb(nrst), .clk(ck_mux), .d(net099),
     .vss_pl(vss_pl));
assign net061 = hld ? q4 : net084;
assign net060 = hld ? q3 : net031;
assign net018 = hld ? q0 : net089;
assign net099 = hld ? q1 : net092;
assign net091 = hld ? q2 : net090;

endmodule