module M_execute__cpu_exec (
in_instr,
in_pc,
in_xa,
in_xb,
in_trigger,
out_op,
out_write_rd,
out_no_rd,
out_jump,
out_load,
out_store,
out_val,
out_storeVal,
out_working,
out_n,
out_storeAddr,
out_intop,
out_r,
reset,
out_clock,
clock
);
input  [31:0] in_instr;
input  [11:0] in_pc;
input signed [31:0] in_xa;
input signed [31:0] in_xb;
input  [0:0] in_trigger;
output  [2:0] out_op;
output  [4:0] out_write_rd;
output  [0:0] out_no_rd;
output  [0:0] out_jump;
output  [0:0] out_load;
output  [0:0] out_store;
output signed [31:0] out_val;
output  [0:0] out_storeVal;
output  [0:0] out_working;
output  [31:0] out_n;
output  [0:0] out_storeAddr;
output  [0:0] out_intop;
output signed [31:0] out_r;
input reset;
output out_clock;
input clock;
assign out_clock = clock;
reg signed [31:0] _t___block_1_shift;
reg  [0:0] _t___block_1_j;
wire signed [31:0] _w_imm_u;
wire signed [31:0] _w_imm_j;
wire signed [31:0] _w_imm_i;
wire signed [31:0] _w_imm_b;
wire signed [31:0] _w_imm_s;
wire  [4:0] _w_opcode;
wire  [0:0] _w_AUIPC;
wire  [0:0] _w_LUI;
wire  [0:0] _w_JAL;
wire  [0:0] _w_JALR;
wire  [0:0] _w_IntImm;
wire  [0:0] _w_IntReg;
wire  [0:0] _w_Cycles;
wire  [0:0] _w_branch;
wire  [0:0] _w_regOrImm;
wire  [0:0] _w_pcOrReg;
wire  [0:0] _w_sub;
wire  [0:0] _w_aluShift;
wire signed [31:0] _w_addr_a;
wire signed [31:0] _w_b;
wire signed [32:0] _w_a_minus_b;
wire  [0:0] _w_a_lt_b;
wire  [0:0] _w_a_lt_b_u;
wire  [0:0] _w_a_eq_b;
wire signed [31:0] _w_addr_imm;

reg  [4:0] _d_shamt = 0;
reg  [4:0] _q_shamt = 0;
reg  [31:0] _d_cycle = 0;
reg  [31:0] _q_cycle = 0;
reg  [2:0] _d_op;
reg  [2:0] _q_op;
reg  [4:0] _d_write_rd;
reg  [4:0] _q_write_rd;
reg  [0:0] _d_no_rd;
reg  [0:0] _q_no_rd;
reg  [0:0] _d_jump;
reg  [0:0] _q_jump;
reg  [0:0] _d_load;
reg  [0:0] _q_load;
reg  [0:0] _d_store;
reg  [0:0] _q_store;
reg signed [31:0] _d_val;
reg signed [31:0] _q_val;
reg  [0:0] _d_storeVal;
reg  [0:0] _q_storeVal;
reg  [0:0] _d_working = 0;
reg  [0:0] _q_working = 0;
reg  [31:0] _d_n;
reg  [31:0] _q_n;
reg  [0:0] _d_storeAddr;
reg  [0:0] _q_storeAddr;
reg  [0:0] _d_intop;
reg  [0:0] _q_intop;
reg signed [31:0] _d_r;
reg signed [31:0] _q_r;
assign out_op = _q_op;
assign out_write_rd = _q_write_rd;
assign out_no_rd = _q_no_rd;
assign out_jump = _q_jump;
assign out_load = _q_load;
assign out_store = _q_store;
assign out_val = _q_val;
assign out_storeVal = _q_storeVal;
assign out_working = _q_working;
assign out_n = _q_n;
assign out_storeAddr = _q_storeAddr;
assign out_intop = _q_intop;
assign out_r = _q_r;


assign _w_imm_u = {in_instr[12+:20],12'b0};
assign _w_imm_j = {{12{in_instr[31+:1]}},in_instr[12+:8],in_instr[20+:1],in_instr[21+:10],1'b0};
assign _w_imm_i = {{20{in_instr[31+:1]}},in_instr[20+:12]};
assign _w_imm_b = {{20{in_instr[31+:1]}},in_instr[7+:1],in_instr[25+:6],in_instr[8+:4],1'b0};
assign _w_imm_s = {{20{in_instr[31+:1]}},in_instr[25+:7],in_instr[7+:5]};
assign _w_opcode = in_instr[2+:5];
assign _w_AUIPC = _w_opcode==5'b00101;
assign _w_LUI = _w_opcode==5'b01101;
assign _w_JAL = _w_opcode==5'b11011;
assign _w_JALR = _w_opcode==5'b11001;
assign _w_IntImm = _w_opcode==5'b00100;
assign _w_IntReg = _w_opcode==5'b01100;
assign _w_Cycles = _w_opcode==5'b11100;
assign _w_branch = _w_opcode==5'b11000;
assign _w_regOrImm = _w_IntReg|_w_branch;
assign _w_pcOrReg = _w_AUIPC|_w_JAL|_w_branch;
assign _w_sub = _w_IntReg&in_instr[30+:1];
assign _w_aluShift = (_w_IntImm|_w_IntReg)&_d_op[0+:2]==2'b01;
assign _w_addr_a = _w_pcOrReg ? $signed({1'b0,in_pc[0+:10],2'b0}):in_xa;
assign _w_b = _w_regOrImm ? (in_xb):_w_imm_i;
assign _w_a_minus_b = {1'b1,~_w_b}+{1'b0,in_xa}+33'b1;
assign _w_a_lt_b = (in_xa[31+:1]^_w_b[31+:1]) ? in_xa[31+:1]:_w_a_minus_b[32+:1];
assign _w_a_lt_b_u = _w_a_minus_b[32+:1];
assign _w_a_eq_b = _w_a_minus_b[0+:32]==0;
assign _w_addr_imm = (_w_AUIPC ? _w_imm_u:32'b0)|(_w_JAL ? _w_imm_j:32'b0)|(_w_branch ? _w_imm_b:32'b0)|((_w_JALR|_d_load) ? _w_imm_i:32'b0)|(_d_store ? _w_imm_s:32'b0);

`ifdef FORMAL
initial begin
assume(reset);
end
`endif
always @* begin
_d_shamt = _q_shamt;
_d_cycle = _q_cycle;
_d_op = _q_op;
_d_write_rd = _q_write_rd;
_d_no_rd = _q_no_rd;
_d_jump = _q_jump;
_d_load = _q_load;
_d_store = _q_store;
_d_val = _q_val;
_d_storeVal = _q_storeVal;
_d_working = _q_working;
_d_n = _q_n;
_d_storeAddr = _q_storeAddr;
_d_intop = _q_intop;
_d_r = _q_r;
// _always_pre
_d_load = _w_opcode==5'b00000;
_d_store = _w_opcode==5'b01000;
_d_op = in_instr[12+:3];
_d_write_rd = in_instr[7+:5];
_d_no_rd = _w_branch|_d_store|(in_instr[7+:5]==5'b0);
_d_intop = (_w_IntImm|_w_IntReg);
_d_storeAddr = _w_AUIPC;
_d_val = _w_LUI ? _w_imm_u:_q_cycle;
_d_storeVal = _w_LUI|_w_Cycles;
_d_cycle = _q_cycle+1;
// __block_1
if (_q_working) begin
// __block_2
// __block_4
_d_shamt = _q_shamt-1;
_t___block_1_shift = _d_op[2+:1] ? (in_instr[30+:1] ? {_q_r[31+:1],_q_r[1+:31]}:{$signed(1'b0),_q_r[1+:31]}):{_q_r[0+:31],$signed(1'b0)};
// __block_5
end else begin
// __block_3
// __block_6
_d_shamt = ((_w_aluShift&in_trigger) ? $unsigned(_w_b[0+:5]):0);
_t___block_1_shift = in_xa;
// __block_7
end
// __block_8
_d_working = (_d_shamt!=0);
  case (_d_op)
  3'b000: begin
// __block_10_case
// __block_11
_d_r = _w_sub ? _w_a_minus_b:in_xa+_w_b;
// __block_12
  end
  3'b010: begin
// __block_13_case
// __block_14
_d_r = _w_a_lt_b;
// __block_15
  end
  3'b011: begin
// __block_16_case
// __block_17
_d_r = _w_a_lt_b_u;
// __block_18
  end
  3'b100: begin
// __block_19_case
// __block_20
_d_r = in_xa^_w_b;
// __block_21
  end
  3'b110: begin
// __block_22_case
// __block_23
_d_r = in_xa|_w_b;
// __block_24
  end
  3'b001: begin
// __block_25_case
// __block_26
_d_r = _t___block_1_shift;
// __block_27
  end
  3'b101: begin
// __block_28_case
// __block_29
_d_r = _t___block_1_shift;
// __block_30
  end
  3'b111: begin
// __block_31_case
// __block_32
_d_r = in_xa&_w_b;
// __block_33
  end
  default: begin
// __block_34_case
// __block_35
_d_r = {32{1'bx}};
// __block_36
  end
endcase
// __block_9
  case (_d_op[1+:2])
  2'b00: begin
// __block_38_case
// __block_39
_t___block_1_j = _w_a_eq_b;
// __block_40
  end
  2'b10: begin
// __block_41_case
// __block_42
_t___block_1_j = _w_a_lt_b;
// __block_43
  end
  2'b11: begin
// __block_44_case
// __block_45
_t___block_1_j = _w_a_lt_b_u;
// __block_46
  end
  default: begin
// __block_47_case
// __block_48
_t___block_1_j = 1'bx;
// __block_49
  end
endcase
// __block_37
_d_jump = (_w_JAL|_w_JALR)|(_w_branch&(_t___block_1_j^_d_op[0+:1]));
_d_n = _w_addr_a+_w_addr_imm;
// __block_50
// _always_post
end

always @(posedge clock) begin
_q_shamt <= _d_shamt;
_q_cycle <= _d_cycle;
_q_op <= _d_op;
_q_write_rd <= _d_write_rd;
_q_no_rd <= _d_no_rd;
_q_jump <= _d_jump;
_q_load <= _d_load;
_q_store <= _d_store;
_q_val <= _d_val;
_q_storeVal <= _d_storeVal;
_q_working <= _d_working;
_q_n <= _d_n;
_q_storeAddr <= _d_storeAddr;
_q_intop <= _d_intop;
_q_r <= _d_r;
end

endmodule