module FIFO_Write_Pointer ( W_CLK, W_rst_n, W_inc, Wq2_rptr, W_Full, W_ptr, 
        W_Addr );
  input [4:0] Wq2_rptr;
  output [4:0] W_ptr;
  output [3:0] W_Addr;
  input W_CLK, W_rst_n, W_inc;
  output W_Full;
  wire   n38, \Binary_W_ptr[4] , FULL_VALUE, n1, n3, n4, n5, n6, n7, n8, n9,
         n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23,
         n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37;
  wire   [3:0] Gray_W_ptr;
  wire   [4:0] Binary_W_ptr_next;

  DFFRQX2M \Binary_W_ptr_reg[4]  ( .D(n5), .CK(W_CLK), .RN(W_rst_n), .Q(
        \Binary_W_ptr[4] ) );
  DFFRQX2M \W_ptr_reg[4]  ( .D(n5), .CK(W_CLK), .RN(W_rst_n), .Q(W_ptr[4]) );
  DFFRQX4M \Binary_W_ptr_reg[0]  ( .D(n1), .CK(W_CLK), .RN(W_rst_n), .Q(
        W_Addr[0]) );
  DFFRQX4M \Binary_W_ptr_reg[2]  ( .D(n3), .CK(W_CLK), .RN(W_rst_n), .Q(
        W_Addr[2]) );
  DFFRQX4M \Binary_W_ptr_reg[1]  ( .D(Binary_W_ptr_next[1]), .CK(W_CLK), .RN(
        W_rst_n), .Q(W_Addr[1]) );
  DFFRQX2M \W_ptr_reg[3]  ( .D(Gray_W_ptr[3]), .CK(W_CLK), .RN(W_rst_n), .Q(
        W_ptr[3]) );
  DFFRQX2M \W_ptr_reg[0]  ( .D(Gray_W_ptr[0]), .CK(W_CLK), .RN(W_rst_n), .Q(
        W_ptr[0]) );
  DFFRQX2M \W_ptr_reg[1]  ( .D(Gray_W_ptr[1]), .CK(W_CLK), .RN(W_rst_n), .Q(
        W_ptr[1]) );
  DFFRQX2M \W_ptr_reg[2]  ( .D(Gray_W_ptr[2]), .CK(W_CLK), .RN(W_rst_n), .Q(
        W_ptr[2]) );
  DFFRHQX4M W_Full_reg ( .D(FULL_VALUE), .CK(W_CLK), .RN(W_rst_n), .Q(n38) );
  DFFRQX4M \Binary_W_ptr_reg[3]  ( .D(Binary_W_ptr_next[3]), .CK(W_CLK), .RN(
        W_rst_n), .Q(W_Addr[3]) );
  XOR2X4M U3 ( .A(n19), .B(n3), .Y(n20) );
  XOR2X4M U4 ( .A(n21), .B(Wq2_rptr[0]), .Y(n36) );
  INVX2M U5 ( .A(n31), .Y(Gray_W_ptr[2]) );
  XNOR2X4M U6 ( .A(n18), .B(W_Addr[0]), .Y(n1) );
  NAND2BX4M U7 ( .AN(n25), .B(W_Addr[3]), .Y(n11) );
  OAI221X4M U8 ( .A0(W_Addr[3]), .A1(n28), .B0(n27), .B1(n28), .C0(n26), .Y(
        n29) );
  INVX2M U9 ( .A(n25), .Y(n27) );
  OR3X2M U10 ( .A(n25), .B(n24), .C(n23), .Y(n26) );
  XOR2X8M U11 ( .A(n3), .B(n30), .Y(n31) );
  CLKXOR2X16M U12 ( .A(n4), .B(W_Addr[2]), .Y(n3) );
  XOR2X8M U13 ( .A(n19), .B(n1), .Y(n21) );
  CLKXOR2X8M U14 ( .A(n10), .B(W_Addr[1]), .Y(n19) );
  INVX2M U15 ( .A(n30), .Y(Binary_W_ptr_next[3]) );
  AOI222X4M U16 ( .A0(W_inc), .A1(n7), .B0(n24), .B1(n15), .C0(n24), .C1(n8), 
        .Y(n6) );
  INVX32M U17 ( .A(W_inc), .Y(n8) );
  XOR2X8M U18 ( .A(n9), .B(n29), .Y(n33) );
  NOR3X12M U19 ( .A(n12), .B(n14), .C(n8), .Y(n4) );
  CLKBUFX40M U20 ( .A(n38), .Y(W_Full) );
  NAND2BX1M U21 ( .AN(W_Full), .B(W_inc), .Y(n18) );
  CLKINVX2M U22 ( .A(n21), .Y(Gray_W_ptr[0]) );
  XOR2X8M U23 ( .A(n31), .B(Wq2_rptr[2]), .Y(n32) );
  XOR2X8M U24 ( .A(n11), .B(n22), .Y(n5) );
  XOR2X8M U25 ( .A(Wq2_rptr[4]), .B(n5), .Y(n34) );
  CLKINVX1M U26 ( .A(n20), .Y(Gray_W_ptr[1]) );
  INVXLM U27 ( .A(n19), .Y(Binary_W_ptr_next[1]) );
  AND3X6M U28 ( .A(n34), .B(n33), .C(n32), .Y(n35) );
  INVX2M U29 ( .A(n15), .Y(n16) );
  INVX2M U30 ( .A(n17), .Y(n7) );
  OR2X2M U31 ( .A(n14), .B(n13), .Y(n15) );
  INVX2M U32 ( .A(n23), .Y(n28) );
  INVX2M U33 ( .A(n6), .Y(n9) );
  NAND2BX2M U34 ( .AN(n14), .B(W_inc), .Y(n10) );
  NAND2BX2M U35 ( .AN(W_Full), .B(W_Addr[0]), .Y(n14) );
  CLKINVX2M U36 ( .A(W_Addr[3]), .Y(n24) );
  NAND2BX2M U37 ( .AN(n12), .B(W_Addr[2]), .Y(n13) );
  INVX2M U38 ( .A(W_Addr[1]), .Y(n12) );
  CLKXOR2X2M U39 ( .A(n22), .B(Wq2_rptr[3]), .Y(n23) );
  INVX2M U40 ( .A(\Binary_W_ptr[4] ), .Y(n22) );
  CLKXOR2X2M U41 ( .A(n5), .B(Binary_W_ptr_next[3]), .Y(Gray_W_ptr[3]) );
  NAND2BX4M U42 ( .AN(n15), .B(W_inc), .Y(n25) );
  OR3X2M U43 ( .A(n14), .B(n24), .C(n13), .Y(n17) );
  OAI222X4M U44 ( .A0(n8), .A1(n17), .B0(W_Addr[3]), .B1(n16), .C0(W_Addr[3]), 
        .C1(W_inc), .Y(n30) );
  XOR2X4M U45 ( .A(Wq2_rptr[1]), .B(n20), .Y(n37) );
  AND3X4M U46 ( .A(n36), .B(n37), .C(n35), .Y(FULL_VALUE) );
endmodule