dakies/OSS_Verilog huggingface dataset:
module cdclib_sync4_set_type_l_gate
    (
    input  wire              clk,     // clock
    input  wire              rst_n,   // async reset
    input  wire 	     data_in, // data in
    output wire 	     data_out // data out
     );


   reg		data_in_sync;
   reg		data_in_sync2;
   reg		data_in_sync3;
   reg		data_in_sync4;
   
   always @(negedge rst_n or posedge clk) begin
      if (rst_n == 1'b0) begin
        data_in_sync <= 	1'b1;
        data_in_sync2 <= 	1'b1;
        data_in_sync3 <= 	1'b1;
        data_in_sync4 <= 	1'b1;
      end
      else begin
        data_in_sync <= 	data_in;
        data_in_sync2 <= 	data_in_sync;
        data_in_sync3 <= 	data_in_sync2;
        data_in_sync4 <= 	data_in_sync3;
      end
   end    
     
   assign data_out = data_in_sync4;

endmodule // cdclib_sync4_set_type_l_gate
module cdclib_rst_n_sync
  ( input  wire rst_n,        // Asynchronous reset
    input  wire rst_n_bypass, // PLD reset input in scan mode
    input  wire clk,          // Clock to synchronize rst_n to
    input  wire scan_mode_n,  // Scan mode control
    output wire rst_n_sync    // Synchronized rst_n deassertion output  
  );

wire rst_n_sync_int;

// reset synchronizer core
cdclib_rst_n_sync_core cdclib_rst_n_sync_core
  ( 
    .rst_n(rst_n),              // Asynchronous reset
    .clk(clk),                  // Clock to synchronize rst_n to
    .tie_high(1'b1),            // Tie high input
    .rst_n_sync(rst_n_sync_int) // Synchronized rst_n deassertion output  
  );
 
// Reset synchronizer bypass
assign rst_n_sync = (scan_mode_n == 1'b0) ? rst_n_bypass : rst_n_sync_int;

endmodule
module cdclib_sync4_set_type_w_gate
    (
    input  wire              clk,     // clock
    input  wire              rst_n,   // async reset
    input  wire 	     data_in, // data in
    output wire 	     data_out // data out
     );


   reg		data_in_sync;
   reg		data_in_sync2;
   reg		data_in_sync3;
   reg		data_in_sync4;
   
   always @(negedge rst_n or posedge clk) begin
      if (rst_n == 1'b0) begin
        data_in_sync <= 	1'b1;
        data_in_sync2 <= 	1'b1;
        data_in_sync3 <= 	1'b1;
        data_in_sync4 <= 	1'b1;
      end
      else begin
        data_in_sync <= 	data_in;
        data_in_sync2 <= 	data_in_sync;
        data_in_sync3 <= 	data_in_sync2;
        data_in_sync4 <= 	data_in_sync3;
      end
   end    
     
   assign data_out = data_in_sync4;

endmodule // cdclib_sync4_set_type_w_gate
module cdclib_sync2_set_type_w_gate
    (
    input  wire              clk,     // clock
    input  wire              rst_n,   // async reset
    input  wire 	     data_in, // data in
    output wire 	     data_out // data out
     );


   reg		data_in_sync;
   reg		data_in_sync2;
   
   always @(negedge rst_n or posedge clk) begin
      if (rst_n == 1'b0) begin
        data_in_sync <= 	1'b1;
        data_in_sync2 <= 	1'b1;
      end
      else begin
        data_in_sync <= 	data_in;
        data_in_sync2 <= 	data_in_sync;
      end
   end    
     
   assign data_out = data_in_sync2;

endmodule // cdclib_sync2_set_type_w_gate
module cdclib_pulse_stretch 
   #(
      parameter RESET_VAL        = 0, // Reset value 
      parameter HIGH_PULSE       = 1  // High or low pulse
    )
  (
    input  wire         clk,         // clock
    input  wire         rst_n,       // async reset
    input  wire [1:0]   r_num_stages,  // number of stages required
    input  wire         data_in,     // data in
    output  reg         data_out     // stretched data out             
   );

   wire                         reset_value;
   assign reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0;  // To eliminate truncating warning

   reg                  data_d1, data_d2, data_d3, data_d4;
   reg                  data_out_comb;
      
   always @* begin
      data_out_comb = data_in;
      
      case (r_num_stages)
        2'b00: data_out_comb = data_in;
        2'b01: data_out_comb = HIGH_PULSE ? data_d1 | data_in : data_d1 & data_in;
        2'b10: data_out_comb = HIGH_PULSE ? data_d2 | data_d1 | data_in : data_d2 & data_d1 & data_in ;
        2'b11: data_out_comb = HIGH_PULSE ? data_d3 | data_d2 | data_d1 | data_in : data_d3 & data_d2 & data_d1 & data_in;
        default: data_out_comb = data_in;
      endcase // case(r_num_stages)
   end // always @ *

   always @(negedge rst_n or posedge clk) begin
      if (~rst_n) begin
         data_d1 <= reset_value;
         data_d2 <= reset_value;
         data_d3 <= reset_value;
         data_d4 <= reset_value;
         data_out <= reset_value;
      end
      else begin
         data_d1 <= data_in;
         data_d2 <= data_d1;
         data_d3 <= data_d2;
         data_d4 <= data_d3;
         data_out <= data_out_comb;
      end
   end // always @ (negedge rst_n or posedge clk)
      
endmodule // cdclib_pulse_stretch
module cdclib_bintogray_inc8
   #(
      parameter WIDTH           = 6 // Data width 
    )
   (
   // Inputs
   input  wire [WIDTH-1:0]  data_in,       // data in
   // Outputs
   output wire  [WIDTH-1:0]  data_out       // data out
   );


assign data_out = {(data_in[WIDTH-1:3]>>1) ^ data_in[WIDTH-1:3], 3'b0};


endmodule
module cdclib_bintogray
   #(
      parameter WIDTH           = 2 // Data width 
    )
   (
   // Inputs
   input  wire [WIDTH-1:0]  data_in,       // data in
   // Outputs
   output wire  [WIDTH-1:0]  data_out       // data out
   );


assign data_out = (data_in>>1) ^ data_in;

endmodule
module an_io_double_edge_ff (clk_in, reset_n, test_enable_n, data_in, data_out `ifndef INTCNOPWR ,vcc ,vss `endif);
input  [1:0] clk_in;            // clk_in[0] is p, clk_in[1] is n
input        reset_n;           // Reset active low
input        test_enable_n;     // Reset active low
input  [1:0] data_in;
output [1:0] data_out;          // Complimentary output
reg notifier;

`ifndef INTCNOPWR
input vcc, vss;
`endif
wire [1:0] clk_buf_n;

assign clk_buf_n[1] = ~(test_enable_n & clk_in[1]);
assign clk_buf_n[0] = ~(test_enable_n & clk_in[0]);
wire  delayed_clk_in_1;
wire  delayed_clk_in_0;
wire  delayed_data_in_1;
wire  delayed_data_in_0;

reg  [1:0] lat;
always @(reset_n or clk_buf_n[0] or data_in[0])
  if (~reset_n)          lat[0] <= 1'b0;
  else if (clk_buf_n[0]) lat[0] <= data_in[0];

always @(reset_n or clk_buf_n[1] or data_in[1])
  if (~reset_n)          lat[1] <= 1'b0;
  else if (clk_buf_n[1]) lat[1] <= data_in[1];

assign data_out[0] = (clk_in[0] &  lat[0]) | (clk_in[1] &  lat[1]) | ( lat[0] &  lat[1]);
assign data_out[1] = (clk_in[0] & ~lat[0]) | (clk_in[1] & ~lat[1]) | (~lat[0] & ~lat[1]);
	specify
                if (~test_enable_n) 
	       			(data_in[0] => data_out[1]) = 0;
                if (~test_enable_n) 
                		(data_in[1] => data_out[1]) = 0;
		if (~test_enable_n)
                		(clk_in[0] => data_out[1]) = 0;
		if (test_enable_n)
                		(posedge clk_in[0] => (data_out[1]:data_in[0])) = (0,0);
		if (test_enable_n)
                		(posedge clk_in[1] => (data_out[1]:data_in[1])) = (0,0);
		if (~test_enable_n)
                		(posedge clk_in[1] => (data_out[1]:data_in[1])) = (0,0);
		if (~test_enable_n)
                		(data_in[0] => data_out[0]) = 0;
		if (~test_enable_n)
                		(data_in[1] => data_out[0]) = 0;
		if (~test_enable_n)
                		(clk_in[0] => data_out[0]) = 0;
		if (test_enable_n)
		                (posedge clk_in[0] => (data_out[0]:data_in[0])) = (0,0);
		if (test_enable_n)
                		(posedge clk_in[1] => (data_out[0]:data_in[1])) = (0,0);
		if (~test_enable_n)
                		(posedge clk_in[1] => (data_out[0]:data_in[1])) = (0,0);
		$setuphold (posedge clk_in[1], posedge data_in[1], 0, 0, notifier,,, delayed_clk_in_1, delayed_data_in_1);
		$setuphold (posedge clk_in[1], negedge data_in[1], 0, 0, notifier,,, delayed_clk_in_1, delayed_data_in_1);
		$setuphold (posedge clk_in[0], posedge data_in[0], 0, 0, notifier,,, delayed_clk_in_0, delayed_data_in_0);
		$setuphold (posedge clk_in[0], negedge data_in[0], 0, 0, notifier,,, delayed_clk_in_0, delayed_data_in_0);
		$width (posedge clk_in[1], 0, 0, notifier);
		$width (posedge clk_in[0], 0, 0, notifier);
	endspecify
endmodule
module an_io_phdet_ff_ln (q, dn, dp, rst_n, clk_p `ifndef INTCNOPWR ,vcc ,vss `endif);
        output q;
        input dn, dp, rst_n, clk_p;
        reg notifier;
        wire delayed_dn, delayed_dp, delayed_clk_p;
`ifndef INTCNOPWR
input vcc, vss;
`endif

        // Function
        wire int_fwire_Iq, int_fwire_r, xcr_0;

        not (int_fwire_r, rst_n);
        altos_dff_r_err (xcr_0, delayed_clk_p, delayed_dp, int_fwire_r);
        altos_dff_r (int_fwire_Iq, notifier, delayed_clk_p, delayed_dp, int_fwire_r, xcr_0);
        buf (q, int_fwire_Iq);

        // Timing
        specify
                (posedge clk_p => (q+:dp)) = 0;
                $setuphold (posedge clk_p, posedge dn, 0, 0, notifier,,, delayed_clk_p, delayed_dn);
                $setuphold (posedge clk_p, negedge dn, 0, 0, notifier,,, delayed_clk_p, delayed_dn);
                $setuphold (posedge clk_p, posedge dp, 0, 0, notifier,,, delayed_clk_p, delayed_dp);
                $setuphold (posedge clk_p, negedge dp, 0, 0, notifier,,, delayed_clk_p, delayed_dp);
                $width (posedge clk_p, 0, 0, notifier);
        endspecify
endmodule
module aibcr3_dcc_helper ( ckout, clk_dcd, dcc_byp,
     launch, measure, rstb );

output  ckout;

input  clk_dcd, dcc_byp, launch, measure, rstb;

wire net72;
wire net73;
wire net49;
wire net029;
wire net71;
wire launchb;
wire net029_dly;

assign tieHI = 1'b1;
assign tieLO = 1'b0;
assign net075 = ~rstb;
assign net50 = ~net72;
assign net72 = ~net73;
assign net029 = ~net72;
assign #30 net029_dly = net029;
assign net52 = ~net075;
assign ckout = net49;
assign net71 = net029_dly ? measure : launch;
assign net49 = dcc_byp? clk_dcd : net50;
//assign launchb = ~launch;

aibcr3_ulvt16_dffcdn_cust x24 ( .Q(sync1), .CDN(net52), .CK(launch),
     .D(tieHI));
aibcr3_ulvt16_dffcdn_cust x25 ( .Q(sync1out), .CDN(net52), .CK(launch),
     .D(sync1));

aibcr3_ulvt16_dffcdn_cust x23 ( .Q(net73), .CDN(syncrstb), .CK(net71),
     .D(net72));

// 2nd synchronizer
aibcr3_ulvt16_dffcdn_cust x21 ( .Q(net55), .CDN(net52), .CK(launch),
     .D(sync1out));
aibcr3_ulvt16_dffcdn_cust x22 ( .Q(syncrstb), .CDN(net52), .CK(launch),
     .D(net55));



endmodule
module simple(A, B);

   input  [3:0] A;
   output [3:0] B;

   // mix up the input bits
   assign B = { A[0], A[2], A[1], A[3] };

endmodule
module testIm_rom (
	address,
	clock,
	q);

	input	[9:0]  address;
	input	  clock;
	output	[8:0]  q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri1	  clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire [8:0] sub_wire0;
	wire [8:0] q = sub_wire0[8:0];

	altsyncram	altsyncram_component (
				.address_a (address),
				.clock0 (clock),
				.q_a (sub_wire0),
				.aclr0 (1'b0),
				.aclr1 (1'b0),
				.address_b (1'b1),
				.addressstall_a (1'b0),
				.addressstall_b (1'b0),
				.byteena_a (1'b1),
				.byteena_b (1'b1),
				.clock1 (1'b1),
				.clocken0 (1'b1),
				.clocken1 (1'b1),
				.clocken2 (1'b1),
				.clocken3 (1'b1),
				.data_a ({9{1'b1}}),
				.data_b (1'b1),
				.eccstatus (),
				.q_b (),
				.rden_a (1'b1),
				.rden_b (1'b1),
				.wren_a (1'b0),
				.wren_b (1'b0));
	defparam
		altsyncram_component.address_aclr_a = "NONE",
		altsyncram_component.clock_enable_input_a = "BYPASS",
		altsyncram_component.clock_enable_output_a = "BYPASS",
		altsyncram_component.init_file = "../Software/testIm6.mif",
		altsyncram_component.intended_device_family = "Cyclone IV E",
		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
		altsyncram_component.lpm_type = "altsyncram",
		altsyncram_component.numwords_a = 1024,
		altsyncram_component.operation_mode = "ROM",
		altsyncram_component.outdata_aclr_a = "NONE",
		altsyncram_component.outdata_reg_a = "UNREGISTERED",
		altsyncram_component.widthad_a = 10,
		altsyncram_component.width_a = 9,
		altsyncram_component.width_byteena_a = 1;


endmodule
module testIm_ctrl(
  input clock,
  input reset,
  
  input [`SCREEN_X_BITWIDTH:0] x_coord,
  input [`SCREEN_Y_BITWIDTH:0] y_coord,

  output reg [9:0] test_addr
);


// shift left control
always@(posedge clock or negedge reset) begin
  if(reset == 1'b0) begin
    test_addr <= 0;
  end else if( x_coord >= 300 &&
               x_coord < (300 + `SCREEN_X_WIDTH'd`BUFFER_W) &&
               y_coord >= 300 &&
               y_coord < (300 + `SCREEN_Y_WIDTH'd`BUFFER_H)
              )   
    //shift_left <= 1'd1;
    test_addr <= test_addr + 1;
//  else if (x_coord == (300 + `SCREEN_X_WIDTH'd`BUFFER_W) &&
//          y_coord >= 300 &&
//               y_coord < (300 + `SCREEN_Y_WIDTH'd`BUFFER_H - 1) 
//          )   
//    //shift_up <= 1'd1;
//    test_addr <= test_addr + 1;
  else if (x_coord == 0 & y_coord == 0)
    test_addr <= 0;
  else
    test_addr <= test_addr;
end // always

endmodule
module fm_ram_1024w (
	clock,
	data,
	rdaddress,
	wraddress,
	wren,
	q);

	input	  clock;
	input	[23:0]  data;
	input	[9:0]  rdaddress;
	input	[9:0]  wraddress;
	input	  wren;
	output	[23:0]  q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri1	  clock;
	tri0	  wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire [23:0] sub_wire0;
	wire [23:0] q = sub_wire0[23:0];

	altsyncram	altsyncram_component (
				.address_a (wraddress),
				.address_b (rdaddress),
				.clock0 (clock),
				.data_a (data),
				.wren_a (wren),
				.q_b (sub_wire0),
				.aclr0 (1'b0),
				.aclr1 (1'b0),
				.addressstall_a (1'b0),
				.addressstall_b (1'b0),
				.byteena_a (1'b1),
				.byteena_b (1'b1),
				.clock1 (1'b1),
				.clocken0 (1'b1),
				.clocken1 (1'b1),
				.clocken2 (1'b1),
				.clocken3 (1'b1),
				.data_b ({24{1'b1}}),
				.eccstatus (),
				.q_a (),
				.rden_a (1'b1),
				.rden_b (1'b1),
				.wren_b (1'b0));
	defparam
		altsyncram_component.address_aclr_b = "NONE",
		altsyncram_component.address_reg_b = "CLOCK0",
		altsyncram_component.clock_enable_input_a = "BYPASS",
		altsyncram_component.clock_enable_input_b = "BYPASS",
		altsyncram_component.clock_enable_output_b = "BYPASS",
		altsyncram_component.intended_device_family = "Cyclone IV E",
		altsyncram_component.lpm_type = "altsyncram",
		altsyncram_component.numwords_a = 1024,
		altsyncram_component.numwords_b = 1024,
		altsyncram_component.operation_mode = "DUAL_PORT",
		altsyncram_component.outdata_aclr_b = "NONE",
		altsyncram_component.outdata_reg_b = "UNREGISTERED",
		altsyncram_component.power_up_uninitialized = "FALSE",
		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
		altsyncram_component.widthad_a = 10,
		altsyncram_component.widthad_b = 10,
		altsyncram_component.width_a = 24,
		altsyncram_component.width_b = 24,
		altsyncram_component.width_byteena_a = 1;


endmodule
module Sdram_RD_FIFO (
	aclr,
	data,
	rdclk,
	rdreq,
	wrclk,
	wrreq,
	q,
	wrusedw);

	input	  aclr;
	input	[31:0]  data;
	input	  rdclk;
	input	  rdreq;
	input	  wrclk;
	input	  wrreq;
	output	[15:0]  q;
	output	[7:0]  wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0	  aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire [7:0] sub_wire0;
	wire [15:0] sub_wire1;
	wire [7:0] wrusedw = sub_wire0[7:0];
	wire [15:0] q = sub_wire1[15:0];

	dcfifo_mixed_widths	dcfifo_mixed_widths_component (
				.wrclk (wrclk),
				.rdreq (rdreq),
				.aclr (aclr),
				.rdclk (rdclk),
				.wrreq (wrreq),
				.data (data),
				.wrusedw (sub_wire0),
				.q (sub_wire1)
				// synopsys translate_off
				,
				.rdempty (),
				.rdfull (),
				.rdusedw (),
				.wrempty (),
				.wrfull ()
				// synopsys translate_on
				);
	defparam
		dcfifo_mixed_widths_component.intended_device_family = "Cyclone IV E",
		dcfifo_mixed_widths_component.lpm_numwords = 256,
		dcfifo_mixed_widths_component.lpm_showahead = "OFF",
		dcfifo_mixed_widths_component.lpm_type = "dcfifo",
		dcfifo_mixed_widths_component.lpm_width = 32,
		dcfifo_mixed_widths_component.lpm_widthu = 8,
		dcfifo_mixed_widths_component.lpm_widthu_r = 9,
		dcfifo_mixed_widths_component.lpm_width_r = 16,
		dcfifo_mixed_widths_component.overflow_checking = "ON",
		dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
		dcfifo_mixed_widths_component.underflow_checking = "ON",
		dcfifo_mixed_widths_component.use_eab = "ON",
		dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
		dcfifo_mixed_widths_component.wrsync_delaypipe = 4;


endmodule
module Sdram_WR_FIFO (
	aclr,
	data,
	rdclk,
	rdreq,
	wrclk,
	wrreq,
	q,
	rdusedw);

	input	  aclr;
	input	[15:0]  data;
	input	  rdclk;
	input	  rdreq;
	input	  wrclk;
	input	  wrreq;
	output	[31:0]  q;
	output	[7:0]  rdusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0	  aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire [31:0] sub_wire0;
	wire [7:0] sub_wire1;
	wire [31:0] q = sub_wire0[31:0];
	wire [7:0] rdusedw = sub_wire1[7:0];

	dcfifo_mixed_widths	dcfifo_mixed_widths_component (
				.wrclk (wrclk),
				.rdreq (rdreq),
				.aclr (aclr),
				.rdclk (rdclk),
				.wrreq (wrreq),
				.data (data),
				.q (sub_wire0),
				.rdusedw (sub_wire1)
				// synopsys translate_off
				,
				.rdempty (),
				.rdfull (),
				.wrempty (),
				.wrfull (),
				.wrusedw ()
				// synopsys translate_on
				);
	defparam
		dcfifo_mixed_widths_component.intended_device_family = "Cyclone IV E",
		dcfifo_mixed_widths_component.lpm_numwords = 512,
		dcfifo_mixed_widths_component.lpm_showahead = "OFF",
		dcfifo_mixed_widths_component.lpm_type = "dcfifo",
		dcfifo_mixed_widths_component.lpm_width = 16,
		dcfifo_mixed_widths_component.lpm_widthu = 9,
		dcfifo_mixed_widths_component.lpm_widthu_r = 8,
		dcfifo_mixed_widths_component.lpm_width_r = 32,
		dcfifo_mixed_widths_component.overflow_checking = "ON",
		dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
		dcfifo_mixed_widths_component.underflow_checking = "ON",
		dcfifo_mixed_widths_component.use_eab = "ON",
		dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
		dcfifo_mixed_widths_component.wrsync_delaypipe = 4;


endmodule
module char_box(
  input [11:0] gray,
  input [15:0] iX_Cont,
  input [15:0] iY_Cont,
  
  output [11:0] g
  );
  
  wire box;
  
  assign box = (iX_Cont == 16'd300) & (iY_Cont <= 16'd328) & (iY_Cont >= 16'd300) |
					(iX_Cont == 16'd328) & (iY_Cont <= 16'd328) & (iY_Cont >= 16'd300) |
					(iY_Cont == 16'd300) & (iX_Cont <= 16'd328) & (iX_Cont >= 16'd300) |
					(iY_Cont == 16'd328) & (iX_Cont <= 16'd328) & (iX_Cont >= 16'd300);
					
  assign g = box ? 12'hfff : gray;
  endmodule
module rgb2gray(
  input [11:0] r,
  input [11:0] g,
  input [11:0] b,
  output [11:0] gray
  );
  wire [13:0] sum0;
  wire [13:0] sum1;
  wire [13:0]gray_wire;
  
  assign sum0 = r+b;
  assign sum1 = sum0+g;
  assign gray_wire = sum1 / 14'd3;
  
  // 12 bit color channel
  //assign gray = (gray_wire[13:12] == 2'd0) ? gray_wire[11:0] : 12'hfff;
  // 9 bit color channel
  assign gray = (gray_wire[13:12] == 2'd0) ? { gray_wire[11:3],3'd0 } : 12'hff8;
  endmodule
module CCD_Capture(	oDATA,
					oDVAL,
					oX_Cont,
					oY_Cont,
					oFrame_Cont,
					iDATA,
					iFVAL,
					iLVAL,
					iSTART,
					iEND,
					iCLK,
					iRST
					);
					
input	[11:0]	iDATA;
input			iFVAL;
input			iLVAL;
input			iSTART;
input			iEND;
input			iCLK;
input			iRST;
output	[11:0]	oDATA;
output	[15:0]	oX_Cont;
output	[15:0]	oY_Cont;
output	[31:0]	oFrame_Cont;
output			oDVAL;
reg				Pre_FVAL;
reg				mCCD_FVAL;
reg				mCCD_LVAL;
reg		[11:0]	mCCD_DATA;
reg		[15:0]	X_Cont;
reg		[15:0]	Y_Cont;
reg		[31:0]	Frame_Cont;
reg				mSTART;

`ifdef VGA_640x480p60
parameter COLUMN_WIDTH = 1280;
`else
parameter COLUMN_WIDTH = 800;
`endif  

assign	oX_Cont		=	X_Cont;
assign	oY_Cont		=	Y_Cont;
assign	oFrame_Cont	=	Frame_Cont;
assign	oDATA		=	mCCD_DATA;
assign	oDVAL		=	mCCD_FVAL&mCCD_LVAL;

always@(posedge iCLK or negedge iRST)
begin
	if(!iRST)
	mSTART	<=	0;
	else
	begin
		if(iSTART)
		mSTART	<=	1;
		if(iEND)
		mSTART	<=	0;		
	end
end

always@(posedge iCLK or negedge iRST)
begin
	if(!iRST)
	begin
		Pre_FVAL	<=	0;
		mCCD_FVAL	<=	0;
		mCCD_LVAL	<=	0;

		X_Cont		<=	0;
		Y_Cont		<=	0;
	end
	else
	begin
		Pre_FVAL	<=	iFVAL;
		if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
		mCCD_FVAL	<=	1;
		else if({Pre_FVAL,iFVAL}==2'b10)
		mCCD_FVAL	<=	0;
		mCCD_LVAL	<=	iLVAL;
		if(mCCD_FVAL)
		begin
			if(mCCD_LVAL)
			begin
				if(X_Cont<(COLUMN_WIDTH-1))
				X_Cont	<=	X_Cont+1;
				else
				begin
					X_Cont	<=	0;
					Y_Cont	<=	Y_Cont+1;
				end
			end
		end
		else
		begin
			X_Cont	<=	0;
			Y_Cont	<=	0;
		end
	end
end

always@(posedge iCLK or negedge iRST)
begin
	if(!iRST)
	Frame_Cont	<=	0;
	else
	begin
		if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
		Frame_Cont	<=	Frame_Cont+1;
	end
end

always@(posedge iCLK or negedge iRST)
begin
	if(!iRST)
		mCCD_DATA	<=	0;
	else if (iLVAL)
		mCCD_DATA	<=	iDATA;
	else
		mCCD_DATA	<=	0;	
end			

reg	ifval_dealy;

wire ifval_fedge;	
reg	[15:0]	y_cnt_d;


always@(posedge iCLK or negedge iRST)
begin
	if(!iRST)
		y_cnt_d	<=	0;
	else
		y_cnt_d	<=	Y_Cont;	
end


always@(posedge iCLK or negedge iRST)
begin
	if(!iRST)
		ifval_dealy	<=	0;
	else
		ifval_dealy	<=	iFVAL;	
end

assign ifval_fedge = ({ifval_dealy,iFVAL}==2'b10)?1:0;  


endmodule
module Line_Buffer (
	clken,
	clock,
	shiftin,
	shiftout,
	taps0x,
	taps1x,
	taps2x);

	input	  clken;
	input	  clock;
	input	[11:0]  shiftin;
	output	[11:0]  shiftout;
	output	[11:0]  taps0x;
	output	[11:0]  taps1x;
	output	[11:0]  taps2x;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri1	  clken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire [35:0] sub_wire0;
	wire [11:0] sub_wire5;
	wire [23:12] sub_wire3 = sub_wire0[23:12];
	wire [11:0] sub_wire4 = sub_wire0[11:0];
	wire [35:24] sub_wire2 = sub_wire0[35:24];
	wire [35:24] sub_wire1 = sub_wire2[35:24];
	wire [11:0] taps2x = sub_wire1[35:24];
	wire [11:0] taps1x = sub_wire3[23:12];
	wire [11:0] taps0x = sub_wire4[11:0];
	wire [11:0] shiftout = sub_wire5[11:0];

	altshift_taps	altshift_taps_component (
				.clken (clken),
				.clock (clock),
				.shiftin (shiftin),
				.taps (sub_wire0),
				.shiftout (sub_wire5)
				// synopsys translate_off
				,
				.aclr ()
				// synopsys translate_on
				);
	defparam
		altshift_taps_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
		altshift_taps_component.lpm_type = "altshift_taps",
		altshift_taps_component.number_of_taps = 3,
		altshift_taps_component.tap_distance = 800,
		altshift_taps_component.width = 12;


endmodule
module RAW2RGB(	oRed,
				oGreen,
				oBlue,
				oDVAL,
				iX_Cont,
				iY_Cont,
				iDATA,
				iDVAL,
				iCLK,
				iRST
				);

input	[10:0]	iX_Cont;
input	[10:0]	iY_Cont;
input	[11:0]	iDATA;
input			iDVAL;
input			iCLK;
input			iRST;
output	[11:0]	oRed;
output	[11:0]	oGreen;
output	[11:0]	oBlue;
output			oDVAL;
wire	[11:0]	mDATA_0;
wire	[11:0]	mDATA_1;
reg		[11:0]	mDATAd_0;
reg		[11:0]	mDATAd_1;
reg		[11:0]	mCCD_R;
reg		[12:0]	mCCD_G;
reg		[11:0]	mCCD_B;
reg				mDVAL;

assign	oRed	=	mCCD_R[11:0];
assign	oGreen	=	mCCD_G[12:1];
assign	oBlue	=	mCCD_B[11:0];
assign	oDVAL	=	mDVAL;

Line_Buffer1 	u0	(	.clken(iDVAL),
						.clock(iCLK),
						.shiftin(iDATA),
						.taps0x(mDATA_1),
						.taps1x(mDATA_0)	);

always@(posedge iCLK or negedge iRST)
begin
	if(!iRST)
	begin
		mCCD_R	<=	0;
		mCCD_G	<=	0;
		mCCD_B	<=	0;
		mDATAd_0<=	0;
		mDATAd_1<=	0;
		mDVAL	<=	0;
	end
	else
	begin
		mDATAd_0	<=	mDATA_0;
		mDATAd_1	<=	mDATA_1;
		mDVAL		<=	{iY_Cont[0]|iX_Cont[0]}	?	1'b0	:	iDVAL;
		if({iY_Cont[0],iX_Cont[0]}==2'b10)
		begin
			mCCD_R	<=	mDATA_0;
			mCCD_G	<=	mDATAd_0+mDATA_1;
			mCCD_B	<=	mDATAd_1;
		end	
		else if({iY_Cont[0],iX_Cont[0]}==2'b11)
		begin
			mCCD_R	<=	mDATAd_0;
			mCCD_G	<=	mDATA_0+mDATAd_1;
			mCCD_B	<=	mDATA_1;
		end
		else if({iY_Cont[0],iX_Cont[0]}==2'b00)
		begin
			mCCD_R	<=	mDATA_1;
			mCCD_G	<=	mDATA_0+mDATAd_1;
			mCCD_B	<=	mDATAd_0;
		end
		else if({iY_Cont[0],iX_Cont[0]}==2'b01)
		begin
			mCCD_R	<=	mDATAd_1;
			mCCD_G	<=	mDATAd_0+mDATA_1;
			mCCD_B	<=	mDATA_0;
		end
	end
end

endmodule
module	Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2,oRST_3,oRST_4);
input		iCLK;
input		iRST;
output reg	oRST_0;
output reg	oRST_1;
output reg	oRST_2;
output reg	oRST_3;
output reg	oRST_4;

reg	[31:0]	Cont;

always@(posedge iCLK or negedge iRST)
begin
	if(!iRST)
	begin
		Cont	<=	0;
		oRST_0	<=	0;
		oRST_1	<=	0;
		oRST_2	<=	0;
		oRST_3	<=	0;
		oRST_4	<=	0;
	end
	else
	begin
		if(Cont!=32'h01FFFFFF)
		Cont	<=	Cont+1;
		if(Cont>=32'h001FFFFF)
		oRST_0	<=	1;
		if(Cont>=32'h002FFFFF)
		oRST_1	<=	1;
		if(Cont>=32'h011FFFFF)
		oRST_2	<=	1;
		if(Cont>=32'h016FFFFF)
		oRST_3	<=	1;
		if(Cont>=32'h01FFFFFF)
		oRST_4	<=	1;
	end
end

endmodule
module I2C_Controller (
	CLOCK,
	I2C_SCLK,//I2C CLOCK
 	I2C_SDAT,//I2C DATA
	I2C_DATA,//DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
	GO,      //GO transfor
	END,     //END transfor 
	W_R,     //W_R
	ACK,      //ACK
	RESET

);
	input  CLOCK;
	input  [31:0]I2C_DATA;	
	input  GO;
	input  RESET;	
	input  W_R;
 	inout  I2C_SDAT;	
	output I2C_SCLK;
	output END;	
	output ACK;

reg SDO;
reg SCLK;
reg END;
reg [31:0]SD;
reg [6:0]SD_COUNTER;

wire I2C_SCLK=SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <=39))? ~CLOCK :0 );
wire I2C_SDAT=SDO?1'bz:0 ;

reg ACK1,ACK2,ACK3,ACK4;
wire ACK=ACK1 | ACK2 |ACK3 |ACK4;

//--I2C COUNTER
always @(negedge RESET or posedge CLOCK ) begin
if (!RESET) SD_COUNTER=6'b111111;
else begin
if (GO==0) 
	SD_COUNTER=0;
	else 
	if (SD_COUNTER < 41) SD_COUNTER=SD_COUNTER+1;	
end
end
//----

always @(negedge RESET or  posedge CLOCK ) begin
if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0;ACK4=0; END=1; end
else
case (SD_COUNTER)
	6'd0  : begin ACK1=0 ;ACK2=0 ;ACK3=0 ;ACK4=0 ; END=0; SDO=1; SCLK=1;end
	//start
	6'd1  : begin SD=I2C_DATA;SDO=0;end
	6'd2  : SCLK=0;
	//SLAVE ADDR
	6'd3  : SDO=SD[31];
	6'd4  : SDO=SD[30];
	6'd5  : SDO=SD[29];
	6'd6  : SDO=SD[28];
	6'd7  : SDO=SD[27];
	6'd8  : SDO=SD[26];
	6'd9  : SDO=SD[25];
	6'd10 : SDO=SD[24];	
	6'd11 : SDO=1'b1;//ACK

	//SUB ADDR
	6'd12  : begin SDO=SD[23]; ACK1=I2C_SDAT; end
	6'd13  : SDO=SD[22];
	6'd14  : SDO=SD[21];
	6'd15  : SDO=SD[20];
	6'd16  : SDO=SD[19];
	6'd17  : SDO=SD[18];
	6'd18  : SDO=SD[17];
	6'd19  : SDO=SD[16];
	6'd20  : SDO=1'b1;//ACK

	//DATA
	6'd21  : begin SDO=SD[15]; ACK2=I2C_SDAT; end
	6'd22  : SDO=SD[14];
	6'd23  : SDO=SD[13];
	6'd24  : SDO=SD[12];
	6'd25  : SDO=SD[11];
	6'd26  : SDO=SD[10];
	6'd27  : SDO=SD[9];
	6'd28  : SDO=SD[8];
	6'd29  : SDO=1'b1;//ACK

	//DATA
	6'd30  : begin SDO=SD[7]; ACK3=I2C_SDAT; end
	6'd31  : SDO=SD[6];
	6'd32  : SDO=SD[5];
	6'd33  : SDO=SD[4];
	6'd34  : SDO=SD[3];
	6'd35  : SDO=SD[2];
	6'd36  : SDO=SD[1];
	6'd37  : SDO=SD[0];
	6'd38  : SDO=1'b1;//ACK

	
	//stop
    6'd39 : begin SDO=1'b0;	SCLK=1'b0; ACK4=I2C_SDAT; end	
    6'd40 : SCLK=1'b1; 
    6'd41 : begin SDO=1'b1; END=1; end 

endcase
end



endmodule
module Line_Buffer1 (
	clken,
	clock,
	shiftin,
	shiftout,
	taps0x,
	taps1x);

	input	  clken;
	input	  clock;
	input	[11:0]  shiftin;
	output	[11:0]  shiftout;
	output	[11:0]  taps0x;
	output	[11:0]  taps1x;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri1	  clken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire [23:0] sub_wire0;
	wire [11:0] sub_wire3;
	wire [23:12] sub_wire1 = sub_wire0[23:12];
	wire [11:0] sub_wire2 = sub_wire0[11:0];
	wire [11:0] taps1x = sub_wire1[23:12];
	wire [11:0] taps0x = sub_wire2[11:0];
	wire [11:0] shiftout = sub_wire3[11:0];

	altshift_taps	altshift_taps_component (
				.clken (clken),
				.clock (clock),
				.shiftin (shiftin),
				.taps (sub_wire0),
				.shiftout (sub_wire3)
				// synopsys translate_off
				,
				.aclr ()
				// synopsys translate_on
				);
	defparam
		altshift_taps_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
		altshift_taps_component.lpm_type = "altshift_taps",
		altshift_taps_component.number_of_taps = 2,
		altshift_taps_component.tap_distance = 1280,
		altshift_taps_component.width = 12;


endmodule
module SEG7_LUT_8 (	oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7,iDIG );
input	[31:0]	iDIG;
output	[6:0]	oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7;

SEG7_LUT	u0	(	oSEG0,iDIG[3:0]		);
SEG7_LUT	u1	(	oSEG1,iDIG[7:4]		);
SEG7_LUT	u2	(	oSEG2,iDIG[11:8]	);
SEG7_LUT	u3	(	oSEG3,iDIG[15:12]	);
SEG7_LUT	u4	(	oSEG4,iDIG[19:16]	);
SEG7_LUT	u5	(	oSEG5,iDIG[23:20]	);
SEG7_LUT	u6	(	oSEG6,iDIG[27:24]	);
SEG7_LUT	u7	(	oSEG7,iDIG[31:28]	);

endmodule
module SEG7_LUT	(	oSEG,iDIG	);
input	[3:0]	iDIG;
output	[6:0]	oSEG;
reg		[6:0]	oSEG;

always @(iDIG)
begin
		case(iDIG)
		4'h1: oSEG = 7'b1111001;	// ---t----
		4'h2: oSEG = 7'b0100100; 	// |	  |
		4'h3: oSEG = 7'b0110000; 	// lt	 rt
		4'h4: oSEG = 7'b0011001; 	// |	  |
		4'h5: oSEG = 7'b0010010; 	// ---m----
		4'h6: oSEG = 7'b0000010; 	// |	  |
		4'h7: oSEG = 7'b1111000; 	// lb	 rb
		4'h8: oSEG = 7'b0000000; 	// |	  |
		4'h9: oSEG = 7'b0011000; 	// ---b----
		4'ha: oSEG = 7'b0001000;
		4'hb: oSEG = 7'b0000011;
		4'hc: oSEG = 7'b1000110;
		4'hd: oSEG = 7'b0100001;
		4'he: oSEG = 7'b0000110;
		4'hf: oSEG = 7'b0001110;
		4'h0: oSEG = 7'b1000000;
		endcase
end

endmodule
module feature_map_ram_1024w (
	clock,
	data,
	rdaddress,
	wraddress,
	wren,
	q);

	parameter init_file = "";
	
	input	  clock;
	input	[23:0]  data;
	input	[9:0]  rdaddress;
	input	[9:0]  wraddress;
	input	  wren;
	output	[23:0]  q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri1	  clock;
	tri0	  wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire [23:0] sub_wire0;
	wire [23:0] q = sub_wire0[23:0];

	altsyncram	altsyncram_component (
				.address_a (wraddress),
				.address_b (rdaddress),
				.clock0 (clock),
				.data_a (data),
				.wren_a (wren),
				.q_b (sub_wire0),
				.aclr0 (1'b0),
				.aclr1 (1'b0),
				.addressstall_a (1'b0),
				.addressstall_b (1'b0),
				.byteena_a (1'b1),
				.byteena_b (1'b1),
				.clock1 (1'b1),
				.clocken0 (1'b1),
				.clocken1 (1'b1),
				.clocken2 (1'b1),
				.clocken3 (1'b1),
				.data_b ({24{1'b1}}),
				.eccstatus (),
				.q_a (),
				.rden_a (1'b1),
				.rden_b (1'b1),
				.wren_b (1'b0));
	defparam
		altsyncram_component.address_aclr_b = "NONE",
		altsyncram_component.address_reg_b = "CLOCK0",
		altsyncram_component.clock_enable_input_a = "BYPASS",
		altsyncram_component.clock_enable_input_b = "BYPASS",
		altsyncram_component.clock_enable_output_b = "BYPASS",
		altsyncram_component.init_file = init_file,
		altsyncram_component.intended_device_family = "Cyclone IV E",
		altsyncram_component.lpm_type = "altsyncram",
		altsyncram_component.numwords_a = 1024,
		altsyncram_component.numwords_b = 1024,
		altsyncram_component.operation_mode = "DUAL_PORT",
		altsyncram_component.outdata_aclr_b = "NONE",
		altsyncram_component.outdata_reg_b = "UNREGISTERED",
		altsyncram_component.power_up_uninitialized = "FALSE",
		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
		altsyncram_component.widthad_a = 10,
		altsyncram_component.widthad_b = 10,
		altsyncram_component.width_a = 24,
		altsyncram_component.width_b = 24,
		altsyncram_component.width_byteena_a = 1;


endmodule
module nh_shift_reg_ctrl(
  input clock,
  input reset,
  
  input shift_in_rdy,
  input [`NH_BITWIDTH:0] shift_in,
  
  output dval,
  output [(`NH_WIDTH*`NH_SIZE)-1:0] current_nh
);

// wire declarations
wire [`NH_BITWIDTH:0] shift_ins [`NH_DIM-1:0]; 
wire [(`NH_SIZE*2)-1:0] reg_valid;

// reg declarations
reg [`NH_BITWIDTH:0] nh_reg [`NH_DIM-1:0][`NH_DIM-1:0];

// assign statments
assign dval = reg_valid[0];



// instantiate the shift registers to hold the current nh
genvar i;
genvar j;
generate 
for (j=0; j<`NH_DIM-1; j=j+1) begin : nh_row_loop
  for (i=0; i<`NH_DIM-1; i=i+1) begin : le_sr_inst 
    // assign dval signal to wire 
    assign reg_valid[(j*`NH_DIM+i)+`NH_SIZE] = nh_reg[i][j];
    // connect nh le's into shift reg
    always@(posedge clock or negedge reset) begin
      if(reset == 1'b0) begin
        nh_reg[i][j] <= `NH_WIDTH'd0;
      end else begin
        nh_reg[i][j] <= nh_reg[i+1][j];
      end // reset
    end // always
  end // for i
end // for j 
endgenerate


// instantiate shift register to buffer the part of the line not in nh
genvar k;
generate
for( k=0; k<`NH_DIM-1; i=i+1) begin : ram_sr_inst
  ram_sr sr_inst(
    .clock(clock),
    .shift_in({shift_in_rdy, nh_reg[`NH_DIM-1][k]}),
    .shift_out(nh_reg[0][k+1])
  );
end // for
endgenerate

// OR the data valid signals
genvar m;
generate
for (m=0; m<(`NH_SIZE*2)-1; m=m+1) begin: or_loop
  assign reg_valid[(m/2)-1] = reg_valid[m] | reg_valid[m-1];
end // for
endgenerate
  
endmodule
module nh_shift_reg(
  input clock,
  input reset,
  
  input shift_in_rdy,
  input [`NH_BITWIDTH:0] shift_in,
  
  output dval,
  output [`NH_BITWIDTH:0] nh_max
);

// wire declarations
//wire [`NH_BITWIDTH:0] shift_ins [`NH_DIM-1:0]; 
wire [(`NH_SIZE*2)-2:0] reg_valid;
wire [`NH_BITWIDTH:0] nh_row_max [`NH_DIM-1:0];
wire [`NH_BITWIDTH+1:0] nh_sr_wire [`NH_SR_DEPTH-1:0];

// reg declarations
reg [`NH_BITWIDTH+1:0] nh_reg [`NH_DIM-1:0][`NH_DIM-1:0];

// assign statments
assign dval = reg_valid[0];

// connect nh window and sr buffer
//always@(*) begin
always@(posedge clock or negedge reset) begin
  if( reset == 1'b0) begin
    nh_reg[1][1] <= {1'd0, `NH_WIDTH'd0};
    nh_reg[1][0] <= {1'd0, `NH_WIDTH'd0};
  end else begin
    nh_reg[1][1] <= {shift_in_rdy, shift_in};
    nh_reg[1][0] <= nh_sr_wire[`NH_SR_DEPTH-1];
  end
end
  
assign nh_sr_wire[0] = nh_reg[0][1]; 


// instantiate the shift registers to hold the current nh
genvar i;
genvar j;
generate 
for (j=0; j<`NH_DIM; j=j+1) begin : nh_row_loop
  for (i=0; i<`NH_DIM-1; i=i+1) begin : le_sr_inst 
    // assign dval signal to wire 
//    assign reg_valid[(j*`NH_DIM+i)+`NH_SIZE] = nh_reg[i][j][`NH_BITWIDTH+1];
    // connect nh le's into shift reg
    always@(posedge clock or negedge reset) begin
      if(reset == 1'b0) begin
        nh_reg[i][j] <= `NH_WIDTH'd0;
      end else begin
        nh_reg[i][j] <= nh_reg[i+1][j];
      end // reset
    end // always
  end // for i
end // for j 
endgenerate

generate
for (j=0; j<`NH_DIM; j=j+1) begin : valid_row_loop
  for (i=0; i<`NH_DIM; i=i+1) begin : valid_height_loop 
    // assign dval signal to wire 
    assign reg_valid[(j*`NH_DIM+i)+`NH_SIZE-1] = nh_reg[i][j][`NH_BITWIDTH+1];
  end // i
end // j
endgenerate

// instantiate shift register to buffer the part of the line not in nh 
genvar k;
generate
for( k=0; k<`NH_SR_DEPTH-1; k=k+1) begin : ram_sr_inst
  nh_sr_unit nh_sr_unit_inst(
    .clock(clock),
    .reset(reset),
    .shift_in(nh_sr_wire[k]),
    .shift_out(nh_sr_wire[k+1])
  );
end // for
endgenerate

// AND the data valid signals
genvar m;
generate
for (m=(`NH_SIZE*2)-2; m>=1; m=m-2) begin: or_loop
  assign reg_valid[(m/2)-1] = reg_valid[m] & reg_valid[m-1];
end // for
endgenerate

// Find the Maximum in the NH
//////////////////////////////
// HARD CODED TO NH_DIM = 2 //
//////////////////////////////
assign nh_row_max[0] = (nh_reg[0][0][`NH_BITWIDTH:0] > nh_reg[0][1][`NH_BITWIDTH:0]) ? nh_reg[0][0][`NH_BITWIDTH:0] : nh_reg[0][1][`NH_BITWIDTH:0];
assign nh_row_max[1] = (nh_reg[1][0][`NH_BITWIDTH:0] > nh_reg[1][1][`NH_BITWIDTH:0]) ? nh_reg[1][0][`NH_BITWIDTH:0] : nh_reg[1][1][`NH_BITWIDTH:0];
assign nh_max = (nh_row_max[0] > nh_row_max[1]) ? nh_row_max[0] : nh_row_max[1];

endmodule
module nh_sr_unit (
  input clock,
  input reset,
  input [`NH_BITWIDTH+1:0] shift_in,

  output reg [`NH_BITWIDTH+1:0] shift_out
);

always@(posedge clock or negedge reset) begin
  if(reset == 1'b0)
    shift_out <= {1'd0, `NH_WIDTH'd0};
  else
    shift_out <= shift_in;
end // always

endmodule
module mult_adder(
      input     clock, 
		  input     reset, 
		  input [`MULT_ADDER_IN_BITWIDTH:0]  in,
		  input [`MULT_ADDER_IN_BITWIDTH:0]  kernal,
		  input [`CONV_ADD_BITWIDTH:0] bias,
		  output [`CONV_ADD_BITWIDTH:0] out	
		  );

// wire declarations
wire [`CONV_PRODUCT_BITWIDTH:0] in_add_vector_wire [`MA_TREE_SIZE-1:0];
wire [`CONV_ADD_BITWIDTH:0] adder_tree_wire [((`MA_TREE_SIZE*2)-1)-1:0];
wire [(`MA_TREE_SIZE*2)-1-1:0]carry_wire ;  

// assign statments
assign out = adder_tree_wire[0] + bias;
assign carry_wire [(`MA_TREE_SIZE*2)-1-1:`MA_TREE_SIZE-1] = `MA_TREE_SIZE'd0;

// connect input vector to multipliers
genvar i;
generate
//for(i = 0; i < `KERNEL_SIZE_SQ; i=i+1) begin : connect_mul
for(i = 0; i < `MA_TREE_SIZE; i=i+1) begin : connect_mul
   mult_adder_mult ma_mult_inst(
    .clock(clock),
    .reset(reset),
    .operand_a(in[`CONV_MULT_WIDTH*(i+1)-1:i*`CONV_MULT_WIDTH]),
    .operand_b(kernal[`CONV_MULT_WIDTH*(i+1)-1:i*`CONV_MULT_WIDTH]),
    .out(in_add_vector_wire[i])
			     ); 
  end
endgenerate

// map products to adder tree wire
//genvar i;
genvar pad_count;
generate
//for(i = 0; i < `KERNEL_SIZE_SQ; i=i+1) begin : connect_in_vector
for(i = 0; i < `MA_TREE_SIZE; i=i+1) begin : connect_in_vector
    // assign the lsbs here
    // assign adder_tree_wire[i+`MA_TREE_SIZE-1][`CONV_PRODUCT_BITWIDTH:0] = in[(`CONV_PRODUCT_WIDTH*i)+`CONV_PRODUCT_BITWIDTH:`CONV_PRODUCT_WIDTH*i];
	 assign adder_tree_wire[i+`MA_TREE_SIZE-1][`CONV_PRODUCT_BITWIDTH:0] = in_add_vector_wire[i];
    // loop over msb and assign sign bit here
    for(pad_count=0; pad_count<`MULT_PAD_WIDTH; pad_count=pad_count+1) begin : sign_bit_extention_loop
      //assign adder_tree_wire[i+`MA_TREE_SIZE-1][`CONV_PRODUCT_WIDTH+pad_count] = in[(`CONV_PRODUCT_WIDTH*i)+`CONV_PRODUCT_BITWIDTH];
		assign adder_tree_wire[i+`MA_TREE_SIZE-1][`CONV_PRODUCT_WIDTH+pad_count] = in_add_vector_wire[i][`CONV_PRODUCT_BITWIDTH];
    end // pad count 
  end
endgenerate

// connect adder tree
genvar j;
generate
//for(j= (`KERNIL_SIZE_SQ*2)-2 ; j >=1 ; j=j-2) begin : sum_products
for(j= (`MA_TREE_SIZE*2)-2 ; j >=1 ; j=j-2) begin : sum_products
  mult_adder_add ma_add_inst(
    .clock(clock),
    .reset(reset),
    .operand_a(adder_tree_wire[j-1]),
    .operand_b(adder_tree_wire[j]),
    .c_a(carry_wire[j-1]),
    .c_b(carry_wire[j]),
    .out(adder_tree_wire[(j/2)-1]),
    .carry(carry_wire[(j/2)-1])
  );  

end // for
endgenerate
   
endmodule // mult_adder
module mult_adder_mult(
  input clock,
  input reset,
  input signed [`CONV_MULT_BITWIDTH:0] operand_a,
  input signed [`CONV_MULT_BITWIDTH:0] operand_b,
  output [`CONV_PRODUCT_BITWIDTH:0] out 
);
   reg signed[`CONV_PRODUCT_BITWIDTH:0]    product;
   
   assign out = product[`CONV_PRODUCT_BITWIDTH:0];

   always@(posedge clock or negedge reset) begin
      if(reset == 1'b0) 
	      product <= `CONV_PRODUCT_WIDTH'd0;
      else  
	      product <= operand_a * operand_b;
   end // always
endmodule
module mult_adder_add(
  input clock,
  input reset,
  input [`CONV_ADD_BITWIDTH:0] operand_a,
  input [`CONV_ADD_BITWIDTH:0] operand_b,
  input c_a, // overflow or carry indicators
  input c_b,
  output [`CONV_ADD_BITWIDTH:0] out,
  output carry
);
   reg [`CONV_ADD_BITWIDTH+1:0]    sum;

   assign out = sum[`CONV_ADD_BITWIDTH:0];
   assign carry = sum[`CONV_ADD_BITWIDTH + 1] | c_a | c_b;
   
   always@(posedge clock or negedge reset) begin
      if(reset == 1'b0) 
	      sum <= {1'b0,`CONV_ADD_WIDTH'd0};
      else  
	      sum <= operand_a + operand_b;
   end // always
   endmodule
module shifting_window(
  input clock,
  input reset,
  input shift_up, // shift all rows up
  input shift_left, // to load new pixel into bottom row
  input [`CAMERA_PIXEL_BITWIDTH:0] pixel_in,
  output [`BUFFER_OUT_VECTOR_BITWIDTH:0] buffer_out 
);

// paremeters


// wire declarations
wire [`CAMERA_PIXEL_BITWIDTH:0] buffer_wire [`BUFFER_BW:0][`BUFFER_BH:0];

// reg declarations


  genvar i;
  genvar j;
  generate
    for(j=1;j < `BUFFER_H; j=j+1) begin : core_buffer_h_loop
      for(i=0; i < `BUFFER_W; i=i+1) begin : core_buffer_w_loop
        buffer_unit unit_inst(
          .clock(clock),
          .reset(reset),
          .shift(shift_up),
          .in(buffer_wire[i][j-1]), // bottom to top (height) 
          .out(buffer_wire[i][j])
        );
      end
    end
  endgenerate

  // loop over first row of width and height
  genvar k;
  generate 
  for (k = 1; k < `BUFFER_W; k=k+1) begin : width_row0_loop
    buffer_unit w_row0_unit_inst(
      .clock(clock),
      .reset(reset),
      .shift(shift_left),
      .in(buffer_wire[k-1][0]), // right to left (width)
      .out(buffer_wire[k][0])
    );
  end // for

  endgenerate

  // instantiate origin window unit
  buffer_unit origin_unit_inst(
      .clock(clock),
      .reset(reset),
      .shift(shift_left),
      .in(pixel_in), // right to left (width)
      .out(buffer_wire[0][0])
    );
 



  // loop to connect buffer out vector to buffer_wire
  genvar n;
  genvar m;
  generate
    for (n=0; n < `BUFFER_H; n=n+1) begin : buffer_height_loop
      for (m=0; m < `BUFFER_W; m=m+1) begin : buffer_width_loop
        /*
        assign buffer_wire[m][n] = buffer_out[
        (`CAMERA_PIXEL_WIDTH*m)+(`BUFFER_W*`CAMERA_PIXEL_WIDTH*n) +`CAMERA_PIXEL_BITWIDTH:
          (`CAMERA_PIXEL_WIDTH*m)+(`BUFFER_W*`CAMERA_PIXEL_WIDTH*n)
          ];
        */
       assign buffer_out[
        (`CAMERA_PIXEL_WIDTH*m)+(`BUFFER_W*`CAMERA_PIXEL_WIDTH*n) +`CAMERA_PIXEL_BITWIDTH:
          (`CAMERA_PIXEL_WIDTH*m)+(`BUFFER_W*`CAMERA_PIXEL_WIDTH*n)
          ] = buffer_wire[m][n];
      end // for m
    end // for n
  endgenerate

endmodule
module buffer_unit(
  input clock,
  input reset,
  input shift,
  input [`CAMERA_PIXEL_BITWIDTH:0] in,
  output reg [`CAMERA_PIXEL_BITWIDTH:0] out
);
  always@(posedge clock or negedge reset) begin
    if(reset == 1'b0)
      out <= `CAMERA_PIXEL_WIDTH'd0;
    else if(shift) 
        out <= in;
      else
        out <= out;
  end // always
endmodule
module fm_coord_sr (
  input clock,
  input reset,
  
  input [`X_COORD_BITWIDTH:0] x_coord, // from mult adder ctrl
  input [`Y_COORD_BITWIDTH:0] y_coord, // from mult adder ctrl
  output [`X_COORD_BITWIDTH:0] fm_x_coord, // from mult adder ctrl
  output [`Y_COORD_BITWIDTH:0] fm_y_coord // from mult adder ctrl
);

// reg declarations
reg [`X_COORD_BITWIDTH:0] xc [`FM_COORD_SR_DEPTH-1:0];
reg [`Y_COORD_BITWIDTH:0] yc [`FM_COORD_SR_DEPTH-1:0];


// assign statments
assign fm_x_coord = xc[`FM_COORD_SR_DEPTH-1];
assign fm_y_coord = yc[`FM_COORD_SR_DEPTH-1];


// input to shift reg
always@(posedge clock or negedge reset) begin
  if(reset == 1'b0) begin
    xc[0] <= `X_COORD_WIDTH'd0;
    yc[0] <= `Y_COORD_WIDTH'd0;
  end else begin 
    xc[0] <= x_coord;
    yc[0] <= y_coord;
  end // reset 
end // always

// loop to build shift reg
genvar i;
generate
for (i=0; i<`FM_COORD_SR_DEPTH-1; i=i+1) begin : coord_sr_gen
  always@(posedge clock or negedge reset) begin 
    if(reset == 1'b0) begin
      xc[i+1] <= `X_COORD_WIDTH'd0;
      yc[i+1] <= `Y_COORD_WIDTH'd0;
    end else begin
      xc[i+1] <= xc[i];
      yc[i+1] <= yc[i];
    end // reset
  end // always
end // for
endgenerate

endmodule
module window_wrapper(
  input clock,
  input reset,
  // buffer inputs
  input [`CAMERA_PIXEL_BITWIDTH:0] pixel_in,
  input shift_left,
  input shift_up,
  // window inputs
  input [`X_COORD_BITWIDTH:0] kernel_x, // the bottom right corner of the kernel position
  input [`Y_COORD_BITWIDTH:0] kernel_y, // the bottom right corner of the kernel position

  // the kernel sized view of the buffer to be fed into the multipliers
  output [`WINDOW_VECTOR_BITWIDTH:0] window_out 
);

// wire declarations
wire [`BUFFER_OUT_VECTOR_BITWIDTH:0] buffer_vector;
wire [`CAMERA_PIXEL_BITWIDTH:0] window_wire [`KERNEL_SIZE-1:0][`KERNEL_SIZE-1:0];

// reg declarations


// instantiate shifting window
shifting_window shifting_window_inst(
  .clock(clock),
  .reset(reset),
  .shift_up(shift_up), // shift all rows up
  .shift_left(shift_left), // to load new pixel into bottom row
  .pixel_in(pixel_in),
  .buffer_out(buffer_vector) 
);

// generate window selectors
genvar i;
genvar j;
generate
for (j=0; j<`KERNEL_SIZE; j=j+1) begin : selector_height_loop
  for (i=0; i<`KERNEL_SIZE; i=i+1) begin : selector_width_loop
    window_selector selector_inst(
      .clock(clock),
      .reset(reset),
      .buffer_vector(buffer_vector),
      .x(kernel_x+i),
      .y(kernel_y+j),
      .value_out(window_wire[i][j])
    );
  end // for i
end // for j
endgenerate

genvar n;
genvar m;
generate
for (n=0; n<`KERNEL_SIZE; n=n+1) begin : kernel_h_loop
  for (m=0; m<`KERNEL_SIZE; m=m+1) begin : kernel_w_loop
    assign window_out[
    (`CAMERA_PIXEL_WIDTH*m)+(`KERNEL_SIZE*`CAMERA_PIXEL_WIDTH*n)+`CAMERA_PIXEL_BITWIDTH:
    (`CAMERA_PIXEL_WIDTH*m)+(`KERNEL_SIZE*`CAMERA_PIXEL_WIDTH*n)
    ] = window_wire[m][n];
  end // for m
end // for n
endgenerate


endmodule
module read_port_mux( // combinds several sram read ports into one address space
  input clock,
  input reset,
 
  input [`RAM_SELECT_BITWIDTH:0] ram_select,
  input [(`FFN_IN_WIDTH*`NUM_KERNELS)-1:0] buffer_data_vector,

  output reg [`FFN_IN_BITWIDTH:0] data_out
);

always@(*) begin
  if (reset == 1'b0) begin 
    data_out = `FFN_IN_WIDTH'd0;
  end else begin
    case(ram_select)
      8'd0: data_out = buffer_data_vector[23:0];
      8'd1: data_out = buffer_data_vector[47:24];
      8'd2: data_out = buffer_data_vector[71:48];
      8'd3: data_out = buffer_data_vector[95:72];
      8'd4: data_out = buffer_data_vector[119:96];
      8'd5: data_out = buffer_data_vector[143:120];
      8'd6: data_out = buffer_data_vector[167:144];
      8'd7: data_out = buffer_data_vector[191:168];
    endcase
  end //reset
end //always
endmodule
module feature_map_buffer_ctrl(
  input clock,
  input reset,
  input data_rdy,
  
  input [`X_COORD_BITWIDTH:0] xcoord,
  input [`Y_COORD_BITWIDTH:0] ycoord, 

  output reg [`FM_ADDR_BITWIDTH:0] addr,
  output reg buffer_full
);


//assign addr = xcoord + (ycoord * `FM_ADDR_WIDTH'd`FM_WIDTH);
always@(posedge clock or negedge reset) begin
  if(reset == 1'b0) 
    addr <= `FM_ADDR_WIDTH'd0;
  else if (data_rdy)
    if(xcoord[0]&ycoord[0])
	   addr <= addr + `FM_ADDR_WIDTH'd1;
	 else 
	   addr <= addr;
  else
    addr <= `FM_ADDR_WIDTH'd0;
end // always

//// incriment address
//always@(*/*posedge clock or negedge reset*/) begin
//  if(reset == 1'b0) begin
//    addr <= `FM_ADDR_WIDTH'd0;
//  end else begin
//    if(data_rdy) begin
//      // addr <= addr + `FM_ADDR_WIDTH'd0;
//      addr <= xcoord + (ycoord * `FM_ADDR_WIDTH'd`FM_WIDTH);
//    end else begin
//      // reset addres
//      addr <= `FM_ADDR_WIDTH'd0;
//    end // rdy
//  end // reset
//end // always


// set buffer full signal
always@(posedge clock or negedge reset) begin
  if (reset == 1'b0) begin
    buffer_full <= 1'b0;
  end else begin
									// - 1 to adjust for 0 index
    if (addr == `ADDR_MAX - 1) begin
      buffer_full <= 1'b1;
    end else begin
      buffer_full <= 1'b0;
    end // addr == max
  end // reset
end // always

endmodule
module rect_linear(
  input clock,
  input reset,
  input [`RECT_IN_BITWIDTH:0] rect_in, 
  output reg [`RECT_OUT_BITWIDTH:0] rect_out
		   );
   
   always@(posedge clock or negedge reset)begin
      if (reset == 1'b0) begin
	 rect_out <= `RECT_OUT_WIDTH'd0;
      end else begin
	 if (rect_in[`RECT_IN_BITWIDTH]) begin
	    rect_out <= `RECT_OUT_WIDTH'd0; 
	 end else begin
	    rect_out <= rect_in;
	 end
      end
   end
   
endmodule
module pixel_normalization(
  input norm_type,
  input gray_scale,
  input unsigned [`CAMERA_PIXEL_BITWIDTH:0] pixel_in,
  output reg [`CAMERA_PIXEL_BITWIDTH:0] pixel_out,
  output reg [`CAMERA_PIXEL_BITWIDTH:0] screen_pixel
);

//assign screen_pixel = pixel_out + 9'b100000000;
// assign pixel_out = pixel_in + {1'b1, `CAMERA_PIXEL_BITWIDTH'd0};
always@(*) begin
  if(norm_type)
    //   pixel_out = pixel_in + {1'b1, `CAMERA_PIXEL_BITWIDTH'd0};
    pixel_out = (pixel_in <= 9'b011111111) ? 9'b011111111 : 9'b100000000;
  else
    pixel_out = (pixel_in > 9'b011111111) ? 9'b011111111 : 9'b100000000;
end

always@(*) begin
  if(gray_scale)
    screen_pixel = pixel_in;
  else if(norm_type)
    //   pixel_out = pixel_in + {1'b1, `CAMERA_PIXEL_BITWIDTH'd0};
    screen_pixel = (pixel_in <= 9'b011111111) ? 9'b111111111 : 9'b000000000;
  else
    screen_pixel = (pixel_in > 9'b011111111) ? 9'b111111111 : 9'b000000000;
end
endmodule