dakies/OSS_Verilog huggingface dataset:
module lab5
(
	input        MAX10_CLK1_50,
    input  [1:0] KEY,
    input  [9:0] SW,
    output [9:0] LEDR
);
    parameter WIDTH = 4;//WIDTH should be no more than 9

    wire [WIDTH - 1:0] x_bus, y_bus, z_bus;   
    wire carry_in_wire, carry_out_wire;
    
    assign reset = KEY[1];
    assign clock = MAX10_CLK1_50;

    //argument selector
    assign load_x =  SW[9] & ~KEY[0] ? 1'b1 : 1'b0;
    assign load_y = ~SW[9] & ~KEY[0] ? 1'b1 : 1'b0;
    
    //x synchronization
    register #(.WIDTH(WIDTH)) x_register
    (
        .clock   (clock      ),
        .reset   (reset      ),
        .load    (load_x     ),
        .data_in (SW[WIDTH:1]),
        .data_out(x_bus      )
    );
    
    //y synchronization
    register #(.WIDTH(WIDTH)) y_register
    (
        .clock   (clock      ),
        .reset   (reset      ),
        .load    (load_y     ),
        .data_in (SW[WIDTH:1]),
        .data_out(y_bus      )
    );
    
    //carry in synchronization
    unit_delay #(.WIDTH(1)) carry_in_register
    (
        .clock   (clock        ),
        .data_in (SW[ 0 ]      ),
        .data_out(carry_in_wire)
    );
    
    //adder
    carry_lookahead_adder #(.WIDTH(WIDTH)) i_CLA
    (
        .carry_in (carry_in_wire ),
        .x        (x_bus         ),
        .y        (y_bus         ),
        .z        (z_bus         ),
        .carry_out(carry_out_wire)
    );
    
    //adder result synchronization
    unit_delay #(.WIDTH(WIDTH)) z_register
    (
        .clock   (clock    ),
        .data_in (z_bus    ),
        .data_out(LEDR[WIDTH - 1:0])
    );
    
    //carry out synchronization
    unit_delay #(.WIDTH(1)) carry_out_register
    (
        .clock   (clock         ),
        .data_in (carry_out_wire),
        .data_out(LEDR[9]       )
    ); 
        
    assign LEDR[8] = 0;
    
endmodule
module lab5
(
	 input  [9:0] SW,
    output [9:0] LEDR
);

    //left shifter
    left_shifter #(.WIDTH(4)) i_left_shifter
    (
        .x    (SW  [3:0]),
        .shamt(SW  [9:8]),
        .z    (LEDR[3:0])
    );

    //right shifter
    right_shifter #(.WIDTH(4)) i_right_shifter
    (
        .x    (SW  [7:4]),
        .shamt(SW  [9:8]),
        .z    (LEDR[9:6])
    );
    
    assign LEDR[5:4] = 0;
endmodule
module lab5
(
	input        MAX10_CLK1_50,
    input  [1:0] KEY,
    input  [9:0] SW,
    output [9:0] LEDR
);
    parameter GROUP_WIDTH = 4;
    parameter GROUP_COUNT = 2;
    parameter WIDTH = GROUP_COUNT * GROUP_WIDTH;
    //GROUP_WIDTH * GROUP_COUNT should be no more than 8

    wire [WIDTH - 1:0] x_bus, y_bus, z_bus;   
    wire carry_in_wire, carry_out_wire;
    
    assign reset = KEY[1];
    assign clock = MAX10_CLK1_50;

    //argument selector
    assign load_x =  SW[9] & ~KEY[0] ? 1'b1 : 1'b0;
    assign load_y = ~SW[9] & ~KEY[0] ? 1'b1 : 1'b0;
    
    //x synchronization
    register #(.WIDTH(WIDTH)) x_register
    (
        .clock   (clock      ),
        .reset   (reset      ),
        .load    (load_x     ),
        .data_in (SW[WIDTH:1]),
        .data_out(x_bus      )
    );
    
    //y synchronization
    register #(.WIDTH(WIDTH)) y_register
    (
        .clock   (clock      ),
        .reset   (reset      ),
        .load    (load_y     ),
        .data_in (SW[WIDTH:1]),
        .data_out(y_bus      )
    );
    
    //carry in synchronization
    unit_delay #(.WIDTH(1)) carry_in_register
    (
        .clock   (clock        ),
        .data_in (SW[ 0 ]      ),
        .data_out(carry_in_wire)
    );
    
    //adder
    ripple_block_CLA
    #(
        .GROUP_WIDTH(GROUP_WIDTH),
        .GROUP_COUNT(GROUP_COUNT)
    )
    i_RCA
    (
        .carry_in (carry_in_wire ),
        .x        (x_bus         ),
        .y        (y_bus         ),
        .z        (z_bus         ),
        .carry_out(carry_out_wire)
    );
    
    //adder result synchronization
    unit_delay #(.WIDTH(WIDTH)) z_register
    (
        .clock   (clock    ),
        .data_in (z_bus    ),
        .data_out(LEDR[WIDTH - 1:0])
    );
    
    //carry out synchronization
    unit_delay #(.WIDTH(1)) carry_out_register
    (
        .clock   (clock         ),
        .data_in (carry_out_wire),
        .data_out(LEDR[9]       )
    ); 
        
    assign LEDR[8] = 0;
    
endmodule
module lab5
(
	input        MAX10_CLK1_50,
    input  [1:0] KEY,
    input  [9:0] SW,
    output [9:0] LEDR
);
    parameter WIDTH = 4;//WIDTH should be no more than 9

    wire [WIDTH - 1:0] x_bus, y_bus, z_bus;   
    wire carry_in_wire, carry_out_wire;
    
    assign reset = KEY[1];
    assign clock = MAX10_CLK1_50;

    //argument selector
    assign load_x =  SW[9] & ~KEY[0] ? 1'b1 : 1'b0;
    assign load_y = ~SW[9] & ~KEY[0] ? 1'b1 : 1'b0;
    
    //x synchronization
    register #(.WIDTH(WIDTH)) x_register
    (
        .clock   (clock      ),
        .reset   (reset      ),
        .load    (load_x     ),
        .data_in (SW[WIDTH:1]),
        .data_out(x_bus      )
    );
    
    //y synchronization
    register #(.WIDTH(WIDTH)) y_register
    (
        .clock   (clock      ),
        .reset   (reset      ),
        .load    (load_y     ),
        .data_in (SW[WIDTH:1]),
        .data_out(y_bus      )
    );
    
    //carry in synchronization
    unit_delay #(.WIDTH(1)) carry_in_register
    (
        .clock   (clock        ),
        .data_in (SW[ 0 ]      ),
        .data_out(carry_in_wire)
    );
    
    //adder
    ripple_carry_adder #(.WIDTH(WIDTH)) i_RCA
    (
        .carry_in (carry_in_wire ),
        .x        (x_bus         ),
        .y        (y_bus         ),
        .z        (z_bus         ),
        .carry_out(carry_out_wire)
    );
    
    //adder result synchronization
    unit_delay #(.WIDTH(WIDTH)) z_register
    (
        .clock   (clock    ),
        .data_in (z_bus    ),
        .data_out(LEDR[WIDTH - 1:0])
    );
    
    //carry out synchronization
    unit_delay #(.WIDTH(1)) carry_out_register
    (
        .clock   (clock         ),
        .data_in (carry_out_wire),
        .data_out(LEDR[9]       )
    ); 
        
    assign LEDR[8] = 0;
    
endmodule
module lab5
(
	 input           MAX10_CLK1_50,
    input   [ 1:0]  KEY,
    input   [ 9:0]  SW,
    output  [ 9:0]  LEDR
);

    wire [7:0] x_bus, y_bus, z_bus;   
    wire carry_in_wire, carry_out_wire;
    
    assign reset = KEY[1];
    assign clock = MAX10_CLK1_50;

    //argument selector
    assign load_x =  SW[9] & ~KEY[0] ? 1'b1 : 1'b0;
    assign load_y = ~SW[9] & ~KEY[0] ? 1'b1 : 1'b0;
    
    //x synchronization
    register 
    # ( .WIDTH(8) )
    x_register (
        .clock   ( clock   ),
        .reset   ( reset   ),
        .load    ( load_x  ),
        .data_in ( SW[8:1] ),
        .data_out( x_bus   )
    );
    
    //y synchronization
    register 
    # ( .WIDTH(8) )
    y_register (
        .clock   ( clock   ),
        .reset   ( reset   ),
        .load    ( load_y  ),
        .data_in ( SW[8:1] ),
        .data_out( y_bus   )
    );
    
    //carry in synchronization
    unit_delay
    # ( .WIDTH( 1 ) )
    carry_in_register (
        .clock   ( clock         ),
        .data_in ( SW[ 0 ]       ),
        .data_out( carry_in_wire )
    );
    
    //adder
    prefix_adder
    #( .LEVELS(3), .WIDTH(8) )
    PA_dut
    (
        .carry_in ( carry_in_wire  ),
        .x        ( x_bus          ),
        .y        ( y_bus          ),
        .z        ( z_bus          ),
        .carry_out( carry_out_wire )
    );
    
    //adder result synchronization
    unit_delay
    # ( .WIDTH( 8 ) )
    z_register (
        .clock   ( clock     ),
        .data_in ( z_bus     ),
        .data_out( LEDR[7:0] )
    );
    
    //carry out synchronization
    unit_delay
    # ( .WIDTH( 1 ) )
    carry_out_register (
        .clock   ( clock          ),
        .data_in ( carry_out_wire ),
        .data_out( LEDR[9]        )
    ); 
        
    assign LEDR[8] = 0;
    
endmodule
module lab5
(
    input        MAX10_CLK1_50,
	input  [1:0] KEY,
    input  [9:0] SW,
    output [9:0] LEDR
);
    //wires
    wire [3:0] x_bus, y_bus;
    wire       load_x, load_y;
    wire       clock;
    wire       reset;
    
    assign clock = MAX10_CLK1_50;
    assign reset = KEY[1];
    
    //register for the arguments
    register #(.WIDTH(4)) x_register
    (
        .clock   (clock  ),
        .reset   (reset  ),
        .load    (load_x ),
        .data_in (SW[4:1]),
        .data_out(x_bus  )
    );

    register #(.WIDTH(4)) y_register
    (
        .clock   (clock  ),
        .reset   (reset  ),
        .load    (load_y ),
        .data_in (SW[4:1]),
        .data_out(y_bus  )
    );
    
    //argument selector
    assign load_x =  SW[0] & ~KEY[0] ? 1'b1 : 1'b0;
    assign load_y = ~SW[0] & ~KEY[0] ? 1'b1 : 1'b0;

    //alu
    alu
    #(
        .WIDTH(4),
        .SHIFT(2)
    )
    i_alu
    (
        .x        ( x_bus     ),
        .y        ( y_bus     ),
        .shamt    ( SW[6:5]   ),
        .operation( SW[9:8]   ),
        .zero     ( LEDR[9]   ),
        .result   ( LEDR[3:0] )
);
    
    assign LEDR[8:4] = 0;
    
endmodule
module lab5
(
    input  [9:0] SW,
    output [9:0] LEDR
);

    //left rotator
    left_rotator #(.WIDTH(4)) i_left_rotator
    (
        .x    (SW  [3:0]),
        .shamt(SW  [9:8]),
        .z    (LEDR[3:0])
    );

    //right rotator
    right_rotator #(.WIDTH(4)) i_right_rotator
    (
        .x    (SW  [7:4]),
        .shamt(SW  [9:8]),
        .z    (LEDR[9:6])
    );
    
    assign LEDR[5:4] = 0;
endmodule
module lab5
(
	input        MAX10_CLK1_50,
    input  [1:0] KEY,
    input  [9:0] SW,
    output [9:0] LEDR
);
    parameter GROUP_0_WIDTH = 2;
    parameter GROUP_1_WIDTH = 2;
    parameter GROUP_COUNT = 2;
    parameter WIDTH = GROUP_0_WIDTH * GROUP_1_WIDTH * GROUP_COUNT;
    //WIDTH should be no more than 8

    wire [WIDTH - 1:0] x_bus, y_bus, z_bus;   
    wire carry_in_wire, carry_out_wire;
    
    assign reset = KEY[1];
    assign clock = MAX10_CLK1_50;

    //argument selector
    assign load_x =  SW[9] & ~KEY[0] ? 1'b1 : 1'b0;
    assign load_y = ~SW[9] & ~KEY[0] ? 1'b1 : 1'b0;
    
    //x synchronization
    register #(.WIDTH(WIDTH)) x_register
    (
        .clock   (clock      ),
        .reset   (reset      ),
        .load    (load_x     ),
        .data_in (SW[WIDTH:1]),
        .data_out(x_bus      )
    );
    
    //y synchronization
    register #(.WIDTH(WIDTH)) y_register
    (
        .clock   (clock      ),
        .reset   (reset      ),
        .load    (load_y     ),
        .data_in (SW[WIDTH:1]),
        .data_out(y_bus      )
    );
    
    //carry in synchronization
    unit_delay #(.WIDTH(1)) carry_in_register
    (
        .clock   (clock        ),
        .data_in (SW[ 0 ]      ),
        .data_out(carry_in_wire)
    );
    
    //adder
    two_level_CLA
    #(
        .WIDTH_0    (GROUP_0_WIDTH),
        .WIDTH_1    (GROUP_1_WIDTH),
        .GROUP_COUNT(GROUP_COUNT  )
    )
    i_CLA
    (
        .carry_in (carry_in_wire ),
        .x        (x_bus         ),
        .y        (y_bus         ),
        .z        (z_bus         ),
        .carry_out(carry_out_wire)
    );
    
    //adder result synchronization
    unit_delay #(.WIDTH(WIDTH)) z_register
    (
        .clock   (clock    ),
        .data_in (z_bus    ),
        .data_out(LEDR[WIDTH - 1:0])
    );
    
    //carry out synchronization
    unit_delay #(.WIDTH(1)) carry_out_register
    (
        .clock   (clock         ),
        .data_in (carry_out_wire),
        .data_out(LEDR[9]       )
    ); 
        
    assign LEDR[8] = 0;
    
endmodule
module lab5
(
	input  [1:0] KEY,
    input  [9:0] SW,
    output [9:0] LEDR
);

    //comparator
    comparator #(.WIDTH(4)) i_comparator
    (
        .x  (SW [3:0]),
        .y  (SW [7:4]),
        .eq (LEDR[0]  ),
        .neq(LEDR[1]  ),
        .lt (LEDR[2]  ),
        .lte(LEDR[3]  ),
        .gt (LEDR[4]  ),
        .gte(LEDR[5]  )
    );
    
    assign LEDR[9:6] = 0;
    
endmodule
module lab5
(
    input  [9:0] SW,
    output [9:0] LEDR
);

	full_adder i_full_adder_behavioral
    (
        .carry_in (SW[0]  ),
        .x        (SW[1]  ),
        .y        (SW[2]  ),
        .z        (LEDR[0]),
        .carry_out(LEDR[1])
    );
    
    full_adder_structural i_full_adder_structural
    (
        .carry_in (SW[3] ),
        .x        (SW[4]  ),
        .y        (SW[5]  ),
        .z        (LEDR[3]),
        .carry_out(LEDR[4])
    );
    
    assign LEDR[2]   = 0;
    assign LEDR[9:5] = 0;

endmodule
module lab5
(
    input  [9:0] SW,
    output [9:0] LEDR
);
    //WIDTH	no greater than 4
    parameter WIDTH = 2;
    
	 //adder
    adder #(.WIDTH(WIDTH)) i_adder
    (
        .carry_in (SW [0]                  ),
        .x        (SW [WIDTH:1]            ),
        .y        (SW [2 * WIDTH:WIDTH + 1]),
        .z        (LEDR[2 * WIDTH - 1:0]   ),
        .carry_out(LEDR[9]                 )
    );
    
    assign LEDR[8:2 * WIDTH] = 0;
    
endmodule
module lab5
(
    input        MAX10_CLK1_50,
	input  [1:0] KEY,
    input  [9:0] SW,
    output [9:0] LEDR
);
    //wires
    wire [3:0] x_bus, y_bus;
    wire       load_x, load_y;
    wire       clock;
    wire       reset;
    
    assign clock = MAX10_CLK1_50;
    assign reset = KEY[1];
    
    //register for the arguments
    register #(.WIDTH(4)) x_register
    (
        .clock   (clock  ),
        .reset   (reset  ),
        .load    (load_x ),
        .data_in (SW[4:1]),
        .data_out(x_bus  )
    );

    register #(.WIDTH(4)) y_register
    (
        .clock   (clock  ),
        .reset   (reset  ),
        .load    (load_y ),
        .data_in (SW[4:1]),
        .data_out(y_bus  )
    );
    
    //argument selector
    assign load_x =  SW[0] & ~KEY[0] ? 1'b1 : 1'b0;
    assign load_y = ~SW[0] & ~KEY[0] ? 1'b1 : 1'b0;

    //alu
    alu_structural
    #(
        .WIDTH(4),
        .SHIFT(2)
    )
    i_alu
    (
        .x        ( x_bus     ),
        .y        ( y_bus     ),
        .shamt    ( SW[6:5]   ),
        .operation( SW[9:8]   ),
        .carry_in ( 0         ),
        .overflow ( LEDR[8]   ),
        .zero     ( LEDR[9]   ),
        .result   ( LEDR[3:0] )
);
    
    assign LEDR[7:4] = 0;
    
endmodule
module lab5
(
	input        MAX10_CLK1_50,
    input  [1:0] KEY,
    input  [9:0] SW,
    output [9:0] LEDR
);
    parameter GROUP_COUNT = 2;
    parameter GROUP_WIDTH = 2;
    parameter WIDTH = GROUP_COUNT * GROUP_WIDTH;
    //WIDTH should be no more than 8

    wire [WIDTH - 1:0] x_bus, y_bus, z_bus;   
    wire carry_in_wire, carry_out_wire;
    
    assign reset = KEY[1];
    assign clock = MAX10_CLK1_50;

    //argument selector
    assign load_x =  SW[9] & ~KEY[0] ? 1'b1 : 1'b0;
    assign load_y = ~SW[9] & ~KEY[0] ? 1'b1 : 1'b0;
    
    //x synchronization
    register #(.WIDTH(WIDTH)) x_register
    (
        .clock   (clock      ),
        .reset   (reset      ),
        .load    (load_x     ),
        .data_in (SW[WIDTH:1]),
        .data_out(x_bus      )
    );
    
    //y synchronization
    register #(.WIDTH(WIDTH)) y_register
    (
        .clock   (clock      ),
        .reset   (reset      ),
        .load    (load_y     ),
        .data_in (SW[WIDTH:1]),
        .data_out(y_bus      )
    );
    
    //carry in synchronization
    unit_delay #(.WIDTH(1)) carry_in_register
    (
        .clock   (clock        ),
        .data_in (SW[ 0 ]      ),
        .data_out(carry_in_wire)
    );
    
    //adder
    group_ripple_carry_adder
    #(
        .BLOCK_COUNT(GROUP_COUNT),
        .WIDTH      (GROUP_WIDTH)
    )
    i_RCA
    (
        .carry_in (carry_in_wire ),
        .x        (x_bus         ),
        .y        (y_bus         ),
        .z        (z_bus         ),
        .carry_out(carry_out_wire)
    );
    
    //adder result synchronization
    unit_delay #(.WIDTH(WIDTH)) z_register
    (
        .clock   (clock    ),
        .data_in (z_bus    ),
        .data_out(LEDR[WIDTH - 1:0])
    );
    
    //carry out synchronization
    unit_delay #(.WIDTH(1)) carry_out_register
    (
        .clock   (clock         ),
        .data_in (carry_out_wire),
        .data_out(LEDR[9]       )
    ); 
        
    assign LEDR[8] = 0;
    
endmodule
module lab5
(
	input        MAX10_CLK1_50,
    input  [1:0] KEY,
    input  [9:0] SW,
    output [9:0] LEDR
);
    parameter WIDTH = 8;//WIDTH should be no more than 9

    wire [WIDTH - 1:0] x_bus, y_bus, z_bus;   
    wire carry_in_wire, carry_out_wire;
    
    assign reset = KEY[1];
    assign clock = MAX10_CLK1_50;

    //argument selector
    assign load_x =  SW[9] & ~KEY[0] ? 1'b1 : 1'b0;
    assign load_y = ~SW[9] & ~KEY[0] ? 1'b1 : 1'b0;
    
    //x synchronization
    register #(.WIDTH(WIDTH)) x_register
    (
        .clock   (clock      ),
        .reset   (reset      ),
        .load    (load_x     ),
        .data_in (SW[WIDTH:1]),
        .data_out(x_bus      )
    );
    
    //y synchronization
    register #(.WIDTH(WIDTH)) y_register
    (
        .clock   (clock      ),
        .reset   (reset      ),
        .load    (load_y     ),
        .data_in (SW[WIDTH:1]),
        .data_out(y_bus      )
    );
    
    //carry in synchronization
    unit_delay #(.WIDTH(1)) carry_in_register
    (
        .clock   (clock        ),
        .data_in (SW[ 0 ]      ),
        .data_out(carry_in_wire)
    );
    
    //adder
    carry_lookahead_adder #(.WIDTH(WIDTH)) i_CLA
    (
        .carry_in (carry_in_wire ),
        .x        (x_bus         ),
        .y        (y_bus         ),
        .z        (z_bus         ),
        .carry_out(carry_out_wire)
    );
    
    //adder result synchronization
    unit_delay #(.WIDTH(WIDTH)) z_register
    (
        .clock   (clock    ),
        .data_in (z_bus    ),
        .data_out(LEDR[WIDTH - 1:0])
    );
    
    //carry out synchronization
    unit_delay #(.WIDTH(1)) carry_out_register
    (
        .clock   (clock         ),
        .data_in (carry_out_wire),
        .data_out(LEDR[9]       )
    ); 
        
    assign LEDR[8] = 0;
    
endmodule
module lab5
(
    input        MAX10_CLK1_50,
	input  [1:0] KEY,
    input  [9:0] SW,
    output [9:0] LEDR
);
    parameter WIDTH = 4;
    
    //wires
    wire [WIDTH - 1:0] x_bus, y_bus, z_bus;
    wire               load_x, load_y;
    wire               carry_in_wire;
    wire               carry_out_wire;
    wire               clock;
    wire               reset;
    
    assign clock = MAX10_CLK1_50;
    assign reset = KEY[1];
    
    //register for the arguments
    register #(.WIDTH(WIDTH)) x_register
    (
        .clock   (clock  ),
        .reset   (reset  ),
        .load    (load_x ),
        .data_in (SW[WIDTH:1]),
        .data_out(x_bus  )
    );

    register #(.WIDTH(WIDTH)) y_register
    (
        .clock   (clock  ),
        .reset   (reset  ),
        .load    (load_y ),
        .data_in (SW[WIDTH:1]),
        .data_out(y_bus  )
    );
    
    //carry_in synchronization
    unit_delay #(.WIDTH(1)) carry_in_register (
        .clock   ( clock         ),
        .data_in ( SW[ 0 ]       ),
        .data_out( carry_in_wire )
    );
    
    //argument selector
    assign load_x =  SW[0] & ~KEY[0] ? 1'b1 : 1'b0;
    assign load_y = ~SW[0] & ~KEY[0] ? 1'b1 : 1'b0;

    //adder
    adder #(.WIDTH(WIDTH)) i_adder
    (
        .carry_in (carry_in_wire ),
        .x        (x_bus         ),
        .y        (y_bus         ),
        .z        (z_bus         ),
        .carry_out(carry_out_wire)
    );
    
    //output synchronization
    unit_delay #(.WIDTH(WIDTH)) z_register (
        .clock   (clock            ),
        .data_in (z_bus            ),
        .data_out(LEDR[WIDTH - 1:0])
    );
    
    unit_delay #(.WIDTH(1)) carry_out_register (
        .clock   (clock         ),
        .data_in (carry_out_wire),
        .data_out(LEDR[9]       )
    );
    
    assign LEDR[8:WIDTH] = 0;
    
endmodule
module lab5
(
    input  [9:0] SW,
    output [9:0] LEDR
);

	half_adder i_half_adder_behavioral
    (
        .x        (SW[0]  ),
        .y        (SW[1]  ),
        .z        (LEDR[0]),
        .carry_out(LEDR[1])
    );
    
    half_adder_structural i_half_adder_structural
    (
        .x        ( SW[2]  ),
        .y        ( SW[3]  ),
        .z        ( LEDR[2]),
        .carry_out( LEDR[3])
    );
    
    assign LEDR[9:4] = 0;

endmodule
module tb();

    reg CLOCK_50 = 0;               // DE-series 50 MHz clock
    reg [9:0] SW = 0;               // DE-series SW switches
    reg [3:0] KEY = 0;              // DE-series pushbutton keys
    wire [(8*6) -1:0] HEX;          // HEX displays (six ports)
    wire [9:0] LEDR;                // DE-series LEDs

    reg key_action = 0;
    reg [7:0] scan_code = 0;
    wire [2:0] ps2_lock_control;

    wire [7:0] VGA_X;               // "VGA" column
    wire [6:0] VGA_Y;               // "VGA" row
    wire [2:0] VGA_COLOR;           // "VGA pixel" colour (0-7)
    wire plot;                      // "Pixel" is drawn when this is pulsed
    wire [31:0] GPIO;               // DE-series GPIO port

    initial $sim_fpga(CLOCK_50, SW, KEY, LEDR, HEX, key_action, scan_code, 
                      ps2_lock_control, VGA_X, VGA_Y, VGA_COLOR, plot, GPIO);

   
    // create the 50 MHz clock signal
    always #10
        CLOCK_50 <= ~CLOCK_50;

    
    top DUT (.CLOCK_50(CLOCK_50), .KEY(KEY), .SW(SW), .LEDR(LEDR));

endmodule
module top (CLOCK_50, KEY, SW, LEDR);

    input CLOCK_50;             // DE-series 50 MHz clock signal
	 input wire [3:0] KEY;       // DE-series pushbuttons
    input wire [9:0] SW;        // DE-series switches
    
    output wire [9:0] LEDR;     // DE-series LEDs   

    lab5 lab5 (CLOCK_50, KEY[1:0], SW[9:0], LEDR[9:0]);

endmodule
module register
# (
    parameter WIDTH = 8
)
(
    input                      clock,
    input                      reset,
    input                      load,
    input 	   [ WIDTH - 1:0 ] data_in,
    output reg [ WIDTH - 1:0 ] data_out
);

	always @ ( posedge clock, negedge reset )
		if ( ~reset )
            data_out <= { WIDTH { 1'b0 } };
        else if ( load )
            data_out <= data_in;
endmodule
module carry_lookahead_generator
# (
    parameter WIDTH = 8
)
(
    input                  carry_in,
    input  [WIDTH - 1 : 0] generate_in, propagate_in,
    output [WIDTH     : 1] carry,
    output                 group_generate, group_propagate
);
    
    //Temporary wires for the carry calculation
    wire [((WIDTH + 1) * WIDTH) / 2 - 1 : 0] p_temp, g_temp;
    wire [WIDTH - 1 : 0] c_temp, pg_temp;
    
    generate
        
        genvar i, j;
        
        for (i = 0; i <= WIDTH - 1; i = i + 1)
        begin : stage
            //Calculate carry            
            for (j = 0; j <= i; j = j + 1)
            begin : block 
                assign p_temp[((i + 1) * i) / 2 + j] = & propagate_in[i : j];
                case(j)
                	0       : assign g_temp[((i + 1) * i) / 2 + j] = generate_in[i];
                	default : assign g_temp[((i + 1) * i) / 2 + j] = p_temp[((i + 1) * i) / 2 + j] & generate_in[j - 1];
                endcase
                end
                
            assign c_temp [i] = p_temp[((i + 1) * i) / 2] & carry_in;
            assign pg_temp[i] = | g_temp[(( i + 2) * (i + 1)) / 2 - 1 : ((i + 1) * i) / 2]; 
            
            assign carry [i + 1] = pg_temp[i] | c_temp[i];

        end
    endgenerate
    
    assign group_propagate = p_temp [(WIDTH * (WIDTH - 1)) / 2];
    assign group_generate  = pg_temp[WIDTH - 1];
    
endmodule
module carry_lookahead_adder
# (
    parameter WIDTH = 8
)
(
    input                  carry_in,
    input  [WIDTH - 1 : 0] x,
    input  [WIDTH - 1 : 0] y,
    output [WIDTH - 1 : 0] z,
    output                 carry_out,
    output                 group_generate,
    output                 group_propagate
);
    wire [WIDTH : 0] carry;
    wire [WIDTH - 1 : 0] generate_wire, propagate_wire; 
    
    assign carry[0] = carry_in; 
    
    carry_lookahead_generator #(.WIDTH(WIDTH)) i_CLG
    (
        .carry_in       (carry_in        ),
        .generate_in    (generate_wire   ),
        .propagate_in   (propagate_wire  ),
        .carry          (carry[WIDTH : 1]),
        .group_generate (group_generate  ),
        .group_propagate(group_propagate )        
    );
    
    generate
        
        genvar i;
        
        for (i = 0; i <= WIDTH - 1; i = i + 1)
        begin : stage
            //Create generate and propagate signals
            assign generate_wire [i] = x[i] & y[i];
            assign propagate_wire[i] = x[i] ^ y[i];
            //Calculate sum (z bus)
            assign z[i] = carry[i] ^ propagate_wire[i];
        end
    endgenerate
    
    assign carry_out = carry[WIDTH];

endmodule
module unit_delay
# (
    parameter WIDTH = 1
) 
(
    input                      clock,
    input      [ WIDTH - 1:0 ] data_in,
    output reg [ WIDTH - 1:0 ] data_out
);

    always @ (posedge clock)
        data_out <= data_in;

endmodule
module testbench;
   // input and output test signals
   reg  c_in;
   reg  [ 7:0 ] x, y;
   wire [ 7:0 ] z;
   wire c_out;
 
   // create the instances of the modules you want to test
    carry_lookahead_adder #( .WIDTH(8) ) CLA_dut(
        .carry_in ( c_in  ),
        .x        ( x     ),
        .y        ( y     ),
        .z        ( z     ),
        .carry_out( c_out )
    );
        
    //write test sequence
    initial begin
        x    = 8'b00000000;
        y    = 8'b00000000;
        c_in = 1'b0;
        #8
        $stop;
    end
    
    initial
        forever begin
            #1;
            x = $urandom_range( 0, 255 );
            y = $urandom_range( 0, 255 );
            
            c_in = $urandom_range( 0 ,1 );
        end
            
    // do at the beginning of the simulation
    //  print signal values on every change
    initial 
        $monitor("Time:\t%g, x: %b, y: %b, c_in %b, z: %b, c_out: %b",
                $time,
                x,
                y,
                c_in,
                z,
                c_out
            );
            
    // do at the beginning of the simulation
    //configure signals dump for waveform's creation
    initial begin 
        $dumpfile("dump.vcd");
        $dumpvars(1);  //iverilog dump init
    end
    
endmodule
module tb();

    reg CLOCK_50 = 0;               // DE-series 50 MHz clock
    reg [9:0] SW = 0;               // DE-series SW switches
    reg [3:0] KEY = 0;              // DE-series pushbutton keys
    wire [(8*6) -1:0] HEX;          // HEX displays (six ports)
    wire [9:0] LEDR;                // DE-series LEDs

    reg key_action = 0;
    reg [7:0] scan_code = 0;
    wire [2:0] ps2_lock_control;

    wire [7:0] VGA_X;               // "VGA" column
    wire [6:0] VGA_Y;               // "VGA" row
    wire [2:0] VGA_COLOR;           // "VGA pixel" colour (0-7)
    wire plot;                      // "Pixel" is drawn when this is pulsed
    wire [31:0] GPIO;               // DE-series GPIO port

    initial $sim_fpga(CLOCK_50, SW, KEY, LEDR, HEX, key_action, scan_code, 
                      ps2_lock_control, VGA_X, VGA_Y, VGA_COLOR, plot, GPIO);

   
    // create the 50 MHz clock signal
    always #10
        CLOCK_50 <= ~CLOCK_50;

    
    top DUT (.SW(SW), .LEDR(LEDR));

endmodule
module top (SW, LEDR);

    input wire [9:0] SW;        // DE-series switches
 
    output wire [9:0] LEDR;     // DE-series LEDs   

    lab5 lab5 (SW[9:0], LEDR[9:0]);

endmodule
module right_shifter
#( 
    parameter WIDTH = 8,
    parameter SHIFT = 3 //SHIFT specifies the number of bits for shamt argument
)
(
    input  [WIDTH - 1:0] x,
    input  [SHIFT - 1:0] shamt,
    output [WIDTH - 1:0] z
);
    assign z = x >> shamt;
endmodule
module left_shifter
#( 
    parameter WIDTH = 8,
    parameter SHIFT = 3 //SHIFT specifies the number of bits for shamt argument
)
(
    input  [WIDTH - 1:0] x,
    input  [SHIFT - 1:0] shamt,
    output [WIDTH - 1:0] z
);
    assign z = x << shamt;
endmodule
module testbench;
    parameter WIDTH = 8;
    parameter SHIFT = 3;
    // input and output test signals
    reg  [WIDTH - 1:0] x;
    reg  [SHIFT - 1:0] shamt;
    wire [WIDTH - 1:0] ls_out;
    wire [WIDTH - 1:0] rs_out;
 
    // create the instances of the modules you want to test
    left_shifter
    #(
        .WIDTH(WIDTH),
        .SHIFT(SHIFT)
    )
    left_shifter_dut
    (
        .x    (x     ),
        .shamt(shamt ),
        .z    (ls_out)
    );
    
    right_shifter
    #(
        .WIDTH(WIDTH),
        .SHIFT(SHIFT)
    )
    right_shifter_dut
    (
        .x    (x     ),
        .shamt(shamt ),
        .z    (rs_out)
    );
    
    //write test sequence
    initial begin
        x     = 0;
        shamt = 0;
        #8
        $stop;
    end
    
    initial
        forever begin
            #1;
            x     = $urandom_range(0, 2 ** WIDTH - 1);
            shamt = $urandom_range(0, 2 ** SHIFT - 1);
        end
            
    // do at the beginning of the simulation
    //  print signal values on every change
    initial 
        $monitor("Time:\t%g, x: %b, shamt: %b, ls_out: %b, rs_out: %b",
                $time,
                x,
                shamt,
                ls_out,
                rs_out
            );
            
    // do at the beginning of the simulation
    //configure signals dump for waveform's creation
    initial begin 
        $dumpfile("dump.vcd");
        $dumpvars(1);  //iverilog dump init
    end
    
endmodule
module ripple_block_CLA
# (
    parameter GROUP_WIDTH = 4,
    parameter GROUP_COUNT = 2
)
(
    input                                      carry_in,
    input  [GROUP_COUNT * GROUP_WIDTH - 1 : 0] x,
    input  [GROUP_COUNT * GROUP_WIDTH - 1 : 0] y,
    output [GROUP_COUNT * GROUP_WIDTH - 1 : 0] z,
    output                                     carry_out
);
    wire [GROUP_COUNT : 0] carry;
    
    assign carry[0] = carry_in;
        
    generate
        
        genvar i;
        
        for (i = 0; i <= GROUP_COUNT - 1; i = i + 1)
        begin : stage
            carry_lookahead_adder #(.WIDTH(GROUP_WIDTH)) i_CLA
            (
                .carry_in (carry[i]                                      ),
                .x        (x[(i + 1) * GROUP_WIDTH - 1 : i * GROUP_WIDTH]),
                .y        (y[(i + 1) * GROUP_WIDTH - 1 : i * GROUP_WIDTH]),
                .z        (z[(i + 1) * GROUP_WIDTH - 1 : i * GROUP_WIDTH]),
                .carry_out(carry[i + 1]                                  )        
            );
        end
    endgenerate
    
    assign carry_out = carry[GROUP_COUNT];

endmodule
module testbench;
   // input and output test signals
   reg  c_in;
   reg  [ 7:0 ] x, y;
   wire [ 7:0 ] z;
   wire c_out;
 
   // create the instances of the modules you want to test
    ripple_block_CLA #( .GROUP_WIDTH(4), .GROUP_COUNT(2) ) CLA_dut(
        .carry_in ( c_in  ),
        .x        ( x     ),
        .y        ( y     ),
        .z        ( z     ),
        .carry_out( c_out )
    );
        
    //write test sequence
    initial begin
        x    = 8'b00000000;
        y    = 8'b00000000;
        c_in = 1'b0;
        #8
        $stop;
    end
    
    initial
        forever begin
            #1;
            x = $urandom_range( 0, 255 );
            y = $urandom_range( 0, 255 );
            
            c_in = $urandom_range( 0 ,1 );
        end
            
    // do at the beginning of the simulation
    //  print signal values on every change
    initial 
        $monitor("Time:\t%g, x: %b, y: %b, c_in %b, z: %b, c_out: %b",
                $time,
                x,
                y,
                c_in,
                z,
                c_out
            );
            
    // do at the beginning of the simulation
    //configure signals dump for waveform's creation
    initial begin 
        $dumpfile("dump.vcd");
        $dumpvars(1);  //iverilog dump init
    end
    
endmodule
module ripple_carry_adder
# (
    parameter WIDTH = 8
)
(
    input                  carry_in,
    input  [WIDTH - 1 : 0] x,
    input  [WIDTH - 1 : 0] y,
    output [WIDTH - 1 : 0] z,
    output                 carry_out
);
    wire [WIDTH : 0] carry;
    
    assign carry[0] = carry_in; 
    
    generate
    
        genvar i;
    
        for (i = 0; i <= WIDTH - 1; i = i + 1)
        begin : stage
            full_adder FA
            (
                .x		   (x    [i]    ),
                .y         (y    [i]    ),
                .z         (z    [i]    ),
                .carry_in  (carry[i]    ),
                .carry_out (carry[i + 1])
            );
        end
    endgenerate
    
    assign carry_out = carry[WIDTH];

endmodule
module full_adder
(
    input wire  x, y, carry_in,
	output wire z, carry_out
);
    assign {carry_out, z} = x + y + carry_in;
endmodule
module testbench;
   // input and output test signals
   reg  c_in;
   reg  [ 7:0 ] x, y;
   wire [ 7:0 ] z;
   wire c_out;
 
   // create the instances of the modules you want to test
    ripple_carry_adder #( .WIDTH(8) ) RCA_dut(
        .carry_in ( c_in  ),
        .x        ( x     ),
        .y        ( y     ),
        .z        ( z     ),
        .carry_out( c_out )
    );
        
    //write test sequence
    initial begin
        x    = 8'b00000000;
        y    = 8'b00000000;
        c_in = 1'b0;
        #8
        $stop;
    end
    
    initial
        forever begin
            #1;
            x = $urandom_range( 0, 255 );
            y = $urandom_range( 0, 255 );
            
            c_in = $urandom_range( 0 ,1 );
        end
            
    // do at the beginning of the simulation
    //  print signal values on every change
    initial 
        $monitor("Time:\t%g, x: %b, y: %b, c_in %b, z: %b, c_out: %b",
                $time,
                x,
                y,
                c_in,
                z,
                c_out
            );
            
    // do at the beginning of the simulation
    //configure signals dump for waveform's creation
    initial begin 
        $dumpfile("dump.vcd");
        $dumpvars(1);  //iverilog dump init
    end
    
endmodule
module gp_cell
(
    input  wire g_left, g_right, p_left, p_right,
    output wire g_out, p_out
);

    assign g_out = g_left | p_left & g_right;
    assign p_out = p_left & p_right;
    
endmodule
module prefix_adder
# (
    parameter LEVELS = 3,
    parameter WIDTH = 2 ** LEVELS
)
(
    input                      carry_in,
    input    [ WIDTH - 1 : 0 ] x,
    input    [ WIDTH - 1 : 0 ] y,
    output   [ WIDTH - 1 : 0 ] z,
    output                     carry_out
);
    wire [ WIDTH - 1 : 0 ] carry;
    
    wire [ WIDTH - 1 : 0 ] generate_wire, propagate_wire; 
    
    prefix_carry_generator
    # ( .LEVELS(LEVELS), .WIDTH(WIDTH) )
    i_PCG
    (
        .carry_in    ( carry_in       ),
        .generate_in ( generate_wire  ),
        .propagate_in( propagate_wire ),
        .carry       ( carry          ),
        .carry_out   ( carry_out      )
    );
    
    generate
        
        genvar i;
        
        for (i = 0; i <= WIDTH - 1; i = i + 1)
        begin : stage
            //Create generate and propagate signals
            assign generate_wire [ i ] = x[ i ] & y[ i ];
            assign propagate_wire[ i ] = x[ i ] ^ y[ i ];
            //Calculate sum (z bus)
            assign z[ i ] = carry[ i ] ^ propagate_wire[ i ];
        end
    endgenerate
    
endmodule
module prefix_carry_generator
# (
    parameter LEVELS = 3,
    parameter WIDTH  = 2 ** LEVELS
)
(
    input                      carry_in,
    input    [ WIDTH - 1 : 0 ] generate_in, propagate_in,
    output   [ WIDTH - 1 : 0 ] carry,
    output                     carry_out
);
    //Sklansky adder    
    wire [WIDTH : 0] g_temp [LEVELS : 0];
    wire [WIDTH : 0] p_temp [LEVELS : 0];
    
    assign g_temp[0] = {generate_in, carry_in};
    assign p_temp[0] = {propagate_in, carry_in};
    
    generate
        
        genvar i, j;
        
        for (i = 0; i <= LEVELS - 1; i = i + 1)
        begin : stage
            for (j = 0; j <= WIDTH; j = j + 1)
            begin : block
                if( (j / 2 ** i) % 2 == 1 )
                    gp_cell i_gp_cell
                    (
                        .g_left (g_temp[i][j]                        ),
                        .g_right(g_temp[i][(j / (2**i)) * (2**i) - 1]),
                        .p_left (p_temp[i][j]                        ),
                        .p_right(p_temp[i][(j / (2**i)) * (2**i) - 1]),
                        .g_out  (g_temp[i+1][j]                      ),
                        .p_out  (p_temp[i+1][j]                      )
                    );
                else
                begin
                    assign g_temp[i+1][j] = g_temp[i][j];
                    assign p_temp[i+1][j] = p_temp[i][j];
                end
            end
        end
    endgenerate
    
    assign carry = g_temp[LEVELS][WIDTH-1:0];
    assign carry_out = g_temp[LEVELS][WIDTH]|p_temp[LEVELS][WIDTH]&g_temp[LEVELS][WIDTH-1];
    

endmodule
module testbench;
   // input and output test signals
   reg  c_in;
   reg  [ 7:0 ] x, y;
   wire [ 7:0 ] z;
   wire c_out;
 
   // create the instances of the modules you want to test
    prefix_adder #( .LEVELS(3), .WIDTH(8) ) CLA_dut(
        .carry_in ( c_in  ),
        .x        ( x     ),
        .y        ( y     ),
        .z        ( z     ),
        .carry_out( c_out )
    );
        
    //write test sequence
    initial begin
        x    = 8'b00000000;
        y    = 8'b00000000;
        c_in = 1'b0;
        #8
        $stop;
    end
    
    initial
        forever begin
            #1;
            x = $urandom_range( 0, 255 );
            y = $urandom_range( 0, 255 );
            
            c_in = $urandom_range( 0 ,1 );
        end
            
    // do at the beginning of the simulation
    //  print signal values on every change
    initial 
        $monitor("Time:\t%g, x: %b, y: %b, c_in %b, z: %b, c_out: %b",
                $time,
                x,
                y,
                c_in,
                z,
                c_out
            );
            
    // do at the beginning of the simulation
    //configure signals dump for waveform's creation
    initial begin 
        $dumpfile("dump.vcd");
        $dumpvars(1);  //iverilog dump init
    end
    
endmodule
module alu
#(
    parameter WIDTH = 4,
    parameter SHIFT = 2
)
(
    input      [WIDTH - 1:0] x, y,
    input      [SHIFT - 1:0] shamt,
    input      [ 1:0]        operation,
    output                   zero,
    output reg [WIDTH - 1:0] result
);

    always @ (*) begin
        case (operation)
            `ALU_AND : result = x & y; 
            `ALU_ADD : result = x + y;
            `ALU_SLL : result = y << shamt;
            `ALU_SLT : result = (x < y) ? 1 : 0;
        endcase
    end

    //Flags
    assign zero      = (result == 0);

endmodule
module testbench;
    parameter WIDTH = 8;
    parameter SHIFT = 3;
    // input and output test signals
    reg  [WIDTH - 1:0] x, y;
    reg  [SHIFT - 1:0] shamt;
    reg  [1:0]         operation;
    wire [WIDTH - 1:0] result;
    wire               zero;
 
    // create the instances of the modules you want to test
    alu
    #(
        .WIDTH(WIDTH),
        .SHIFT(SHIFT)
    )
    alu_dut
    (
        .operation(operation),
        .x        (x        ),
        .y        (y        ),
        .shamt    (shamt    ),
        .result   (result   ),
        .zero     (zero     )
    );
       
    //write test sequence
    initial begin
        x         = 0;
        y         = 0;
        shamt     = 0;
        operation = 0;
        #8;
        $stop;
    end
    
    initial
        forever begin
            #1;
            x     = $urandom_range(0, 2 ** (WIDTH - 1) - 1);
            y     = $urandom_range(0, 2 ** (WIDTH - 1) - 1);
            shamt = $urandom_range(0, 2 ** SHIFT - 1);
            
        end
        
    initial
        forever begin
            #2;
            operation = operation + 1;
	end
            
            
    // do at the beginning of the simulation
    //  print signal values on every change
    initial 
        $monitor("Time:\t%g, operation: %b, x: %b, y: %b, shamt: %b, result: %b, z_f: %b",
                $time,
                operation,
                x,
                y,
                shamt,
                result,
                zero
            );
            
    // do at the beginning of the simulation
    //configure signals dump for waveform's creation
    initial begin 
        $dumpfile("dump.vcd");
        $dumpvars(1);  //iverilog dump init
    end
    
endmodule
module left_rotator
#( 
    parameter WIDTH = 8,
    parameter SHIFT = 3 //SHIFT specifies the number of bits for shamt argument
)
(
    input  [WIDTH - 1:0] x,
    input  [SHIFT - 1:0] shamt,
    output [WIDTH - 1:0] z
);

    wire [2 * WIDTH - 1:0] temp;
    assign temp = {x, x} << shamt;
    assign z = temp[2 * WIDTH - 1: WIDTH];
endmodule
module right_rotator
#( 
    parameter WIDTH = 8,
    parameter SHIFT = 3 //SHIFT specifies the number of bits for shamt argument
)
(
    input  [WIDTH - 1:0] x,
    input  [SHIFT - 1:0] shamt,
    output [WIDTH - 1:0] z
);

    wire [2 * WIDTH - 1:0] temp;
    assign temp = {x, x} >> shamt;
    assign z = temp[WIDTH - 1: 0];
endmodule
module testbench;
    parameter WIDTH = 8;
    parameter SHIFT = 3;
    // input and output test signals
    reg  [WIDTH - 1:0] x;
    reg  [SHIFT - 1:0] shamt;
    wire [WIDTH - 1:0] lr_out;
    wire [WIDTH - 1:0] rr_out;
 
    // create the instances of the modules you want to test
    left_rotator
    #(
        .WIDTH(WIDTH),
        .SHIFT(SHIFT)
    )
    left_rotator_dut
    (
        .x    (x     ),
        .shamt(shamt ),
        .z    (lr_out)
    );
    
    right_rotator
    #(
        .WIDTH(WIDTH),
        .SHIFT(SHIFT)
    )
    right_rotator_dut
    (
        .x    (x     ),
        .shamt(shamt ),
        .z    (rr_out)
    );
    
    //write test sequence
    initial begin
        x     = 0;
        shamt = 0;
        #8
        $stop;
    end
    
    initial
        forever begin
            #1;
            x     = $urandom_range(0, 2 ** WIDTH - 1);
            shamt = $urandom_range(0, 2 ** SHIFT - 1);
        end
            
    // do at the beginning of the simulation
    //  print signal values on every change
    initial 
        $monitor("Time:\t%g, x: %b, shamt: %b, lr_out: %b, rr_out: %b",
                $time,
                x,
                shamt,
                lr_out,
                rr_out
            );
            
    // do at the beginning of the simulation
    //configure signals dump for waveform's creation
    initial begin 
        $dumpfile("dump.vcd");
        $dumpvars(1);  //iverilog dump init
    end
    
endmodule
module two_level_CLA
# (
    parameter WIDTH_0 = 2,
    parameter WIDTH_1 = 2,
    parameter GROUP_COUNT = 2
)
(
    input                                             carry_in,
    input  [GROUP_COUNT * WIDTH_1 * WIDTH_0 - 1 : 0 ] x,
    input  [GROUP_COUNT * WIDTH_1 * WIDTH_0 - 1 : 0 ] y,
    output [GROUP_COUNT * WIDTH_1 * WIDTH_0 - 1 : 0 ] z,
    output                                            carry_out
);
    wire [GROUP_COUNT * WIDTH_1 - 1 : 0] p_temp, g_temp;
    wire [GROUP_COUNT * WIDTH_1 : 0]     c_temp;

    
    assign c_temp[0] = carry_in;
        
    generate
        
        genvar i;
        genvar j;
        
        for (i = 0; i <= GROUP_COUNT * WIDTH_1 - 1; i = i + 1)
        begin : stage
            carry_lookahead_adder #(.WIDTH(WIDTH_0)) i_CLA
            (
                .carry_in       (c_temp[i]                             ),
                .x              (x[(i + 1) * WIDTH_0 - 1 : i * WIDTH_0]),
                .y              (y[(i + 1) * WIDTH_0 - 1 : i * WIDTH_0]),
                .z              (z[(i + 1) * WIDTH_0 - 1 : i * WIDTH_0]),
                .group_propagate(p_temp[i]                             ),
                .group_generate (g_temp[i]                             ),
                .carry_out      ()
            );
        end
        
        for (j = 0; j <= GROUP_COUNT - 1; j = j + 1)
        begin : clg_stage
            carry_lookahead_generator #(.WIDTH(WIDTH_1)) i_CLG
            (
                .carry_in       (c_temp[WIDTH_1 * j]                        ),
                .generate_in    (g_temp[WIDTH_1 * (j + 1) - 1 : WIDTH_1 * j]),
                .propagate_in   (p_temp[WIDTH_1 * (j + 1) - 1 : WIDTH_1 * j]),
                .carry          (c_temp[WIDTH_1 * (j + 1) : WIDTH_1 * j + 1]),
                .group_propagate(),
                .group_generate ()        
            );
        end
    endgenerate
    
    assign carry_out = c_temp[GROUP_COUNT * WIDTH_1];

endmodule
module testbench;
   // input and output test signals
   reg  c_in;
   reg  [ 7:0 ] x, y;
   wire [ 7:0 ] z;
   wire c_out;
 
   // create the instances of the modules you want to test
    two_level_CLA
    #(
        .GROUP_0_WIDTH(2),
        .GROUP_1_WIDTH(2),
        .GROUP_COUNT(2)
    )
    CLA_dut
    (
        .carry_in ( c_in  ),
        .x        ( x     ),
        .y        ( y     ),
        .z        ( z     ),
        .carry_out( c_out )
    );
        
    //write test sequence
    initial begin
        x    = 8'b00000000;
        y    = 8'b00000000;
        c_in = 1'b0;
        #8
        $stop;
    end
    
    initial
        forever begin
            #1;
            x = $urandom_range( 0, 255 );
            y = $urandom_range( 0, 255 );
            
            c_in = $urandom_range( 0 ,1 );
        end
            
    // do at the beginning of the simulation
    //  print signal values on every change
    initial 
        $monitor("Time:\t%g, x: %b, y: %b, c_in %b, z: %b, c_out: %b",
                $time,
                x,
                y,
                c_in,
                z,
                c_out
            );
            
    // do at the beginning of the simulation
    //configure signals dump for waveform's creation
    initial begin 
        $dumpfile("dump.vcd");
        $dumpvars(1);  //iverilog dump init
    end
    
endmodule
module tb();

    reg CLOCK_50 = 0;               // DE-series 50 MHz clock
    reg [9:0] SW = 0;               // DE-series SW switches
    reg [3:0] KEY = 0;              // DE-series pushbutton keys
    wire [(8*6) -1:0] HEX;          // HEX displays (six ports)
    wire [9:0] LEDR;                // DE-series LEDs

    reg key_action = 0;
    reg [7:0] scan_code = 0;
    wire [2:0] ps2_lock_control;

    wire [7:0] VGA_X;               // "VGA" column
    wire [6:0] VGA_Y;               // "VGA" row
    wire [2:0] VGA_COLOR;           // "VGA pixel" colour (0-7)
    wire plot;                      // "Pixel" is drawn when this is pulsed
    wire [31:0] GPIO;               // DE-series GPIO port

    initial $sim_fpga(CLOCK_50, SW, KEY, LEDR, HEX, key_action, scan_code, 
                      ps2_lock_control, VGA_X, VGA_Y, VGA_COLOR, plot, GPIO);

   
    // create the 50 MHz clock signal
    always #10
        CLOCK_50 <= ~CLOCK_50;

    
    top DUT (.KEY(KEY), .SW(SW), .LEDR(LEDR));

endmodule
module top (KEY, SW, LEDR);

    input wire [3:0] KEY;       // DE-series pushbuttons
    input wire [9:0] SW;        // DE-series switches
    
    output wire [9:0] LEDR;     // DE-series LEDs   

    lab5 lab5 (KEY[1:0], SW[9:0], LEDR[9:0]);

endmodule
module comparator
#( 
    parameter WIDTH = 8
)
(
    input  [WIDTH - 1:0] x, y,    
    output eq, neq, lt, lte, gt, gte
);
    assign eq  = (x == y);
    assign neq = (x != y);
    assign lt  = (x <  y);
    assign lte = (x <= y);
    assign gt  = (x >  y);
    assign gte = (x >= y);
endmodule