dakies/OSS_Verilog huggingface dataset:
module Mux_0xdd6473406d1a99a
(
  input  wire [   0:0] clk,
  input  wire [  15:0] in_$000,
  input  wire [  15:0] in_$001,
  output reg  [  15:0] out,
  input  wire [   0:0] reset,
  input  wire [   0:0] sel
);

  // localparam declarations
  localparam nports = 2;


  // array declarations
  wire   [  15:0] in_[0:1];
  assign in_[  0] = in_$000;
  assign in_[  1] = in_$001;

  // PYMTL SOURCE:
  //
  // @s.combinational
  // def comb_logic():
  //       assert s.sel < nports
  //       s.out.v = s.in_[ s.sel ]

  // logic for comb_logic()
  always @ (*) begin
    out = in_[sel];
  end


endmodule
module RegEn_0x68db79c4ec1d6e5b
(
  input  wire [   0:0] clk,
  input  wire [   0:0] en,
  input  wire [  15:0] in_,
  output reg  [  15:0] out,
  input  wire [   0:0] reset
);



  // PYMTL SOURCE:
  //
  // @s.posedge_clk
  // def seq_logic():
  //       if s.en:
  //         s.out.next = s.in_

  // logic for seq_logic()
  always @ (posedge clk) begin
    if (en) begin
      out <= in_;
    end
    else begin
    end
  end


endmodule
module RegRst_0x9f365fdf6c8998a
(
  input  wire [   0:0] clk,
  input  wire [   1:0] in_,
  output reg  [   1:0] out,
  input  wire [   0:0] reset
);

  // localparam declarations
  localparam reset_value = 0;



  // PYMTL SOURCE:
  //
  // @s.posedge_clk
  // def seq_logic():
  //       if s.reset:
  //         s.out.next = reset_value
  //       else:
  //         s.out.next = s.in_

  // logic for seq_logic()
  always @ (posedge clk) begin
    if (reset) begin
      out <= reset_value;
    end
    else begin
      out <= in_;
    end
  end


endmodule
module ZeroComparator_0x422b1f52edd46a85
(
  input  wire [   0:0] clk,
  input  wire [  15:0] in_,
  output reg  [   0:0] out,
  input  wire [   0:0] reset
);



  // PYMTL SOURCE:
  //
  // @s.combinational
  // def comb_logic():
  //       s.out.value = s.in_ == 0

  // logic for comb_logic()
  always @ (*) begin
    out = (in_ == 0);
  end


endmodule
module LtComparator_0x422b1f52edd46a85
(
  input  wire [   0:0] clk,
  input  wire [  15:0] in0,
  input  wire [  15:0] in1,
  output reg  [   0:0] out,
  input  wire [   0:0] reset
);



  // PYMTL SOURCE:
  //
  // @s.combinational
  // def comb_logic():
  //       s.out.value = s.in0 < s.in1

  // logic for comb_logic()
  always @ (*) begin
    out = (in0 < in1);
  end


endmodule
module Mux_0x683fa1a418b072c9
(
  input  wire [   0:0] clk,
  input  wire [  15:0] in_$000,
  input  wire [  15:0] in_$001,
  input  wire [  15:0] in_$002,
  output reg  [  15:0] out,
  input  wire [   0:0] reset,
  input  wire [   1:0] sel
);

  // localparam declarations
  localparam nports = 3;


  // array declarations
  wire   [  15:0] in_[0:2];
  assign in_[  0] = in_$000;
  assign in_[  1] = in_$001;
  assign in_[  2] = in_$002;

  // PYMTL SOURCE:
  //
  // @s.combinational
  // def comb_logic():
  //       assert s.sel < nports
  //       s.out.v = s.in_[ s.sel ]

  // logic for comb_logic()
  always @ (*) begin
    out = in_[sel];
  end


endmodule
module IntXbar_4( // @[:freechips.rocketchip.system.TinyConfig.fir@102861.2]
  input   auto_int_in_2_0, // @[:freechips.rocketchip.system.TinyConfig.fir@102864.4]
  input   auto_int_in_1_0, // @[:freechips.rocketchip.system.TinyConfig.fir@102864.4]
  input   auto_int_in_1_1, // @[:freechips.rocketchip.system.TinyConfig.fir@102864.4]
  input   auto_int_in_0_0, // @[:freechips.rocketchip.system.TinyConfig.fir@102864.4]
  output  auto_int_out_0, // @[:freechips.rocketchip.system.TinyConfig.fir@102864.4]
  output  auto_int_out_1, // @[:freechips.rocketchip.system.TinyConfig.fir@102864.4]
  output  auto_int_out_2, // @[:freechips.rocketchip.system.TinyConfig.fir@102864.4]
  output  auto_int_out_3 // @[:freechips.rocketchip.system.TinyConfig.fir@102864.4]
);
  assign auto_int_out_0 = auto_int_in_0_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102877.4]
  assign auto_int_out_1 = auto_int_in_1_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102877.4]
  assign auto_int_out_2 = auto_int_in_1_1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102877.4]
  assign auto_int_out_3 = auto_int_in_2_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@102877.4]
endmodule
module IntSyncCrossingSink_2( // @[:freechips.rocketchip.system.TinyConfig.fir@115330.2]
  input   auto_in_sync_0, // @[:freechips.rocketchip.system.TinyConfig.fir@115333.4]
  output  auto_out_0 // @[:freechips.rocketchip.system.TinyConfig.fir@115333.4]
);
  assign auto_out_0 = auto_in_sync_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115342.4]
endmodule
module SynchronizerShiftReg_w1_d3( // @[:freechips.rocketchip.system.TinyConfig.fir@115270.2]
  input   clock, // @[:freechips.rocketchip.system.TinyConfig.fir@115271.4]
  input   io_d, // @[:freechips.rocketchip.system.TinyConfig.fir@115273.4]
  output  io_q // @[:freechips.rocketchip.system.TinyConfig.fir@115273.4]
);
  reg  sync_0; // @[ShiftReg.scala 114:16:freechips.rocketchip.system.TinyConfig.fir@115278.4]
  reg [31:0] _RAND_0;
  reg  sync_1; // @[ShiftReg.scala 114:16:freechips.rocketchip.system.TinyConfig.fir@115279.4]
  reg [31:0] _RAND_1;
  reg  sync_2; // @[ShiftReg.scala 114:16:freechips.rocketchip.system.TinyConfig.fir@115280.4]
  reg [31:0] _RAND_2;
  assign io_q = sync_0; // @[ShiftReg.scala 123:8:freechips.rocketchip.system.TinyConfig.fir@115284.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  sync_0 = _RAND_0[0:0];
  `endif // RANDOMIZE_REG_INIT
  `ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  sync_1 = _RAND_1[0:0];
  `endif // RANDOMIZE_REG_INIT
  `ifdef RANDOMIZE_REG_INIT
  _RAND_2 = {1{`RANDOM}};
  sync_2 = _RAND_2[0:0];
  `endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end
  always @(posedge clock) begin
    sync_0 <= sync_1;
    sync_1 <= sync_2;
    sync_2 <= io_d;
  end
endmodule
module IntSyncCrossingSink_1( // @[:freechips.rocketchip.system.TinyConfig.fir@115314.2]
  input   auto_in_sync_0, // @[:freechips.rocketchip.system.TinyConfig.fir@115317.4]
  input   auto_in_sync_1, // @[:freechips.rocketchip.system.TinyConfig.fir@115317.4]
  output  auto_out_0, // @[:freechips.rocketchip.system.TinyConfig.fir@115317.4]
  output  auto_out_1 // @[:freechips.rocketchip.system.TinyConfig.fir@115317.4]
);
  assign auto_out_0 = auto_in_sync_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115326.4]
  assign auto_out_1 = auto_in_sync_1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.TinyConfig.fir@115326.4]
endmodule
module bsg_scan_width_p8_or_p1_lo_to_hi_p1
(
  i,
  o
);

  input [7:0] i;
  output [7:0] o;
  wire [7:0] o;
  wire t_2__7_,t_2__6_,t_2__5_,t_2__4_,t_2__3_,t_2__2_,t_2__1_,t_2__0_,t_1__7_,t_1__6_,
  t_1__5_,t_1__4_,t_1__3_,t_1__2_,t_1__1_,t_1__0_;
  assign t_1__7_ = i[0] | 1'b0;
  assign t_1__6_ = i[1] | i[0];
  assign t_1__5_ = i[2] | i[1];
  assign t_1__4_ = i[3] | i[2];
  assign t_1__3_ = i[4] | i[3];
  assign t_1__2_ = i[5] | i[4];
  assign t_1__1_ = i[6] | i[5];
  assign t_1__0_ = i[7] | i[6];
  assign t_2__7_ = t_1__7_ | 1'b0;
  assign t_2__6_ = t_1__6_ | 1'b0;
  assign t_2__5_ = t_1__5_ | t_1__7_;
  assign t_2__4_ = t_1__4_ | t_1__6_;
  assign t_2__3_ = t_1__3_ | t_1__5_;
  assign t_2__2_ = t_1__2_ | t_1__4_;
  assign t_2__1_ = t_1__1_ | t_1__3_;
  assign t_2__0_ = t_1__0_ | t_1__2_;
  assign o[0] = t_2__7_ | 1'b0;
  assign o[1] = t_2__6_ | 1'b0;
  assign o[2] = t_2__5_ | 1'b0;
  assign o[3] = t_2__4_ | 1'b0;
  assign o[4] = t_2__3_ | t_2__7_;
  assign o[5] = t_2__2_ | t_2__6_;
  assign o[6] = t_2__1_ | t_2__5_;
  assign o[7] = t_2__0_ | t_2__4_;

endmodule
module itlb_vaddr_width_p56_paddr_width_p22_eaddr_width_p64_btb_indx_width_p9_bht_indx_width_p5_ras_addr_width_p22_asid_width_p10_ppn_start_bit_p12_tag_width_p10
(
  clk_i,
  reset_i,
  fe_itlb_i,
  fe_itlb_v_i,
  fe_itlb_ready_o,
  pc_gen_itlb_i,
  pc_gen_itlb_v_i,
  pc_gen_itlb_ready_o,
  itlb_icache_o,
  itlb_icache_data_resp_v_o,
  itlb_icache_data_resp_ready_i,
  itlb_fe_o,
  itlb_fe_v_o,
  itlb_fe_ready_i
);

  input [108:0] fe_itlb_i;
  input [63:0] pc_gen_itlb_i;
  output [9:0] itlb_icache_o;
  output [133:0] itlb_fe_o;
  input clk_i;
  input reset_i;
  input fe_itlb_v_i;
  input pc_gen_itlb_v_i;
  input itlb_icache_data_resp_ready_i;
  input itlb_fe_ready_i;
  output fe_itlb_ready_o;
  output pc_gen_itlb_ready_o;
  output itlb_icache_data_resp_v_o;
  output itlb_fe_v_o;
  wire [133:0] itlb_fe_o;
  wire fe_itlb_ready_o,pc_gen_itlb_ready_o,itlb_icache_data_resp_v_o,itlb_fe_v_o;
  reg [9:0] itlb_icache_o;
  assign pc_gen_itlb_ready_o = 1'b1;
  assign itlb_icache_data_resp_v_o = 1'b1;
  assign fe_itlb_ready_o = 1'b0;
  assign itlb_fe_v_o = 1'b0;

  always @(posedge clk_i) begin
    if(1'b1) begin
      { itlb_icache_o[9:0] } <= { pc_gen_itlb_i[21:12] };
    end 
  end


endmodule
module bp_be_dcache_lru_encode_ways_p8
(
  lru_i,
  way_id_o
);

  input [6:0] lru_i;
  output [2:0] way_id_o;
  wire [2:0] way_id_o;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
  N22,N23,N24,N25,N26,N27,N28,N29,N30;
  assign N11 = N8 & N9;
  assign N12 = N11 & N10;
  assign N13 = lru_i[3] & N9;
  assign N14 = N13 & N10;
  assign N16 = N15 & lru_i[1];
  assign N17 = N16 & N10;
  assign N18 = lru_i[4] & lru_i[1];
  assign N19 = N18 & N10;
  assign N22 = N20 & N21;
  assign N23 = N22 & lru_i[0];
  assign N24 = lru_i[5] & N21;
  assign N25 = N24 & lru_i[0];
  assign N27 = N26 & lru_i[2];
  assign N28 = N27 & lru_i[0];
  assign N29 = lru_i[6] & lru_i[2];
  assign N30 = N29 & lru_i[0];
  assign way_id_o = (N0)? { 1'b0, 1'b0, 1'b0 } : 
                    (N1)? { 1'b0, 1'b0, 1'b1 } : 
                    (N2)? { 1'b0, 1'b1, 1'b0 } : 
                    (N3)? { 1'b0, 1'b1, 1'b1 } : 
                    (N4)? { 1'b1, 1'b0, 1'b0 } : 
                    (N5)? { 1'b1, 1'b0, 1'b1 } : 
                    (N6)? { 1'b1, 1'b1, 1'b0 } : 
                    (N7)? { 1'b1, 1'b1, 1'b1 } : 1'b0;
  assign N0 = N12;
  assign N1 = N14;
  assign N2 = N17;
  assign N3 = N19;
  assign N4 = N23;
  assign N5 = N25;
  assign N6 = N28;
  assign N7 = N30;
  assign N8 = ~lru_i[3];
  assign N9 = ~lru_i[1];
  assign N10 = ~lru_i[0];
  assign N15 = ~lru_i[4];
  assign N20 = ~lru_i[5];
  assign N21 = ~lru_i[2];
  assign N26 = ~lru_i[6];

endmodule
module bp_be_dcache_lru_decode_ways_p8
(
  way_id_i,
  data_o,
  mask_o
);

  input [2:0] way_id_i;
  output [6:0] data_o;
  output [6:0] mask_o;
  wire [6:0] data_o,mask_o;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
  N22,N23,N24,N25,N26,N27,N28,N29,N30;
  assign mask_o[0] = 1'b1;
  assign N11 = N8 & N9;
  assign N12 = N11 & N10;
  assign N13 = way_id_i[2] | way_id_i[1];
  assign N14 = N13 | N10;
  assign N16 = way_id_i[2] | N9;
  assign N17 = N16 | way_id_i[0];
  assign N19 = N16 | N10;
  assign N21 = N8 | way_id_i[1];
  assign N22 = N21 | way_id_i[0];
  assign N24 = N21 | N10;
  assign N26 = N8 | N9;
  assign N27 = N26 | way_id_i[0];
  assign N29 = way_id_i[2] & way_id_i[1];
  assign N30 = N29 & way_id_i[0];
  assign data_o = (N0)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1 } : 
                  (N1)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 } : 
                  (N2)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b1 } : 
                  (N3)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } : 
                  (N4)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } : 
                  (N5)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } : 
                  (N6)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 
                  (N7)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
  assign N0 = N12;
  assign N1 = N15;
  assign N2 = N18;
  assign N3 = N20;
  assign N4 = N23;
  assign N5 = N25;
  assign N6 = N28;
  assign N7 = N30;
  assign mask_o[6:1] = (N0)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1 } : 
                       (N1)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1 } : 
                       (N2)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1 } : 
                       (N3)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1 } : 
                       (N4)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0 } : 
                       (N5)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0 } : 
                       (N6)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } : 
                       (N7)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } : 1'b0;
  assign N8 = ~way_id_i[2];
  assign N9 = ~way_id_i[1];
  assign N10 = ~way_id_i[0];
  assign N15 = ~N14;
  assign N18 = ~N17;
  assign N20 = ~N19;
  assign N23 = ~N22;
  assign N25 = ~N24;
  assign N28 = ~N27;

endmodule
module bsg_encode_one_hot_width_p1
(
  i,
  addr_o,
  v_o
);

  input [0:0] i;
  output [0:0] addr_o;
  output v_o;
  wire [0:0] addr_o;
  wire v_o;
  assign v_o = i[0];
  assign addr_o[0] = 1'b0;

endmodule
module bsg_decode_num_out_p8
(
  i,
  o
);

  input [2:0] i;
  output [7:0] o;
  wire [7:0] o;
  assign o = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } << i;

endmodule
module bsg_circular_ptr_slots_p32_max_add_p31
(
  clk,
  reset_i,
  add_i,
  o
);

  input [4:0] add_i;
  output [4:0] o;
  input clk;
  input reset_i;
  wire N0,N1,N2,N3,N4,N5,N6,N7;
  wire [4:0] ptr_n;
  reg [4:0] o;
  assign ptr_n = o + add_i;
  assign { N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
                                  (N1)? ptr_n : 1'b0;
  assign N0 = reset_i;
  assign N1 = N2;
  assign N2 = ~reset_i;

  always @(posedge clk) begin
    if(1'b1) begin
      { o[4:0] } <= { N7, N6, N5, N4, N3 };
    end
  end


endmodule
module bsg_dff_en_width_p5
(
  clk_i,
  data_i,
  en_i,
  data_o
);

  input [4:0] data_i;
  output [4:0] data_o;
  input clk_i;
  input en_i;
  reg [4:0] data_o;

  always @(posedge clk_i) begin
    if(en_i) begin
      { data_o[4:0] } <= { data_i[4:0] };
    end
  end


endmodule
module bsg_dff_en_width_p36
(
  clk_i,
  data_i,
  en_i,
  data_o
);

  input [35:0] data_i;
  output [35:0] data_o;
  input clk_i;
  input en_i;
  reg [35:0] data_o;

  always @(posedge clk_i) begin
    if(en_i) begin
      { data_o[35:0] } <= { data_i[35:0] };
    end
  end


endmodule
module bsg_circular_ptr_slots_p8_max_add_p1
(
  clk,
  reset_i,
  add_i,
  o
);

  input [0:0] add_i;
  output [2:0] o;
  input clk;
  input reset_i;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8;
  wire [2:0] genblk1_genblk1_ptr_r_p1;
  reg [2:0] o;
  assign genblk1_genblk1_ptr_r_p1 = o + 1'b1;
  assign { N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0 } :
                          (N1)? genblk1_genblk1_ptr_r_p1 : 1'b0;
  assign N0 = reset_i;
  assign N1 = N2;
  assign N2 = ~reset_i;
  assign N6 = ~add_i[0];
  assign N7 = N6 & N2;
  assign N8 = ~N7;

  always @(posedge clk) begin
    if(N8) begin
      { o[2:0] } <= { N5, N4, N3 };
    end
  end


endmodule
module bsg_mem_1r1w_synth_width_p26_els_p2_read_write_same_addr_p0_harden_p0
(
  w_clk_i,
  w_reset_i,
  w_v_i,
  w_addr_i,
  w_data_i,
  r_v_i,
  r_addr_i,
  r_data_o
);

  input [0:0] w_addr_i;
  input [25:0] w_data_i;
  input [0:0] r_addr_i;
  output [25:0] r_data_o;
  input w_clk_i;
  input w_reset_i;
  input w_v_i;
  input r_v_i;
  wire [25:0] r_data_o;
  wire N0,N1,N2,N3,N4,N5,N7,N8;
  reg [51:0] mem;
  assign r_data_o[25] = (N3)? mem[25] :
                        (N0)? mem[51] : 1'b0;
  assign N0 = r_addr_i[0];
  assign r_data_o[24] = (N3)? mem[24] :
                        (N0)? mem[50] : 1'b0;
  assign r_data_o[23] = (N3)? mem[23] :
                        (N0)? mem[49] : 1'b0;
  assign r_data_o[22] = (N3)? mem[22] :
                        (N0)? mem[48] : 1'b0;
  assign r_data_o[21] = (N3)? mem[21] :
                        (N0)? mem[47] : 1'b0;
  assign r_data_o[20] = (N3)? mem[20] :
                        (N0)? mem[46] : 1'b0;
  assign r_data_o[19] = (N3)? mem[19] :
                        (N0)? mem[45] : 1'b0;
  assign r_data_o[18] = (N3)? mem[18] :
                        (N0)? mem[44] : 1'b0;
  assign r_data_o[17] = (N3)? mem[17] :
                        (N0)? mem[43] : 1'b0;
  assign r_data_o[16] = (N3)? mem[16] :
                        (N0)? mem[42] : 1'b0;
  assign r_data_o[15] = (N3)? mem[15] :
                        (N0)? mem[41] : 1'b0;
  assign r_data_o[14] = (N3)? mem[14] :
                        (N0)? mem[40] : 1'b0;
  assign r_data_o[13] = (N3)? mem[13] :
                        (N0)? mem[39] : 1'b0;
  assign r_data_o[12] = (N3)? mem[12] :
                        (N0)? mem[38] : 1'b0;
  assign r_data_o[11] = (N3)? mem[11] :
                        (N0)? mem[37] : 1'b0;
  assign r_data_o[10] = (N3)? mem[10] :
                        (N0)? mem[36] : 1'b0;
  assign r_data_o[9] = (N3)? mem[9] :
                       (N0)? mem[35] : 1'b0;
  assign r_data_o[8] = (N3)? mem[8] :
                       (N0)? mem[34] : 1'b0;
  assign r_data_o[7] = (N3)? mem[7] :
                       (N0)? mem[33] : 1'b0;
  assign r_data_o[6] = (N3)? mem[6] :
                       (N0)? mem[32] : 1'b0;
  assign r_data_o[5] = (N3)? mem[5] :
                       (N0)? mem[31] : 1'b0;
  assign r_data_o[4] = (N3)? mem[4] :
                       (N0)? mem[30] : 1'b0;
  assign r_data_o[3] = (N3)? mem[3] :
                       (N0)? mem[29] : 1'b0;
  assign r_data_o[2] = (N3)? mem[2] :
                       (N0)? mem[28] : 1'b0;
  assign r_data_o[1] = (N3)? mem[1] :
                       (N0)? mem[27] : 1'b0;
  assign r_data_o[0] = (N3)? mem[0] :
                       (N0)? mem[26] : 1'b0;
  assign N5 = ~w_addr_i[0];
  assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
                      (N2)? { 1'b0, 1'b0 } : 1'b0;
  assign N1 = w_v_i;
  assign N2 = N4;
  assign N3 = ~r_addr_i[0];
  assign N4 = ~w_v_i;

  always @(posedge w_clk_i) begin
    if(N8) begin
      { mem[51:26] } <= { w_data_i[25:0] };
    end
    if(N7) begin
      { mem[25:0] } <= { w_data_i[25:0] };
    end
  end


endmodule
module bsg_mux_width_p32_els_p2
(
  data_i,
  sel_i,
  data_o
);

  input [63:0] data_i;
  input [0:0] sel_i;
  output [31:0] data_o;
  wire [31:0] data_o;
  wire N0,N1;
  assign data_o[31] = (N1)? data_i[31] :
                      (N0)? data_i[63] : 1'b0;
  assign N0 = sel_i[0];
  assign data_o[30] = (N1)? data_i[30] :
                      (N0)? data_i[62] : 1'b0;
  assign data_o[29] = (N1)? data_i[29] :
                      (N0)? data_i[61] : 1'b0;
  assign data_o[28] = (N1)? data_i[28] :
                      (N0)? data_i[60] : 1'b0;
  assign data_o[27] = (N1)? data_i[27] :
                      (N0)? data_i[59] : 1'b0;
  assign data_o[26] = (N1)? data_i[26] :
                      (N0)? data_i[58] : 1'b0;
  assign data_o[25] = (N1)? data_i[25] :
                      (N0)? data_i[57] : 1'b0;
  assign data_o[24] = (N1)? data_i[24] :
                      (N0)? data_i[56] : 1'b0;
  assign data_o[23] = (N1)? data_i[23] :
                      (N0)? data_i[55] : 1'b0;
  assign data_o[22] = (N1)? data_i[22] :
                      (N0)? data_i[54] : 1'b0;
  assign data_o[21] = (N1)? data_i[21] :
                      (N0)? data_i[53] : 1'b0;
  assign data_o[20] = (N1)? data_i[20] :
                      (N0)? data_i[52] : 1'b0;
  assign data_o[19] = (N1)? data_i[19] :
                      (N0)? data_i[51] : 1'b0;
  assign data_o[18] = (N1)? data_i[18] :
                      (N0)? data_i[50] : 1'b0;
  assign data_o[17] = (N1)? data_i[17] :
                      (N0)? data_i[49] : 1'b0;
  assign data_o[16] = (N1)? data_i[16] :
                      (N0)? data_i[48] : 1'b0;
  assign data_o[15] = (N1)? data_i[15] :
                      (N0)? data_i[47] : 1'b0;
  assign data_o[14] = (N1)? data_i[14] :
                      (N0)? data_i[46] : 1'b0;
  assign data_o[13] = (N1)? data_i[13] :
                      (N0)? data_i[45] : 1'b0;
  assign data_o[12] = (N1)? data_i[12] :
                      (N0)? data_i[44] : 1'b0;
  assign data_o[11] = (N1)? data_i[11] :
                      (N0)? data_i[43] : 1'b0;
  assign data_o[10] = (N1)? data_i[10] :
                      (N0)? data_i[42] : 1'b0;
  assign data_o[9] = (N1)? data_i[9] :
                     (N0)? data_i[41] : 1'b0;
  assign data_o[8] = (N1)? data_i[8] :
                     (N0)? data_i[40] : 1'b0;
  assign data_o[7] = (N1)? data_i[7] :
                     (N0)? data_i[39] : 1'b0;
  assign data_o[6] = (N1)? data_i[6] :
                     (N0)? data_i[38] : 1'b0;
  assign data_o[5] = (N1)? data_i[5] :
                     (N0)? data_i[37] : 1'b0;
  assign data_o[4] = (N1)? data_i[4] :
                     (N0)? data_i[36] : 1'b0;
  assign data_o[3] = (N1)? data_i[3] :
                     (N0)? data_i[35] : 1'b0;
  assign data_o[2] = (N1)? data_i[2] :
                     (N0)? data_i[34] : 1'b0;
  assign data_o[1] = (N1)? data_i[1] :
                     (N0)? data_i[33] : 1'b0;
  assign data_o[0] = (N1)? data_i[0] :
                     (N0)? data_i[32] : 1'b0;
  assign N1 = ~sel_i[0];

endmodule
module bsg_mux_segmented_segments_p5_segment_width_p128
(
  data0_i,
  data1_i,
  sel_i,
  data_o
);

  input [639:0] data0_i;
  input [639:0] data1_i;
  input [4:0] sel_i;
  output [639:0] data_o;
  wire [639:0] data_o;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9;
  assign data_o[127:0] = (N0)? data1_i[127:0] :
                         (N5)? data0_i[127:0] : 1'b0;
  assign N0 = sel_i[0];
  assign data_o[255:128] = (N1)? data1_i[255:128] :
                           (N6)? data0_i[255:128] : 1'b0;
  assign N1 = sel_i[1];
  assign data_o[383:256] = (N2)? data1_i[383:256] :
                           (N7)? data0_i[383:256] : 1'b0;
  assign N2 = sel_i[2];
  assign data_o[511:384] = (N3)? data1_i[511:384] :
                           (N8)? data0_i[511:384] : 1'b0;
  assign N3 = sel_i[3];
  assign data_o[639:512] = (N4)? data1_i[639:512] :
                           (N9)? data0_i[639:512] : 1'b0;
  assign N4 = sel_i[4];
  assign N5 = ~sel_i[0];
  assign N6 = ~sel_i[1];
  assign N7 = ~sel_i[2];
  assign N8 = ~sel_i[3];
  assign N9 = ~sel_i[4];

endmodule
module bsg_round_robin_arb_inputs_p2
(
  clk_i,
  reset_i,
  grants_en_i,
  reqs_i,
  grants_o,
  sel_one_hot_o,
  v_o,
  tag_o,
  yumi_i
);

  input [1:0] reqs_i;
  output [1:0] grants_o;
  output [1:0] sel_one_hot_o;
  output [0:0] tag_o;
  input clk_i;
  input reset_i;
  input grants_en_i;
  input yumi_i;
  output v_o;
  wire [1:0] grants_o,sel_one_hot_o;
  wire [0:0] tag_o;
  wire v_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,
  N21,N22;
  reg [0:0] last_r;
  assign N13 = N0 & N1;
  assign N0 = ~reqs_i[1];
  assign N1 = ~reqs_i[0];
  assign N14 = reqs_i[1] & N2;
  assign N2 = ~last_r[0];
  assign N15 = N3 & reqs_i[0] & N4;
  assign N3 = ~reqs_i[1];
  assign N4 = ~last_r[0];
  assign N16 = reqs_i[0] & last_r[0];
  assign N17 = reqs_i[1] & N5 & last_r[0];
  assign N5 = ~reqs_i[0];
  assign sel_one_hot_o = (N6)? { 1'b0, 1'b0 } :
                         (N7)? { 1'b1, 1'b0 } :
                         (N8)? { 1'b0, 1'b1 } :
                         (N9)? { 1'b0, 1'b1 } :
                         (N10)? { 1'b1, 1'b0 } : 1'b0;
  assign N6 = N13;
  assign N7 = N14;
  assign N8 = N15;
  assign N9 = N16;
  assign N10 = N17;
  assign tag_o[0] = (N6)? 1'b0 :
                    (N7)? 1'b1 :
                    (N8)? 1'b0 :
                    (N9)? 1'b0 :
                    (N10)? 1'b1 : 1'b0;
  assign N20 = (N11)? 1'b0 :
               (N12)? tag_o[0] : 1'b0;
  assign N11 = reset_i;
  assign N12 = N19;
  assign grants_o[1] = sel_one_hot_o[1] & grants_en_i;
  assign grants_o[0] = sel_one_hot_o[0] & grants_en_i;
  assign v_o = reqs_i[1] | reqs_i[0];
  assign N18 = ~yumi_i;
  assign N19 = ~reset_i;
  assign N21 = N18 & N19;
  assign N22 = ~N21;

  always @(posedge clk_i) begin
    if(N22) begin
      { last_r[0:0] } <= { N20 };
    end
  end


endmodule
module bsg_mux_segmented_segments_p8_segment_width_p8
(
  data0_i,
  data1_i,
  sel_i,
  data_o
);

  input [63:0] data0_i;
  input [63:0] data1_i;
  input [7:0] sel_i;
  output [63:0] data_o;
  wire [63:0] data_o;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15;
  assign data_o[7:0] = (N0)? data1_i[7:0] :
                       (N8)? data0_i[7:0] : 1'b0;
  assign N0 = sel_i[0];
  assign data_o[15:8] = (N1)? data1_i[15:8] :
                        (N9)? data0_i[15:8] : 1'b0;
  assign N1 = sel_i[1];
  assign data_o[23:16] = (N2)? data1_i[23:16] :
                         (N10)? data0_i[23:16] : 1'b0;
  assign N2 = sel_i[2];
  assign data_o[31:24] = (N3)? data1_i[31:24] :
                         (N11)? data0_i[31:24] : 1'b0;
  assign N3 = sel_i[3];
  assign data_o[39:32] = (N4)? data1_i[39:32] :
                         (N12)? data0_i[39:32] : 1'b0;
  assign N4 = sel_i[4];
  assign data_o[47:40] = (N5)? data1_i[47:40] :
                         (N13)? data0_i[47:40] : 1'b0;
  assign N5 = sel_i[5];
  assign data_o[55:48] = (N6)? data1_i[55:48] :
                         (N14)? data0_i[55:48] : 1'b0;
  assign N6 = sel_i[6];
  assign data_o[63:56] = (N7)? data1_i[63:56] :
                         (N15)? data0_i[63:56] : 1'b0;
  assign N7 = sel_i[7];
  assign N8 = ~sel_i[0];
  assign N9 = ~sel_i[1];
  assign N10 = ~sel_i[2];
  assign N11 = ~sel_i[3];
  assign N12 = ~sel_i[4];
  assign N13 = ~sel_i[5];
  assign N14 = ~sel_i[6];
  assign N15 = ~sel_i[7];

endmodule
module bp_be_dcache_wbuf_queue_width_p97
(
  clk_i,
  data_i,
  el0_en_i,
  el1_en_i,
  mux0_sel_i,
  mux1_sel_i,
  el0_snoop_o,
  el1_snoop_o,
  data_o
);

  input [96:0] data_i;
  output [96:0] el0_snoop_o;
  output [96:0] el1_snoop_o;
  output [96:0] data_o;
  input clk_i;
  input el0_en_i;
  input el1_en_i;
  input mux0_sel_i;
  input mux1_sel_i;
  wire [96:0] data_o;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
  N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
  N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
  N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
  N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
  N102;
  reg [96:0] el0_snoop_o,el1_snoop_o;
  assign { N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5 } = (N0)? el0_snoop_o :
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                (N1)? data_i : 1'b0;
  assign N0 = mux0_sel_i;
  assign N1 = N4;
  assign data_o = (N2)? el1_snoop_o :
                  (N3)? data_i : 1'b0;
  assign N2 = mux1_sel_i;
  assign N3 = N102;
  assign N4 = ~mux0_sel_i;
  assign N102 = ~mux1_sel_i;

  always @(posedge clk_i) begin
    if(el0_en_i) begin
      { el0_snoop_o[96:0] } <= { data_i[96:0] };
    end
    if(el1_en_i) begin
      { el1_snoop_o[96:0] } <= { N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5 };
    end
  end


endmodule
module bsg_circular_ptr_slots_p32_max_add_p1
(
  clk,
  reset_i,
  add_i,
  o
);

  input [0:0] add_i;
  output [4:0] o;
  input clk;
  input reset_i;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10;
  wire [4:0] genblk1_genblk1_ptr_r_p1;
  reg [4:0] o;
  assign genblk1_genblk1_ptr_r_p1 = o + 1'b1;
  assign { N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
                                  (N1)? genblk1_genblk1_ptr_r_p1 : 1'b0;
  assign N0 = reset_i;
  assign N1 = N2;
  assign N2 = ~reset_i;
  assign N8 = ~add_i[0];
  assign N9 = N8 & N2;
  assign N10 = ~N9;

  always @(posedge clk) begin
    if(N10) begin
      { o[4:0] } <= { N7, N6, N5, N4, N3 };
    end
  end


endmodule
module bsg_scan_width_p5_or_p1_lo_to_hi_p1
(
  i,
  o
);

  input [4:0] i;
  output [4:0] o;
  wire [4:0] o;
  wire t_2__4_,t_2__3_,t_2__2_,t_2__1_,t_2__0_,t_1__4_,t_1__3_,t_1__2_,t_1__1_,t_1__0_;
  assign t_1__4_ = i[0] | 1'b0;
  assign t_1__3_ = i[1] | i[0];
  assign t_1__2_ = i[2] | i[1];
  assign t_1__1_ = i[3] | i[2];
  assign t_1__0_ = i[4] | i[3];
  assign t_2__4_ = t_1__4_ | 1'b0;
  assign t_2__3_ = t_1__3_ | 1'b0;
  assign t_2__2_ = t_1__2_ | t_1__4_;
  assign t_2__1_ = t_1__1_ | t_1__3_;
  assign t_2__0_ = t_1__0_ | t_1__2_;
  assign o[0] = t_2__4_ | 1'b0;
  assign o[1] = t_2__3_ | 1'b0;
  assign o[2] = t_2__2_ | 1'b0;
  assign o[3] = t_2__1_ | 1'b0;
  assign o[4] = t_2__0_ | t_2__4_;

endmodule
module bsg_dff_width_p640
(
  clk_i,
  data_i,
  data_o
);

  input [639:0] data_i;
  output [639:0] data_o;
  input clk_i;
  reg [639:0] data_o;

  always @(posedge clk_i) begin
    if(1'b1) begin
      { data_o[639:0] } <= { data_i[639:0] };
    end
  end


endmodule
module itlb_vaddr_width_p56_paddr_width_p22_eaddr_width_p64_btb_indx_width_p9_bht_indx_width_p5_ras_addr_width_p22_asid_width_p10_ppn_start_bit_p12_tag_width_p10
(
  clk_i,
  reset_i,
  fe_itlb_i,
  fe_itlb_v_i,
  fe_itlb_ready_o,
  pc_gen_itlb_i,
  pc_gen_itlb_v_i,
  pc_gen_itlb_ready_o,
  itlb_icache_o,
  itlb_icache_data_resp_v_o,
  itlb_icache_data_resp_ready_i,
  itlb_fe_o,
  itlb_fe_v_o,
  itlb_fe_ready_i
);

  input [108:0] fe_itlb_i;
  input [63:0] pc_gen_itlb_i;
  output [9:0] itlb_icache_o;
  output [133:0] itlb_fe_o;
  input clk_i;
  input reset_i;
  input fe_itlb_v_i;
  input pc_gen_itlb_v_i;
  input itlb_icache_data_resp_ready_i;
  input itlb_fe_ready_i;
  output fe_itlb_ready_o;
  output pc_gen_itlb_ready_o;
  output itlb_icache_data_resp_v_o;
  output itlb_fe_v_o;
  wire [133:0] itlb_fe_o;
  wire fe_itlb_ready_o,pc_gen_itlb_ready_o,itlb_icache_data_resp_v_o,itlb_fe_v_o;
  reg [9:0] itlb_icache_o;
  assign pc_gen_itlb_ready_o = 1'b1;
  assign itlb_icache_data_resp_v_o = 1'b1;
  assign fe_itlb_ready_o = 1'b0;
  assign itlb_fe_v_o = 1'b0;

  always @(posedge clk_i) begin
    if(1'b1) begin
      { itlb_icache_o[9:0] } <= { pc_gen_itlb_i[21:12] };
    end
  end


endmodule
module bsg_mem_1r1w_synth_width_p27_els_p2_read_write_same_addr_p0_harden_p0
(
  w_clk_i,
  w_reset_i,
  w_v_i,
  w_addr_i,
  w_data_i,
  r_v_i,
  r_addr_i,
  r_data_o
);

  input [0:0] w_addr_i;
  input [26:0] w_data_i;
  input [0:0] r_addr_i;
  output [26:0] r_data_o;
  input w_clk_i;
  input w_reset_i;
  input w_v_i;
  input r_v_i;
  wire [26:0] r_data_o;
  wire N0,N1,N2,N3,N4,N5,N7,N8;
  reg [53:0] mem;
  assign r_data_o[26] = (N3)? mem[26] :
                        (N0)? mem[53] : 1'b0;
  assign N0 = r_addr_i[0];
  assign r_data_o[25] = (N3)? mem[25] :
                        (N0)? mem[52] : 1'b0;
  assign r_data_o[24] = (N3)? mem[24] :
                        (N0)? mem[51] : 1'b0;
  assign r_data_o[23] = (N3)? mem[23] :
                        (N0)? mem[50] : 1'b0;
  assign r_data_o[22] = (N3)? mem[22] :
                        (N0)? mem[49] : 1'b0;
  assign r_data_o[21] = (N3)? mem[21] :
                        (N0)? mem[48] : 1'b0;
  assign r_data_o[20] = (N3)? mem[20] :
                        (N0)? mem[47] : 1'b0;
  assign r_data_o[19] = (N3)? mem[19] :
                        (N0)? mem[46] : 1'b0;
  assign r_data_o[18] = (N3)? mem[18] :
                        (N0)? mem[45] : 1'b0;
  assign r_data_o[17] = (N3)? mem[17] :
                        (N0)? mem[44] : 1'b0;
  assign r_data_o[16] = (N3)? mem[16] :
                        (N0)? mem[43] : 1'b0;
  assign r_data_o[15] = (N3)? mem[15] :
                        (N0)? mem[42] : 1'b0;
  assign r_data_o[14] = (N3)? mem[14] :
                        (N0)? mem[41] : 1'b0;
  assign r_data_o[13] = (N3)? mem[13] :
                        (N0)? mem[40] : 1'b0;
  assign r_data_o[12] = (N3)? mem[12] :
                        (N0)? mem[39] : 1'b0;
  assign r_data_o[11] = (N3)? mem[11] :
                        (N0)? mem[38] : 1'b0;
  assign r_data_o[10] = (N3)? mem[10] :
                        (N0)? mem[37] : 1'b0;
  assign r_data_o[9] = (N3)? mem[9] :
                       (N0)? mem[36] : 1'b0;
  assign r_data_o[8] = (N3)? mem[8] :
                       (N0)? mem[35] : 1'b0;
  assign r_data_o[7] = (N3)? mem[7] :
                       (N0)? mem[34] : 1'b0;
  assign r_data_o[6] = (N3)? mem[6] :
                       (N0)? mem[33] : 1'b0;
  assign r_data_o[5] = (N3)? mem[5] :
                       (N0)? mem[32] : 1'b0;
  assign r_data_o[4] = (N3)? mem[4] :
                       (N0)? mem[31] : 1'b0;
  assign r_data_o[3] = (N3)? mem[3] :
                       (N0)? mem[30] : 1'b0;
  assign r_data_o[2] = (N3)? mem[2] :
                       (N0)? mem[29] : 1'b0;
  assign r_data_o[1] = (N3)? mem[1] :
                       (N0)? mem[28] : 1'b0;
  assign r_data_o[0] = (N3)? mem[0] :
                       (N0)? mem[27] : 1'b0;
  assign N5 = ~w_addr_i[0];
  assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
                      (N2)? { 1'b0, 1'b0 } : 1'b0;
  assign N1 = w_v_i;
  assign N2 = N4;
  assign N3 = ~r_addr_i[0];
  assign N4 = ~w_v_i;

  always @(posedge w_clk_i) begin
    if(N8) begin
      { mem[53:27] } <= { w_data_i[26:0] };
    end
    if(N7) begin
      { mem[26:0] } <= { w_data_i[26:0] };
    end
  end


endmodule
module bsg_dff_reset_en_width_p8
(
  clk_i,
  reset_i,
  en_i,
  data_i,
  data_o
);

  input [7:0] data_i;
  output [7:0] data_o;
  input clk_i;
  input reset_i;
  input en_i;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13;
  reg [7:0] data_o;
  assign N3 = (N0)? 1'b1 :
              (N13)? 1'b1 :
              (N2)? 1'b0 : 1'b0;
  assign N0 = reset_i;
  assign { N11, N10, N9, N8, N7, N6, N5, N4 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
                                                (N13)? data_i : 1'b0;
  assign N1 = en_i | reset_i;
  assign N2 = ~N1;
  assign N12 = ~reset_i;
  assign N13 = en_i & N12;

  always @(posedge clk_i) begin
    if(N3) begin
      { data_o[7:0] } <= { N11, N10, N9, N8, N7, N6, N5, N4 };
    end
  end


endmodule
module bp_be_pipe_fp
(
  clk_i,
  reset_i,
  decode_i,
  rs1_i,
  rs2_i,
  exc_i,
  result_o
);

  input [42:0] decode_i;
  input [63:0] rs1_i;
  input [63:0] rs2_i;
  input [6:0] exc_i;
  output [63:0] result_o;
  input clk_i;
  input reset_i;
  wire [63:0] result_o;
  assign result_o[0] = 1'b0;
  assign result_o[1] = 1'b0;
  assign result_o[2] = 1'b0;
  assign result_o[3] = 1'b0;
  assign result_o[4] = 1'b0;
  assign result_o[5] = 1'b0;
  assign result_o[6] = 1'b0;
  assign result_o[7] = 1'b0;
  assign result_o[8] = 1'b0;
  assign result_o[9] = 1'b0;
  assign result_o[10] = 1'b0;
  assign result_o[11] = 1'b0;
  assign result_o[12] = 1'b0;
  assign result_o[13] = 1'b0;
  assign result_o[14] = 1'b0;
  assign result_o[15] = 1'b0;
  assign result_o[16] = 1'b0;
  assign result_o[17] = 1'b0;
  assign result_o[18] = 1'b0;
  assign result_o[19] = 1'b0;
  assign result_o[20] = 1'b0;
  assign result_o[21] = 1'b0;
  assign result_o[22] = 1'b0;
  assign result_o[23] = 1'b0;
  assign result_o[24] = 1'b0;
  assign result_o[25] = 1'b0;
  assign result_o[26] = 1'b0;
  assign result_o[27] = 1'b0;
  assign result_o[28] = 1'b0;
  assign result_o[29] = 1'b0;
  assign result_o[30] = 1'b0;
  assign result_o[31] = 1'b0;
  assign result_o[32] = 1'b0;
  assign result_o[33] = 1'b0;
  assign result_o[34] = 1'b0;
  assign result_o[35] = 1'b0;
  assign result_o[36] = 1'b0;
  assign result_o[37] = 1'b0;
  assign result_o[38] = 1'b0;
  assign result_o[39] = 1'b0;
  assign result_o[40] = 1'b0;
  assign result_o[41] = 1'b0;
  assign result_o[42] = 1'b0;
  assign result_o[43] = 1'b0;
  assign result_o[44] = 1'b0;
  assign result_o[45] = 1'b0;
  assign result_o[46] = 1'b0;
  assign result_o[47] = 1'b0;
  assign result_o[48] = 1'b0;
  assign result_o[49] = 1'b0;
  assign result_o[50] = 1'b0;
  assign result_o[51] = 1'b0;
  assign result_o[52] = 1'b0;
  assign result_o[53] = 1'b0;
  assign result_o[54] = 1'b0;
  assign result_o[55] = 1'b0;
  assign result_o[56] = 1'b0;
  assign result_o[57] = 1'b0;
  assign result_o[58] = 1'b0;
  assign result_o[59] = 1'b0;
  assign result_o[60] = 1'b0;
  assign result_o[61] = 1'b0;
  assign result_o[62] = 1'b0;
  assign result_o[63] = 1'b0;

endmodule
module bp_be_dcache_lru_encode_ways_p8
(
  lru_i,
  way_id_o
);

  input [6:0] lru_i;
  output [2:0] way_id_o;
  wire [2:0] way_id_o;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
  N22,N23,N24,N25,N26,N27,N28,N29,N30;
  assign N11 = N8 & N9;
  assign N12 = N11 & N10;
  assign N13 = lru_i[3] & N9;
  assign N14 = N13 & N10;
  assign N16 = N15 & lru_i[1];
  assign N17 = N16 & N10;
  assign N18 = lru_i[4] & lru_i[1];
  assign N19 = N18 & N10;
  assign N22 = N20 & N21;
  assign N23 = N22 & lru_i[0];
  assign N24 = lru_i[5] & N21;
  assign N25 = N24 & lru_i[0];
  assign N27 = N26 & lru_i[2];
  assign N28 = N27 & lru_i[0];
  assign N29 = lru_i[6] & lru_i[2];
  assign N30 = N29 & lru_i[0];
  assign way_id_o = (N0)? { 1'b0, 1'b0, 1'b0 } :
                    (N1)? { 1'b0, 1'b0, 1'b1 } :
                    (N2)? { 1'b0, 1'b1, 1'b0 } :
                    (N3)? { 1'b0, 1'b1, 1'b1 } :
                    (N4)? { 1'b1, 1'b0, 1'b0 } :
                    (N5)? { 1'b1, 1'b0, 1'b1 } :
                    (N6)? { 1'b1, 1'b1, 1'b0 } :
                    (N7)? { 1'b1, 1'b1, 1'b1 } : 1'b0;
  assign N0 = N12;
  assign N1 = N14;
  assign N2 = N17;
  assign N3 = N19;
  assign N4 = N23;
  assign N5 = N25;
  assign N6 = N28;
  assign N7 = N30;
  assign N8 = ~lru_i[3];
  assign N9 = ~lru_i[1];
  assign N10 = ~lru_i[0];
  assign N15 = ~lru_i[4];
  assign N20 = ~lru_i[5];
  assign N21 = ~lru_i[2];
  assign N26 = ~lru_i[6];

endmodule
module bsg_dff_reset_en_width_p1
(
  clk_i,
  reset_i,
  en_i,
  data_i,
  data_o
);

  input [0:0] data_i;
  output [0:0] data_o;
  input clk_i;
  input reset_i;
  input en_i;
  wire N0,N1,N2,N3,N4,N5,N6;
  reg [0:0] data_o;
  assign N3 = (N0)? 1'b1 :
              (N6)? 1'b1 :
              (N2)? 1'b0 : 1'b0;
  assign N0 = reset_i;
  assign N4 = (N0)? 1'b0 :
              (N6)? data_i[0] : 1'b0;
  assign N1 = en_i | reset_i;
  assign N2 = ~N1;
  assign N5 = ~reset_i;
  assign N6 = en_i & N5;

  always @(posedge clk_i) begin
    if(N3) begin
      { data_o[0:0] } <= { N4 };
    end
  end


endmodule
module bsg_decode_num_out_p2
(
  i,
  o
);

  input [0:0] i;
  output [1:0] o;
  wire [1:0] o;
  assign o = { 1'b0, 1'b1 } << i[0];

endmodule
module bsg_dff_width_p1890
(
  clk_i,
  data_i,
  data_o
);

  input [1889:0] data_i;
  output [1889:0] data_o;
  input clk_i;
  reg [1889:0] data_o;

  always @(posedge clk_i) begin
    if(1'b1) begin
      { data_o[1889:0] } <= { data_i[1889:0] };
    end
  end


endmodule
module bsg_dff_width_p35
(
  clk_i,
  data_i,
  data_o
);

  input [34:0] data_i;
  output [34:0] data_o;
  input clk_i;
  reg [34:0] data_o;

  always @(posedge clk_i) begin
    if(1'b1) begin
      { data_o[34:0] } <= { data_i[34:0] };
    end
  end


endmodule
module bp_be_dcache_lru_decode_ways_p8
(
  way_id_i,
  data_o,
  mask_o
);

  input [2:0] way_id_i;
  output [6:0] data_o;
  output [6:0] mask_o;
  wire [6:0] data_o,mask_o;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
  N22,N23,N24,N25,N26,N27,N28,N29,N30;
  assign mask_o[0] = 1'b1;
  assign N11 = N8 & N9;
  assign N12 = N11 & N10;
  assign N13 = way_id_i[2] | way_id_i[1];
  assign N14 = N13 | N10;
  assign N16 = way_id_i[2] | N9;
  assign N17 = N16 | way_id_i[0];
  assign N19 = N16 | N10;
  assign N21 = N8 | way_id_i[1];
  assign N22 = N21 | way_id_i[0];
  assign N24 = N21 | N10;
  assign N26 = N8 | N9;
  assign N27 = N26 | way_id_i[0];
  assign N29 = way_id_i[2] & way_id_i[1];
  assign N30 = N29 & way_id_i[0];
  assign data_o = (N0)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1 } :
                  (N1)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 } :
                  (N2)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b1 } :
                  (N3)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
                  (N4)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
                  (N5)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
                  (N6)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
                  (N7)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
  assign N0 = N12;
  assign N1 = N15;
  assign N2 = N18;
  assign N3 = N20;
  assign N4 = N23;
  assign N5 = N25;
  assign N6 = N28;
  assign N7 = N30;
  assign mask_o[6:1] = (N0)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1 } :
                       (N1)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1 } :
                       (N2)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1 } :
                       (N3)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1 } :
                       (N4)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0 } :
                       (N5)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0 } :
                       (N6)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } :
                       (N7)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } : 1'b0;
  assign N8 = ~way_id_i[2];
  assign N9 = ~way_id_i[1];
  assign N10 = ~way_id_i[0];
  assign N15 = ~N14;
  assign N18 = ~N17;
  assign N20 = ~N19;
  assign N23 = ~N22;
  assign N25 = ~N24;
  assign N28 = ~N27;

endmodule
module bsg_dff_reset_en_64_80000124
(
  clk_i,
  reset_i,
  en_i,
  data_i,
  data_o
);

  input [63:0] data_i;
  output [63:0] data_o;
  input clk_i;
  input reset_i;
  input en_i;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
  N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
  N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
  N62,N63,N64,N65,N66,N67,N68,N69;
  reg [63:0] data_o;
  assign N3 = (N0)? 1'b1 :
              (N69)? 1'b1 :
              (N2)? 1'b0 : 1'b0;
  assign N0 = reset_i;
  assign { N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
                                                                                                                                                                                                                                                                                                                                        (N69)? data_i : 1'b0;
  assign N1 = en_i | reset_i;
  assign N2 = ~N1;
  assign N68 = ~reset_i;
  assign N69 = en_i & N68;

  always @(posedge clk_i) begin
    if(N3) begin
      { data_o[63:0] } <= { N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4 };
    end
  end


endmodule
module bp_be_pipe_mul
(
  clk_i,
  reset_i,
  decode_i,
  rs1_i,
  rs2_i,
  exc_i,
  result_o
);

  input [42:0] decode_i;
  input [63:0] rs1_i;
  input [63:0] rs2_i;
  input [6:0] exc_i;
  output [63:0] result_o;
  input clk_i;
  input reset_i;
  wire [63:0] result_o;
  assign result_o[0] = 1'b0;
  assign result_o[1] = 1'b0;
  assign result_o[2] = 1'b0;
  assign result_o[3] = 1'b0;
  assign result_o[4] = 1'b0;
  assign result_o[5] = 1'b0;
  assign result_o[6] = 1'b0;
  assign result_o[7] = 1'b0;
  assign result_o[8] = 1'b0;
  assign result_o[9] = 1'b0;
  assign result_o[10] = 1'b0;
  assign result_o[11] = 1'b0;
  assign result_o[12] = 1'b0;
  assign result_o[13] = 1'b0;
  assign result_o[14] = 1'b0;
  assign result_o[15] = 1'b0;
  assign result_o[16] = 1'b0;
  assign result_o[17] = 1'b0;
  assign result_o[18] = 1'b0;
  assign result_o[19] = 1'b0;
  assign result_o[20] = 1'b0;
  assign result_o[21] = 1'b0;
  assign result_o[22] = 1'b0;
  assign result_o[23] = 1'b0;
  assign result_o[24] = 1'b0;
  assign result_o[25] = 1'b0;
  assign result_o[26] = 1'b0;
  assign result_o[27] = 1'b0;
  assign result_o[28] = 1'b0;
  assign result_o[29] = 1'b0;
  assign result_o[30] = 1'b0;
  assign result_o[31] = 1'b0;
  assign result_o[32] = 1'b0;
  assign result_o[33] = 1'b0;
  assign result_o[34] = 1'b0;
  assign result_o[35] = 1'b0;
  assign result_o[36] = 1'b0;
  assign result_o[37] = 1'b0;
  assign result_o[38] = 1'b0;
  assign result_o[39] = 1'b0;
  assign result_o[40] = 1'b0;
  assign result_o[41] = 1'b0;
  assign result_o[42] = 1'b0;
  assign result_o[43] = 1'b0;
  assign result_o[44] = 1'b0;
  assign result_o[45] = 1'b0;
  assign result_o[46] = 1'b0;
  assign result_o[47] = 1'b0;
  assign result_o[48] = 1'b0;
  assign result_o[49] = 1'b0;
  assign result_o[50] = 1'b0;
  assign result_o[51] = 1'b0;
  assign result_o[52] = 1'b0;
  assign result_o[53] = 1'b0;
  assign result_o[54] = 1'b0;
  assign result_o[55] = 1'b0;
  assign result_o[56] = 1'b0;
  assign result_o[57] = 1'b0;
  assign result_o[58] = 1'b0;
  assign result_o[59] = 1'b0;
  assign result_o[60] = 1'b0;
  assign result_o[61] = 1'b0;
  assign result_o[62] = 1'b0;
  assign result_o[63] = 1'b0;

endmodule