module axi_mcb_b_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
                    // Width of ID signals.
                    // Range: >= 1.
  parameter integer C_ID_WIDTH                = 4 ,
                    // Enforces strict checking across all MCB ports for 
                    // write data coherency.  This will ensure no race 
                    // conditions will exist between the BRESP and any 
                    // other read/write command on a different MCB port.  
                    // Not necessary for single port MCB operation.
                    // Range: 0, 1
  parameter integer C_STRICT_COHERENCY        = 0
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations     
///////////////////////////////////////////////////////////////////////////////
  input  wire                                 clk,
  input  wire                                 reset,

  // AXI signals
  output wire [C_ID_WIDTH-1:0]                bid,
  output wire [1:0]                           bresp,
  output wire                                 bvalid,
  input  wire                                 bready,

  // Signals to/from the axi_mcb_aw_channel modules
  input  wire                                 b_push,
  input  wire [C_ID_WIDTH-1:0]                b_awid,
  output wire                                 b_full,

  // MCB signals
  // Signal from MCB indicating FIFO underrun or FIFO error, not used.
  input  wire                                 mcb_error,
  // Signal from MCB indicating either cmd fifo  is empty
  input  wire                                 mcb_cmd_empty,
  // Signal from MCB indicating either cmd fifo is full  
  input  wire                                 mcb_cmd_full, 
  // Signal from MCB indicating either wr  fifo  is empty
  input  wire                                 mcb_wr_empty

);

////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// FIFO settings
localparam P_WIDTH  = C_ID_WIDTH;
localparam P_DEPTH  = 4;
localparam P_AWIDTH = 2;
// AXI protocol responses:
localparam P_OKAY   = 2'b00;
localparam P_EXOKAY = 2'b01;
localparam P_SLVERR = 2'b10;
localparam P_DECERR = 2'b11;

////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg                     bvalid_i;
wire [C_ID_WIDTH-1:0]   bid_i;
wire                    bhandshake;
wire                    empty;
wire                    mcb_cmd_is_done;

////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////

// assign AXI outputs
assign bid        = bid_i;
assign bresp      = P_OKAY;
assign bvalid     = bvalid_i;
assign bhandshake = bvalid & bready;
assign mcb_cmd_is_done = mcb_cmd_empty | mcb_wr_empty | (~mcb_cmd_full  & b_full);

// Register output of bvalid
always @(posedge clk) begin
  if (reset | bhandshake) begin
    bvalid_i <= 1'b0;
  end else if (~empty & ((C_STRICT_COHERENCY == 0) | mcb_cmd_is_done)) begin
    bvalid_i <= 1'b1;
  end
end



axi_mcb_simple_fifo #(
  .C_WIDTH                  (P_WIDTH),
  .C_AWIDTH                 (P_AWIDTH),
  .C_DEPTH                  (P_DEPTH)
)
bid_fifo_0
(
  .clk     ( clk        ) ,
  .rst     ( reset      ) ,
  .wr_en   ( b_push     ) ,
  .rd_en   ( bhandshake ) ,
  .din     ( b_awid     ) ,
  .dout    ( bid_i      ) ,
  .a_full  (            ) ,
  .full    ( b_full     ) ,
  .a_empty (            ) ,
  .empty   ( empty      ) 
);

endmodule