dakies/OSS_Verilog huggingface dataset:
module testbench_shift_reg
#(parameter DATA_WIDTH=8,
parameter LENGTH=4);

reg [DATA_WIDTH*LENGTH-1:0] parameters_test;
reg [DATA_WIDTH-1:0] inputs_test;
wire [DATA_WIDTH*LENGTH-1:0] data_test;
wire [DATA_WIDTH-1:0] outputs_test;
reg [1:0] control;
reg clk, reset_n;

shift_reg #(.DATA_WIDTH(DATA_WIDTH), .LENGTH(LENGTH)) shift_register
(
.clock(clk),
.reset_n(reset_n),
.ctrl_code(control),
.data_in(parameters_test),
.data_read(outputs_test),
.data_write(inputs_test),
.data_out(data_test)
);

initial $dumpvars;

initial begin
clk = 0;
forever #10 clk=!clk;
end

integer ii;

initial
begin
reset_n=0; control=0;
#80; reset_n=1;
#20;
for (ii=0; ii<LENGTH; ii=ii+1) begin
parameters_test[DATA_WIDTH*ii +: DATA_WIDTH] = ii+1;
end
control=1;
#20; control=3; #80; control=2; inputs_test=5; #20; inputs_test=6; #20; inputs_test=7; #20; control=0; #20; control=3; #80;
end
endmodule
module testbench_wrapper
#(parameter DATA_WIDTH=16,
parameter ARRAY_W=10, //j
parameter ARRAY_L=784, //i
parameter CLOCK_DIVIDE=2);

reg clk, reset_n, param_load, start_comp;
wire [7:0] hex_output;

sys_array_wrapper #(.DATA_WIDTH(DATA_WIDTH), .ARRAY_W(ARRAY_W), .ARRAY_L(ARRAY_L), .CLOCK_DIVIDE(CLOCK_DIVIDE)) wrappper
(
.clk(clk),
.reset_n(reset_n),
.load_params(param_load),
.start_comp(start_comp),
.hex_connect(hex_output)
);

initial $dumpvars;

initial begin
clk = 0;
forever #10 clk=!clk;
end

initial
begin
reset_n=0; param_load = 0; start_comp = 0;
#80; reset_n=1;
#20;
param_load = 1;
#20; param_load = 0; #10; start_comp = 1; #20; start_comp = 0; #100;
end
endmodule
module testbench_sum_nmax
#(parameter DATA_WIDTH=8,
parameter LENGTH=10);

reg [2*DATA_WIDTH*LENGTH-1:0] inputs_test;
wire [LENGTH-1:0] outputs_test;
reg [DATA_WIDTH*LENGTH-1:0] biases_test;
reg clk, reset_n, ready;

sum_and_max #(.DATA_WIDTH(DATA_WIDTH), .LENGTH(LENGTH)) dut
(
.clk(clk),
.reset_n(reset_n),
.ready(ready),
.input_data(inputs_test),
.biases(biases_test),
.maxi(outputs_test)
);

initial $dumpvars;

initial begin
clk = 0;
forever #10 clk=!clk;
end

integer ii;

initial
begin
reset_n=0; ready=0;
#80; reset_n=1;
#20;
for (ii=0; ii<LENGTH; ii=ii+1) begin
inputs_test[2*DATA_WIDTH*ii +: 2*DATA_WIDTH] = ii+1;
biases_test[DATA_WIDTH*ii +: DATA_WIDTH] = ii-1;
end
ready=1; #20;
for (ii=0; ii<LENGTH; ii=ii+1) begin
inputs_test[2*DATA_WIDTH*ii +: 2*DATA_WIDTH] = ii+2;
end
#20;
for (ii=0; ii<LENGTH; ii=ii+1) begin
inputs_test[2*DATA_WIDTH*ii +: 2*DATA_WIDTH] = ii-2;
end
#80;
end
endmodule
module testbench_signed_cmp;

reg clk;
reg [15:0] a,b;
wire [15:0] less;

signed_cmp comparator
(
.clk(clk),
.a(a),
.b(b),
.less(less)
);

initial $dumpvars;

initial begin
clk = 0;
forever #10 clk=!clk;
end

initial
begin
a <= 16'h0012; b <= 16'h0014; #40;
a <= 16'hffd2; b <= 16'h0352; #20;
end

endmodule
module pmod_als
#(
    parameter QUERY_DELAY = 40
)
(
    input             clk,
    input             rst_n,
    output reg        cs,
    output            sck,
    input             sdo,
    output reg  [7:0] value
);

    localparam  S_IDLE       = 0,
                S_PREFIX     = 1,
                S_DATA       = 2,
                S_POSTFIX    = 3;

    localparam  IDLE_SIZE    = QUERY_DELAY,
                PREFIX_SIZE  = 2,
                DATA_SIZE    = 7,
                POSTFIX_SIZE = 4;

    // sck clock divider
    wire sck_edge;
    sck_clk_divider scd
    (
        .clk        ( clk      ),
        .rst_n      ( rst_n    ),
        .sck        ( sck      ),
        .sck_edge   ( sck_edge )
    );

    // State hold registers
    reg  [ 1:0] State;
    reg  [23:0] cnt;
    reg  [ 7:0] buffer;

    // Next state determining
    always @ (posedge clk or negedge rst_n)
        if(~rst_n) begin
            State  <= S_IDLE;
            cnt    <= 24'b0;
            buffer <= 8'b0;
            value  <= 8'b0;
            cs     <= 1'b1;
            end
        else begin
            if (sck_edge)
                case(State) 
                    S_IDLE    : begin 
                                    if(cnt == IDLE_SIZE) begin
                                        State <= S_PREFIX;
                                        cs <= 1'b0;
                                    end
                                    cnt <= (cnt == IDLE_SIZE) ? 0 : cnt + 1;
                                end
                    S_PREFIX  : begin 
                                    if(cnt == PREFIX_SIZE) State <= S_DATA;
                                    cnt <= (cnt == PREFIX_SIZE) ? 0 : cnt + 1;
                                end
                    S_DATA    : begin 
                                    if(cnt == DATA_SIZE) State <= S_POSTFIX;
                                    cnt <= (cnt == DATA_SIZE) ? 0 : cnt + 1;
                                    buffer <= { buffer[6:0], sdo };
                                end
                    S_POSTFIX : begin 
                                    if(cnt == POSTFIX_SIZE) begin
                                        State <= S_IDLE;
                                        cs <= 1'b1;
                                    end
                                    cnt <= (cnt == POSTFIX_SIZE) ? 0 : cnt + 1;
                                    value <= buffer;
                                end
                endcase
        end

endmodule
module sck_clk_divider
(
    input       clk,
    input       rst_n,
    output  reg sck,
    output  reg sck_edge
);
    localparam  S_DOWN = 0,
                S_EDGE = 1,
                S_UP   = 2;

    localparam  DOWN_SIZE = 7,
                UP_SIZE = DOWN_SIZE - 1; // because 1 cycle of S_EDGE;

    // State hold registers
    reg  [1:0] State;
    reg  [2:0] cnt;

    // Next state determining
    always @ (posedge clk or negedge rst_n)
        if(~rst_n) begin
            State  <= S_DOWN;
            cnt    <= 3'b0;
            end
        else begin
            case(State) 
                S_DOWN : begin 
                            if(cnt == DOWN_SIZE) begin
                                State <= S_EDGE;
                                sck_edge <= 1'b1;
                                sck <= 1'b1;
                            end
                            cnt <= (cnt == DOWN_SIZE) ? 0 : cnt + 1;
                         end
                S_EDGE : begin 
                            State <= S_UP; 
                            cnt <= 0;
                            sck_edge <= 1'b0;
                         end
                S_UP   : begin 
                            if(cnt == UP_SIZE) begin
                                State <= S_DOWN;
                                sck <= 1'b0;
                            end
                            cnt <= (cnt == UP_SIZE) ? 0 : cnt + 1;
                         end
            endcase
        end

endmodule
module register
#(
    parameter SIZE = 32
)
(
    input                       clk,
    input                       rst,
    input      [ SIZE - 1 : 0 ] d,
    output reg [ SIZE - 1 : 0 ] q
);
    always @ (posedge clk or negedge rst)
        if(~rst)
            q <= { SIZE { 1'b0}};
        else
            q <= d;
endmodule
module register_we
#(
    parameter SIZE = 32
)
(
    input                       clk,
    input                       rst,
    input                       we,
    input      [ SIZE - 1 : 0 ] d,
    output reg [ SIZE - 1 : 0 ] q
);
    always @ (posedge clk or negedge rst)
        if(~rst)
            q <= { SIZE { 1'b0}};
        else
            if(we) q <= d;
endmodule
module pmod_als
#(
    parameter QUERY_DELAY = 40
)
(
    input             clk,
    input             rst_n,
    output            cs,
    output            sck,
    input             sdo,
    output      [7:0] value
);

    localparam  S_IDLE       = 0,
                S_PREFIX     = 1,
                S_DATA       = 2,
                S_POSTFIX    = 3;

    localparam  IDLE_SIZE    = QUERY_DELAY,
                PREFIX_SIZE  = 2,
                DATA_SIZE    = 7,
                POSTFIX_SIZE = 4;

    // sck clock divider
    wire sck_edge;
    sck_clk_divider scd
    (
        .clk        ( clk      ),
        .rst_n      ( rst_n    ),
        .sck        ( sck      ),
        .sck_edge   ( sck_edge )
    );

    // State hold registers
    wire [1:0] State;
    reg  [1:0] Next;
    register_we #(.SIZE(2)) r_state(clk, rst_n, sck_edge, Next, State);

    wire [23:0] cnt;
    reg  [23:0] cntNext;
    register_we #(.SIZE(24)) r_cnt(clk, rst_n, sck_edge, cntNext, cnt);

    wire [7:0] buffer;
    reg  [7:0] bufferNext;
    register_we #(.SIZE(8)) r_buffer(clk, rst_n, sck_edge, bufferNext, buffer);

    reg  [7:0] valueNext;
    register_we #(.SIZE(8)) r_value(clk, rst_n, sck_edge, valueNext, value);

    // Next state determining
    always @(*) begin
        Next = State;
        case(State)
            S_IDLE    : if(cnt == IDLE_SIZE)    Next = S_PREFIX;
            S_PREFIX  : if(cnt == PREFIX_SIZE)  Next = S_DATA;
            S_DATA    : if(cnt == DATA_SIZE)    Next = S_POSTFIX;
            S_POSTFIX : if(cnt == POSTFIX_SIZE) Next = S_IDLE;
        endcase
    end

    always @(*) begin
        cntNext = cnt + 1;
        case(State)
            S_IDLE    : if (cnt == IDLE_SIZE)    cntNext = 0;
            S_PREFIX  : if (cnt == PREFIX_SIZE)  cntNext = 0;
            S_DATA    : if (cnt == DATA_SIZE)    cntNext = 0;
            S_POSTFIX : if (cnt == POSTFIX_SIZE) cntNext = 0;
        endcase
    end

    always @(*) begin
        bufferNext = buffer;
        valueNext = value;
        case(State)
            S_DATA    : bufferNext = { bufferNext[6:0], sdo };
            S_POSTFIX : valueNext = bufferNext;
        endcase
    end

    // buffered output
    wire csNext = (Next == S_IDLE);
    register_we #(.SIZE(1)) r_cs(clk, rst_n, sck_edge, csNext, cs);

endmodule
module sck_clk_divider
(
    input       clk,
    input       rst_n,
    output      sck,
    output      sck_edge
);
    wire [3:0] cnt;
    wire [3:0] cntNext = cnt + 1;
    register #(.SIZE(4)) r_cnt(clk, rst_n, cntNext, cnt);

    assign sck = cnt[3];
    assign sck_edge = (cnt == 4'b1000);

endmodule
module pmod_als
#(
    parameter QUERY_DELAY = 40
)
(
    input             clk,
    input             rst_n,
    output            cs,
    output            sck,
    input             sdo,
    output      [7:0] value
);

    localparam  S_IDLE       = 0,
                S_PREFIX     = 1,
                S_DATA       = 2,
                S_POSTFIX    = 3;

    localparam  IDLE_SIZE    = QUERY_DELAY,
                PREFIX_SIZE  = 2,
                DATA_SIZE    = 7,
                POSTFIX_SIZE = 4;

    // sck clock divider
    wire sck_edge;
    sck_clk_divider scd
    (
        .clk        ( clk      ),
        .rst_n      ( rst_n    ),
        .sck        ( sck      ),
        .sck_edge   ( sck_edge )
    );

    // State hold registers
    wire [1:0] State;
    reg  [1:0] Next;
    register_we #(.SIZE(2)) r_state(clk, rst_n, sck_edge, Next, State);

    wire [23:0] cnt;
    reg  [23:0] cntNext;
    register_we #(.SIZE(24)) r_cnt(clk, rst_n, sck_edge, cntNext, cnt);

    wire [7:0] buffer;
    reg  [7:0] bufferNext;
    register_we #(.SIZE(8)) r_buffer(clk, rst_n, sck_edge, bufferNext, buffer);

    reg  [7:0] valueNext;
    register_we #(.SIZE(8)) r_value(clk, rst_n, sck_edge, valueNext, value);

    // Next state determining
    always @(*) begin
        Next = State;
        case(State)
            S_IDLE    : if(cnt == IDLE_SIZE)    Next = S_PREFIX;
            S_PREFIX  : if(cnt == PREFIX_SIZE)  Next = S_DATA;
            S_DATA    : if(cnt == DATA_SIZE)    Next = S_POSTFIX;
            S_POSTFIX : if(cnt == POSTFIX_SIZE) Next = S_IDLE;
        endcase
    end

    always @(*) begin
        cntNext = cnt + 1;
        case(State)
            S_IDLE    : if (cnt == IDLE_SIZE)    cntNext = 0;
            S_PREFIX  : if (cnt == PREFIX_SIZE)  cntNext = 0;
            S_DATA    : if (cnt == DATA_SIZE)    cntNext = 0;
            S_POSTFIX : if (cnt == POSTFIX_SIZE) cntNext = 0;
        endcase
    end

    always @(*) begin
        bufferNext = buffer;
        valueNext = value;
        case(State)
            S_DATA    : bufferNext = { bufferNext[6:0], sdo };
            S_POSTFIX : valueNext = bufferNext;
        endcase
    end

    // output
    assign cs = (State == S_IDLE);

endmodule
module sck_clk_divider
(
    input       clk,
    input       rst_n,
    output      sck,
    output      sck_edge
);
    localparam  S_DOWN = 0,
                S_EDGE = 1,
                S_UP   = 2;

    localparam  DOWN_SIZE = 7,
                UP_SIZE = DOWN_SIZE - 1; // because 1 cycle of S_EDGE;

    // State hold registers
    wire [1:0] State;
    reg  [1:0] Next;
    register #(.SIZE(2)) r_state(clk, rst_n, Next, State);

    wire [2:0] cnt;
    reg  [2:0] cntNext;
    register #(.SIZE(3)) r_cnt(clk, rst_n, cntNext, cnt);

    // Next state determining
    always @(*) begin
        Next = State;
        case(State)
            S_DOWN  : if(cnt == DOWN_SIZE) Next = S_EDGE;
            S_EDGE  : Next = S_UP;
            S_UP    : if(cnt == UP_SIZE) Next = S_DOWN;
        endcase
    end

    always @(*) begin
        cntNext = cnt + 1;
        case(State)
            S_DOWN  : if (cnt == DOWN_SIZE) cntNext = 0;
            S_EDGE  : cntNext = 0;
            S_UP    : if (cnt == UP_SIZE) cntNext = 0;
        endcase
    end

    // Output value
    assign sck      = (State != S_DOWN);
    assign sck_edge = (State == S_EDGE);

endmodule
module pmod_als
#(
    parameter CNTSIZE = 11
)
(
    input             clk,
    input             rst_n,
    output            cs,
    output            sck,
    input             sdo,
    output      [7:0] value
);
    wire [ CNTSIZE - 1:0] cnt;
    wire [ CNTSIZE - 1:0] cntNext = cnt + 1;
    register #(.SIZE(CNTSIZE)) r_counter(clk, rst_n, cntNext, cnt);

    assign sck = cnt [3];
    assign cs  = ~(cnt[CNTSIZE - 1:8] == { (CNTSIZE - 8) { 1'b1 }});

    wire sampleBit = ( cs == 1'b0 && cnt [3:0] == 4'b1000     );
    wire valueDone = ( cs == 1'b0 && cnt [7:0] == 8'b10101001 );

    wire [7:0] shift;
    wire [7:0] shiftNext = (shift << 1) | sdo;
    register_we #(.SIZE(8)) r_shift(clk, rst_n, sampleBit, shiftNext, shift);

    wire [7:0] valueNext = shift;
    register_we #(.SIZE(8))  r_value(clk, rst_n, valueDone, valueNext, value);

endmodule
module pmod_als
#(
    parameter QUERY_DELAY = 40
)
(
    input             clk,
    input             rst_n,
    output            cs,
    output            sck,
    input             sdo,
    output reg  [7:0] value
);

    localparam  S_IDLE       = 0,
                S_PREFIX     = 1,
                S_DATA       = 2,
                S_POSTFIX    = 3;

    localparam  IDLE_SIZE    = QUERY_DELAY,
                PREFIX_SIZE  = 2,
                DATA_SIZE    = 7,
                POSTFIX_SIZE = 4;

    // sck clock divider
    wire sck_edge;
    sck_clk_divider scd
    (
        .clk        ( clk      ),
        .rst_n      ( rst_n    ),
        .sck        ( sck      ),
        .sck_edge   ( sck_edge )
    );

    // State hold registers
    reg  [ 1:0] State;
    reg  [23:0] cnt;
    reg  [ 7:0] buffer;

    // State hold registers next value
    reg  [ 1:0] Next;
    reg  [23:0] cntNext;
    reg  [ 7:0] bufferNext;
    reg  [ 7:0] valueNext;

    // Next value to state on every clock
    always @ (posedge clk or negedge rst_n)
        if(~rst_n) begin
            State  <= S_IDLE;
            cnt    <= 24'b0;
            buffer <= 8'b0;
            value  <= 8'b0;
            end
        else begin
            State  <= Next;
            cnt    <= cntNext;
            buffer <= bufferNext;
            value  <= valueNext;
        end

    // Next state determining
    always @(*) begin
        Next = State;
        if(sck_edge)
            case(State)
                S_IDLE    : if(cnt == IDLE_SIZE)    Next = S_PREFIX;
                S_PREFIX  : if(cnt == PREFIX_SIZE)  Next = S_DATA;
                S_DATA    : if(cnt == DATA_SIZE)    Next = S_POSTFIX;
                S_POSTFIX : if(cnt == POSTFIX_SIZE) Next = S_IDLE;
            endcase
    end

    always @(*) begin
        cntNext = cnt;
        if(sck_edge) begin
            cntNext = cnt + 1;
            case(State)
                S_IDLE    : if (cnt == IDLE_SIZE)    cntNext = 0;
                S_PREFIX  : if (cnt == PREFIX_SIZE)  cntNext = 0;
                S_DATA    : if (cnt == DATA_SIZE)    cntNext = 0;
                S_POSTFIX : if (cnt == POSTFIX_SIZE) cntNext = 0;
            endcase
        end
    end

    always @(*) begin
        bufferNext = buffer;
        valueNext = value;
        if(sck_edge)
            case(State)
                S_DATA    : bufferNext = { bufferNext[6:0], sdo };
                S_POSTFIX : valueNext = bufferNext;
            endcase
    end

    // output
    assign cs = (State == S_IDLE);

endmodule
module sck_clk_divider
(
    input       clk,
    input       rst_n,
    output      sck,
    output      sck_edge
);
    localparam  S_DOWN = 0,
                S_EDGE = 1,
                S_UP   = 2;

    localparam  DOWN_SIZE = 7,
                UP_SIZE = DOWN_SIZE - 1; // because 1 cycle of S_EDGE;

    // State hold registers
    reg  [1:0] State;
    reg  [2:0] cnt;

    // State hold registers next value
    reg  [1:0] Next;
    reg  [2:0] cntNext;

    always @ (posedge clk or negedge rst_n)
        if(~rst_n) begin
            State  <= S_DOWN;
            cnt    <= 3'b0;
            end
        else begin
            State  <= Next;
            cnt    <= cntNext;
        end

    // Next state determining
    always @(*) begin
        Next = State;
        case(State)
            S_DOWN  : if(cnt == DOWN_SIZE) Next = S_EDGE;
            S_EDGE  : Next = S_UP;
            S_UP    : if(cnt == UP_SIZE) Next = S_DOWN;
        endcase
    end

    always @(*) begin
        cntNext = cnt + 1;
        case(State)
            S_DOWN  : if (cnt == DOWN_SIZE) cntNext = 0;
            S_EDGE  : cntNext = 0;
            S_UP    : if (cnt == UP_SIZE) cntNext = 0;
        endcase
    end

    // Output value
    assign sck      = (State != S_DOWN);
    assign sck_edge = (State == S_EDGE);

endmodule
module sck_clk_divider
(
    input       clk,
    input       rst_n,
    output      sck,
    output      sck_edge
);
    localparam  S_DOWN = 0,
                S_EDGE = 1,
                S_UP   = 2;

    localparam  DOWN_SIZE = 7,
                UP_SIZE = DOWN_SIZE - 1; // because 1 cycle of S_EDGE;

    // State hold registers
    wire [1:0] State;
    reg  [1:0] Next;
    register #(.SIZE(2)) r_state(clk, rst_n, Next, State);

    wire [2:0] cnt;
    reg  [2:0] cntNext;
    register #(.SIZE(3)) r_cnt(clk, rst_n, cntNext, cnt);

    // Next state determining
    always @(*) begin
        Next = State;
        case(State)
            S_DOWN  : if(cnt == DOWN_SIZE) Next = S_EDGE;
            S_EDGE  : Next = S_UP;
            S_UP    : if(cnt == UP_SIZE) Next = S_DOWN;
        endcase
    end

    always @(*) begin
        cntNext = cnt + 1;
        case(State)
            S_DOWN  : if (cnt == DOWN_SIZE) cntNext = 0;
            S_EDGE  : cntNext = 0;
            S_UP    : if (cnt == UP_SIZE) cntNext = 0;
        endcase
    end

    // output
    assign sck_edge = (State == S_EDGE);

    // buffered output
    wire sckNext = (Next != S_DOWN);
    register #(.SIZE(1)) r_sck(clk, rst_n, sckNext, sck);

endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    pmod_als pmod_als (KEY[0], KEY[3], LEDR[8], LEDR[9], SW[0], LEDR[7:0]);

endmodule
module de10_lite
(
    input               ADC_CLK_10,
    input               MAX10_CLK1_50,
    input               MAX10_CLK2_50,

    output  [  7:0 ]    HEX0,
    output  [  7:0 ]    HEX1,
    output  [  7:0 ]    HEX2,
    output  [  7:0 ]    HEX3,
    output  [  7:0 ]    HEX4,
    output  [  7:0 ]    HEX5,

    input   [  1:0 ]    KEY,
    output  [  9:0 ]    LEDR,
    input   [  9:0 ]    SW,
    inout   [ 35:0 ]    GPIO
);

    // SPI bus
    wire        cs;
    wire        sck;
    wire        sdo;

    // ALS connection table
    // PIN     GPIO     ALS   direction
    // ==== ========== ===== ===========
    //  29   VCC        VCC
    //  31   GPIO[26]   GND   output
    //  33   GPIO[28]   SCK   output
    //  35   GPIO[30]   SDO   input
    //  37   GPIO[32]   NC    hiZ
    //  39   GPIO[34]   CS    output

    assign GPIO[26] = 1'b0;
    assign GPIO[28] = sck;
    assign sdo      = GPIO[30];
    assign GPIO[32] = 1'bz;
    assign GPIO[34] = cs;

    // global signals
    wire clk   = MAX10_CLK1_50;
    wire rst_n = KEY[0];

    // sensor value
    wire  [7:0] value;

    //sensor
    pmod_als 
        #( .QUERY_DELAY(1 << 21) )
    als
    (
        .clk    ( clk   ),
        .rst_n  ( rst_n ),
        .cs     ( cs    ),
        .sck    ( sck   ),
        .sdo    ( sdo   ),
        .value  ( value )
    );

    //outputs
    assign LEDR[0]   = ~cs;
    assign LEDR[9:1] = 8'b0;

    wire [ 31:0 ] h7segment = { 16'b0, value };

    assign HEX0 [7] = 1'b1;
    assign HEX1 [7] = 1'b1;
    assign HEX2 [7] = 1'b1;
    assign HEX3 [7] = 1'b1;
    assign HEX4 [7] = 1'b1;
    assign HEX5 [7] = 1'b1;

    hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
    hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
    hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
    hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
    hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
    hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );

endmodule
module hex_display
(
    input      [3:0] digit,
    output reg [6:0] seven_segments
);

    always @*
        case (digit)
        'h0: seven_segments = 'b1000000;  // a b c d e f g
        'h1: seven_segments = 'b1111001;
        'h2: seven_segments = 'b0100100;  //   --a--
        'h3: seven_segments = 'b0110000;  //  |     |
        'h4: seven_segments = 'b0011001;  //  f     b
        'h5: seven_segments = 'b0010010;  //  |     |
        'h6: seven_segments = 'b0000010;  //   --g--
        'h7: seven_segments = 'b1111000;  //  |     |
        'h8: seven_segments = 'b0000000;  //  e     c
        'h9: seven_segments = 'b0011000;  //  |     |
        'ha: seven_segments = 'b0001000;  //   --d-- 
        'hb: seven_segments = 'b0000011;
        'hc: seven_segments = 'b1000110;
        'hd: seven_segments = 'b0100001;
        'he: seven_segments = 'b0000110;
        'hf: seven_segments = 'b0001110;
        endcase

endmodule
module testbench;

    // simulation options
    parameter Tt     = 20;
    parameter Cycles = 4000;

    // global signals
    reg         clk;
    reg         rst_n;

    // SPI bus
    wire        cs;
    wire        sck;
    wire        sdo;

    // sensor value
    wire  [7:0] value;

    // DUT start
    pmod_als als
    (
        .clk    ( clk   ),
        .rst_n  ( rst_n ),
        .cs     ( cs    ),
        .sck    ( sck   ),
        .sdo    ( sdo   ),
        .value  ( value )
    );
    // DUT end

    // peripheral device stub
    pmod_als_stub stub
    (
        .cs     ( cs    ),
        .sck    ( sck   ),
        .sdo    ( sdo   )
    );

    // simulation init - clock
    initial begin
        clk = 0;
        forever clk = #(Tt/2) ~clk;
    end

    // simulation init - reset
    initial begin
        rst_n   = 0;
        repeat (4)  @(posedge clk);
        rst_n   = 1;
    end

    // simulation duration
    initial begin
        repeat (Cycles)  @(posedge clk);
        $display ("Timeout");
        $stop;
    end

    // simulation output
    initial 
        $monitor("value=%h", value);

    initial 
        $dumpvars;

endmodule
module pmod_als_stub
#(
    parameter value = 8'hAB
)
(
    input             cs,
    input             sck,
    output            sdo
);
    wire [7:0]  tvalue  = value;
    wire [15:0] tpacket = { 3'b0, tvalue, 4'b0, 1'bz };

    reg  [15:0] buffer;
    reg         sdata;

    assign sdo = cs ? 1'bz : sdata;

    always @(negedge sck or posedge cs) begin
        if(!cs)
            { sdata, buffer } <= { buffer, 1'b0 };
        else
            { sdata, buffer } <= { 1'b0, tpacket };
    end

endmodule
module de10_lite
(
    input               ADC_CLK_10,
    input               MAX10_CLK1_50,
    input               MAX10_CLK2_50,

    output  [  7:0 ]    HEX0,
    output  [  7:0 ]    HEX1,
    output  [  7:0 ]    HEX2,
    output  [  7:0 ]    HEX3,
    output  [  7:0 ]    HEX4,
    output  [  7:0 ]    HEX5,

    input   [  1:0 ]    KEY,
    output  [  9:0 ]    LEDR,
    input   [  9:0 ]    SW,
    inout   [ 35:0 ]    GPIO
);

    // SPI bus
    wire        cs;
    wire        sck;
    wire        sdo;

    // ALS connection table
    // PIN     GPIO     ALS   direction
    // ==== ========== ===== ===========
    //  29   VCC        VCC
    //  31   GPIO[26]   GND   output
    //  33   GPIO[28]   SCK   output
    //  35   GPIO[30]   SDO   input
    //  37   GPIO[32]   NC    hiZ
    //  39   GPIO[34]   CS    output

    assign GPIO[26] = 1'b0;
    assign GPIO[28] = sck;
    assign sdo      = GPIO[30];
    assign GPIO[32] = 1'bz;
    assign GPIO[34] = cs;

    // global signals
    wire clk   = MAX10_CLK1_50;
    wire rst_n = KEY[0];

    // sensor value
    wire  [7:0] value;

    //sensor
    pmod_als 
        #( .CNTSIZE(24) )
    als
    (
        .clk    ( clk   ),
        .rst_n  ( rst_n ),
        .cs     ( cs    ),
        .sck    ( sck   ),
        .sdo    ( sdo   ),
        .value  ( value )
    );

    //outputs
    assign LEDR[0]   = ~cs;
    assign LEDR[9:1] = 8'b0;

    wire [ 31:0 ] h7segment = { 16'b0, value };

    assign HEX0 [7] = 1'b1;
    assign HEX1 [7] = 1'b1;
    assign HEX2 [7] = 1'b1;
    assign HEX3 [7] = 1'b1;
    assign HEX4 [7] = 1'b1;
    assign HEX5 [7] = 1'b1;

    hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
    hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
    hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
    hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
    hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
    hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );

endmodule
module lab7_6

#(parameter DATA_WIDTH=8, parameter STACK_SIZE=4)

(
    input  clock,
    input  reset,
    input  push,
    input  pop,

    input  [DATA_WIDTH - 1:0] write_data,
    output reg [DATA_WIDTH - 1:0] read_data
);

    reg [DATA_WIDTH - 1:0] stack [0:STACK_SIZE - 1];
	
	// invert clk button
    wire w_clk = ~ clock;

    integer i;

    always @(posedge w_clk)
    begin
        if (reset)
        begin
            for (i = 0; i < STACK_SIZE; i = i + 1)
                stack [i] <= 0;
        end
        else if (push)
        begin
            for (i = 0; i < STACK_SIZE - 1; i = i + 1)
				    stack [i + 1] <= stack [i];

            stack [0] <= write_data;
        end
        else if (pop)
        begin
            for (i = 0; i < STACK_SIZE - 1; i = i + 1)
                stack [i] <= stack [i + 1];

            stack [STACK_SIZE - 1] <= 0;
	    read_data <= stack [0];
        end
    end

endmodule
module hexto7segment
(
    input      [3:0]               in_hex,
    output reg [6:0]               out_7seg
);

always @in_hex
    case (in_hex)
        4'b0000 :             //Digit 0
            out_7seg = 7'b1000000;
        4'b0001 :            //Digit 1
            out_7seg = 7'b1111001  ;
        4'b0010 :            //Digit 2
            out_7seg = 7'b0100100 ; 
        4'b0011 :             //Digit 3
            out_7seg = 7'b0110000 ;
        4'b0100 :            //Digit 4
            out_7seg = 7'b0011001 ;
        4'b0101 :            //Digit 5
            out_7seg = 7'b0010010 ;  
        4'b0110 :            //Digit 6
            out_7seg = 7'b0000010 ;
        4'b0111 :            //Digit 7
            out_7seg = 7'b1111000;
        4'b1000 :            //Digit 8
            out_7seg = 7'b0000000;
        4'b1001 :            //Digit 9
            out_7seg = 7'b0011000 ;
        4'b1010 :            //Digit A
            out_7seg = 7'b0001000 ; 
        4'b1011 :            //Digit B
            out_7seg = 7'b0000011;
        4'b1100 :            //Digit C
            out_7seg = 7'b1000110 ;
        4'b1101 :            //Digit D
            out_7seg = 7'b0100001 ;
        4'b1110 :            //Digit E
            out_7seg = 7'b0000110 ;
        4'b1111 :            //Digit F
            out_7seg = 7'b0001110 ;
    endcase
endmodule
module dc2
(
   input      [1:0]               a,
   output reg [3:0]               dc_out
);

always @a
    case (a)
        2'b00	:	dc_out = 4'b0001;
        2'b01	:	dc_out = 4'b0010;
        2'b10	:	dc_out = 4'b0100;
        2'b11	:	dc_out = 4'b1000;
    endcase
endmodule
module register
#(
    parameter SIZE = 4
)
(
    input                          ena, 
    input                          clk,
	input                          rst_n,
    input      [SIZE - 1 : 0]      d,
    output reg [SIZE - 1 : 0]      q
);
    always @ (posedge clk or negedge rst_n)
        if (! rst_n)
            q <= {SIZE {1'b0}};
        else if (ena)
            q <= d;
endmodule
module dual_port_RAM
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=4)
(
    input                          we, 
    input                          clk,
    // Read port:
    input      [(DATA_WIDTH-1):0]  data_in,
    input      [(ADDR_WIDTH-1):0]  read_addr, 
    // Write port:
    input      [(ADDR_WIDTH-1):0]  write_addr,
    output reg [(DATA_WIDTH-1):0]  data_out
);
    // Declare the array variable
    reg [DATA_WIDTH-1:0] dp_ram [0:2**ADDR_WIDTH-1];
    
    always @ (posedge clk)
    begin
        // Write
        if (we)
            dp_ram [write_addr] <= data_in;
 
         // Read
        data_out <= dp_ram [read_addr];
    end
endmodule
module lab7_5
#(
	parameter DATA_WIDTH=8, 
	parameter ADDR_WIDTH=4
)
(
    input                          clk,
	input                          rst_n, 
    input      [9:0]               SW,
    output     [7:0]               HEX0,
    output     [7:0]               HEX1,
    output     [7:0]               HEX2,
    output     [7:0]               HEX3,
    output     [7:0]               HEX4,
    output     [7:0]               HEX5
);

	wire       [3:0]               w_we;          //DC output for write enable
	wire	   [(DATA_WIDTH-1):0]  data_in_reg;   //data_in register output
	wire	   [(ADDR_WIDTH-1):0]  read_addr_reg; //read_addr register output
	wire	   [(ADDR_WIDTH-1):0]  write_addr_reg;//write_addr register output
	wire	   [(DATA_WIDTH-1):0]  data_out;      //memory output
	
	dc2 dc2in4 (.a(SW[9:8]), .dc_out(w_we[3:0]));
	assign HEX0[7] = ~w_we[0];
	assign HEX1[7] = ~w_we[0];
	assign HEX2[7] = ~w_we[3];
	assign HEX3[7] = ~w_we[3];
	assign HEX4[7] = ~w_we[1];
	assign HEX5[7] = ~w_we[2];
	
	
	register #(8) register_data_in (.ena(w_we[0]), .clk(clk), .rst_n(rst_n), .d(SW[7:0]), .q(data_in_reg));
	register #(4) register_read_addr (.ena(w_we[1]), .clk(clk), .rst_n(rst_n), .d(SW[3:0]), .q(read_addr_reg));
	register #(4) register_write_addr (.ena(w_we[2]), .clk(clk), .rst_n(rst_n), .d(SW[3:0]), .q(write_addr_reg));
	
	hexto7segment hexto7segment_data_in0 (.in_hex(data_in_reg[3:0]), .out_7seg(HEX0[6:0]));
	hexto7segment hexto7segment_data_in1 (.in_hex(data_in_reg[7:4]), .out_7seg(HEX1[6:0]));
	hexto7segment hexto7segment_data_out0 (.in_hex(data_out[3:0]), .out_7seg(HEX2[6:0]));
	hexto7segment hexto7segment_data_out1 (.in_hex(data_out[7:4]), .out_7seg(HEX3[6:0]));
	hexto7segment hexto7segment_read_addr (.in_hex(read_addr_reg), .out_7seg(HEX4[6:0]));
	hexto7segment hexto7segment_write_addr (.in_hex(write_addr_reg), .out_7seg(HEX5[6:0]));
	
	dual_port_RAM #(8,4) dual_port_RAM 
	(
		.we(w_we[3]), 
		.clk(clk), 
		.data_in(data_in_reg), 
		.read_addr(read_addr_reg),
		.write_addr(write_addr_reg),
		.data_out(data_out)
	);
	
endmodule
module lab7_2
(
	input [3:0] x,
	output reg y
);

	always @* 
	begin
		case(x)
			 'b0000: y<= 0;
			 'b0001: y<= 0;
			 'b0010: y<= 0;
			 'b0011: y<= 0;
 			 'b0100: y<= 0;
			 'b0101: y<= 0;
			 'b0110: y<= 0;
			 'b0111: y<= 0;
			 'b1000: y<= 0;
			 'b1001: y<= 0;
			 'b1010: y<= 0;
			 'b1011: y<= 0;
 			 'b1100: y<= 0;
			 'b1101: y<= 0;
			 'b1110: y<= 0;
			 'b1111: y<= 1;
		endcase
	end

endmodule
module lab7_7

#(
	parameter DATA_WIDTH=8, 
	parameter PTR_WIDTH=2
)

(
    input  clock,
    input  rst_n,
    input  push,
    input  pop,

    input  [DATA_WIDTH - 1:0] write_data,
    output reg [DATA_WIDTH - 1:0] read_data
);

    reg [DATA_WIDTH - 1:0] stack [0:2**PTR_WIDTH - 1];
	reg [PTR_WIDTH - 1:0] pointer;

 
	always @(posedge clock or negedge rst_n) 
	  begin
		if (!rst_n)
			pointer <= {PTR_WIDTH {1'b0}};
			
		else case ( {push, pop} )
			2'b10:  begin
				if (pointer < 2**PTR_WIDTH - 1) begin
						stack[pointer] <= write_data;
						pointer <= pointer + 1;  
					end
				else
					stack[pointer] <= write_data;
				end
			2'b01: begin 
				if (pointer != 0) begin
				read_data <= stack [pointer-1];
					pointer <= pointer - 1;
				end
				else
					read_data <= 0;
				end
			default: read_data <= stack [pointer];
			endcase
		end
	
endmodule
module register
#(
    parameter SIZE = 4
)
(
    input                          ena, 
    input                          clk,
    input      [SIZE - 1 : 0]      d,
    output reg [SIZE - 1 : 0]      q
);
    always @ (posedge clk)
	if (ena) 
            q <= d;
endmodule
module lab7_1
#(
	parameter DATA_WIDTH=4, 
	parameter ADDR_WIDTH=2
)
(
    input                          clk,
    input      [6:0]               SW,
    output     [3:0]               LEDR
);

	reg        [3:0]               w_we;          //DC output for write enable
	reg        [3:0]               mux_out;       //mux out 
	wire	   [(DATA_WIDTH-1):0]  reg0;          //output register 0
	wire	   [(DATA_WIDTH-1):0]  reg1;          //output register 1
	wire	   [(DATA_WIDTH-1):0]  reg2;          //output register 2
	wire	   [(DATA_WIDTH-1):0]  reg3;          //output register 3
	
	// DC
	always @(SW[6:4])
		begin
			if (SW[6]) 
				case (SW[5:4])
					2'b00    :    w_we = 4'b0001;
					2'b01    :    w_we = 4'b0010;
					2'b10    :    w_we = 4'b0100;
					2'b11    :    w_we = 4'b1000;
					default	 :    w_we = 4'b0000;
				endcase
			else 
				w_we = 4'b0000;
		end
	
	//mux
	always @*
    case (SW[5:4])
        2'b00    :    mux_out = reg0;
        2'b01    :    mux_out = reg1;
        2'b10    :    mux_out = reg2; 
        2'b11    :    mux_out = reg3;
		default	 :    mux_out = 4'b0000;
    endcase

	assign LEDR = mux_out;
	
	register #(4) register0 (.ena(w_we[0]), .clk(clk), .d(SW[3:0]), .q(reg0));
	register #(4) register1 (.ena(w_we[1]), .clk(clk), .d(SW[3:0]), .q(reg1));
	register #(4) register2 (.ena(w_we[2]), .clk(clk), .d(SW[3:0]), .q(reg2));
	register #(4) register3 (.ena(w_we[3]), .clk(clk), .d(SW[3:0]), .q(reg3));
	
	
endmodule
module lab7_4
#(parameter DATA_WIDTH=4, parameter ADDR_WIDTH=6)
(   input                           clk,
    input     [(ADDR_WIDTH-1):0]    addr,
    output    [(DATA_WIDTH-1):0]    data_out,
    output    [(ADDR_WIDTH-1):0]    addr_out
);

    // ROM array
    reg       [DATA_WIDTH-1:0]      rom[0:2**ADDR_WIDTH-1];

    // invert chip select signal and clk button
    wire w_clk = ~ clk;
    reg [ADDR_WIDTH-1:0] addr_reg;
    
    // read ROM content from file
    initial 
	 begin
        $readmemh("../../rom.txt", rom);
    end
    
    always @ (posedge w_clk)
    begin
       addr_reg <= addr;
    end
     
    assign data_out = rom[addr_reg];
    assign addr_out = addr_reg;
endmodule
module lab7_3

#(parameter DATA_WIDTH=4, parameter ADDR_WIDTH=6)

(
    input [(DATA_WIDTH-1):0] data_in,
    input [(ADDR_WIDTH-1):0] addr,
    input we, clk,
    output [(DATA_WIDTH-1):0] data_out,
    output [(ADDR_WIDTH-1):0] addr_out
);

    // Memory array and address register:
    reg [DATA_WIDTH-1:0] ram[0:2**ADDR_WIDTH-1];
    reg [ADDR_WIDTH-1:0] addr_reg;

    wire w_we = ~ we;
    wire w_clk = ~ clk;

    always @ (posedge w_clk)
    begin
        if (w_we)                      // write enable = 1
            ram[addr] <= data_in;      // write input data to memory

        addr_reg <= addr;              // latch address in internal register
    end

    assign data_out = ram[addr_reg];   // read data at latched address
    assign addr_out = addr_reg;        

endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    lab7_6 lab7_6 (KEY[0], KEY[1], KEY[2], KEY[3], SW[7:0], LEDR[7:0]);
 
endmodule
module testbench;
    // input and output test signals

	reg clk;
	reg reset;
	reg push;
	reg pop;
	reg [7:0] write_data;
	wire [7:0] read_data;

    // creating the instance of the module we want to test
    //  lab7_6 - module name
    //  dut  - instance name ('dut' means 'device under test')
    lab7_6 dut (clk, reset, push, pop, write_data, read_data);
	
initial 
	begin
		// set inital values of signal
		clk = 1;
		reset = 1;
		push = 1;
		pop = 0;
		write_data = 8'b00000000; 
		
		// write data in RAM
		#20; 					     			    // pause
			write_data = 8'b00000001;
		#10;
			reset = 0;
		#10; 					     			    // pause
			write_data = 8'b00000010;
		#20; 					     			    // pause
			write_data = 8'b00000011;
		#20; 					     			    // pause
			write_data = 8'b00000100;
		#20; 					     			    // pause
			write_data = 8'b00000101;
		#20; 					     			    // pause
			write_data = 8'b00000110;
			push = 0;
			pop = 1;
		#20; 					     			    // pause
			write_data = 8'b00000111;
		#20; 					     			    // pause
			write_data = 8'b00001000;
		#20; 					     			    // pause
			write_data = 8'b00001001;
		#20; 					     			    // pause
			write_data = 8'b00001011;
	end
	
	//every 10 ns invert clk 
	always #10 clk = ~clk;


	initial 
		#220 $finish;
	
   // do at the beginning of the simulation
   // print signal values on every change
   initial 
       $monitor("clk=%b reset=%b push=%b pop=%b write_data=%b read_data=%b", 
			clk, reset, push, pop, write_data, read_data);

   // do at the beginning of the simulation
   initial 
       $dumpvars;  //iverilog dump init

endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    lab7_2 lab7_2 (SW[3:0], LEDR[0]);
 
endmodule
module testbench;
    // input and output test signals

	reg [3:0] x;
	wire y;

    // creating the instance of the module we want to test
    //  lab7_2 - module name
    //  dut  - instance name ('dut' means 'device under test')
    lab7_2 dut ( x, y );
	
initial 
	begin
		// set inital values of signal
		x = 4'b0000;
	
        repeat(15)
        begin
			#10;                     
			x = x + 4'b0001;	 
        end
	end
	
	initial 
		#160 $finish;
	
   // do at the beginning of the simulation
   // print signal values on every change
   initial 
       $monitor("x=%b y=%h", x, y);

   // do at the beginning of the simulation
   initial 
       $dumpvars;  //iverilog dump init

endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    lab7_7 lab7_7 (KEY[0], KEY[1], KEY[2], KEY[3], SW[7:0], LEDR[7:0]);
 
endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    lab7_1 lab7_1 (KEY[0], SW[6:0], LEDR[3:0]);
 
endmodule
module testbench;
    // input and output test signals

    reg              clk;
    reg     [6:0]    SW;
    wire    [3:0]    LEDR;

    // creating the instance of the module we want to test
    //  lab7_1 - module name
    //  dut  - instance name ('dut' means 'device under test')
    lab7_1 dut ( clk, SW, LEDR );
    
initial 
    begin
        // set inital values of signal
        clk = 1;
        SW = 7'b1001111;
        #5;                     
        
        repeat(3)
        begin
            #20;                     
            SW[5:4] = SW[5:4]+2'b01;     
        end

        #40; 
        SW = 7'b0000000;
        repeat(3)
        begin
            #20;                     
            SW[5:4] = SW[5:4]+2'b01;     
        end
    end
    
    //every 10 ns invert clk 
    always #10 clk = ~clk;

    
    initial 
        #200 $finish;
    
   // do at the beginning of the simulation
   // print signal values on every change
   initial 
       $monitor("clk=%b SW=%h LEDR=%h", 
            clk, SW, LEDR);

   // do at the beginning of the simulation
   initial 
       $dumpvars;  //iverilog dump init

endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    lab7_4 lab7_4 (KEY[0], SW[9:4], LEDR[3:0], LEDR[9:4]);
 
endmodule
module testbench;
    // input and output test signals

	reg clk;
	reg [5:0] addr;
	wire [3:0] data_out;
	wire [5:0] addr_out;
	integer i;
 
    // creating the instance of the module we want to test
    //  lab7_41 - module name
    //  dut  - instance name ('dut' means 'device under test')
    lab7_4 dut (clk, addr, data_out, addr_out);
	
initial 
	begin
		// set initial values of signal
		clk = 0;
		#20; 				// pause
		addr = 6'b000000;	// set address signals value
            for (i=0 ; i<=16; i=i+1)
            begin
				#20; 			// pause
				addr = addr+6'b000001;	// set address signals value
            end
	end
	
	//every 10 ns invert clk 
	always #10 clk = ~clk;
	
	initial 
		#380 $finish;
	   
   // do at the beginning of the simulation
   // print signal values on every change
   initial 
       $monitor("clk=%b addr=%b data_out=%b addr_out=%b", 
			clk, addr, data_out, addr_out);

   // do at the beginning of the simulation
   initial 
       $dumpvars;  //iverilog dump init

endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    lab7_3 lab7_3 (SW[3:0], SW[9:4], KEY[3], KEY[0], LEDR[3:0], LEDR[9:4]);
 
endmodule
module testbench;
    // input and output test signals

    reg [3:0] data_in;
    reg [5:0] addr;
    reg we;
    reg clk;
    wire [3:0] data_out;
    wire [5:0] addr_out;

    // creating the instance of the module we want to test
    lab7_3 dut (data_in, addr, we, clk, data_out, addr_out);
    
    initial 
    begin
        // set initial values of signal
        clk = 0;
        we = 0;
        addr = 6'b000000;
        data_in = 4'b0000; 

        // write data in RAM
        #20; we = 0;                  // write enable
        for (addr=0; addr < 6; addr= addr+1)
            begin
                #20;
                data_in = data_in + 1;
            end

        //read data from RAM
        #20; we = 1;
        for (addr=0; addr < 6; addr= addr+1)
            #20; // end of for loop     
    end
    
    //every 10 ns invert clk 
    always #10 clk = ~clk;
    
    initial 
        #300 $finish;
    
   // do at the beginning of the simulation
   // print signal values on every change
   initial 
       $monitor("data_in=%b addr=%b we=%b clk=%b data_out=%b addr_out=%b", 
            data_in, addr, we, clk, data_out, addr_out);

   // do at the beginning of the simulation
   initial 
       $dumpvars;

endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    b2_enc_if lab3 (SW[9:0], LEDR[3:0], KEY[0]);
 
endmodule
module testbench;
    // input and output test signals
   	reg  enable;

    reg [15:0] binary;

    wire [3:0] binary_out;
 
   // creating the instance of the module we want to test
	b2_enc_if b2_enc_if(binary,binary_out,enable);
	
	initial 
    begin
        // set inital values of signal
        enable = 1;
        binary = 0;
		
        #1;
           binary=16'b0000000000000001;
        #1;
           binary=16'b0000000000000010;
        #1;
           binary=16'b0000000000000100;
        #1;
           binary=16'b0000000000001000;
        #1;
           binary=16'b0000000000010000;
        #1;
           binary=16'b0000000000100000;
        #1;
           binary=16'b0000000001000000;
        #1;
           binary=16'b0000000010000000;
        #1;
           binary=16'b0000000100000000;
	#1;
           binary=16'b0000001000000000;
        #1;
           binary=16'b0000010000000000;
        #1;
           binary=16'b0000100000000000;
	#1;
           binary=16'b0001000000000000;
        #1;
           binary=16'b0010000000000000;
        #1;
           binary=16'b0100000000000000;
        #1;
           binary=16'b1000000000000000;
        #1;
           binary=16'b0100000000000000;
           enable = 0;

    end
    // do at the beginning of the simulation
    //  print signal values on every change
    initial 
         $monitor("enable=%b, binary=%b, binary_out=%b",
            enable, binary, binary_out);
    // do at the beginning of the simulation
    initial 
        $dumpvars;  //iverilog dump init
endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    b8_4bit_dec_assign_logic lab3 (SW, LEDR, KEY[0]);
 
endmodule
module testbench;
    // input and output test signals
   	reg  enable;

    reg [3:0] binary;

    wire [15:0] binary_out_logic;
 
   // creating the instance of the module we want to test
	b8_4bit_dec_assign_logic b8_4bit_dec_assign_logic(
		.in(binary),
		.out(binary_out_logic),
		.enable(enable)
	);
	
	initial 
    begin
        // set inital values of signal
        enable = 1;
        binary = 0;
		
        #1;                                           
           binary=binary+1;
        #1;
           binary=binary+1;
        #1;
           binary=binary+1;
        #1;
           binary=binary+1;
        #1;
           binary=binary+1;
        #1;
           binary=binary+1;
        #1;
           binary=binary+1;
        #1;
           binary=binary+1;
        #1;
           binary=binary+1;
		#1;
           binary=binary+1;
        #1;
           binary=binary+1;
        #1;
           binary=binary+1;
		#1;
           binary=binary+1;
        #1;
           binary=binary+1;
        #1;
           binary=binary+1;
           enable = 0;
	   	   binary = 1;
        #1;
           binary=binary+1;

    end
    // do at the beginning of the simulation
    //  print signal values on every change
    initial 
         $monitor("enable=%b, binary=%b, binary_out_logic=%b",
            enable, binary, binary_out_logic);
    // do at the beginning of the simulation
    initial 
        $dumpvars;  //iverilog dump init
endmodule
module top (SW, KEY, LEDR);

    input wire [9:0] SW;        // DE-series switches
    input wire [3:0] KEY;       // DE-series pushbuttons

    output wire [9:0] LEDR;     // DE-series LEDs   

    b3_enc_case lab3 (SW[9:0], LEDR[3:0], KEY[0]);
 
endmodule