dakies/OSS_Verilog huggingface dataset:
module MUXCY (O, CI, DI, S);


`ifdef XIL_TIMING

    parameter LOC = "UNPLACED";

`endif


    output O;
    input CI, DI, S;
    
    reg O_out;

	always @(CI or DI or S) 
	    if (S)
		O_out = CI;
	    else
		O_out = DI;

    assign O = O_out;
    
`ifdef XIL_TIMING

    specify
                                                                                 
        (CI => O) = (0:0:0, 0:0:0);
        (DI => O) = (0:0:0, 0:0:0);
	(S => O) = (0:0:0, 0:0:0);
        specparam PATHPULSE$ = 0;
                                                                                 
    endspecify

`endif

endmodule
module EFUSE_USR (
  EFUSEUSR
);

  parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000;

`ifdef XIL_TIMING

  parameter LOC = "UNPLACED";

`endif

    
  output [31:0] EFUSEUSR;

  assign EFUSEUSR = SIM_EFUSE_VALUE;

  specify

      specparam PATHPULSE$ = 0;

  endspecify

endmodule
module KEEPER (O);

    inout O;
    

`ifdef XIL_TIMING

    parameter LOC = "UNPLACED";

`endif

    
    reg   in;

    always @(O)
	if (O)
	    in <= 1;
	else
	    in <= 0;

    buf (pull1, pull0) B1 (O, in);

endmodule
module PULLDOWN (O);


`ifdef XIL_TIMING

    parameter LOC = "UNPLACED";

`endif


    output O;

    wire A;

    pulldown (A);
    buf (weak0,weak1) #(100,100) (O,A);

endmodule
module FRAME_ECCE4
`ifdef XIL_TIMING
#(
  parameter LOC = "UNPLACED"
)
`endif
(
  output CRCERROR,
  output ECCERRORNOTSINGLE,
  output ECCERRORSINGLE,
  output ENDOFFRAME,
  output ENDOFSCAN,
  output [26:0] FAR,

  input [1:0] FARSEL,
  input ICAPBOTCLK,
  input ICAPTOPCLK
);
  
endmodule
module INV (O, I);


`ifdef XIL_TIMING

  parameter LOC = "UNPLACED";

`endif

  output O;
  input I;

  not n1 (O, I);

`ifdef XIL_TIMING

  specify

	(I => O) = (0:0:0, 0:0:0);
	specparam PATHPULSE$ = 0;

  endspecify

`endif

endmodule
module AUTOBUF (O, I);

    parameter BUFFER_TYPE = "AUTO";

`ifdef XIL_TIMING

    parameter LOC = "UNPLACED";

`endif

    
    output O;

    input  I;

    initial begin
	
	case (BUFFER_TYPE)
	    "AUTO" : ;
	    "BUF" : ;
	    "BUFG" : ;
	    "BUFGP" : ;
	    "BUFH" : ;
	    "BUFIO" : ;
	    "BUFIO2" : ;
	    "BUFIO2FB" : ;
	    "BUFR" : ;
	    "IBUF" : ;
	    "IBUFG" : ;
	    "NONE" : ;
	    "OBUF" : ;
	    default : begin
		$display("Attribute Syntax Error : The Attribute BUFFER_TYPE on AUTOBUF instance %m is set to %s.  Legal values for this attribute are AUTO, BUF, BUFG, BUFGP, BUFH, BUFIO, BUFIO2, BUFIO2FB, BUFR, IBUF, IBUFG, NONE, and OBUF.", BUFFER_TYPE);
	    end
	endcase
	
    end

    buf B1 (O, I);
    
`ifdef XIL_TIMING

    specify

	(I => O) = (0:0:0, 0:0:0);
	specparam PATHPULSE$ = 0;
	
    endspecify

`endif
    
endmodule
module VCC(P);


`ifdef XIL_TIMING

    parameter LOC = "UNPLACED";

`endif


    output P;

    assign P = 1'b1;

endmodule
module XORCY (O, CI, LI);


`ifdef XIL_TIMING

    parameter LOC = "UNPLACED";

`endif

    
    output O;

    input  CI, LI;

	xor X1 (O, CI, LI);

`ifdef XIL_TIMING

    specify
        
        (CI => O) = (0:0:0, 0:0:0);
        (LI => O) = (0:0:0, 0:0:0);
        specparam PATHPULSE$ = 0;
        
    endspecify

`endif
    
endmodule
module MUXF8 (O, I0, I1, S);


`ifdef XIL_TIMING

    parameter LOC = "UNPLACED";

`endif

    
    output O;
    input I0, I1, S;
    
    reg O_out;

    always @(I0 or I1 or S) 
        if (S)
	    O_out = I1;
	else
	    O_out = I0;
    
    assign O = O_out;
    
`ifdef XIL_TIMING

    specify
                                                                                 
        (I0 => O) = (0:0:0, 0:0:0);
        (I1 => O) = (0:0:0, 0:0:0);
	(S => O) = (0:0:0, 0:0:0);
        specparam PATHPULSE$ = 0;
                                                                                 
    endspecify

`endif
    
endmodule
module PULLUP (O);


`ifdef XIL_TIMING

    parameter LOC = "UNPLACED";

`endif

  
    output O;

    wire A;

    pullup (A);
    buf (weak0,weak1) #(100,100) (O,A);

endmodule
module BUFHCE #(
  `ifdef XIL_TIMING //Simprim 
  parameter LOC = "UNPLACED",
  `endif
  parameter CE_TYPE = "SYNC",
  parameter integer INIT_OUT = 0,
  parameter [0:0] IS_CE_INVERTED = 1'b0
)(
  output O,

  input CE,
  input I
);

  `ifdef XIL_TIMING //Simprim 
  reg notifier;
  `endif
  wire del_I, delCE;
  wire  NCE, o_bufg_o, o_bufg1_o;
  reg CE_TYPE_BINARY;
  reg INIT_OUT_BINARY;
  reg IS_CE_INVERTED_BIN = IS_CE_INVERTED;

  initial begin
    case (CE_TYPE)
      "SYNC" : CE_TYPE_BINARY = 1'b0;
      "ASYNC" : CE_TYPE_BINARY = 1'b1;
      default : begin
        $display("Attribute Syntax Error : The Attribute CE_TYPE on BUFHCE instance %m is set to %s.  Legal values for this attribute are SYNC, or ASYNC.", CE_TYPE);
        #1 $finish;
      end
    endcase

    if ((INIT_OUT >= 0) && (INIT_OUT <= 1))
      INIT_OUT_BINARY = INIT_OUT;
    else begin
      $display("Attribute Syntax Error : The Attribute INIT_OUT on BUFHCE instance %m is set to %d.  Legal values for this attribute are  0 to 1.", INIT_OUT);
      #1 $finish;
    end

  end

    
    BUFGCTRL bufgctrl0_inst (.O(o_bufg_o),
			     .CE0(~NCE),
			     .CE1(NCE),
			     .I0(del_I),
			     .I1(1'b0), 
			     .IGNORE0(CE_TYPE_BINARY), 
			     .IGNORE1(1'b0), 
			     .S0(1'b1), 
			     .S1(1'b1));
    
    defparam bufgctrl0_inst.INIT_OUT = 1'b0;
    defparam bufgctrl0_inst.PRESELECT_I0 = "TRUE";
    defparam bufgctrl0_inst.PRESELECT_I1 = "FALSE";
                               
                                       
    INV I1 (.I(delCE ^ IS_CE_INVERTED_BIN),
            .O(NCE));

    
    BUFGCTRL bufgctrl1_inst (.O(o_bufg1_o), 
			     .CE0(~NCE), 
			     .CE1(NCE), 
			     .I0(del_I), 
			     .I1(1'b1), 
			     .IGNORE0(CE_TYPE_BINARY), 
			     .IGNORE1(1'b0), 
			     .S0(1'b1), 
			     .S1(1'b1));
    
    defparam bufgctrl1_inst.INIT_OUT = 1'b0;
    defparam bufgctrl1_inst.PRESELECT_I0 = "TRUE";
    defparam bufgctrl1_inst.PRESELECT_I1 = "FALSE";

    
    assign O = (INIT_OUT == 1) ? o_bufg1_o : o_bufg_o;

    
`ifndef XIL_TIMING
    
    assign del_I = I;
    assign delCE = CE;
    
`endif

    
    specify

	(I => O) = (0:0:0, 0:0:0);
      
`ifdef XIL_TIMING

	$period (posedge I, 0:0:0, notifier);
	$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, del_I, delCE);
	$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, del_I, delCE);
	$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, del_I, delCE);
	$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, del_I, delCE);

`endif

	specparam PATHPULSE$ = 0;
	
    endspecify

    
endmodule
module LUT3 #(
`ifdef XIL_TIMING
  parameter LOC = "UNPLACED",
`endif
  parameter [7:0] INIT = 8'h00
)(
  output O,

  input I0,
  input I1,
  input I2
);

// define constants
  localparam MODULE_NAME = "LUT3";

  reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
  `include "LUT3_dr.v"
`else
  reg [7:0] INIT_REG = INIT;
`endif

  x_lut3_mux8 (O, INIT_REG[7], INIT_REG[6], INIT_REG[5], INIT_REG[4], INIT_REG[3], INIT_REG[2], INIT_REG[1], INIT_REG[0], I2, I1, I0);

`ifdef XIL_TIMING
  specify
	(I0 => O) = (0:0:0, 0:0:0);
	(I1 => O) = (0:0:0, 0:0:0);
	(I2 => O) = (0:0:0, 0:0:0);
	specparam PATHPULSE$ = 0;
  endspecify
`endif

endmodule
module BUF (O, I);


`ifdef XIL_TIMING

    parameter LOC = "UNPLACED";

`endif

    output O;
    input I;
    
    buf B1 (O, I);

`ifdef XIL_TIMING

    specify

	(I => O) = (0:0:0, 0:0:0);
	specparam PATHPULSE$ = 0;
	
    endspecify

`endif
    
endmodule
module USR_ACCESSE2 (
  CFGCLK,
  DATA,
  DATAVALID
);

  `ifdef XIL_TIMING

    parameter LOC = "UNPLACED";

  `endif //

  output CFGCLK;
  output DATAVALID;
  output [31:0] DATA;

  specify

    specparam PATHPULSE$ = 0;
  endspecify
endmodule
module MASTER_JTAG 
  `ifdef XIL_TIMING //Simprim adding LOC only 
#(
  parameter LOC = "UNPLACED"  
)
  `endif
(
  output TDO,

  input TCK,
  input TDI,
  input TMS
);
  
endmodule
module tb_RegFile;
    reg [4:0]R1;
    reg [4:0]R2;
    reg [4:0]RD;
    reg [63:0]RD_DATA;
    reg reg_write_enable;

    wire [63:0]R1_data;
    wire [63:0]R2_data;

    RegFile regfile(R1, R2, RD, RD_DATA, reg_write_enable, R1_data, R2_data );

    initial begin
        R1 = 0;
        R2 = 0;
        RD = 0;
        RD_DATA = 0;
        reg_write_enable = 0;
        #20;

        R1 = 0;
        R2 = 0;
        RD = 1;
        RD_DATA = 5;
        reg_write_enable = 1;
        #20;

        R1 = 1;
        R2 = 0;
        RD = 2;
        RD_DATA = 10;
        reg_write_enable = 1;
        #20;

        R1 = 1;
        R2 = 2;
        RD = 0;
        RD_DATA = 0;
        reg_write_enable = 0;
        #20;
    end

    initial begin
        $dumpfile("vcd/regfile.vcd");
        $dumpvars(0, tb_RegFile);
    end
endmodule
module tb_ALU;
    reg [63:0] a;
    reg [63:0] b;
    reg [3:0]  op;

    wire [63:0] result;
    wire isEqual;

    ALU alu(a, b, op, result, isEqual);

    initial begin
        // add
        a = 5;          b = 5;      op = 0; #20;
        // sub
        a = 66;         b = 11;     op = 1; #20;        
        // and
        a = 3'b101;     b = 3'b110; op = 2; #20;
        // or
        a = 3'b101;     b = 3'b110; op = 3; #20;
        // xor
        a = 3'b110;     b = 3'b010; op = 4; #20;
        // sll (Shift Left Logical)
        a = 1;          b = 3;      op = 5; #20;
        // srl (Shift Right Logical)
        a = 8;          b = 2;      op = 6; #20;
        // sra (Shift Right Arithmetic)
        a = -8;         b = 2;      op = 7; #20;
        // mul
        a = 6;          b = 5;      op = 8; #20;
        // mulh
        a = 64'h8000000000000000;   b = 4;  op = 9; #20; // output will be ...0010 = 2
        // div
        a = 66;         b = 11;     op = 10; #20;
        // rem
        a = 62;         b = 3;      op = 11; #20;
        // slt (Set Less Than)
        a = -1;         b = 9;      op = 12; #20;
        // sltu (Set Less Than Unsigned)
        a = -1;         b = 9;      op = 13; #20;
    end

    initial begin
        $dumpfile("vcd/alu.vcd");
        $dumpvars(0, tb_ALU);
    end
endmodule
module tb_RAM;
    reg [9:0] ADDRESS;
    reg [63:0] DATA_IN;
    reg WRITE_ENABLE;
    reg CLK;

    reg [63:0] DATA_OUT;

    RAM ram(ADDRESS, DATA_IN, WRITE_ENABLE, CLK, DATA_OUT);

    initial begin
        // Write #1
        ADDRESS = 1;
        DATA_IN = 55;
        WRITE_ENABLE = 1;
        CLK = 1; #20; CLK = 0; #20;

        // Write #2
        ADDRESS = 2;
        DATA_IN = 99;
        WRITE_ENABLE = 1;
        CLK = 1; #20; CLK = 0; #20;

        // Read #1
        ADDRESS = 1;
        WRITE_ENABLE = 0;
        DATA_IN = 0;
        CLK = 1; #20; CLK = 0; #20;

        // Read #2
        ADDRESS = 2;
        WRITE_ENABLE = 0;
        DATA_IN = 0;
        CLK = 1; #20; CLK = 0; #20;
    end

    initial begin
        $dumpfile("vcd/ram.vcd");
        $dumpvars(0, tb_RAM);
    end
endmodule
module tb_Main;
    wire [9:0] RAM_ADDR;
    wire [63:0] RAM_READ_DATA;
    wire [63:0] RAM_WRITE_DATA;
    wire RAM_WRITE_ENABLE;

    wire [9:0] INSTRUCTION_ADDR;
    wire [31:0] INSTRUCTION;
    reg CLK = 1;
    
    CPU cpu(
        .RAM_READ_DATA(RAM_READ_DATA),
        .INSTRUCTION(INSTRUCTION),
        .CLK(CLK),

        .RAM_ADDR(RAM_ADDR),
        .RAM_WRITE_DATA(RAM_WRITE_DATA),
        .RAM_WRITE_ENABLE(RAM_WRITE_ENABLE),
        .INSTRUCTION_ADDR(INSTRUCTION_ADDR)
    );
    
    ROM rom(
        .ADDRESS(INSTRUCTION_ADDR),

        .DATA(INSTRUCTION)
    );

    RAM ram(
        .ADDRESS(RAM_ADDR),
        .DATA_IN(RAM_WRITE_DATA),
        .WRITE_ENABLE(RAM_WRITE_ENABLE),
        .CLK(CLK),

        .DATA_OUT(RAM_READ_DATA)    
    );

    initial begin
        for(int i=0; i<40; i=i+1) begin
            CLK=1; #20; CLK=0; #20;
        end
    end

    initial begin
        $dumpfile("vcd/main.vcd");
        $dumpvars(0, tb_Main);
    end
    
endmodule
module ALU(
    input [63:0] X,
    input [63:0] Y,
    input [3:0] OP,

    output [63:0] OUTPUT,
    output isEqual
);
    reg [127:0] RESULT;

    wire signed [63:0] X_signed = X;
    wire signed [63:0] Y_signed = Y;

    assign isEqual = X == Y;

    always @(*) begin
        case (OP)
            0:  RESULT <= X + Y; // add
            1:  RESULT <= X - Y; // sub
            2:  RESULT <= X & Y; // and
            3:  RESULT <= X | Y; // or
            4:  RESULT <= X ^ Y; // xor
            5:  RESULT <= X << Y; // shift left logical
            6:  RESULT <= X >> Y; // shift right logical
            7:  RESULT <= X_signed >>> Y; // shift right arithmetic
            8:  RESULT <= X * Y; // mul
            9:  RESULT <= X * Y; // mulh
            10: RESULT <= X / Y; // div
            11: RESULT <= X % Y; // rem
            12: RESULT <= (X_signed < Y_signed ? 1 : 0); // set less than (slt)
            13: RESULT <= (X < Y ? 1 : 0); // set less than (sltu)
        endcase
    end

    assign OUTPUT = OP == 9 ? RESULT[127:64] : RESULT[63:0];

endmodule
module RegFile(
    input [4:0]R1,
    input [4:0]R2,
    input [4:0]RD,
    input [63:0]RD_DATA,
    input WRITE_ENABLE,

    output [63:0]R1_DATA,
    output [63:0]R2_DATA
);
    reg [63:0] REGISTERS[31:0]; // 64 Bit length, 32 Registers

    integer i = 0;
    initial begin
        for (i = 0; i< 32 ; i = i + 1) begin
            REGISTERS[i] <= 0;
        end
    end

    assign R1_DATA = REGISTERS[R1];
    assign R2_DATA = REGISTERS[R2];

    always @(*) begin
        if (WRITE_ENABLE == 1 && RD != 0)
            REGISTERS[RD] <= RD_DATA;
    end
    

    // GTK WAVE trick to show Arrays. NOT NECESSARY:
    generate
        genvar idx;
        for(idx = 1; idx < 31; idx = idx+1) begin: REG_DATAS
            wire [63:0] R_DATA = REGISTERS[idx];
        end
    endgenerate
endmodule
module ROM(
    input [9:0] ADDRESS,    
    output [31:0] DATA
);
    reg [31:0] memory [1023:0]; // 10-bit address. 32-bit cell size.

    assign DATA = memory[ADDRESS];

    initial begin
        // Example program:

        memory[0] = 32'h00000013; // nop (add x0 x0 0)
        
        // start:
        memory[1] = 32'h00100093; // addi x1 x0 1
        memory[2] = 32'h00100313; // addi x6 x0 1
        memory[3] = 32'h00400613; // addi x12 x0 4
        memory[4] = 32'h0060A023; // sw x6 0(x1)        x6 R2 Dep (WB)

        // loop:
        memory[5] = 32'h0000A303; // lw x6 0(x1)        
        memory[6] = 32'h00130313; // addi x6 x6 1       LoadStall and x6 R1 Dep (WB)
        memory[7] = 32'h0060A023; // sw x6 0(x1)        x6 R2 Dep
        memory[8] = 32'hFEC34AE3; // blt x6 x12 -12     x6 R1 Dep (WB)

        // data_dep_test:
        memory[9] = 32'h03700413; // addi x8 x0 55
        memory[10] = 32'h00800433; // add x8 x0 x8      x8 R2 Dep
        memory[11] = 32'h00140413; // addi x8 x8 1      x8 R1 Dep
        
        // finish:
        memory[12] = 32'h00000013; // nop (add x0 x0 0)
    end
endmodule
module ImmediateExtractor(
    input [31:0] INSTRUCTION,
    input [2:0] SELECTION,
    output reg signed [63:0] VALUE
);
    wire [11:0] IMM_11_0    = INSTRUCTION[31:20];
    wire [19:0] IMM_31_12   = INSTRUCTION[31:12];
    wire [4:0] IMM_4_0      = INSTRUCTION[11:7];
    wire [6:0] IMM_11_5     = INSTRUCTION[31:25];
    wire IMM_11_B           = INSTRUCTION[7];
    wire [3:0] IMM_4_1      = INSTRUCTION[11:8];
    wire [5:0] IMM_10_5     = INSTRUCTION[30:25];
    wire IMM_12             = INSTRUCTION[31];
    wire [7:0] IMM_19_12    = INSTRUCTION[19:12];
    wire IMM_11_J           = INSTRUCTION[20];
    wire [9:0] IMM_10_1     = INSTRUCTION[30:21];
    wire IMM_20             = INSTRUCTION[31];

    // Extend bits and get immediate values of types.    
    wire signed [63:0] Imm_I = { {64{IMM_11_0[11]}}, IMM_11_0 };
    wire signed [63:0] Imm_U = { {64{IMM_31_12[19]}}, IMM_31_12, 12'h000 };
    wire signed [63:0] Imm_B = { {64{IMM_12}}, IMM_11_B, IMM_10_5, IMM_4_1, 1'b0 };
    wire signed [63:0] Imm_S = { {64{IMM_11_5[6]}}, IMM_11_5, IMM_4_0 };
    wire signed [63:0] Imm_UJ = { {64{IMM_20}}, IMM_19_12, IMM_11_J, IMM_10_1, 1'b0 };

    always @(*) begin
        case (SELECTION)
            1: VALUE = Imm_I;
            2: VALUE = Imm_U;
            3: VALUE = Imm_S;
            4: VALUE = Imm_B;
            5: VALUE = Imm_UJ;
            default : VALUE = 0;
        endcase
    end
endmodule
module Encoder_4 (
    input [3:0] in,
    output reg [1:0] out
  );
  initial begin
    out = 0;
  end

  always @(in) begin
    casex (in)
      4'b1xxx : out = 3;
      4'b01xx : out = 2;
      4'b001x : out = 1;
      4'b0001 : out = 0;
      4'b0000 : out = 0;
      default: out = 0;
    endcase
  end
endmodule
module Encoder_8 (
    input [7:0] in,
    output reg [2:0] out
  );
  initial begin
    out = 0;
  end
  
  always @(in) begin
    casex (in)
      8'b1xxxxxxx : out = 7;
      8'b01xxxxxx : out = 6;
      8'b001xxxxx : out = 5;
      8'b0001xxxx : out = 4;
      8'b00001xxx : out = 3;
      8'b000001xx : out = 2;
      8'b0000001x : out = 1;
      8'b00000001 : out = 0;
      8'b00000000 : out = 0;
      default: out = 0;
    endcase
  end
  
endmodule
module Encoder_16 (
    input [15:0] in,
    output reg [3:0] out
  );
  initial begin
    out = 0;
  end
  
  always @(in) begin
    casex (in)
      16'b1xxxxxxxxxxxxxxx : out = 15;
      16'b01xxxxxxxxxxxxxx : out = 14;
      16'b001xxxxxxxxxxxxx : out = 13;
      16'b0001xxxxxxxxxxxx : out = 12;
      16'b00001xxxxxxxxxxx : out = 11;
      16'b000001xxxxxxxxxx : out = 10;
      16'b0000001xxxxxxxxx : out = 9;
      16'b00000001xxxxxxxx : out = 8;
      16'b000000001xxxxxxx : out = 7;
      16'b0000000001xxxxxx : out = 6;
      16'b00000000001xxxxx : out = 5;
      16'b000000000001xxxx : out = 4;
      16'b0000000000001xxx : out = 3;
      16'b00000000000001xx : out = 2;
      16'b000000000000001x : out = 1;
      16'b0000000000000001 : out = 0;
      16'b0000000000000000 : out = 0;
      default: out = 0;
    endcase
  end
  
endmodule
module one_cell(port1, clock, output1, set_b);
  input port1;
  input clock;
  input set_b;
  output output1;

  sky130_fd_sc_hd__dfstp_1 ff1(
    .Q(output1),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );

endmodule
module scan_architect(port1,
  clock1,
  clock2,
  set_b,
  output1,
  output2,
  output3,
  output4,
  output5,
  output6,
  output7,
  output8,
  output9,
  output10,
  output11,
  output12,
  output13,
  output14,
  output15,
  output16,
  output17,
  output18,
  output19,
  output20);
  input port1;
  input clock1;
  input clock2;
  input set_b;
  output output1;
  output output2;
  output output3;
  output output4;
  output output5;
  output output6;
  output output7;
  output output8;
  output output9;
  output output10;
  output output11;
  output output12;
  output output13;
  output output14;
  output output15;
  output output16;
  output output17;
  output output18;
  output output19;
  output output20;

  // Rising edge flops
  sky130_fd_sc_hd__dfstp_1 ff1_clk1_rising(
    .Q(output1),
    .D(port1),
    .CLK(clock1),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff2_clk2_rising(
    .Q(output2),
    .D(port1),
    .CLK(clock2),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff3_clk1_rising(
    .Q(output3),
    .D(port1),
    .CLK(clock1),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff4_clk2_rising(
    .Q(output4),
    .D(port1),
    .CLK(clock2),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff5_clk1_rising(
    .Q(output5),
    .D(port1),
    .CLK(clock1),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff6_clk2_rising(
    .Q(output6),
    .D(port1),
    .CLK(clock2),
    .SET_B(set_b)
  );
  sky130_fd_sc_hd__dfstp_1 ff7_clk1_rising(
    .Q(output7),
    .D(port1),
    .CLK(clock1),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff8_clk2_rising(
    .Q(output8),
    .D(port1),
    .CLK(clock2),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff9_clk1_rising(
    .Q(output9),
    .D(port1),
    .CLK(clock1),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff10_clk2_rising(
    .Q(output10),
    .D(port1),
    .CLK(clock2),
    .SET_B(set_b)
  );
  
  // Falling edge flops
  sky130_fd_sc_hd__dfbbn_1 ff1_clk1_falling(
    .Q(output11),
    .D(port1),
    .CLK_N(clock1),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfbbn_1 ff2_clk2_falling(
    .Q(output12),
    .D(port1),
    .CLK_N(clock2),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfbbn_1 ff3_clk1_falling(
    .Q(output13),
    .D(port1),
    .CLK_N(clock1),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfbbn_1 ff4_clk2_falling(
    .Q(output14),
    .D(port1),
    .CLK_N(clock2),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfbbn_1 ff5_clk1_falling(
    .Q(output15),
    .D(port1),
    .CLK_N(clock1),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfbbn_1 ff6_clk2_falling(
    .Q(output16),
    .D(port1),
    .CLK_N(clock2),
    .SET_B(set_b)
  );
  sky130_fd_sc_hd__dfbbn_1 ff7_clk1_falling(
    .Q(output17),
    .D(port1),
    .CLK_N(clock1),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfbbn_1 ff8_clk2_falling(
    .Q(output18),
    .D(port1),
    .CLK_N(clock2),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfbbn_1 ff9_clk1_falling(
    .Q(output19),
    .D(port1),
    .CLK_N(clock1),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfbbn_1 ff10_clk2_falling(
    .Q(output20),
    .D(port1),
    .CLK_N(clock2),
    .SET_B(set_b)
  );


endmodule
module place_sort(port1,
  clock,
  set_b,
  output1,
  output2,
  output3,
  output4,
  output5,
  output6,
  output7,
  output8,
  output9,
  output10);
  input port1;
  input clock;
  input set_b;
  output output1;
  output output2;
  output output3;
  output output4;
  output output5;
  output output6;
  output output7;
  output output8;
  output output9;
  output output10;


  // Rising edge flops
  sky130_fd_sc_hd__dfstp_1 ff1_clk1_rising(
    .Q(output1),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff2_clk1_rising(
    .Q(output2),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff3_clk1_rising(
    .Q(output3),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff4_clk1_rising(
    .Q(output4),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff5_clk1_rising(
    .Q(output5),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff6_clk1_rising(
    .Q(output6),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );
  sky130_fd_sc_hd__dfstp_1 ff7_clk1_rising(
    .Q(output7),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff8_clk1_rising(
    .Q(output8),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff9_clk1_rising(
    .Q(output9),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff10_clk1_rising(
    .Q(output10),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );


endmodule
module one_cell(port1, clock, output1, set_b);
  input port1;
  input clock;
  input set_b;
  output output1;

  DFF_X1 ff1(
    .D(port1),
    .Q(output1),
    .CL(clock)
  );

endmodule
module max_chain_count(port1,
  clock,
  set_b,
  output1,
  output2,
  output3,
  output4,
  output5,
  output6,
  output7,
  output8,
  output9,
  output10);
  input port1;
  input clock;
  input set_b;
  output output1;
  output output2;
  output output3;
  output output4;
  output output5;
  output output6;
  output output7;
  output output8;
  output output9;
  output output10;


  // Rising edge flops
  sky130_fd_sc_hd__dfstp_1 ff1_clk1_rising(
    .Q(output1),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff2_clk1_rising(
    .Q(output2),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff3_clk1_rising(
    .Q(output3),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff4_clk1_rising(
    .Q(output4),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff5_clk1_rising(
    .Q(output5),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff6_clk1_rising(
    .Q(output6),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );
  sky130_fd_sc_hd__dfstp_1 ff7_clk1_rising(
    .Q(output7),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff8_clk1_rising(
    .Q(output8),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff9_clk1_rising(
    .Q(output9),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff10_clk1_rising(
    .Q(output10),
    .D(port1),
    .CLK(clock),
    .SET_B(set_b)
  );


endmodule
module sub_modules(port1, clock, output1, set_b);
  input port1;
  input clock;
  input set_b;
  output output1;

 shift_register_2b my_shift_register(port1, output1, clock);

endmodule
module shift_register_2b(from, to, clock);
  input from;
  output to;
  input clock;
  wire net1;

  sky130_fd_sc_hd__dfstp_1 ff1(
    .Q(net1),
    .D(from),
    .CLK(clock),
    .SET_B(set_b)
  );

  sky130_fd_sc_hd__dfstp_1 ff2(
    .Q(to),
    .D(net1),
    .CLK(clock),
    .SET_B(set_b)
  );
endmodule
module macro_only ( );
  wire   w1, w2, w3, w4;
  wire   w11, w21, w31, w41;
  wire   w12, w22, w32, w42;

  HM_100x400_4x4 U1 ( .O1(w1), .O2(w2), .O3(w3), .O4(w4) ) ;
  HM_100x100_1x1 U2 ( .I1(w1), .O1(w11) ) ;
  HM_100x100_1x1 U3 ( .I1(w2), .O1(w21) ) ;
  HM_100x100_1x1 U4 ( .I1(w3), .O1(w31) ) ;
  HM_100x100_1x1 U5 ( .I1(w4), .O1(w41) ) ;
  HM_100x100_1x1 U7 ( .I1(w11) , .O1(w12) ) ;
  HM_100x100_1x1 U8 ( .I1(w21) , .O1(w22) ) ;
  HM_100x100_1x1 U9 ( .I1(w31) , .O1(w32) ) ;
  HM_100x100_1x1 U10 ( .I1(w41) , .O1(w42) ) ;
  HM_100x400_4x4 U6 ( .I1(w12), .I2(w22), .I3(w32), .I4(w42) ) ;

endmodule
module top (in1, clk1, clk2, clk3, out);
  input in1, clk1, clk2, clk3;
  output out;

   // unconnected reg output
  DFF_X1 r1 (.D(in1), .CK(clk1), .Q(r1q), .QN(r1qn));

  // no driver for r2q
  BUF_X1 u1 (.A(r1q), .Z(u1z));
  AND2_X1 u2 (.A1(r1q), .A2(u1z), .ZN(u2z));
  DFF_X1 r3 (.D(u2z), .CK(clk3), .Q());
endmodule // top
module top (in1, clk1, clk2, clk3, out);
  input in1, clk1, clk2, clk3;
  output out;

   // unconnected reg output
  DFF_X1 r1 (.D(in1), .CK(clk1), .Q(r1q), .QN(r1qn));

  // no driver for r2q
  BUF_X1 u1 (.A(), .Z(u1z));
  AND2_X1 u2 (.A1(r1q), .A2(u1z), .ZN(u2z));
  DFF_X1 r3 (.D(u2z), .CK(clk3), .Q(out));
endmodule // top
module top (in1, clk1, out1, out2);
  input in1, clk1;
  output out1, out2;

  DFF_X1 r1 (.D(in1), .CK(clk1), .Q(out1));
  assign out2 = out1;
endmodule // top
module top (in1, clk1, clk2, clk3, out);
  input in1, clk1, clk2, clk3;
  output out;

   // unconnected reg output
  DFF_X1 r1 (.D(in1), .CK(clk1), .Q(r1q), .QN(r1qn));

  // no driver for r2q
  BUF_X1 u1 (.A(r2q), .Z(u1z));
  AND2_X1 u2 (.A1(r1q), .A2(u1z), .ZN(u2z));
  DFF_X1 r3 (.D(u2z), .CK(clk3), .Q(out));
endmodule // top
module top (in1, out1, out2);
   input in1;
   output out1;
   output out2;

   (* dont_touch *) BUF_X1 u1 (.A(in1), .Z(out1));
   BUF_X1 u2 (.A(in1), .Z(out2));
endmodule // top
module top (in1, clk1, out1);
  input in1, clk1;
  output out1;

  AND2_X1 u1 (.A1(in1), .A2(1'b0), .ZN(u1z));
  DFF_X1 r1 (.D(u1z), .CK(clk1), .Q(r1q));
  DFF_X1 r2 (.D(r1q), .CK(clk1), .Q(out1));
endmodule // top
module hierclock(
                 input        clk_i,
                 input        rst_n_i,
                 input [3:0]  a_i,
                 input [3:0]  b_i,
                 input        a_ld_i,
                 input        b_ld_i,
                 output [3:0] a_count_o,
                 output a_count_valid_o,
                 output [3:0] b_count_o,
                 output b_count_valid_o
                 );
   wire                 clk1_int;
   wire                 clk2_int;

   clockgen U1 (.clk_i(clk_i), 
                .rst_n_i(rst_n_i), 
                .clk1_o(clk1_int), 
                .clk2_o(clk2_int));
   
   counter  U2(.clk_i(clk1_int),.rst_n_i(rst_n_i),.load_i(a_ld_i), 
               .load_value_i(a_i), 
               .count_value_o(a_count_o), 
               .count_valid_o(a_count_valid_o)
               );
   counter  U3(.clk_i(clk2_int), .rst_n_i(rst_n_i), .load_i(b_ld_i), 
               .load_value_i(b_i), 
               .count_value_o(b_count_o), 
               .count_valid_o(b_count_valid_o)
               );
   
endmodule // hierclock
module counter (input clk_i,
                input  rst_n_i,
                input  load_i,
                input[3:0]  load_value_i,
                output[3:0] count_value_o,
                output count_valid_o);

   reg [3:0]                counter_q;
   reg                      count_valid_q;

   assign count_value_o = counter_q;
   assign count_valid_o = count_valid_q;
   
   always @(posedge clk_i)
     begin
        if (~rst_n_i)
          begin
             counter_q <= 4'b0;
             count_valid_q <= 1'b0;
          end
        else
          begin
             if (load_i)
               begin
                  counter_q <= load_value_i;
                  count_valid_q <= 1'b0;
               end
             else
               begin
                  counter_q <= counter_q + 1'b1;
                  count_valid_q <= 1'b1;
               end
          end
     end
endmodule // counter
module clockgen (input clk_i,
                 input  rst_n_i,
                 output clk1_o,
                 output clk2_o);
   reg [3:0]            counter_q;

   always @(posedge clk_i)
     begin
        if (~rst_n_i)
          counter_q <= 4'b0;
        else
          begin
             counter_q <= counter_q + 1'b1;
          end
     end
   assign clk1_o = counter_q[1];
   assign clk2_o = counter_q[3];
endmodule // clockgen
module top (in1, in2, clk1, clk2, clk3, out);
  input in1, in2, clk1, clk2, clk3;
  output out;
  wire r1q, r2q, u1z, u2z;

  snl_ffqx1 r1 (.D(in1), .CP(clk1), .Q(r1q));
  snl_ffqx1 r2 (.D(in2), .CP(clk2), .Q(r2q));
  snl_bufx1 u1 (.A(r2q), .Z(u1z));
  snl_and02x1 u2 (.A(r1q), .B(u1z), .Z(u2z));
  snl_ffqx1 r3 (.D(u2z), .CP(clk3), .Q(out));
endmodule // top
module top (in1, in2, clk1, clk2, clk3, out);
  input in1, in2, clk1, clk2, clk3;
  output out;
  wire r1q, r2q, u1z, u2z;

  DFF_X1 r1 (.D(in1), .CK(clk1), .Q(r1q));
  DFF_X1 r2 (.D(in2), .CK(clk2), .Q(r2q));
  BUF_X1 u1 (.A(r2q), .Z(u1z));
  AND2_X1 u2 (.A1(r1q), .A2(u1z), .ZN(u2z));
  DFF_X1 r3 (.D(u2z), .CK(clk3), .Q(out));
endmodule // top
module top (in1,
    in2,
    clk1,
    clk2,
    clk3,
    out);
 input in1;
 input in2;
 input clk1;
 input clk2;
 input clk3;
 output out;

 DFF_X1 r1 (.Q(r1q),
    .D(in1),
    .CK(clk1));
 DFF_X1 r2 (.Q(r2q),
    .D(in2),
    .CK(clk2));
 DFF_X1 r3 (.Q(out),
    .D(u2z),
    .CK(clk3));
 BUF_X1 u1 (.Z(u1z),
    .A(r2q));
 AND2_X1 u2 (.ZN(u2z),
    .A1(r1q),
    .A2(u1z));
endmodule
module top (in1, out1);
   input in1;
   output out1;
   wire out1_alias;

   BUF_X1 u1 (.A(in1), .Z(out1_alias));
   assign out1 = out1_alias;
endmodule // top
module testcase(clk, din, dout);
  input clk;
  input din;
  output dout;

  DFF_X1 _0_ (
    .CK(clk),
    .D(din),
    .Q(dout)
  );
endmodule
module top (in, out, clk);
   input clk;
   input [3:0] in; 
   output [3:0] out; 

   bus4 bus1(.clk(clk), .in(in), .out(out));
endmodule
module top (in1, in2, clk1, clk2, clk3, out);
  input in1, in2, clk1, clk2, clk3;
  output out;
  wire r1q, r2q, u1z, u2z;

  xxx r1 (.D(in1), .CP(clk1), .Q(r1q));
  snl_ffqx1 r2 (.D(in2), .CP(clk2), .Q(r2q));
  snl_bufx1 u1 (.A(r2q), .Z(u1z));
  snl_and02x1 u2 (.A(r1q), .B(u1z), .Z(u2z));
  snl_ffqx1 r3 (.D(u2z), .CP(clk3), .Q(out));
endmodule // top
module top (in, clk1, clk2, out);
   input in, clk1, clk2;
   output out;

   block1 b1 (.in(in), .clk(clk1), .out(b1out));
   block1 b2 (.in(b1out), .clk(clk2), .out(out));
endmodule // top
module block1 (in, clk, out);
   input in, clk;
   output out;

   snl_bufx1 u1 (.A(in), .Z(u1out));
   (* src = "hier1.v:15.3-15.47" *)
   snl_ffqx1 r1 (.D(u1out), .CP(clk), .Q(r1q));
   snl_bufx1 u2 (.A(r1q), .Z(out));
endmodule // top
module top (in1, in2, clk1, clk2, clk3, out);
  input in1, in2, clk1, clk2, clk3;
  output out;
  wire r1q, r2q, u1z, u2z;

  DFF_X1 r1 (.D(in1), .CK(clk1), .Q(r1q));
  DFF_X1 r2 (.D(in2), .CK(clk2), .Q(r2q));
  // missing liberty
  BUF_X10 u1 (.A(r2q), .Z(u1z));
  // missing lef and liberty
  AND2_X10 u2 (.A1(r1q), .A2(u1z), .ZN(u2z));
  DFF_X1 r3 (.D(u2z), .CK(clk3), .Q(out));
endmodule // top
module top (in1, in2, out);
  input in1, in2;
  output out;
  wire u1zn, u2zn;

  NAND2_X1 u1 (.A1(in1), .A2(1'b0), .ZN(u1zn));
  INV_X1 u2 (.A(u1zn), .ZN(u2zn));
  OR2_X1 u3 (.A1(u2zn), .A2(in2), .ZN(out));
endmodule // top
module top (in1, in2, out1);
   input in1, in2;
   output out1;
   tri in1;

   bidir b1(.IO(in1), .A(in2), .Z(out1));
endmodule
module gate1 (a1,a2,zn);
   input a1;
   input a2;
   output zn;

   AND2_X1 _5_ (
    .A1(a1),
    .A2(a2),
    .ZN(zn)
  );
   
endmodule // gatel
module top (a,b, out);
   input a;
   input b;
   output out;

   
   wire   a_int;
   
  INV_X1 _4_ (
    .A(a),
    .ZN(a_int)
  );
   
//   gate1 gate1_inst (
//	      .a1(a_int),
//	      .a2(b),
//	      .zn(out)
//	      );

   gate1 gate2_inst (
	      .a1(a_int),
	      .a2(b),
	      .zn(out)
	      );



endmodule
module reg5 (out,
    clk,
    in);
 output out;
 input [2:0] clk;
 input [0:1] in;

 wire r1q;
 wire r2q;
 wire u1z;
 wire u2z;

 snl_ffqx1 r1 (.Q(r1q),
    .D(in[0]),
    .CP(clk[0]));
 snl_ffqx1 r2 (.Q(r2q),
    .D(in[1]),
    .CP(clk[1]));
 snl_ffqx1 r3 (.Q(out),
    .D(u2z),
    .CP(clk[2]));
 snl_bufx1 u1 (.Z(u1z),
    .A(r2q));
 snl_and02x1 u2 (.Z(u2z),
    .A(r1q),
    .B(u1z));
endmodule
module mem2 (
	clk, 
	mem_out0,
	mem_out1);
   input clk;
   output [6:0] mem_out0;
   output [6:0] mem_out1;
   
   fakeram45_64x7 mem0 (.clk(clk),
	                .rd_out(mem_out0));
   
   fakeram45_64x7 mem1 (.clk(clk),
	                .rd_out(mem_out1));
endmodule
module gcd_mem3 (
	clk, 
	req_msg, 
	req_rdy, 
	req_val, 
	reset, 
	resp_msg, 
	resp_rdy, 
	resp_val, 
	mem_out0, 
	mem_out1, 
	mem_out2);
   input clk;
   input [31:0] req_msg;
   output req_rdy;
   input req_val;
   input reset;
   output [15:0] resp_msg;
   input resp_rdy;
   output resp_val;
   output [6:0] mem_out0;
   output [6:0] mem_out1;
   output [6:0] mem_out2;
   wire [6:0]   data;
   
   // mem0/rd_out -> r1* -> r2* -> r3* -> mem1/wd_in
   DFF_X1 r10 (.D(mem_out0[0]),
	.CK(clk),
	.Q(l1[0]));
   DFF_X1 r11 (.D(mem_out0[1]),
	.CK(clk),
	.Q(l1[1]));
   DFF_X1 r12 (.D(mem_out0[2]),
	.CK(clk),
	.Q(l1[2]));
   DFF_X1 r13 (.D(mem_out0[3]),
	.CK(clk),
	.Q(l1[3]));
   DFF_X1 r14 (.D(mem_out0[4]),
	.CK(clk),
	.Q(l1[4]));
   DFF_X1 r15 (.D(mem_out0[5]),
	.CK(clk),
	.Q(l1[5]));
   DFF_X1 r16 (.D(mem_out0[6]),
	.CK(clk),
	.Q(l1[6]));

   DFF_X1 r20 (.D(l1[0]),
	.CK(clk),
	.Q(l2[0]));
   DFF_X1 r21 (.D(l1[1]),
	.CK(clk),
	.Q(l2[1]));
   DFF_X1 r22 (.D(l1[2]),
	.CK(clk),
	.Q(l2[2]));
   DFF_X1 r23 (.D(l1[3]),
	.CK(clk),
	.Q(l2[3]));
   DFF_X1 r24 (.D(l1[4]),
	.CK(clk),
	.Q(l2[4]));
   DFF_X1 r25 (.D(l1[5]),
	.CK(clk),
	.Q(l2[5]));
   DFF_X1 r26 (.D(l1[6]),
	.CK(clk),
	.Q(l2[6]));
   
   DFF_X1 r30 (.D(l2[0]),
	.CK(clk),
	.Q(l3[0]));
   DFF_X1 r31 (.D(l2[1]),
	.CK(clk),
	.Q(l3[1]));
   DFF_X1 r32 (.D(l2[2]),
	.CK(clk),
	.Q(l3[2]));
   DFF_X1 r33 (.D(l2[3]),
	.CK(clk),
	.Q(l3[3]));
   DFF_X1 r34 (.D(l2[4]),
	.CK(clk),
	.Q(l3[4]));
   DFF_X1 r35 (.D(l2[5]),
	.CK(clk),
	.Q(l3[5]));
   DFF_X1 r36 (.D(l2[6]),
	.CK(clk),
	.Q(l3[6]));

   fakeram45_64x7 mem0 (.clk(clk),
	.rd_out(mem_out0),
	.we_in(_006_),
	.ce_in(_007_),
	.addr_in({ _008_,
		_009_,
		_010_,
		_011_,
		_012_,
		_013_ }),
	.wd_in({ _014_,
		_015_,
		_016_,
		_017_,
		_018_,
		_019_,
		_020_ }),
	.w_mask_in({ _021_,
		_076_,
		_077_,
		_078_,
		_079_,
		_080_,
		_081_ }));
   fakeram45_64x7 mem1 (.clk(clk),
	.rd_out(mem_out1),
	.we_in(_090_),
	.ce_in(_091_),
	.addr_in({ _092_,
		_093_,
		_094_,
		_095_,
		_096_,
		_097_ }),
	.wd_in(l3[6:0]),
	.w_mask_in({ _105_,
		_106_,
		_107_,
		_054_,
		_055_,
		_056_,
		_003_ }));
   fakeram45_64x7 mem2 (.clk(clk),
	.rd_out(mem_out2),
	.we_in(_012_),
	.ce_in(_013_),
	.addr_in({ _014_,
		_015_,
		_016_,
		_017_,
		_018_,
		_019_ }),
	.wd_in({ _020_,
		_021_,
		_076_,
		_077_,
		_078_,
		_079_,
		_080_ }),
	.w_mask_in({ _081_,
		_082_,
		_083_,
		_084_,
		_085_,
		_086_,
		_087_ }));
endmodule
module top();
   wire mid;
   
  INV_X1 \disolved_top/leaf (.ZN(mid));
  block b(.i(mid));
  
endmodule
module block(input i);

  INV_X1 \disolved_block/leaf (.A(i));
  
endmodule
module top (in1, in2, clk1, clk2, clk3, out, reset);
  input in1, in2, clk1, clk2, clk3, reset;
  output out;
  wire r1q, r2q, u1z, u2z;

  sky130_fd_sc_hd__dfrtn_1 r1 (.D(in1), .CLK_N(clk1), .Q(r1q), .RESET_B(reset));
  sky130_fd_sc_hd__dfrtn_1 r2 (.D(in2), .CLK_N(clk2), .Q(r2q), .RESET_B(reset));
  sky130_fd_sc_hd__buf_1 u1 (.A(r2q), .X(u1z));
  sky130_fd_sc_hd__and2_0 u2 (.A(r1q), .B(u1z), .X(u2z));
  sky130_fd_sc_hd__dfrtn_1 r3 (.D(u2z), .CLK_N(clk3), .Q(out), .RESET_B(reset));
endmodule // top
module top (in1, in2, clk1, clk2, clk3, out);
    input in1, in2, clk1, clk2, clk3;
    output out;
    wire r1q, r2q, u1z, u2z;
    MOCK_HYBRID_A r1 (.A1(in1), .A2(clk1), .ZN(r1q));
    MOCK_HYBRID_G u2 (.A1(r1q), .A2(u1z), .ZN(u2z));
    MOCK_HYBRID_AG r2 (.A1(in2), .A2(clk2), .ZN(r2q));
    MOCK_HYBRID_G u1 (.A1(r2q), .A2(u2z), .ZN(u1z));
    MOCK_HYBRID_AG u3 (.A1(u1z), .A2(clk3), .ZN(out));
endmodule // top
module top (in1, in2, clk1, clk2, clk3, out);
  input in1, in2, clk1, clk2, clk3;
  output out;
  wire r1q, r2q, u1z, u2z, u2z0, u2z1;

  DFF_X1 r1 (.D(in1), .CK(clk1), .Q(r1q));
  DFF_X1 r2 (.D(in2), .CK(clk2), .Q(r2q));
  BUF_X1 u1 (.A(r2q), .Z(u1z));
  AND2_X1 u2 (.A1(r1q), .A2(1'b0), .ZN(u2z0));
  AND2_X1 u3 (.A1(u1z), .A2(1'b1), .ZN(u2z1));
  AND2_X1 u4 (.A1(u2z0), .A2(u2z1), .ZN(u2z));
  DFF_X1 r3 (.D(u2z), .CK(clk3), .Q(out));
endmodule // top
module top (in1, in2, clk1, clk2, clk3, out);
  input in1, in2, clk1, clk2, clk3;
  output out;
  wire r1q, r2q, u1z, u2z;

  MOCK_SINGLE r1 (.A1(in1), .A2(clk1), .ZN(r1q));
  MOCK_SINGLE r2 (.A1(in2), .A2(clk2), .ZN(r2q));
  MOCK_DOUBLE u2 (.A1(r1q), .A2(u1z), .ZN(u2z));
  MOCK_DOUBLE r3 (.A1(u2z), .A2(clk3), .ZN(out));
endmodule // top
module top (in1, in2, clk1, clk2, clk3, out);
  input in1, in2, clk1, clk2, clk3;
  output out;
  wire r1q, r2q, u1z, u2z;

  MOCK_SINGLE r1 (.A1(in1), .A2(clk1), .ZN(r1q));
  MOCK_SINGLE r2 (.A1(in2), .A2(clk2), .ZN(r2q));
  MOCK_SINGLE u2 (.A1(r1q), .A2(u1z), .ZN(u2z));
  MOCK_SINGLE r3 (.A1(u2z), .A2(clk3), .ZN(out));
endmodule // top
module top (in1, in2, clk1, clk2, clk3, out);
    input in1, in2, clk1, clk2, clk3;
    output out;
    wire r1q, r2q, u1z, u2z;
    MOCK_HYBRID_A r1 (.A1(in1), .A2(clk1), .ZN(r1q));
    MOCK_HYBRID_G u2 (.A1(r1q), .A2(u1z), .ZN(u2z));
    MOCK_HYBRID_AG r2 (.A1(in2), .A2(clk2), .ZN(r2q));
    MOCK_HYBRID_G u1 (.A1(r2q), .A2(u2z), .ZN(u1z));
    MOCK_HYBRID_GA u3 (.A1(u1z), .A2(clk3), .ZN(out));
endmodule // top
module dummy_slave(
    input wb_clk_i,
    input wb_rst_i,
    
    input wb_stb_i,
    input wb_cyc_i,
    input wb_we_i,
    input [3:0] wb_sel_i,
    input [31:0] wb_adr_i,
    input [31:0] wb_dat_i,
    
    output reg [31:0] wb_dat_o,
    output reg wb_ack_o
);
    reg [31:0] store;

    wire valid = wb_cyc_i & wb_stb_i;

    always @(posedge wb_clk_i) begin
        if (wb_rst_i == 1'b 1) begin
            wb_ack_o <= 1'b 0;
        end else begin
            if (wb_we_i == 1'b 1) begin
                if (wb_sel_i[0]) store[7:0]   <= wb_dat_i[7:0];
                if (wb_sel_i[1]) store[15:8]  <= wb_dat_i[15:8];
                if (wb_sel_i[2]) store[23:16] <= wb_dat_i[23:16];
                if (wb_sel_i[3]) store[31:24] <= wb_dat_i[31:24];
            end
            wb_dat_o <= store;
            wb_ack_o <= valid & !wb_ack_o;
        end
    end
endmodule
module sky130_fd_io__top_xres4v2 ( TIE_WEAK_HI_H,  XRES_H_N, TIE_HI_ESD, TIE_LO_ESD,
                                   AMUXBUS_A, AMUXBUS_B, PAD, PAD_A_ESD_H, ENABLE_H, EN_VDDIO_SIG_H, INP_SEL_H, FILT_IN_H,
                                   DISABLE_PULLUP_H, PULLUP_H, ENABLE_VDDIO
                                   ,VCCD, VCCHIB, VDDA, VDDIO,VDDIO_Q, VSSA, VSSD, VSSIO, VSSIO_Q, VSWITCH
                                 );
output XRES_H_N;
inout AMUXBUS_A;
inout AMUXBUS_B;
inout PAD;
input DISABLE_PULLUP_H;
input ENABLE_H;
input EN_VDDIO_SIG_H;
input INP_SEL_H;
input FILT_IN_H;
inout PULLUP_H;
input ENABLE_VDDIO;
input VCCD;
input VCCHIB;
input VDDA;
input VDDIO;
input VDDIO_Q;
input VSSA;
input VSSD;
input VSSIO;
input VSSIO_Q;
input VSWITCH;
inout PAD_A_ESD_H;
output TIE_HI_ESD;
output TIE_LO_ESD;
inout TIE_WEAK_HI_H;
endmodule
module digital_pll_controller(reset, clock, osc, div, trim);
    input reset;
    input clock;
    input osc;
    input [4:0] div;
    output [25:0] trim;		// Use ring_osc2x13, with 26 trim bits

    wire [25:0] trim;
    reg [2:0] oscbuf;
    reg [2:0] prep;

    reg [4:0] count0;
    reg [4:0] count1;
    reg [6:0] tval;	// Includes 2 bits fractional
    wire [4:0] tint;	// Integer part of the above

    wire [5:0] sum;

    assign sum = count0 + count1;
 
    // Integer to thermometer code (maybe there's an algorithmic way?)
    assign tint = tval[6:2];
                                     // |<--second-->|<-- first-->|
    assign trim = (tint == 5'd0)  ? 26'b0000000000000_0000000000000 :
          (tint == 5'd1)  ? 26'b0000000000000_0000000000001 :
          (tint == 5'd2)  ? 26'b0000000000000_0000001000001 :
          (tint == 5'd3)  ? 26'b0000000000000_0010001000001 :
          (tint == 5'd4)  ? 26'b0000000000000_0010001001001 :
          (tint == 5'd5)  ? 26'b0000000000000_0010101001001 :
          (tint == 5'd6)  ? 26'b0000000000000_1010101001001 :
          (tint == 5'd7)  ? 26'b0000000000000_1010101101001 :
          (tint == 5'd8)  ? 26'b0000000000000_1010101101101 :
          (tint == 5'd9)  ? 26'b0000000000000_1011101101101 :
          (tint == 5'd10) ? 26'b0000000000000_1011101111101 :
          (tint == 5'd11) ? 26'b0000000000000_1111101111101 :
          (tint == 5'd12) ? 26'b0000000000000_1111101111111 :
          (tint == 5'd13) ? 26'b0000000000000_1111111111111 :
          (tint == 5'd14) ? 26'b0000000000001_1111111111111 :
          (tint == 5'd15) ? 26'b0000001000001_1111111111111 :
          (tint == 5'd16) ? 26'b0010001000001_1111111111111 :
          (tint == 5'd17) ? 26'b0010001001001_1111111111111 :
          (tint == 5'd18) ? 26'b0010101001001_1111111111111 :
          (tint == 5'd19) ? 26'b1010101001001_1111111111111 :
          (tint == 5'd20) ? 26'b1010101101001_1111111111111 :
          (tint == 5'd21) ? 26'b1010101101101_1111111111111 :
          (tint == 5'd22) ? 26'b1011101101101_1111111111111 :
          (tint == 5'd23) ? 26'b1011101111101_1111111111111 :
          (tint == 5'd24) ? 26'b1111101111101_1111111111111 :
          (tint == 5'd25) ? 26'b1111101111111_1111111111111 :
                    26'b1111111111111_1111111111111;
   
    always @(posedge clock or posedge reset) begin
    if (reset == 1'b1) begin
        tval <= 7'd0;	// Note:  trim[0] must be zero for startup to work.
        oscbuf <= 3'd0;
        prep <= 3'd0;
        count0 <= 5'd0;
        count1 <= 5'd0;

    end else begin
        oscbuf <= {oscbuf[1:0], osc};

        if (oscbuf[2] != oscbuf[1]) begin
        count1 <= count0;
        count0 <= 5'b00001;
        prep <= {prep[1:0], 1'b1};

        if (prep == 3'b111) begin
            if (sum > div) begin
		if (tval < 127) begin
            	    tval <= tval + 1;
		end
            end else if (sum < div) begin
		if (tval > 0) begin
            	    tval <= tval - 1;
		end
            end
        end
        end else begin
        if (count0 != 5'b11111) begin
                count0 <= count0 + 1;
        end
        end
    end
    end

endmodule	// digital_pll_controller
module BYTE (
`ifdef USE_POWER_PINS
    input VPWR,
    input VGND,
`endif
    input CLK,
    input WE,
    input SEL,
    input [7:0] Di,
    output [7:0] Do
);

    wire [7:0]  q_wire;
    wire        we_wire;
    wire        SEL_B;
    wire        GCLK;

    sky130_fd_sc_hd__inv_1 INV(
     `ifdef USE_POWER_PINS
        .VPWR(VPWR),
        .VGND(VGND),
        .VPB(VPWR),
        .VNB(VGND),
    `endif
        .Y(SEL_B),
        .A(SEL)
    );

    sky130_fd_sc_hd__and2_1 CGAND( 
    `ifdef USE_POWER_PINS
        .VPWR(VPWR),
        .VGND(VGND),
        .VPB(VPWR),
        .VNB(VGND),
    `endif
        .A(SEL),
        .B(WE),
        .X(we_wire)
    );

    sky130_fd_sc_hd__dlclkp_1 CG( 
    `ifdef USE_POWER_PINS
        .VPWR(VPWR),
        .VGND(VGND),
        .VPB(VPWR),
        .VNB(VGND),
    `endif
        .CLK(CLK),
        .GCLK(GCLK),
        .GATE(we_wire) 
    );

    generate 
        genvar i;
        for(i=0; i<8; i=i+1) begin : BIT
            sky130_fd_sc_hd__dfxtp_1 FF (
            `ifdef USE_POWER_PINS
                .VPWR(VPWR),
                .VGND(VGND),
                .VPB(VPWR),
                .VNB(VGND),
            `endif 
                .D(Di[i]),
                .Q(q_wire[i]),
                .CLK(GCLK)
            );

            sky130_fd_sc_hd__ebufn_2 OBUF ( 
            `ifdef USE_POWER_PINS
                .VPWR(VPWR),
                .VGND(VGND),
                .VPB(VPWR),
                .VNB(VGND),
            `endif
                .A(q_wire[i]),
                .Z(Do[i]),
                .TE_B(SEL_B)
            );

        end
    endgenerate 

endmodule
module WORD32 (
`ifdef USE_POWER_PINS
    input VPWR,
    input VGND,
`endif
    input CLK,
    input [3:0] WE,
    input SEL,
    input [31:0] Di,
    output [31:0] Do
);

    BYTE B0 (
    `ifdef USE_POWER_PINS
        .VPWR(VPWR),
        .VGND(VGND),
    `endif 
        .CLK(CLK), .WE(WE[0]), .SEL(SEL), .Di(Di[7:0]), .Do(Do[7:0]) );
    
    BYTE B1 ( 
    `ifdef USE_POWER_PINS
        .VPWR(VPWR), 
        .VGND(VGND),
    `endif
        .CLK(CLK), .WE(WE[1]), .SEL(SEL), .Di(Di[15:8]), .Do(Do[15:8]) );
    
    BYTE B2 ( 
    `ifdef USE_POWER_PINS
        .VPWR(VPWR),
        .VGND(VGND),
    `endif
        .CLK(CLK), .WE(WE[2]), .SEL(SEL), .Di(Di[23:16]), .Do(Do[23:16]) );
    
    BYTE B3 ( 
    `ifdef USE_POWER_PINS
        .VPWR(VPWR),
        .VGND(VGND),
    `endif
        .CLK(CLK), .WE(WE[3]), .SEL(SEL), .Di(Di[31:24]), .Do(Do[31:24]) );
    
endmodule
module DEC1x2 (
`ifdef USE_POWER_PINS
    input VPWR,
    input VGND,
`endif
    input           EN,
    input   [0:0]   A,
    output  [1:0]   SEL
);
    sky130_fd_sc_hd__and2b_2    AND1 ( 
     `ifdef USE_POWER_PINS
        .VPWR(VPWR),
        .VGND(VGND),
        .VPB(VPWR),
        .VNB(VGND),
    `endif
        .X(SEL[0]),
        .A_N(A),
        .B(EN)
    );

    sky130_fd_sc_hd__and2_2     AND3 ( 
    `ifdef USE_POWER_PINS
        .VPWR(VPWR),
        .VGND(VGND),
        .VPB(VPWR),
        .VNB(VGND),
    `endif
        .X(SEL[1]),
        .A(A),
        .B(A[0])
    );
    
endmodule
module DEC2x4 (
`ifdef USE_POWER_PINS
    input VPWR,
    input VGND,
`endif
    input           EN,
    input   [1:0]   A,
    output  [3:0]   SEL
);
    sky130_fd_sc_hd__nor3b_4    AND0 ( 
     `ifdef USE_POWER_PINS
        .VPWR(VPWR),
        .VGND(VGND),
        .VPB(VPWR),
        .VNB(VGND),
    `endif
        .Y(SEL[0]),
        .A(A[0]),
        .B(A[1]),
        .C_N(EN)
    );

    sky130_fd_sc_hd__and3b_4    AND1 (
     `ifdef USE_POWER_PINS
        .VPWR(VPWR),
        .VGND(VGND),
        .VPB(VPWR),
        .VNB(VGND),
    `endif 
        .X(SEL[1]),
        .A_N(A[1]),
        .B(A[0]),
        .C(EN) 
    );

    sky130_fd_sc_hd__and3b_4    AND2 ( 
     `ifdef USE_POWER_PINS
        .VPWR(VPWR),
        .VGND(VGND),
        .VPB(VPWR),
        .VNB(VGND),
    `endif
        .X(SEL[2]),
        .A_N(A[0]),
        .B(A[1]),
        .C(EN)
    );
   
    sky130_fd_sc_hd__and3_4     AND3 ( 
     `ifdef USE_POWER_PINS
        .VPWR(VPWR),
        .VGND(VGND),
        .VPB(VPWR),
        .VNB(VGND),
    `endif
        .X(SEL[3]),
        .A(A[1]),
        .B(A[0]),
        .C(EN) 
    );
    
endmodule