dakies/OSS_Verilog huggingface dataset:
module tb_nand;
    reg a, b;
    wire nand_out;
         
    demux_nand dut(a, b, nand_out);
    initial begin
            a= 1'b0; b= 1'b0;
        #10 a= 1'b0; b= 1'b1;
        #10 a= 1'b1; b= 1'b0;
        #10 a= 1'b1; b= 1'b1;
    end
    initial 
     begin $monitor("a: %b  b: %b  nand: %b ",a, b, nand_out);
     #40 $finish;
     end
endmodule
module star_pattern_2;

integer i,j;

initial begin

	for(i=1;i<10;i=i+1)begin
	    for(j=1;j<10-i;j=j+1)begin
		$write("*");
	    end
	  $display("");
	end
    end
endmodule
module star_pattern_1;

integer i,j;

initial begin

    for(i=1; i<10; i=i+1) begin
        for(j=1; j<=i; j=j+1) begin
		$write("*");
	  end
	$display("");
	end
    end
endmodule
module number_pattern_1;

integer i,j;

initial begin
    for(i=0; i<10; i=i+1) begin
	  for(j=0; j<=i; j=j+1) begin
	      $write("%0d  ",j+1);
	  end
      $display("");
    end
  end
endmodule
module number_pattern_4;

integer i,j;

integer n=1;

initial begin

	for(i=0;i<=9;i=i+1)begin
	    for(j=0;j<9-i;j=j+1)begin
		$write("%0d  ",n+i);
	    end
	  $display("");
	end
    end
endmodule
module number_pattern_3;

integer i,j;

integer n=1;

initial begin

	for(i=0;i<=8;i=i+1)begin
	    for(j=0;j<=i;j=j+1)begin
		$write("%0d  ",n+i);
	    end
	  $display("");
	end
    end
endmodule
module number_pattern_2;

integer i,j;

initial begin
	for(i=0;i<=10;i=i+1)begin
	    for(j=1;j<=10-i;j=j+1)begin
		$write("%0d  ",j);
	    end
	  $display("");
	end
    end
endmodule
module test_input_2;

// Parameters
parameter DATA_WIDTH = 8;
parameter LABEL_WIDTH = 1;
parameter SIGNED = 1;
parameter ASCENDING = 1;

// Inputs
reg clk = 0;
reg rst = 0;
reg x_valid = 0;
reg [DATA_WIDTH-1 : 0] x_0 = 0;
reg [DATA_WIDTH-1 : 0] x_1 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_0 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_1 = 0;

// Outputs
wire [DATA_WIDTH-1 : 0] y_0;
wire [DATA_WIDTH-1 : 0] y_1;
wire [LABEL_WIDTH-1 : 0] y_label_0;
wire [LABEL_WIDTH-1 : 0] y_label_1;
wire y_valid;

initial begin
    // myhdl integration
    $from_myhdl(
        clk,
        rst,
	x_0,
	x_1,
	x_label_0,
	x_label_1,
        x_valid
        );
    $to_myhdl(
        y_0,
	y_1,
	y_label_0,
	y_label_1,
        y_valid
    );

    // dump file
    $dumpfile("test_input_2.lxt");
    $dumpvars(0, test_input_2);
end

input_2 #(
    .DATA_WIDTH(DATA_WIDTH),
    .LABEL_WIDTH(LABEL_WIDTH),
    .SIGNED(SIGNED),
    .ASCENDING(ASCENDING)
)
UUT (
    .clk(clk),
    .rst(rst),
    .x_valid(x_valid),
    .x_0(x_0),
    .x_1(x_1),
    .x_label_0(x_label_0),
    .x_label_1(x_label_1),
    .y_0(y_0),
    .y_1(y_1),
    .y_label_0(y_label_0),
    .y_label_1(y_label_1),
    .y_valid(y_valid)
);

endmodule
module bitonic_sorting_top #
(
    parameter LOG_INPUT_NUM = 4, // Eg: If LOG_INPUT_NUM=4, then input number is 2**4=16 
    parameter DATA_WIDTH = 8,
    parameter LABEL_WIDTH = LOG_INPUT_NUM,
    parameter SIGNED = 0,
    parameter ASCENDING = 1

)
(
    input clk, rst, x_valid,
    // Put all the inputs into one vector.
    // x[DATA_WIDTH-1 : 0] is the first input x_0, 
    // x[DATA_WIDTH*2-1 : DATA_WIDTH] is the second input x_1, etc.
    input [DATA_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] x,
    input [LABEL_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] x_label,
    output [DATA_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] y,
    output [LABEL_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] y_label,
    output y_valid
);

bitonic_sorting_recursion # 
(
    .LOG_INPUT_NUM(LOG_INPUT_NUM),
    .DATA_WIDTH(DATA_WIDTH),
    .LABEL_WIDTH(LABEL_WIDTH),
    .SIGNED(SIGNED),
    .ASCENDING(ASCENDING)
)
bitonic_sorting_inst
(
    .clk(clk),
    .rst(rst),
    .x_valid(x_valid),
    .x(x),
    .x_label(x_label),
    .y(y),
    .y_label(y_label),
    .y_valid(y_valid)
);


endmodule
module input_2 #
(
    parameter DATA_WIDTH = 8,
    parameter LABEL_WIDTH = 1,
    parameter SIGNED = 0,
    parameter ASCENDING = 1
)
(
    input clk, rst, x_valid,
    input [DATA_WIDTH-1 : 0] x_0, x_1,
    input [LABEL_WIDTH-1 : 0] x_label_0, x_label_1,
    output reg [DATA_WIDTH-1 : 0] y_0, y_1,
    output reg [LABEL_WIDTH-1 : 0] y_label_0, y_label_1,
    output reg y_valid
);

always @ (posedge clk)
begin
    if (rst == 1'b1) begin
        y_0 <= 0;
        y_1 <= 0;
        y_valid <= 0;
    end else begin
        y_valid <= x_valid;
        if (SIGNED == 0) begin
            if (ASCENDING == 1) begin
                if ($unsigned(x_0) < $unsigned(x_1)) begin
                    y_0 <= x_0;
                    y_label_0 <= x_label_0;
                    y_1 <= x_1;
                    y_label_1 <= x_label_1;
                end else begin
                    y_0 <= x_1;
                    y_label_0 <= x_label_1;
                    y_1 <= x_0;
                    y_label_1 <= x_label_0;
                end
            end else if (ASCENDING == 0) begin
                if ($unsigned(x_0) > $unsigned(x_1)) begin
                    y_0 <= x_0;
                    y_label_0 <= x_label_0;
                    y_1 <= x_1;
                    y_label_1 <= x_label_1;
                end else begin
                    y_0 <= x_1;
                    y_label_0 <= x_label_1;
                    y_1 <= x_0;
                    y_label_1 <= x_label_0;
                end
            end
        end else if (SIGNED == 1) begin
            if (ASCENDING == 1) begin
                if ($signed(x_0) < $signed(x_1)) begin
                    y_0 <= x_0;
                    y_label_0 <= x_label_0;
                    y_1 <= x_1;
                    y_label_1 <= x_label_1;
                end else begin
                    y_0 <= x_1;
                    y_label_0 <= x_label_1;
                    y_1 <= x_0;
                    y_label_1 <= x_label_0;
                end
            end else if (ASCENDING == 0) begin
                if ($signed(x_0) > $signed(x_1)) begin
                    y_0 <= x_0;
                    y_label_0 <= x_label_0;
                    y_1 <= x_1;
                    y_label_1 <= x_label_1;
                end else begin
                    y_0 <= x_1;
                    y_label_0 <= x_label_1;
                    y_1 <= x_0;
                    y_label_1 <= x_label_0;
                end
            end
        end
    end
end

endmodule
module test_input_4;

// Parameters
parameter DATA_WIDTH = 8;
parameter LABEL_WIDTH = 2;
parameter SIGNED = 1;
parameter ASCENDING = 0;

// Inputs
reg clk = 0;
reg rst = 0;
reg x_valid = 0;
reg [DATA_WIDTH-1 : 0] x_0 = 0;
reg [DATA_WIDTH-1 : 0] x_1 = 0;
reg [DATA_WIDTH-1 : 0] x_2 = 0;
reg [DATA_WIDTH-1 : 0] x_3 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_0 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_1 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_2 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_3 = 0;

// Outputs
wire [DATA_WIDTH-1 : 0] y_0;
wire [DATA_WIDTH-1 : 0] y_1;
wire [DATA_WIDTH-1 : 0] y_2;
wire [DATA_WIDTH-1 : 0] y_3;
wire [LABEL_WIDTH-1 : 0] y_label_0;
wire [LABEL_WIDTH-1 : 0] y_label_1;
wire [LABEL_WIDTH-1 : 0] y_label_2;
wire [LABEL_WIDTH-1 : 0] y_label_3;
wire y_valid;

initial begin
    // myhdl integration
    $from_myhdl(
        clk,
        rst,
	x_0,
	x_1,
	x_2,
	x_3,
	x_label_0,
	x_label_1,
	x_label_2,
	x_label_3,
        x_valid
        );
    $to_myhdl(
        y_0,
	y_1,
        y_2,
	y_3,
	y_label_0,
	y_label_1,
	y_label_2,
	y_label_3,
        y_valid
    );

    // dump file
    $dumpfile("test_input_4.lxt");
    $dumpvars(0, test_input_4);
end

input_4 #(
    .DATA_WIDTH(DATA_WIDTH),
    .LABEL_WIDTH(LABEL_WIDTH),
    .SIGNED(SIGNED),
    .ASCENDING(ASCENDING)
)
UUT (
    .clk(clk),
    .rst(rst),
    .x_valid(x_valid),
    .x_0(x_0),
    .x_1(x_1),
    .x_2(x_2),
    .x_3(x_3),
    .x_label_0(x_label_0),
    .x_label_1(x_label_1),
    .x_label_2(x_label_2),
    .x_label_3(x_label_3),
    .y_0(y_0),
    .y_1(y_1),
    .y_2(y_2),
    .y_3(y_3),
    .y_label_0(y_label_0),
    .y_label_1(y_label_1),
    .y_label_2(y_label_2),
    .y_label_3(y_label_3),
    .y_valid(y_valid)
);

endmodule
module test_input_8;

// Parameters
parameter DATA_WIDTH = 8;
parameter LABEL_WIDTH = 3;
parameter SIGNED = 1;
parameter ASCENDING = 0;

// Inputs
reg clk = 0;
reg rst = 0;
reg x_valid = 0;
reg [DATA_WIDTH-1 : 0] x_0 = 0;
reg [DATA_WIDTH-1 : 0] x_1 = 0;
reg [DATA_WIDTH-1 : 0] x_2 = 0;
reg [DATA_WIDTH-1 : 0] x_3 = 0;
reg [DATA_WIDTH-1 : 0] x_4 = 0;
reg [DATA_WIDTH-1 : 0] x_5 = 0;
reg [DATA_WIDTH-1 : 0] x_6 = 0;
reg [DATA_WIDTH-1 : 0] x_7 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_0 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_1 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_2 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_3 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_4 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_5 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_6 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_7 = 0;

// Outputs
wire [DATA_WIDTH-1 : 0] y_0;
wire [DATA_WIDTH-1 : 0] y_1;
wire [DATA_WIDTH-1 : 0] y_2;
wire [DATA_WIDTH-1 : 0] y_3;
wire [DATA_WIDTH-1 : 0] y_4;
wire [DATA_WIDTH-1 : 0] y_5;
wire [DATA_WIDTH-1 : 0] y_6;
wire [DATA_WIDTH-1 : 0] y_7;
wire [LABEL_WIDTH-1 : 0] y_label_0;
wire [LABEL_WIDTH-1 : 0] y_label_1;
wire [LABEL_WIDTH-1 : 0] y_label_2;
wire [LABEL_WIDTH-1 : 0] y_label_3;
wire [LABEL_WIDTH-1 : 0] y_label_4;
wire [LABEL_WIDTH-1 : 0] y_label_5;
wire [LABEL_WIDTH-1 : 0] y_label_6;
wire [LABEL_WIDTH-1 : 0] y_label_7;
wire y_valid;

initial begin
    // myhdl integration
    $from_myhdl(
        clk,
        rst,
	x_0,
	x_1,
	x_2,
	x_3,
	x_4,
	x_5,
	x_6,
	x_7,
	x_label_0,
	x_label_1,
	x_label_2,
	x_label_3,
	x_label_4,
	x_label_5,
	x_label_6,
	x_label_7,
        x_valid
        );
    $to_myhdl(
        y_0,
	y_1,
        y_2,
	y_3,
        y_4,
	y_5,
        y_6,
	y_7,
	y_label_0,
	y_label_1,
	y_label_2,
	y_label_3,
	y_label_4,
	y_label_5,
	y_label_6,
	y_label_7,
        y_valid
    );

    // dump file
    $dumpfile("test_input_8.lxt");
    $dumpvars(0, test_input_8);
end

input_8 #(
    .DATA_WIDTH(DATA_WIDTH),
    .LABEL_WIDTH(LABEL_WIDTH),
    .SIGNED(SIGNED),
    .ASCENDING(ASCENDING)
)
UUT (
    .clk(clk),
    .rst(rst),
    .x_valid(x_valid),
    .x({x_7, x_6, x_5, x_4, x_3, x_2, x_1, x_0}),
    .x_label({x_label_7, x_label_6, x_label_5, x_label_4, x_label_3, x_label_2, x_label_1, x_label_0}),
    .y({y_7, y_6, y_5, y_4, y_3, y_2, y_1, y_0}),
    .y_label({y_label_7, y_label_6, y_label_5, y_label_4, y_label_3, y_label_2, y_label_1, y_label_0}),
    .y_valid(y_valid)
);

endmodule
module input_4 #
(
    parameter DATA_WIDTH = 8,
    parameter LABEL_WIDTH = 1,
    parameter SIGNED = 0,
    parameter ASCENDING = 1
)
(
    input clk, rst, x_valid,
    input [DATA_WIDTH-1 : 0] x_0, x_1, x_2, x_3,
    input [LABEL_WIDTH-1 : 0] x_label_0, x_label_1, x_label_2, x_label_3,
    output [DATA_WIDTH-1 : 0] y_0, y_1, y_2, y_3,
    output [LABEL_WIDTH-1 : 0] y_label_0, y_label_1, y_label_2, y_label_3,
    output y_valid
);

// Declare the wires which come out of the input_2 compare network of every stage
wire [DATA_WIDTH-1 : 0] stage0_rslt_0, stage0_rslt_1, stage0_rslt_2, stage0_rslt_3;
wire [LABEL_WIDTH-1: 0] stage0_labl_0, stage0_labl_1, stage0_labl_2, stage0_labl_3;
wire stage0_valid;


// Stage 1, use two 2-input comparators with opposite ascending features to sort.
// Stage0_0 has the same ascending feature with the entire network output.
// Stage0_1 has the opposite ascending feature with the entire network output.
input_2 #
(
    .DATA_WIDTH(DATA_WIDTH),
    .LABEL_WIDTH(LABEL_WIDTH),
    .SIGNED(SIGNED),
    .ASCENDING(ASCENDING)
)
input_2_stage0_0 
(
    .clk(clk),
    .rst(rst),
    .x_valid(x_valid),
    .x_0(x_0),
    .x_1(x_1),
    .x_label_0(x_label_0),
    .x_label_1(x_label_1),
    .y_0(stage0_rslt_0),
    .y_1(stage0_rslt_1),
    .y_label_0(stage0_labl_0),
    .y_label_1(stage0_labl_1),
    .y_valid(stage0_valid)
);

input_2 #
(
    .DATA_WIDTH(DATA_WIDTH),
    .LABEL_WIDTH(LABEL_WIDTH),
    .SIGNED(SIGNED),
    .ASCENDING(1-ASCENDING)
)
input_2_stage0_1 
(
    .clk(clk),
    .rst(rst),
    .x_valid(x_valid),
    .x_0(x_2),
    .x_1(x_3),
    .x_label_0(x_label_2),
    .x_label_1(x_label_3),
    .y_0(stage0_rslt_2),
    .y_1(stage0_rslt_3),
    .y_label_0(stage0_labl_2),
    .y_label_1(stage0_labl_3),
    .y_valid()
);

// Stage 2, use a 4-input bitonic required compare network to sort the outputs of the stage 1.
// input_4_bitonic_required module should have the same ascending feature with the entire network output.
input_4_bitonic_required #
(
    .DATA_WIDTH(DATA_WIDTH),
    .LABEL_WIDTH(LABEL_WIDTH),
    .SIGNED(SIGNED),
    .ASCENDING(ASCENDING)
)
input_4_stage1_0 
(
    .clk(clk),
    .rst(rst),
    .x_valid(stage0_valid),
    .x_0(stage0_rslt_0),
    .x_1(stage0_rslt_1),
    .x_2(stage0_rslt_2),
    .x_3(stage0_rslt_3),
    .x_label_0(stage0_labl_0),
    .x_label_1(stage0_labl_1),
    .x_label_2(stage0_labl_2),
    .x_label_3(stage0_labl_3),
    .y_0(y_0),
    .y_1(y_1),
    .y_2(y_2),
    .y_3(y_3),
    .y_label_0(y_label_0),
    .y_label_1(y_label_1),
    .y_label_2(y_label_2),
    .y_label_3(y_label_3),
    .y_valid(y_valid)
);


endmodule
module input_16 #
(
    parameter DATA_WIDTH = 8,
    parameter LABEL_WIDTH = 1,
    parameter SIGNED = 0,
    parameter ASCENDING = 1
)
(
    input clk, rst, x_valid,
    input [DATA_WIDTH*16-1 : 0] x,
    input [LABEL_WIDTH*16-1 : 0] x_label,
    output [DATA_WIDTH*16-1 : 0] y,
    output [LABEL_WIDTH*16-1 : 0] y_label,
    output y_valid
);

// Declare the wires which come out of the input_2 compare network of every stage
wire [DATA_WIDTH*16-1 : 0] stage0_rslt;
wire [LABEL_WIDTH*16-1: 0] stage0_labl;
wire stage0_valid;


// Stage 1, use two 8-input comparators with opposite ascending features to sort.
// Stage0_0 has the same ascending feature with the entire network output.
// Stage0_1 has the opposite ascending feature with the entire network output.
input_8 #
(
    .DATA_WIDTH(DATA_WIDTH),
    .LABEL_WIDTH(LABEL_WIDTH),
    .SIGNED(SIGNED),
    .ASCENDING(ASCENDING)
)
input_8_stage0_0 
(
    .clk(clk),
    .rst(rst),
    .x_valid(x_valid),
    .x(x[DATA_WIDTH*8-1:0]),
    .x_label(x_label[LABEL_WIDTH*8-1:0]),
    .y(stage0_rslt[DATA_WIDTH*8-1:0]),
    .y_label(stage0_labl[LABEL_WIDTH*8-1:0]),
    .y_valid(stage0_valid)
);

input_8 #
(
    .DATA_WIDTH(DATA_WIDTH),
    .LABEL_WIDTH(LABEL_WIDTH),
    .SIGNED(SIGNED),
    .ASCENDING(1-ASCENDING)
)
input_8_stage0_1 
(
    .clk(clk),
    .rst(rst),
    .x_valid(x_valid),
    .x(x[DATA_WIDTH*16-1:DATA_WIDTH*8]),
    .x_label(x_label[LABEL_WIDTH*16-1:LABEL_WIDTH*8]),
    .y(stage0_rslt[DATA_WIDTH*16-1:DATA_WIDTH*8]),
    .y_label(stage0_labl[LABEL_WIDTH*16-1:LABEL_WIDTH*8]),
    .y_valid()
);

// Stage 2, use a 8-input bitonic required compare network to sort the outputs of the stage 1.
// input_8_bitonic_required module should have the same ascending feature with the entire network output.
input_16_bitonic_required #
(
    .DATA_WIDTH(DATA_WIDTH),
    .LABEL_WIDTH(LABEL_WIDTH),
    .SIGNED(SIGNED),
    .ASCENDING(ASCENDING)
)
input_16_stage1_0 
(
    .clk(clk),
    .rst(rst),
    .x_valid(stage0_valid),
    .x(stage0_rslt),
    .x_label(stage0_labl),
    .y(y),
    .y_label(y_label),
    .y_valid(y_valid)
);


endmodule
module input_16_bitonic_required #
(
    parameter DATA_WIDTH = 8,
    parameter LABEL_WIDTH = 4,
    parameter SIGNED = 0,
    parameter ASCENDING = 1
)
(
    input clk, rst, x_valid,
    // Put all the inputs into one vector.
    // x[DATA_WIDTH-1 : 0] is the first input x_0, 
    // x[DATA_WIDTH*2-1 : DATA_WIDTH] is the second input x_1, etc.
    input [DATA_WIDTH*16-1 : 0] x,
    input [LABEL_WIDTH*16-1 : 0] x_label,
    output [DATA_WIDTH*16-1 : 0] y,
    output [LABEL_WIDTH*16-1 : 0] y_label,
    output y_valid
);

// Declare the wires which come out of the input_2 compare network of every stage
wire [DATA_WIDTH*16-1 : 0] stage0_rslt;
wire [LABEL_WIDTH*16-1: 0] stage0_labl;
wire stage0_valid;
genvar i;


// Stage 1
// Stage0_0~7 has the same ascending feature with the entire network output.
for ( i = 0; i < 8; i = i + 1) begin: stage0
    input_2 #
    (
        .DATA_WIDTH(DATA_WIDTH),
        .LABEL_WIDTH(LABEL_WIDTH),
        .SIGNED(SIGNED),
        .ASCENDING(ASCENDING)
    )
    input_2_stage0
    (
        .clk(clk),
        .rst(rst),
        .x_valid(x_valid),
        .x_0(x[DATA_WIDTH*(i+1)-1:DATA_WIDTH*i]),
        .x_1(x[DATA_WIDTH*(i+9)-1:DATA_WIDTH*(i+8)]),
        .x_label_0(x_label[LABEL_WIDTH*(i+1)-1:LABEL_WIDTH*i]),
        .x_label_1(x_label[LABEL_WIDTH*(i+9)-1:LABEL_WIDTH*(i+8)]),
        .y_0(stage0_rslt[DATA_WIDTH*(i+1)-1:DATA_WIDTH*i]),
        .y_1(stage0_rslt[DATA_WIDTH*(i+9)-1:DATA_WIDTH*(i+8)]),
        .y_label_0(stage0_labl[LABEL_WIDTH*(i+1)-1:LABEL_WIDTH*i]),
        .y_label_1(stage0_labl[LABEL_WIDTH*(i+9)-1:LABEL_WIDTH*(i+8)]),
        .y_valid(stage0_valid)
    );
end

// Stage 2
// Stage1_0 has the same ascending feature with the entire network output.
// Stage1_1 has the same ascending feature with the entire network output as well.
input_8_bitonic_required #
(
    .DATA_WIDTH(DATA_WIDTH),
    .LABEL_WIDTH(LABEL_WIDTH),
    .SIGNED(SIGNED),
    .ASCENDING(ASCENDING)
)
input_8_stage1_0 
(
    .clk(clk),
    .rst(rst),
    .x_valid(stage0_valid),
    .x(stage0_rslt[DATA_WIDTH*8-1:0]),
    .x_label(stage0_labl[LABEL_WIDTH*8-1:0]),
    .y(y[DATA_WIDTH*8-1:0]),
    .y_label(y_label[LABEL_WIDTH*8-1:0]),
    .y_valid(y_valid)
);

input_8_bitonic_required #
(
    .DATA_WIDTH(DATA_WIDTH),
    .LABEL_WIDTH(LABEL_WIDTH),
    .SIGNED(SIGNED),
    .ASCENDING(ASCENDING)
)
input_8_stage1_1 
(
    .clk(clk),
    .rst(rst),
    .x_valid(stage0_valid),
    .x(stage0_rslt[DATA_WIDTH*16-1:DATA_WIDTH*8]),
    .x_label(stage0_labl[LABEL_WIDTH*16-1:LABEL_WIDTH*8]),
    .y(y[DATA_WIDTH*16-1:DATA_WIDTH*8]),
    .y_label(y_label[LABEL_WIDTH*16-1:LABEL_WIDTH*8]),
    .y_valid()
);


endmodule
module input_4_bitonic_required #
(
    parameter DATA_WIDTH = 8,
    parameter LABEL_WIDTH = 1,
    parameter SIGNED = 0,
    parameter ASCENDING = 1
)
(
    input clk, rst, x_valid,
    input [DATA_WIDTH-1 : 0] x_0, x_1, x_2, x_3,
    input [LABEL_WIDTH-1 : 0] x_label_0, x_label_1, x_label_2, x_label_3,
    output [DATA_WIDTH-1 : 0] y_0, y_1, y_2, y_3,
    output [LABEL_WIDTH-1 : 0] y_label_0, y_label_1, y_label_2, y_label_3,
    output y_valid
);

// Declare the wires which come out of the input_2 compare network of every stage
wire [DATA_WIDTH-1 : 0] stage0_rslt_0, stage0_rslt_1, stage0_rslt_2, stage0_rslt_3;
wire [LABEL_WIDTH-1: 0] stage0_labl_0, stage0_labl_1, stage0_labl_2, stage0_labl_3;
wire stage0_valid;


// Stage 1
// Stage0_0 has the same ascending feature with the entire network output.
// Stage0_1 has the same ascending feature with the entire network output as well.
input_2 #
(
    .DATA_WIDTH(DATA_WIDTH),
    .LABEL_WIDTH(LABEL_WIDTH),
    .SIGNED(SIGNED),
    .ASCENDING(ASCENDING)
)
input_2_stage0_0 
(
    .clk(clk),
    .rst(rst),
    .x_valid(x_valid),
    .x_0(x_0),
    .x_1(x_2),
    .x_label_0(x_label_0),
    .x_label_1(x_label_2),
    .y_0(stage0_rslt_0),
    .y_1(stage0_rslt_2),
    .y_label_0(stage0_labl_0),
    .y_label_1(stage0_labl_2),
    .y_valid(stage0_valid)
);

input_2 #
(
    .DATA_WIDTH(DATA_WIDTH),
    .LABEL_WIDTH(LABEL_WIDTH),
    .SIGNED(SIGNED),
    .ASCENDING(ASCENDING)
)
input_2_stage0_1 
(
    .clk(clk),
    .rst(rst),
    .x_valid(x_valid),
    .x_0(x_1),
    .x_1(x_3),
    .x_label_0(x_label_1),
    .x_label_1(x_label_3),
    .y_0(stage0_rslt_1),
    .y_1(stage0_rslt_3),
    .y_label_0(stage0_labl_1),
    .y_label_1(stage0_labl_3),
    .y_valid()
);

// Stage 2
// Stage1_0 has the same ascending feature with the entire network output.
// Stage1_1 has the same ascending feature with the entire network output as well.
input_2 #
(
    .DATA_WIDTH(DATA_WIDTH),
    .LABEL_WIDTH(LABEL_WIDTH),
    .SIGNED(SIGNED),
    .ASCENDING(ASCENDING)
)
input_2_stage1_0 
(
    .clk(clk),
    .rst(rst),
    .x_valid(stage0_valid),
    .x_0(stage0_rslt_0),
    .x_1(stage0_rslt_1),
    .x_label_0(stage0_labl_0),
    .x_label_1(stage0_labl_1),
    .y_0(y_0),
    .y_1(y_1),
    .y_label_0(y_label_0),
    .y_label_1(y_label_1),
    .y_valid(y_valid)
);

input_2 #
(
    .DATA_WIDTH(DATA_WIDTH),
    .LABEL_WIDTH(LABEL_WIDTH),
    .SIGNED(SIGNED),
    .ASCENDING(ASCENDING)
)
input_2_stage1_1 
(
    .clk(clk),
    .rst(rst),
    .x_valid(stage0_valid),
    .x_0(stage0_rslt_2),
    .x_1(stage0_rslt_3),
    .x_label_0(stage0_labl_2),
    .x_label_1(stage0_labl_3),
    .y_0(y_2),
    .y_1(y_3),
    .y_label_0(y_label_2),
    .y_label_1(y_label_3),
    .y_valid()
);


endmodule
module aes_rcon(clk, kld, out);
input		clk;
input		kld;
output	[31:0]	out;
reg	[31:0]	out;
reg	[3:0]	rcnt;
wire	[3:0]	rcnt_next;

always @(posedge clk)
	if(kld)		out <= #1 32'h01_00_00_00;
	else		out <= #1 frcon(rcnt_next);

assign rcnt_next = rcnt + 4'h1;
always @(posedge clk)
	if(kld)		rcnt <= #1 4'h0;
	else		rcnt <= #1 rcnt_next;

function [31:0]	frcon;
input	[3:0]	i;
(* parallel_case *) case(i)
   4'h0: frcon=32'h01_00_00_00;
   4'h1: frcon=32'h02_00_00_00;
   4'h2: frcon=32'h04_00_00_00;
   4'h3: frcon=32'h08_00_00_00;
   4'h4: frcon=32'h10_00_00_00;
   4'h5: frcon=32'h20_00_00_00;
   4'h6: frcon=32'h40_00_00_00;
   4'h7: frcon=32'h80_00_00_00;
   4'h8: frcon=32'h1b_00_00_00;
   4'h9: frcon=32'h36_00_00_00;
   default: frcon=32'h00_00_00_00;
endcase
endfunction

endmodule
module div_uu(clk, ena, z, d, q, s, div0, ovf);

	//
	// parameters
	//
	parameter z_width = 16;
	parameter d_width = z_width /2;

	//
	// inputs & outputs
	//
	input clk;               // system clock
	input ena;               // clock enable

	input  [z_width -1:0] z; // divident
	input  [d_width -1:0] d; // divisor
	output [d_width -1:0] q; // quotient
	reg [d_width-1:0] q;
	output [d_width -1:0] s; // remainder
	reg [d_width-1:0] s;
	output div0;
	reg div0;
	output ovf;
	reg ovf;

	//
	// functions
	//
	function [z_width:0] gen_s;
		input [z_width:0] si;
		input [z_width:0] di;
	begin
	  if(si[z_width])
	    gen_s = {si[z_width-1:0], 1'b0} + di;
	  else
	    gen_s = {si[z_width-1:0], 1'b0} - di;
	end
	endfunction

	function [d_width-1:0] gen_q;
		input [d_width-1:0] qi;
		input [z_width:0] si;
	begin
	  gen_q = {qi[d_width-2:0], ~si[z_width]};
	end
	endfunction

	function [d_width-1:0] assign_s;
		input [z_width:0] si;
		input [z_width:0] di;
		reg [z_width:0] tmp;
	begin
	  if(si[z_width])
	    tmp = si + di;
	  else
	    tmp = si;

	  assign_s = tmp[z_width-1:z_width-4];
	end
	endfunction

	//
	// variables
	//
	reg [d_width-1:0] q_pipe  [d_width-1:0];
	reg [z_width:0] s_pipe  [d_width:0];
	reg [z_width:0] d_pipe  [d_width:0];

	reg [d_width:0] div0_pipe, ovf_pipe;
	//
	// perform parameter checks
	//
`ifdef SIMULATION
	initial
	begin
	  if(d_width !== z_width / 2)
	    $display("div.v parameter error (d_width != z_width/2).");
	end
`endif

	integer n0, n1, n2, n3;

	// generate divisor (d) pipe
	always @(d)
	  d_pipe[0] <= {1'b0, d, {(z_width-d_width){1'b0}} };

	always @(posedge clk)
	  if(ena)
	    for(n0=1; n0 <= d_width; n0=n0+1)
	       d_pipe[n0] <= #1 d_pipe[n0-1];

	// generate internal remainder pipe
	always @(z)
	  s_pipe[0] <= z;

	always @(posedge clk)
	  if(ena)
	    for(n1=1; n1 <= d_width; n1=n1+1)
	       s_pipe[n1] <= #1 gen_s(s_pipe[n1-1], d_pipe[n1-1]);

	// generate quotient pipe
	always @(posedge clk)
	  q_pipe[0] <= #1 0;

	always @(posedge clk)
	  if(ena)
	    for(n2=1; n2 < d_width; n2=n2+1)
	       q_pipe[n2] <= #1 gen_q(q_pipe[n2-1], s_pipe[n2]);


	// flags (divide_by_zero, overflow)
	always @(z or d)
	begin
	  ovf_pipe[0]  <= !(z[z_width-1:d_width] < d);
	  div0_pipe[0] <= ~|d;
	end

	always @(posedge clk)
	  if(ena)
	    for(n3=1; n3 <= d_width; n3=n3+1)
	    begin
	        ovf_pipe[n3] <= #1 ovf_pipe[n3-1];
	        div0_pipe[n3] <= #1 div0_pipe[n3-1];
	    end

	// assign outputs
	always @(posedge clk)
	  if(ena)
	    ovf <= #1 ovf_pipe[d_width];

	always @(posedge clk)
	  if(ena)
	    div0 <= #1 div0_pipe[d_width];

	always @(posedge clk)
	  if(ena)
	    q <= #1 gen_q(q_pipe[d_width-1], s_pipe[d_width]);

	always @(posedge clk)
	  if(ena)
	    s <= #1 assign_s(s_pipe[d_width], d_pipe[d_width]);
endmodule
module jpeg_rzs(clk, ena, rst, deni, dci, rleni, sizei, ampi, deno, dco, rleno, sizeo, ampo);

	//
	// inputs & outputs
	//
	input        clk;
	input        ena;
	input        rst;
	input        deni;
	input        dci;
	input [ 3:0] sizei;
	input [ 3:0] rleni;
	input [11:0] ampi;

	output        deno;
	output        dco;
	output [ 3:0] sizeo;
	output [ 3:0] rleno;
	output [11:0] ampo;

	reg        deno, dco;
	reg [ 3:0] sizeo, rleno;
	reg [11:0] ampo;

	//
	// variables
	//

	reg [ 3:0] size;
	reg [ 3:0] rlen;
	reg [11:0] amp;
	reg        den;
	reg        dc;

	wire eob;
	wire zerobl;
	reg  state;

	//
	// module body
	//

	always @(posedge clk)
	  if(ena & deni)
	    begin
	        size <= #1 sizei;
	        rlen <= #1 rleni;
	        amp  <= #1 ampi;
	    end

	always @(posedge clk)
	  if(ena)
	    begin
	        sizeo <= #1 size;
	        rleno <= #1 rlen;
	        ampo  <= #1 amp;

	        dc    <= #1 dci;
	        dco   <= #1 dc;
	    end

	assign zerobl = &rleni &  ~|sizei & deni;
	assign eob    = ~|{rleni, sizei} & deni & ~dci;

	always @(posedge clk or negedge rst)
	  if (!rst)
	     begin
	         state <= #1 1'b0;
	         den   <= #1 1'b0;
	         deno  <= #1 1'b0;
	     end
	  else
	    if(ena)
	      (* full_case, parallel_case *) case (state)
	         1'b0:
	             begin
	                 if (zerobl)
	                    begin
	                        state <= #1 1'b1; // go to zero-detection state
	                        den   <= #1 1'b0; // do not yet set data output enable
	                        deno  <= #1 den;  // output previous data
	                    end
	                 else
	                    begin
	                        state <= #1 1'b0; // stay in 'normal' state
	                        den   <= #1 deni; // set data output enable
	                        deno  <= #1 den;  // output previous data
	                    end
	             end

	         1'b1:
	             begin
	                 deno <= #1 1'b0;

	                 if (deni)
	                    if (zerobl)
	                       begin
	                           state <= #1 1'b1; // stay in zero-detection state
	                           den   <= #1 1'b0; // hold current zer-block
	                           deno  <= #1 1'b1; // output previous zero-block
	                       end
	                    else if (eob)
	                       begin
	                           state <= #1 1'b0; // go to 'normal' state
	                           den   <= #1 1'b1; // set output enable for EOB
	                           deno  <= #1 1'b0; // (was already zero), maybe optimize ??
	                       end
	                    else
	                       begin
	                           state <= #1 1'b0; // go to normal state
	                           den   <= #1 1'b1; // set data output enable
	                           deno  <= #1 1'b1; // oops, zero-block should have been output
	                       end
	             end
	      endcase
endmodule
module dct_mac(clk, ena, dclr, din, coef, result);

	//
	// parameters
	//
	parameter dwidth = 8;
	parameter cwidth = 16;
	parameter mwidth = dwidth + cwidth;  // multiplier result
	parameter rwidth = mwidth +3;        // add 3 bits for growth

	//
	// inputs & outputs
	//
	input               clk;    // clock input
	input               ena;    // clock enable
	input               dclr;   // start new mac (delayed 1 cycle)
	input  [dwidth-1:0] din;    // data input
	input  [cwidth-1:0] coef;   // coefficient input
	output [rwidth-1:0] result; // mac-result
	reg [rwidth -1:0] result;

	//
	// variables
	//
	wire [mwidth-1:0] idin;
	wire [mwidth-1:0] icoef;

	reg  [mwidth -1:0] mult_res /* synthesis syn_multstyle="block_mult" syn_pipeline=1*/ ;
	wire [rwidth -1:0] ext_mult_res;


	//
	// module body
	//
	assign icoef = { {(mwidth-cwidth){coef[cwidth-1]}}, coef};
	assign idin  = { {(mwidth-dwidth){din[dwidth-1]}}, din};

	// generate multiplier structure
	always @(posedge clk)
	  if(ena)
	    mult_res <= #1 icoef * idin;

	assign ext_mult_res = { {3{mult_res[mwidth-1]}}, mult_res};

	// generate adder structure
	always @(posedge clk)
	  if(ena)
	    if(dclr)
	      result <= #1 ext_mult_res;
	    else
	      result <= #1 ext_mult_res + result;
endmodule
module adder (input [31:0] a, b,
              output [31:0] y);
   
   assign y = a + b;
   
endmodule
module shifter (input  wire signed [31:0] a,
		input wire [ 4:0]  shamt,
		input wire [ 1:0]  shtype,
		output reg [31:0] y);
   
   always@(*)
     case (shtype)
       2'b00:   
	 begin
	    y = a << shamt;
	 end	    
       2'b01:   
	 begin
	    y = a >> shamt;
	 end
       2'b10:   
	 begin
	    y = a >>> shamt;
	 end
       default: 
	 begin
	    y = a;
	 end
     endcase // case (shtype)

endmodule
module magcompare2b (LT, GT, A, B);

   input [1:0] A;
   input [1:0] B;
   
   output      LT;
   output      GT;

   // Determine if A < B  using a minimized sum-of-products expression
   assign LT = ~A[1]&B[1] | ~A[1]&~A[0]&B[0] | ~A[0]&B[1]&B[0];

   // Determine if A > B  using a minimized sum-of-products expression
   assign GT = A[1]&~B[1] | A[1]&A[0]&~B[0] | A[0]&~B[1]&~B[0];

endmodule
module maindec (input  [6:0] op,
		output 	     memtoreg, memwrite,
		output 	     branch, alusrc,
		output 	     regwrite,
		output 	     storepc,
		output 	     pcadd,
		output 	     pcext,
		output [2:0] imm,
		output [2:0] aluop,
		output 	     auipc_cntrl,
		output 	     memread,
                input 	     gt, lt, eq,
		output 	     suspend);
   
   reg [16:0] 		     controls;

   assign {memread, auipc_cntrl, pcadd, pcext, suspend, regwrite, alusrc,
           branch, memwrite,
           memtoreg, storepc, aluop, imm} = controls;

   always @(*)
     case(op)
       7'b011_0011: controls <= 17'b00000100_000_010_000; // R
       7'b000_0011: controls <= 17'b10000110_010_100_000; // LW
       7'b010_0011: controls <= 17'b00000010_100_100_001; // SW
       7'b110_0011: controls <= 17'b00110011_000_000_010; // BXX
       7'b110_1111: controls <= 17'b00110110_001_000_011; // JAL/J
       7'b001_0011: controls <= 17'b00000110_000_000_000; // ADDI/ORI
       7'b011_0111: controls <= 17'b00000110_000_000_100; // LUI
       7'b111_0011: controls <= 17'b00001000_000_000_000; // ecall/ebreak
       7'b110_0111: controls <= 17'b00000110_001_000_000; // JALR/JR
       7'b001_0111: controls <= 17'b01100110_000_000_100; // AUIPC
       default:     controls <= 17'b00000000_000_000_000; // default
     endcase // case (op)
   
endmodule
module regfile (input         clk, 
		input         we3, 
		input  [4:0]  ra1, ra2, wa3, 
		input  [31:0] wd3, 
		output [31:0] rd1, rd2);

   reg [31:0] 		      rf[31:0];

   // three ported register file
   // read two ports combinationally
   // write third port on rising edge of clock
   // register 0 hardwired to 0

   always @(posedge clk)
     if (we3 && wa3!=0) rf[wa3] <= wd3;	

   assign rd1 = (ra1 != 0) ? rf[ra1] : 0;
   assign rd2 = (ra2 != 0) ? rf[ra2] : 0;
   
endmodule
module magcompare2c (LT, GT, GT_in, LT_in);

   input [1:0] LT_in;
   input [1:0] GT_in;
   
   output      LT;
   output      GT;

   // Determine if A < B  using a minimized sum-of-products expression
   assign GT = GT_in[1] | ~LT_in[1]&GT_in[0];

   // Determine if A > B  using a minimized sum-of-products expression
   assign LT = LT_in[1] | !GT_in[1]&LT_in[0];

endmodule
module alu (input wire [31:0]  a, b, 
            input wire [3:0] 	alucont,
	    input wire 	sltunsigned,
            output reg [31:0] result,
	    output wire 	zero);

   wire [32:0] 		a2, b2, sum;
   wire [31:0] 		slt;
   wire [31:0] 		exor;   

   assign a2 = {sltunsigned ? 1'b0 : a[31], a};
   assign b2 = alucont[2] ? ~{sltunsigned ? 1'b0 : b[31], b} : 
	       {sltunsigned ? 1'b0 : b[31], b};
   assign sum = a2 + b2 + alucont[2];
   assign exor = a2 ^ b2;   
   assign slt = sum[32];

   always@(*)
     case({alucont[3], alucont[1:0]})
       3'b000: result <= a2 & b2;
       3'b001: result <= a2 | b2;
       3'b010: result <= sum[31:0];
       3'b011: result <= slt;
       3'b100: result <= exor;
       default: result <= 32'h0;       
     endcase // case ({alucont[3], alucont[1:0]})

   assign zero = ~| exor;

endmodule
module ibex_counter (
	clk_i,
	rst_ni,
	counter_inc_i,
	counterh_we_i,
	counter_we_i,
	counter_val_i,
	counter_val_o
);
	parameter signed [31:0] CounterWidth = 32;
	input wire clk_i;
	input wire rst_ni;
	input wire counter_inc_i;
	input wire counterh_we_i;
	input wire counter_we_i;
	input wire [31:0] counter_val_i;
	output wire [63:0] counter_val_o;
	wire [63:0] counter;
	reg [CounterWidth - 1:0] counter_upd;
	reg [63:0] counter_load;
	reg we;
	reg [CounterWidth - 1:0] counter_d;
	always @(*) begin
		we = counter_we_i | counterh_we_i;
		counter_load[63:32] = counter[63:32];
		counter_load[31:0] = counter_val_i;
		if (counterh_we_i) begin
			counter_load[63:32] = counter_val_i;
			counter_load[31:0] = counter[31:0];
		end
		counter_upd = counter[CounterWidth - 1:0] + {{CounterWidth - 1 {1'b0}}, 1'b1};
		if (we)
			counter_d = counter_load[CounterWidth - 1:0];
		else if (counter_inc_i)
			counter_d = counter_upd[CounterWidth - 1:0];
		else
			counter_d = counter[CounterWidth - 1:0];
	end
	reg [CounterWidth - 1:0] counter_q;
	always @(posedge clk_i or negedge rst_ni)
		if (!rst_ni)
			counter_q <= {CounterWidth {1'sb0}};
		else
			counter_q <= counter_d;
	generate
		if (CounterWidth < 64) begin : g_counter_narrow
			wire [63:CounterWidth] unused_counter_load;
			assign counter[CounterWidth - 1:0] = counter_q;
			assign counter[63:CounterWidth] = {(63 >= CounterWidth ? 64 - CounterWidth : CounterWidth - 62) {1'sb0}};
			assign unused_counter_load = counter_load[63:CounterWidth];
		end
		else begin : g_counter_full
			assign counter = counter_q;
		end
	endgenerate
	assign counter_val_o = counter;
endmodule
module ibex_register_file_fpga (
	clk_i,
	rst_ni,
	test_en_i,
	dummy_instr_id_i,
	raddr_a_i,
	rdata_a_o,
	raddr_b_i,
	rdata_b_o,
	waddr_a_i,
	wdata_a_i,
	we_a_i
);
	parameter [0:0] RV32E = 0;
	parameter [31:0] DataWidth = 32;
	parameter [0:0] DummyInstructions = 0;
	input wire clk_i;
	input wire rst_ni;
	input wire test_en_i;
	input wire dummy_instr_id_i;
	input wire [4:0] raddr_a_i;
	output wire [DataWidth - 1:0] rdata_a_o;
	input wire [4:0] raddr_b_i;
	output wire [DataWidth - 1:0] rdata_b_o;
	input wire [4:0] waddr_a_i;
	input wire [DataWidth - 1:0] wdata_a_i;
	input wire we_a_i;
	localparam signed [31:0] ADDR_WIDTH = (RV32E ? 4 : 5);
	localparam signed [31:0] NUM_WORDS = 2 ** ADDR_WIDTH;
	reg [DataWidth - 1:0] mem [0:NUM_WORDS - 1];
	wire we;
	assign rdata_a_o = (raddr_a_i == {5 {1'sb0}} ? {DataWidth {1'sb0}} : mem[raddr_a_i]);
	assign rdata_b_o = (raddr_b_i == {5 {1'sb0}} ? {DataWidth {1'sb0}} : mem[raddr_b_i]);
	assign we = (waddr_a_i == {5 {1'sb0}} ? 1'b0 : we_a_i);
	always @(posedge clk_i) begin : sync_write
		if (we == 1'b1)
			mem[waddr_a_i] <= wdata_a_i;
	end
	wire unused_rst_ni;
	assign unused_rst_ni = rst_ni;
	wire unused_dummy_instr;
	assign unused_dummy_instr = dummy_instr_id_i;
	wire unused_test_en;
	assign unused_test_en = test_en_i;
endmodule
module prim_clock_gating (
  input  clk_i,
  input  en_i,
  input  test_en_i,
  output clk_o
);

  reg en_latch;

  always @* begin
    if (!clk_i) begin
      en_latch = en_i | test_en_i;
    end
  end
  assign clk_o = en_latch & clk_i;

endmodule
module prim_secded_39_32_dec (
	in,
	d_o,
	syndrome_o,
	err_o
);
	input [38:0] in;
	output wire [31:0] d_o;
	output wire [6:0] syndrome_o;
	output wire [1:0] err_o;
	wire single_error;
	assign syndrome_o[0] = ((((((((((((in[32] ^ in[2]) ^ in[3]) ^ in[7]) ^ in[8]) ^ in[14]) ^ in[15]) ^ in[16]) ^ in[18]) ^ in[19]) ^ in[23]) ^ in[24]) ^ in[28]) ^ in[29];
	assign syndrome_o[1] = (((((((((((((in[33] ^ in[3]) ^ in[6]) ^ in[8]) ^ in[12]) ^ in[13]) ^ in[15]) ^ in[17]) ^ in[19]) ^ in[21]) ^ in[25]) ^ in[27]) ^ in[29]) ^ in[30]) ^ in[31];
	assign syndrome_o[2] = (((((((((((((in[34] ^ in[0]) ^ in[5]) ^ in[7]) ^ in[9]) ^ in[10]) ^ in[12]) ^ in[13]) ^ in[15]) ^ in[16]) ^ in[22]) ^ in[23]) ^ in[26]) ^ in[27]) ^ in[31];
	assign syndrome_o[3] = (((((((((((((in[35] ^ in[0]) ^ in[1]) ^ in[4]) ^ in[6]) ^ in[9]) ^ in[11]) ^ in[12]) ^ in[14]) ^ in[22]) ^ in[23]) ^ in[25]) ^ in[28]) ^ in[29]) ^ in[30];
	assign syndrome_o[4] = (((((((((((in[36] ^ in[0]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[11]) ^ in[17]) ^ in[20]) ^ in[24]) ^ in[26]) ^ in[27]) ^ in[30];
	assign syndrome_o[5] = (((((((((((((in[37] ^ in[1]) ^ in[2]) ^ in[4]) ^ in[6]) ^ in[10]) ^ in[13]) ^ in[14]) ^ in[16]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[21]) ^ in[22]) ^ in[26];
	assign syndrome_o[6] = ((((((((((((((in[38] ^ in[1]) ^ in[5]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[10]) ^ in[11]) ^ in[17]) ^ in[18]) ^ in[20]) ^ in[21]) ^ in[24]) ^ in[25]) ^ in[28]) ^ in[31];
	assign d_o[0] = (syndrome_o == 7'h1c) ^ in[0];
	assign d_o[1] = (syndrome_o == 7'h68) ^ in[1];
	assign d_o[2] = (syndrome_o == 7'h31) ^ in[2];
	assign d_o[3] = (syndrome_o == 7'h13) ^ in[3];
	assign d_o[4] = (syndrome_o == 7'h38) ^ in[4];
	assign d_o[5] = (syndrome_o == 7'h54) ^ in[5];
	assign d_o[6] = (syndrome_o == 7'h2a) ^ in[6];
	assign d_o[7] = (syndrome_o == 7'h45) ^ in[7];
	assign d_o[8] = (syndrome_o == 7'h43) ^ in[8];
	assign d_o[9] = (syndrome_o == 7'h4c) ^ in[9];
	assign d_o[10] = (syndrome_o == 7'h64) ^ in[10];
	assign d_o[11] = (syndrome_o == 7'h58) ^ in[11];
	assign d_o[12] = (syndrome_o == 7'h0e) ^ in[12];
	assign d_o[13] = (syndrome_o == 7'h26) ^ in[13];
	assign d_o[14] = (syndrome_o == 7'h29) ^ in[14];
	assign d_o[15] = (syndrome_o == 7'h07) ^ in[15];
	assign d_o[16] = (syndrome_o == 7'h25) ^ in[16];
	assign d_o[17] = (syndrome_o == 7'h52) ^ in[17];
	assign d_o[18] = (syndrome_o == 7'h61) ^ in[18];
	assign d_o[19] = (syndrome_o == 7'h23) ^ in[19];
	assign d_o[20] = (syndrome_o == 7'h70) ^ in[20];
	assign d_o[21] = (syndrome_o == 7'h62) ^ in[21];
	assign d_o[22] = (syndrome_o == 7'h2c) ^ in[22];
	assign d_o[23] = (syndrome_o == 7'h0d) ^ in[23];
	assign d_o[24] = (syndrome_o == 7'h51) ^ in[24];
	assign d_o[25] = (syndrome_o == 7'h4a) ^ in[25];
	assign d_o[26] = (syndrome_o == 7'h34) ^ in[26];
	assign d_o[27] = (syndrome_o == 7'h16) ^ in[27];
	assign d_o[28] = (syndrome_o == 7'h49) ^ in[28];
	assign d_o[29] = (syndrome_o == 7'h0b) ^ in[29];
	assign d_o[30] = (syndrome_o == 7'h1a) ^ in[30];
	assign d_o[31] = (syndrome_o == 7'h46) ^ in[31];
	assign single_error = ^syndrome_o;
	assign err_o[0] = single_error;
	assign err_o[1] = ~single_error & |syndrome_o;
endmodule
module prim_generic_ram_1p (
	clk_i,
	req_i,
	write_i,
	addr_i,
	wdata_i,
	wmask_i,
	rdata_o
);
	parameter signed [31:0] Width = 32;
	parameter signed [31:0] Depth = 128;
	parameter signed [31:0] DataBitsPerMask = 1;
	parameter _sv2v_width_MemInitFile = 1;
	parameter [_sv2v_width_MemInitFile - 1:0] MemInitFile = "";
	localparam signed [31:0] Aw = $clog2(Depth);
	input wire clk_i;
	input wire req_i;
	input wire write_i;
	input wire [Aw - 1:0] addr_i;
	input wire [Width - 1:0] wdata_i;
	input wire [Width - 1:0] wmask_i;
	output reg [Width - 1:0] rdata_o;
	localparam signed [31:0] MaskWidth = Width / DataBitsPerMask;
	reg [Width - 1:0] mem [0:Depth - 1];
	wire [MaskWidth - 1:0] wmask;
	generate
		genvar k;
		for (k = 0; k < MaskWidth; k = k + 1) begin : gen_wmask
			assign wmask[k] = &wmask_i[k * DataBitsPerMask+:DataBitsPerMask];
		end
	endgenerate
	always @(posedge clk_i)
		if (req_i)
			if (write_i) begin : sv2v_autoblock_2
				reg signed [31:0] i;
				for (i = 0; i < MaskWidth; i = i + 1)
					if (wmask[i])
						mem[addr_i][i * DataBitsPerMask+:DataBitsPerMask] <= wdata_i[i * DataBitsPerMask+:DataBitsPerMask];
			end
			else
				rdata_o <= mem[addr_i];
	initial if (MemInitFile != "") begin : gen_meminit
		$display("Initializing memory %m from file '%s'.", MemInitFile);
		$readmemh(MemInitFile, mem);
	end
endmodule
module ibex_csr (
	clk_i,
	rst_ni,
	wr_data_i,
	wr_en_i,
	rd_data_o,
	rd_error_o
);
	parameter [31:0] Width = 32;
	parameter [0:0] ShadowCopy = 1'b0;
	parameter [Width - 1:0] ResetValue = 1'sb0;
	input wire clk_i;
	input wire rst_ni;
	input wire [Width - 1:0] wr_data_i;
	input wire wr_en_i;
	output wire [Width - 1:0] rd_data_o;
	output wire rd_error_o;
	reg [Width - 1:0] rdata_q;
	always @(posedge clk_i or negedge rst_ni)
		if (!rst_ni)
			rdata_q <= ResetValue;
		else if (wr_en_i)
			rdata_q <= wr_data_i;
	assign rd_data_o = rdata_q;
	generate
		if (ShadowCopy) begin : gen_shadow
			reg [Width - 1:0] shadow_q;
			always @(posedge clk_i or negedge rst_ni)
				if (!rst_ni)
					shadow_q <= ~ResetValue;
				else if (wr_en_i)
					shadow_q <= ~wr_data_i;
			assign rd_error_o = rdata_q != ~shadow_q;
		end
		else begin : gen_no_shadow
			assign rd_error_o = 1'b0;
		end
	endgenerate
endmodule
module stream_demux_N_OUP3
(
  inp_valid_i,
  inp_ready_o,
  oup_sel_i,
  oup_valid_o,
  oup_ready_i
);

  input [1:0] oup_sel_i;
  output [2:0] oup_valid_o;
  input [2:0] oup_ready_i;
  input inp_valid_i;
  output inp_ready_o;
  wire [2:0] oup_valid_o;
  wire inp_ready_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14;
  assign N10 = N0 & oup_sel_i[1];
  assign N0 = ~oup_sel_i[0];
  assign N9 = oup_sel_i[0] & N1;
  assign N1 = ~oup_sel_i[1];
  assign N14 = N2 & N3;
  assign N2 = ~oup_sel_i[0];
  assign N3 = ~oup_sel_i[1];
  assign oup_valid_o[0] = (N4)? inp_valid_i : 
                          (N11)? 1'b0 : 1'b0;
  assign N4 = N14;
  assign oup_valid_o[1] = (N5)? inp_valid_i : 
                          (N12)? 1'b0 : 1'b0;
  assign N5 = N9;
  assign oup_valid_o[2] = (N6)? inp_valid_i : 
                          (N13)? 1'b0 : 1'b0;
  assign N6 = N10;
  assign inp_ready_o = (N4)? oup_ready_i[0] : 
                       (N7)? oup_ready_i[1] : 
                       (N8)? oup_ready_i[2] : 1'b0;
  assign N7 = oup_sel_i[0];
  assign N8 = oup_sel_i[1];
  assign N11 = ~N14;
  assign N12 = ~N9;
  assign N13 = ~N10;

endmodule
module lzc_00000003
(
  in_i,
  cnt_o,
  empty_o
);

  input [2:0] in_i;
  output [1:0] cnt_o;
  output empty_o;
  wire [1:0] cnt_o,sel_nodes;
  wire empty_o,N0,index_nodes_1__0_,N1;
  assign cnt_o[1] = ~sel_nodes[1];
  assign cnt_o[0] = (N0)? index_nodes_1__0_ : 
                    (N1)? 1'b0 : 1'b0;
  assign N0 = sel_nodes[1];
  assign index_nodes_1__0_ = ~in_i[0];
  assign sel_nodes[0] = sel_nodes[1] | in_i[2];
  assign N1 = ~sel_nodes[1];
  assign sel_nodes[1] = in_i[0] | in_i[1];
  assign empty_o = ~sel_nodes[0];

endmodule
module lzc_00000004
(
  in_i,
  cnt_o,
  empty_o
);

  input [3:0] in_i;
  output [1:0] cnt_o;
  output empty_o;
  wire [1:0] cnt_o;
  wire empty_o,N0,index_nodes_2__0_,index_nodes_1__0_,N1;
  wire [2:0] sel_nodes;
  assign cnt_o[1] = ~sel_nodes[1];
  assign cnt_o[0] = (N0)? index_nodes_1__0_ : 
                    (N1)? index_nodes_2__0_ : 1'b0;
  assign N0 = sel_nodes[1];
  assign index_nodes_1__0_ = ~in_i[0];
  assign index_nodes_2__0_ = ~in_i[2];
  assign sel_nodes[0] = sel_nodes[1] | sel_nodes[2];
  assign N1 = ~sel_nodes[1];
  assign sel_nodes[1] = in_i[0] | in_i[1];
  assign sel_nodes[2] = in_i[2] | in_i[3];
  assign empty_o = ~sel_nodes[0];

endmodule
module lfsr_8bit_00000008
(
  clk_i,
  rst_ni,
  en_i,
  refill_way_oh,
  refill_way_bin
);

  output [7:0] refill_way_oh;
  output [2:0] refill_way_bin;
  input clk_i;
  input rst_ni;
  input en_i;
  wire [7:0] refill_way_oh;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
  N22,N23,N24;
  reg [7:3] shift_q;
  reg [2:0] refill_way_bin;

  always @(posedge clk_i or posedge N13) begin
    if(N13) begin
      shift_q[7] <= 1'b0;
    end else if(en_i) begin
      shift_q[7] <= shift_q[6];
    end 
  end


  always @(posedge clk_i or posedge N13) begin
    if(N13) begin
      shift_q[6] <= 1'b0;
    end else if(en_i) begin
      shift_q[6] <= shift_q[5];
    end 
  end


  always @(posedge clk_i or posedge N13) begin
    if(N13) begin
      shift_q[5] <= 1'b0;
    end else if(en_i) begin
      shift_q[5] <= shift_q[4];
    end 
  end


  always @(posedge clk_i or posedge N13) begin
    if(N13) begin
      shift_q[4] <= 1'b0;
    end else if(en_i) begin
      shift_q[4] <= shift_q[3];
    end 
  end


  always @(posedge clk_i or posedge N13) begin
    if(N13) begin
      shift_q[3] <= 1'b0;
    end else if(en_i) begin
      shift_q[3] <= refill_way_bin[2];
    end 
  end


  always @(posedge clk_i or posedge N13) begin
    if(N13) begin
      refill_way_bin[2] <= 1'b0;
    end else if(en_i) begin
      refill_way_bin[2] <= refill_way_bin[1];
    end 
  end


  always @(posedge clk_i or posedge N13) begin
    if(N13) begin
      refill_way_bin[1] <= 1'b0;
    end else if(en_i) begin
      refill_way_bin[1] <= refill_way_bin[0];
    end 
  end


  always @(posedge clk_i or posedge N13) begin
    if(N13) begin
      refill_way_bin[0] <= 1'b0;
    end else if(en_i) begin
      refill_way_bin[0] <= N12;
    end 
  end

  assign N14 = refill_way_bin[0] & refill_way_bin[1];
  assign refill_way_oh[7] = N14 & refill_way_bin[2];
  assign N15 = N0 & refill_way_bin[1];
  assign N0 = ~refill_way_bin[0];
  assign refill_way_oh[6] = N15 & refill_way_bin[2];
  assign N16 = refill_way_bin[0] & N1;
  assign N1 = ~refill_way_bin[1];
  assign refill_way_oh[5] = N16 & refill_way_bin[2];
  assign N17 = N2 & N3;
  assign N2 = ~refill_way_bin[0];
  assign N3 = ~refill_way_bin[1];
  assign refill_way_oh[4] = N17 & refill_way_bin[2];
  assign N18 = refill_way_bin[0] & refill_way_bin[1];
  assign refill_way_oh[3] = N18 & N4;
  assign N4 = ~refill_way_bin[2];
  assign N19 = N5 & refill_way_bin[1];
  assign N5 = ~refill_way_bin[0];
  assign refill_way_oh[2] = N19 & N6;
  assign N6 = ~refill_way_bin[2];
  assign N20 = refill_way_bin[0] & N7;
  assign N7 = ~refill_way_bin[1];
  assign refill_way_oh[1] = N20 & N8;
  assign N8 = ~refill_way_bin[2];
  assign N21 = N9 & N10;
  assign N9 = ~refill_way_bin[0];
  assign N10 = ~refill_way_bin[1];
  assign refill_way_oh[0] = N21 & N11;
  assign N11 = ~refill_way_bin[2];
  assign N12 = ~N24;
  assign N24 = N23 ^ refill_way_bin[1];
  assign N23 = N22 ^ refill_way_bin[2];
  assign N22 = shift_q[7] ^ shift_q[3];
  assign N13 = ~rst_ni;

endmodule
module lfsr_8bit_00000004
(
  clk_i,
  rst_ni,
  en_i,
  refill_way_oh,
  refill_way_bin
);

  output [3:0] refill_way_oh;
  output [1:0] refill_way_bin;
  input clk_i;
  input rst_ni;
  input en_i;
  wire [3:0] refill_way_oh;
  wire N0,N1,N2,N3,N4,N5,N6,N7,N8;
  reg [7:2] shift_q;
  reg [1:0] refill_way_bin;

  always @(posedge clk_i or posedge N5) begin
    if(N5) begin
      shift_q[7] <= 1'b0;
    end else if(en_i) begin
      shift_q[7] <= shift_q[6];
    end 
  end


  always @(posedge clk_i or posedge N5) begin
    if(N5) begin
      shift_q[6] <= 1'b0;
    end else if(en_i) begin
      shift_q[6] <= shift_q[5];
    end 
  end


  always @(posedge clk_i or posedge N5) begin
    if(N5) begin
      shift_q[5] <= 1'b0;
    end else if(en_i) begin
      shift_q[5] <= shift_q[4];
    end 
  end


  always @(posedge clk_i or posedge N5) begin
    if(N5) begin
      shift_q[4] <= 1'b0;
    end else if(en_i) begin
      shift_q[4] <= shift_q[3];
    end 
  end


  always @(posedge clk_i or posedge N5) begin
    if(N5) begin
      shift_q[3] <= 1'b0;
    end else if(en_i) begin
      shift_q[3] <= shift_q[2];
    end 
  end


  always @(posedge clk_i or posedge N5) begin
    if(N5) begin
      shift_q[2] <= 1'b0;
    end else if(en_i) begin
      shift_q[2] <= refill_way_bin[1];
    end 
  end


  always @(posedge clk_i or posedge N5) begin
    if(N5) begin
      refill_way_bin[1] <= 1'b0;
    end else if(en_i) begin
      refill_way_bin[1] <= refill_way_bin[0];
    end 
  end


  always @(posedge clk_i or posedge N5) begin
    if(N5) begin
      refill_way_bin[0] <= 1'b0;
    end else if(en_i) begin
      refill_way_bin[0] <= N4;
    end 
  end

  assign refill_way_oh[3] = refill_way_bin[0] & refill_way_bin[1];
  assign refill_way_oh[2] = N0 & refill_way_bin[1];
  assign N0 = ~refill_way_bin[0];
  assign refill_way_oh[1] = refill_way_bin[0] & N1;
  assign N1 = ~refill_way_bin[1];
  assign refill_way_oh[0] = N2 & N3;
  assign N2 = ~refill_way_bin[0];
  assign N3 = ~refill_way_bin[1];
  assign N4 = ~N8;
  assign N8 = N7 ^ refill_way_bin[1];
  assign N7 = N6 ^ shift_q[2];
  assign N6 = shift_q[7] ^ shift_q[3];
  assign N5 = ~rst_ni;

endmodule
module Subtractor_0x422b1f52edd46a85
(
  input  wire [   0:0] clk,
  input  wire [  15:0] in0,
  input  wire [  15:0] in1,
  output reg  [  15:0] out,
  input  wire [   0:0] reset
);



  // PYMTL SOURCE:
  //
  // @s.combinational
  // def comb_logic():
  //       s.out.value = s.in0 - s.in1

  // logic for comb_logic()
  always @ (*) begin
    out = (in0-in1);
  end


endmodule