module or1200_freeze_cm4(
		clk_i_cml_1,
		clk_i_cml_2,
		clk_i_cml_3,
		
	// Clock and reset
	clk, rst,

	// Internal i/f
	multicycle, flushpipe, extend_flush, lsu_stall, if_stall,
	lsu_unstall, du_stall, mac_stall, 
	force_dslot_fetch, abort_ex,
	genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze,
	icpu_ack_i, icpu_err_i
);


input clk_i_cml_1;
input clk_i_cml_2;
input clk_i_cml_3;
reg  extend_flush_cml_3;
reg  extend_flush_cml_2;
reg  extend_flush_cml_1;
reg  lsu_stall_cml_3;
reg  lsu_stall_cml_2;
reg  if_stall_cml_3;
reg  lsu_unstall_cml_3;
reg  lsu_unstall_cml_2;
reg  lsu_unstall_cml_1;
reg  abort_ex_cml_2;
reg  du_stall_cml_3;
reg  du_stall_cml_2;
reg  du_stall_cml_1;
reg  mac_stall_cml_3;
reg  mac_stall_cml_2;
reg  mac_stall_cml_1;
reg  ex_freeze_cml_3;
reg  icpu_ack_i_cml_3;
reg  icpu_ack_i_cml_2;
reg  icpu_err_i_cml_3;
reg  multicycle_freeze_cml_3;
reg  multicycle_freeze_cml_2;
reg [ 2 - 1 : 0 ] multicycle_cnt_cml_3;
reg [ 2 - 1 : 0 ] multicycle_cnt_cml_2;
reg [ 2 - 1 : 0 ] multicycle_cnt_cml_1;
reg  flushpipe_r_cml_3;
reg  flushpipe_r_cml_2;
reg  flushpipe_r_cml_1;



//
// I/O
//
input				clk;
input				rst;
input	[`OR1200_MULTICYCLE_WIDTH-1:0]	multicycle;
input				flushpipe;
input				extend_flush;
input				lsu_stall;
input				if_stall;
input				lsu_unstall;
input				force_dslot_fetch;
input				abort_ex;
input				du_stall;
input				mac_stall;
output				genpc_freeze;
output				if_freeze;
output				id_freeze;
output				ex_freeze;
output				wb_freeze;
input				icpu_ack_i;
input				icpu_err_i;

//
// Internal wires and regs
//
wire				multicycle_freeze;
reg	[`OR1200_MULTICYCLE_WIDTH-1:0]	multicycle_cnt;
reg				flushpipe_r;

//
// Pipeline freeze
//
// Rules how to create freeze signals:
// 1. Not overwriting pipeline stages:
// Freze signals at the beginning of pipeline (such as if_freeze) can be asserted more
// often than freeze signals at the of pipeline (such as wb_freeze). In other words, wb_freeze must never
// be asserted when ex_freeze is not. ex_freeze must never be asserted when id_freeze is not etc.
//
// 2. Inserting NOPs in the middle of pipeline only if supported:
// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.
// This way NOP is asserted from stage ID into EX stage.
//
//assign genpc_freeze = du_stall | flushpipe_r | lsu_stall;

// SynEDA CoreMultiplier
// assignment(s): genpc_freeze
// replace(s): du_stall, flushpipe_r
assign genpc_freeze = du_stall_cml_3 | flushpipe_r_cml_3;

// SynEDA CoreMultiplier
// assignment(s): if_freeze
// replace(s): extend_flush
assign if_freeze = id_freeze | extend_flush_cml_3;
//assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~flushpipe | du_stall;

// SynEDA CoreMultiplier
// assignment(s): id_freeze
// replace(s): lsu_stall, if_stall, lsu_unstall, du_stall, mac_stall, multicycle_freeze
assign id_freeze = (lsu_stall_cml_3 | (~lsu_unstall_cml_3 & if_stall_cml_3) | multicycle_freeze_cml_3 | force_dslot_fetch) | du_stall_cml_3 | mac_stall_cml_3;
assign ex_freeze = wb_freeze;
//assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) & ~flushpipe | du_stall | mac_stall;

// SynEDA CoreMultiplier
// assignment(s): wb_freeze
// replace(s): lsu_stall, lsu_unstall, abort_ex, du_stall, mac_stall, multicycle_freeze
assign wb_freeze = (lsu_stall_cml_2 | (~lsu_unstall_cml_2 & if_stall) | multicycle_freeze_cml_2) | du_stall_cml_2 | mac_stall_cml_2 | abort_ex_cml_2;

//
// registered flushpipe
//

// SynEDA CoreMultiplier
// assignment(s): flushpipe_r
// replace(s): icpu_ack_i, icpu_err_i, flushpipe_r
always @(posedge clk or posedge rst)
	if (rst)
		flushpipe_r <= #1 1'b0;
	else begin  flushpipe_r <= flushpipe_r_cml_3; if (icpu_ack_i_cml_3 | icpu_err_i_cml_3)
//	else if (!if_stall)
		flushpipe_r <= #1 flushpipe;
	else if (!flushpipe)
		flushpipe_r <= #1 1'b0; end
		
//
// Multicycle freeze
//

// SynEDA CoreMultiplier
// assignment(s): multicycle_freeze
// replace(s): multicycle_cnt
assign multicycle_freeze = |multicycle_cnt_cml_1;

//
// Multicycle counter
//

// SynEDA CoreMultiplier
// assignment(s): multicycle_cnt
// replace(s): ex_freeze, multicycle_cnt
always @(posedge clk or posedge rst)
	if (rst)
		multicycle_cnt <= #1 2'b00;
	else begin  multicycle_cnt <= multicycle_cnt_cml_3; if (|multicycle_cnt_cml_3)
		multicycle_cnt <= #1 multicycle_cnt_cml_3 - 2'd1;
	else if (|multicycle & !ex_freeze_cml_3)
		multicycle_cnt <= #1 multicycle; end


always @ (posedge clk_i_cml_1) begin
extend_flush_cml_1 <= extend_flush;
lsu_unstall_cml_1 <= lsu_unstall;
du_stall_cml_1 <= du_stall;
mac_stall_cml_1 <= mac_stall;
multicycle_cnt_cml_1 <= multicycle_cnt;
flushpipe_r_cml_1 <= flushpipe_r;
end
always @ (posedge clk_i_cml_2) begin
extend_flush_cml_2 <= extend_flush_cml_1;
lsu_stall_cml_2 <= lsu_stall;
lsu_unstall_cml_2 <= lsu_unstall_cml_1;
abort_ex_cml_2 <= abort_ex;
du_stall_cml_2 <= du_stall_cml_1;
mac_stall_cml_2 <= mac_stall_cml_1;
icpu_ack_i_cml_2 <= icpu_ack_i;
multicycle_freeze_cml_2 <= multicycle_freeze;
multicycle_cnt_cml_2 <= multicycle_cnt_cml_1;
flushpipe_r_cml_2 <= flushpipe_r_cml_1;
end
always @ (posedge clk_i_cml_3) begin
extend_flush_cml_3 <= extend_flush_cml_2;
lsu_stall_cml_3 <= lsu_stall_cml_2;
if_stall_cml_3 <= if_stall;
lsu_unstall_cml_3 <= lsu_unstall_cml_2;
du_stall_cml_3 <= du_stall_cml_2;
mac_stall_cml_3 <= mac_stall_cml_2;
ex_freeze_cml_3 <= ex_freeze;
icpu_ack_i_cml_3 <= icpu_ack_i_cml_2;
icpu_err_i_cml_3 <= icpu_err_i;
multicycle_freeze_cml_3 <= multicycle_freeze_cml_2;
multicycle_cnt_cml_3 <= multicycle_cnt_cml_2;
flushpipe_r_cml_3 <= flushpipe_r_cml_2;
end
endmodule