dakies/OSS_Verilog huggingface dataset:
module virtex6_pmem(
	clka,
	ena,
	wea,
	addra,
	dina,
	douta);


input clka;
input ena;
input [1 : 0] wea;
input [11 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;

// synthesis translate_off

      BLK_MEM_GEN_V3_3 #(
		.C_ADDRA_WIDTH(12),
		.C_ADDRB_WIDTH(12),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(8),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex6"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(0),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(4096),
		.C_READ_DEPTH_B(4096),
		.C_READ_WIDTH_A(16),
		.C_READ_WIDTH_B(16),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(1),
		.C_USE_BYTE_WEB(1),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(2),
		.C_WEB_WIDTH(2),
		.C_WRITE_DEPTH_A(4096),
		.C_WRITE_DEPTH_B(4096),
		.C_WRITE_MODE_A("WRITE_FIRST"),
		.C_WRITE_MODE_B("WRITE_FIRST"),
		.C_WRITE_WIDTH_A(16),
		.C_WRITE_WIDTH_B(16),
		.C_XDEVICEFAMILY("virtex6"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.DOUTA(douta),
		.RSTA(),
		.REGCEA(),
		.CLKB(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.ADDRB(),
		.DINB(),
		.DOUTB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of virtex6_pmem is "black_box"

endmodule
module virtex6_dmem(
	clka,
	ena,
	wea,
	addra,
	dina,
	douta);


input clka;
input ena;
input [1 : 0] wea;
input [9 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;

// synthesis translate_off

      BLK_MEM_GEN_V3_3 #(
		.C_ADDRA_WIDTH(10),
		.C_ADDRB_WIDTH(10),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(8),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex6"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(0),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(1024),
		.C_READ_DEPTH_B(1024),
		.C_READ_WIDTH_A(16),
		.C_READ_WIDTH_B(16),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(1),
		.C_USE_BYTE_WEB(1),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(2),
		.C_WEB_WIDTH(2),
		.C_WRITE_DEPTH_A(1024),
		.C_WRITE_DEPTH_B(1024),
		.C_WRITE_MODE_A("WRITE_FIRST"),
		.C_WRITE_MODE_B("WRITE_FIRST"),
		.C_WRITE_WIDTH_A(16),
		.C_WRITE_WIDTH_B(16),
		.C_XDEVICEFAMILY("virtex6"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.DOUTA(douta),
		.RSTA(),
		.REGCEA(),
		.CLKB(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.ADDRB(),
		.DINB(),
		.DOUTB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of virtex6_dmem is "black_box"

endmodule
module spartan3e_dmem(
	clka,
	ena,
	wea,
	addra,
	dina,
	douta);


input clka;
input ena;
input [0 : 0] wea;
input [9 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;

// synthesis translate_off

      BLK_MEM_GEN_V3_3 #(
		.C_ADDRA_WIDTH(10),
		.C_ADDRB_WIDTH(10),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(9),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("spartan3"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(0),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(1024),
		.C_READ_DEPTH_B(1024),
		.C_READ_WIDTH_A(8),
		.C_READ_WIDTH_B(8),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(0),
		.C_USE_BYTE_WEB(0),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(1),
		.C_WEB_WIDTH(1),
		.C_WRITE_DEPTH_A(1024),
		.C_WRITE_DEPTH_B(1024),
		.C_WRITE_MODE_A("WRITE_FIRST"),
		.C_WRITE_MODE_B("WRITE_FIRST"),
		.C_WRITE_WIDTH_A(8),
		.C_WRITE_WIDTH_B(8),
		.C_XDEVICEFAMILY("spartan3e"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.DOUTA(douta),
		.RSTA(),
		.REGCEA(),
		.CLKB(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.ADDRB(),
		.DINB(),
		.DOUTB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of spartan3e_dmem is "black_box"

endmodule
module spartan3adsp_pmem(
	clka,
	ena,
	wea,
	addra,
	dina,
	douta);


input clka;
input ena;
input [1 : 0] wea;
input [11 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;

// synthesis translate_off

      BLK_MEM_GEN_V3_3 #(
		.C_ADDRA_WIDTH(12),
		.C_ADDRB_WIDTH(12),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(8),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("spartan3"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(0),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(4096),
		.C_READ_DEPTH_B(4096),
		.C_READ_WIDTH_A(16),
		.C_READ_WIDTH_B(16),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(1),
		.C_USE_BYTE_WEB(1),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(2),
		.C_WEB_WIDTH(2),
		.C_WRITE_DEPTH_A(4096),
		.C_WRITE_DEPTH_B(4096),
		.C_WRITE_MODE_A("WRITE_FIRST"),
		.C_WRITE_MODE_B("WRITE_FIRST"),
		.C_WRITE_WIDTH_A(16),
		.C_WRITE_WIDTH_B(16),
		.C_XDEVICEFAMILY("spartan3adsp"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.DOUTA(douta),
		.RSTA(),
		.REGCEA(),
		.CLKB(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.ADDRB(),
		.DINB(),
		.DOUTB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of spartan3adsp_pmem is "black_box"

endmodule
module virtex5_dmem(
	clka,
	ena,
	wea,
	addra,
	dina,
	douta);


input clka;
input ena;
input [1 : 0] wea;
input [9 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;

// synthesis translate_off

      BLK_MEM_GEN_V3_3 #(
		.C_ADDRA_WIDTH(10),
		.C_ADDRB_WIDTH(10),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(8),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(0),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(1024),
		.C_READ_DEPTH_B(1024),
		.C_READ_WIDTH_A(16),
		.C_READ_WIDTH_B(16),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(1),
		.C_USE_BYTE_WEB(1),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(2),
		.C_WEB_WIDTH(2),
		.C_WRITE_DEPTH_A(1024),
		.C_WRITE_DEPTH_B(1024),
		.C_WRITE_MODE_A("WRITE_FIRST"),
		.C_WRITE_MODE_B("WRITE_FIRST"),
		.C_WRITE_WIDTH_A(16),
		.C_WRITE_WIDTH_B(16),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.DOUTA(douta),
		.RSTA(),
		.REGCEA(),
		.CLKB(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.ADDRB(),
		.DINB(),
		.DOUTB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of virtex5_dmem is "black_box"

endmodule
module virtex5_pmem(
	clka,
	ena,
	wea,
	addra,
	dina,
	douta);


input clka;
input ena;
input [1 : 0] wea;
input [11 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;

// synthesis translate_off

      BLK_MEM_GEN_V3_3 #(
		.C_ADDRA_WIDTH(12),
		.C_ADDRB_WIDTH(12),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(8),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(0),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(4096),
		.C_READ_DEPTH_B(4096),
		.C_READ_WIDTH_A(16),
		.C_READ_WIDTH_B(16),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(1),
		.C_USE_BYTE_WEB(1),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(2),
		.C_WEB_WIDTH(2),
		.C_WRITE_DEPTH_A(4096),
		.C_WRITE_DEPTH_B(4096),
		.C_WRITE_MODE_A("WRITE_FIRST"),
		.C_WRITE_MODE_B("WRITE_FIRST"),
		.C_WRITE_WIDTH_A(16),
		.C_WRITE_WIDTH_B(16),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.DOUTA(douta),
		.RSTA(),
		.REGCEA(),
		.CLKB(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.ADDRB(),
		.DINB(),
		.DOUTB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of virtex5_pmem is "black_box"

endmodule
module spartan3adsp_dmem(
	clka,
	ena,
	wea,
	addra,
	dina,
	douta);


input clka;
input ena;
input [1 : 0] wea;
input [9 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;

// synthesis translate_off

      BLK_MEM_GEN_V3_3 #(
		.C_ADDRA_WIDTH(10),
		.C_ADDRB_WIDTH(10),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(8),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("spartan3"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(0),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(1024),
		.C_READ_DEPTH_B(1024),
		.C_READ_WIDTH_A(16),
		.C_READ_WIDTH_B(16),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(1),
		.C_USE_BYTE_WEB(1),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(2),
		.C_WEB_WIDTH(2),
		.C_WRITE_DEPTH_A(1024),
		.C_WRITE_DEPTH_B(1024),
		.C_WRITE_MODE_A("WRITE_FIRST"),
		.C_WRITE_MODE_B("WRITE_FIRST"),
		.C_WRITE_WIDTH_A(16),
		.C_WRITE_WIDTH_B(16),
		.C_XDEVICEFAMILY("spartan3adsp"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.DOUTA(douta),
		.RSTA(),
		.REGCEA(),
		.CLKB(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.ADDRB(),
		.DINB(),
		.DOUTB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of spartan3adsp_dmem is "black_box"

endmodule
module virtex4_pmem(
	clka,
	ena,
	wea,
	addra,
	dina,
	douta);


input clka;
input ena;
input [1 : 0] wea;
input [11 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;

// synthesis translate_off

      BLK_MEM_GEN_V3_3 #(
		.C_ADDRA_WIDTH(12),
		.C_ADDRB_WIDTH(12),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(8),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex4"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(0),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(4096),
		.C_READ_DEPTH_B(4096),
		.C_READ_WIDTH_A(16),
		.C_READ_WIDTH_B(16),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(1),
		.C_USE_BYTE_WEB(1),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(2),
		.C_WEB_WIDTH(2),
		.C_WRITE_DEPTH_A(4096),
		.C_WRITE_DEPTH_B(4096),
		.C_WRITE_MODE_A("WRITE_FIRST"),
		.C_WRITE_MODE_B("WRITE_FIRST"),
		.C_WRITE_WIDTH_A(16),
		.C_WRITE_WIDTH_B(16),
		.C_XDEVICEFAMILY("virtex4"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.DOUTA(douta),
		.RSTA(),
		.REGCEA(),
		.CLKB(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.ADDRB(),
		.DINB(),
		.DOUTB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of virtex4_pmem is "black_box"

endmodule
module virtex4_dmem(
	clka,
	ena,
	wea,
	addra,
	dina,
	douta);


input clka;
input ena;
input [1 : 0] wea;
input [9 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;

// synthesis translate_off

      BLK_MEM_GEN_V3_3 #(
		.C_ADDRA_WIDTH(10),
		.C_ADDRB_WIDTH(10),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(8),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex4"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(0),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(1024),
		.C_READ_DEPTH_B(1024),
		.C_READ_WIDTH_A(16),
		.C_READ_WIDTH_B(16),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(1),
		.C_USE_BYTE_WEB(1),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(2),
		.C_WEB_WIDTH(2),
		.C_WRITE_DEPTH_A(1024),
		.C_WRITE_DEPTH_B(1024),
		.C_WRITE_MODE_A("WRITE_FIRST"),
		.C_WRITE_MODE_B("WRITE_FIRST"),
		.C_WRITE_WIDTH_A(16),
		.C_WRITE_WIDTH_B(16),
		.C_XDEVICEFAMILY("virtex4"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.DOUTA(douta),
		.RSTA(),
		.REGCEA(),
		.CLKB(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.ADDRB(),
		.DINB(),
		.DOUTB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of virtex4_dmem is "black_box"

endmodule
module spartan6_pmem(
	clka,
	ena,
	wea,
	addra,
	dina,
	douta);


input clka;
input ena;
input [1 : 0] wea;
input [11 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;

// synthesis translate_off

      BLK_MEM_GEN_V3_3 #(
		.C_ADDRA_WIDTH(12),
		.C_ADDRB_WIDTH(12),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(8),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("spartan6"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(0),
		.C_HAS_INJECTERR(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_RSTA(0),
		.C_HAS_RSTB(0),
		.C_INITA_VAL("0"),
		.C_INITB_VAL("0"),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(0),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(4096),
		.C_READ_DEPTH_B(4096),
		.C_READ_WIDTH_A(16),
		.C_READ_WIDTH_B(16),
		.C_RSTRAM_A(0),
		.C_RSTRAM_B(0),
		.C_RST_PRIORITY_A("CE"),
		.C_RST_PRIORITY_B("CE"),
		.C_RST_TYPE("SYNC"),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_USE_BYTE_WEA(1),
		.C_USE_BYTE_WEB(1),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_WEA_WIDTH(2),
		.C_WEB_WIDTH(2),
		.C_WRITE_DEPTH_A(4096),
		.C_WRITE_DEPTH_B(4096),
		.C_WRITE_MODE_A("WRITE_FIRST"),
		.C_WRITE_MODE_B("WRITE_FIRST"),
		.C_WRITE_WIDTH_A(16),
		.C_WRITE_WIDTH_B(16),
		.C_XDEVICEFAMILY("spartan6"))
	inst (
		.CLKA(clka),
		.ENA(ena),
		.WEA(wea),
		.ADDRA(addra),
		.DINA(dina),
		.DOUTA(douta),
		.RSTA(),
		.REGCEA(),
		.CLKB(),
		.RSTB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.ADDRB(),
		.DINB(),
		.DOUTB(),
		.INJECTSBITERR(),
		.INJECTDBITERR(),
		.SBITERR(),
		.DBITERR(),
		.RDADDRECC());


// synthesis translate_on

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of spartan6_pmem is "black_box"

endmodule
module dmem(WD,RD,WEN,REN,WADDR,RADDR,RWCLK,RESET);
input [7:0] WD;
output [7:0] RD;
input  WEN, REN;
input [9:0] WADDR, RADDR;
input RWCLK, RESET;

    wire VCC, GND;
    
    VCC VCC_1_net(.Y(VCC));
    GND GND_1_net(.Y(GND));
    RAM4K9 dmem_R0C1(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9(
        WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]), .ADDRA6(
        WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), .ADDRA3(
        WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), .ADDRA0(
        WADDR[0]), .ADDRB11(GND), .ADDRB10(GND), .ADDRB9(RADDR[9])
        , .ADDRB8(RADDR[8]), .ADDRB7(RADDR[7]), .ADDRB6(RADDR[6]), 
        .ADDRB5(RADDR[5]), .ADDRB4(RADDR[4]), .ADDRB3(RADDR[3]), 
        .ADDRB2(RADDR[2]), .ADDRB1(RADDR[1]), .ADDRB0(RADDR[0]), 
        .DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND), 
        .DINA4(GND), .DINA3(WD[7]), .DINA2(WD[6]), .DINA1(WD[5]), 
        .DINA0(WD[4]), .DINB8(GND), .DINB7(GND), .DINB6(GND), 
        .DINB5(GND), .DINB4(GND), .DINB3(GND), .DINB2(GND), 
        .DINB1(GND), .DINB0(GND), .WIDTHA0(GND), .WIDTHA1(VCC), 
        .WIDTHB0(GND), .WIDTHB1(VCC), .PIPEA(GND), .PIPEB(VCC), 
        .WMODEA(GND), .WMODEB(GND), .BLKA(WEN), .BLKB(REN), .WENA(
        GND), .WENB(VCC), .CLKA(RWCLK), .CLKB(RWCLK), .RESET(
        RESET), .DOUTA8(), .DOUTA7(), .DOUTA6(), .DOUTA5(), 
        .DOUTA4(), .DOUTA3(), .DOUTA2(), .DOUTA1(), .DOUTA0(), 
        .DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(), .DOUTB4(), 
        .DOUTB3(RD[7]), .DOUTB2(RD[6]), .DOUTB1(RD[5]), .DOUTB0(
        RD[4]));
    RAM4K9 dmem_R0C0(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9(
        WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]), .ADDRA6(
        WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), .ADDRA3(
        WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), .ADDRA0(
        WADDR[0]), .ADDRB11(GND), .ADDRB10(GND), .ADDRB9(RADDR[9])
        , .ADDRB8(RADDR[8]), .ADDRB7(RADDR[7]), .ADDRB6(RADDR[6]), 
        .ADDRB5(RADDR[5]), .ADDRB4(RADDR[4]), .ADDRB3(RADDR[3]), 
        .ADDRB2(RADDR[2]), .ADDRB1(RADDR[1]), .ADDRB0(RADDR[0]), 
        .DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND), 
        .DINA4(GND), .DINA3(WD[3]), .DINA2(WD[2]), .DINA1(WD[1]), 
        .DINA0(WD[0]), .DINB8(GND), .DINB7(GND), .DINB6(GND), 
        .DINB5(GND), .DINB4(GND), .DINB3(GND), .DINB2(GND), 
        .DINB1(GND), .DINB0(GND), .WIDTHA0(GND), .WIDTHA1(VCC), 
        .WIDTHB0(GND), .WIDTHB1(VCC), .PIPEA(GND), .PIPEB(VCC), 
        .WMODEA(GND), .WMODEB(GND), .BLKA(WEN), .BLKB(REN), .WENA(
        GND), .WENB(VCC), .CLKA(RWCLK), .CLKB(RWCLK), .RESET(
        RESET), .DOUTA8(), .DOUTA7(), .DOUTA6(), .DOUTA5(), 
        .DOUTA4(), .DOUTA3(), .DOUTA2(), .DOUTA1(), .DOUTA0(), 
        .DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(), .DOUTB4(), 
        .DOUTB3(RD[3]), .DOUTB2(RD[2]), .DOUTB1(RD[1]), .DOUTB0(
        RD[0]));
    
endmodule
module ram (

// OUTPUTs
    ram_dout,                      // RAM data output

// INPUTs
    ram_addr,                      // RAM address
    ram_cen,                       // RAM chip enable (low active)
    ram_clk,                       // RAM clock
    ram_din,                       // RAM data input
    ram_wen                        // RAM write enable (low active)
);

// PARAMETERs
//============
parameter ADDR_MSB   =  6;         // MSB of the address bus
parameter MEM_SIZE   =  256;       // Memory size in bytes

// OUTPUTs
//============
output      [15:0] ram_dout;       // RAM data output

// INPUTs
//============
input [ADDR_MSB:0] ram_addr;       // RAM address
input              ram_cen;        // RAM chip enable (low active)
input              ram_clk;        // RAM clock
input       [15:0] ram_din;        // RAM data input
input        [1:0] ram_wen;        // RAM write enable (low active)


// RAM
//============

reg         [15:0] mem [0:(MEM_SIZE/2)-1];
reg   [ADDR_MSB:0] ram_addr_reg;

wire        [15:0] mem_val = mem[ram_addr];
   
  
always @(posedge ram_clk)
  if (~ram_cen & ram_addr<(MEM_SIZE/2))
    begin
      if      (ram_wen==2'b00) mem[ram_addr] <= ram_din;
      else if (ram_wen==2'b01) mem[ram_addr] <= {ram_din[15:8], mem_val[7:0]};
      else if (ram_wen==2'b10) mem[ram_addr] <= {mem_val[15:8], ram_din[7:0]};
      ram_addr_reg <= ram_addr;
    end

assign ram_dout = mem[ram_addr_reg];


endmodule // ram
module  io_cell (

// INOUTs
    pad,                       // I/O Pad
		 
// OUTPUTs
    data_in,                   // Input value

// INPUTs
    data_out_en,               // Output enable
    data_out                   // Output value
);

// INOUTs
//=========
inout          pad;            // I/O Pad

// OUTPUTs
//=========
output         data_in;        // Input value

// INPUTs
//=========
input          data_out_en;    // Output enable
input          data_out;       // Output value


//=============================================================================
// 1)  I/O CELL
//=============================================================================

assign  data_in  =  pad;
assign  pad      =  data_out_en ? data_out : 1'bz;


endmodule // io_cell
module MAXPOOL1_TB;

	// Inputs
	reg [21:0] y;
	reg clk;
	reg start;
	reg reset;

	// Outputs
	wire [21:0] z;
	wire [3:0] mx_done;

	// Instantiate the Unit Under Test (UUT)
	MAXPOOL1 uut (
		.y(y), 
		.clk(clk), 
		.start(start), 
		.reset(reset),
		.mx_done(mx_done),
		.z(z)
	);

	initial begin
		// Initialize Inputs
		y = 0;
		clk = 0;
		start = 0;
		reset = 0;

		// Wait 100 ns for global reset to finish
		#50;
      reset = 1; 
		// Add stimulus here
		#100 reset = 0; start = 1; 
		    y = 15;  #50  y = 20;  #50  y = 25;  #50  y = 30; #50 y = 35; #50 y = 40; #50 y = 45; #50 y = 50; 
		#50 y = 55;  #50  y = 60;  #50  y = 65;  #50  y = 70; #50 y = 75; #50 y = 80; #50 y = 15; #50 y = 90; 
		#50 y = 100; #50  y = 120; #50  y = 125; #50 y = 30;  #50 y = 35; #50 y = 40; #50 y = 45; #50 y = 50; 
		#50 y = 55;  #50  y = 60;  #50  y = 65;  #50 y = 70;  #50 y = 75; #50 y = 80; #50 y = 85; #50 y = 90; 
		#50 y = 55;  #50  y = 60;  #50  y = 65;  #50  y = 70; #50 y = 75; #50 y = 80; #50 y = 15; #50 y = 90; 
		#50 y = 100; #50  y = 120; #50  y = 125; #50 y = 30;  #50 y = 35; #50 y = 40; #50 y = 45; #50 y = 50; 
		#50 y = 55;  #50  y = 60;  #50  y = 65;  #50 y = 70;  #50 y = 75; #50 y = 80; #50 y = 85; #50 y = 90;
		#50 y = 55;  #50  y = 60;  #50  y = 65;  #50  y = 70; #50 y = 75; #50 y = 80; #50 y = 15; #50 y = 90; 
		#50 y = 100; #50  y = 120; #50  y = 125; #50 y = 30;  #50 y = 35; #50 y = 40; #50 y = 45; #50 y = 1000; 
		#50 y = 55;  #50  y = 60;  #50  y = 65;  #50 y = 70;  #50 y = 75; #50 y = 80; #50 y = 85; #50 y = 90;
		#50 y = 55;  #50  y = 60;  #50  y = 65;  #50  y = 150; #50 y = 75; #50 y = 80; #50 y = 15; #50 y = 90; 
		#50 y = 100; #50  y = 120; #50  y = 125; #50 y = 30;  #50 y = 35; #50 y = 40; #50 y = 45; #50 y = 50; 
		#50 y = 55;  #50  y = 60;  #50  y = 65;  #50 y = 70;  #50 y = 75; #50 y = 80; #50 y = 85; #50 y = 90; //#10000 start = 0;
		
	end
	
	always #25 clk = ~clk;
      
endmodule
module NODE_10(
input signed [35:0] A,
input [5:0] step,
input CLK,
input ENABLE,
input RST,
output reg signed [39:0] OUT //16-bit output
    );
    
reg signed [39:0] accumulator = 40'd0; //store the matrix mult here
reg signed [8:0] weights [63:0]; //store the weights here
reg signed [7:0] bias; //store node bias here

initial begin
   weights[0]<=9'b001011010;
   weights[1]<=9'b000100011;
   weights[2]<=9'b000000100;
   weights[3]<=9'b111110011;
   weights[4]<=9'b000000110;
   weights[5]<=9'b000101110;
   weights[6]<=9'b111000001;
   weights[7]<=9'b000000000;
   weights[8]<=9'b111100110;
   weights[9]<=9'b111110011;
   weights[10]<=9'b000000110;
   weights[11]<=9'b000010100;
   weights[12]<=9'b111111100;
   weights[13]<=9'b000110101;
   weights[14]<=9'b000001111;
   weights[15]<=9'b111101100;
   weights[16]<=9'b111010111;
   weights[17]<=9'b000100011;
   weights[18]<=9'b111110101;
   weights[19]<=9'b000101001;
   weights[20]<=9'b110110100;
   weights[21]<=9'b000011010;
   weights[22]<=9'b111110010;
   weights[23]<=9'b111100001;
   weights[24]<=9'b000011000;
   weights[25]<=9'b000101011;
   weights[26]<=9'b111100000;
   weights[27]<=9'b000010001;
   weights[28]<=9'b000001101;
   weights[29]<=9'b000100011;
   weights[30]<=9'b000111101;
   weights[31]<=9'b000011110;
   weights[32]<=9'b001000101;
   weights[33]<=9'b000110011;
   weights[34]<=9'b000010101;
   weights[35]<=9'b111110000;
   weights[36]<=9'b111101100;
   weights[37]<=9'b111011000;
   weights[38]<=9'b000000011;
   weights[39]<=9'b111011101;
   weights[40]<=9'b000001111;
   weights[41]<=9'b111011111;
   weights[42]<=9'b111100111;
   weights[43]<=9'b111101010;
   weights[44]<=9'b000101111;
   weights[45]<=9'b111101001;
   weights[46]<=9'b000001000;
   weights[47]<=9'b000011110;
   weights[48]<=9'b000000000;
   weights[49]<=9'b000110010;
   weights[50]<=9'b111110010;
   weights[51]<=9'b111000100;
   weights[52]<=9'b111101011;
   weights[53]<=9'b000001101;
   weights[54]<=9'b000010001;
   weights[55]<=9'b000010011;
   weights[56]<=9'b000011100;
   weights[57]<=9'b111111111;
   weights[58]<=9'b111110101;
   weights[59]<=9'b111110010;
   weights[60]<=9'b111110110;
   weights[61]<=9'b000010011;
   weights[62]<=9'b111111101;
   weights[63]<=9'b000100010;
   bias<=8'b11001100;
 end
 
 //MAIN SYNCHRONOUS ACCUMULATION BLOCK
 always @ ( posedge CLK )
 begin
    if( ENABLE == 1 && RST == 0 )
    begin
        if ( step == 0 )
        begin
            accumulator <=  A * weights[step];
        end
        else if( step == 63 )
        begin
            OUT <= accumulator + bias + A * weights[step];
        end else accumulator <=  A * weights[step] + accumulator;
    end
 end

endmodule
module ShiftReg2(
    input [21:0] x,
    input clk,
    output reg [22:0] o1,o2,o3,o4
    );
    
    reg [21:0] Register [0:10];
    integer i;
    
    always@(posedge clk)
    begin
    Register[10] <= x;
    for(i=0; i < 10; i = i + 1)
    begin
        Register[i] <= Register[i+1];
    end
    
    o1 <= {1'b0, Register[0]};
    o2 <= {1'b0, Register[1]};
    
    o3 <= {1'b0, Register[9]};
    o4 <= {1'b0, Register[10]};
     
    end
    
endmodule
module NODE_0(
input signed [35:0] A,
input [5:0] step,
input CLK,
input ENABLE,
input RST,
output reg signed [39:0] OUT, //128-bit output
output reg DONE
    );

reg signed [39:0] accumulator = 40'd0; //store the matrix mult here
reg signed [8:0] weights [63:0]; //store the weights here
reg signed [7:0] bias; //store node bias here

initial begin
   weights[0]<=9'b111001101;
   weights[1]<=9'b111011100;
   weights[2]<=9'b000000110;
   weights[3]<=9'b000011101;
   weights[4]<=9'b000100100;
   weights[5]<=9'b001010000;
   weights[6]<=9'b000100101;
   weights[7]<=9'b000010010;
   weights[8]<=9'b111101100;
   weights[9]<=9'b000000010;
   weights[10]<=9'b111011011;
   weights[11]<=9'b001010010;
   weights[12]<=9'b111000111;
   weights[13]<=9'b000111000;
   weights[14]<=9'b111101101;
   weights[15]<=9'b111010100;
   weights[16]<=9'b111010101;
   weights[17]<=9'b000000101;
   weights[18]<=9'b111111100;
   weights[19]<=9'b111111111;
   weights[20]<=9'b000111010;
   weights[21]<=9'b111010100;
   weights[22]<=9'b000000001;
   weights[23]<=9'b111011111;
   weights[24]<=9'b000000001;
   weights[25]<=9'b000101010;
   weights[26]<=9'b000011110;
   weights[27]<=9'b000000001;
   weights[28]<=9'b001000110;
   weights[29]<=9'b000010101;
   weights[30]<=9'b000000010;
   weights[31]<=9'b000001000;
   weights[32]<=9'b110011110;
   weights[33]<=9'b000001010;
   weights[34]<=9'b000100011;
   weights[35]<=9'b000010011;
   weights[36]<=9'b111101101;
   weights[37]<=9'b111011110;
   weights[38]<=9'b000010110;
   weights[39]<=9'b111110011;
   weights[40]<=9'b111100001;
   weights[41]<=9'b111110001;
   weights[42]<=9'b000000001;
   weights[43]<=9'b111110110;
   weights[44]<=9'b000100101;
   weights[45]<=9'b000100101;
   weights[46]<=9'b000010101;
   weights[47]<=9'b000000010;
   weights[48]<=9'b111011100;
   weights[49]<=9'b000100001;
   weights[50]<=9'b111101011;
   weights[51]<=9'b000110110;
   weights[52]<=9'b000001011;
   weights[53]<=9'b111001000;
   weights[54]<=9'b000101010;
   weights[55]<=9'b111111001;
   weights[56]<=9'b000001100;
   weights[57]<=9'b000010001;
   weights[58]<=9'b000010001;
   weights[59]<=9'b111111000;
   weights[60]<=9'b111110100;
   weights[61]<=9'b111111001;
   weights[62]<=9'b111010100;
   weights[63]<=9'b000100001;
   bias<=8'b11111010;
   end


 //MAIN SYNCHRONOUS ACCUMULATION BLOCK
 always @ ( posedge CLK )
 begin
    if( ENABLE == 1 && RST == 0 )
    begin
        if ( step == 0 )
        begin
            accumulator <=  A * weights[step];
            DONE <= 0;
        end
        else if( step == 63 )
        begin
            OUT <= accumulator + bias + A * weights[step];
            DONE <= 1;
        end else accumulator <=  A * weights[step] + accumulator;
    end
 end

endmodule
module NODE_6(
input signed [35:0] A,
input [5:0] step,
input CLK,
input ENABLE,
input RST,
output reg signed [39:0] OUT //16-bit output
    );
    
reg signed [39:0] accumulator = 40'd0; //store the matrix mult here
reg signed [8:0] weights [63:0]; //store the weights here
reg signed [7:0] bias; //store node bias here

 initial begin
  weights[0]<=9'b111110111;
   weights[1]<=9'b110111100;
   weights[2]<=9'b000101000;
   weights[3]<=9'b111000110;
   weights[4]<=9'b000000011;
   weights[5]<=9'b110101011;
   weights[6]<=9'b000000110;
   weights[7]<=9'b000001001;
   weights[8]<=9'b000001110;
   weights[9]<=9'b111011010;
   weights[10]<=9'b111100101;
   weights[11]<=9'b000010010;
   weights[12]<=9'b000100100;
   weights[13]<=9'b111101001;
   weights[14]<=9'b000100001;
   weights[15]<=9'b111110111;
   weights[16]<=9'b111100110;
   weights[17]<=9'b000100101;
   weights[18]<=9'b110111010;
   weights[19]<=9'b000101111;
   weights[20]<=9'b000001010;
   weights[21]<=9'b111111111;
   weights[22]<=9'b111100011;
   weights[23]<=9'b001000000;
   weights[24]<=9'b000110101;
   weights[25]<=9'b101101011;
   weights[26]<=9'b000100001;
   weights[27]<=9'b000010110;
   weights[28]<=9'b111011101;
   weights[29]<=9'b111111111;
   weights[30]<=9'b111001101;
   weights[31]<=9'b101011010;
   weights[32]<=9'b111111010;
   weights[33]<=9'b111101000;
   weights[34]<=9'b000010001;
   weights[35]<=9'b000000111;
   weights[36]<=9'b000001100;
   weights[37]<=9'b111010001;
   weights[38]<=9'b111101110;
   weights[39]<=9'b000001110;
   weights[40]<=9'b000100000;
   weights[41]<=9'b000101001;
   weights[42]<=9'b000000011;
   weights[43]<=9'b000000011;
   weights[44]<=9'b000100000;
   weights[45]<=9'b111010101;
   weights[46]<=9'b111001011;
   weights[47]<=9'b000101010;
   weights[48]<=9'b111010101;
   weights[49]<=9'b111111010;
   weights[50]<=9'b000100010;
   weights[51]<=9'b000001010;
   weights[52]<=9'b000011101;
   weights[53]<=9'b000000011;
   weights[54]<=9'b110101000;
   weights[55]<=9'b111101100;
   weights[56]<=9'b111101000;
   weights[57]<=9'b000001001;
   weights[58]<=9'b000000011;
   weights[59]<=9'b000000101;
   weights[60]<=9'b000100001;
   weights[61]<=9'b111101111;
   weights[62]<=9'b000110101;
   weights[63]<=9'b111100010;
   bias<=8'b11111100;
 end
 
 //MAIN SYNCHRONOUS ACCUMULATION BLOCK
 always @ ( posedge CLK )
 begin
    if( ENABLE == 1 && RST == 0 )
    begin
        if ( step == 0 )
        begin
            accumulator <=  A * weights[step];
        end
        else if( step == 63 )
        begin
            OUT <= accumulator + bias + A * weights[step];
        end else accumulator <=  A * weights[step] + accumulator;
    end
 end

endmodule
module NODE_15(
input signed [35:0] A,
input [5:0] step,
input CLK,
input ENABLE,
input RST,
output reg signed [39:0] OUT //16-bit output
    );
    
reg signed [39:0] accumulator = 40'd0; //store the matrix mult here
reg signed [8:0] weights [63:0]; //store the weights here
reg signed [7:0] bias; //store node bias here

initial begin
   weights[0]<=9'b111010111;
   weights[1]<=9'b111010101;
   weights[2]<=9'b000000100;
   weights[3]<=9'b000010000;
   weights[4]<=9'b111011011;
   weights[5]<=9'b101111101;
   weights[6]<=9'b110001010;
   weights[7]<=9'b000001101;
   weights[8]<=9'b111110101;
   weights[9]<=9'b111111000;
   weights[10]<=9'b000001100;
   weights[11]<=9'b000100110;
   weights[12]<=9'b111010111;
   weights[13]<=9'b111110010;
   weights[14]<=9'b111111110;
   weights[15]<=9'b111100110;
   weights[16]<=9'b111100000;
   weights[17]<=9'b000100101;
   weights[18]<=9'b000011011;
   weights[19]<=9'b111100000;
   weights[20]<=9'b000011000;
   weights[21]<=9'b110010100;
   weights[22]<=9'b000101000;
   weights[23]<=9'b111000111;
   weights[24]<=9'b000001010;
   weights[25]<=9'b111111100;
   weights[26]<=9'b111100101;
   weights[27]<=9'b000001001;
   weights[28]<=9'b111111110;
   weights[29]<=9'b111110010;
   weights[30]<=9'b111010000;
   weights[31]<=9'b111010000;
   weights[32]<=9'b000100011;
   weights[33]<=9'b111011000;
   weights[34]<=9'b000000011;
   weights[35]<=9'b111101111;
   weights[36]<=9'b000100000;
   weights[37]<=9'b111110010;
   weights[38]<=9'b111001100;
   weights[39]<=9'b000010001;
   weights[40]<=9'b000100001;
   weights[41]<=9'b111011001;
   weights[42]<=9'b000010010;
   weights[43]<=9'b000010001;
   weights[44]<=9'b110101101;
   weights[45]<=9'b110101101;
   weights[46]<=9'b001000000;
   weights[47]<=9'b111110100;
   weights[48]<=9'b000011010;
   weights[49]<=9'b110110110;
   weights[50]<=9'b000001101;
   weights[51]<=9'b111110110;
   weights[52]<=9'b000011110;
   weights[53]<=9'b000000010;
   weights[54]<=9'b000101101;
   weights[55]<=9'b000100010;
   weights[56]<=9'b111111001;
   weights[57]<=9'b000001110;
   weights[58]<=9'b000000001;
   weights[59]<=9'b000001000;
   weights[60]<=9'b111011011;
   weights[61]<=9'b110100010;
   weights[62]<=9'b111101011;
   weights[63]<=9'b111001011;
   bias<=8'b00001110;
 end
 
 always @ ( posedge CLK )
 begin
    if( ENABLE == 1 && RST == 0 )
    begin
        if ( step == 0 )
        begin
            accumulator <=  A * weights[step];
        end
        else if( step == 63 )
        begin
            OUT <= accumulator + bias + A * weights[step];
        end else accumulator <=  A * weights[step] + accumulator;
    end
 end
 
endmodule
module Counter2(
    input clk,
    input start,
    input reset,
    output reg [3:0] count1,
    output reg [3:0] count2,
    output reg done
    );
    
    parameter mod = 9;
    
    always @ ( posedge clk )
    begin
        if( reset || ~start )
        begin
            count1 <= 0;
            count2 <= 0;
            done <= 0;
        end else if ( start )
        begin
            if( count2 < mod-1 )
            begin
                if( count1 < mod-1 )
                begin
                    count1 <= count1 + 1;
                    done <= 0;
                end else
                begin
                    count1 <= 0;
                    count2 <= count2 + 1;
                    done <= 0;
                end
            end else if ( count2 == mod-1 )
            begin
                if( count1 < mod - 2 )
                    begin
                        count1 <= count1 + 1;
                        done <= 0;
                    end else if ( count1 == mod - 2 )
                    begin
                        count1 <= count1 + 1;
                        done <= 1;
                    end
                    else
                    begin
                        count1 <= 0;
                        count2 <= 0;
                        done <= 0;
                    end
            end
        end
    end
endmodule
module TB_CONV1;
    reg clk;
    reg [7:0] R,G,B;
    reg reset;
    
    wire signed [21:0] y;
    wire [1:0] state;
    wire [6:0] count;
    
    CONV1 uut( .clk(clk), .reset(reset), .R(R), .G(G), .B(B), .y(y), .states(state), .count(count));
    
    always #5 clk = ~clk;
         
    integer image_R,image_G,image_B;
    integer output_File;
    integer filter_num = 0; //Filter Number (0 to 7)
         
     initial begin
         clk = 0;
         reset = 0;
         image_R=$fopen("image_R.txt","r");
         image_G=$fopen("image_G.txt","r");
         image_B=$fopen("image_B.txt","r");
         output_File=$fopen("convimage.txt","w");
         #400000;
         $finish;
     end
     
     always @ (posedge clk)
     begin
        $fwrite(output_File,"%d\n",y);
        if( (state == 1) && ( count < 64 ))
        begin
             $fscanf(image_R,"%d\n",R);
             $fscanf(image_G,"%d\n",G);
             $fscanf(image_B,"%d\n",B);
        end
         if($feof(image_R)&& $feof(image_G)&& $feof(image_B) && (filter_num != 7))
         begin
            $fclose(image_R);$fclose(image_G);$fclose(image_B);
            filter_num = filter_num + 1;
            image_R=$fopen("image_R.txt","r");
            image_G=$fopen("image_G.txt","r");
            image_B=$fopen("image_B.txt","r");
         end else if($feof(image_R)&& $feof(image_G)&& $feof(image_B) && (filter_num == 7))
         begin
            $fclose(image_R);$fclose(image_G);$fclose(image_B);
         end
         
     end
endmodule
module TB_CONV2;
    reg clk;
    reg reset;
    reg [21:0] G1, G2, G3, G4, G5, G6, G7, G8; 
    wire [6:0] addr2;
    wire signed [35:0] z;

    CONV2 uut( .G1(G1), .G2(G2), .G3(G3), .G4(G4), .G5(G5), .G6(G6), .G7(G7), .G8(G8), .clk(clk), .reset(reset), .addr(addr2),.y(z));    
    
    always #5 clk= ~clk;
    
    initial
    begin
        clk = 0;
        reset = 0;
        G1 = 1;
        G2 = 1;
        G3 = 1;
        G4 = 1;
        G5 = 1;
        G6 = 1;
        G7 = 1;
        G8 = 1;
        
        
    end
endmodule
module TB_WeightsRAM_CONV2;
    reg clk;
    reg enable;
    reg [3:0] addr;
    wire [35:0] weights;
    
    WeightsRAM_1 weightram1(.clk(clk), .enable(enable), .addr(addr), .weights(weights));
    
    always #5 clk = ~clk;
    
    initial begin
        clk=0;
        enable=0;
        addr=0;
        #3;
        enable = 1;
        #10;
        addr=1;
        #10;
        addr=2;
        #10;
        addr=5;
        #10;
        addr=15;
    end
endmodule
module ShiftReg(
    input [7:0] x,
    input clk,
    output reg [7:0] o1,o2,o3,o4,o5,o6,o7,o8,o9,o10,o11,o12,o13,o14,o15,o16
    );
    
    reg [7:0] Register [0:204];
    integer i;
    
 /* assign o1 = Register[0];
    assign o2 = Register[1];
    assign o3 = Register[2];
    assign o4 = Register[3];
    
    assign o5 = Register[67];
    assign o6 = Register[68];
    assign o7 = Register[69];
    assign o8 = Register[70];
    
    assign o9 = Register[134];
    assign o10 = Register[135];
    assign o11 = Register[136];
    assign o12 = Register[137];
    
    assign o13 = Register[201];
    assign o14 = Register[202];
    assign o15 = Register[203];
    assign o16 = Register[204];*/
    
    
    always@(posedge clk)
    begin
    Register[204] <= x;
    for(i=0; i < 204; i = i + 1)
    begin
        Register[i] <= Register[i+1];
    end
    
    o1 <= Register[0];
    o2 <= Register[1];
    o3 <= Register[2];
    o4 <= Register[3];
    
    o5 <= Register[67];
    o6 <= Register[68];
    o7 <= Register[69];
    o8 <= Register[70];
    
    o9 <= Register[134];
    o10 <= Register[135];
    o11 <= Register[136];
    o12 <= Register[137];
    
    o13 <= Register[201];
    o14 <= Register[202];
    o15 <= Register[203];
    o16 <= Register[204]; 
    end
    
endmodule
module counter_8(
    input clk,
    input start,
    input reset,
    output reg [3:0] count1,
    output reg [3:0] count2,
    output reg done
    );
    
    parameter mod = 8;
    
    always @ ( posedge clk )
    begin
        if( reset || ~start )
        begin
            count1 <= 0;
            count2 <= 0;
            done   <= 0;
        end else if ( start )
        begin
            if( count2 < mod-1 )
            begin
                if( count1 < mod-1+1 )
                begin
                    count1 <= count1 + 1;
                    done <= 0;
                end else
                begin
                    count1 <= 0;
                    count2 <= count2 + 1;
                    done <= 0;
                end
            end else if ( count2 == mod-1 )
            begin
                if( count1 < mod - 2+1 )
                    begin
                        count1 <= count1 + 1;
                        done <= 0;
                    end else if ( count1 == mod - 2+1 )
                    begin
                        count1 <= count1 + 1;
                        done <= 1;
                    end
                    else
                    begin
                        count1 <= 0;
                        count2 <= 0;
                        done   <= 0;
                    end
            end
        end
    end
endmodule
module Counter(
    input clk,
    input start,
    input reset,
    output reg [6:0] count1,
    output reg [6:0] count2,
    output reg done
    );
    
    parameter mod = 67;
    
    always @ ( posedge clk )
    begin
        if( reset || ~start )
        begin
            count1 <= 0;
            count2 <= 0;
            done <= 0;
        end else if ( start )
        begin
            if( count2 < mod-1 )
            begin
                if( count1 < mod-1 )
                begin
                    count1 <= count1 + 1;
                    done <= 0;
                end else
                begin
                    count1 <= 0;
                    count2 <= count2 + 1;
                    done <= 0;
                end
            end else if ( count2 == mod-1 )
            begin
                if( count1 < mod - 2 )
                    begin
                        count1 <= count1 + 1;
                        done <= 0;
                    end else if ( count1 == mod - 2 )
                    begin
                        count1 <= count1 + 1;
                        done <= 1;
                    end
                    else
                    begin
                        count1 <= 0;
                        count2 <= 0;
                        done <= 0;
                    end
            end
        end
    end
endmodule
module NODE_8(
input signed [35:0] A,
input [5:0] step,
input CLK,
input ENABLE,
input RST,
output reg signed [39:0] OUT //16-bit output
    );
    
reg signed [39:0] accumulator = 40'd0; //store the matrix mult here
reg signed [8:0] weights [63:0]; //store the weights here
reg signed [7:0] bias; //store node bias here

initial begin
   weights[0]<=9'b000110010;
   weights[1]<=9'b111110010;
   weights[2]<=9'b000000111;
   weights[3]<=9'b111101101;
   weights[4]<=9'b000000011;
   weights[5]<=9'b000000010;
   weights[6]<=9'b110100011;
   weights[7]<=9'b000110011;
   weights[8]<=9'b000001011;
   weights[9]<=9'b000011001;
   weights[10]<=9'b111101110;
   weights[11]<=9'b000000110;
   weights[12]<=9'b000111000;
   weights[13]<=9'b000010010;
   weights[14]<=9'b111101100;
   weights[15]<=9'b000011010;
   weights[16]<=9'b111011011;
   weights[17]<=9'b111110111;
   weights[18]<=9'b000110010;
   weights[19]<=9'b001000101;
   weights[20]<=9'b111110010;
   weights[21]<=9'b111111011;
   weights[22]<=9'b111110111;
   weights[23]<=9'b111111111;
   weights[24]<=9'b111010110;
   weights[25]<=9'b000101010;
   weights[26]<=9'b000000110;
   weights[27]<=9'b111011011;
   weights[28]<=9'b111110101;
   weights[29]<=9'b111010101;
   weights[30]<=9'b000111000;
   weights[31]<=9'b111111101;
   weights[32]<=9'b001000010;
   weights[33]<=9'b111000100;
   weights[34]<=9'b000000000;
   weights[35]<=9'b111111101;
   weights[36]<=9'b000000100;
   weights[37]<=9'b111001011;
   weights[38]<=9'b000001110;
   weights[39]<=9'b111110000;
   weights[40]<=9'b111101111;
   weights[41]<=9'b000011111;
   weights[42]<=9'b000010100;
   weights[43]<=9'b111011010;
   weights[44]<=9'b001000111;
   weights[45]<=9'b110110101;
   weights[46]<=9'b000011100;
   weights[47]<=9'b111110111;
   weights[48]<=9'b000001111;
   weights[49]<=9'b001010000;
   weights[50]<=9'b110111011;
   weights[51]<=9'b000011111;
   weights[52]<=9'b000011000;
   weights[53]<=9'b111101101;
   weights[54]<=9'b001000000;
   weights[55]<=9'b000100001;
   weights[56]<=9'b000000110;
   weights[57]<=9'b000000011;
   weights[58]<=9'b111101010;
   weights[59]<=9'b111111110;
   weights[60]<=9'b111100011;
   weights[61]<=9'b000001010;
   weights[62]<=9'b110100110;
   weights[63]<=9'b110101100;
   bias<=8'b11111101;
 end
 
 always @ ( posedge CLK )
 begin
    if( ENABLE == 1 && RST == 0 )
    begin
        if ( step == 0 )
        begin
            accumulator <=  A * weights[step];
        end
        else if( step == 63 )
        begin
            OUT <= accumulator + bias + A * weights[step];
        end else accumulator <=  A * weights[step] + accumulator;
    end
 end

endmodule