dakies/OSS_Verilog huggingface dataset:
module SBCon
(
// Inputs
  PCLK,                 //-- APB bus clock
  PRESETn,              //-- APB bus reset
  PSEL,                 //-- APB device select
  PENABLE,              //-- identifies APB active cycle
  PWRITE,               //-- APB transfer direction
  PADDR,                //-- APB address
  PWDATA,               //-- APB write data

  SDA,                  // serial data input
// Outputs
  PRDATA,               //-- APB read data
  SCL,
  SDAOUTEN_n
);

  input          PCLK;
  input          PRESETn;
  input          PSEL;
  input          PENABLE;
  input          PWRITE;
  input   [7:2]  PADDR;
  input  [31:0]  PWDATA;
  input          SDA;
  output [31:0]  PRDATA;
  output         SCL;
  output         SDAOUTEN_n;


`define SB_CONTROL     6'b000000       // 0   status
`define SB_CONTROLS    6'b000000       // 0   set outputs SDA or SCL
`define SB_CONTROLC    6'b000001       // 4   clr outputs SDA or SCL

  reg   [1:0] reg_sb_enable;
  reg   [1:0] reg_prdataout;
  wire  [1:0] nxt_prdata;
  wire [31:0] PRDATA;


  // Enable registers have seperate set and clear operations
  //  WriteEnableRegs : process(PCLK, PRESETn)
  always @(posedge PCLK or negedge PRESETn)
  begin
    if (~PRESETn)
      begin
        reg_sb_enable <= 2'b00;
      end
    else
     begin
      if (PSEL & PWRITE & PENABLE)
       begin
         // set SB enable bits
        if (PADDR[7:2] == `SB_CONTROLS)
           reg_sb_enable <= PWDATA[1:0] | reg_sb_enable;

        // clear SB enable bits
        if (PADDR[7:2] == `SB_CONTROLC)
           reg_sb_enable <= (~PWDATA[1:0]) & reg_sb_enable;
       end
     end
  end

  assign nxt_prdata = ((PADDR == `SB_CONTROL) && (PSEL)) ? ({SDA,reg_sb_enable[0]}) : 2'b00;

//  --------------------------------------------------------------------------------
//  -- When the peripheral is not being accessed, '0's are driven
//  -- on the Read Databus (PRDATA) so as not to place any restrictions
//  -- on the method of external bus connection. The external data buses of the
//  -- peripherals on the APB may then be connected to the ASB-to-APB bridge using
//  -- Muxed or ORed bus connection method.
//  --------------------------------------------------------------------------------

  // Register output data
  always @(posedge PCLK or negedge PRESETn)
  begin
    if (~PRESETn)
      begin
        reg_prdataout[1:0] <= 2'b00;
      end
    else
      begin
        reg_prdataout[1:0] <= nxt_prdata[1:0];
      end
  end // ReadRegs;

  // Output to external
  assign PRDATA     = {{30{1'b0}},reg_prdataout};
  assign SCL        = reg_sb_enable[0];
  assign SDAOUTEN_n = reg_sb_enable[1];

endmodule
module fpga_100hz_gen (
  input  wire  clk25mhz,
  input  wire  reset_n,
  output wire  clk100hz
  );

  reg [16:0]  reg_cntr;

  reg         reg_clk100hz;

  // Counter overflow at 200Hz
  always @(posedge clk25mhz or negedge reset_n)
  begin
    if (~reset_n)
      reg_cntr <= {17{1'b0}};
    else
      if (reg_cntr==124999)
        reg_cntr <= {17{1'b0}};
      else
        reg_cntr <= reg_cntr + {{16{1'b0}}, 1'b1};
  end

  // Toggle at 200Hz -> 100Hz clock
  always @(posedge clk25mhz or negedge reset_n)
  begin
    if (~reset_n)
      reg_clk100hz <= 1'b0;
    else
      if (reg_cntr==124999)
        reg_clk100hz <= ~reg_clk100hz;
  end

  assign clk100hz = reg_clk100hz;

endmodule
module fpga_sync_regs (
  dest_clk,
  dest_resetn,
  source_data,
  dest_data
  );

//  Simple metastability register

parameter INPUT_WIDTH      = 8;                 // Width of data bus
parameter INPUT_MAX        = INPUT_WIDTH - 1;   // Upper bound of data vector

  input                dest_clk;
  input                dest_resetn;
  input  [INPUT_MAX:0] source_data;
  output [INPUT_MAX:0] dest_data;

  // synchronization registers to avoid metastability issue
  wire [INPUT_MAX:0] dest_data;
  reg  [INPUT_MAX:0] dest_data_i1;
  reg  [INPUT_MAX:0] dest_data_i2;

  always @ (posedge dest_clk or negedge dest_resetn)
  begin
  if (!dest_resetn) begin
    dest_data_i1 <= {INPUT_WIDTH{1'b0}};
    dest_data_i2 <= {INPUT_WIDTH{1'b0}};
  end else begin
    dest_data_i1 <= source_data;
    dest_data_i2 <= dest_data_i1;
  end
  end

  assign dest_data = dest_data_i2;

endmodule
module fpga_sys_bus_mux (
  input   wire            hclk,
  input   wire            hresetn,

  input   wire            spibus_select, // 0 = processor, 1 = SPI

  // Bus connection from processor
  input   wire            cpusys_hsel,        // select
  input   wire    [31:0]  cpusys_haddr,       // address
  input   wire     [1:0]  cpusys_htrans,      // transfer control
  input   wire     [2:0]  cpusys_hsize,       // size
  input   wire            cpusys_hwrite,      // write control
  input   wire    [31:0]  cpusys_hwdata,      // write data
  input   wire            cpusys_hready,      // ready

  output  wire            cpusys_hreadyout,   // ready
  output  wire    [31:0]  cpusys_hrdata,      // read data output from SRAM
  output  wire            cpusys_hresp,       // response

  // AHB connection from SPI to APB/AHB block
  input   wire            spi2mem_s1_hsel,
  input   wire    [31:0]  spi2mem_s1_haddr,
  input   wire     [1:0]  spi2mem_s1_htrans,
  input   wire            spi2mem_s1_hwrite,
  input   wire    [31:0]  spi2mem_s1_hwdata,
  input   wire     [1:0]  spi2mem_s1_hsize,

  output  wire    [31:0]  spi2mem_s1_hrdata,
  output  wire            spi2mem_s1_hready,
  output  wire            spi2mem_s1_hresp,

  // AHB connection to FPGA system
  output  wire            fpgasys_hsel,        // select
  output  wire    [31:0]  fpgasys_haddr,       // address
  output  wire     [1:0]  fpgasys_htrans,      // transfer control
  output  wire     [2:0]  fpgasys_hsize,       // size
  output  wire            fpgasys_hwrite,      // write control
  output  wire    [31:0]  fpgasys_hwdata,      // write data
  output  wire            fpgasys_hready,      // ready

  input   wire            fpgasys_hreadyout,   // ready
  input   wire    [31:0]  fpgasys_hrdata,      // read data output from SRAM
  input   wire            fpgasys_hresp        // response
  );

  // Simple bus mux - spibus_select can only be switched when CPU is not active

  assign fpgasys_hsel  = (spibus_select) ? spi2mem_s1_hsel  : cpusys_hsel;
  assign fpgasys_haddr = (spibus_select) ? spi2mem_s1_haddr : cpusys_haddr;
  assign fpgasys_htrans= (spibus_select) ? spi2mem_s1_htrans: cpusys_htrans;
  assign fpgasys_hsize = (spibus_select) ? {1'b0,spi2mem_s1_hsize}: cpusys_hsize;
  assign fpgasys_hwrite= (spibus_select) ? spi2mem_s1_hwrite  : cpusys_hwrite;
  assign fpgasys_hwdata= (spibus_select) ? spi2mem_s1_hwdata  : cpusys_hwdata;
  assign fpgasys_hready= (spibus_select) ? fpgasys_hreadyout  : cpusys_hready;

  assign cpusys_hreadyout  = (spibus_select) ? 1'b1  : fpgasys_hreadyout;
  assign cpusys_hrdata     = fpgasys_hrdata;
  assign cpusys_hresp      = (spibus_select) ? 1'b0 : fpgasys_hresp;

  assign spi2mem_s1_hrdata = fpgasys_hrdata;
  assign spi2mem_s1_hready = (spibus_select) ? fpgasys_hreadyout : 1'b1;
  assign spi2mem_s1_hresp  = (spibus_select) ? fpgasys_hresp     : 1'b0;

endmodule
module fpga_rst_sync  (
  input  wire  clk,
  input  wire  rst_n_in,
  input  wire  rst_request,
  output wire  rst_n_out
  );

  reg   [1:0]  reg_rst_sync;

  always @(posedge clk or negedge rst_n_in)
  begin
  if (~rst_n_in)
    reg_rst_sync <= 2'b00;
  else
    if (rst_request)
      reg_rst_sync <= 2'b00;
    else
      reg_rst_sync <= {reg_rst_sync[0], 1'b1};
  end

  assign     rst_n_out = reg_rst_sync[1];

endmodule
module meta_regs (
  dest_clk,
  dest_resetn,
  source_data,
  dest_data
  );

//  Simple metastability register

parameter INPUT_WIDTH      = 8;                 // Width of data bus
parameter INPUT_MAX        = INPUT_WIDTH - 1;   // Upper bound of data vector

  input                dest_clk;
  input                dest_resetn;
  input  [INPUT_MAX:0] source_data;
  output [INPUT_MAX:0] dest_data;

  // synchronization registers to avoid metastability issue
  wire [INPUT_MAX:0] dest_data;
  reg  [INPUT_MAX:0] dest_data_i1;
  reg  [INPUT_MAX:0] dest_data_i2;

  always @ (posedge dest_clk or negedge dest_resetn)
  begin
  if (!dest_resetn) begin
    dest_data_i1 <= {INPUT_WIDTH{1'b0}};
    dest_data_i2 <= {INPUT_WIDTH{1'b0}};
  end else begin
    dest_data_i1 <= source_data;
    dest_data_i2 <= dest_data_i1;
  end
  end

  assign dest_data = dest_data_i2;

endmodule
module ddr_out (
  datain_h,
  datain_l,
  outclock,
  dataout);

  input    datain_h;
  input    datain_l;
  input    outclock;
  output   dataout;

  wire  sub_wire0;
  wire  dataout = sub_wire0;

  altddio_out  u_altddio_out_component (
        .datain_h (datain_h),
        .datain_l (datain_l),
        .outclock (outclock),
        .dataout (sub_wire0),
        .aclr (1'b0),
        .aset (1'b0),
        .oe (1'b1),
        .oe_out (),
        .outclocken (1'b1),
        .sclr (1'b0),
        .sset (1'b0));
  defparam
    u_altddio_out_component.extend_oe_disable = "OFF",
    u_altddio_out_component.intended_device_family = "Cyclone V",
    u_altddio_out_component.invert_output = "OFF",
    u_altddio_out_component.lpm_hint = "UNUSED",
    u_altddio_out_component.lpm_type = "altddio_out",
    u_altddio_out_component.oe_reg = "UNREGISTERED",
    u_altddio_out_component.power_up_high = "OFF",
    u_altddio_out_component.width = 1;


endmodule
module SspIntGen (
                  TXMIS, 
                  RXMIS, 
                  RORMIS,
                  DataStp,
                  RTIMSync,

                  RORIC,
                  RTIC,
                  RORINTR,
                  RTINTR,
                  INTR
                 );

// Inputs
input  TXMIS;    // Tx FIFO Service request
input  RXMIS;    // Rx FIFO Service request
input  RORMIS;   // Rx FIFO Overrun interrupt
input  DataStp;  // Rx TimeOut interrupt input
input  RTIMSync; // Rx TimeOut Interrupt Mask Sync
input  RORIC;    // Rx FIFO Overrun Clear input
input  RTIC;     // Rx TimeOut Clear input

// Outputs
output RORINTR;  // Rx FIFO Overrun interrupt output
output RTINTR;   // RX TimeOut Masked Interrupt output
output INTR;     // Combined interrupt

// -----------------------------------------------------------------------------
//
//                               SspIntGen
//                               =========
//
// -----------------------------------------------------------------------------
//
// Overview
// ========
//
// The combined interrupt INTR is generated as an OR of the individual 
// interrupt sources RXMIS, TXMIS and RORINTR and RTINTR.
// 
// -----------------------------------------------------------------------------

// -----------------------------------------------------------------------------
// Wire declarations
// -----------------------------------------------------------------------------

// -----------------------------------------------------------------------------
// Register  declarations
// -----------------------------------------------------------------------------

// -----------------------------------------------------------------------------
//
// Main body of code
// =================
//
// -----------------------------------------------------------------------------

// ---------------------------------------------------------------------
// -- When the relevant interrupt clear signal is asserted, the
// -- asynchronous interrupt is cleared.  
// ---------------------------------------------------------------------

assign RTINTR  = DataStp & RTIMSync & ~RTIC;
assign RORINTR = RORMIS  & ~RORIC;

// -----------------------------------------------------------------------------
// OR the individual interrupts to generate INTR
// -----------------------------------------------------------------------------
assign INTR = RXMIS | TXMIS | RORINTR | RTINTR;

endmodule
module SspRevAnd (
// Inputs
                 TieOff1,
                 TieOff2,
// Outputs
                 Revision
                 );

// Inputs
input        TieOff1;  // AND gate input 1
input        TieOff2;  // AND gate input 2
// Outputs
output       Revision; // AND gate output

// ---------------------------------------------------------------------
//
//                              SspRevAnd
//                              =========
//
// ---------------------------------------------------------------------
//
// Overview
// ========
//   This module contains a single AND gate to be used as a
// place-holder cell to mark the Revision of the Ssp.
// The 2 input pins will be tied-off at the top level of the
// hierarchy. These "TieOffs" can be identified during layout
// and re-wired to "VDD" or "VSS" if needed.
//
// ---------------------------------------------------------------------


// ---------------------------------------------------------------------
// Register declarations
// ---------------------------------------------------------------------


// ---------------------------------------------------------------------
//
// Main body of code
// =================
//
// ---------------------------------------------------------------------



assign Revision = TieOff1 & TieOff2;

endmodule
module cxapbasyncbridge_cdc_corrupt_gry (
  clk, 
  resetn, 
  sync,
  d_async,
  q_async
  );

  parameter WIDTH = 1;
  
  // ------------------------------------------------------
  // port declaration
  // ------------------------------------------------------
  input               clk; 
  input               resetn; 
  input               sync;
  input  [WIDTH-1:0]  d_async;
  output [WIDTH-1:0]  q_async;

  // -------------------------------------------
  // reg/wire declarations
  // ------------------------------------------------------

`ifdef ARM_CDC_CHECK

  reg      [WIDTH-1:0]  d_latch;
  reg      [WIDTH-1:0]  out_async;
  reg      [WIDTH-1:0]  corrupt;
  wire     [WIDTH-1:0]  change_vector;
  wire                  change;

  integer            i;

  //Bypass when in sync mode
  assign q_async = (sync) ? d_async : out_async;

  //Latch to detect changes in d_async
  always @(d_async)
     d_latch <= d_async; 

  //Create change vector (single delta cycle)
  assign change_vector = (d_async ^ d_latch);

  //Create a change pulse (single delta cycle)
  assign change = |change_vector;
  
  //Corrupt bits 
  always @(posedge clk or posedge change)
    begin 
       if (change) begin
          corrupt <= change_vector;
       end else begin
          corrupt <= {WIDTH{1'b0}};
       end
    end

  always @(corrupt or d_async)
    for (i = 0; i < WIDTH; i=i+1) begin
       out_async[i] = corrupt[i] ? 1'bz : d_async[i];
    end   
  
`else

  assign q_async = d_async;

`endif
  
endmodule
module cxapbasyncbridge_cdc_comb_and (q, d_async, valid);

  parameter WIDTH = 4; // Width of the payload

  // ------------------------------------------------------
  // port declaration
  // ------------------------------------------------------
  output [WIDTH-1:0] q;
  input  [WIDTH-1:0] d_async;     // May be connected to an asynchronous input
  input              valid;

  assign  q = (valid) ? d_async : {WIDTH{1'b0}};

`ifdef ARM_CDC_CHECK

  integer   i;

  // Use an assertion if assertions are enabled.
  wire [WIDTH-1:0]  q_d;
  reg               z_detect;

  initial
    z_detect = 1'b0;

  // Create a delayed signal to ensure that any error fires at the correct
  // time
  assign #1 q_d = q;

  // Stop the simulation if any bits are Z when mux is enabled
  always @(q_d)
    if (valid)
      for (i = 0; i <= WIDTH; i = i + 1)
        if (d_async[i] === 1'bz)
          begin
            z_detect <= 1'b1;
          end

  always @(posedge z_detect)
     begin
          $display("FATAL : Unsafe operation detected across CDC boundary");
          $stop;
     end

`endif

endmodule
module cxapbasyncbridge ( 
// Slave Interface 
//Clock and reset signals 
input pclkens, 
input pclks, 
input presetsn, 
//APB3 Bus 
input [31:0] paddrs, 
input [31:0] pwdatas, 
input pwrites, 
input penables, 
input psels, 
output [31:0] prdatas, 
output pslverrs, 
output preadys, 
// Master Interface 
//Clock and reset signals 
input pclkenm, 
input pclkm, 
input presetmn, 
//APB3 Bus 
output [31:0] paddrm, 
output [31:0] pwdatam, 
output pwritem, 
output penablem, 
output pselm, 
input [31:0] prdatam, 
input pslverrm, 
input preadym 
); 

//---------------------------------------------------------------------------- 
// Wire Declaration 
//---------------------------------------------------------------------------- 

wire apb_req_async; 
wire apb_ack_async; 
wire [64:0] apb_fwd_data_async; 
wire [32:0] apb_rev_data_async; 

//---------------------------------------------------------------------------- 
// Start of code 
//---------------------------------------------------------------------------- 

cxapbasyncbridge_master_domain u_mstr ( 
//APB3 Bus 
.paddrm (paddrm), 
.pwdatam (pwdatam), 
.pwritem (pwritem), 
.penablem (penablem), 
.pselm (pselm), 
.prdatam (prdatam), 
.pslverrm (pslverrm), 
.preadym (preadym), 
//Inter-domain APB bus 
.apbs_req_async (apb_req_async), 
.apbs_ack_async (apb_ack_async), 
.apbs_fwd_data_async (apb_fwd_data_async), 
.apbs_rev_data_async (apb_rev_data_async), 
//Clock and reset signals 
.pclkenm (pclkenm), 
.pclkm (pclkm), 
.presetmn (presetmn) 
); 

cxapbasyncbridge_slave_domain u_slave ( 
//APB3 Bus 
.paddrs (paddrs), 
.pwdatas (pwdatas), 
.pwrites (pwrites), 
.penables (penables), 
.psels (psels), 
.prdatas (prdatas), 
.pslverrs (pslverrs), 
.preadys (preadys), 
//Inter-domain APB bus 
.apbm_req_async (apb_req_async), 
.apbm_ack_async (apb_ack_async), 
.apbm_fwd_data_async (apb_fwd_data_async), 
.apbm_rev_data_async (apb_rev_data_async), 
//Clock and reset signals 
.pclkens (pclkens), 
.pclks (pclks), 
.presetsn (presetsn) 
); 
endmodule
module cxapbasyncbridge_cdc_launch_gry (
  clk, 
  resetn, 
  enable,
  in_cdc,
  out_async
  );

  parameter WIDTH = 1;
  
  // ------------------------------------------------------
  // port declaration
  // ------------------------------------------------------
  input               clk; 
  input               resetn; 
  input               enable;
  input  [WIDTH-1:0]  in_cdc;
  output [WIDTH-1:0]  out_async;

  // -------------------------------------------
  // reg/wire declarations
  // ------------------------------------------------------

  reg   [WIDTH-1:0]  out_async;

  always@(posedge clk or negedge resetn)
     begin : p_cdc_launch_seq
        if(!resetn)
           out_async <= {WIDTH{1'b0}};
        else if (enable)
           out_async <= in_cdc;
     end

`ifdef ARM_ASSERT_ON

  //----------------------------------------------------------------------------
  // OVL_ASSERT: Check that the value is correctly gray encoded
  //----------------------------------------------------------------------------
  //----------------------------------------------------------------------------
  // OVL_ASSERT_RTL
  ovl_code_distance
    #(0, 1, 1, WIDTH, 0, "Clock domain crossing signal is not correctly gray encoded")
      ovl_gray_enc_check
        (.clock        (clk),
         .reset      (resetn),
         .enable     (1'b1),
         .test_expr1 (in_cdc),
         .test_expr2 (out_async),
         .fire       ());
  // OVL_ASSERT_END

`endif
  
endmodule
module cxapbasyncbridge_cdc_capt_sync (clk, resetn, d_async, sync_en, q);

  parameter WIDTH = 4;

  // ------------------------------------------------------
  // port declaration
  // ------------------------------------------------------
  input                clk;
  input                resetn;
  input [WIDTH-1:0]    d_async;     // May be connected to an asynchronous input
  input                sync_en;
  output [WIDTH-1:0]   q;


  // ------------------------------------------------------
  // reg/wire declarations
  // ------------------------------------------------------
  wire [WIDTH-1:0]     d_noz;
  reg  [WIDTH-1:0]     d_sync1;
  reg  [WIDTH-1:0]     q;

`ifdef ARM_CDC_CHECK

  cxapbasyncbridge_cdc_random #(WIDTH) u_cdc_random_z(
                             .din (d_async),
                             .dout (d_noz)
                             );

`else

  assign d_noz = d_async;

`endif

  always @(posedge clk or negedge resetn)
    if (!resetn)
      begin
        d_sync1 <= {WIDTH{1'b0}};
        q <= {WIDTH{1'b0}};
      end
    else if(sync_en)
      begin
        d_sync1 <= d_noz;
        q <= d_sync1;
      end
      
endmodule
module cxapbasyncbridge_cdc_launch_data (
  clk, 
  resetn, 
  enable,
  in_cdc,
  out_async
  );

  parameter WIDTH = 1;
  
  // ------------------------------------------------------
  // port declaration
  // ------------------------------------------------------
  input               clk; 
  input               resetn; 
  input               enable;
  input  [WIDTH-1:0]  in_cdc;
  output [WIDTH-1:0]  out_async;

  // -------------------------------------------
  // reg/wire declarations
  // ------------------------------------------------------

  reg   [WIDTH-1:0]  out_async;

  always@(posedge clk or negedge resetn)
     begin : p_cdc_launch_seq
        if(~resetn)
           out_async <= {WIDTH{1'b0}};
        else if (enable)
           out_async <= in_cdc;
     end

endmodule
module cxapbasyncbridge_cdc_random
  ( din, dout);

  // ------------------------------------------------------
  // parameter declaration
  // ------------------------------------------------------

  parameter WIDTH = 4;
  parameter HIER_LEN = 100;

  // ------------------------------------------------------
  // port declaration
  // ------------------------------------------------------
  input [WIDTH-1:0]     din;
  output [WIDTH-1:0]    dout;

`ifdef ARM_CDC_CHECK

  // ------------------------------------------------------
  // reg/wire declarations
  // ------------------------------------------------------
  reg [WIDTH-1:0]       dout;

  integer               seed;
  integer               i;
  integer               j;
  integer               seed_char;
  reg [0:(8*HIER_LEN)]  seed_string;
  integer               top_level_seed;
  
  reg [31:0]            lfsr;
  wire                  lfsr_feedback;
                           
  // generate random seed from the hierarchical filename
  initial 
    begin
      $swrite(seed_string,"%m");
    
      //convert string into an integer for the seed
      //by converting one ascii byte at a time and adding it
      //to the seed
      
      seed = 0;
      for (i = 0; i < (8*HIER_LEN); i = i + 8) 
        begin
          seed_char = (seed_string[i+:8]);
          seed = seed + seed_char;     
        end
      
      
      if ($value$plusargs("seed=%d",top_level_seed)) seed = seed+top_level_seed;
      
      $display ("%s using seed %h",seed_string, seed);
      
      lfsr <= seed;
      
    end 
  
  assign lfsr_feedback = lfsr[2] ^ lfsr[30];

  always @(din)
    for (j = 0; j < WIDTH; j = j + 1) begin

        if ((din[j] ^ din[j]) !== 1'b0)
          begin
            dout[j] = lfsr[0];
            lfsr = {lfsr[30:0],lfsr_feedback};
          end
        else
          dout[j] = din[j];
    end      
  
`else
    assign dout = din;
`endif

endmodule
module cxapbasyncbridge_cdc_corrupt (
  clk, 
  sync,
  d,
  q
  );

  parameter WIDTH = 1;
  
  // ------------------------------------------------------
  // port declaration
  // ------------------------------------------------------
  input               clk; 
  input               sync;
  input  [WIDTH-1:0]  d;
  output [WIDTH-1:0]  q;

  // -------------------------------------------
  // reg/wire declarations
  // ------------------------------------------------------

`ifdef ARM_CDC_CHECK

  wire                  change;
  reg      [WIDTH-1:0]  d_latch;
  wire     [WIDTH-1:0]  out;
  reg      p1;
  reg      p2;


  //Set the appropriate output based on sync
  assign q = (sync) ? d : out;

  //Latch to detect change on incoming data 
  always @(d)
     d_latch <= d;

  //Create delta cycle pulse to reset pipeline on change
  assign change = (d !== d_latch);   

  //Pipeline is reset to 1s on any change in data
  //Data should be corrupted until the pipeline is clear
  always @(posedge clk or posedge change)
    begin 
       if (change) begin
          p1 <= 1'b1;
          p2 <= 1'b1;
       end else begin
          p1 <= 1'b0;
          p2 <= p1;
       end
    end

  //Corrupt data while there is something in the pipeline 
  assign out = (p2) ? {WIDTH{1'bz}} : d;

`else

  assign q = d;

`endif  
endmodule
module arduino_shield (
  input  wire        UART,
  input  wire        I2C,
  input  wire        SPI,
  inout  wire [15:0] SH_IO,
  output wire        I2C_OE
  );

    wire [15:0] gpio;

    wire uart_rx;
    wire uart_tx;

    wire i2c_scl;
    wire i2c_sda;
    wire i2c_scl_int;
    wire i2c_sda_int;
    wire i2c_oe_int;

    wire spi_sck;
    wire spi_ss;
    wire spi_mosi;
    wire spi_miso;

    wire sh_io_int14;
    // Intentionally unused signals
    wire   unused;


//---------------------UART / GPIO Mux---------------------------------------------
    assign SH_IO[0] = UART ? uart_rx  : gpio[0];
    assign uart_tx  = UART ? SH_IO[1] : 1'bz;


//---------------------------------------------------------------------------------

//---------------------I2C / GPIO Mux----------------------------------------------
    pullup (i2c_scl); // pullup scl line
    pullup (i2c_sda); // pullup sda line

    assign i2c_scl_int = I2C         ? SH_IO[15] : 1'bz;
    assign i2c_scl     = i2c_scl_int ? 1'bz      : 1'b0;

    assign sh_io_int14 = I2C_OE                     ? i2c_sda     : 1'bz;   // I2C_SDA <=> SH_IO[14]
    assign SH_IO[14]   = I2C                        ? sh_io_int14 : gpio[14];
    assign i2c_sda_int = (~SH_IO[14] & ~i2c_oe_int) ? 1'b0        : 1'bz;
    assign i2c_sda     = I2C                        ? i2c_sda_int : 1'bz;

    assign I2C_OE = I2C ? i2c_oe_int : 1'bz;

  I2C_SRAM u_i2c_sram (
   .power_cycle (1'b1),
   .A0          (1'b0),
   .A1          (1'b0),
   .A2          (1'b0),
   .WP          (1'b0),
   .SDA         (i2c_sda),
   .SCL         (i2c_scl),
   .SDA_OE      (i2c_oe_int),
   .HSB_bar     (),
   .INT         ()
  );

//---------------------------------------------------------------------------------

//---------------------SPI / GPIO Mux----------------------------------------------

    assign spi_sck   = SPI ? SH_IO[13] : 1'bz;
    assign spi_ss    = SPI ? SH_IO[10] : 1'bz;
    assign spi_mosi  = SPI ? SH_IO[11] : 1'bz;
    assign SH_IO[12] = SPI ? spi_miso  : gpio[12];
    assign gpio[13]  = SPI ? 1'bz      : SH_IO[13];
    assign gpio[10]  = SPI ? 1'bz      : SH_IO[10];
    assign SH_IO[11] = SPI ? 1'bz      : gpio[11];

   SPI_EEPROM u_spi_eeprom (
     .SI          (spi_mosi),
     .SCK         (spi_sck),
     .CS_N        (spi_ss),
     .WP_N        (1'b1),
     .HOLD_N      (1'b1),
     .RESET       (1'b0),
     .SO          (spi_miso)
  );

//---------------------------------------------------------------------------------

  assign unused = |{gpio[10],
                    gpio[13],
                    uart_tx
                    };


endmodule
module tb_arduino_shield (
  inout wire [51:0] EXP,
  input wire        SPI0,
  input wire        SPI1,
  input wire        I2C0,
  input wire        I2C1,
  input wire        UART0,
  input wire        UART1
  );

  wire [15:0] SH0_IO;
  wire [15:0] SH1_IO;
  wire I2C_OE_0;
  wire I2C_OE_1;


  arduino_adaptor
  u_arduino_adaptor
  (
  .SPI0     (SPI0),
  .SPI1     (SPI1),
  .I2C0     (I2C0),
  .I2C1     (I2C1),
  .EXP      (EXP),
  .SH0_IO   (SH0_IO),
  .SH1_IO   (SH1_IO),
  .I2C_OE_0 (I2C_OE_0),
  .I2C_OE_1 (I2C_OE_1)
  );

  arduino_shield
  u_arduino_shield0
  (
  .UART   (UART0),
  .I2C    (I2C1),
  .SPI    (SPI0),
  .SH_IO  (SH0_IO),
  .I2C_OE (I2C_OE_0)
  );

  arduino_shield

  u_arduino_shield1
  (
  .UART   (UART1),
  .I2C    (I2C1),
  .SPI    (SPI1),
  .SH_IO  (SH1_IO),
  .I2C_OE (I2C_OE_1)
  );

endmodule
module GS8160Z36DT  #(
        parameter SPEED = 300,
                              A_bits = 19
)
(A, CK, nBa, nBb, nBc, nBd, nW, nE1, E2, nE3, nG, pADV,
      nCKE, DQa, DQb, DQc, DQd, ZZ, nFT, nLBO);


  parameter  A_size     = 19,    // +16M -4 bytes in parallel
      DQ_size   = 9,
    bank_size   = 2**A_bits;

  input  [A_size-1:0]    A;     // address
  input        CK;    // clock
  input        nBa;    // bank A write enable
  input        nBb;    // bank B write enable
  input        nBc;    // bank C write enable
  input        nBd;    // bank D write enable
  input        nW;     // byte write enable
  input        nE1;    // chip enable 1
  input        E2;    // chip enable 2
  input        nE3;    // chip enable 3
  input        nG;    // output enable
  input        pADV;    // Advance not / load
  input        nCKE;
  inout  [DQ_size-1:0]    DQa;    // byte A data
  inout  [DQ_size-1:0]    DQb;    // byte B data
  inout  [DQ_size-1:0]    DQc;    // byte C data
  inout  [DQ_size-1:0]    DQd;    // byte D data
  input        ZZ;      // power down
  input        nFT;    // Pipeline / Flow through
  input        nLBO;    // Linear Burst Order not
  wire        TMS;    // Scan Test Mode Select
  wire        TDI;    // Scan Test Data In
  wire        TDO;    // Scan Test Data Out
  wire        TCK;    // Scan Test Clock

  wire                      nBe = 1,
          nBf = 1,
          nBg = 1,
          nBh = 1;
  wire    [8:0]             DQe,
          DQf,
          DQg,
          DQh;

   parameter       tKQ_pipe  = (SPEED==400 | SPEED==375 | SPEED==333 | SPEED==250) ? 2.5 : SPEED==200 ? 3.0 : 3.8;
   parameter       tKQ_flow  = SPEED==400 ? 4.0 : SPEED==375 ? 4.2 : SPEED==333 ? 4.5: SPEED==250 ? 5.5 : SPEED==200 ? 6.5 : 7.5;
   parameter       tKQX_pipe = 1.5;
   parameter       tKQX_flow = 2.0;

   assign       tKQ  = nFT ? tKQ_pipe : tKQ_flow;
   assign       tKQX = nFT ? tKQX_pipe : tKQX_flow;
       
`include  "core.v"

endmodule
module cmsdk_mcu_stclkctrl #(
  // Ratio between FCLK and SysTick reference clock
  parameter DIV_RATIO = 18'd01000,

  // Divide by half for each phase
  parameter DIVIDER_RELOAD = (DIV_RATIO>>1)-1
 )
 (
  input  wire        FCLK,      // Free running clock
  input  wire        SYSRESETn, // System reset

  output wire        STCLKEN,   // SysTick clock
  output wire [25:0] STCALIB    // SysTick calibration
  );

  reg     [17:0] reg_clk_divider;
  reg            reg_stclken;

  assign STCALIB[25] = 1'b0; // NoRef - reference clock provided
  assign STCALIB[24] = 1'b1; // Skew - reference info not available
  assign STCALIB[23:0] = {24{1'b0}}; // 10 ms value  set to 0, indicate this value is not used

  // Divider
  wire [17:0] reg_clk_div_min1 = reg_clk_divider -1;
  always @(posedge FCLK or negedge SYSRESETn)
  begin
  if (~SYSRESETn)
    reg_clk_divider <= {18{1'b0}};
  else
    begin
    if (|reg_clk_divider)
      reg_clk_divider <= reg_clk_div_min1[17:0];
    else
      reg_clk_divider <= DIVIDER_RELOAD[17:0];
    end
  end

  // Toggle register
  always @(posedge FCLK or negedge SYSRESETn)
  begin
  if (~SYSRESETn)
    reg_stclken <= 1'b0;
  else
    begin
    if (reg_clk_divider==18'h00000)
      reg_stclken <= ~reg_stclken;
    end
  end

  // Connect to top level
  assign STCLKEN = reg_stclken;

endmodule
module ip_pll  // al_ip/ip_pll.v(26)
  (
  refclk,
  reset,
  clk0_out,
  clk1_out,
  clk2_out,
  clk3_out,
  clk4_out
  );

  input refclk;  // al_ip/ip_pll.v(34)
  input reset;  // al_ip/ip_pll.v(35)
  output clk0_out;  // al_ip/ip_pll.v(36)
  output clk1_out;  // al_ip/ip_pll.v(37)
  output clk2_out;  // al_ip/ip_pll.v(38)
  output clk3_out;  // al_ip/ip_pll.v(39)
  output clk4_out;  // al_ip/ip_pll.v(40)

  wire clk0_buf;  // al_ip/ip_pll.v(42)

  EG_PHY_GCLK bufg_feedback (
    .clki(clk0_buf),
    .clko(clk0_out));  // al_ip/ip_pll.v(44)
  EG_PHY_CONFIG #(
    .DONE_PERSISTN("ENABLE"),
    .INIT_PERSISTN("ENABLE"),
    .JTAG_PERSISTN("DISABLE"),
    .PROGRAMN_PERSISTN("DISABLE"))
    config_inst ();
  EG_PHY_PLL #(
    .CLKC0_CPHASE(4),
    .CLKC0_DIV(5),
    .CLKC0_DIV2_ENABLE("DISABLE"),
    .CLKC0_ENABLE("ENABLE"),
    .CLKC0_FPHASE(0),
    .CLKC1_CPHASE(5),
    .CLKC1_DIV(5),
    .CLKC1_DIV2_ENABLE("DISABLE"),
    .CLKC1_ENABLE("ENABLE"),
    .CLKC1_FPHASE(2),
    .CLKC2_CPHASE(11),
    .CLKC2_DIV(12),
    .CLKC2_DIV2_ENABLE("DISABLE"),
    .CLKC2_ENABLE("ENABLE"),
    .CLKC2_FPHASE(0),
    .CLKC3_CPHASE(19),
    .CLKC3_DIV(20),
    .CLKC3_DIV2_ENABLE("DISABLE"),
    .CLKC3_ENABLE("ENABLE"),
    .CLKC3_FPHASE(0),
    .CLKC4_CPHASE(119),
    .CLKC4_DIV(120),
    .CLKC4_DIV2_ENABLE("DISABLE"),
    .CLKC4_ENABLE("ENABLE"),
    .CLKC4_FPHASE(0),
    .DERIVE_PLL_CLOCKS("DISABLE"),
    .DPHASE_SOURCE("DISABLE"),
    .DYNCFG("DISABLE"),
    .FBCLK_DIV(4),
    .FEEDBK_MODE("NORMAL"),
    .FEEDBK_PATH("CLKC0_EXT"),
    .FIN("24.000"),
    .FREQ_LOCK_ACCURACY(2),
    .GEN_BASIC_CLOCK("DISABLE"),
    .GMC_GAIN(2),
    .GMC_TEST(14),
    .ICP_CURRENT(9),
    .IF_ESCLKSTSW("DISABLE"),
    .INTFB_WAKE("DISABLE"),
    .KVCO(2),
    .LPF_CAPACITOR(1),
    .LPF_RESISTOR(8),
    .NORESET("DISABLE"),
    .ODIV_MUXC0("DIV"),
    .ODIV_MUXC1("DIV"),
    .ODIV_MUXC2("DIV"),
    .ODIV_MUXC3("DIV"),
    .ODIV_MUXC4("DIV"),
    .PLLC2RST_ENA("DISABLE"),
    .PLLC34RST_ENA("DISABLE"),
    .PLLMRST_ENA("DISABLE"),
    .PLLRST_ENA("ENABLE"),
    .PLL_LOCK_MODE(0),
    .PREDIV_MUXC0("VCO"),
    .PREDIV_MUXC1("VCO"),
    .PREDIV_MUXC2("VCO"),
    .PREDIV_MUXC3("VCO"),
    .PREDIV_MUXC4("VCO"),
    .REFCLK_DIV(1),
    .REFCLK_SEL("INTERNAL"),
    .STDBY_ENABLE("DISABLE"),
    .STDBY_VCO_ENA("DISABLE"),
    .SYNC_ENABLE("DISABLE"),
    .VCO_NORESET("DISABLE"))
    pll_inst (
    .daddr(6'b000000),
    .dclk(1'b0),
    .dcs(1'b0),
    .di(8'b00000000),
    .dwe(1'b0),
    .fbclk(clk0_out),
    .psclk(1'b0),
    .psclksel(3'b000),
    .psdown(1'b0),
    .psstep(1'b0),
    .refclk(refclk),
    .reset(reset),
    .stdby(1'b0),
    .clkc({clk4_out,clk3_out,clk2_out,clk1_out,clk0_buf}));  // al_ip/ip_pll.v(83)

endmodule
module camera_reader
(
	input 	wire 		clk,
	input 	wire 		reset_n,
	
	output 	wire 		csi_xclk,
	
	input 	wire 		csi_pclk,
	input 	wire [7:0] 	csi_data,
	input 	wire 		csi_vsync,
	input 	wire 		csi_hsync,
	
	output 	reg  [15:0] data_out = 0,
	output 	wire 		wrreq,
	output 	wire 		wrclk,
	output 	reg  [15:0]	wraddr
);

reg [19:0] pixel_counter = 0;
assign csi_xclk  = (reset_n == 1) ? clk : 0;
reg vsync_passed = 0;
reg write_pixel  = 0;
reg [7:0] 	subpixel;
reg [15:0] 	current_pixel;
reg wrclk1 = 0;

always@(posedge csi_pclk)
begin
	wrclk1 <= ~wrclk1;
end

always@(negedge wrclk1)
begin
	if(csi_hsync == 1)
		write_pixel <= 1;
	else
		write_pixel <= 0;
end

always@(posedge wrreq )
begin
	data_out <= current_pixel;
end

always@(posedge csi_pclk or negedge reset_n)
begin
	if(reset_n == 0)
	begin
		pixel_counter <= 0;
		vsync_passed <= 0;
	end
	else
	begin
		if(csi_vsync == 0)
		begin
			pixel_counter <= 0;
			vsync_passed <= 1;
			wraddr <= 0;
		end
		else
			if(csi_hsync == 1 && vsync_passed == 1)
			begin
				if(pixel_counter[0] == 0)
				begin
					pixel_counter <= pixel_counter + 1;
					subpixel <= csi_data;
				end
				else
				begin
					current_pixel <= { subpixel, csi_data };
					pixel_counter <= pixel_counter + 1;
					wraddr <= wraddr + 1;
				end
			end
			else
			begin
				if(write_pixel == 1)
					pixel_counter <= pixel_counter + 1;
				else
					pixel_counter <= 0;
			end
	end
end

assign wrreq = ((write_pixel == 1) && (pixel_counter>1)) ? wrclk1 : 0;
assign wrclk = ~csi_pclk;

endmodule
module Driver
#(
	parameter H_SYNC = 128	, 		// 行同步信号时间
	parameter H_BACK = 88	, 		// 行消隐后肩时间
	parameter H_DISP = 800	, 		// 行数据有效时间
	parameter H_FRONT = 40	, 		// 行消隐前肩时间
	parameter H_TOTAL = 1056, 		// 行扫描总时间
			
	parameter V_SYNC = 4	, 		// 列同步信号时间
	parameter V_BACK = 23 	, 		// 列消隐后肩时间
	parameter V_DISP = 600	, 		// 列数据有效时间
	parameter V_FRONT = 1	, 		// 列消隐前肩时间
	parameter V_TOTAL = 628  		// 列扫描总时间

//	parameter H_SYNC = 136	, 		// 行同步信号时间
//	parameter H_BACK = 160	, 		// 行消隐后肩时间
//	parameter H_DISP = 1024	, 		// 行数据有效时间
//	parameter H_FRONT = 24	, 		// 行消隐前肩时间
//	parameter H_TOTAL = 1344, 		// 行扫描总时间
			
//	parameter V_SYNC = 6	, 		// 列同步信号时间
//	parameter V_BACK = 29 	, 		// 列消隐后肩时间
//	parameter V_DISP = 768	, 		// 列数据有效时间
//	parameter V_FRONT = 3	, 		// 列消隐前肩时间
//	parameter V_TOTAL = 806  		// 列扫描总时间
)
(
	input  wire			clk,			//VGA clock
	input  wire			rst_n,     		//sync reset
	input  wire	[23:0]	lcd_data,		//lcd data
	
	//lcd interface
	output wire			lcd_dclk,   	//lcd pixel clock
	output wire			lcd_hs,	    	//lcd horizontal sync
	output wire			lcd_vs,	    	//lcd vertical sync
	output wire			lcd_en,			//lcd display enable
	output wire	[23:0]	lcd_rgb,		//lcd display data

	//user interface
	output wire	[11:0]	lcd_xpos,		//lcd horizontal coordinate
	output wire	[11:0]	lcd_ypos		//lcd vertical coordinate
);	
 
localparam	H_AHEAD = 	12'd1;

reg [11:0] hcnt; 
reg [11:0] vcnt;
wire lcd_request;

/*******************************************
		SYNC--BACK--DISP--FRONT
*******************************************/ 
//h_sync counter & generator
always @ (posedge clk or negedge rst_n)
begin
	if (!rst_n)
		hcnt <= 12'd0;
	else
	begin
        if(hcnt < H_TOTAL - 1'b1)		//line over			
            hcnt <= hcnt + 1'b1;
        else
            hcnt <= 12'd0;
	end
end 

assign	lcd_hs = (hcnt <= H_SYNC - 1'b1) ? 1'b0 : 1'b1; // line over flag

//v_sync counter & generator
always@(posedge clk or negedge rst_n)
begin
	if (!rst_n)
		vcnt <= 12'b0;
	else if(hcnt == H_TOTAL - 1'b1)	//line over
		begin
		if(vcnt == V_TOTAL - 1'b1)		//frame over
			vcnt <= 12'd0;
		else
			vcnt <= vcnt + 1'b1;
		end
end

assign	lcd_vs = (vcnt <= V_SYNC - 1'b1) ? 1'b0 : 1'b1; // frame over flag

// LCD clock
assign	lcd_dclk = clk;

// Control Display
assign	lcd_en		=	(hcnt >= H_SYNC + H_BACK  && hcnt < H_SYNC + H_BACK + H_DISP) &&
						(vcnt >= V_SYNC + V_BACK  && vcnt < V_SYNC + V_BACK + V_DISP) 
						? 1'b1 : 1'b0;                   // Display Enable Signal
						
assign	lcd_rgb 	= 	lcd_en ? lcd_data : 24'h000000;	

//ahead x clock
assign	lcd_request	=	(hcnt >= H_SYNC + H_BACK - H_AHEAD && hcnt < H_SYNC + H_BACK + H_DISP - H_AHEAD) &&
						(vcnt >= V_SYNC + V_BACK && vcnt < V_SYNC + V_BACK + V_DISP) 
						? 1'b1 : 1'b0;
//lcd xpos & ypos
assign	lcd_xpos	= 	lcd_request ? (hcnt - (H_SYNC + H_BACK - H_AHEAD)) : 12'd0;
assign	lcd_ypos	= 	lcd_request ? (vcnt - (V_SYNC + V_BACK)) : 12'd0;

endmodule
module VGA_CTRL (
	Clk40M,		//系统输入时钟40MHZ
	Rst_n,		//复位输入，低电平复位
	data_in,	//待显示数据
	hcount,		//TFT行扫描计数器
	vcount,		//TFT场扫描计数器
	VGA_RGB,	//TFT数据输出
	VGA_HS,		//TFT行同步信号
	VGA_VS,		//TFT场同步信号
	VGA_BLANK,
	VGA_VCLK,
	VGA_DE
	//Error
);
	

`define RED      16'hf800
`define GREEN    16'h07e0
`define BLUE     16'h001f
`define WHITE    16'hffff
`define BLACK    16'h0000
`define YELLOW   16'hffe0
`define CYAN     16'hf81f
`define ROYAL    16'h07ff
`define PINK     16'hfe19

	
	//----------------模块输入端口----------------
	input  Clk40M;			//系统输入时钟40MHZ
	input  Rst_n;
	input  [15:0]data_in;	//待显示数据

	//----------------模块输出端口----------------
	output [11:0]hcount;
	output [11:0]vcount;
	output [15:0]VGA_RGB;	//TFT数据输出
	output VGA_HS;			//TFT行同步信号
	output VGA_VS;			//TFT场同步信号
	output VGA_BLANK;
	output VGA_DE;
	output VGA_VCLK;
	//output reg Error;

	//----------------内部寄存器定义----------------
	reg [15:0] data_buff;		//缓冲
	reg [11:0] hcount_r;		//TFT行扫描计数器
	reg [11:0] vcount_r;		//TFT场扫描计数器
	//----------------内部连线定义----------------
	wire hcount_ov;		//行扫描一行结束时为1
	wire vcount_ov;		//列扫描一行结束时为1
	wire VGA_DE;		//有效显示区标定

	//VGA行、场扫描时序参数表
	parameter	VGA_HS_end = 12'd128,
				hdat_begin = 12'd216,
				hdat_end = 12'd1016,
				hpixel_end = 12'd1056,
				VGA_VS_end = 12'd4,
				vdat_begin = 12'd27,
				vdat_end = 12'd627,
				vline_end = 12'd628;

	assign hcount = VGA_DE ? ( hcount_r - hdat_begin ) : 12'd0;
	assign vcount = VGA_DE ? ( vcount_r - vdat_begin ) : 12'd0;
	
	assign VGA_BLANK = ~VGA_DE;
	assign VGA_VCLK = Clk40M;
	

	//**********************VGA驱动部分**********************
	
	//缓冲
	always @( posedge Clk40M /*or negedge Rst_n*/ ) begin
		if ( ~Rst_n ) begin
			data_buff <= 16'b0;
		end else begin
			data_buff <= data_in;
		end
	end
	
	//行扫描
	always @( posedge Clk40M /*or negedge Rst_n*/ ) begin
		if ( ~Rst_n ) begin
			hcount_r <= 12'd0;
		end else begin
			if ( hcount_r < hpixel_end - 1 ) begin
				hcount_r <= hcount_r + 1'b1;
			end else begin
				hcount_r <= 12'd0;
			end
		end
	end

	assign hcount_ov = ( hcount_r == hpixel_end - 1 );

	//场扫描
	always @( posedge Clk40M or negedge Rst_n ) begin
		if ( ~Rst_n ) begin
			vcount_r <= 12'd0;
		end else begin
			if ( hcount_ov ) begin
				if ( vcount_r < vline_end - 1 ) begin
					vcount_r <= vcount_r + 1'b1;
				end else begin
					vcount_r <= 12'd0;
				end
			end else begin
				vcount_r <= vcount_r;
			end
		end
	end
		
	assign 	vcount_ov = ( vcount_r == vline_end - 1 );

	//数据、同步信号输出
	assign VGA_DE = ( ( hcount_r >= hdat_begin ) && ( hcount_r < hdat_end ) )
					&& ( ( vcount_r >= vdat_begin ) && ( vcount_r < vdat_end ) );
					
	assign VGA_HS = ( hcount_r >= VGA_HS_end ) ? 1'b1 : 1'b0;
	assign VGA_VS = ( vcount_r >= VGA_VS_end ) ? 1'b1 : 1'b0;
	assign VGA_RGB = VGA_DE ? data_buff : 16'b0;



endmodule
module Sdram_WR_FIFO (
	reset,
	aclr,
	data,
	rdclk,
//	clk,
	rdreq,
	wrclk,
	wrreq,
	q,
	rdempty,
	rdusedw,
	wrfull,
	wrusedw);
	
	input     reset;
	input	  aclr;
	input	[15:0]  data;
//    input 	 clk;
	input	  rdclk;
	input	  rdreq;
	input	  wrclk;
	input	  wrreq;
	output	[15:0]  q;
	output	  rdempty;
	output	[15:0]  rdusedw;
	output	  wrfull;
	output	[15:0]  wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0	  aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire [15:0] sub_wire0;
	wire  sub_wire1;
	wire [15:0] sub_wire2;
	wire  sub_wire3;
	wire [15:0] sub_wire4;
	wire [15:0] q = sub_wire0[15:0];
	wire  rdempty = sub_wire1;
	wire [15:0] rdusedw = sub_wire2[15:0];
	wire  wrfull = sub_wire3;
	wire [15:0] wrusedw = sub_wire4[15:0];

	softfifo	dcfifo_component (
				.rst(reset),
				.clkw (wrclk),
//				.clk(clk),
				.di (data),
				.we (wrreq),
				.full_flag (sub_wire3),
				.wrusedw (sub_wire4),
				.clkr (rdclk),
				.dout (sub_wire0),
				.re (rdreq),
				.empty_flag (sub_wire1),
				.rdusedw (sub_wire2));
	/*
	defparam
		dcfifo_component.intended_device_family = "Cyclone IV E",
		dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
		dcfifo_component.lpm_numwords = 512,
		dcfifo_component.lpm_showahead = "OFF",
		dcfifo_component.lpm_type = "dcfifo",
		dcfifo_component.lpm_width = 16,
		dcfifo_component.lpm_widthu = 9,
		dcfifo_component.overflow_checking = "ON",
		dcfifo_component.rdsync_delaypipe = 4,
		dcfifo_component.read_aclr_synch = "OFF",
		dcfifo_component.underflow_checking = "ON",
		dcfifo_component.use_eab = "ON",
		dcfifo_component.write_aclr_synch = "OFF",
		dcfifo_component.wrsync_delaypipe = 4;
	*/

endmodule
module pll1  // al_ip/pll1.v(23)
  (
  refclk,
  clk0_out,
  clk1_out
  );

  input refclk;  // al_ip/pll1.v(27)
  output clk0_out;  // al_ip/pll1.v(28)
  output clk1_out;  // al_ip/pll1.v(29)

  wire clk0_buf;  // al_ip/pll1.v(31)

  EG_PHY_GCLK bufg_feedback (
    .clki(clk0_buf),
    .clko(clk0_out));  // al_ip/pll1.v(33)
  EG_PHY_CONFIG #(
    .DONE_PERSISTN("ENABLE"),
    .INIT_PERSISTN("ENABLE"),
    .JTAG_PERSISTN("DISABLE"),
    .PROGRAMN_PERSISTN("DISABLE"))
    config_inst ();
  EG_PHY_PLL #(
    .CLKC0_CPHASE(4),
    .CLKC0_DIV(5),
    .CLKC0_DIV2_ENABLE("DISABLE"),
    .CLKC0_ENABLE("ENABLE"),
    .CLKC0_FPHASE(0),
    .CLKC1_CPHASE(5),
    .CLKC1_DIV(5),
    .CLKC1_DIV2_ENABLE("DISABLE"),
    .CLKC1_ENABLE("ENABLE"),
    .CLKC1_FPHASE(2),
    .CLKC2_CPHASE(1),
    .CLKC2_DIV(1),
    .CLKC2_DIV2_ENABLE("DISABLE"),
    .CLKC2_ENABLE("DISABLE"),
    .CLKC2_FPHASE(0),
    .CLKC3_CPHASE(1),
    .CLKC3_DIV(1),
    .CLKC3_DIV2_ENABLE("DISABLE"),
    .CLKC3_ENABLE("DISABLE"),
    .CLKC3_FPHASE(0),
    .CLKC4_CPHASE(1),
    .CLKC4_DIV(1),
    .CLKC4_DIV2_ENABLE("DISABLE"),
    .CLKC4_ENABLE("DISABLE"),
    .CLKC4_FPHASE(0),
    .DERIVE_PLL_CLOCKS("DISABLE"),
    .DPHASE_SOURCE("DISABLE"),
    .DYNCFG("DISABLE"),
    .FBCLK_DIV(8),
    .FEEDBK_MODE("NORMAL"),
    .FEEDBK_PATH("CLKC0_EXT"),
    .FIN("25.000"),
    .FREQ_LOCK_ACCURACY(2),
    .GEN_BASIC_CLOCK("DISABLE"),
    .GMC_GAIN(6),
    .GMC_TEST(14),
    .ICP_CURRENT(3),
    .IF_ESCLKSTSW("DISABLE"),
    .INTFB_WAKE("DISABLE"),
    .KVCO(6),
    .LPF_CAPACITOR(3),
    .LPF_RESISTOR(2),
    .NORESET("DISABLE"),
    .ODIV_MUXC0("DIV"),
    .ODIV_MUXC1("DIV"),
    .ODIV_MUXC2("DIV"),
    .ODIV_MUXC3("DIV"),
    .ODIV_MUXC4("DIV"),
    .PLLC2RST_ENA("DISABLE"),
    .PLLC34RST_ENA("DISABLE"),
    .PLLMRST_ENA("DISABLE"),
    .PLLRST_ENA("DISABLE"),
    .PLL_LOCK_MODE(0),
    .PREDIV_MUXC0("VCO"),
    .PREDIV_MUXC1("VCO"),
    .PREDIV_MUXC2("VCO"),
    .PREDIV_MUXC3("VCO"),
    .PREDIV_MUXC4("VCO"),
    .REFCLK_DIV(1),
    .REFCLK_SEL("INTERNAL"),
    .STDBY_ENABLE("DISABLE"),
    .STDBY_VCO_ENA("DISABLE"),
    .SYNC_ENABLE("DISABLE"),
    .VCO_NORESET("DISABLE"))
    pll_inst (
    .daddr(6'b000000),
    .dclk(1'b0),
    .dcs(1'b0),
    .di(8'b00000000),
    .dwe(1'b0),
    .fbclk(clk0_out),
    .psclk(1'b0),
    .psclksel(3'b000),
    .psdown(1'b0),
    .psstep(1'b0),
    .refclk(refclk),
    .reset(1'b0),
    .stdby(1'b0),
    .clkc({open_n47,open_n48,open_n49,clk1_out,clk0_buf}));  // al_ip/pll1.v(60)

endmodule
module sdr_sdram(CLK, RESET_N, ADDR, CMD, CMDACK, DATAIN, DATAOUT, SA, BA, CS_N, CKE, RAS_N, CAS_N, WE_N, DQ);
   
   parameter        ASIZE = 21;
   parameter        DSIZE = 32;
   parameter        ROWSIZE = 11;
   parameter        COLSIZE = 8;
   parameter        BANKSIZE = 2;
   parameter        ROWSTART = 8;
   parameter        COLSTART = 0;
   parameter        BANKSTART = 19;
   
   input            CLK;
   input            RESET_N;
   input [20:0]     ADDR;
   input [2:0]      CMD;
   output           CMDACK;
   input [31:0]     DATAIN;
   output [31:0]    DATAOUT;
   reg [31:0]       DATAOUT;
   output [10:0]    SA;
   reg [10:0]       SA;
   output [1:0]     BA;
   reg [1:0]        BA;
   output           CS_N;
   reg              CS_N;
   output           CKE;
   reg              CKE;
   output           RAS_N;
   reg              RAS_N;
   output           CAS_N;
   reg              CAS_N;
   output           WE_N;
   reg              WE_N;
   inout [31:0]     DQ;
   
   
   wire [10:0]      ISA;
   wire [1:0]       IBA;
   wire             ICS_N;
   wire             ICKE;
   wire             IRAS_N;
   wire             ICAS_N;
   wire             IWE_N;
   reg  [DSIZE-1:0] DQIN;
   wire [DSIZE-1:0] IDATAOUT;
   wire [DSIZE-1:0] DQOUT;
   
   wire [ASIZE-1:0] saddr;
   wire [1:0]       sc_cl;
   wire [1:0]       sc_rc;
   wire [3:0]       sc_rrd;
   wire             sc_pm;
   wire [3:0]       sc_bl;
   wire             load_mode;
   wire             nop;
   wire             reada;
   wire             writea;
   wire             precharge;
   wire             oe;
   wire             cm_ack;
   
   wire             CLK133B;
   
   
   control_interface #(ASIZE) ux_control(.CLK(CLK), .RESET_N(RESET_N), .CMD(CMD), .ADDR(ADDR), .CM_ACK(cm_ack), .NOP(nop), .READA(reada), .WRITEA(writea), .PRECHARGE(precharge), .LOAD_MODE(load_mode), .SADDR(saddr), .SC_CL(sc_cl), .SC_RC(sc_rc), .SC_RRD(sc_rrd), .SC_PM(sc_pm), .SC_BL(sc_bl),.CMD_ACK(CMDACK));
   
   
   command #(ASIZE, DSIZE, ROWSIZE, COLSIZE, BANKSIZE, ROWSTART, COLSTART, BANKSTART) ux_command(.CLK(CLK), .RESET_N(RESET_N), .SADDR(saddr), .NOP(nop), .READA(reada), .WRITEA(writea),.PRECHARGE(precharge), .LOAD_MODE(load_mode), .SC_CL(sc_cl), .SC_RC(sc_rc), .SC_RRD(sc_rrd), .SC_PM(sc_pm), .SC_BL(sc_bl),.CM_ACK(cm_ack), .OE(oe), .SA(ISA), .BA(IBA), .CS_N(ICS_N), .CKE(ICKE), .RAS_N(IRAS_N), .CAS_N(ICAS_N), .WE_N(IWE_N));
   
   
   sdr_data_path #(DSIZE) ux_data_path(.CLK(CLK), .RESET_N(RESET_N), .OE(oe), .DATAIN(DATAIN), .DATAOUT(IDATAOUT), .DQIN(DQIN), .DQOUT(DQOUT));
   
   
   always @(posedge CLK)
      
      begin
         SA <= ISA;
         BA <= IBA;
         CS_N <= ICS_N;
         CKE <= ICKE;
         RAS_N <= IRAS_N;
         CAS_N <= ICAS_N;
         WE_N <= IWE_N;
         DQIN <= DQ;
         DATAOUT <= IDATAOUT;
      end
   
   assign DQ = (oe == 1'b1) ? DQOUT : 
               {32{1'bZ}};
   
endmodule