dakies/OSS_Verilog huggingface dataset:
module mrx_protocol (/*AUTOARG*/
   // Outputs
   fifo_access, fifo_packet,
   // Inputs
   rx_clk, nreset, datasize, lsbfirst, io_access, io_packet
   );

   //#####################################################################
   //# INTERFACE
   //#####################################################################

   //parameters
   parameter  PW   = 104;               // packet width (core)
   parameter  NMIO = 8;                 // io packet width
   parameter  CW   = $clog2(2*PW/NMIO); // transfer count width
   
   //clock and reset
   input              rx_clk;        // rx clock
   input 	      nreset;        // async active low reset
   
   //config
   input [7:0] 	      datasize;      // dynamic width of output data
   input 	      lsbfirst;
   
   //16 bit interface
   input 	      io_access;     // access signal from IO
   input [2*NMIO-1:0] io_packet;     // data from IO 
   
   //wide input interface
   output 	      fifo_access;   // access for fifo
   output [PW-1:0]    fifo_packet;   // packet for fifo

   //#####################################################################
   //# BODY
   //#####################################################################

   //regs
   reg [2:0] 	   mrx_state;
   reg [CW-1:0]    mrx_count;   
   reg 		   fifo_access;
   wire 	   shift;
   wire 	   transfer_done;
   
   
   //##########################
   //# STATE MACHINE
   //##########################

   `define MRX_IDLE     3'b000
   `define MRX_BUSY     3'b001

   always @ (posedge rx_clk or negedge nreset)
     if(!nreset)
       mrx_state[2:0] <= `MRX_IDLE;
     else
       case (mrx_state[2:0])
	 `MRX_IDLE:  mrx_state[2:0] <= io_access  ? `MRX_BUSY : `MRX_IDLE;
	 `MRX_BUSY:  mrx_state[2:0] <= ~io_access ? `MRX_IDLE : `MRX_BUSY;
	 default: mrx_state[2:0] <= 'b0;	 
       endcase // case (mrx_state[2:0])

   //tx word counter
   always @ (posedge rx_clk)    
     if((mrx_state[2:0]==`MRX_IDLE) | transfer_done)
       mrx_count[CW-1:0] <= datasize[CW-1:0];
     else if(mrx_state[2:0]==`MRX_BUSY)
       mrx_count[CW-1:0] <= mrx_count[CW-1:0] - 1'b1;   
   
   assign transfer_done = (mrx_count[CW-1:0]==1'b1) & (mrx_state[2:0]==`MRX_BUSY);
   assign shift         = (mrx_state[2:0]==`MRX_BUSY);
   
   //pipeline access signal
   always @ (posedge rx_clk or negedge nreset)
     if(!nreset)
       fifo_access <= 'b0;
     else
       fifo_access <= transfer_done;
   
   //##########################
   //# SHIFT REGISTER
   //##########################

   oh_ser2par #(.PW(PW),
		.SW(2*NMIO))
   
   ser2par (// Outputs
	    .dout	(fifo_packet[PW-1:0]),
	    // Inputs
	    .clk	(rx_clk),
	    .din	(io_packet[2*NMIO-1:0]),
	    .lsbfirst	(lsbfirst),
	    .shift	(shift)
	    );
    
   
endmodule // mrx_protocol
module dut(/*AUTOARG*/
   // Outputs
   dut_active, clkout, wait_out, access_out, packet_out,
   // Inputs
   clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
   );

   //##########################################################################
   //# INTERFACE 
   //##########################################################################

   parameter AW    = 32;
   parameter ID    = 12'h810;   
   parameter S_IDW = 12; 
   parameter M_IDW = 6; 
   parameter PW    = 2*AW + 40;     
   parameter N     = 1;

   //clock,reset
   input            clk1;
   input            clk2;
   input            nreset;
   input [N*N-1:0]  vdd;
   input 	    vss;
   output 	    dut_active;
   output 	    clkout;
   
   //Stimulus Driven Transaction
   input [N-1:0]     access_in;
   input [N*PW-1:0]  packet_in;
   output [N-1:0]    wait_out;

   //DUT driven transaction
   output [N-1:0]    access_out;
   output [N*PW-1:0] packet_out;
   input [N-1:0]     wait_in;

   //##########################################################################
   //#BODY 
   //##########################################################################

   wire 	     mem_rd_wait;
   wire 	     mem_wr_wait;
   wire 	     mem_access;
   wire [PW-1:0]     mem_packet;

   /*AUTOINPUT*/
  
   // End of automatics
   /*AUTOWIRE*/
      
   assign clkout     = clk1;   
   assign dut_active = 1'b1;
   assign wait_out   = 1'b0;
   
   emmu eemu (// Outputs
	      .reg_rdata		(),
	      .emesh_access_out		(access_out),
	      .emesh_packet_out		(packet_out[PW-1:0]),
	      // Inputs
	      .nreset			(nreset),
	      .mmu_en			(1'b0),
	      .wr_clk			(clk1),
	      .reg_access		(1'b0),
	      .reg_packet		({(PW){1'b0}}),
	      .rd_clk			(clk1),
	      .emesh_access_in		(access_in),
	      .emesh_packet_in		(packet_in[PW-1:0]),
	      .emesh_wait_in		(wait_in));
   
   
endmodule
module pi2c (/*AUTOARG*/
   // Outputs
   i2c_sda_i, i2c_scl_i,
   // Inouts
   i2c_sda, i2c_scl,
   // Inputs
   i2c_sda_o, i2c_sda_t, i2c_scl_o, i2c_scl_t
   );

   parameter PORTABLE = 0;
      
   input  i2c_sda_o;
   input  i2c_sda_t;
   output i2c_sda_i;
   
   input  i2c_scl_o;
   input  i2c_scl_t;
   output i2c_scl_i;
   
   inout  i2c_sda;
   inout  i2c_scl;
   
   generate
      if(PORTABLE==1) begin
	 wire   i2c_sda = i2c_sda_t ? 1'bz: i2c_sda_o;
	 wire   i2c_sda_i = i2c_sda;
	 
	 wire   i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
	 wire   i2c_scl_i = i2c_scl;
      end
      else
	begin
	   IOBUF #(
		   .DRIVE(8),              // Specify the output drive strength
		   .IBUF_LOW_PWR("TRUE"),  // Low Power - "TRUE", High Performance = "FALSE" 
		   .IOSTANDARD("DEFAULT"), // Specify the I/O standard
		   .SLEW("SLOW")           // Specify the output slew rate
		   ) i_sda (
			    .O(i2c_sda_i),  // Buffer output
			    .IO(i2c_sda),   // Buffer inout port (connect directly to top-level port)
			    .I(i2c_sda_o),  // Buffer input
			    .T(i2c_sda_t)   // 3-state enable input, high=input, low=output
			    );
	   
	   IOBUF #(
		   .DRIVE(8),
		   .IBUF_LOW_PWR("TRUE"),
		   .IOSTANDARD("DEFAULT"),
		   .SLEW("SLOW")   
		   ) i_scl (
			    .O(i2c_scl_i),
			    .IO(i2c_scl), 
			    .I(i2c_scl_o),
			    .T(i2c_scl_t) 
			    );
	end
   endgenerate
      
endmodule // pi2c
module dut(/*AUTOARG*/
   // Outputs
   dut_active, clkout, wait_out, access_out, packet_out,
   // Inputs
   clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
   );

   //##########################################################################
   //# INTERFACE 
   //##########################################################################

   parameter AW    = 32;
   parameter ID    = 12'h810;   
   parameter S_IDW = 12; 
   parameter M_IDW = 6; 
   parameter PW    = 2*AW + 40;     
   parameter N     = 1;

   //clock,reset
   input            clk1;
   input            clk2;
   input            nreset;
   input [N*N-1:0]  vdd;
   input 	    vss;
   output 	    dut_active;
   output 	    clkout;
   
   //Stimulus Driven Transaction
   input [N-1:0]     access_in;
   input [N*PW-1:0]  packet_in;
   output [N-1:0]    wait_out;

   //DUT driven transaction
   output [N-1:0]    access_out;
   output [N*PW-1:0] packet_out;
   input [N-1:0]     wait_in;

   //##########################################################################
   //#BODY 
   //##########################################################################

   wire 	     mem_rd_wait;
   wire 	     mem_wr_wait;
   wire 	     mem_access;
   wire [PW-1:0]     mem_packet;

   /*AUTOINPUT*/
  
   // End of automatics
   /*AUTOWIRE*/
      
   assign clkout     = clk1;   
   assign dut_active = 1'b1;
   assign wait_out   = 1'b0;
   
   emailbox emailbox (.reg_rdata	(),
		      .mailbox_irq	(mailbox_irq),
		      .mailbox_wait	(),
		      // Inputs
		      .nreset		(nreset),
		      .wr_clk		(clk1),
		      .rd_clk		(clk1),
		      .emesh_access	(access_in),
		      .emesh_packet	(packet_in[PW-1:0]),
		      .reg_access	(1'b0),
		      .reg_packet	({(PW){1'b0}}),
		      .mailbox_irq_en	(1'b1)
		      );
   
endmodule
module dut(/*AUTOARG*/
   // Outputs
   dut_active, clkout, wait_out, access_out, packet_out,
   // Inputs
   clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
   );

   //#####################################################################
   //# INTERFACE
   //#####################################################################

   //parameters
   parameter N       =  1;   
   parameter AW      = 32;               // address width
   parameter NMIO    =  8;               // IO data width
   parameter DEF_CFG =  18'h1070;        // for 104 bits   
   parameter DEF_CLK =  7;   
   localparam PW     = 2*AW + 40;        // standard packet   
   
   //clock, reset
   input            clk1;
   input            clk2;
   input            nreset;
   input [N*N-1:0]  vdd;
   input 	    vss;
   output 	    dut_active;
   output 	    clkout;
   
   //Stimulus Driven Transaction
   input [N-1:0]     access_in;
   input [N*PW-1:0]  packet_in;
   output [N-1:0]    wait_out;

   //DUT driven transactoin
   output [N-1:0]    access_out;
   output [N*PW-1:0] packet_out;
   input [N-1:0]     wait_in;

   //########################################
   //# BODY
   //########################################

   //wires
   wire 	     reg_access_in;   
   wire [PW-1:0]     reg_packet_in;
   wire 	     reg_wait_in;
   wire 	     edma_access_in;
   
   /*AUTOINPUT*/
   // End of automatics
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire			irq;			// From edma of edma.v
   wire			reg_access_out;		// From edma of edma.v
   wire [PW-1:0]	reg_packet_out;		// From edma of edma.v
   wire			reg_wait_out;		// From edma of edma.v
   // End of automatics
 
   
   assign dut_active       = 1'b1;
   assign clkout           = clk1;

   //########################################
   //# DECODE (SPLITTING CTRL+DATA)
   //########################################

   //hack: send to regfile if addr[31:20] is zero
   assign edma_access_in   = access_in & |packet_in[39:28];
   assign reg_access_in    = access_in & ~(|packet_in[39:28]);   
   assign reg_packet_in    = packet_in;
   assign reg_wait_in      = wait_in;

   //########################################
   //# DUT: EDMA
   //########################################
   
   /*edma  AUTO_TEMPLATE (
            .clk	    (clk1),
            .access_in	    (edma_access_in),
         
    );
    */
 
   edma #(.AW(AW))
	
   edma (/*AUTOINST*/
	 // Outputs
	 .irq				(irq),
	 .wait_out			(wait_out),
	 .access_out			(access_out),
	 .packet_out			(packet_out[PW-1:0]),
	 .reg_wait_out			(reg_wait_out),
	 .reg_access_out		(reg_access_out),
	 .reg_packet_out		(reg_packet_out[PW-1:0]),
	 // Inputs
	 .clk				(clk1),			 // Templated
	 .nreset			(nreset),
	 .access_in			(edma_access_in),	 // Templated
	 .packet_in			(packet_in[PW-1:0]),
	 .wait_in			(wait_in),
	 .reg_access_in			(reg_access_in),
	 .reg_packet_in			(reg_packet_in[PW-1:0]),
	 .reg_wait_in			(reg_wait_in));
   
     
endmodule // dut
module CLKDIV(/*AUTOARG*/
   // Outputs
   clkout,
   // Inputs
   clkin, divcfg, reset
   );

   input       clkin;    // Input clock
   input [3:0] divcfg;   // Divide factor (1-128)
   input       reset;    // Counter init
   output      clkout;   // Divided clock phase aligned with clkin 

   reg        clkout_reg;
   reg [7:0]  counter;   
   reg [7:0]  divcfg_dec;
   reg [3:0]  divcfg_reg;
   
   wire       div_bp;   
   wire       posedge_match;
   wire       negedge_match;  
   
   // ###################
   // # Decode divcfg
   // ###################

   always @ (divcfg[3:0])
     casez (divcfg[3:0])
       4'b0001 : divcfg_dec[7:0] = 8'b00000010;  // Divide by 2
       4'b0010 : divcfg_dec[7:0] = 8'b00000100;  // Divide by 4
       4'b0011 : divcfg_dec[7:0] = 8'b00001000;  // Divide by 8
       4'b0100 : divcfg_dec[7:0] = 8'b00010000;  // Divide by 16
       4'b0101 : divcfg_dec[7:0] = 8'b00100000;  // Divide by 32
       4'b0110 : divcfg_dec[7:0] = 8'b01000000;  // Divide by 64
       4'b0111 : divcfg_dec[7:0] = 8'b10000000;  // Divide by 128
       default : divcfg_dec[7:0] = 8'b00000000;   // others
     endcase
   
   always @ (posedge clkin or posedge reset)
     if(reset)
       counter[7:0] <= 8'b00000001;
     else if(posedge_match)
       counter[7:0] <= 8'b00000001;// Self resetting
     else
       counter[7:0] <= (counter[7:0] + 8'b00000001);
   
   assign posedge_match    = (counter[7:0]==divcfg_dec[7:0]);
   assign negedge_match    = (counter[7:0]=={1'b0,divcfg_dec[7:1]}); 
   
   always @ (posedge clkin or posedge reset)
     if(reset)
       clkout_reg <= 1'b0;   
     else if(posedge_match)
       clkout_reg <= 1'b1;
     else if(negedge_match)
       clkout_reg <= 1'b0;

   //Divide by one bypass
   assign div_bp  = (divcfg[3:0]==4'b0000);
   assign clkout  = div_bp ? clkin : clkout_reg;
 
endmodule // CLKDIV
module IBUFE3 #(
`ifdef XIL_TIMING
  parameter LOC = "UNPLACED",
`endif
  parameter IBUF_LOW_PWR = "TRUE",
  parameter IOSTANDARD = "DEFAULT",
  parameter integer SIM_INPUT_BUFFER_OFFSET = 0,
  parameter USE_IBUFDISABLE = "FALSE"
)(
  output O,

  input I,
  input IBUFDISABLE,
  input [3:0] OSC,
  input OSC_EN,
  input VREF
);
  
// define constants
  localparam MODULE_NAME = "IBUFE3";
  localparam in_delay    = 0;
  localparam out_delay   = 0;
  localparam inclk_delay    = 0;
  localparam outclk_delay   = 0;

// Parameter encodings and registers
  localparam IBUF_LOW_PWR_FALSE = 1;
  localparam IBUF_LOW_PWR_TRUE = 0;
  localparam USE_IBUFDISABLE_FALSE = 0;
  localparam USE_IBUFDISABLE_TRUE = 1;

// include dynamic registers - XILINX test only
  reg trig_attr = 1'b0;
  localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
  localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET;
  localparam [40:1] USE_IBUFDISABLE_REG = USE_IBUFDISABLE;


endmodule
module oh_clockdiv_model(/*AUTOARG*/
   // Outputs
   clkout,
   // Inputs
   clkin, divcfg, reset
   );

   input       clkin;    // Input clock
   input [3:0] divcfg;   // Divide factor (1-128)
   input       reset;    // Counter init
   output      clkout;   // Divided clock phase aligned with clkin 

   reg        clkout_reg;
   reg [7:0]  counter;   
   reg [7:0]  divcfg_dec;
   reg [3:0]  divcfg_reg;
   
   wire       div_bp;   
   wire       posedge_match;
   wire       negedge_match;  
   
   // ###################
   // # Decode divcfg
   // ###################

   always @ (divcfg[3:0])
     casez (divcfg[3:0])
       4'b0001 : divcfg_dec[7:0] = 8'b00000010;  // Divide by 2
       4'b0010 : divcfg_dec[7:0] = 8'b00000100;  // Divide by 4
       4'b0011 : divcfg_dec[7:0] = 8'b00001000;  // Divide by 8
       4'b0100 : divcfg_dec[7:0] = 8'b00010000;  // Divide by 16
       4'b0101 : divcfg_dec[7:0] = 8'b00100000;  // Divide by 32
       4'b0110 : divcfg_dec[7:0] = 8'b01000000;  // Divide by 64
       4'b0111 : divcfg_dec[7:0] = 8'b10000000;  // Divide by 128
       default : divcfg_dec[7:0] = 8'b00000000;   // others
     endcase
   
   always @ (posedge clkin or posedge reset)
     if(reset)
       counter[7:0] <= 8'b00000001;
     else if(posedge_match)
       counter[7:0] <= 8'b00000001;// Self resetting
     else
       counter[7:0] <= (counter[7:0] + 8'b00000001);
   
   assign posedge_match    = (counter[7:0]==divcfg_dec[7:0]);
   assign negedge_match    = (counter[7:0]=={1'b0,divcfg_dec[7:1]}); 
   
   always @ (posedge clkin or posedge reset)
     if(reset)
       clkout_reg <= 1'b0;   
     else if(posedge_match)
       clkout_reg <= 1'b1;
     else if(negedge_match)
       clkout_reg <= 1'b0;

   //Divide by one bypass
   assign div_bp  = (divcfg[3:0]==4'b0000);
   assign clkout  = div_bp ? clkin : clkout_reg;
 
endmodule // oh_clockdiv
module IBUFDS_INTERMDISABLE (O, I, IB, IBUFDISABLE, INTERMDISABLE);

`ifdef XIL_TIMING
  parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
  parameter DIFF_TERM = "FALSE";
  parameter DQS_BIAS = "FALSE";
  parameter IBUF_LOW_PWR = "TRUE";
  parameter IOSTANDARD = "DEFAULT";
  parameter SIM_DEVICE = "7SERIES";
  parameter USE_IBUFDISABLE = "TRUE";

  localparam MODULE_NAME = "IBUFDS_INTERMDISABLE";


    output O;

    input  I;
    input  IB;
    input  IBUFDISABLE;
    input  INTERMDISABLE;

endmodule // IBUFDS_INTERMDISABLE
module IDELAYE3 #(
  `ifdef XIL_TIMING
  parameter LOC = "UNPLACED",  
  `endif
  parameter CASCADE = "NONE",
  parameter DELAY_FORMAT = "TIME",
  parameter DELAY_SRC = "IDATAIN",
  parameter DELAY_TYPE = "FIXED",
  parameter integer DELAY_VALUE = 0,
  parameter [0:0] IS_CLK_INVERTED = 1'b0,
  parameter [0:0] IS_RST_INVERTED = 1'b0,
  parameter LOOPBACK = "FALSE",
  parameter real REFCLK_FREQUENCY = 300.0,
  parameter real SIM_VERSION = 2.0,
  parameter UPDATE_MODE = "ASYNC"
)(
  output CASC_OUT,
  output [8:0] CNTVALUEOUT,
  output DATAOUT,

  input CASC_IN,
  input CASC_RETURN,
  input CE,
  input CLK,
  input [8:0] CNTVALUEIN,
  input DATAIN,
  input EN_VTC,
  input IDATAIN,
  input INC,
  input LOAD,
  input RST
);
 
endmodule
module IBUF_INTERMDISABLE (O, I, IBUFDISABLE, INTERMDISABLE);

    parameter IBUF_LOW_PWR = "TRUE";
    parameter IOSTANDARD = "DEFAULT";
    parameter SIM_DEVICE = "7SERIES";
    parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
    parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
    
    output O;

    input  I;
    input  IBUFDISABLE;
    input  INTERMDISABLE;

endmodule
module IBUFDS_DIFF_OUT (O, OB, I, IB);

    parameter DIFF_TERM = "FALSE";
    parameter DQS_BIAS = "FALSE";
    parameter IBUF_LOW_PWR = "TRUE";
    parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
    parameter LOC = " UNPLACED";
`endif
    output O, OB;

    input  I, IB;


endmodule
module IBUFDS_INTERMDISABLE_INT (O, I, IB, IBUFDISABLE, INTERMDISABLE);

`ifdef XIL_TIMING
  parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
  parameter DIFF_TERM = "FALSE";
  parameter DQS_BIAS = "FALSE";
  parameter IBUF_LOW_PWR = "TRUE";
  parameter IOSTANDARD = "DEFAULT";
  parameter USE_IBUFDISABLE = "TRUE";

  localparam MODULE_NAME = "IBUFDS_INTERMDISABLE_INT";


    output O;

    input  I;
    input  IB;
    input  IBUFDISABLE;
    input  INTERMDISABLE;

 
endmodule
module RAM32X1D (/*AUTOARG*/
   // Outputs
   DPO, SPO,
   // Inputs
   A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE
   );

   //inputs
   input A0;
   input A1;
   input A2;
   input A3;
   input A4;
   input D;
   input DPRA0;
   input DPRA1;
   input DPRA2;
   input DPRA3;
   input DPRA4;
   input WCLK;
   input WE;
   
   //outputs
   output DPO;
   output SPO;

   assign DPO=1'b0;
   assign SPO=1'b0;
   
  
endmodule // RAM32X1D
module OSERDESE2 ( /*AUTOARG*/
   // Outputs
   OFB, OQ, SHIFTOUT1, SHIFTOUT2, TBYTEOUT, TFB, TQ,
   // Inputs
   CLK, CLKDIV, D1, D2, D3, D4, D5, D6, D7, D8, OCE, RST, SHIFTIN1,
   SHIFTIN2, T1, T2, T3, T4, TBYTEIN, TCE
   );

   parameter DATA_RATE_OQ=0;
   parameter DATA_RATE_TQ=0;
   parameter DATA_WIDTH=0;
   parameter INIT_OQ=0;
   parameter INIT_TQ=0;
   parameter SERDES_MODE=0;
   parameter SRVAL_OQ=0;
   parameter SRVAL_TQ=0;
   parameter TBYTE_CTL=0;
   parameter TBYTE_SRC=0;
   parameter TRISTATE_WIDTH=0;

     
   output OFB;                    // output feedback port
   output OQ;                     // data output port, D1 appears first
   output SHIFTOUT1;              // connect to shift in of master
   output SHIFTOUT2;              // connect to shift in of master
   output TBYTEOUT;               // byte group tristate output to IOB
   output TFB;                    // 3-state control output for ODELAYE2
   output TQ;                     // 3-state control output
   input  CLK;                    // high speed shift out clock
   input  CLKDIV;                 // low speed clock (/4 for example)
   input  D1;                     // first bit to shift out
   input  D2;                     //
   input  D3;                     //
   input  D4;                     //
   input  D5;                     //
   input  D6;                     //
   input  D7;                     //
   input  D8;                     //
   input  OCE;                    // active high clock enable for datapath
   input  RST;                    // async reset, all output flops driven low
   input  SHIFTIN1;               // connect to shift out of other
   input  SHIFTIN2;               // connect to shift out of other
   input  T1;                     // parallel 3-state signals
   input  T2;                     // ??why 4??
   input  T3;                     //
   input  T4;                     //
   input  TBYTEIN;                // byte group tristate input
   input  TCE;                    // active high clock enable for 3-state

   //Statemachine
   reg [2:0] state;


   reg [7:0] buffer;
   reg [1:0] clkdiv_sample;
   reg [3:0] even;
   reg [3:0] odd;
   
   //parallel sample
   always @ (posedge CLKDIV)
     buffer[7:0]<={D8,D7,D6,D5,D4,D3,D2,D1};
   
   //sample clkdiv
   always @ (negedge CLK)
     clkdiv_sample[1:0] <= {clkdiv_sample[0],CLKDIV};

   //shift on second consective clk rising edge that clkdi_sample==0

   wire      load_parallel = (clkdiv_sample[1:0]==2'b00);

   always @ (posedge CLK)
     if(load_parallel)
       even[3:0]<={buffer[6],buffer[4],buffer[2],buffer[0]};
     else
       even[3:0]<={1'b0,even[3:1]};

   always @ (posedge CLK)
     if(load_parallel)
       odd[3:0]<={buffer[7],buffer[5],buffer[3],buffer[1]};
     else
       odd[3:0]<={1'b0,odd[3:1]};
     
   assign OQ = CLK ? even[0] : odd[0];
   
   //setting other outputs
   assign OFB       = 1'b0;
   assign TQ        = 1'b0;
   assign TBYTEOUT  = 1'b0;
   assign SHIFTOUT1 = 1'b0;   		      
   assign SHIFTOUT2 = 1'b0;   
   assign TFB       = 1'b0;
   
endmodule // OSERDESE2
module IBUF (O, I);

    parameter CAPACITANCE = "DONT_CARE";
    parameter IBUF_DELAY_VALUE = "0";
    parameter IBUF_LOW_PWR = "TRUE";
    parameter IFD_DELAY_VALUE = "AUTO";
    parameter IOSTANDARD = "DEFAULT";

`ifdef XIL_TIMING

    parameter LOC = " UNPLACED";

`endif

    
    output O;
    input  I;

    buf B1 (O, I);
    
endmodule
module BUFG (/*AUTOARG*/
   // Outputs
   O,
   // Inputs
   I
   );
   input I;
   output O;

   assign O = I;
   
endmodule // IBUFDS
module IBUFDS_IBUFDISABLE (O, I, IB, IBUFDISABLE);

`ifdef XIL_TIMING
  parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
  parameter DIFF_TERM = "FALSE";
  parameter DQS_BIAS = "FALSE";
  parameter IBUF_LOW_PWR = "TRUE";
  parameter IOSTANDARD = "DEFAULT";
  parameter SIM_DEVICE = "7SERIES";
  parameter USE_IBUFDISABLE = "TRUE";

  localparam MODULE_NAME = "IBUFDS_IBUFDISABLE";


    output O;

    input  I;
    input  IB;
    input  IBUFDISABLE;
   
endmodule
module IBUF_IBUFDISABLE (O, I, IBUFDISABLE);

    parameter IBUF_LOW_PWR = "TRUE";
    parameter IOSTANDARD = "DEFAULT";
    parameter SIM_DEVICE = "7SERIES";
    parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
    parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
    
    output O;

    input  I;
    input  IBUFDISABLE;
   
endmodule
module IOBUFDSE3 #(
`ifdef XIL_TIMING
  parameter LOC = "UNPLACED",
`endif
  parameter DIFF_TERM = "FALSE",
  parameter DQS_BIAS = "FALSE",
  parameter IBUF_LOW_PWR = "TRUE",
  parameter IOSTANDARD = "DEFAULT",
  parameter integer SIM_INPUT_BUFFER_OFFSET = 0,
  parameter USE_IBUFDISABLE = "FALSE"
)(
  output O,

  inout IO,
  inout IOB,

  input DCITERMDISABLE,
  input I,
  input IBUFDISABLE,
  input [3:0] OSC,
  input [1:0] OSC_EN,
  input T
);
  
// define constants
  localparam MODULE_NAME = "IOBUFDSE3";
  localparam in_delay    = 0;
  localparam out_delay   = 0;
  localparam inclk_delay    = 0;
  localparam outclk_delay   = 0;

// Parameter encodings and registers
  localparam DIFF_TERM_FALSE = 0;
  localparam DIFF_TERM_TRUE = 1;
  localparam DQS_BIAS_FALSE = 0;
  localparam DQS_BIAS_TRUE = 1;
  localparam IBUF_LOW_PWR_FALSE = 1;
  localparam IBUF_LOW_PWR_TRUE = 0;
  localparam USE_IBUFDISABLE_FALSE = 0;
  localparam USE_IBUFDISABLE_TRUE = 1;

// include dynamic registers - XILINX test only
  reg trig_attr = 1'b0;
  localparam [40:1] DIFF_TERM_REG = DIFF_TERM;
  localparam [40:1] DQS_BIAS_REG = DQS_BIAS;
  localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
  localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET;
  localparam [40:1] USE_IBUFDISABLE_REG = USE_IBUFDISABLE;


endmodule
module IOBUF(/*AUTOARG*/
   // Outputs
   O,
   // Inouts
   IO,
   // Inputs
   T, I
   );

   parameter DRIVE        = 8;
   parameter IOSTANDARD   = "LVDS_25";
   parameter DIFF_TERM    = "TRUE";
   parameter SLEW         = "FAST";
   parameter IBUF_LOW_PWR = "TRUE";
   
   inout IO;
   input T;
   input I;
   output O;

   assign O  = IO;

   assign IO = T ? 1'bz : I;
   
endmodule // IOBUF
module BUFIO (/*AUTOARG*/
   // Outputs
   O,
   // Inputs
   I
   );

   output O;
   input  I;
    
   assign O=I;
     
endmodule
module IBUFDS_GTE2 (
    O,
    ODIV2,

    CEB,
    I,
    IB
    );
`ifdef XIL_TIMING
    parameter LOC = "UNPLACED";
`endif
    parameter CLKCM_CFG = "TRUE";
    parameter CLKRCV_TRST = "TRUE";
    parameter [1:0] CLKSWING_CFG = 2'b11;

    output O;
    output ODIV2;

    input CEB;
    input I;
    input IB;



endmodule
module IDDR (/*AUTOARG*/
   // Outputs
   Q1, Q2,
   // Inputs
   C, CE, D, R, S
   );

   //Default parameters
    parameter DDR_CLK_EDGE        = "OPPOSITE_EDGE";    
    parameter INIT_Q1             = 1'b0;
    parameter INIT_Q2             = 1'b0;
    parameter [0:0] IS_C_INVERTED = 1'b0;
    parameter [0:0] IS_D_INVERTED = 1'b0;
    parameter SRTYPE              = "SYNC";

   localparam HOLDHACK            = 0.1;
      
   output   Q1;   // IDDR registered output (first) 
   output   Q2;   // IDDR registered output (second)    
   input    C;    // clock
   input    CE;   // clock enable, set to high to clock in data
   input    D;    // data input from IOB
   input    R;    // sync or async reset
   input    S;    // syn/async "set to 1"

   //trick for string comparison
   localparam [152:1] DDR_CLK_EDGE_REG = DDR_CLK_EDGE;

   reg 	    Q1_pos;
   reg 	    Q1_reg;

   reg 	    Q2_pos;
   reg 	    Q2_neg;
   
   always @ (posedge C)
     if(CE)
       Q1_pos <= #(HOLDHACK) D;

   always @ (posedge C)
     if(CE)
       Q1_reg <= #(HOLDHACK) Q1_pos;
         
   always @ (negedge C)
     if(CE)
       Q2_neg <= #(HOLDHACK) D;
   
   always @ (posedge C)
     if(CE)
      Q2_pos <= #(HOLDHACK) Q2_neg;

   //Select behavior based on parameters
   assign Q1 = (DDR_CLK_EDGE_REG == "SAME_EDGE_PIPELINED") ? Q1_reg :
	       (DDR_CLK_EDGE_REG == "SAME_EDGE")           ? Q1_pos :
	                                                     1'b0;
   
   assign Q2 = (DDR_CLK_EDGE_REG == "SAME_EDGE_PIPELINED") ? Q2_pos :
	       (DDR_CLK_EDGE_REG == "SAME_EDGE")           ? Q2_pos :
	                                                     1'b0;
            
endmodule // IDDR
module OBUFDS_GTE3_ADV #(
  `ifdef XIL_TIMING //Simprim 
  parameter LOC = "UNPLACED",  
  `endif
  parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
  parameter [4:0] REFCLK_ICNTL_TX = 5'b00000
)(
  output O,
  output OB,

  input CEB,
  input [3:0] I,
  input [1:0] RXRECCLK_SEL
);
endmodule
module IBUFGDS (/*AUTOARG*/
   // Outputs
   O,
   // Inputs
   I, IB
   );

   parameter DIFF_TERM=0;
   parameter IOSTANDARD=0;

   input I;
   input IB;
   output O;

   assign O = I & ~IB;
   
   
endmodule // IBUFGDS
module IOBUFDS (O, IO, IOB, I, T);

`ifdef XIL_TIMING
    parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
    parameter DIFF_TERM = "FALSE";
    parameter DQS_BIAS = "FALSE";
    parameter IBUF_LOW_PWR = "TRUE";
    parameter IOSTANDARD = "DEFAULT";
    parameter SLEW = "SLOW";

   localparam MODULE_NAME = "IOBUFDS";


    output O;
    inout  IO, IOB;
    input  I, T;

   assign O = IO & ~IOB;
   assign IO = T ? 1'bz : I;
   assign IOB = T ? 1'bz : ~I;
   
endmodule
module IDELAYE2 (/*AUTOARG*/
   // Outputs
   CNTVALUEOUT, DATAOUT,
   // Inputs
   C, CE, CINVCTRL, CNTVALUEIN, DATAIN, IDATAIN, INC, LD, LDPIPEEN,
   REGRST
   );

   parameter         CINVCTRL_SEL = "FALSE";          // Enable clock inversion
   parameter         DELAY_SRC = "IDATAIN";           // Delay input 
   parameter         HIGH_PERFORMANCE_MODE  = "FALSE";// Reduced jitter
   parameter         IDELAY_TYPE  = "FIXED";          // Type of delay line
   parameter integer IDELAY_VALUE = 0;                // Input delay tap setting
   parameter [0:0]   IS_C_INVERTED = 1'b0;            // 
   parameter [0:0]   IS_DATAIN_INVERTED = 1'b0;       //
   parameter [0:0]   IS_IDATAIN_INVERTED = 1'b0;      //
   parameter         PIPE_SEL = "FALSE";              // Select pipelined mode
   parameter real    REFCLK_FREQUENCY = 200.0;        // Ref clock frequency
   parameter         SIGNAL_PATTERN    = "DATA";      // Input signal type

`ifdef XIL_TIMING
    parameter LOC = "UNPLACED";
    parameter integer SIM_DELAY_D = 0;
    localparam DELAY_D = (IDELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0;
`endif // ifdef XIL_TIMING

`ifndef XIL_TIMING
    integer DELAY_D=0;
`endif // ifndef XIL_TIMING

   output [4:0] CNTVALUEOUT; // count value for monitoring tap value
   output 	DATAOUT;     // delayed data
   input 	C;           // clock input for variable mode
   input 	CE;          // enable increment/decrement function
   input 	CINVCTRL;    // dynamically inverts clock polarity
   input [4:0] 	CNTVALUEIN;  // counter value for tap delay
   input 	DATAIN;      // data input from FGPA logic
   input 	IDATAIN;     // data input from IBUF
   input 	INC;         // increment tap delay
   input 	LD;          // loads the delay primitive
   input 	LDPIPEEN;    // enables the pipeline register delay 
   input 	REGRST;      // reset for pipeline register

   
   parameter real tap = 1 / (32 * 2 * (REFCLK_FREQUENCY/1000));
     
   reg [4:0] idelay_reg=5'b0;
   reg 	     DATAOUT;
   
   always @ (posedge C)
     if(LD)   
       begin
	  idelay_reg[4:0] <= CNTVALUEIN[4:0];  
       end
   
   //Variable delay
   always @ (IDATAIN)
     DATAOUT <= #(idelay_reg * tap) IDATAIN;

   
   //not modeled
   assign CNTVALUEOUT=5'b0;
   		  
endmodule // IDELAYE2
module IOBUFDS_DIFF_OUT_INTERMDISABLE (O, OB, IO, IOB, I, IBUFDISABLE, INTERMDISABLE, TM, TS);

    parameter DIFF_TERM = "FALSE";
    parameter DQS_BIAS = "FALSE";
    parameter IBUF_LOW_PWR = "TRUE";
    parameter IOSTANDARD = "DEFAULT";
    parameter SIM_DEVICE = "7SERIES";
    parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
    parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING

    output O;
    output OB;
    inout  IO;
    inout  IOB;
    input  I;
    input  IBUFDISABLE;
    input  INTERMDISABLE;
    input  TM;
    input  TS;

endmodule
module ODDR (/*AUTOARG*/
   // Outputs
   Q,
   // Inputs
   C, CE, D1, D2, R, S
   );

   parameter DDR_CLK_EDGE=0; //clock recovery mode
   parameter INIT=0; //Q init value
   parameter SRTYPE=0;//"SYNC", "ASYNC"
   
   input  C;    // Clock input
   input  CE;   // Clock enable input
   input  D1;   // Data input1
   input  D2;   // Data input2
   input  R;    // Reset (depends on SRTYPE)
   input  S;    // Active high asynchronous pin
   output Q;    // Data Output that connects to the IOB pad

   reg 	  Q1,Q2;
   reg 	  Q2_reg;
   
   //Generate different logic based on parameters

   //Only doing same edge and async reset for now   
   
   always @ (posedge C or posedge R)
     if (R)
       Q1 <= 1'b0;
     else
       Q1 <= D1;

   always @ (posedge C or posedge R)
     if (R)
       Q2 <= 1'b0;
     else
       Q2 <= D2;
  
   always @ (negedge C or posedge R)
     if (R)
       Q2_reg <= 1'b0;
     else
       Q2_reg <= Q2;

       
   assign Q = C ? Q1 : Q2_reg;
      
endmodule // ODDR
module ODELAYE2 (/*AUTOARG*/
   // Outputs
   CNTVALUEOUT, DATAOUT,
   // Inputs
   C, CE, CINVCTRL, CLKIN, CNTVALUEIN, INC, LD, LDPIPEEN, ODATAIN,
   REGRST
   );

    parameter CINVCTRL_SEL              = "FALSE";
    parameter DELAY_SRC                 = "ODATAIN";
    parameter HIGH_PERFORMANCE_MODE     = "FALSE";
    parameter [0:0] IS_C_INVERTED       = 1'b0;
    parameter [0:0] IS_ODATAIN_INVERTED = 1'b0;
    parameter ODELAY_TYPE               = "FIXED";
    parameter integer ODELAY_VALUE      = 0;
    parameter PIPE_SEL                  = "FALSE";
    parameter real REFCLK_FREQUENCY     = 200.0;
    parameter SIGNAL_PATTERN            = "DATA";

   input 	 C;           //clock for VARIABLE, VAR_LOAD,VAR_LOAD_PIPE mode
   input 	 REGRST;      //reset pipeline reg to all zeroes
   input 	 LD;          //loads programmed values depending on "mode"     
   input 	 CE;          //enable encrement/decrement function
   input 	 INC;         //increment/decrement tap delays
   input 	 CINVCTRL;    //dynamically inverts clock polarity
   input [4:0] 	 CNTVALUEIN;  //input value from FPGA logic
   input 	 CLKIN;       //clk from I/O clock mux??
   input 	 ODATAIN;     //data from OSERDESE2 output
   output 	 DATAOUT;     //delayed data to pin
   input 	 LDPIPEEN;    //enables pipeline reg??
   output [4:0]  CNTVALUEOUT; //current value for FPGA logic

   
   assign DATAOUT=ODATAIN;
      
endmodule // ODELAYE2
module IDELAYCTRL (/*AUTOARG*/
   // Outputs
   RDY,
   // Inputs
   REFCLK, RST
   );

   output  RDY;    //goes high when delay has been calibrated
   input   REFCLK; //reference clock for setting tap delay
   input   RST;    //reset pulse for setting 
   
   reg 	    RDY;
   
   always @ (posedge REFCLK or posedge RST)
     if(RST)
       RDY <= 1'b0;
     else
       RDY <= 1'b1; //one clock cycle on REFCLK
   
endmodule // IDELAYCTRL
module IOBUFDS_DCIEN (O, IO, IOB, DCITERMDISABLE, I, IBUFDISABLE, T);

`ifdef XIL_TIMING
    parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
    parameter DIFF_TERM = "FALSE";
    parameter DQS_BIAS = "FALSE";
    parameter IBUF_LOW_PWR = "TRUE";
    parameter IOSTANDARD = "DEFAULT";
    parameter SIM_DEVICE = "7SERIES";
    parameter SLEW = "SLOW";
    parameter USE_IBUFDISABLE = "TRUE";

   localparam MODULE_NAME = "IOBUFDS_DCIEN";


    output O;
    inout  IO;
    inout  IOB;
    input  DCITERMDISABLE;
    input  I;
    input  IBUFDISABLE;
    input  T;

   

endmodule
module IOBUF_INTERMDISABLE (O, IO, I, IBUFDISABLE, INTERMDISABLE, T);

    parameter integer DRIVE = 12;
    parameter IBUF_LOW_PWR = "TRUE";
    parameter IOSTANDARD = "DEFAULT";
    parameter SIM_DEVICE = "7SERIES";
    parameter SLEW = "SLOW";
    parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
    parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING

    output O;
    inout  IO;
    input  I;
    input  IBUFDISABLE;
    input  INTERMDISABLE;
    input  T;

endmodule
module OBUF (/*AUTOARG*/
   // Outputs
   O,
   // Inputs
   I
   );

    parameter CAPACITANCE   = "DONT_CARE";
    parameter integer DRIVE = 12;
    parameter IOSTANDARD    = "DEFAULT";
`ifdef XIL_TIMING
    parameter LOC = " UNPLACED";
`endif
    parameter SLEW = "SLOW";
   
   output 	      O;
   input 	      I;
   
   wire 	      GTS = 1'b0;  //Note, uses globals, ugly! 

   bufif0 B1 (O, I, GTS);
    
endmodule
module OBUFT (O, I, T);

   parameter CAPACITANCE   = "DONT_CARE";
   parameter integer DRIVE = 12;
   parameter IOSTANDARD    = "DEFAULT";
   parameter SLEW          = "FAST";
   
   output 	      O;
   input 	      I, T;

   assign O = T ? 1'bz : I;
   
endmodule
module BUFR (/*AUTOARG*/
   // Outputs
   O,
   // Inputs
   I, CE, CLR
   );

   parameter BUFR_DIVIDE=4;
   parameter SIM_DEVICE=0;

   input I;   //clock input
   input CE;  //async output clock enable
   input CLR; //async clear for divider logic
   output O;  //clock output

   //assign O=I & CE & ~CLR;

   //TODO: need to paraemtrize this!!!   
   clock_divider clock_divider (
				// Outputs
				.clkout		(O),
				// Inputs
				.clkin		(I),
				.divcfg		(4'b0010),//div4
				.reset		(CLR)
				);
   
   
endmodule // IBUFDS
module OBUFDS (/*AUTOARG*/
   // Outputs
   O, OB,
   // Inputs
   I
   );

    parameter CAPACITANCE = "DONT_CARE";
    parameter IOSTANDARD = "DEFAULT";
    parameter SLEW = "SLOW";
    
   input  I;    
   output O, OB;


   assign O  = I;
   assign OB = ~I;

endmodule // OBUFDS
module OBUFTDS (/*AUTOARG*/
   // Outputs
   O, OB,
   // Inputs
   I, T
   );

   parameter IOSTANDARD=0;
   parameter SLEW=0;
   
   input I;    //input
   input T;    //tristate signal
   output O;   //output
   output OB;  //output_bar

   assign O  = T ? 1'bz : I;
   assign OB = T ? 1'bz : ~I;
   
   
endmodule // OBUFTDS
module BUF (O, I);


`ifdef XIL_TIMING

    parameter LOC = "UNPLACED";

`endif

    output O;
    input I;
    
    buf B1 (O, I);

endmodule
module IBUFDS (/*AUTOARG*/
   // Outputs
   O,
   // Inputs
   I, IB
   );

   parameter DIFF_TERM=0;
   parameter IOSTANDARD=0;

   input I;
   input IB;
   output O;

   assign O = I & ~IB;
   
endmodule // IBUFDS
module IBUFDS_IBUFDISABLE_INT (O, I, IB, IBUFDISABLE);

`ifdef XIL_TIMING
  parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
  parameter DIFF_TERM = "FALSE";
  parameter DQS_BIAS = "FALSE";
  parameter IBUF_LOW_PWR = "TRUE";
  parameter IOSTANDARD = "DEFAULT";
  parameter USE_IBUFDISABLE = "TRUE";

  localparam MODULE_NAME = "IBUFDS_IBUFDISABLE_INT";


    output O;

    input  I;
    input  IB;
    input  IBUFDISABLE;

endmodule
module IDELAYE2_FINEDELAY (
  CNTVALUEOUT,
  DATAOUT,

  C,
  CE,
  CINVCTRL,
  CNTVALUEIN,
  DATAIN,
  IDATAIN,
  IFDLY,
  INC,
  LD,
  LDPIPEEN,
  REGRST
);

    parameter CINVCTRL_SEL = "FALSE";
    parameter DELAY_SRC = "IDATAIN";
    parameter FINEDELAY = "BYPASS";
    parameter HIGH_PERFORMANCE_MODE    = "FALSE";
    parameter IDELAY_TYPE  = "FIXED";
    parameter integer IDELAY_VALUE = 0;
    parameter [0:0] IS_C_INVERTED = 1'b0;
    parameter [0:0] IS_DATAIN_INVERTED = 1'b0;
    parameter [0:0] IS_IDATAIN_INVERTED = 1'b0;
    parameter PIPE_SEL = "FALSE";
    parameter real REFCLK_FREQUENCY = 200.0;
    parameter SIGNAL_PATTERN    = "DATA";


`ifdef XIL_TIMING
    parameter LOC = "UNPLACED";
    parameter integer SIM_DELAY_D = 0;
    localparam DELAY_D = (IDELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0;
`endif // ifdef XIL_TIMING

`ifndef XIL_TIMING
    integer DELAY_D=0;
`endif // ifndef XIL_TIMING

    output [4:0] CNTVALUEOUT;
    output DATAOUT;

    input C;
    input CE;
    input CINVCTRL;
    input [4:0] CNTVALUEIN;
    input DATAIN;
    input IDATAIN;
    input [2:0] IFDLY;
    input INC;
    input LD;
    input LDPIPEEN;
    input REGRST;


endmodule // IDELAYE2_FINEDELAY
module oh_pads_corner
  (//feed through signals
   inout 	       vddio, // io supply
   inout 	       vssio, // io ground
   inout 	       vdd, // core supply
   inout 	       vss // common ground
   );

   asic_iocorner i0 (
     .vddio,
     .vssio,
     .vdd,
     .vss
   );
  
endmodule // oh_pads_corner
module oh_pads_gpio 
  #(parameter NGPIO  =  8,   // total IO signal pads
    parameter NVDDIO =  8,   // total IO supply pads
    parameter NVSSIO =  8,   // total IO ground pads
    parameter DIR    = "NO"  // "NO", "SO", "EA", "WE"
    )
   (//pad
    inout [NGPIO-1:0] 	pad, // pad
    //feed through signals
    inout 		vddio, // io supply
    inout 		vssio, // io ground
    inout 		vdd, // core supply
    inout 		vss, // common ground
    inout 		poc, // power-on-ctrl
    //core facing signals
    input [NGPIO-1:0] 	dout, // data to drive to pad
    output [NGPIO-1:0] 	din, // data from pad
    input [NGPIO-1:0] 	oen, // output enable (bar)
    input [NGPIO-1:0] 	ie, // input enable
    input [NGPIO*8-1:0] cfg // io config
    );
   
   //########################################################
   //# GPIO PINS
   //########################################################
   
   genvar 	     i;   
   generate
      for(i=0;i<NGPIO;i=i+1)
	begin : g00
`ifdef CFG_ASIC
	   asic_iobuf #(.DIR(DIR))
	   dpad (// Outputs
		 .out	   (din[i]),
		 // Inouts
		 .poc	  (poc),
		 .vdd	  (vdd),
		 .vss	  (vss),
		 .vddio   (vddio),
		 .vssio   (vssio),
		 .pad	  (pad[i]),
		 // Inputs
		 .pe	  (cfg[8*i]),
		 .ie	  (ie[i]),
		 .i	  (dout[i]),
		 .oen	  (oen[i]),
		 .ps	  (cfg[8*i+1]),
		 .sl	  (cfg[8*i+2]),
		 .ds      (cfg[(8*i+4)+:4]));
`else
	   assign din[i] = pad[i] & ie[i];
	   assign pad[i] = ~oen ? dout[i] : 1'bz;
`endif
	end	   
   endgenerate
   
   //########################################################
   //# IO SUPPLY PINS
   //########################################################
`ifdef CFG_ASIC
   generate
      for(i=0;i<NVDDIO;i=i+1) 
	begin : g10
	   //VDDIO
	   asic_iosupply #(.DIR(DIR))
	   ivddio (.vdd     (vdd),
		   .vss     (vss),
		   .vddio   (vddio),
		   .vssio   (vssio),
		   .poc     (poc));
	end      
   endgenerate
`endif

   //########################################################
   //# IO GROUND PINS
   //########################################################

`ifdef CFG_ASIC   
   generate
      for(i=0;i<NVSSIO;i=i+1) 
	begin : g10
	   //VSSIO
	   asic_ioground #(.DIR(DIR))
	   ivssio (.vdd     (vdd),
		   .vss     (vss),
		   .vddio   (vddio),
		   .vssio   (vssio),
		   .poc     (poc));
	end
   endgenerate
`endif
   
endmodule // io_pads_gpio
module axislave_stub (/*AUTOARG*/
   // Outputs
   s_axi_arready, s_axi_awready, s_axi_bid, s_axi_bresp, s_axi_bvalid,
   s_axi_rid, s_axi_rdata, s_axi_rlast, s_axi_rresp, s_axi_rvalid,
   s_axi_wready,
   // Inputs
   s_axi_aclk, s_axi_aresetn, s_axi_arid, s_axi_araddr, s_axi_arburst,
   s_axi_arcache, s_axi_arlock, s_axi_arlen, s_axi_arprot,
   s_axi_arqos, s_axi_arsize, s_axi_arvalid, s_axi_awid, s_axi_awaddr,
   s_axi_awburst, s_axi_awcache, s_axi_awlock, s_axi_awlen,
   s_axi_awprot, s_axi_awqos, s_axi_awsize, s_axi_awvalid,
   s_axi_bready, s_axi_rready, s_axi_wid, s_axi_wdata, s_axi_wlast,
   s_axi_wstrb, s_axi_wvalid
   );

   parameter         S_IDW               = 12;
   
   /*****************************/
   /*AXI slave interface        */
   /*****************************/  
   //Clock and reset
   input 	  s_axi_aclk;
   input 	  s_axi_aresetn;
   
   //Read address channel
   input [S_IDW-1:0] s_axi_arid;    //write address ID
   input [31:0]    s_axi_araddr;
   input [1:0] 	   s_axi_arburst;
   input [3:0] 	   s_axi_arcache;
   input  	   s_axi_arlock;
   input [7:0] 	   s_axi_arlen;
   input [2:0] 	   s_axi_arprot;
   input [3:0] 	   s_axi_arqos;
   output 	   s_axi_arready;
   input [2:0] 	   s_axi_arsize;
   input 	   s_axi_arvalid;
   
   //Write address channel
   input [S_IDW-1:0] s_axi_awid;    //write address ID
   input [31:0]    s_axi_awaddr;
   input [1:0] 	   s_axi_awburst;
   input [3:0] 	   s_axi_awcache;
   input  	   s_axi_awlock;
   input [7:0] 	   s_axi_awlen;
   input [2:0] 	   s_axi_awprot;
   input [3:0] 	   s_axi_awqos;   
   input [2:0] 	   s_axi_awsize;
   input 	   s_axi_awvalid;
   output 	   s_axi_awready;
   
   //Buffered write response channel
   output [S_IDW-1:0] s_axi_bid;    //write address ID
   output [1:0]     s_axi_bresp;
   output 	    s_axi_bvalid;
   input 	    s_axi_bready;
   
   //Read channel
   output [S_IDW-1:0] s_axi_rid;    //write address ID
   output [31:0]      s_axi_rdata;
   output 	      s_axi_rlast;   
   output [1:0]       s_axi_rresp;
   output 	      s_axi_rvalid;
   input 	      s_axi_rready;

   //Write channel
   input [S_IDW-1:0]  s_axi_wid;    //write address ID
   input [31:0]       s_axi_wdata;
   input 	      s_axi_wlast;   
   input [3:0] 	      s_axi_wstrb;
   input 	      s_axi_wvalid;
   output 	      s_axi_wready;

   //read address chanel
   assign s_axi_arready        = 'b0;   

   //write address channel
   assign s_axi_awready        = 'b0;

   //buffered write response
   assign s_axi_bid[S_IDW-1:0] = 'b0;
   assign s_axi_bresp[1:0]     = 'b0;
   
   //read channel
   assign s_axi_rid[S_IDW-1:0] = 'b0;
   assign s_axi_rdata[31:0]    = 'b0;
   assign s_axi_rlast          = 'b0;
   assign s_axi_rresp[1:0]     = 'b0;
   assign s_axi_rvalid         = 'b0;

   //write channel
   assign s_axi_wready         = 'b0;
   
   
endmodule // saxi_tieoff
module spi_slave #( parameter UREGS = 13,  // number of spi slave regs   
		    parameter AW    = 32,  // addresss width
		    parameter PW    = 104 // packet width
		    )
   (
    //clk,reset, cfg
    input 	    clk, // core clock
    input 	    nreset, // async active low reset
    input 	    hw_en, // block enbale pin   
    output [511:0]  spi_regs, // all registers for control
    output 	    spi_irq, // interrupt
    //IO interface
    input 	    sclk, // spi clock
    input 	    mosi, // slave input
    input 	    ss, // slave select
    output 	    miso, // slave output
    // read request to core
    output 	    access_out, // valid transaction
    output [PW-1:0] packet_out, // data to core (from spi port)
    input 	    wait_in, // pushback from core (not implemented)
    // return from core
    input 	    access_in, // read response from core
    input [PW-1:0]  packet_in, // read response packet from core
    output 	    wait_out        // pushback (not used)
    );
   
   //###############
   //# LOCAL WIRES
   //###############
   /*AUTOINPUT*/
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire			cpha;			// From spi_slave_regs of spi_slave_regs.v
   wire			cpol;			// From spi_slave_regs of spi_slave_regs.v
   wire			irq_en;			// From spi_slave_regs of spi_slave_regs.v
   wire			lsbfirst;		// From spi_slave_regs of spi_slave_regs.v
   wire [5:0]		spi_addr;		// From spi_slave_io of spi_slave_io.v
   wire			spi_clk;		// From spi_slave_io of spi_slave_io.v
   wire			spi_en;			// From spi_slave_regs of spi_slave_regs.v
   wire [7:0]		spi_rdata;		// From spi_slave_regs of spi_slave_regs.v, ...
   wire [7:0]		spi_wdata;		// From spi_slave_io of spi_slave_io.v
   wire			spi_write;		// From spi_slave_io of spi_slave_io.v
   // End of automatics
   
   spi_slave_regs #(.AW(AW),
		    .PW(PW),
		    .UREGS(UREGS))
   spi_slave_regs (/*AUTOINST*/
		   // Outputs
		   .spi_rdata		(spi_rdata[7:0]),
		   .spi_en		(spi_en),
		   .cpol		(cpol),
		   .cpha		(cpha),
		   .lsbfirst		(lsbfirst),
		   .irq_en		(irq_en),
		   .spi_regs		(spi_regs[511:0]),
		   .wait_out		(wait_out),
		   // Inputs
		   .clk			(clk),
		   .nreset		(nreset),
		   .hw_en		(hw_en),
		   .spi_clk		(spi_clk),
		   .spi_wdata		(spi_wdata[7:0]),
		   .spi_write		(spi_write),
		   .spi_addr		(spi_addr[5:0]),
		   .access_out		(access_out),
		   .access_in		(access_in),
		   .packet_in		(packet_in[PW-1:0]));
   

   spi_slave_io #(.PW(PW))
   spi_slave_io (/*AUTOINST*/
		 // Outputs
		 .miso			(miso),
		 .spi_clk		(spi_clk),
		 .spi_write		(spi_write),
		 .spi_addr		(spi_addr[5:0]),
		 .spi_wdata		(spi_wdata[7:0]),
		 .spi_rdata		(spi_rdata[7:0]),
		 .access_out		(access_out),
		 .packet_out		(packet_out[PW-1:0]),
		 // Inputs
		 .sclk			(sclk),
		 .mosi			(mosi),
		 .ss			(ss),
		 .spi_en		(spi_en),
		 .cpol			(cpol),
		 .cpha			(cpha),
		 .lsbfirst		(lsbfirst),
		 .clk			(clk),
		 .nreset		(nreset),
		 .wait_in		(wait_in));
   
   
endmodule // spi_slave
module asic_oai22 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  b0,
    input  b1,
    output z
    );

   assign z = ~((a0 | a1) & (b0 | b1));

endmodule
module asic_muxi3 #(parameter PROP = "DEFAULT")   (
    input  d0,
    input  d1,
    input  d2,
    input  s0,
    input  s1,
    output z
    );

   assign z = ~((d0 & ~s0 & ~s1) |
		(d1 & s0  & ~s1) |
		(d2 & s1));

endmodule
module asic_aoi311 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  a2,
    input  b0,
    input  c0,
    output z
    );

   assign z = ~((a0 & a1 & a2) | b0 | c0);

endmodule
module asic_ao221 #(parameter PROP = "DEFAULT")  (
   input  a0,
   input  a1,
   input  b0,
   input  b1,
   input  c0,
   output z
   );

   assign z = (a0 & a1) | (b0 & b1) | (c0);

endmodule
module asic_footer #(parameter PROP = "DEFAULT")   (
    input  nsleep, // 0 = disabled ground
    input  vssin,  // input supply
    output vssout  // gated output supply
    );

   // Primitive Device
   nmos m0 (vddout, vddin, nsleep); //d,s,g

endmodule
module asic_aoi221 #(parameter PROP = "DEFAULT")  (
   input  a0,
   input  a1,
   input  b0,
   input  b1,
   input  c0,
   output z
   );

   assign z = ~((a0 & a1) | (b0 & b1) | c0);

endmodule
module asic_oa211 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  b0,
    input  c0,
    output z
    );

   assign z = (a0 | a1) & b0 & c0;

endmodule
module asic_oa32 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  a2,
    input  b0,
    input  b1,
    output z
    );

   assign z = (a0 | a1 | a2) & (b0 | b1);

endmodule
module asic_oa311 #(parameter PROP = "DEFAULT")   (
    input  a0,
    input  a1,
    input  a2,
    input  b0,
    input  c0,
    output z
    );

   assign z = (a0 | a1 | a2) & b0 & c0;

endmodule
module asic_ao32 #(parameter PROP = "DEFAULT")  (
   input  a0,
   input  a1,
   input  a2,
   input  b0,
   input  b1,
   output z
   );

   assign z = (a0 & a1 & a2) | (b0 & b1);

endmodule