dakies/OSS_Verilog huggingface dataset:
module c3aibadapt_cmn_shadow_status_regs 
#(
   parameter DATA_WIDTH    = 16  // Data width
 )
(
input  wire                                 rst_n,         // reset
input  wire                                 clk,           // clock
input  wire [DATA_WIDTH-1:0]                stat_data_in,  // status data input
input  wire                                 write_en,      // write data enable from DPRIO

output wire                                 write_en_ack,  // write data enable acknowlege to DPRIO
output reg  [DATA_WIDTH-1:0]                stat_data_out  // status data output

);

wire   write_en_sync;

// Bit sync for write_en
// hd_dpcmn_bitsync2 
c3lib_bitsync
  #(
  .SRC_DATA_FREQ_MHZ    (500),    // Source data freq
  .DST_CLK_FREQ_MHZ     (1000),   // Dest clock freq
  .DWIDTH               (1),      // Sync Data input
  .RESET_VAL            (0)  // Reset value
  )
  write_en_sync_1 (
   .clk     (clk),           // read clock
   .rst_n   (rst_n),         // async reset for read clock domain
   .data_in (write_en),      // data in
   .data_out(write_en_sync)  // data out
  );

// Write_en acknowlege
assign write_en_ack = write_en_sync;

// Registering data_in with write_en
always @(negedge rst_n or posedge clk)
  if (rst_n == 1'b0)
    begin
      stat_data_out   <= {DATA_WIDTH{1'b0}};
    end
  else if (write_en_sync == 1'b1)
    begin      
      stat_data_out <= stat_data_in;
    end


endmodule
module c3aibadapt_cmn_parity_checker
    #(
	parameter WIDTH = 'd0   
    )   
    (
        output  reg			parity_error,
	input	wire			clk,
	input	wire			rst_n,
        input   wire [WIDTH-1:0]    	data,
	input	wire			parity_checker_ena,
	input	wire			parity_received
    );

	wire	parity_calculated;

	assign parity_calculated = ^data[WIDTH-1:0];

        always @(negedge rst_n or posedge clk)
        begin
                if (~rst_n)
                begin
			parity_error <= 1'b0;
                end
                else
                begin
                	parity_error <= parity_error || ( (parity_calculated != parity_received) && parity_checker_ena) ;
                end
        end

endmodule // c3aibadapt_cmn_parity_checker
module c3aibadapt_cmn_cp_dist_pair
  #(
    parameter ASYNC_RESET_VAL = 'd0,   // Asynchronous reset value
    parameter WIDTH         = 'd1   // Control width
    )
    (
    input  wire                clk,                        // clock 
    input  wire                rst_n,                      // async reset
    input  wire                srst_n,                   // sync reset
    input wire                 data_enable,                // data enable / data valid
    input  wire [WIDTH-1:0]    master_in,                  // master control signal
    input  wire [WIDTH-1:0]    us_in,                  // CP distributed signal in up
    input  wire [WIDTH-1:0]    ds_in,                 // CP distributed signal in dwn
    input  wire                r_us_master,            // CRAM to control master or distributed up
    input  wire                r_ds_master,           // CRAM to control master or distributed dwn
    input  wire                r_us_bypass_pipeln,     // CRAM combo or registered up
    input  wire                r_ds_bypass_pipeln,    // CRAM combo or registered dwn
    output  wire [WIDTH-1:0]   us_out,                 // CP distributed signal out up
    output  wire [WIDTH-1:0]   ds_out,                // CP distributed signal out dwn
    output  wire [WIDTH-1:0]   ds_tap,                // CP output for this channel dwn 
    output  wire [WIDTH-1:0]   us_tap                  // CP output for this channel up
     );

   c3aibadapt_cmn_cp_dist
     #(
       .ASYNC_RESET_VAL (ASYNC_RESET_VAL),
       .WIDTH         (WIDTH)
       )
       adapt_cmn_cp_dist_dwn
         (
          .clk                  (clk),
          .rst_n                (rst_n), 
          .srst_n               (srst_n), 
          .data_enable          (data_enable),
          .master_in            (master_in),
          .dist_in              (us_in),
          .r_dist_master        (r_ds_master),
          .r_dist_bypass_pipeln (r_ds_bypass_pipeln),
          .dist_out             (ds_out),
          .dist_tap             (ds_tap)
          );

   c3aibadapt_cmn_cp_dist
     #(
       .ASYNC_RESET_VAL (ASYNC_RESET_VAL),
       .WIDTH         (WIDTH)
       )
       adapt_cmn_cp_dist_up
         (
          .clk                  (clk),
          .rst_n                (rst_n),
          .srst_n               (srst_n), 
          .data_enable          (data_enable),
          .master_in            (master_in),
          .dist_in              (ds_in),
          .r_dist_master        (r_us_master),
          .r_dist_bypass_pipeln (r_us_bypass_pipeln),
          .dist_out             (us_out),
          .dist_tap             (us_tap)
          );
   
   
endmodule // c3aibadapt_cmn_cp_dist_pair
module c3aibadapt_cmn_clkgate
(
	input	wire		cp,
	input	wire		e,
	input	wire		te,
	output	wire		q
);

	wire	clk;
	wire	clk_n;
	wire	clken;
	reg	latch_clken;

	assign clk = cp;
	assign clk_n = ~cp;
	assign clken = e || te;

        always @(clk_n or clken)
        begin
		if (clk_n)
                begin
                        latch_clken <= clken;
                end
        end

	assign q = clk & latch_clken;

endmodule // c3aibadapt_cmn_clkgate
module c3aibadapt_cmn_clkinv
(
        output  wire    ZN,
        input   wire    I
);

	assign ZN = ~I;

endmodule // c3aibadapt_cmn_clkinv
module c3aibadapt_avmmrst_ctl
(
	input	wire		csr_rdy_dly_in,
	input	wire		avmm_clock_reset_rx_osc_clk,
	input	wire		avmm_clock_reset_tx_osc_clk,
	input	wire		avmm_clock_reset_avmm_clk,
	input	wire		r_avmm_free_run_div_clk,
	input	wire		dft_adpt_rst,
	input	wire		scan_rst_n,
	input	wire		scan_mode_n,
	output	wire		avmm_reset_rx_osc_clk_rst_n,
	output	wire		avmm_reset_rx_osc_clk_for_clkdiv_rst_n,
	output	wire		avmm_reset_tx_osc_clk_rst_n,
	output	wire		avmm_reset_avmm_rst_n
);

	wire		int_avmm_hrd_rst_n;
	wire            int_div_clk_rst_n_bypass;
        wire            int_div_clk_scan_mode_n;

assign int_avmm_hrd_rst_n = (scan_mode_n & ~dft_adpt_rst & csr_rdy_dly_in) | (~scan_mode_n & scan_rst_n);

// hd_dpcmn_rst_n_sync hd_dpcmn_rst_n_sync_rx_osc_clk
c3lib_rstsync #(.RESET_VAL(0), .DST_CLK_FREQ_MHZ(1000))
  rst_n_sync_rx_osc_clk 
  (
  .rst_n(int_avmm_hrd_rst_n),
  .rst_n_bypass(scan_rst_n),
  .clk (avmm_clock_reset_rx_osc_clk),
  .scan_mode_n(scan_mode_n),
  .rst_n_sync(avmm_reset_rx_osc_clk_rst_n)
  );

c3lib_rstsync #(.RESET_VAL(0), .DST_CLK_FREQ_MHZ(1000))
  rst_n_sync_tx_osc_clk 
  (
  .rst_n(int_avmm_hrd_rst_n),
  .rst_n_bypass(scan_rst_n),
  .clk (avmm_clock_reset_tx_osc_clk),
  .scan_mode_n(scan_mode_n),
  .rst_n_sync(avmm_reset_tx_osc_clk_rst_n)
  );

c3lib_rstsync #(.RESET_VAL(0), .DST_CLK_FREQ_MHZ(200))
  rst_n_sync_avmm_clk
  (
  .rst_n(int_avmm_hrd_rst_n),
  .rst_n_bypass(scan_rst_n),
  .clk (avmm_clock_reset_avmm_clk),
  .scan_mode_n(scan_mode_n),
  .rst_n_sync(avmm_reset_avmm_rst_n)
  );

assign int_div_clk_rst_n_bypass = (scan_mode_n | scan_rst_n);
assign int_div_clk_scan_mode_n = (scan_mode_n & ~r_avmm_free_run_div_clk);

c3lib_rstsync #(.RESET_VAL(0), .DST_CLK_FREQ_MHZ(1000))
  rst_n_sync_rx_osc_clk_for_clkdiv 
  (
  .rst_n(int_avmm_hrd_rst_n),
  .rst_n_bypass(int_div_clk_rst_n_bypass),
  .clk (avmm_clock_reset_rx_osc_clk),
  .scan_mode_n(int_div_clk_scan_mode_n),
  .rst_n_sync(avmm_reset_rx_osc_clk_for_clkdiv_rst_n)
  );

	//assign avmm_reset_rx_osc_clk_for_clkdiv_rst_n = (r_avmm_free_run_div_clk) ? 1'b1 : avmm_reset_rx_osc_clk_rst_n;

endmodule // c3aibadapt_avmmrst_ctl
module c3aibadapt_avmm2_config
(
input   wire            avmm_clock_dprio_clk, 
input   wire            avmm_reset_avmm_rst_n,

// From AVMM Transfer 
input   wire            remote_pld_avmm_read,
input   wire    [8:0]   remote_pld_avmm_reg_addr,	
input   wire            remote_pld_avmm_request,
input   wire            remote_pld_avmm_write,
input   wire    [7:0]   remote_pld_avmm_writedata,	

// From NF HSSI
input   wire            pld_avmm2_busy,	
input   wire    [7:0]   pld_avmm2_readdata,

// To AVMM Transfer
output  wire            remote_pld_avmm_busy,
output  wire    [7:0]   remote_pld_avmm_readdata,	
output  wire            remote_pld_avmm_readdatavalid,

// To NF HSSI
output  wire            pld_avmm2_read,	
output  wire    [8:0]   pld_avmm2_reg_addr,	
output  wire            pld_avmm2_request,
output  wire            pld_avmm2_write,
output  wire    [7:0]   pld_avmm2_writedata
);

reg [3:0] avmm2_readdatavalid_int;

// To/From NF HSSI 
assign pld_avmm2_read     = remote_pld_avmm_read;
assign pld_avmm2_reg_addr = remote_pld_avmm_reg_addr;
assign pld_avmm2_request  = remote_pld_avmm_request;
assign pld_avmm2_write    = remote_pld_avmm_write;
assign pld_avmm2_writedata= remote_pld_avmm_writedata;

assign remote_pld_avmm_busy     = pld_avmm2_busy;

// generate readdatavalid based on received read
always @(negedge avmm_reset_avmm_rst_n or posedge avmm_clock_dprio_clk)
  if (avmm_reset_avmm_rst_n == 1'b0)
    begin
      avmm2_readdatavalid_int <= 4'b0000;
    end
  else
    begin
      avmm2_readdatavalid_int <= {avmm2_readdatavalid_int[2:0],remote_pld_avmm_read};
    end


assign remote_pld_avmm_readdatavalid = !remote_pld_avmm_busy && avmm2_readdatavalid_int[3];
assign remote_pld_avmm_readdata      = pld_avmm2_readdata;
 
endmodule
module c3aibadapt_cfg_rdmux (
  // Output
  output reg  [31:0]  cfg_avmm_rdata,
  output reg          cfg_avmm_rdatavld,
  output reg          cfg_avmm_waitreq,
  output reg          cfg_avmm_slave_read,
  output reg          cfg_avmm_slave_write,

  // Input
  input  wire         cfg_write,
  input  wire         cfg_read,
  input  wire         cfg_rst_n,
  input  wire         r_ifctl_usr_active,
  input  wire [31:0]  chnl_cfg_rdata,
  input  wire         chnl_cfg_rdatavld,
  input  wire         chnl_cfg_waitreq,
  input  wire [31:0]  cfg_only_rdata,
  input  wire         cfg_only_rdatavld,
  input  wire         cfg_only_waitreq,
  input  wire [31:0]  ehip_cfg_rdata,
  input  wire         ehip_cfg_rdatavld,
  input  wire         ehip_cfg_waitreq,
  input  wire [31:0]  adpt_cfg_rdata,
  input  wire         adpt_cfg_rdatavld,
  input  wire         adpt_cfg_waitreq
);

// In config mode (r_ifctl_usr_active = 0), CRSSM can 
// r_ifctl_usr_active is asserted when User has control of AVMM interface.
// r_ifctl_usr_active affects channel-related signals. CRSSM can only access
// config-only space when r_ifctl_usr_active is asserted.
// In this case, CRSSM can only access Config-only space
always @(*) begin
  cfg_avmm_waitreq  = adpt_cfg_waitreq  & ehip_cfg_waitreq  & (r_ifctl_usr_active ? cfg_only_waitreq  : (cfg_only_waitreq  & chnl_cfg_waitreq));
  cfg_avmm_rdatavld = adpt_cfg_rdatavld | ehip_cfg_rdatavld | (r_ifctl_usr_active ? cfg_only_rdatavld : (cfg_only_rdatavld | chnl_cfg_rdatavld));
  cfg_avmm_rdata    = adpt_cfg_rdata    | ehip_cfg_rdata    | (r_ifctl_usr_active ? cfg_only_rdata    : (cfg_only_rdata    | chnl_cfg_rdata));
end

// Scenario1: 
// Assert: one_hot(chnl_cfg_rdatavld, ehip_cfg_rdatavld, adpt_cfg_rdatavld);

// Scenario2:
// helper1 = (chnl_cfg_rdatavld!='0); helper2 =  (chnl_cfg_rdatavld!='0); helper3 =  (adpt_cfg_rdatavld != '0)
// Assert: one_hot (helper1, helper2, helper3);

always @(*) begin
  cfg_avmm_slave_write = cfg_write;
  cfg_avmm_slave_read  = cfg_read;
end

endmodule
module c3aibadapt_avmm2_async
(
input  wire avmm_clock_tx_osc_clk,
input  wire avmm_reset_tx_osc_clk_rst_n,

// From NF HSSI
input  wire pld_pll_cal_done,
input  wire pld_avmm2_busy,

// FRom SR
input  wire avmm2_async_hssi_fabric_ssr_load,

// To SR
output wire [1:0] avmm2_hssi_fabric_ssr_data
);

wire nc_0;
wire nc_1;

c3aibadapt_cmn_async_capture_bit
     #(
       .SYNC_STAGE  (2),
       .RESET_VAL   (0)
       )
      async_pld_pll_cal_done
      (
          .clk      (avmm_clock_tx_osc_clk),
          .rst_n    (avmm_reset_tx_osc_clk_rst_n),
          .data_in  (pld_pll_cal_done),
          .unload   (avmm2_async_hssi_fabric_ssr_load),
          .data_in_sync_out (nc_0),
          .data_out (avmm2_hssi_fabric_ssr_data[0])
      );

c3aibadapt_cmn_async_capture_bit
     #(
       .SYNC_STAGE  (2),
       .RESET_VAL   (1)
       )
      async_pld_avmm2_busy
      (
          .clk      (avmm_clock_tx_osc_clk),
          .rst_n    (avmm_reset_tx_osc_clk_rst_n),
          .data_in  (pld_avmm2_busy),
          .unload   (avmm2_async_hssi_fabric_ssr_load),
          .data_in_sync_out (nc_1),
          .data_out (avmm2_hssi_fabric_ssr_data[1])
      );


endmodule
module c3aibadapt_avmm_async
(
input  wire avmm_clock_hrdrst_tx_osc_clk,
input  wire avmm_reset_hrdrst_tx_osc_clk_rst_n,
input  wire avmm_clock_hrdrst_rx_osc_clk,
input  wire avmm_reset_hrdrst_rx_osc_clk_rst_n,

// From SR
input  wire avmm_async_fabric_hssi_ssr_load,
input  wire avmm_hrdrst_fabric_osc_transfer_en_ssr_data, 
input  wire avmm_async_hssi_fabric_ssr_load,

// From Reset SM
input  wire avmm_hrdrst_hssi_osc_transfer_en,

// To SR
output wire avmm_hrdrst_hssi_osc_transfer_en_ssr_data,

// To Reset SM
output wire avmm_hrdrst_hssi_osc_transfer_en_sync, 
output wire sr_fabric_osc_transfer_en 
);

c3aibadapt_async_update
    #( .AWIDTH       (1),
       .RESET_VAL    (0)
     ) async_avmm_hrdrst_fabric_osc_transfer_en
     ( .clk             (avmm_clock_hrdrst_rx_osc_clk),
       .rst_n           (avmm_reset_hrdrst_rx_osc_clk_rst_n),
       .sr_load         (avmm_async_fabric_hssi_ssr_load),
       .async_data_in   (avmm_hrdrst_fabric_osc_transfer_en_ssr_data),
       .async_data_out  (sr_fabric_osc_transfer_en)
     );

c3aibadapt_cmn_async_capture_bit
     #(
       .SYNC_STAGE  (3),
       .RESET_VAL   (0)
       )
      async_avmm_hrdrst_hssi_osc_transfer_en
      (
          .clk      (avmm_clock_hrdrst_tx_osc_clk),
          .rst_n    (avmm_reset_hrdrst_tx_osc_clk_rst_n),
          .data_in  (avmm_hrdrst_hssi_osc_transfer_en),
          .unload   (avmm_async_hssi_fabric_ssr_load),
          .data_in_sync_out (avmm_hrdrst_hssi_osc_transfer_en_sync),
          .data_out (avmm_hrdrst_hssi_osc_transfer_en_ssr_data)
      );

endmodule
module c3aibadapt_avmmclk_gate
(
	input	wire		cp,
	input	wire		e,
	input	wire		te,
	output	wire		q
);

	wire	clk;
	wire	clk_n;
	wire	clken;
	reg	latch_clken;

	assign clk = cp;
	assign clk_n = ~cp;
	assign clken = e || te;

        always @(clk_n or clken)
        begin
		if (clk_n)
                begin
                        latch_clken <= clken;
                end
        end

	assign q = clk & latch_clken;

endmodule // c3aibadapt_avmmclk_gate
module c3aibadapt_avmm1_async
(
input  wire avmm_clock_tx_osc_clk,
input  wire avmm_reset_tx_osc_clk_rst_n,

// From NF HSSI
input  wire pld_chnl_cal_done,
input  wire pld_avmm1_busy,

// FRom SR
input  wire avmm1_async_hssi_fabric_ssr_load,

// To SR
output wire [1:0] avmm1_hssi_fabric_ssr_data
);


wire nc_0;
wire nc_1;

c3aibadapt_cmn_async_capture_bit
     #(
       .SYNC_STAGE  (2),
       .RESET_VAL   (0)
       )
      async_pld_chnl_cal_done
      (
          .clk      (avmm_clock_tx_osc_clk),
          .rst_n    (avmm_reset_tx_osc_clk_rst_n),
          .data_in  (pld_chnl_cal_done),
          .unload   (avmm1_async_hssi_fabric_ssr_load),
          .data_in_sync_out (nc_0),
          .data_out (avmm1_hssi_fabric_ssr_data[0])
      );


c3aibadapt_cmn_async_capture_bit
     #(
       .SYNC_STAGE  (2),
       .RESET_VAL   (1)
       )
      async_pld_avmm1_busy
      (
          .clk      (avmm_clock_tx_osc_clk),
          .rst_n    (avmm_reset_tx_osc_clk_rst_n),
          .data_in  (pld_avmm1_busy),
          .unload   (avmm1_async_hssi_fabric_ssr_load),
          .data_in_sync_out (nc_1),
          .data_out (avmm1_hssi_fabric_ssr_data[1])
      );


endmodule
module altr_hps_mux41
    (
    input  wire              mux_in0,     // mux in 0
    input  wire              mux_in1,     // mux in 1
    input  wire              mux_in2,     // mux in 1
    input  wire              mux_in3,     // mux in 1
    input  wire [1:0]        mux_sel,     // mux selector
    output wire             mux_out      // mux out
     );

`ifdef ALTR_HPS_INTEL_MACROS_OFF
    assign mux_out = mux_sel[1] ? 
            mux_sel[0] ? mux_in3 : mux_in2 :
            mux_sel[0] ? mux_in1 : mux_in0;
`else
`endif

endmodule // altr_hps_mux41
module altr_hps_cyc_dly
  (
    input wire 				     clk,
    input wire 				     i_rst_n,          
    output reg 				     dly_rst_n			     
   );
   
   parameter DLY  = 'd8;
   // counter size:
   // counter counts from 0 to DLY-1, then saturates. minimum size should cover DLY-1.
   // To be safe, counter size can cover DLY in case there is one run-over. 
   // e.g.: DLY = 2, counter size = 2 (instead of 1). DLY = 3, size = 3 (instead of 2) ; 
   // DLY =3~6, size =3. DLY=7~14, size=4... 
   //    
   parameter CNT_WIDTH = DLY > 'd1022 ? 'd11 :
			 DLY > 'd510 ?  'd10 :
			 DLY > 'd254 ?  'd9 :
			 DLY > 'd126 ? 'd8 :
			 DLY > 'd62 ? 'd7 :
			 DLY > 'd30 ? 'd6 :
			 DLY > 'd14 ? 'd5 :
			 DLY > 'd6 ? 'd4 :
			 DLY > 'd2 ? 'd3 :
			 DLY > 'd1 ? 'd2 :
			 'd1;

`ifdef ALTR_HPS_SIMULATION
initial // check parameters
 begin

  if( DLY > 'd2046)
   begin
    $display("ERROR : %m : DELAY parameter is too big , MAX Value is 2046.");
    $finish;
   end
 
 if( DLY == 'd0)
   begin
    $display("ERROR : %m : DELAY parameter is 0, no need to instantiate this cell.");
    $finish;
   end

 end
`endif

   reg [CNT_WIDTH-1:0]  dly_cntr;
   wire 		cntr_reached = (dly_cntr >= (DLY-'d1));
   
   
   always @(posedge clk or negedge i_rst_n)
     if (!i_rst_n) begin
	/*AUTORESET*/
	// Beginning of autoreset for uninitialized flops
	dly_cntr <= {(1+(CNT_WIDTH-1)){1'b0}};
	dly_rst_n <= 1'h0;
	// End of automatics
     end
     else begin
	dly_cntr <= cntr_reached ? 
		    dly_cntr :
		    dly_cntr + { {CNT_WIDTH-1{1'b0}}, 1'b1 };
	dly_rst_n <= cntr_reached;	
     end

endmodule
module altr_hps_bin2gray (
	 bin_in,
	 gray_out
);

input  [2:0] bin_in;
output [2:0] gray_out;
reg    [2:0] gray_out;

always @(*) 
begin  // 3 bit gray code 
	 case(bin_in)
		  3'b000 : gray_out = 3'b000; 
		  3'b001 : gray_out = 3'b001; 
		  3'b010 : gray_out = 3'b011; 
		  3'b011 : gray_out = 3'b010; 
		  3'b100 : gray_out = 3'b110; 
		  3'b101 : gray_out = 3'b111; 
		  3'b110 : gray_out = 3'b101; 
		  3'b111 : gray_out = 3'b100; 
		  default: gray_out = 3'b000;
	 endcase
end

endmodule
module altr_hps_gtie_generator #(
        parameter TIE_WIDTH = 1,
        parameter [TIE_WIDTH-1:0] TIE_VALUE = 'd0
    ) ( 
        output wire  [TIE_WIDTH-1 : 0] z_out     // output
    );
    genvar i;
    generate for(i = 0; i < TIE_WIDTH; i = i + 1) begin : gtie
        
        if (TIE_VALUE[i] == 1'b1) begin
            // tie high
            altr_hps_gtieh u_gtieh (
               .z_out (z_out[i])
            );                      
        end else begin
            // tie low
            altr_hps_gtiel u_gtiel (
               .z_out (z_out[i])
            );
        
        end // if
      end // for
           
    endgenerate // generate

endmodule // altr_hps_gtie_generator
module altr_hps_latch(
  d,        // Latch input
  q,        // Latch output
  e_n);     // Enable

input d,
      e_n;
output q;

`ifdef ALTR_HPS_INTEL_MACROS_OFF
  reg q;

  always @(e_n or d)
    begin
      if(~e_n)
        q <= d;
    end
`else
`endif

endmodule // altr_hps_latch
module altr_hps_or
    (
    input  wire              or_in1,     // and input 1
    input  wire              or_in2,     // and input 2
    output  wire             or_out      // or output
     );

`ifdef ALTR_HPS_INTEL_MACROS_OFF
    assign or_out = or_in1 | or_in2;
`else
`endif

endmodule // altr_hps_or
module altr_hps_buf (
    input  wire         buf_in,     // clock input
    output wire         buf_out     // clock output
);

`ifdef ALTR_HPS_INTEL_MACROS_OFF
   assign buf_out = buf_in;
`else
`endif

endmodule // altr_hps_ckbuf
module altr_hps_t2_register
    (
    input  wire              clk,      // clock
    input  wire              rst_n,    // async reset
    input  wire              scan_en,   // scan enable
    input  wire              data_in,   // data in
    input  wire              scan_in,   // scan in
    output wire              data_out   // data out
     );

`ifdef ALTR_HPS_INTEL_MACROS_OFF

   reg   dff1;
   
   always @(posedge clk or negedge rst_n)
   begin
      if (!rst_n)
         dff1     <= 1'b0;
      else
         dff1 <= scan_en ? scan_in : data_in;
   end
   assign data_out = dff1;

`else
 
 
 

`endif

endmodule // altr_interface_register
module altr_hps_bitsync4
  #(
    parameter DWIDTH = 1'b1,    // Sync Data input
    //parameter SYNCSTAGE = 4, // Sync stages
    parameter RESET_VAL = 1'b0  // Reset value
    )
    (
    input  wire              clk,     // clock
    input  wire              rst_n,   // async reset
    input  wire [DWIDTH-1:0] data_in, // data in
    output wire [DWIDTH-1:0] data_out // data out
     );

`ifdef ALTR_HPS_INTEL_MACROS_OFF

   // End users may pass in RESET_VAL with a width exceeding 1 bit
   // Evaluate the value first and use 1 bit value
   localparam RESET_VAL_1B = (RESET_VAL == 'd0) ? 1'b0 : 1'b1;

   reg [DWIDTH-1:0]  dff4;
   reg [DWIDTH-1:0]  dff3;
   reg [DWIDTH-1:0]  dff2;
   reg [DWIDTH-1:0]  dff1;

   always @(posedge clk or negedge rst_n)
      if (!rst_n) begin
         dff4     <= {DWIDTH{RESET_VAL_1B}}; 
         dff3     <= {DWIDTH{RESET_VAL_1B}}; 
         dff2     <= {DWIDTH{RESET_VAL_1B}}; 
         dff1     <= {DWIDTH{RESET_VAL_1B}}; 
      end
      else begin
         dff4     <= dff3;
         dff3     <= dff2;
         dff2     <= dff1;
         dff1     <= data_in;
      end

   // data_out has to be a wire since it needs to also hook up to the TSMC cell
   assign data_out = dff4;

`else
`endif

endmodule // altr_hps_bitsync4
module altr_hps_cknor (
    input  wire              nor_in1,     // or input 1
    input  wire              nor_in2,     // or input 2
    output  wire             nor_out      // or output
);

// -------------------
// Port declarations
// -------------------

// -----
// RTL
// -----

`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign nor_out = ~(nor_in1 | nor_in2);

`else


`endif

endmodule
module altr_hps_rstnsync
  (
    input wire 	clk,		// Destination clock of reset to be synced
    input wire 	i_rst_n,        // Asynchronous reset input
    input wire	scan_mode,	// Scan bypass for reset
    output wire sync_rst_n	// Synchronized reset output
   
   );

   reg	first_stg_rst_n;					     
   wire prescan_sync_rst_n;
   
   always @(posedge clk or negedge i_rst_n)
     if (!i_rst_n)
       first_stg_rst_n <= 1'b0;
     else
       first_stg_rst_n <= 1'b1;

   altr_hps_bitsync 
     #(.DWIDTH(1), .RESET_VAL(0)                      ) 
   i_sync_rst_n
     (
      .clk           (clk               ),
      .rst_n         (i_rst_n           ), 
      .data_in       (first_stg_rst_n   ),
      .data_out      (prescan_sync_rst_n) 
      );

   // Added scan bypass mux (Fogbugz #26486)
   altr_hps_mux21 
   	i_rstsync_mux 
	(
		.mux_in0	(prescan_sync_rst_n),
		.mux_in1	(i_rst_n),
		.mux_sel	(scan_mode),
		.mux_out	(sync_rst_n)
	);
      
   endmodule
module altr_hps_bitsync
  #(
    parameter DWIDTH = 1'b1,    // Sync Data input
    //parameter SYNCSTAGE = 2, // Sync stages
    parameter RESET_VAL = 1'b0  // Reset value
    )
    (
    input  wire              clk,     // clock
    input  wire              rst_n,   // async reset
    input  wire [DWIDTH-1:0] data_in, // data in
    output wire [DWIDTH-1:0] data_out // data out
     );

`ifdef ALTR_HPS_INTEL_MACROS_OFF

   // End users may pass in RESET_VAL with a width exceeding 1 bit
   // Evaluate the value first and use 1 bit value
   localparam RESET_VAL_1B = (RESET_VAL == 'd0) ? 1'b0 : 1'b1;

   reg [DWIDTH-1:0]  dff2;
   reg [DWIDTH-1:0]  dff1;

   always @(posedge clk or negedge rst_n)
      if (!rst_n) begin
         dff2     <= {DWIDTH{RESET_VAL_1B}}; 
         dff1     <= {DWIDTH{RESET_VAL_1B}}; 
      end
      else begin
         dff2     <= dff1;
         dff1     <= data_in;
      end

   // data_out has to be a wire since it needs to also hook up to the TSMC cell
   assign data_out = dff2;

`else


`endif

endmodule // altr_hps_bitsync
module altr_hps_gtieh (
    output wire         z_out     // output
);

`ifdef ALTR_HPS_INTEL_MACROS_OFF
   assign z_out = 1'b1;
`else
`endif

endmodule // altr_hps_gtieh
module altr_hps_ckbuf (
    input  wire         ck_in,     // clock input
    output wire         ck_out     // clock output
);

`ifdef ALTR_HPS_INTEL_MACROS_OFF
   assign ck_out = ck_in;
`else
   

`endif

endmodule // altr_hps_ckbuf
module altr_hps_ckor (
    input  wire              or_in1,     // or input 1
    input  wire              or_in2,     // or input 2
    output  wire             or_out      // or output
);

// -------------------
// Port declarations
// -------------------

// -----
// RTL
// -----

wire   or_out_n;

`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign or_out = or_in1 | or_in2;

`else



`endif

endmodule
module altr_hps_ckmux41
    (
    input  wire              clk_0,     // clock 0
    input  wire              clk_1,     // clock 1
    input  wire              clk_2,     // clock 2
    input  wire              clk_3,     // clock 3
    input  wire  [1:0]       clk_sel,   // clock selector
    output wire              clk_o      // clock out
     );

     wire clk_mux_a;
     wire clk_mux_b;
     
`ifdef ALTR_HPS_INTEL_MACROS_OFF
    assign clk_mux_a = clk_sel[0] ? clk_1 : clk_0;
    assign clk_mux_b = clk_sel[0] ? clk_3 : clk_2;
    
    assign clk_o     = clk_sel[1] ? clk_mux_b : clk_mux_a;
`else

`endif

endmodule // altr_hps_ckmux41
module altr_hps_gltchfltr 
          #(parameter RESET_VAL = 'd0)  (  // Reset value

    // src_clk domain signals.
    input                      clk,
    input                      rst_n,

    input wire                 din,           // Async. input
    output reg                 dout_clean     // Synchronous output to clk.
                                              // Glitch free output signal.
	  );

// signals
wire            din_sync;
reg             din_sync_r;
wire            detect_transition;
wire            dout_enable;
reg     [ 2: 0] cntr;


altr_hps_bitsync #(.DWIDTH(1), .RESET_VAL(RESET_VAL)) gltchfltr_sync (
    .clk(clk),
    .rst_n(rst_n),
    .data_in(din),
    .data_out(din_sync)
);

// 2 extra flops
always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin

    din_sync_r <= RESET_VAL;
    dout_clean <= RESET_VAL;

  end else begin

    din_sync_r <= din_sync;

    if (dout_enable) begin
      dout_clean <= din_sync_r;
    end

  end
end

// Transition when bits are not equal (xor)
assign detect_transition = din_sync ^ din_sync_r;

// Enable output flop only when count is equal to 3'b111 and not transition.
assign dout_enable = (cntr == 3'b111) & ~detect_transition;

// 3 bit counter for 8 stable clocks without a transition.
always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin

    cntr <= 3'd0;

  end else begin

    cntr <= detect_transition ? 3'd0: cntr + 3'd1;

  end
end


endmodule
module altr_hps_en_bitsync
#(
     parameter DWIDTH = 1,    // Sync Data input
     parameter RESET_VAL = 0  // Reset value
   )
   (
     input               clk,         // clock
     input               rst_n,       // async reset
     input               clk_en,      // clock enable
     input  [DWIDTH-1:0] data_in,     // data in
     output [DWIDTH-1:0] data_out     // data out
   );

wire clk_o;

altr_hps_clkgate clkgate (
  .clk            (clk),
  .clk_enable_i   (clk_en),
  .clk_o          (clk_o)
);

altr_hps_bitsync #(
  .DWIDTH      (DWIDTH),
  .RESET_VAL   (RESET_VAL)
) bitsync (
  .clk         (clk_o),
  .rst_n       (rst_n),
  .data_in     (data_in),
  .data_out    (data_out)
);

endmodule
module altr_hps_cknand (
    input  wire              nand_in1,     // and input 1
    input  wire              nand_in2,     // and input 2
    output  wire             nand_out      // and output
);

// -------------------
// Port declarations
// -------------------

// -----
// RTL
// -----

`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign nand_out = ~(nand_in1 & nand_in2);

`else


`endif

endmodule
module altr_hps_nor3
    (
    input  wire              nor_in1,     // and input 1
    input  wire              nor_in2,     // and input 2
    input  wire              nor_in3,     // and input 3
    output  wire             nor_out      // and output
     );

`ifdef ALTR_HPS_INTEL_MACROS_OFF
    assign nor_out = ~(nor_in1 | nor_in2 | nor_in3);
`else
 
`endif

endmodule // altr_hps_nor3
module altr_hps_nand4
    (
    input  wire              nand_in1,     // and input 1
    input  wire              nand_in2,     // and input 2
    input  wire              nand_in3,     // and input 3
    input  wire              nand_in4,     // and input 4
    output  wire             nand_out      // and output
     );

`ifdef ALTR_HPS_INTEL_MACROS_OFF
    assign nand_out = ~(nand_in1 & nand_in2 & nand_in3 & nand_in4);
`else

`endif

endmodule // altr_hps_nand2
module altr_hps_en_bitsync4
#(
     parameter DWIDTH = 1,    // Sync Data input
     parameter RESET_VAL = 0  // Reset value
   )
   (
     input               clk,         // clock
     input               rst_n,       // async reset
     input               clk_en,      // clock enable
     input  [DWIDTH-1:0] data_in,     // data in
     output [DWIDTH-1:0] data_out     // data out
   );

wire clk_o;

altr_hps_clkgate clkgate (
  .clk            (clk),
  .clk_enable_i   (clk_en),
  .clk_o          (clk_o)
);

altr_hps_bitsync4 #(
  .DWIDTH      (DWIDTH),
  .RESET_VAL   (RESET_VAL)
) bitsync (
  .clk         (clk_o),
  .rst_n       (rst_n),
  .data_in     (data_in),
  .data_out    (data_out)
);

endmodule
module altr_hps_and
    (
    input  wire              and_in1,     // and input 1
    input  wire              and_in2,     // and input 2
    output  wire             and_out      // and output
     );

`ifdef ALTR_HPS_INTEL_MACROS_OFF
    assign and_out = and_in1 & and_in2;
`else

`endif

endmodule // altr_hps_and
module altr_hps_gray2bin (
	 gray_in,
	 bin_out
);
input  [2:0] gray_in;
output [2:0] bin_out;
reg    [2:0] bin_out;

always @(*) 
begin // gray to binary converting
	 case(gray_in)
		  3'b000: bin_out = 3'b000;
		  3'b001: bin_out = 3'b001;
		  3'b011: bin_out = 3'b010;
		  3'b010: bin_out = 3'b011;
		  3'b110: bin_out = 3'b100;
		  3'b111: bin_out = 3'b101;
		  3'b101: bin_out = 3'b110;
		  3'b100: bin_out = 3'b111;
		  default:bin_out = 3'b000;
	 endcase
end
endmodule
module altr_hps_gltchfltr_vec 
          #(parameter RESET_VAL = 'd0,   // Reset value
            parameter DWIDTH = 'd2,
            parameter COUNT = 'd8,
            parameter RELOAD = 'd1 )  (  

   // src_clk domain signals.
   input                      clk,
   input                      rst_n,

   input wire [DWIDTH-1:0]  din,           // Async. input
   output reg [DWIDTH-1:0]  dout_clean     // Synchronous output to clk.
                                          // Glitch free output signal.
   );

function integer clog2;
   input [31:0] value;  // Input variable
   for (clog2=0; value>0; clog2=clog2+1)
   value = value>>'d1;
endfunction

localparam FULL   = COUNT - 'd1;
localparam CWIDTH = clog2(FULL);

// The reset methodology will follow altr_hps_bitsync
localparam RESET_VAL_1B = (RESET_VAL == 'd0) ? 1'b0 : 1'b1;

// signals
wire [DWIDTH-1:0] din_sync;
reg  [DWIDTH-1:0] din_sync_r;
wire              detect_transition;
wire              dout_enable;
wire              deglitching;
reg  [CWIDTH-1:0] cntr;


altr_hps_bitsync #(.DWIDTH(DWIDTH), .RESET_VAL(RESET_VAL)) gltchfltr_sync (
    .clk(clk),
    .rst_n(rst_n),
    .data_in(din),
    .data_out(din_sync)
);

// 2 extra flops per bit
always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin

    din_sync_r <= {DWIDTH{RESET_VAL_1B}};
    dout_clean <= {DWIDTH{RESET_VAL_1B}};

  end else begin

    din_sync_r <= din_sync;

    if (dout_enable) begin
      dout_clean <= din_sync_r;
    end

  end
end

// Transition when bits are not equal (xor)
assign detect_transition = |(din_sync ^ din_sync_r);

// RELOAD == 1 causes it's behavior to match with altr_hps_gltchfltr
assign deglitching = (RELOAD == 'd1 ) ? 1'b1 : ( |(din_sync ^ dout_clean) );

// Enable output flop only when count is equal to 3'b111 and not transition.
assign dout_enable = (cntr == FULL) & ~detect_transition;

// 3 bit counter for 8 stable clocks without a transition.
always @(posedge clk or negedge rst_n) begin
   if (~rst_n) begin

      cntr <= {CWIDTH{1'b0}};

   end else begin

      // Some seriously long cascaded muxes
      cntr <= deglitching ? ( detect_transition ? {CWIDTH{1'b0}} : (cntr == FULL) ? {CWIDTH{1'b0}} : cntr + {{CWIDTH-1{1'b0}}, 1'b1} ) : {CWIDTH{1'b0}};

      // Here's what it means
      // if (deglitching)  -- it means a new input is sampled and is different from current output
      //    if (detect_transition)  -- 1 pulse signal indicating a change in the synchronized input
      //                            -- detect_transition pulses when a new input is sampled and will also pulse if the input changes again while deglitching
      //       reset counter to zero
      //    else if (counter == FULL)  -- has the counter his FULL count yet? 
      //       reset counter to zero
      //    else
      //       increment the counter
      // else                          -- this "else" matches with "if (deglitching)" 
      //                               -- when deglitching is no longer required - reset the counter to zero
      //    reset counter to zero
            
   end

end

endmodule
module altr_hps_clkgate (
  clk,
  clk_enable_i,
  clk_o
  );

input clk;
input clk_enable_i;

output clk_o;

reg clk_enable_lat;

`ifdef ALTR_HPS_INTEL_MACROS_OFF
always @ (clk or clk_enable_i)
  begin
    if (~clk)
      clk_enable_lat <= clk_enable_i;
  end

assign clk_o = clk & clk_enable_lat;

`else


`endif
endmodule
module altr_hps_nand3
    (
    input  wire              nand_in1,     // and input 1
    input  wire              nand_in2,     // and input 2
    input  wire              nand_in3,     // and input 3
    output  wire             nand_out      // and output
     );

`ifdef ALTR_HPS_INTEL_MACROS_OFF
    assign nand_out = ~(nand_in1 & nand_in2 & nand_in3);
`else

`endif

endmodule // altr_hps_nand3
module altr_hps_ckand_gate (
    input  wire              and_clk,     // and input 1
    input  wire              and_en,     // and input 2
    output  wire             and_out      // and output
);

// -------------------
// Port declarations
// -------------------

// -----
// RTL
// -----

`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign and_out = and_clk & and_en;

`else



`endif

endmodule
module altr_hps_bitsync_generator #( parameter DWIDTH = 1, parameter [DWIDTH-1:0] RESET_VAL = 'd0 ) 
(
	input wire clk,				//clock
	input wire rst_n,			//async reset
	input wire [DWIDTH-1:0] data_in,	//data in
        output wire [DWIDTH-1:0] data_out	//data out
);

genvar i;

generate 
 for(i = 0; i < DWIDTH; i=i+1)
 begin: bit_sync_i
	if(RESET_VAL[i] == 1'b0)
	 begin
		altr_hps_bitsync #(.DWIDTH(1), .RESET_VAL(1'b0) ) bitsync_clr_inst (
			.clk(clk),
			.rst_n(rst_n),
			.data_in(data_in[i]),
			.data_out(data_out[i])
		);
	 end
	else
	 begin
		altr_hps_bitsync #(.DWIDTH(1), .RESET_VAL(1'b1) ) bitsync_pst_inst (
			.clk(clk),
			.rst_n(rst_n),
			.data_in(data_in[i]),
			.data_out(data_out[i])
		);
	 end
 end //end for     
endgenerate // endgenerate

endmodule // altr_hps_bitsync_generator
module altr_hps_nor2
    (
    input  wire              nor_in1,     // and input 1
    input  wire              nor_in2,     // and input 2
    output  wire             nor_out      // and output
     );

`ifdef ALTR_HPS_INTEL_MACROS_OFF
    assign nor_out = ~(nor_in1 | nor_in2);
`else
`endif

endmodule // altr_hps_nor2
module altr_hps_mux21
    (
    input  wire              mux_in0,     // mux in 0
    input  wire              mux_in1,     // mux in 1
    input  wire              mux_sel,     // mux selector
    output  wire             mux_out      // mux out
     );

`ifdef ALTR_HPS_INTEL_MACROS_OFF
    assign mux_out = mux_sel ? mux_in1 : mux_in0;
`else

`endif

endmodule // altr_hps_mux21
module altr_hps_te_clkgate (
  clk,
  clk_enable_i,
  test_enable_i,
  clk_o
  );

input clk;
input clk_enable_i;
input test_enable_i;

output clk_o;

reg clk_enable_lat;

`ifdef ALTR_HPS_INTEL_MACROS_OFF
always @ (clk or clk_enable_i)
  begin
    if (~clk)
      clk_enable_lat <= clk_enable_i;
  end

assign clk_o = clk & clk_enable_lat;

`else

`endif
endmodule
module altr_hps_ckmux32to1
    (
    input  wire [31:0]       clk_i, 

    input  wire  [4:0]       clk_sel,   // clock selector
    output wire              clk_o      // clock out
     );


`ifdef ALTR_HPS_INTEL_MACROS_OFF

  reg clk_o_reg;

  always @*
  begin : clk_sel_mux
    case(clk_sel[4:0])
      5'b00000: clk_o_reg = clk_i[0];
      5'b00001: clk_o_reg = clk_i[1];
      5'b00010: clk_o_reg = clk_i[2];
      5'b00011: clk_o_reg = clk_i[3];
      5'b00100: clk_o_reg = clk_i[4];
      5'b00101: clk_o_reg = clk_i[5];
      5'b00110: clk_o_reg = clk_i[6];
      5'b00111: clk_o_reg = clk_i[7];
      5'b01000: clk_o_reg = clk_i[8];
      5'b01001: clk_o_reg = clk_i[9];
      5'b01010: clk_o_reg = clk_i[10];
      5'b01011: clk_o_reg = clk_i[11];
      5'b01100: clk_o_reg = clk_i[12];
      5'b01101: clk_o_reg = clk_i[13];
      5'b01110: clk_o_reg = clk_i[14];
      5'b01111: clk_o_reg = clk_i[15];
      5'b10000: clk_o_reg = clk_i[16];
      5'b10001: clk_o_reg = clk_i[17];
      5'b10010: clk_o_reg = clk_i[18];
      5'b10011: clk_o_reg = clk_i[19];
      5'b10100: clk_o_reg = clk_i[20];
      5'b10101: clk_o_reg = clk_i[21];
      5'b10110: clk_o_reg = clk_i[22];
      5'b10111: clk_o_reg = clk_i[23];
      5'b11000: clk_o_reg = clk_i[24];
      5'b11001: clk_o_reg = clk_i[25];
      5'b11010: clk_o_reg = clk_i[26];
      5'b11011: clk_o_reg = clk_i[27];
      5'b11100: clk_o_reg = clk_i[28];
      5'b11101: clk_o_reg = clk_i[29];
      5'b11110: clk_o_reg = clk_i[30];
      5'b11111: clk_o_reg = clk_i[31];
      default: clk_o_reg = 1'bx;
    endcase
  end

  assign clk_o = clk_o_reg;

`else

`endif

endmodule // altr_hps_ckmux32to1
module altr_hps_sync_clr
#(parameter DWIDTH='d1)
(
  input clk,				//main clk signal
  input rst_n,				//main reset signal
  input clr,				//active high clear signal (expected this clear signal to be quasi-static)
  input [DWIDTH-1:0] data_in,		//data in
  output [DWIDTH-1:0] data_out		//data out
);

`ifdef ALTR_HPS_INTEL_MACROS_OFF

reg [DWIDTH-1:0] dff1;
reg [DWIDTH-1:0] dff2;

always @(posedge clk or negedge rst_n)
begin
	if(!rst_n) 
	begin
		dff1 <= {DWIDTH{1'b0}};
		dff2 <= {DWIDTH{1'b0}};
	end
	else
	begin
		dff1 <= data_in & ~clr;
		dff2 <= dff1 & ~clr;	
	end
end

assign data_out = dff2;

`else

`endif

endmodule
module altr_hps_ckinv (
  clk,
  clk_inv
);

// -------------------
// Port declarations
// -------------------

input clk;
output clk_inv;

// -----
// RTL
// -----

`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign clk_inv = !clk;

`else



`endif

endmodule
module altr_hps_ckand (
    input  wire              and_in1,     // and input 1
    input  wire              and_in2,     // and input 2
    output  wire             and_out      // and output
);

// -------------------
// Port declarations
// -------------------

wire   and_out_n;

// -----
// RTL
// -----

`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign and_out = and_in1 & and_in2;

`else




`endif

endmodule
module altr_hps_gtiel (
    output wire         z_out     // output
);

`ifdef ALTR_HPS_INTEL_MACROS_OFF
   assign z_out = 1'b0;
`else
`endif

endmodule // altr_hps_gtiel
module altr_hps_ckor_gate (
    input  wire              or_clk,     // or input 1
    input  wire              or_en,     // or input 2
    output  wire             or_out      // or output
);

// -------------------
// Port declarations
// -------------------

// -----
// RTL
// -----

`ifdef ALTR_HPS_INTEL_MACROS_OFF
assign or_out = or_clk | or_en;

`else



`endif

endmodule
module altr_hps_clkgate_or (
  clk,
  clk_gate,
  clk_o
);

// -------------------
// Port declarations
// -------------------

input clk;
input clk_gate;
output clk_o;

// -----
// RTL
// -----

`ifdef ALTR_HPS_INTEL_MACROS_OFF
//assign clk_o = clk | clk_gate;
//fixed behavioral model to match cgc81
reg clk_enable_lat;
 
always @ (clk or clk_gate)
  begin
    if (clk)
      clk_enable_lat <= clk_gate;
  end
 
assign clk_o = clk | clk_enable_lat;

`else

`endif

endmodule
module altr_hps_interface_register
    (
    input  wire              clk,       // clock
    input  wire              rst_n,     // async reset
    input  wire              test_ctrl, // test control
    input  wire              scanen,    // scan enable
    input  wire              data_in,   // data in
    input  wire              scan_in,   // scan in
    output wire              data_out   // data out
     );

`ifdef ALTR_HPS_INTEL_MACROS_OFF

    reg   dff1;
    wire  muxsel;

   assign  muxsel = scanen | test_ctrl;

   
   always @(posedge clk or negedge rst_n)
   begin
      if (!rst_n)
         dff1     <= 1'b0;
      else
         dff1 <= muxsel ? scan_in : data_in;
   end
  assign data_out = dff1;

`else


`endif

endmodule // altr_hps_interface_register
module altr_hps_ckmux21
    (
    input  wire              clk_0,     // clock 0
    input  wire              clk_1,     // clock 1
    input  wire              clk_sel,   // clock selector
    output  wire             clk_o      // clock out
     );

`ifdef ALTR_HPS_INTEL_MACROS_OFF
    assign clk_o = clk_sel ? clk_1 : clk_0;
`else

`endif

endmodule // altr_hps_ckmux21
module altr_hps_rstnsync4
  (
    input wire 		clk,
    input wire 		i_rst_n,          
    input wire		scan_mode,
    output wire 	sync_rst_n			     
   
   );

   reg 		first_stg_rst_n;					     
   wire		prescan_sync_rst_n;
   
   always @(posedge clk or negedge i_rst_n)
     if (!i_rst_n)
       first_stg_rst_n <= 1'b0;
     else
       first_stg_rst_n <= 1'b1;

   altr_hps_bitsync4 
     #(.DWIDTH(1), .RESET_VAL(0)                       ) 
   i_sync_rst_n
     (
      .clk           (clk               ),
      .rst_n         (i_rst_n           ), 
      .data_in       (first_stg_rst_n   ),
      .data_out      (prescan_sync_rst_n) 
      );

   // Added scan bypass mux (Fogbugz #26486)
   altr_hps_mux21
   	i_rstsync_mux
   (
	   .mux_in0  (prescan_sync_rst_n),
	   .mux_in1  (i_rst_n),
	   .mux_sel	 (scan_mode),  
	   .mux_out  (sync_rst_n)
   );
   
   endmodule
module altr_hps_eccsync (
  input  wire rst_n,          // Reset (active low)
  input  wire clk,            // Clock 
  input  wire err,            // Error interrupt (from ECC RAM, serr/derr)
  input  wire err_ack,        // Error interrupt request (from System Manager)
  output reg  err_req         // Error interrupt acknowledge (to GIC)
);

// Declaration
localparam IDLE = 1'b0,
           REQ  = 1'b1;

reg err_d, ack_d;
wire err_p, ack_p;

// Positive edge detection
assign err_p = err & ~err_d;
assign ack_p = err_ack & ~ack_d;

always @(posedge clk, negedge rst_n) begin
  if (~rst_n) begin
    err_d <= 1'b0;
    ack_d <= 1'b0;
    end
  else begin
    err_d <= err;
    ack_d <= err_ack;
    end
  end

// Hand-shake states
always @(posedge clk, negedge rst_n) begin
  if (~rst_n)
    err_req <= 1'b0;
  else
    case (err_req)
      IDLE: err_req <= err_p & ~err_ack;
      REQ : err_req <= ~ack_p;
      default: err_req <= 1'bx;  // simulation purpose
    endcase
end

endmodule
module cfg_dprio_csr_reg_bit 
(
input  wire      clk,        // clock
input  wire      csr_in,     // CSR serial input
input  wire      csr_en,     // CSR enable
output wire      csr_out,    // Gated CSR serial output
output wire      csr_chain   // Output to connect to CSR chain
);

//reg              csr_reg;
wire             csr_reg;

// Gated CSR output
assign csr_out = (csr_en == 1'b1) ? csr_reg : 1'b0;

// Output to connect to the chain
assign csr_chain = csr_reg;

// DPRIO 1-bit register
//always @ (posedge clk)
//  begin
//    csr_reg <= csr_in;
//  end
  cfg_cmn_non_scan_reg csr_ns_reg (
    .din  (csr_in),
    .clk  (clk),
    .dout (csr_reg)
  );

endmodule
module cfg_dprio_shadow_status_nregs 
#(
   parameter DATA_WIDTH        = 16,  // Data width
   parameter NUM_STATUS_REGS   = 5,   // Number of n-bit status registers
   parameter CLK_FREQ_MHZ      = 250,  // Clock freq in MHz
   parameter TOGGLE_TYPE = 1,
   parameter VID = 1
 )
(
input  wire [NUM_STATUS_REGS-1:0]             rst_n,         // reset
input  wire [NUM_STATUS_REGS-1:0]             clk,           // clock
input  wire [DATA_WIDTH*NUM_STATUS_REGS-1:0]  stat_data_in,  // status data input
input  wire [NUM_STATUS_REGS-1:0]             write_en,      // write data enable from DPRIO

output wire [NUM_STATUS_REGS-1:0]             write_en_ack,  // write data enable acknowlege to DPRIO
output wire [DATA_WIDTH*NUM_STATUS_REGS-1:0]  stat_data_out  // status data output
);

generate 
  genvar i;
  for (i=0; i < NUM_STATUS_REGS; i=i+1)
    begin: shadow_status_nregs
      cfg_dprio_shadow_status_regs 
        #(
           .DATA_WIDTH(DATA_WIDTH),  // Data width
           .CLK_FREQ_MHZ(CLK_FREQ_MHZ),
           .TOGGLE_TYPE(TOGGLE_TYPE),
           .VID(VID)
         ) cfg_dprio_shadow_status_regs
         (
          .rst_n         (rst_n[i]),                                       // reset
          .clk           (clk[i]),                                         // clock
          .stat_data_in  (stat_data_in[DATA_WIDTH*(i+1)-1:DATA_WIDTH*i]),  // status data input
          .write_en      (write_en[i]),                                    // write data enable
          .write_en_ack  (write_en_ack[i]),                                // write data enable acknowlege
          .stat_data_out (stat_data_out[DATA_WIDTH*(i+1)-1:DATA_WIDTH*i])  // status data output
         );
  end
endgenerate

endmodule
module cfg_dprio_csr_reg_nregs 
#(
   parameter BINDEX            = 0,   // Base index
   parameter SEGMENT           = 0,   // CSR segment
   parameter DATA_WIDTH        = 16,  // Data width
   parameter NUM_EXTRA_CSR_REG = 1,   // Number of extra 16-bit register for CSR
   parameter CSR_OUT_NEG_FF_EN = 0,   // Enable negative FF on csr_out
   parameter SECTOR_ROW        = 0,
   parameter SECTOR_COL        = 0
 )
( 
input  wire                                    clk,          // clock
input  wire                                    csr_in,       // serial CSR in
input  wire                                    csr_en,       // CSR enable
input  wire                                    scan_shift_n, // ATPG scan shift control to gate of CSR output

output wire [DATA_WIDTH*NUM_EXTRA_CSR_REG-1:0] csr_reg,      // CRAM connecting to custom logic
output wire                                    csr_out       // serial CSR output
);

wire   [NUM_EXTRA_CSR_REG:0]         chain;
wire                                 csr_out_int;
reg                                  csr_out_reg;
wire                                 csr_en_int;
wire                                 csr_out_neg_bypass;

  // Backdoor access
  `ifdef TOP_SIM
  `include "cfg_csr_backdoor_access.vh"
  `endif

// Gated CSR output during ATPG scan shift
assign csr_en_int = csr_en & scan_shift_n;

// Generate number of required CSR bits
generate 
  genvar i;
  for (i=0; i < NUM_EXTRA_CSR_REG; i=i+1)
    begin: csr_reg_nregs
cfg_dprio_csr_reg_nbits  
 #(
   .DATA_WIDTH(DATA_WIDTH)
   ) csr_reg_nbits 
     (.clk (clk),
      .csr_in (chain[i]), 
      .csr_en (csr_en_int),
      .csr_out (chain[i+1]),
      .csr_reg (csr_reg[DATA_WIDTH*(i+1)-1:DATA_WIDTH*i])
      );
    end
endgenerate

// Connecting the si and so
assign csr_out_int  = chain[NUM_EXTRA_CSR_REG];
assign chain[0]     = csr_in;

// Negative FF for csr_out
always @ (negedge clk)
  begin
    csr_out_reg <= csr_out_int;
  end

// Bypassing negative FF in scan_shift
assign csr_out_neg_bypass = (scan_shift_n == 1'b1) ? csr_out_reg : csr_out_int;

// csr_out assignment
assign csr_out = (CSR_OUT_NEG_FF_EN == 1) ? csr_out_neg_bypass : csr_out_int;

endmodule
module cfg_cmn_clk_mux (
  input  clk1,
  input  clk2,
  input  sel,
  output clk_out
);

  assign clk_out = sel ? clk1 : clk2;

endmodule