dakies/OSS_Verilog huggingface dataset:
module CLK_DIV #
(
    parameter WIDTH = 8
)
(
    input                 clk_in,
    input                 rst_n,
    input  [WIDTH - 1:0]  N,
    output                clk_div
);

reg [WIDTH-1:0] cnt_p = 0;// 上升沿计数单位
reg [WIDTH-1:0] cnt_n = 0;// 下降沿计数单位
reg             clk_in_p = 0;// 上升沿时钟
reg             clk_in_n = 0;// 下降沿时钟

//其中N==1是判断不分频，N[0]是判断是奇数还是偶数，若为1则是奇数分频，若是偶数则是偶数分频。
assign clk_div = (N == 1) ? clk_in : (N[0])   ? (clk_in_p | clk_in_n) : (clk_in_p);
        
always@(posedge clk_in or negedge rst_n) begin
    if (!rst_n)
        cnt_p <= 0;
    else if (cnt_p == (N-1))
        cnt_p <= 0;
    else
        cnt_p <= cnt_p + 1;
end

always@(posedge clk_in or negedge rst_n) begin
    if (!rst_n) 
        clk_in_p <= 1;//此处设置为0也是可以的，这个没有硬性的要求，不管是取0还是取1结果都是正确的。
    else if (cnt_p < (N>>1))/*N整体向右移动一位，最高位补零，其实就是N/2，不过在计算奇数的时候有很明显的优越性*/
        clk_in_p <= 1;
    else
        clk_in_p <= 0;    
end

always@(negedge clk_in or negedge rst_n) begin
    if (!rst_n)
        cnt_n <= 0;
    else if (cnt_n == (N-1))
        cnt_n <= 0;
    else
        cnt_n <= cnt_n + 1;
end

always@(negedge clk_in or negedge rst_n) begin
    if (!rst_n)
        clk_in_n <= 1;
    else if (cnt_n < (N>>1))
        clk_in_n <= 1;
    else
        clk_in_n <= 0;
end

endmodule
module CLK_Sample # (
	parameter PHASE_WIDTH = 32
) (
    input                    clk_in,
    input                    RST,
    input  [PHASE_WIDTH-1:0] sample_fre,
    output		             clk_sample
);

reg  [PHASE_WIDTH-1:0] addr_r = 0;
always @(posedge clk_in) begin
	if (RST) 
		addr_r <= 32'd0;
	else 
		addr_r <= addr_r + sample_fre;
end
assign clk_sample = addr_r[PHASE_WIDTH-1];

endmodule
module AGC(
	input  wire 			  clk,
	input  wire 			  rst,
	input  wire        [7:0]  a_coef,
	input  wire        [15:0] reference,
	input  wire signed [15:0] x_in,
	output wire signed [15:0] y_out
);
		
wire        [31:0] x_mod;		
wire        [31:0] ref_rms;	
wire signed [8:0]  a_coef_s;	
wire signed [32:0] tmp_level;
wire signed [32:0] feedback_level;
reg  signed [32:0] zreg;	

assign ref_rms        = (reference[15:1] * reference[15:1]);
assign a_coef_s       = { 1'b0, a_coef};
		
assign x_mod          = (y_out * y_out);
assign tmp_level      = ($signed(ref_rms - x_mod))>>>18;
assign feedback_level = (tmp_level * a_coef_s) >>> 8;

always @(posedge clk or negedge rst) begin	
	if (!rst) 
		zreg <= 'h0;
	else 
		zreg <=  zreg + feedback_level;
end

assign y_out = (zreg * x_in) >>>16;

endmodule
module mseq #(  
    parameter W = 4'd4,
    parameter POLY = 5'b10011
) (   
    input  clk,
    input  rst_n,
    output mseq_out
);

reg [W-1:0] sreg = 8'b11111111;
assign mseq_out = sreg[0];

always@(posedge clk or posedge rst_n) begin
    if(~rst_n) 
        sreg <= 1'b1;
    else begin
        if(mseq_out) 
            sreg <= (sreg >> 1) ^ (POLY >> 1);
        else 
            sreg <= sreg >> 1;
    end
end

endmodule
module manchester (
    input  clk,
    input  sig_in,
    output man_sig_out
);

reg ck   = 0;
reg ck_r = 0;
always @(posedge clk) begin
    ck <= ck_r;
    ck <= ~ ck;
end

assign man_sig_out = ck ^ sig_in;

endmodule
module IQ_MIXED #(
	//LO_OUTPUR_parameter
    parameter LO_WIDTH     = 12,
	parameter PHASE_WIDTH  = 32,
	//CIC_Filter_parameter
	parameter Fiter_WIDTH  = 38,
	//IQ_MIXED_parameter
    parameter INPUT_WIDTH  = 12,
    parameter OUTPUT_WIDTH = 12
) (
    input                         clk,
    output                        clk_out,  
    input                         RST,

	input  [15:0]                 FACTOR,
    input  [PHASE_WIDTH - 1 : 0]  Fre_word,

    input  [INPUT_WIDTH - 1 : 0]  wave_in,
    output [OUTPUT_WIDTH - 1 : 0] I_OUT,
    output [OUTPUT_WIDTH - 1 : 0] Q_OUT
);

wire  [LO_WIDTH-1:0]    cos_wave;
wire  [LO_WIDTH-1:0]    sin_wave;
wire  [PHASE_WIDTH-1:0] pha_diff;
Cordic # (
    .XY_BITS(LO_WIDTH),               
    .PH_BITS(PHASE_WIDTH),      //1~32     
    .ITERATIONS(16),     //1~32
    .CORDIC_STYLE("ROTATE"),    //ROTATE  //VECTOR
    .PHASE_ACC("ON")            //ON      //OFF
) IQ_Gen_u (
    .clk(clk),
    .RST(RST),
    .x_i(0), 
    .y_i(0),
    .phase_in(Fre_word),       
	.valid_in(~RST),   
        
    .x_o(cos_wave),
    .y_o(sin_wave),
    .phase_out(pha_diff)
);

wire signed [Fiter_WIDTH - 1 : 0] I_SIG;
wire signed [Fiter_WIDTH - 1 : 0] Q_SIG;
reg  signed [INPUT_WIDTH + LO_WIDTH - 1 : 0] I_SIG_r = 0;
reg  signed [INPUT_WIDTH + LO_WIDTH - 1 : 0] Q_SIG_r = 0;
always @(posedge clk) begin
	if (RST) begin
		I_SIG_r <= 24'd0;
		Q_SIG_r <= 24'd0;
	end
	else begin
		I_SIG_r <= $signed(wave_in) * $signed(cos_wave);
		Q_SIG_r <= $signed(wave_in) * $signed(sin_wave);
	end
end
assign I_SIG = I_SIG_r[INPUT_WIDTH + LO_WIDTH - 1 : INPUT_WIDTH + LO_WIDTH - 12];
assign Q_SIG = Q_SIG_r[INPUT_WIDTH + LO_WIDTH - 1 : INPUT_WIDTH + LO_WIDTH - 12];


wire        [Fiter_WIDTH-1:0] Fiter_wave_I;
CIC_DOWN_S3#(
	.INPUT_WIDTH(12),
	.OUTPUT_WIDTH(Fiter_WIDTH)) 
Fiter_I (
    .clk(clk),
    .clk_enable(1'd1),
    .reset(RST),
	.FACTOR(FACTOR),
    .filter_in(I_SIG),
    .filter_out(Fiter_wave_I)
);
assign I_OUT = Fiter_wave_I[Fiter_WIDTH - 1 : Fiter_WIDTH - OUTPUT_WIDTH];

wire        [Fiter_WIDTH-1:0] Fiter_wave_Q;
CIC_DOWN_S3#(
	.INPUT_WIDTH(12),
	.OUTPUT_WIDTH(Fiter_WIDTH)
) Fiter_Q(
    .clk(clk),
    .clk_enable(1'd1),
    .reset(RST),
	.FACTOR(FACTOR),
    .filter_in(Q_SIG),
    .filter_out(Fiter_wave_Q),
	.ce_out(clk_out)
);
assign Q_OUT = Fiter_wave_Q[Fiter_WIDTH - 1 : Fiter_WIDTH - OUTPUT_WIDTH];

endmodule
module Demodulate #(
    parameter PHASE_WIDTH  = 32,
	parameter Fiter_WIDTH  = 38,
    parameter INPUT_WIDTH  = 8,
    parameter OUTPUT_WIDTH = 12
) (
    input                     clk,
    input                     RST,

	input  [15:0]             FACTOR,
    input  [PHASE_WIDTH-1:0]  Fre_word,

    input  [INPUT_WIDTH-1:0]  wave_in,

    output [OUTPUT_WIDTH-1:0] FM_Demodule_OUT,
    output [OUTPUT_WIDTH-1:0] PM_Demodule_OUT,
    output [OUTPUT_WIDTH-1:0] AM_Demodule_OUT
);

// IQ_MIXED Outputs
wire  clk_out;
wire  [OUTPUT_WIDTH - 1 : 0]  I_OUT;
wire  [OUTPUT_WIDTH - 1 : 0]  Q_OUT;

/*
数字下变频处理模块
*/
IQ_MIXED #(
    .LO_WIDTH     ( 12 ),
    .PHASE_WIDTH  ( PHASE_WIDTH  ),
    .Fiter_WIDTH  ( Fiter_WIDTH  ),
    .INPUT_WIDTH  ( INPUT_WIDTH  ),
    .OUTPUT_WIDTH ( OUTPUT_WIDTH )) 
u_IQ_MIXED (
    .clk                  ( clk     ),
    .clk_out                 ( clk_out    ),
    .RST                     ( RST        ),
	
	.FACTOR                  ( FACTOR     ),
    .Fre_word                ( Fre_word   ),

    .wave_in                 ( wave_in    ),
    .I_OUT                   ( I_OUT      ),
    .Q_OUT                   ( Q_OUT      )
);

wire  [OUTPUT_WIDTH-1:0] Y_diff;
Cordic # (
    .XY_BITS(OUTPUT_WIDTH),               
    .PH_BITS(OUTPUT_WIDTH),      //1~32
    .ITERATIONS(16),             //1~32
    .CORDIC_STYLE("VECTOR"))     //ROTATE  //VECTOR
Demodulate_Gen_u (
    .clk(clk_out),
    .RST(RST),
    .x_i(I_OUT), 
    .y_i(Q_OUT),
    .phase_in(0),          
	.valid_in(~RST),   
     
    .x_o(AM_Demodule_OUT),
    .y_o(Y_diff),
    .phase_out(PM_Demodule_OUT)
);

reg [OUTPUT_WIDTH-1:0] PM_Demodule_OUT_r = 0;
always @(posedge clk_out) begin
    PM_Demodule_OUT_r <= PM_Demodule_OUT;
end
assign FM_Demodule_OUT = $signed(PM_Demodule_OUT) - $signed(PM_Demodule_OUT_r);

endmodule
module Loop_filter (
    input                clk_sys,
    input                rst_n,
    input  signed [27:0] Xdin,
    output signed [27:0] Ydout
);

parameter k1 = 12498;
parameter k2 = 4430400;

reg [2:0] cnt;
reg signed [27:0]   Ydin_1;
reg signed [27:0]   Ydout_buf;
always@(posedge clk_sys) begin
    if(!rst_n) 
        cnt <= 3'd0;
    else
        cnt <= cnt + 3'd1;
end
always@(posedge clk_sys) begin
    if(!rst_n) begin
        Ydin_1 <= 28'd0;
        Ydout_buf <= 28'd0;
    end
    else if(cnt == 3'd3)
        Ydin_1 = Ydin_1 + Xdin/k1;
    else if(cnt == 3'd4)
        Ydout_buf <= Ydin_1 + Xdin/k2;
end
assign Ydout = Ydout_buf;
endmodule
module testbench();

parameter TOTAL_STAGE = 8;

reg                    clk_100m  = 0;
reg                    sys_rst_n = 0;
reg [TOTAL_STAGE-1:0]  addr = 0;

wire         valid_out;
always begin
    #10 clk_100m = ~clk_100m;
end
always begin
    #50 sys_rst_n = 1;
end
always begin
    if (valid_out) begin
        #10 addr = addr + 1;#10;
    end
    else begin     
        #10 addr = 0;#10;
    end
end

parameter  REAL_WIDTH  = 18;
parameter  IMGN_WIDTH  = 18;

wire  [REAL_WIDTH-1:0] cos_wave;
wire  [IMGN_WIDTH-1:0] sin_wave;
wire  [15:0] pha_diff;
Cordic #
(
   .XY_BITS(REAL_WIDTH),
   .PH_BITS(16),                 //1~32
   .ITERATIONS(16),              //1~32
   .CORDIC_STYLE("ROTATE"),    //ROTATE  //VECTOR
   .PHASE_ACC("ON")            //ON      //OFF
)
IQ_Gen_u
(
   .clk_in(clk_100m),
   .RST(1'd0),
   .x_i(0),
   .y_i(0),
   .phase_in(16'd2356),//Fre_word = （(2^PH_BITS)/fc）* f   fc：时钟频率   f输出频率

   .x_o(cos_wave),
   .y_o(sin_wave),
   .phase_out(pha_diff),

   .valid_in(1),
   .valid_out(valid_out)
);

wire                   oen;
wire [REAL_WIDTH-1:0]  oReal;
wire [IMGN_WIDTH-1:0]  oImag;
wire [TOTAL_STAGE-1:0] oaddr;
fft #(
    .REAL_WIDTH(REAL_WIDTH),
    .IMGN_WIDTH(REAL_WIDTH),
    .TOTAL_STAGE(TOTAL_STAGE)
)
fft_ins 
(
	.iclk(clk_100m),
	.rst_n(sys_rst_n),

	.iaddr(addr),
	.iReal(cos_wave),
	.iImag(0),
	.ien(valid_out),

	.oReal(oReal),
	.oImag(oImag),
	.oaddr(oaddr),
	.oen(oen)
);

endmodule
module fft #(
	parameter REAL_WIDTH = 18,
	parameter IMGN_WIDTH = 18,
	parameter TOTAL_STAGE = 11
) (
	input                    iclk,
	input                    rst_n,

	input                    ien,
	input  [TOTAL_STAGE-1:0] iaddr,
	input  [REAL_WIDTH-1:0]  iReal,
	input  [IMGN_WIDTH-1:0]  iImag,

	output                   oen,
	output [TOTAL_STAGE-1:0] oaddr,
	output [REAL_WIDTH-1:0]  oReal,
	output [IMGN_WIDTH-1:0]  oImag
);
	
localparam INTER_MODU_WIRE_NUM = ((TOTAL_STAGE-1)/2);
localparam CPLX_WIDTH = REAL_WIDTH + IMGN_WIDTH;

wire [CPLX_WIDTH -1:0] data_end;
wire [TOTAL_STAGE-1:0] addr_end;

wire                   en_w   [INTER_MODU_WIRE_NUM:0];
wire [CPLX_WIDTH -1:0] data_w [INTER_MODU_WIRE_NUM:0];
wire [TOTAL_STAGE-1:0] addr_w [INTER_MODU_WIRE_NUM:0];

assign en_w  [INTER_MODU_WIRE_NUM] = ien;
assign addr_w[INTER_MODU_WIRE_NUM] = iaddr;
assign data_w[INTER_MODU_WIRE_NUM] = {iReal, iImag};

generate
genvar gv_stg;
for(gv_stg=TOTAL_STAGE; gv_stg>=2; gv_stg=gv_stg-2) begin : stagX
fft_stage #( 
	.REAL_WIDTH(REAL_WIDTH),
	.IMGN_WIDTH(IMGN_WIDTH),
	.TOTAL_STAGE(TOTAL_STAGE),
	.FFT_STG(gv_stg) 
)stgX_inst (
	.iclk(iclk),
	.rst_n(rst_n),
	.iaddr(addr_w[((gv_stg-1)/2)]),
	.idata(data_w[((gv_stg-1)/2)]),
	.ien(en_w[((gv_stg-1)/2)]),
	.oaddr(addr_w[((gv_stg-1)/2)-1]),
	.odata(data_w[((gv_stg-1)/2)-1]),
	.oen(en_w[((gv_stg-1)/2)-1])
);
end
if(TOTAL_STAGE[0]) begin : BF_stg1
	BF_stg1 #( 
		.REAL_WIDTH(REAL_WIDTH),
		.IMGN_WIDTH(IMGN_WIDTH),
		.TOTAL_STAGE(TOTAL_STAGE),
		.FFT_STG(1) 
	)stg1_inst (
		.iclk(iclk),
		.rst_n(rst_n),
		.ien(en_w[0]),
		.iaddr(addr_w[0]),
		.idata(data_w[0]),
		.oen(oen),
		.oaddr(addr_end),
		.odata(data_end)
	);
	end
endgenerate

generate	// bit_reverse
genvar index;
	for(index=0; index<TOTAL_STAGE; index=index+1) begin: bit_reverse
		assign oaddr[TOTAL_STAGE-index-1] = addr_end[index];
	end
endgenerate
assign oReal = data_end[CPLX_WIDTH:REAL_WIDTH];
assign oImag = data_end[IMGN_WIDTH:0];

endmodule
module circuit(
   input         clk,
   input         reset,
   input  [7:0]  fmin,
   output [11:0] dmout
);

wire [11:0]   d1;
wire [11:0]   d2;
wire [7:0]    dout;
wire [7:0]    output_xhdl0;
   
multiplier I1(
	.clk(clk), 
	.reset(reset), 
	.input1(fmin), 
	.input2(dout), 
	.output_xhdl0(output_xhdl0)
);

fir I4(
	.clock(clk), 
	.reset(reset), 
	.data_in(d1), 
	.data_out(dmout)
);

loop_filter I3(
	.clk(clk), 
	.reset(reset), 
	.c(output_xhdl0), 
	.d1(d1), 
	.d2(d2)
);

nco I2(
	.clk(clk), 
	.reset(reset), 
	.din(d2), 
	.dout(dout)
);
   
endmodule
module loop_filter(CLK, RESET, C, D1, D2);
   input         CLK;
   input         RESET;
   input [7:0]   C;
   output [11:0] D1;
   output [11:0] D2;
   reg [11:0]    D1;
   reg [11:0]    D2;
   
   
   reg [11:0]    E;
   reg [11:0]    dtemp;
   
   
always @(posedge CLK or posedge RESET)
	if (RESET == 1'b1) begin
		D1 <= {12{1'b0}};
		D2 <= {12{1'b0}};
		E <= {12{1'b0}};
		dtemp <= {12{1'b0}};
	end
	else begin
		dtemp <= ({C[7], C[7], C[7], C, 1'b0}) + dtemp - E;
		E <= {dtemp[11], dtemp[11], dtemp[11], dtemp[11], dtemp[11:4]};
		D1 <= dtemp;
		D2 <= {dtemp[11:4], 4'b0000};
	end
   
endmodule
module FIR(clock, reset, data_in, data_out);
   input         clock;
   input         reset;
   input [11:0]  data_in;
   output [11:0] data_out;
   reg [11:0]    data_out;
   
   
   reg [15:0]    d0;
   reg [15:0]    d1;
   reg [15:0]    d2;
   reg [15:0]    d3;
   reg [15:0]    d4;
   reg [15:0]    d5;
   reg [15:0]    d6;
   reg [15:0]    d7;
   reg [15:0]    d8;
   reg [15:0]    d9;
   reg [15:0]    d10;
   reg [15:0]    d11;
   reg [15:0]    d12;
   reg [15:0]    d13;
   reg [15:0]    d14;
   reg [15:0]    d15;
   reg [15:0]    sum;
   
   
   always @(posedge clock or posedge reset)
      if (reset == 1'b1)
      begin
         d0 <= {16{1'b0}};
         d1 <= {16{1'b0}};
         d2 <= {16{1'b0}};
         d3 <= {16{1'b0}};
         d4 <= {16{1'b0}};
         d5 <= {16{1'b0}};
         d6 <= {16{1'b0}};
         d7 <= {16{1'b0}};
         d8 <= {16{1'b0}};
         d9 <= {16{1'b0}};
         d10 <= {16{1'b0}};
         d11 <= {16{1'b0}};
         d12 <= {16{1'b0}};
         d13 <= {16{1'b0}};
         d14 <= {16{1'b0}};
         d15 <= {16{1'b0}};
         sum <= {16{1'b0}};
         data_out <= {12{1'b0}};
      end
      else 
      begin
         d0 <= {data_in[11], data_in[11], data_in[11], data_in[11], data_in};
         d1 <= d0;
         d2 <= d1;
         d3 <= d2;
         d4 <= d3;
         d5 <= d4;
         d6 <= d5;
         d7 <= d6;
         d8 <= d7;
         d9 <= d8;
         d10 <= d9;
         d11 <= d10;
         d12 <= d11;
         d13 <= d12;
         d14 <= d13;
         d15 <= d14;
         sum <= (d0 + d1 + d2 + d3 + d4 + d5 + d6 + d7 + d8 + d9 + d10 + d11 + d12 + d13 + d14 + d15) >> 4;
         data_out <= (sum[11:0]);
      end
   
endmodule
module sync_fifo #(
   parameter W = 8
)
(
	input 	    		clk, 
	input				reset_n, 
	input				rd_en,
	output [W-1 : 0]  	rd_data,
	input				wr_en, 
	input  [W-1 : 0]  	wr_data,
	output reg  		full, 
	output reg  		empty
);

parameter D = 4;

parameter AW  = (D == 4)   ? 2 :
				(D == 8)   ? 3 :
				(D == 16)  ? 4 :
				(D == 32)  ? 5 :
				(D == 64)  ? 6 :
				(D == 128) ? 7 :
				(D == 256) ? 8 : 0;
   
// synopsys translate_off
initial begin
	if (AW == 0) begin
	$display ("%m : ERROR!!! Fifo depth %d not in range 4 to 256", D);
	end // if (AW == 0)
end // initial begin

// synopsys translate_on

reg [W-1 : 0]    mem[D-1 : 0];
reg [AW-1 : 0]   rd_ptr, wr_ptr;
   
always @ (posedge clk or negedge reset_n) 
	if (reset_n == 1'b0) begin
		wr_ptr <= {AW{1'b0}} ;
	end
	else begin
		if (wr_en & !full) begin
		wr_ptr <= wr_ptr + 1'b1 ;
		end
	end

always @ (posedge clk or negedge reset_n) 
	if (reset_n == 1'b0) begin
		rd_ptr <= {AW{1'b0}} ;
	end
	else begin
		if (rd_en & !empty) begin
		rd_ptr <= rd_ptr + 1'b1 ;
		end
	end


always @ (posedge clk or negedge reset_n) 
	if (reset_n == 1'b0) begin
		empty <= 1'b1 ;
	end
	else begin
		empty <= (((wr_ptr - rd_ptr) == {{(AW-1){1'b0}}, 1'b1}) & rd_en & ~wr_en) ? 1'b1 : 
				((wr_ptr == rd_ptr) & ~rd_en & wr_en) ? 1'b0 : empty ;
	end

always @ (posedge clk or negedge reset_n) 
	if (reset_n == 1'b0) begin
		full <= 1'b0 ;
	end
	else begin
		full <= (((wr_ptr - rd_ptr) == {{(AW-1){1'b1}}, 1'b0}) & ~rd_en & wr_en) ? 1'b1 : 
				(((wr_ptr - rd_ptr) == {AW{1'b1}}) & rd_en & ~wr_en) ? 1'b0 : full ;
	end

always @ (posedge clk) 
	if (wr_en)
		mem[wr_ptr] <= wr_data;

assign  rd_data = mem[rd_ptr];


// synopsys translate_off
always @(posedge clk) begin
	if (wr_en && full) begin
		$display("%m : Error! sfifo overflow!");
	end
end

always @(posedge clk) begin
	if (rd_en && empty) begin
		$display("%m : error! sfifo underflow!");
	end
end
// synopsys translate_on
//---------------------------------------

endmodule
module RAMshift_taps #(
	parameter TOTAL_RAM_Length = 640,
	parameter DATA_WIDTH = 8
) (
	input	  					  clken, 
	input	  					  clock,
	input	[31:0]                Delay_Length,
	input	[DATA_WIDTH - 1 : 0]  shiftin,
	output	[DATA_WIDTH - 1 : 0]  shiftout
);

reg  [31:0] RAM_CNT = 0;
reg	 [DATA_WIDTH - 1 : 0] ram_buf = 0;
reg	 [DATA_WIDTH - 1 : 0] shift_ram [TOTAL_RAM_Length - 1 : 0];

integer m;
initial begin
	for (m = 0; m<=TOTAL_RAM_Length; m=m+1) begin
		shift_ram[m] = 0;
	end    
end

always @(posedge clock) begin
    if (RAM_CNT == (Delay_Length - 1)) 
        RAM_CNT <= 0;
    else if (clken) 
        RAM_CNT <= RAM_CNT + 1;
	else
		RAM_CNT <= RAM_CNT;
end

always @(posedge clock) begin	
	if (clken) begin
		shift_ram[RAM_CNT] <= shiftin;
	end	
	else begin
		shift_ram[RAM_CNT] <= shift_ram[RAM_CNT];
	end
end

assign shiftout = shift_ram[RAM_CNT];

endmodule
module Line_Shift_RAM #(
	parameter  RAM_Length = 640,	//640*480
    parameter  DATA_WIDTH = 8
) (
	input	                   clken,
	input	                   clock,
	input	[DATA_WIDTH-1:0]   shiftin,
	output	[DATA_WIDTH-1:0]   taps0x,
	output	[DATA_WIDTH-1:0]   taps1x
);

RAMshift_taps #(
	.TOTAL_RAM_Length (RAM_Length),
	.DATA_WIDTH (DATA_WIDTH)
) RAMshfit_taps_u1 (
	.clken(clken), 
	.clock(clock),
	.Delay_Length(RAM_Length),
	.shiftin(shiftin),
	.shiftout(taps0x)
);

RAMshift_taps #(
	.TOTAL_RAM_Length (RAM_Length),
	.DATA_WIDTH (DATA_WIDTH)
) RAMshfit_taps_u2 (
	.clken(clken), 
	.clock(clock),
	.Delay_Length(RAM_Length),
	.shiftin(taps0x),
	.shiftout(taps1x)
);
endmodule
module uart_rx(
	input clk_50m,
	input uart_rx,
	output [7:0] uart_rx_data,
	output uart_rx_done
    );
    
parameter [12:0] BAUD_DIV     = 13'd87;//bps115200  每位数据传输时间为t=1/115200 s,周期T=1/100000000，计数值为t/T=868
parameter [12:0] BAUD_DIV_CAP = 13'd43;   

reg [12:0] baud_div=0;				      
reg baud_bps=0;					            
reg bps_start=0;					          
always@(posedge clk_50m)
begin
	if(baud_div==BAUD_DIV_CAP)	    	     
		begin
			baud_bps<=1'b1;
			baud_div<=baud_div+1'b1;
		end
	else if(baud_div<BAUD_DIV && bps_start) 
		begin
			baud_div<=baud_div+1'b1;
			baud_bps<=0;
		end
	else
		begin
			baud_bps<=0;
			baud_div<=0;
		end
end

reg [4:0] uart_rx_r=5'b11111;			 
always@(posedge clk_50m)
begin
	uart_rx_r<={uart_rx_r[3:0],uart_rx};
end
wire uart_rxnt=uart_rx_r[4]|uart_rx_r[3]|uart_rx_r[2]|uart_rx_r[1]|uart_rx_r[0];

reg [3:0] bit_num=0;	    
reg state=1'b0;

reg [7:0] uart_rx_data_r0=0;
reg [7:0] uart_rx_data_r1=0;
reg       uart_rx_dong_r=0;
always@(posedge clk_50m)
begin
    uart_rx_dong_r <= 0;
	case(state)
		1'b0 : 
			if(!uart_rxnt)
				begin
					bps_start<=1'b1;
					state<=1'b1;
				end
		1'b1 :			
			if(baud_bps)	
				begin
					bit_num<=bit_num+1'b1;
					if(bit_num<4'd9)	
						uart_rx_data_r0[bit_num-1]<=uart_rx;
				end
			else if(bit_num==4'd10)
				begin
					bit_num<=0;
					uart_rx_dong_r <= 1;
					uart_rx_data_r1<=uart_rx_data_r0;
					state<=1'b0;
					bps_start<=0;
				end
		default:;
	endcase
end
assign uart_rx_data=uart_rx_data_r1;		
assign uart_rx_done= uart_rx_dong_r;
endmodule
module uart_rx_control
(
	input		    clk_50m,
	input 			rst_n,
	input			uart_rx_done,
	input  [7:0]    uart_rx_data,
	output [31:0]   data_out_0,
	output [15:0]   data_out_1,
	output [15:0]   data_out_2,
	output 			uart_done
);
reg [31:0] 			uart_data_buf_0;
reg [31:0] 			data_out_r_0;

reg [15:0] 			uart_data_buf_1;
reg [15:0] 			data_out_r_1;

reg [15:0] 			uart_data_buf_2;
reg [15:0] 			data_out_r_2;

reg [4:0] 			state;
reg 				   uart_done_buf;

always@(posedge clk_50m or negedge rst_n)
begin
	if(!rst_n)
	begin
		state <= 4'd0;
		uart_data_buf_0 <= 32'd0;
		uart_data_buf_1 <= 15'd0;
		uart_data_buf_2 <= 15'd0;
		uart_done_buf <= 1'd0;
	end
	else
	begin
		case(state)
			5'd0:begin uart_done_buf<=1'd0; state<=state+1; end
			5'd1:if((uart_rx_data == 8'h99)&&uart_rx_done)begin state<=state+1; end
			5'd2:if((uart_rx_data == 8'h50)&&uart_rx_done)begin state<=state+1; end				
			5'd3:if(uart_rx_done)begin uart_data_buf_0[7:0]<=uart_rx_data;  state<=state+1; end
			5'd4:if(uart_rx_done)begin uart_data_buf_0[15:8]<=uart_rx_data; state<=state+1; end
			5'd5:if(uart_rx_done)begin uart_data_buf_0[23:16]<=uart_rx_data; state<=state+1; end
			5'd6:if(uart_rx_done)begin uart_data_buf_0[31:24]<=uart_rx_data; state<=state+1; end
			5'd7:if(uart_rx_done)begin uart_data_buf_1[7:0]<=uart_rx_data;  state<=state+1; end
			5'd8:if(uart_rx_done)begin uart_data_buf_1[15:8]<=uart_rx_data; state<=state+1; end
			5'd9:if(uart_rx_done)begin uart_data_buf_2[7:0]<=uart_rx_data;  state<=state+1; end
			5'd10:if(uart_rx_done)begin uart_data_buf_2[15:8]<=uart_rx_data; state<=state+1; end
			5'd11:begin data_out_r_0<=uart_data_buf_0; 
							data_out_r_1<=uart_data_buf_1;
							data_out_r_2<=uart_data_buf_2;
							uart_done_buf<=1'd1; state<=4'd0; 
					end
		endcase	
	end
end
assign data_out_0 = data_out_r_0;
assign data_out_1 = data_out_r_1;
assign data_out_2 = data_out_r_2;

assign uart_done = uart_done_buf;
endmodule
module uart_tx(
	input clk_50m,
	input [7:0] uart_tx_data,	      
	input uart_tx_en,			        
	output uart_tx,
	output uart_tx_done
);

parameter BAUD_DIV     = 13'd87;  
parameter BAUD_DIV_CAP = 13'd43;     
reg [12:0] baud_div=0;			         
reg baud_bps=0;				            
reg [9:0] send_data=10'b1111111111;    
reg [3:0] bit_num=0;	                
reg uart_send_flag=0;	                
reg uart_tx_r=1;		              
always@(posedge clk_50m)
begin
	if(baud_div==BAUD_DIV_CAP)	        
		begin
			baud_bps<=1'b1;
			baud_div<=baud_div+1'b1;
		end
	else if(baud_div<BAUD_DIV && uart_send_flag)
		begin
			baud_div<=baud_div+1'b1;
			baud_bps<=0;	
		end
	else
		begin
			baud_bps<=0;
			baud_div<=0;
		end
end

always@(posedge clk_50m)
begin
    if(uart_tx_en)	
		begin
			uart_send_flag<=1'b1;
			send_data<={1'b1,uart_tx_data,1'b0};
		end
	else if(bit_num==4'd10)	
		begin
			uart_send_flag<=1'b0;
			send_data<=10'b1111_1111_11;
		end
end

always@(posedge clk_50m)
begin
	if(uart_send_flag)	
		begin
			if(baud_bps)
				begin
					if(bit_num<=4'd9)
						begin
							uart_tx_r<=send_data[bit_num];	
							bit_num<=bit_num+1'b1;
						end
				end
			else if(bit_num==4'd10)
				bit_num<=4'd0;
		end
	else
		begin
			uart_tx_r<=1'b1;	
			bit_num<=0;
		end
end

assign uart_tx=uart_tx_r;
assign uart_tx_done = (bit_num == 10) ? 1:0;
endmodule
module  key_driver 
(
    input       clk, 
    input       rst, 
    input       button_in,
    output reg  button_posedge,
    output reg  button_negedge,
    output reg  button_out
);
//// ---------------- internal constants --------------
parameter N = 32 ;           // debounce timer bitwidth
parameter FREQ = 60;         //model clock :Mhz
parameter MAX_TIME = 20;     //ms
localparam TIMER_MAX_VAL =   MAX_TIME * 1000 * FREQ;
////---------------- internal variables ---------------
reg  [N-1 : 0]  q_reg;      // timing regs
reg  [N-1 : 0]  q_next;
reg DFF1, DFF2;             // input flip-flops
wire q_add;                 // control flags
wire q_reset;
reg button_out_d0;
//// ------------------------------------------------------

////contenious assignment for counter control
assign q_reset = (DFF1  ^ DFF2);          // xor input flip flops to look for level chage to reset counter
assign q_add = ~(q_reg == TIMER_MAX_VAL); // add to counter when q_reg msb is equal to 0
    
//// combo counter to manage q_next 
always @ ( q_reset, q_add, q_reg) begin
    case( {q_reset , q_add})
        2'b00 :
                q_next <= q_reg;
        2'b01 :
                q_next <= q_reg + 1;
        default :
                q_next <= { N {1'b0} };
    endcase     
end

//// Flip flop inputs and q_reg update
always @ ( posedge clk or posedge rst) begin
    if(rst == 1'b1) begin
        DFF1 <= 1'b0;
        DFF2 <= 1'b0;
        q_reg <= { N {1'b0} };
    end
    else begin
        DFF1 <= button_in;
        DFF2 <= DFF1;
        q_reg <= q_next;
    end
end

//// counter control
always @ ( posedge clk or posedge rst) begin
	if(rst == 1'b1)
		button_out <= 1'b1;
    else if(q_reg == TIMER_MAX_VAL)
        button_out <= DFF2;
    else
        button_out <= button_out;
end

always @ ( posedge clk or posedge rst) begin
	if(rst == 1'b1) begin
		button_out_d0 <= 1'b1;
		button_posedge <= 1'b0;
		button_negedge <= 1'b0;
	end
	else begin
		button_out_d0 <= button_out;
		button_posedge <= ~button_out_d0 & button_out;
		button_negedge <= button_out_d0 & ~button_out;
	end	
end

endmodule
module ADF_driver
(
	input       clk,        //系统时钟
	input       wrsig,      //发送命令，上升沿有效
	input [8:0] datain,     //需要发送的数据

	output reg tx_idle,         //线路状态指示，高为线路忙，低为线路空闲
	output reg tx,              //发送数据信号
	output reg clkout,
	output reg LE
);

reg tx_send=0;
reg tx_wrsigbuf=0, tx_wrsigrise=0;
reg[7:0] tx_cnt=0; //计数器
//检测发送命令是否有效
reg [15:0] clk_cnt=0;
reg [31:0]dataint=0;
reg [10:0]cnt_init=0;
reg init=0;
reg [4:0] cnt_wei=0;
reg [15:0]int_v=0;
reg [11:0]frac_v=0;


parameter [31:0]R5=32'b00000000_00011_0000000000000000_101;
parameter [31:0]R4=32'b00000000_1101_01100100_000000_111100;
parameter [31:0]R3=32'b00000000_100000010_111111111111_011;
parameter [31:0]R2=32'b00000000_0000000001_00000_001000010;
parameter [31:0]R1=32'b00000_000000000000_000001100100_001;
reg [31:0]R0=32'b0_00000000_10100000_000000000000_000;

always @(posedge clk) begin//分频进程   CLK/(1000000)
  if(clk_cnt == 16'd24) begin
    clkout <= 1'b1;
    clk_cnt <= clk_cnt + 16'd1;
  end
  else if(clk_cnt == 16'd49) begin
    clkout <= 1'b0;
    clk_cnt <= 16'd0;
  end
  else begin
    clk_cnt <= clk_cnt + 16'd1;
  end
end


always @(negedge clkout) begin
	int_v<=datain/7'd100;
	frac_v<=datain%7'd100;
	if(!init) begin
		cnt_init<=cnt_init+1'b1;
		case(cnt_init)
		11'd5: begin R0<=32'b0_00000000_10100000_000000000000_000; end
		11'd1010: begin tx_send <= 1'b1; dataint<=R5; end
		11'd1046: begin tx_send <= 1'b0; end
		11'd1110: begin tx_send <= 1'b1; dataint<=R4; end
		11'd1146: begin tx_send <= 1'b0; end
		11'd1210: begin tx_send <= 1'b1; dataint<=R3; end
		11'd1246: begin tx_send <= 1'b0; end
		11'd1310: begin tx_send <= 1'b1; dataint<=R2; end
		11'd1346: begin tx_send <= 1'b0; end
		11'd1410: begin tx_send <= 1'b1; dataint<=R1; end
		11'd1446: begin tx_send <= 1'b0; end
		11'd1510: begin tx_send <= 1'b1; dataint<=R0; end
		11'd1546: begin tx_send <= 1'b0; end
		11'd1610: begin tx_send <= 1'b1; dataint<=R3; end
		11'd1646: begin tx_send <= 1'b0; end
		11'd1650: begin init<=1'b1; end
		endcase
	end
	else begin
		tx_wrsigbuf <= wrsig;
		tx_wrsigrise <= (~tx_wrsigbuf) & wrsig;
		if (tx_wrsigrise && (~tx_idle)) begin
			tx_send <= 1'b1;
			R0[30:15]<=int_v;
			R0[14:3]<=frac_v;
		end
		else if(tx_cnt == 8'd36) begin
			tx_send <= 1'b0;
		end
	end
end

always @(negedge clkout) begin
	if(tx_send == 1'b1) begin
		case(tx_cnt) //产生起始位
		8'd1: begin
			LE<=1'b0;
			tx <= dataint[31];
			cnt_wei<=5'd31;
			tx_idle <= 1'b1;
			tx_cnt <= tx_cnt + 8'd1;
		end
		8'd2,8'd3,8'd4,8'd5,8'd6,8'd7,8'd8,8'd9,8'd10,8'd11,8'd12,8'd13,8'd14,8'd15
		,8'd16,8'd17,8'd18,8'd19,8'd20,8'd21,8'd22,8'd23,8'd24,8'd25,8'd26,8'd27,
		8'd28,8'd29,8'd30,8'd31,8'd32,8'd33: begin
			tx <= dataint[cnt_wei]; //发送数据0 位
			cnt_wei<=cnt_wei-1'b1;
			tx_idle <= 1'b1;
			tx_cnt <= tx_cnt + 8'd1;
		end
		8'd34: begin
			tx <= 1'b1; 
			LE<=1'b1;
			tx_idle <= 1'b0;
			tx_cnt <= tx_cnt + 8'd1;
		end
		default: begin
			tx_cnt <= tx_cnt + 8'd1;
		end
		endcase
	end
	else begin
		tx <= 1'b1;
		LE<=1'b1;
		cnt_wei<=5'd31;
		tx_cnt <= 8'd0;
		tx_idle <= 1'b0;
	end
end

endmodule
module HDMI_in #(
    parameter    INPUT_WIDTH  = 12,
    parameter    OUTPUT_WIDTH = 12
) (
    input                           clk_in,
    input                           rst_n,
    input  [INPUT_WIDTH - 1 : 0]    data_in,
    output [OUTPUT_WIDTH - 1 : 0]   data_out
);

endmodule  //HDMI_in
module HDMI_out #(
    parameter    INPUT_WIDTH  = 12,
    parameter    OUTPUT_WIDTH = 12
) (
    input                           clk_in,
    input                           rst_n,
    input  [INPUT_WIDTH - 1 : 0]    data_in,
    output [OUTPUT_WIDTH - 1 : 0]   data_out
);

endmodule  //HDMI_out
module Motor_driver (
    input         clk_in,
    input         rst_n,
    input         Trig,
    input  [15:0] Meter,

    output  reg   Motor_Control
);

parameter MAIN_FRE  = 50000000;
parameter MOTOR_FRE = 1000;
parameter SET_TIME  = MAIN_FRE/MOTOR_FRE/2;

/***************************************************/
//define the data lock
reg  Trig_SIG = 0;
reg  Trig_SIG_buf = 0;
wire Trig_SIG_pose =  Trig_SIG & ~Trig_SIG_buf;
wire Trig_SIG_nege =  ~Trig_SIG & Trig_SIG_buf;

always@(posedge clk_in) begin
    Trig_SIG <= Trig;
    Trig_SIG_buf <= Trig_SIG;
end
/***************************************************/

/***************************************************/
//define the time counter
reg [15:0]      cnt0 = 0;
reg             Motor_Control_r = 0;

always@(posedge clk_in) begin
    if (cnt0 == SET_TIME) begin
        cnt0 <= 15'd0;                   
        Motor_Control_r <= ~Motor_Control_r;
    end
    else
        cnt0 <= cnt0 + 1'd1;          
end
/***************************************************/

/***************************************************/
//define the data lock
reg  motor_sig = 0;
reg  motor_sig_buf = 0;
wire motor_sig_pose =  motor_sig & ~motor_sig_buf;
wire motor_sig_nege =  ~motor_sig & motor_sig_buf;
always@(posedge clk_in) begin
    motor_sig <= Motor_Control_r;
    motor_sig_buf <= motor_sig;
end
/***************************************************/

/***************************************************/
//define the time counter
reg [15:0]      cnt1 = 0;
reg             CNT_CE = 0;
always@(posedge clk_in) begin
	if (Trig_SIG_pose) begin
		CNT_CE <= 1'd1;
	end
	else if(cnt1 == Meter) begin
		if (motor_sig_nege) begin
			CNT_CE <= 1'd0;
		end
		else begin
			CNT_CE <= CNT_CE;
		end
	end
	else begin
		CNT_CE <= CNT_CE;
	end
end
/***************************************************/
reg             MOTOR_CE = 0;
always @(posedge clk_in) begin
	if (CNT_CE) begin
		if (motor_sig_pose) begin
	    	cnt1 <= cnt1 + 1'd1;            //cnt1 counter = cnt1 counter + 1
	        MOTOR_CE <= 1'd1;
		end
		else begin
			MOTOR_CE <= MOTOR_CE;
		end
	end
	else begin
		cnt1 <= 16'd0; 
		MOTOR_CE <= 1'd0;
	end
end

always @(*) begin
	case (MOTOR_CE) 
	    1'b0    :   begin Motor_Control <= 1'b0; end
	    1'b1    :   begin Motor_Control <= Motor_Control_r; end
	    default :   begin Motor_Control <= 1'b0; end
	endcase
end


endmodule
module DAC_PWM #
(
	parameter MAIN_FRE = 500,
	parameter PWM_FRE  = 1000,
	parameter PHASE_WIDTH = 32
)
(
    input                    clk_in,
    input                    RST,
    output                   DAC_PWM,
    input  [PHASE_WIDTH-1:0] data_in
);

localparam [PHASE_WIDTH-1:0] DC_ADD   = (2**(PHASE_WIDTH-1)) - 1;
localparam [PHASE_WIDTH-1:0] FRE_WORD = (2**PHASE_WIDTH)*PWM_FRE/(MAIN_FRE*1000);

reg [PHASE_WIDTH-1:0] addr_r = 0;
always @(posedge clk_in) begin
	if (RST) 
		addr_r <= 0;
	else 
		addr_r <= addr_r + FRE_WORD;
end

reg [PHASE_WIDTH-1:0] duty_r = 0;
always @(posedge clk_in) begin
	if (RST) 
		duty_r <= 32'd0;
	else 
		duty_r <= $signed(data_in) + DC_ADD;
end

assign DAC_PWM = (addr_r <= duty_r) ? 1'b1 : 1'b0;

endmodule
module DA9767 #
(
	parameter INPUT_WIDTH = 14,
	parameter INPUT_STYLE = "signed",
	parameter ALIGNED_STYLE = "LSB"
)
(
	input 			               clk_in,
    input   [INPUT_WIDTH - 1 : 0]  DA_data,
	output						   DA_clk,
	output			               DA_wrt,
	output  [13:0] 	               DA_out
);

generate if(INPUT_STYLE == "signed") begin : OUTPUT
	if (INPUT_WIDTH < 14) begin
		localparam DATA_WIDTH = 14 - INPUT_WIDTH;
		if (ALIGNED_STYLE == "LSB") begin
			assign 	DA_out = $signed({{DATA_WIDTH{DA_data[INPUT_WIDTH-1]}},DA_data}) 
											+ $signed(14'd8192);
		end
		else if(ALIGNED_STYLE == "MSB") begin
			reg [DATA_WIDTH - 1 : 0 ] data_buf = 0;
			assign 	DA_out = $signed({DA_data,data_buf}) + $signed(14'd8192);
		end
	end
	else begin
		assign 	DA_out = $signed(DA_data[INPUT_WIDTH - 1 : INPUT_WIDTH - 14]) + $signed(14'd8192);
	end
end
else if(INPUT_STYLE == "unsigned") begin
	if (INPUT_WIDTH < 14) begin
		localparam DATA_WIDTH = 14 - INPUT_WIDTH;
		if (ALIGNED_STYLE == "LSB") begin
			assign 	DA_out = {{DATA_WIDTH{DA_data[INPUT_WIDTH-1]}},DA_data};
		end
		else if(ALIGNED_STYLE == "MSB") begin
			reg [DATA_WIDTH - 1 : 0 ] data_buf = 0;
			assign 	DA_out = {DA_data,data_buf};
		end
	end
	else begin
		assign 	DA_out = DA_data[INPUT_WIDTH - 1 : INPUT_WIDTH - 14];
	end
end
endgenerate	

assign 				DA_clk = clk_in;
assign 				DA_wrt = clk_in;

endmodule
module DAC3162_driver (
    input               clk_in,
    input               clk_div,

    input    [11:0]     DA3162_CH1,
    input    [11:0]     DA3162_CH2,
    /*DAC*/
    output   [11:0]     dac_data_p,
    output   [11:0]     dac_data_n,
    output              dac_clk_p,
    output              dac_clk_n,
    output              dac_sleep
);

assign dac_sleep = 1'd1;

reg  [11:0] dac_a_int  = 0;
reg  [11:0] dac_b_int  = 0;
reg  [11:0] dac_a_intt = 0;
reg  [11:0] dac_b_intt = 0;

reg  [1:0]  cnt_clk = 0;
reg  [3:0]  power_on_rst_cnt = 4'h0;
reg         power_on_rst = 1;

always @ (posedge clk_in) begin
    dac_a_int<=DA3162_CH1 + 12'b100000000000;
    dac_b_int<=DA3162_CH2 + 12'b100000000000;
    dac_a_intt<=dac_a_int;
    dac_b_intt<=dac_b_int;
end

always @ (posedge clk_div) begin
    if (power_on_rst_cnt == 4'hf) begin
        power_on_rst_cnt <= power_on_rst_cnt;
        power_on_rst <= 0;
    end
    else begin
        power_on_rst_cnt <= power_on_rst_cnt + 1;
        power_on_rst <= 1;
    end
end

LVDS_DDR_clk  DAC3162_clk_u (
    .data_out_from_device ( 4'b0101      ), // input [3:0] data_out_from_device
    .data_out_to_pins_p   ( dac_clk_p    ), // output [0:0] data_out_to_pins_p
    .data_out_to_pins_n   ( dac_clk_n    ), // output [0:0] data_out_to_pins_n
    .clk_in               ( clk_in       ), // input clk_in                            
    .clk_div_in           ( clk_div      ), // input clk_div_in                        
    .io_reset             ( power_on_rst )  // input io_reset
); 

// input  [47:0] data_out_from_device
LVDS_DDR_data  DAC3162_data_u (                                            
    .clk_in               ( clk_in        ), // input clk_in
    .clk_div_in           ( clk_div       ), // input clk_div_in
    .data_out_from_device ({dac_a_int,dac_b_int,dac_a_intt,dac_b_intt}  ), 
    .data_out_to_pins_p   ( dac_data_p    ), // output [11:0] data_out_to_pins_p
    .data_out_to_pins_n   ( dac_data_n    ), // output [11:0] data_out_to_pins_n
    .io_reset             ( power_on_rst  )  // input io_reset
); 

endmodule
module ADS412x_driver(
    // input         sys_rst_n,
    input         user_clk,
    output [11:0] user_rd_data,
    
    output        adc_sclk,  // sclk 
    output        adc_sdata, // sda
    output        adc_reset,
    output        adc_sen,
    input  [11:0] adc_data,
    input         adc_clk,
    output        adc_samp_clk
);

wire sys_rst_n;
assign sys_rst_n = 1;

wire        adc_config_done;
wire        rst_n;
reg  [11:0] adc_data_r;
reg  [11:0] adc_data_rr;

assign adc_samp_clk=user_clk;
assign rst_n = ((adc_config_done == 1'b1) && (sys_rst_n == 1'b1)) ? 1'b1 : 1'b0;

assign user_rd_data=adc_data_rr;////

ADC_CFG u_ADS4128_CFG(
        .clk      ( user_clk        ),
        .rstn     ( sys_rst_n       ),
        .sclk     ( adc_sclk        ),
        .sdata    ( adc_sdata       ),
        .sen      ( adc_sen         ),
        .adc_rst  ( adc_reset       ),
        .cfg_done ( adc_config_done )
);

always @ (posedge adc_clk) begin
    if (rst_n == 1'b0) begin
        adc_data_r  <= 12'h000;
        adc_data_rr <= 12'h000;
    end
    else begin
        adc_data_r  <= adc_data;
        adc_data_rr <= adc_data_r + 12'b1000_0000_0000;
    end
end

endmodule
module AD6645
(
	input 		clk_in,
	input 		rst_n,
	input  [13:0] 	AD_data,
	output [13:0] 	wave_CH
);
reg [13:0] 	wave_CH_buf;
always@(posedge clk_in or negedge rst_n)
begin
	if(!rst_n)
		wave_CH_buf <= 14'd0;
	else
		wave_CH_buf <= AD_data;
end
assign wave_CH = wave_CH_buf - 14'd1700;
endmodule
module AD9226_driver #
(
	parameter signed CH_offset = 27
)
(
	input 			clk_in,
	input 			rst_n,
	input   [11:0] 	AD_data,
	output 			AD_clk,
	output  [11:0] 	wave_CH
);

reg signed [11:0] wave_CH_buf;
always@(posedge clk_in or negedge rst_n) begin
	if(!rst_n)
		wave_CH_buf <= 12'd0;
	else begin
		wave_CH_buf[11] <= AD_data[0];
		wave_CH_buf[10] <= AD_data[1];
		wave_CH_buf[9]  <= AD_data[2];
		wave_CH_buf[8]  <= AD_data[3];
		wave_CH_buf[7]  <= AD_data[4];
		wave_CH_buf[6]  <= AD_data[5];
		wave_CH_buf[5]  <= AD_data[6];
		wave_CH_buf[4]  <= AD_data[7];
		wave_CH_buf[3]  <= AD_data[8];
		wave_CH_buf[2]  <= AD_data[9];
		wave_CH_buf[1]  <= AD_data[10];
		wave_CH_buf[0]  <= AD_data[11];
	end
end

assign wave_CH = $signed(wave_CH_buf) + $signed(CH_offset);
assign AD_clk  = clk_in;

endmodule
module cic_int #(
  parameter DATA_WIDTH = 12,
  parameter STAGE_WIDTH = 1,
  parameter NUM_STAGES = 1
) (
  input clk,
  input [NUM_STAGES-1:0] ce,
  input [DATA_WIDTH-1:0] data_in,
  output [DATA_WIDTH-1:0] data_out
);

reg [DATA_WIDTH-1:0] state = 'h00;
wire [DATA_WIDTH-1:0] sum;
wire [DATA_WIDTH-1:0] mask;

assign data_out = state;
assign sum = (data_in & mask) + (state & mask);
generate
genvar i;

for (i = 0; i < NUM_STAGES; i = i + 1) begin
  localparam j = NUM_STAGES - i - 1;
  localparam H = DATA_WIDTH - STAGE_WIDTH * i - 1;
  localparam L = j == 0 ? 0 : DATA_WIDTH - STAGE_WIDTH * (i+1);

  assign mask[H:L] = {{H-L{1'b1}},j != 0 ? ce[j] : 1'b1};

  always @(posedge clk) begin
    if (ce[j] == 1'b1) begin
      state[H:L] <= sum[H:L];
    end
  end
end

endgenerate

endmodule
module cic_comb #(
  parameter DATA_WIDTH = 32,
  parameter SEQ = 1,
  parameter STAGE_WIDTH = 1,
  parameter NUM_STAGES = 1
) (
  input clk,
  input ce,
  input [NUM_STAGES-1:0] enable,
  input [DATA_WIDTH-1:0] data_in,
  output [DATA_WIDTH-1:0] data_out
);

reg [SEQ-1:0] storage[0:DATA_WIDTH-1];
reg [DATA_WIDTH-1:0] state = 'h00;

reg [2:0] counter = 'h00;
reg active = 1'b0;

integer x;

initial begin
  for (x = 0; x < DATA_WIDTH; x = x + 1) begin
    storage[x] = 'h00;
  end
end

generate if (SEQ != 1) begin

always @(posedge clk) begin
  if (ce == 1'b1) begin
    counter <= SEQ-1;
    active <= 1'b1;
  end else if (active == 1'b1) begin
    counter <= counter - 1'b1;
    if (counter == 'h1) begin
      active <= 1'b0;
    end
  end
end

end
endgenerate

wire [DATA_WIDTH-1:0] mask;
reg [DATA_WIDTH-1:0] data_in_seq;
wire [DATA_WIDTH-1:0] storage_out;
wire [DATA_WIDTH-1:0] diff = (data_in_seq | ~mask) - (storage_out & mask);

always @(*) begin
  if (ce == 1'b1) begin
    data_in_seq <= data_in;
  end else begin
    data_in_seq <= SEQ != 1 ? state : 'h00;
  end
end

generate
genvar i, j;

for (j = 0; j < NUM_STAGES; j = j + 1) begin
  localparam k = NUM_STAGES - j - 1;
  localparam H = DATA_WIDTH - STAGE_WIDTH * j - 1;
  localparam L = k == 0 ? 0 : DATA_WIDTH - STAGE_WIDTH * (j+1);

  assign mask[H:L] = {{H-L{1'b1}},k != 0 ? enable[k] : 1'b1};

  for (i = L; i <= H; i = i + 1) begin: shift_r
    always @(posedge clk) begin
      if (enable[k] == 1'b1 && (ce == 1'b1 || active == 1'b1)) begin
        if (SEQ > 1) begin
          storage[i] <= {storage[i][SEQ-2:0],data_in_seq[i]};
        end else begin
          storage[i] <= data_in_seq[i];
        end
      end
    end

    assign storage_out[i] = storage[i][SEQ-1];

  end

  always @(posedge clk) begin
    if (enable[k] == 1'b1 && (ce == 1'b1 || active == 1'b1)) begin
      state[H:L] <= diff[H:L];
    end
  end
end

endgenerate

assign data_out = state;

endmodule
module axi_ad9625_channel (

  // adc interface

  input                   adc_clk,
  input                   adc_rst,
  input       [191:0]     adc_data,
  input                   adc_or,

  // channel interface

  output      [255:0]     adc_dfmt_data,
  output                  adc_enable,
  output                  up_adc_pn_err,
  output                  up_adc_pn_oos,
  output                  up_adc_or,

  // processor interface

  input                   up_rstn,
  input                   up_clk,
  input                   up_wreq,
  input       [ 13:0]     up_waddr,
  input       [ 31:0]     up_wdata,
  output                  up_wack,
  input                   up_rreq,
  input       [ 13:0]     up_raddr,
  output      [ 31:0]     up_rdata,
  output                  up_rack);

  // internal signals

  wire                    adc_pn_oos_s;
  wire                    adc_pn_err_s;
  wire                    adc_dfmt_enable_s;
  wire                    adc_dfmt_type_s;
  wire                    adc_dfmt_se_s;
  wire        [  3:0]     adc_pnseq_sel_s;

  // instantiations

  axi_ad9625_pnmon i_pnmon (
    .adc_clk (adc_clk),
    .adc_data (adc_data),
    .adc_pn_oos (adc_pn_oos_s),
    .adc_pn_err (adc_pn_err_s),
    .adc_pnseq_sel (adc_pnseq_sel_s));

  genvar n;
  generate
  for (n = 0; n < 16; n = n + 1) begin: g_ad_datafmt_1
  ad_datafmt #(.DATA_WIDTH(12)) i_ad_datafmt (
    .clk (adc_clk),
    .valid (1'b1),
    .data (adc_data[n*12+11:n*12]),
    .valid_out (),
    .data_out (adc_dfmt_data[n*16+15:n*16]),
    .dfmt_enable (adc_dfmt_enable_s),
    .dfmt_type (adc_dfmt_type_s),
    .dfmt_se (adc_dfmt_se_s));
  end
  endgenerate

  up_adc_channel #(
    .COMMON_ID(6'h1),
    .CHANNEL_ID(0),
    .USERPORTS_DISABLE(1),
    .DATAFORMAT_DISABLE(0),
    .DCFILTER_DISABLE(1),
    .IQCORRECTION_DISABLE(1))
  i_up_adc_channel (
    .adc_clk (adc_clk),
    .adc_rst (adc_rst),
    .adc_enable (adc_enable),
    .adc_iqcor_enb (),
    .adc_dcfilt_enb (),
    .adc_dfmt_se (adc_dfmt_se_s),
    .adc_dfmt_type (adc_dfmt_type_s),
    .adc_dfmt_enable (adc_dfmt_enable_s),
    .adc_dcfilt_offset (),
    .adc_dcfilt_coeff (),
    .adc_iqcor_coeff_1 (),
    .adc_iqcor_coeff_2 (),
    .adc_pnseq_sel (adc_pnseq_sel_s),
    .adc_data_sel (),
    .adc_pn_err (adc_pn_err_s),
    .adc_pn_oos (adc_pn_oos_s),
    .adc_or (adc_or),
    .up_adc_pn_err (up_adc_pn_err),
    .up_adc_pn_oos (up_adc_pn_oos),
    .up_adc_or (up_adc_or),
    .up_usr_datatype_be (),
    .up_usr_datatype_signed (),
    .up_usr_datatype_shift (),
    .up_usr_datatype_total_bits (),
    .up_usr_datatype_bits (),
    .up_usr_decimation_m (),
    .up_usr_decimation_n (),
    .adc_usr_datatype_be (1'b0),
    .adc_usr_datatype_signed (1'b1),
    .adc_usr_datatype_shift (8'd0),
    .adc_usr_datatype_total_bits (8'd16),
    .adc_usr_datatype_bits (8'd16),
    .adc_usr_decimation_m (16'd1),
    .adc_usr_decimation_n (16'd1),
    .up_rstn (up_rstn),
    .up_clk (up_clk),
    .up_wreq (up_wreq),
    .up_waddr (up_waddr),
    .up_wdata (up_wdata),
    .up_wack (up_wack),
    .up_rreq (up_rreq),
    .up_raddr (up_raddr),
    .up_rdata (up_rdata),
    .up_rack (up_rack));

endmodule
module adrv9001_aligner4 (
  input             clk,
  input             rst,
  input       [3:0] idata,
  input             ivalid,
  input       [3:0] strobe,
  output reg  [3:0] odata,
  output            ovalid
);

  reg [3:0] idata_d = 'b0;
  reg       ivalid_d = 'b0;

  always @(posedge clk) begin
    if (rst) begin
      idata_d <= 'h0;
    end else if (ivalid) begin
      idata_d <= idata;
    end
    ivalid_d <= ivalid;
  end

  reg [1:0] phase = 'h0;
  always @(posedge clk) begin
    if (rst) begin
      phase <= 0;
    end else if (ivalid) begin
      if ((strobe != 'b1111) && (strobe != 'b0000)) begin
        casex (strobe)
          'b1xxx  : phase <= 0;
          'b01xx  : phase <= 1;
          'b001x  : phase <= 2;
          'b0001  : phase <= 3;
          default : phase <= phase;
        endcase
      end
    end
  end

  always @(posedge clk) begin
    case (phase)
      0 : odata <= idata_d;
      1 : odata <= {idata_d[2:0],idata[3:3]};
      2 : odata <= {idata_d[1:0],idata[3:2]};
      3 : odata <= {idata_d[0:0],idata[3:1]};
    endcase
  end
  assign ovalid = ivalid_d;

endmodule
module adrv9001_pack #(
  parameter WIDTH = 8
)(
  input                      clk,    // Input clock
  input                      rst,
  input                      sof,    // Start of frame indicator marking the MS Beat
  input       [WIDTH-1:0]    idata,  // Input data beat
  input                      ivalid, // Input data qualifier
  output reg  [WIDTH*2-1:0]  odata,  // Output data beat
  output reg                 ovalid, // Output data qualifier
  output reg                 osof    // Output Start of frame indicator
);

  reg  [WIDTH-1:0] idata_d = {WIDTH{1'b0}};
  always @(posedge clk) begin
    if (ivalid) begin
      idata_d <= idata;
    end
  end

  // Single clock mode:
  reg [6:0] sof_d = 7'b000;
  // Use sof_d[2] for frame size of 4 beats
  // Use sof_d[4,6] for frame size of 8 beats
  always @(posedge clk) begin
    if (rst) begin
      sof_d <= 7'b0;
    end else if (ivalid) begin
      sof_d <= {sof_d[5:0],sof};
    end
    if (ivalid &(sof_d[0] | sof_d[2] | sof_d[4] | sof_d[6])) begin
      odata <= {idata_d,idata};
    end
    ovalid <= ivalid & (sof_d[0] | sof_d[2] | sof_d[4] | sof_d[6]);
    osof <= ivalid & sof_d[0];
  end

endmodule
module adrv9001_aligner8 (
  input             clk,
  input             rst,
  input       [7:0] idata,
  input             ivalid,
  input       [7:0] strobe,
  output reg  [7:0] odata,
  output            ovalid
);

  reg [7:0] idata_d = 'b0;
  reg       ivalid_d = 'b0;

  always @(posedge clk) begin
    if (rst) begin
      idata_d <= 'h0;
    end else if (ivalid) begin
      idata_d <= idata;
    end
    ivalid_d <= ivalid;
  end

  reg [2:0] phase = 'h0;
  always @(posedge clk) begin
    if (rst) begin
      phase <= 0;
    end if (ivalid) begin
      if ((strobe != 'b1111_1111) && (strobe != 'b0000_0000)) begin
        casex (strobe)
          'b1xxx_xxxx : phase <= 0;
          'b01xx_xxxx : phase <= 1;
          'b001x_xxxx : phase <= 2;
          'b0001_xxxx : phase <= 3;
          'b0000_1xxx : phase <= 4;
          'b0000_01xx : phase <= 5;
          'b0000_001x : phase <= 6;
          'b0000_0001 : phase <= 7;
          default     : phase <= phase;
        endcase
      end
    end
  end

  always @(posedge clk) begin
    case (phase)
      0 : odata <= idata_d;
      1 : odata <= {idata_d[6:0],idata[7:7]};
      2 : odata <= {idata_d[5:0],idata[7:6]};
      3 : odata <= {idata_d[4:0],idata[7:5]};
      4 : odata <= {idata_d[3:0],idata[7:4]};
      5 : odata <= {idata_d[2:0],idata[7:3]};
      6 : odata <= {idata_d[1:0],idata[7:2]};
      7 : odata <= {idata_d[0:0],idata[7:1]};
    endcase
  end
  assign ovalid = ivalid_d;

endmodule
module sysid_rom#(
  parameter ROM_WIDTH = 32,
  parameter ROM_ADDR_BITS = 6,
  parameter PATH_TO_FILE = "path_to_mem_init_file" )(

  input                             clk,
  input        [ROM_ADDR_BITS-1:0]  rom_addr,
  output  reg  [ROM_WIDTH-1:0]      rom_data);

reg [ROM_WIDTH-1:0] lut_rom [(2**ROM_ADDR_BITS)-1:0];

initial begin
  $readmemh(PATH_TO_FILE, lut_rom, 0, (2**ROM_ADDR_BITS)-1);
end

always @(posedge clk) begin
  rom_data = lut_rom[rom_addr];
end

endmodule