dakies/OSS_Verilog huggingface dataset:
module tim1_tim_top(
  etb_tim1_trig_en_off,
  etb_tim1_trig_en_on,
  etb_tim2_trig_en_off,
  etb_tim2_trig_en_on,
  intr,
  paddr,
  pclk,
  penable,
  prdata,
  presetn,
  psel,
  pwdata,
  pwrite,
  scan_mode,
  tim1_etb_trig,
  tim2_etb_trig
);
input           etb_tim1_trig_en_off; 
input           etb_tim1_trig_en_on; 
input           etb_tim2_trig_en_off; 
input           etb_tim2_trig_en_on; 
input   [31:0]  paddr;               
input           pclk;                
input           penable;             
input           presetn;             
input           psel;                
input   [31:0]  pwdata;              
input           pwrite;              
input           scan_mode;           
output  [1 :0]  intr;                
output  [31:0]  prdata;              
output          tim1_etb_trig;       
output          tim2_etb_trig;       
wire            etb_tim1_trig_en_off; 
wire            etb_tim1_trig_en_on; 
wire            etb_tim2_trig_en_off; 
wire            etb_tim2_trig_en_on; 
wire    [1 :0]  intr;                
wire    [31:0]  paddr;               
wire            pclk;                
wire            penable;             
wire    [31:0]  prdata;              
wire            presetn;             
wire            psel;                
wire    [31:0]  pwdata;              
wire            pwrite;              
wire            scan_mode;           
wire            tim1_etb_trig;       
wire            tim2_etb_trig;       
wire    [1 :0]  timer_en;            
wire            timer_int_flag;      
wire            timer_int_flag_n;    
wire    [1 :0]  timer_int_n;         
wire    [1 :0]  timertrig;           
timers_top  x_timers_top (
  .etb_tim1_trig_en_off (etb_tim1_trig_en_off),
  .etb_tim1_trig_en_on  (etb_tim1_trig_en_on ),
  .etb_tim2_trig_en_off (etb_tim2_trig_en_off),
  .etb_tim2_trig_en_on  (etb_tim2_trig_en_on ),
  .paddr                (paddr[7:0]          ),
  .pclk                 (pclk                ),
  .penable              (penable             ),
  .prdata               (prdata              ),
  .presetn              (presetn             ),
  .psel                 (psel                ),
  .pwdata               (pwdata              ),
  .pwrite               (pwrite              ),
  .scan_mode            (scan_mode           ),
  .tim1_etb_trig        (tim1_etb_trig       ),
  .tim2_etb_trig        (tim2_etb_trig       ),
  .timer_1_clk          (pclk                ),
  .timer_1_resetn       (presetn             ),
  .timer_2_clk          (pclk                ),
  .timer_2_resetn       (presetn             ),
  .timer_en             (timer_en            ),
  .timer_int            (intr                ),
  .timer_int_flag       (timer_int_flag      ),
  .timer_int_flag_n     (timer_int_flag_n    ),
  .timer_int_n          (timer_int_n         ),
  .timertrig            (timertrig           )
);
endmodule
module tim4_sec_top(
  etb_tim1_trig_en_off,
  etb_tim1_trig_en_on,
  etb_tim2_trig_en_off,
  etb_tim2_trig_en_on,
  intr,
  paddr,
  pclk,
  penable,
  pprot,
  prdata,
  presetn,
  psel,
  pwdata,
  pwrite,
  scan_mode,
  tim1_etb_trig,
  tim2_etb_trig,
  tipc_tim4_trust
);
input           etb_tim1_trig_en_off; 
input           etb_tim1_trig_en_on; 
input           etb_tim2_trig_en_off; 
input           etb_tim2_trig_en_on; 
input   [31:0]  paddr;               
input           pclk;                
input           penable;             
input   [2 :0]  pprot;               
input           presetn;             
input           psel;                
input   [31:0]  pwdata;              
input           pwrite;              
input           scan_mode;           
input           tipc_tim4_trust;     
output  [1 :0]  intr;                
output  [31:0]  prdata;              
output          tim1_etb_trig;       
output          tim2_etb_trig;       
wire            etb_tim1_trig_en_off; 
wire            etb_tim1_trig_en_on; 
wire            etb_tim2_trig_en_off; 
wire            etb_tim2_trig_en_on; 
wire    [31:0]  i_prdata;            
wire            i_psel;              
wire            i_pwrite;            
wire    [1 :0]  intr;                
wire    [31:0]  paddr;               
wire            pclk;                
wire            penable;             
wire    [2 :0]  pprot;               
wire    [31:0]  prdata;              
wire            presetn;             
wire            psel;                
wire    [31:0]  pwdata;              
wire            pwrite;              
wire            scan_mode;           
wire            tim1_etb_trig;       
wire            tim2_etb_trig;       
wire            tipc_tim4_trust;     
tim4_tim_top  x_tim4_tim_top (
  .etb_tim1_trig_en_off (etb_tim1_trig_en_off),
  .etb_tim1_trig_en_on  (etb_tim1_trig_en_on ),
  .etb_tim2_trig_en_off (etb_tim2_trig_en_off),
  .etb_tim2_trig_en_on  (etb_tim2_trig_en_on ),
  .intr                 (intr                ),
  .paddr                (paddr               ),
  .pclk                 (pclk                ),
  .penable              (penable             ),
  .prdata               (i_prdata            ),
  .presetn              (presetn             ),
  .psel                 (i_psel              ),
  .pwdata               (pwdata              ),
  .pwrite               (i_pwrite            ),
  .scan_mode            (scan_mode           ),
  .tim1_etb_trig        (tim1_etb_trig       ),
  .tim2_etb_trig        (tim2_etb_trig       )
);
assign prdata[31:0] = i_prdata[31:0];
assign i_pwrite = pwrite;
assign i_psel = psel;

endmodule
module tim4_tim_top(
  etb_tim1_trig_en_off,
  etb_tim1_trig_en_on,
  etb_tim2_trig_en_off,
  etb_tim2_trig_en_on,
  intr,
  paddr,
  pclk,
  penable,
  prdata,
  presetn,
  psel,
  pwdata,
  pwrite,
  scan_mode,
  tim1_etb_trig,
  tim2_etb_trig
);
input           etb_tim1_trig_en_off; 
input           etb_tim1_trig_en_on; 
input           etb_tim2_trig_en_off; 
input           etb_tim2_trig_en_on; 
input   [31:0]  paddr;               
input           pclk;                
input           penable;             
input           presetn;             
input           psel;                
input   [31:0]  pwdata;              
input           pwrite;              
input           scan_mode;           
output  [1 :0]  intr;                
output  [31:0]  prdata;              
output          tim1_etb_trig;       
output          tim2_etb_trig;       
wire            etb_tim1_trig_en_off; 
wire            etb_tim1_trig_en_on; 
wire            etb_tim2_trig_en_off; 
wire            etb_tim2_trig_en_on; 
wire    [1 :0]  intr;                
wire    [31:0]  paddr;               
wire            pclk;                
wire            penable;             
wire    [31:0]  prdata;              
wire            presetn;             
wire            psel;                
wire    [31:0]  pwdata;              
wire            pwrite;              
wire            scan_mode;           
wire            tim1_etb_trig;       
wire            tim2_etb_trig;       
wire    [1 :0]  timer_en;            
wire            timer_int_flag;      
wire            timer_int_flag_n;    
wire    [1 :0]  timer_int_n;         
wire    [1 :0]  timertrig;           
timers_top  x_timers_top (
  .etb_tim1_trig_en_off (etb_tim1_trig_en_off),
  .etb_tim1_trig_en_on  (etb_tim1_trig_en_on ),
  .etb_tim2_trig_en_off (etb_tim2_trig_en_off),
  .etb_tim2_trig_en_on  (etb_tim2_trig_en_on ),
  .paddr                (paddr[7:0]          ),
  .pclk                 (pclk                ),
  .penable              (penable             ),
  .prdata               (prdata              ),
  .presetn              (presetn             ),
  .psel                 (psel                ),
  .pwdata               (pwdata              ),
  .pwrite               (pwrite              ),
  .scan_mode            (scan_mode           ),
  .tim1_etb_trig        (tim1_etb_trig       ),
  .tim2_etb_trig        (tim2_etb_trig       ),
  .timer_1_clk          (pclk                ),
  .timer_1_resetn       (presetn             ),
  .timer_2_clk          (pclk                ),
  .timer_2_resetn       (presetn             ),
  .timer_en             (timer_en            ),
  .timer_int            (intr                ),
  .timer_int_flag       (timer_int_flag      ),
  .timer_int_flag_n     (timer_int_flag_n    ),
  .timer_int_n          (timer_int_n         ),
  .timertrig            (timertrig           )
);
endmodule
module tim3_sec_top(
  etb_tim1_trig_en_off,
  etb_tim1_trig_en_on,
  etb_tim2_trig_en_off,
  etb_tim2_trig_en_on,
  intr,
  paddr,
  pclk,
  penable,
  pprot,
  prdata,
  presetn,
  psel,
  pwdata,
  pwrite,
  scan_mode,
  tim1_etb_trig,
  tim2_etb_trig,
  tipc_tim3_trust
);
input           etb_tim1_trig_en_off; 
input           etb_tim1_trig_en_on; 
input           etb_tim2_trig_en_off; 
input           etb_tim2_trig_en_on; 
input   [31:0]  paddr;               
input           pclk;                
input           penable;             
input   [2 :0]  pprot;               
input           presetn;             
input           psel;                
input   [31:0]  pwdata;              
input           pwrite;              
input           scan_mode;           
input           tipc_tim3_trust;     
output  [1 :0]  intr;                
output  [31:0]  prdata;              
output          tim1_etb_trig;       
output          tim2_etb_trig;       
wire            etb_tim1_trig_en_off; 
wire            etb_tim1_trig_en_on; 
wire            etb_tim2_trig_en_off; 
wire            etb_tim2_trig_en_on; 
wire    [31:0]  i_prdata;            
wire            i_psel;              
wire            i_pwrite;            
wire    [1 :0]  intr;                
wire    [31:0]  paddr;               
wire            pclk;                
wire            penable;             
wire    [2 :0]  pprot;               
wire    [31:0]  prdata;              
wire            presetn;             
wire            psel;                
wire    [31:0]  pwdata;              
wire            pwrite;              
wire            scan_mode;           
wire            tim1_etb_trig;       
wire            tim2_etb_trig;       
wire            tipc_tim3_trust;     
tim3_tim_top  x_tim3_tim_top (
  .etb_tim1_trig_en_off (etb_tim1_trig_en_off),
  .etb_tim1_trig_en_on  (etb_tim1_trig_en_on ),
  .etb_tim2_trig_en_off (etb_tim2_trig_en_off),
  .etb_tim2_trig_en_on  (etb_tim2_trig_en_on ),
  .intr                 (intr                ),
  .paddr                (paddr               ),
  .pclk                 (pclk                ),
  .penable              (penable             ),
  .prdata               (i_prdata            ),
  .presetn              (presetn             ),
  .psel                 (i_psel              ),
  .pwdata               (pwdata              ),
  .pwrite               (i_pwrite            ),
  .scan_mode            (scan_mode           ),
  .tim1_etb_trig        (tim1_etb_trig       ),
  .tim2_etb_trig        (tim2_etb_trig       )
);
assign prdata[31:0] = i_prdata[31:0];
assign i_pwrite = pwrite;
assign i_psel = psel;

endmodule
module tim3_tim_top(
  etb_tim1_trig_en_off,
  etb_tim1_trig_en_on,
  etb_tim2_trig_en_off,
  etb_tim2_trig_en_on,
  intr,
  paddr,
  pclk,
  penable,
  prdata,
  presetn,
  psel,
  pwdata,
  pwrite,
  scan_mode,
  tim1_etb_trig,
  tim2_etb_trig
);
input           etb_tim1_trig_en_off; 
input           etb_tim1_trig_en_on; 
input           etb_tim2_trig_en_off; 
input           etb_tim2_trig_en_on; 
input   [31:0]  paddr;               
input           pclk;                
input           penable;             
input           presetn;             
input           psel;                
input   [31:0]  pwdata;              
input           pwrite;              
input           scan_mode;           
output  [1 :0]  intr;                
output  [31:0]  prdata;              
output          tim1_etb_trig;       
output          tim2_etb_trig;       
wire            etb_tim1_trig_en_off; 
wire            etb_tim1_trig_en_on; 
wire            etb_tim2_trig_en_off; 
wire            etb_tim2_trig_en_on; 
wire    [1 :0]  intr;                
wire    [31:0]  paddr;               
wire            pclk;                
wire            penable;             
wire    [31:0]  prdata;              
wire            presetn;             
wire            psel;                
wire    [31:0]  pwdata;              
wire            pwrite;              
wire            scan_mode;           
wire            tim1_etb_trig;       
wire            tim2_etb_trig;       
wire    [1 :0]  timer_en;            
wire            timer_int_flag;      
wire            timer_int_flag_n;    
wire    [1 :0]  timer_int_n;         
wire    [1 :0]  timertrig;           
timers_top  x_timers_top (
  .etb_tim1_trig_en_off (etb_tim1_trig_en_off),
  .etb_tim1_trig_en_on  (etb_tim1_trig_en_on ),
  .etb_tim2_trig_en_off (etb_tim2_trig_en_off),
  .etb_tim2_trig_en_on  (etb_tim2_trig_en_on ),
  .paddr                (paddr[7:0]          ),
  .pclk                 (pclk                ),
  .penable              (penable             ),
  .prdata               (prdata              ),
  .presetn              (presetn             ),
  .psel                 (psel                ),
  .pwdata               (pwdata              ),
  .pwrite               (pwrite              ),
  .scan_mode            (scan_mode           ),
  .tim1_etb_trig        (tim1_etb_trig       ),
  .tim2_etb_trig        (tim2_etb_trig       ),
  .timer_1_clk          (pclk                ),
  .timer_1_resetn       (presetn             ),
  .timer_2_clk          (pclk                ),
  .timer_2_resetn       (presetn             ),
  .timer_en             (timer_en            ),
  .timer_int            (intr                ),
  .timer_int_flag       (timer_int_flag      ),
  .timer_int_flag_n     (timer_int_flag_n    ),
  .timer_int_n          (timer_int_n         ),
  .timertrig            (timertrig           )
);
endmodule
module tim2_sec_top(
  etb_tim1_trig_en_off,
  etb_tim1_trig_en_on,
  etb_tim2_trig_en_off,
  etb_tim2_trig_en_on,
  intr,
  paddr,
  pclk,
  penable,
  pprot,
  prdata,
  presetn,
  psel,
  pwdata,
  pwrite,
  scan_mode,
  tim1_etb_trig,
  tim2_etb_trig,
  tipc_tim2_trust
);
input           etb_tim1_trig_en_off; 
input           etb_tim1_trig_en_on; 
input           etb_tim2_trig_en_off; 
input           etb_tim2_trig_en_on; 
input   [31:0]  paddr;               
input           pclk;                
input           penable;             
input   [2 :0]  pprot;               
input           presetn;             
input           psel;                
input   [31:0]  pwdata;              
input           pwrite;              
input           scan_mode;           
input           tipc_tim2_trust;     
output  [1 :0]  intr;                
output  [31:0]  prdata;              
output          tim1_etb_trig;       
output          tim2_etb_trig;       
wire            etb_tim1_trig_en_off; 
wire            etb_tim1_trig_en_on; 
wire            etb_tim2_trig_en_off; 
wire            etb_tim2_trig_en_on; 
wire    [31:0]  i_prdata;            
wire            i_psel;              
wire            i_pwrite;            
wire    [1 :0]  intr;                
wire    [31:0]  paddr;               
wire            pclk;                
wire            penable;             
wire    [2 :0]  pprot;               
wire    [31:0]  prdata;              
wire            presetn;             
wire            psel;                
wire    [31:0]  pwdata;              
wire            pwrite;              
wire            scan_mode;           
wire            tim1_etb_trig;       
wire            tim2_etb_trig;       
wire            tipc_tim2_trust;     
tim2_tim_top  x_tim2_tim_top (
  .etb_tim1_trig_en_off (etb_tim1_trig_en_off),
  .etb_tim1_trig_en_on  (etb_tim1_trig_en_on ),
  .etb_tim2_trig_en_off (etb_tim2_trig_en_off),
  .etb_tim2_trig_en_on  (etb_tim2_trig_en_on ),
  .intr                 (intr                ),
  .paddr                (paddr               ),
  .pclk                 (pclk                ),
  .penable              (penable             ),
  .prdata               (i_prdata            ),
  .presetn              (presetn             ),
  .psel                 (i_psel              ),
  .pwdata               (pwdata              ),
  .pwrite               (i_pwrite            ),
  .scan_mode            (scan_mode           ),
  .tim1_etb_trig        (tim1_etb_trig       ),
  .tim2_etb_trig        (tim2_etb_trig       )
);

assign prdata[31:0] = i_prdata[31:0];
assign i_pwrite = pwrite;
assign i_psel = psel;

endmodule
module tim2_tim_top(
  etb_tim1_trig_en_off,
  etb_tim1_trig_en_on,
  etb_tim2_trig_en_off,
  etb_tim2_trig_en_on,
  intr,
  paddr,
  pclk,
  penable,
  prdata,
  presetn,
  psel,
  pwdata,
  pwrite,
  scan_mode,
  tim1_etb_trig,
  tim2_etb_trig
);
input           etb_tim1_trig_en_off; 
input           etb_tim1_trig_en_on; 
input           etb_tim2_trig_en_off; 
input           etb_tim2_trig_en_on; 
input   [31:0]  paddr;               
input           pclk;                
input           penable;             
input           presetn;             
input           psel;                
input   [31:0]  pwdata;              
input           pwrite;              
input           scan_mode;           
output  [1 :0]  intr;                
output  [31:0]  prdata;              
output          tim1_etb_trig;       
output          tim2_etb_trig;       
wire            etb_tim1_trig_en_off; 
wire            etb_tim1_trig_en_on; 
wire            etb_tim2_trig_en_off; 
wire            etb_tim2_trig_en_on; 
wire    [1 :0]  intr;                
wire    [31:0]  paddr;               
wire            pclk;                
wire            penable;             
wire    [31:0]  prdata;              
wire            presetn;             
wire            psel;                
wire    [31:0]  pwdata;              
wire            pwrite;              
wire            scan_mode;           
wire            tim1_etb_trig;       
wire            tim2_etb_trig;       
wire    [1 :0]  timer_en;            
wire            timer_int_flag;      
wire            timer_int_flag_n;    
wire    [1 :0]  timer_int_n;         
wire    [1 :0]  timertrig;           
timers_top  x_timers_top (
  .etb_tim1_trig_en_off (etb_tim1_trig_en_off),
  .etb_tim1_trig_en_on  (etb_tim1_trig_en_on ),
  .etb_tim2_trig_en_off (etb_tim2_trig_en_off),
  .etb_tim2_trig_en_on  (etb_tim2_trig_en_on ),
  .paddr                (paddr[7:0]          ),
  .pclk                 (pclk                ),
  .penable              (penable             ),
  .prdata               (prdata              ),
  .presetn              (presetn             ),
  .psel                 (psel                ),
  .pwdata               (pwdata              ),
  .pwrite               (pwrite              ),
  .scan_mode            (scan_mode           ),
  .tim1_etb_trig        (tim1_etb_trig       ),
  .tim2_etb_trig        (tim2_etb_trig       ),
  .timer_1_clk          (pclk                ),
  .timer_1_resetn       (presetn             ),
  .timer_2_clk          (pclk                ),
  .timer_2_resetn       (presetn             ),
  .timer_en             (timer_en            ),
  .timer_int            (intr                ),
  .timer_int_flag       (timer_int_flag      ),
  .timer_int_flag_n     (timer_int_flag_n    ),
  .timer_int_n          (timer_int_n         ),
  .timertrig            (timertrig           )
);
endmodule
module apb_dummy_top(
  intr,  
  paddr,
  pclk,
  penable,
  pprot,
  prdata,
  psel,
  pwdata,
  pwrite,
  presetn
);
input   [31:0]  paddr;        
input           pclk;         
input           penable;      
input   [2 :0]  pprot;        
input           psel;         
input   [31:0]  pwdata;       
input           pwrite;       
input           presetn;   
output  [31:0]  prdata; 
output          intr;  
assign prdata[31:0] = 32'h0;
assign intr = 1'b0;
endmodule
module ahb_dummy_top(
  haddr,
  hclk,
  hprot,
  hrdata,
  hready,
  hresp,
  hrst_b,
  hsel,
  hsize,
  htrans,
  hwdata,
  hwrite,
  intr
);
input   [31:0]  haddr;        
input           hclk;         
input   [3 :0]  hprot;        
input           hrst_b;       
input           hsel;         
input   [2 :0]  hsize;        
input   [1 :0]  htrans;       
input   [31:0]  hwdata;       
input           hwrite;       
output  [31:0]  hrdata;       
output          hready;  
output  [1 :0]  hresp;    
output		intr;    
wire  [31:0]  hrdata;       
wire          hready;  
wire  [1 :0]  hresp;    
wire          intr;
assign hrdata[31:0] = 32'b0;       
assign hready = 1'b1;  
assign hresp[1:0] = 2'b0;    
assign intr = 1'b0;     
endmodule
module ahbm_dummy_top(
hclk,
hrst_b,
mhrdata,
mhresp,
mhready,
mhgrant,
mhwdata,
mhburst,
mhtrans,
mhwrite,
mhaddr,
mhsize,
mhprot
);
output   [31:0]  mhaddr;       
output   [2 :0]  mhburst;      
output   [3 :0]  mhprot;       
output   [2 :0]  mhsize;       
output   [1 :0]  mhtrans;      
output   [31:0]  mhwdata;      
output           mhwrite; 
input          hclk;      
input          hrst_b;      
input          mhgrant;      
input  [31:0]  mhrdata;      
input          mhready;      
input  [1 :0]  mhresp;  
wire   [31:0]  mhaddr;       
wire   [2 :0]  mhburst;      
wire   [3 :0]  mhprot;       
wire   [2 :0]  mhsize;       
wire   [1 :0]  mhtrans;      
wire   [31:0]  mhwdata;      
wire           mhwrite; 
assign mhaddr[31:0]  = 32'b0; 
assign mhburst[2 :0] = 3'b0; 
assign mhprot[3 :0]  = 4'b0;
assign mhsize[2 :0]  = 3'b0;
assign mhtrans[1 :0] = 2'b0; 
assign mhwdata[31:0] = 32'b0; 
assign mhwrite       = 1'b0;
endmodule
module Standard_Cell_CLK_GATE(
Q, 
CK, 
EN, 
SE
);
   output Q;
   input CK;
   input EN;
   input SE;

wire	E;
reg	q_tmp;
assign E = SE | EN;

always @(E or CK)
begin 
    if(!CK)
	q_tmp = E;
end

assign Q = q_tmp & CK;


endmodule
module Standard_Cell_CLK_MUX2(
X, 
S, 
D0, 
D1
);
   output X;
   input S;
   input D0;
   input D1;

assign X = S ? D1 : D0;

endmodule
module fpga_byte_spram(
  A,
  CEN,
  CLK,
  D,
  Q,
  WEN   
);

parameter  ADDRWIDTH = 17;
parameter  DATAWIDTH = 8;
parameter  MEMDEPTH  = 2**(ADDRWIDTH);


input   [(ADDRWIDTH-1) :0]  A;
input           CEN;
input           CLK;
input   [(DATAWIDTH-1):0]  D;
input           WEN;
output  [(DATAWIDTH-1):0]  Q;

reg     [(DATAWIDTH-1):0]  Q;
reg     [(DATAWIDTH-1):0]  mem[(MEMDEPTH-1):0];

always@(posedge CLK)
begin
  if(!CEN)
  begin
    if(!WEN)
    begin
      mem[A] <= D;
      Q      <= D;
    end
    else
    begin
      Q      <= mem[A];
    end
  end
end
endmodule
module fpga_spram(
  A,
  CEN,
  CLK,
  D,
  Q,
  BWEN   
);

parameter  DATAWIDTH = 32;
parameter  ADDRWIDTH = 17;
parameter  MEMDEPTH  = 2**(ADDRWIDTH);

input   [(ADDRWIDTH-1) :0]  A;
input           CEN;
input           CLK;
input   [(DATAWIDTH-1):0]  D;
input   [3:0]        BWEN;
output  [(DATAWIDTH-1):0]  Q;

wire     [(DATAWIDTH-1):0]  Q;

fpga_byte_spram #(ADDRWIDTH,8,MEMDEPTH) x_fpga_byte0_spram(
  .A(A),
  .CEN(CEN),
  .CLK(CLK),
  .D(D[7:0]),
  .Q(Q[7:0]),
  .WEN(BWEN[0])   
);

fpga_byte_spram #(ADDRWIDTH,8,MEMDEPTH) x_fpga_byte1_spram(
  .A(A),
  .CEN(CEN),
  .CLK(CLK),
  .D(D[15:8]),
  .Q(Q[15:8]),
  .WEN(BWEN[1])   
);

fpga_byte_spram #(ADDRWIDTH,8,MEMDEPTH) x_fpga_byte2_spram(
  .A(A),
  .CEN(CEN),
  .CLK(CLK),
  .D(D[23:16]),
  .Q(Q[23:16]),
  .WEN(BWEN[2])   
);

fpga_byte_spram #(ADDRWIDTH,8,MEMDEPTH) x_fpga_byte3_spram(
  .A(A),
  .CEN(CEN),
  .CLK(CLK),
  .D(D[31:24]),
  .Q(Q[31:24]),
  .WEN(BWEN[3])   
);

endmodule
module PAD_DIG_IO(
    OEN,
    IEN,
    OD,
    ID,
    PAD
);

input   OEN;
input   IEN;
output  ID;
input   OD;
inout   PAD;

assign ID = IEN ? 1'bz : PAD;
assign PAD = OEN ? 1'bz : OD;

endmodule
module PAD_OSC_IO(
    EN    ,
    XOSC_OUT    ,
    XOSC_IN,
    CLK
);

input    EN;
input    XOSC_IN;
output   XOSC_OUT;
output   CLK;

assign CLK = EN ? XOSC_IN : 1'b0;
assign XOSC_OUT = EN ? XOSC_IN : 1'b0;

endmodule
module fifo_reader
  #(
    parameter WIDTH = 0,
    parameter MAX_BLOCK_SIZE = 1024)
   (
    input 	      clk,
    input [WIDTH-1:0] din,
    output reg	      rden = 1'b0,
    input 	      empty);

   real 	       rate = 0.5;
   integer 	       seed = 0;

   time 	       timeout = 0;
   reg 		       err_timeout = 0;

   reg 		       valid = 1'b0;

   real 	       randval;
   always @(posedge clk) begin
      valid <= rden & !empty;
      randval = $dist_uniform(seed, 0, 1000) / 1000.0;
      rden <= (randval <= rate) & !empty;
   end

   task read_word;
      output [WIDTH-1:0] data_o;

      reg 		 rd;
      time 		 t0;

      begin
	 t0 = $time;
	 while(!valid & !err_timeout) begin
	    @(posedge clk);

	    if(timeout > 0)
	      err_timeout = ($time-t0) > timeout;
	 end
	 if(err_timeout) begin
	    $display("%0d : Timeout in FIFO reader", $time);
            $finish;
         end
	 data_o = din;
	 err_timeout = 1'b0;
	 @(posedge clk);
      end
   endtask

endmodule
module ipf_mem (ipf_valid, ipf_data, ipf_addr, clk);

	input	ipf_valid;
	input	[13:0] ipf_addr;
	input	[7:0]  ipf_data;
	input	clk;

	reg [7:0] ipf_M [0:16383];
	integer i;

	initial begin
		for (i=0; i<=16383; i=i+1) ipf_M[i] = 0;
	end

	always@(negedge clk) 
		if (ipf_valid) ipf_M[ ipf_addr ] <= ipf_data;

endmodule
module bs_mult_tb;
	initial begin
		$fsdbDumpfile("bs_mult");
		$fsdbDumpvars;
	end	
	
	reg clk = 1'b1;
	always  #10 clk <= ~clk;
	reg x = 1'b0;
	reg y = 1'b0;
	reg fb = 1'b0;
	reg lb = 1'b0;
	wire p;
	integer i = -1;
	bs_mult I0(.clk(clk), .x(x),  .y(y),  .p(p), .firstbit(fb), .lastbit(lb));
	
	initial begin
		@(posedge clk);
		lb <= 1'b1;
		// bit 0
		@(posedge clk);
		i <= 0;
		lb <= 1'b0;	fb <= 1'b1;		
		x <= 1'b1; y <= 1'b1;
		// bit 1
		@(posedge clk);
		i <= 1;
		x <= 1'b1; y <= 1'b0;
		fb <= 1'b0;
		// bit 2
		@(posedge clk);
		i <= 2;
		x <= 1'b1; y <= 1'b1;
		// bit 3
		@(posedge clk);
		i <= 3;
		x <= 1'b1; y <= 1'b1;
		// bit 4
		@(posedge clk);
		i <= 4;
		x <= 1'b1; y <= 1'b1;
		// bit 5
		@(posedge clk);
		i <= 5;
		x <= 1'b1; y <= 1'b1;
		// bit 6
		@(posedge clk);
		i <= 6;
		x <= 1'b1; y <= 1'b1;
		// bit 7
		@(posedge clk);
		i <= 7;
		x <= 1'b1; y <= 1'b1;
		// bit 8
		@(posedge clk);
		i <= 8;
		x <= 1'b1; y <= 1'b1;
		// bit 9
		@(posedge clk);
		i <= 9;
		x <= 1'b1; y <= 1'b1;
		// bit 10
		@(posedge clk);
		i <= 10;
		x <= 1'b1; y <= 1'b1;
		// bit 11
		@(posedge clk);
		i <= 11;
		x <= 1'b1; y <= 1'b1;
		// bit 12
		@(posedge clk);
		i <= 12;
		x <= 1'b1; y <= 1'b1;
		// bit 13
		@(posedge clk);
		i <= 13;
		x <= 1'b1; y <= 1'b1;
		// bit 14
		@(posedge clk);
		i <= 14;
		x <= 1'b1; y <= 1'b1;
		// bit 15
		@(posedge clk);
		i <= 15;
		x <= 1'b1; y <= 1'b1;
		// bit 16
		@(posedge clk);
		i <= 16;
		x <= 1'b1; y <= 1'b1;
		// bit 15
		@(posedge clk);
		i <= 17;
		x <= 1'b1; y <= 1'b1;
		// bit 15
		@(posedge clk);
		i <= 18;
		x <= 1'b1; y <= 1'b1;
		// bit 15
		@(posedge clk);
		i <= 19;
		x <= 1'b1; y <= 1'b1;
		// bit 15
		@(posedge clk);
		i <= 20;
		x <= 1'b1; y <= 1'b1;
		// bit 15
		@(posedge clk);
		i <= 21;
		x <= 1'b1; y <= 1'b1;
		// bit 22
		@(posedge clk);
		i <= 22;
		x <= 1'b1; y <= 1'b1;
		// bit 15
		@(posedge clk);
		i <= 23;
		x <= 1'b1; y <= 1'b1;
		// bit 15
		@(posedge clk);
		i <= 24;
		x <= 1'b1; y <= 1'b1;
		// bit 15
		@(posedge clk);
		i <= 25;
		x <= 1'b1; y <= 1'b1;
		// bit 15
		@(posedge clk);
		i <= 26;
		x <= 1'b1; y <= 1'b1;
		// bit 15
		@(posedge clk);
		i <= 27;
		x <= 1'b1; y <= 1'b1;
		// bit 15
		@(posedge clk);
		i <= 28;
		x <= 1'b1; y <= 1'b1;
		// bit 15
		@(posedge clk);
		i <= 29;
		x <= 1'b1; y <= 1'b1;
		// bit 15
		@(posedge clk);
		i <= 30;
		x <= 1'b1; y <= 1'b1;
		// bit 15
		@(posedge clk);
		i <= 31;
		x <= 1'b1; y <= 1'b1;
		lb <= 1'b1;		
		// ends here
		@(posedge clk);
		i <= 0;
		x <= 1'b0; y <= 1'b0;
		lb <= 1'b0;		
		@(posedge clk);
		@(posedge clk);
		@(posedge clk);
      $finish;
   end
endmodule
module dpram2 (
	clock,
	data,
	rdaddress,
	wraddress,
	wren,
	q);

	input	  clock;
	input	[7:0]  data;
	input	[9:0]  rdaddress;
	input	[9:0]  wraddress;
	input	  wren;
	output	[7:0]  q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri1	  clock;
	tri0	  wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire [7:0] sub_wire0;
	wire [7:0] q = sub_wire0[7:0];

	altsyncram	altsyncram_component (
				.address_a (wraddress),
				.address_b (rdaddress),
				.clock0 (clock),
				.data_a (data),
				.wren_a (wren),
				.q_b (sub_wire0),
				.aclr0 (1'b0),
				.aclr1 (1'b0),
				.addressstall_a (1'b0),
				.addressstall_b (1'b0),
				.byteena_a (1'b1),
				.byteena_b (1'b1),
				.clock1 (1'b1),
				.clocken0 (1'b1),
				.clocken1 (1'b1),
				.clocken2 (1'b1),
				.clocken3 (1'b1),
				.data_b ({8{1'b1}}),
				.eccstatus (),
				.q_a (),
				.rden_a (1'b1),
				.rden_b (1'b1),
				.wren_b (1'b0));
	defparam
		altsyncram_component.address_aclr_b = "NONE",
		altsyncram_component.address_reg_b = "CLOCK0",
		altsyncram_component.clock_enable_input_a = "BYPASS",
		altsyncram_component.clock_enable_input_b = "BYPASS",
		altsyncram_component.clock_enable_output_b = "BYPASS",
		altsyncram_component.intended_device_family = "MAX 10",
		altsyncram_component.lpm_type = "altsyncram",
		altsyncram_component.numwords_a = 1024,
		altsyncram_component.numwords_b = 1024,
		altsyncram_component.operation_mode = "DUAL_PORT",
		altsyncram_component.outdata_aclr_b = "NONE",
		altsyncram_component.outdata_reg_b = "CLOCK0",
		altsyncram_component.power_up_uninitialized = "FALSE",
		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
		altsyncram_component.widthad_a = 10,
		altsyncram_component.widthad_b = 10,
		altsyncram_component.width_a = 8,
		altsyncram_component.width_b = 8,
		altsyncram_component.width_byteena_a = 1;


endmodule
module mypll2 (
	inclk0,
	phasecounterselect,
	phasestep,
	phaseupdown,
	scanclk,
	c0,
	c1,
	c2,
	c3,
	c4,
	locked,
	phasedone);

	input	  inclk0;
	input	[2:0]  phasecounterselect;
	input	  phasestep;
	input	  phaseupdown;
	input	  scanclk;
	output	  c0;
	output	  c1;
	output	  c2;
	output	  c3;
	output	  c4;
	output	  locked;
	output	  phasedone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0	[2:0]  phasecounterselect;
	tri0	  phasestep;
	tri0	  phaseupdown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

endmodule
module lp_ram_dp (
	data,
	rdaddress,
	rdclock,
	rden,
	wraddress,
	wrclock,
	wren,
	q);

	input	[7:0]  data;
	input	[12:0]  rdaddress;
	input	  rdclock;
	input	  rden;
	input	[12:0]  wraddress;
	input	  wrclock;
	input	  wren;
	output	[7:0]  q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri1	  rden;
	tri1	  wrclock;
	tri0	  wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

endmodule
module processor_slave(clk, rxReady, rxData, txBusy, txStart, txData, readdata, newgotdata, gotdata);
  input clk;
  input[7:0] rxData;
  input rxReady;
  input txBusy;
  output reg txStart;
  output reg[7:0] txData;
  output reg[7:0] readdata;//first byte we got
  input newgotdata;//from other processor
  input[7:0] gotdata;
  
  localparam READ=0, SOLVING=1, WRITE1=2, WRITE2=3;
  localparam LEN = 1;
  localparam LENMAX = LEN - 1;

  integer ioCount;
  reg[7:0] data[0:LENMAX];
  integer state;

  initial begin
    state = READ;
  end

  always @(posedge clk) begin
    case (state)
	 
      READ: begin
		  txStart = 0;
        if (rxReady) begin
          data[ioCount] = rxData;
			 if (ioCount == 0) readdata = rxData;
          if (ioCount == LENMAX) begin
            ioCount = 0;
            state = SOLVING;
          end else begin
            ioCount = ioCount + 1;
          end
        end
		  	if (newgotdata) begin
				ioCount = 0;
				data[0]=gotdata;
				state=WRITE1;
			end
      end

      SOLVING: begin
		  begin
          //if (readdata == 49) get_ext_data=1;
        end
		  state=READ;
        //state = WRITE1;
      end

      WRITE1: begin
        if (!txBusy) begin
          txData = data[ioCount];
          txStart = 1;
          state = WRITE2;
        end
      end

      WRITE2: begin
        txStart = 0;
        if (ioCount != LENMAX) begin
          ioCount = ioCount + 1;
          state = WRITE1;
        end else begin
          ioCount = 0;
          state = READ;
        end
      end
		
    endcase
	 
  end
endmodule
module oscillo(clk, RxD, TxD, clk_flash, data_flash);
input clk;
input RxD;
output TxD;

input clk_flash;
input [7:0] data_flash;

///////////////////////////////////////////////////////////////////

//wire [7:0] RxD_data;
//async_receiver async_rxd(.clk(clk), .RxD(RxD), .RxD_data_ready(RxD_data_ready), .RxD_data(RxD_data));

reg startAcquisition;
wire AcquisitionStarted;

always @(posedge clk)
if(~startAcquisition)
  //startAcquisition <= RxD_data_ready;
  startAcquisition <= RxD;
else
if(AcquisitionStarted)
  startAcquisition <= 0;

reg startAcquisition1; always @(posedge clk_flash) startAcquisition1 <= startAcquisition ;
reg startAcquisition2; always @(posedge clk_flash) startAcquisition2 <= startAcquisition1;

reg Acquiring;
always @(posedge clk_flash)
if(~Acquiring)
  Acquiring <= startAcquisition2;
else
if(&wraddress)
  Acquiring <= 0;

reg [8:0] wraddress;
always @(posedge clk_flash) if(Acquiring) wraddress <= wraddress + 1;

reg Acquiring1; always @(posedge clk) Acquiring1 <= Acquiring;
reg Acquiring2; always @(posedge clk) Acquiring2 <= Acquiring1;
assign AcquisitionStarted = Acquiring2;

reg [8:0] rdaddress;
reg Sending;
wire TxD_busy;

always @(posedge clk)
if(~Sending)
  Sending <= AcquisitionStarted;
else
if(~TxD_busy)
begin
  rdaddress <= rdaddress + 1;
  if(&rdaddress) Sending <= 0;
end

wire TxD_start = ~TxD_busy & Sending;
wire rden = TxD_start;

wire [7:0] ram_output;
async_transmitter async_txd(.clk(clk), .TxD(TxD), .TxD_start(TxD_start), .TxD_busy(TxD_busy), .TxD_data(ram_output));

///////////////////////////////////////////////////////////////////
reg [7:0] data_flash_reg; always @(posedge clk_flash) data_flash_reg <= data_flash;

LPM_RAM_DP #(.LPM_WIDTH(8), .LPM_WIDTHAD(9)) ram_flash (
  .data(data_flash_reg), .wraddress(wraddress), .wren(Acquiring), .wrclock(clk_flash),
  .q(ram_output), .rdaddress(rdaddress), .rden(rden), .rdclock(clk)
);

endmodule
module ram2 (
	address,
	clock,
	data,
	wren,
	q);

	input	[9:0]  address;
	input	  clock;
	input	[7:0]  data;
	input	  wren;
	output	[7:0]  q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri1	  clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire [7:0] sub_wire0;
	wire [7:0] q = sub_wire0[7:0];

	altsyncram	altsyncram_component (
				.address_a (address),
				.clock0 (clock),
				.data_a (data),
				.wren_a (wren),
				.q_a (sub_wire0),
				.aclr0 (1'b0),
				.aclr1 (1'b0),
				.address_b (1'b1),
				.addressstall_a (1'b0),
				.addressstall_b (1'b0),
				.byteena_a (1'b1),
				.byteena_b (1'b1),
				.clock1 (1'b1),
				.clocken0 (1'b1),
				.clocken1 (1'b1),
				.clocken2 (1'b1),
				.clocken3 (1'b1),
				.data_b (1'b1),
				.eccstatus (),
				.q_b (),
				.rden_a (1'b1),
				.rden_b (1'b1),
				.wren_b (1'b0));
	defparam
		altsyncram_component.clock_enable_input_a = "BYPASS",
		altsyncram_component.clock_enable_output_a = "BYPASS",
		altsyncram_component.intended_device_family = "MAX 10",
		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
		altsyncram_component.lpm_type = "altsyncram",
		altsyncram_component.numwords_a = 1024,
		altsyncram_component.operation_mode = "SINGLE_PORT",
		altsyncram_component.outdata_aclr_a = "NONE",
		altsyncram_component.outdata_reg_a = "CLOCK0",
		altsyncram_component.power_up_uninitialized = "FALSE",
		altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
		altsyncram_component.widthad_a = 10,
		altsyncram_component.width_a = 8,
		altsyncram_component.width_byteena_a = 1;


endmodule
module oscillo(clk, RxD, TxD, clk_flash, data_flash);
input clk;
input RxD;
output TxD;
input clk_flash;
input [7:0] data_flash;
reg startAcquisition;
wire AcquisitionStarted;

always @(posedge clk)
if(~startAcquisition)  startAcquisition <= RxD;
else if(AcquisitionStarted)  startAcquisition <= 0;

reg startAcquisition1; always @(posedge clk_flash) startAcquisition1 <= startAcquisition ;
reg startAcquisition2; always @(posedge clk_flash) startAcquisition2 <= startAcquisition1;

reg Acquiring;
always @(posedge clk_flash)
if(~Acquiring)  Acquiring <= startAcquisition2;
else if(&wraddress)  Acquiring <= 0;

reg [8:0] wraddress;
always @(posedge clk_flash) if(Acquiring) wraddress <= wraddress + 1;

reg Acquiring1; always @(posedge clk) Acquiring1 <= Acquiring;
reg Acquiring2; always @(posedge clk) Acquiring2 <= Acquiring1;
assign AcquisitionStarted = Acquiring2;

reg [8:0] rdaddress;
reg Sending;
wire TxD_busy;

always @(posedge clk)
if(~Sending)  Sending <= AcquisitionStarted;
else if(~TxD_busy) begin
  rdaddress <= rdaddress + 1;
  if(&rdaddress) Sending <= 0;
end

wire TxD_start = ~TxD_busy & Sending;
wire rden = TxD_start;

wire [7:0] ram_output;
async_transmitter async_txd(.clk(clk), .TxD(TxD), .TxD_start(TxD_start), .TxD_busy(TxD_busy), .TxD_data(ram_output));

///////////////////////////////////////////////////////////////////
reg [7:0] data_flash_reg; always @(posedge clk_flash) data_flash_reg <= data_flash;

LPM_RAM_DP #(.LPM_WIDTH(8), .LPM_WIDTHAD(9)) ram_flash (
  .data(data_flash_reg), .wraddress(wraddress), .wren(Acquiring), .wrclock(clk_flash),
  .q(ram_output), .rdaddress(rdaddress), .rden(rden), .rdclock(clk)
);

endmodule
module lp_ram_dp_2 (
	data,
	rdaddress,
	rdclock,
	rden,
	wraddress,
	wrclock,
	wren,
	q);

	input	[4:0]  data;
	input	[12:0]  rdaddress;
	input	  rdclock;
	input	  rden;
	input	[12:0]  wraddress;
	input	  wrclock;
	input	  wren;
	output	[4:0]  q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri1	  rden;
	tri1	  wrclock;
	tri0	  wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

endmodule
module pong(clk, vga_h_sync, vga_v_sync, vga_R, vga_G, vga_B, PaddlePosition);
input clk;
input [7:0] PaddlePosition;
output vga_h_sync, vga_v_sync, vga_R, vga_G, vga_B;

wire inDisplayArea;
wire [9:0] CounterX;
wire [8:0] CounterY;

hvsync_generator syncgen(.clk(clk), .vga_h_sync(vga_h_sync), .vga_v_sync(vga_v_sync), 
  .inDisplayArea(inDisplayArea), .CounterX(CounterX), .CounterY(CounterY));

/////////////////////////////////////////////////////////////////
wire border = (CounterX[9:3]==0) || (CounterX[9:3]==79) || (CounterY[8:3]==0) || (CounterY[8:3]==59);
wire[10:0] PaddlePosition2 = (PaddlePosition-49)*80;
wire paddle = (CounterX>=PaddlePosition2+8) && (CounterX<=PaddlePosition2+120) && (CounterY[8:4]==27);
wire BouncingObject = border | paddle; // active if the border or paddle is redrawing itself

/////////////////////////////////////////////////////////////////
parameter Nballs = 15;
wire [Nballs:0] inball;
reg [Nballs:0] inotherball;
wire [9:0] ballX [Nballs:0];
wire [8:0] ballY [Nballs:0];
wire [8:0] ballspeed [Nballs:0];
wire [8:0] ballmass [Nballs:0];

generate
  genvar i;
  for (i=0; i<Nballs; i=i+1) begin : dff
    mball #(.startX(20+((131*i)%600)), .startY(29+((7*i)%440)), .pballmass(1), .pballspeed(1)) ball_i (.clk(clk), 
	    .BouncingObject(BouncingObject), .inotherball(inotherball[i]), 
       .CounterX(CounterX), .CounterY(CounterY), .ballX(ballX[i]), .ballY(ballY[i]), 
		 .inball(inball[i]), .ballspeed(ballspeed[i]), .ballmass(ballmass[i]) );
  end
endgenerate

/////////////////////////////////////////////////////////////////
wire inaball = (inball!=0);
wire R = BouncingObject | inaball | (CounterX[3] ^ CounterY[3]);
wire G = BouncingObject | inaball;
wire B = BouncingObject | inaball;

reg [Nballs:0] iball;
reg [Nballs:0] jball;
always @(posedge clk) begin
   for (iball=0; iball<Nballs; iball=iball+1) begin
	   inotherball[iball] = 0;
	   for (jball=0; jball<Nballs; jball=jball+1) begin
		   if (inball[iball] & iball!=jball & inball[jball]) inotherball[iball] = 1;//ballmass[jball]*ballspeed[jball];
	   end
	end
end

reg vga_R, vga_G, vga_B;
always @(posedge clk) begin
	vga_R <= R & inDisplayArea;
	vga_G <= G & inDisplayArea;
	vga_B <= B & inDisplayArea;
end

endmodule
module uniqueid2 (
		input  wire        clkin,      //  clkin.clk
		input  wire        reset,      //  reset.reset
		output wire        data_valid, // output.valid
		output wire [63:0] chip_id     //       .data
	);

	altchip_id #(
		.DEVICE_FAMILY ("MAX 10"),
		.ID_VALUE      (64'b1111111111111111111111111111111111111111111111111111111111111111),
		.ID_VALUE_STR  ("00000000ffffffff")
	) uniqueid2_inst (
		.clkin      (clkin),      //  clkin.clk
		.reset      (reset),      //  reset.reset
		.data_valid (data_valid), // output.valid
		.chip_id    (chip_id)     //       .data
	);

endmodule
module demux1to2(     Data_in,     sel,    Data_out_0,    Data_out_1    );

//list the inputs and their sizes
    input Data_in;
    input sel;
//list the outputs and their sizes 
    output Data_out_0;
    output Data_out_1;
//Internal variables
    reg Data_out_0;
    reg Data_out_1;

//always block with Data_in and sel in its sensitivity list
    always @(Data_in or sel)
    begin
        case (sel)
            1'b0 : begin
                        Data_out_0 = Data_in;
                        Data_out_1 = 0;
                      end
            1'b1 : begin
                        Data_out_0 = 0;
                        Data_out_1 = Data_in;
                      end
        endcase
    end
    
endmodule
module ring_counter (clk,out_carry,carryin,carryout,delayin,start,out_delay);
input clk;
output reg [7:0] out_carry;
output reg [7:0] out_delay;
input carryin;
output carryout;
input wire [DELAY-1:0] delayin;

parameter DELAY=100; // about 13-14 per tick (10ns) // actually set in serial bdf design file
wire [DELAY-1:0] delay_line /* synthesis keep */;
output reg start;
reg freeze;
assign carryout = freeze; // set the output high when we freeze

wire freezeline;
// assign freezeline = freeze; // freeze the chain whenever we say to freeze internally
assign freezeline = carryin; // freeze the chain based on external freeze signal

//delay line
genvar i;
generate
for (i=1; i<DELAY; i=i+1)
	begin : del
		//assign delay_line [i] = delay_line[i-1+freezeline]; // when freeze is 1, it just is assigned to itself... otherwise it is assigned to it's friend from the left
		assign delay_line [i] = (freezeline) ? delay_line[i] : delay_line[i-1]; // when freeze is 1, it just is assigned to itself... otherwise it is assigned to it's friend from the left
	end
endgenerate
assign delay_line[0] = start; // we trigger the chain with the "start" command

initial begin
	start<=0;
	freeze<=0;
end

//sync them over to the input clock
integer delay_counter=0;
always @(posedge clk) begin
	if (freeze) begin
		//count until the first 0
		if (delay_line[delay_counter]) delay_counter=delay_counter+1;//keep counting
		else out_delay[7:0] = delay_counter;//found the first 0
	end
	else delay_counter=0;//just wait
end

integer counter=0;
integer delayer=0;
//integer cycles=0;
always @(posedge clk) begin
	counter = counter+1;
	if (counter==200000000) begin // every 2 seconds, reset to 0 and wait for start
		freeze=0;
		start=0;
	end
	if (counter==200000050) begin // 500 ns later, start
		start=1;
	end
	if (counter==200000050+delayer) begin // then freeze, after some delay possibly
		freeze=1;
		
//		cycles=cycles+1;
//		if (cycles==10) begin //every 3 seconds, increment the delayer time by a tick
//			delayer=delayer+1;
//			cycles=7;//wait 10 seconds before starting up the incrementing
//		end
		
	end
	if (counter==200000050+delayer+ 100000) counter=0;//do it again
end

integer delay_counter2=1;
always @(posedge clk) begin
	if (counter > 200000050+delayer + 10) begin // give it time to stop
		//count until a 1
		if (delayin[delay_counter2]) out_carry[7:0] = delay_counter2 - 150;//found a 1
		else delay_counter2=delay_counter2+1;//keep counting
	end
	else delay_counter2=1;//just wait
end

endmodule
module lp_ram_dp (
	data,
	rdaddress,
	rdclock,
	rden,
	wraddress,
	wrclock,
	wren,
	q);

	input	[7:0]  data;
	input	[12:0]  rdaddress;
	input	  rdclock;
	input	  rden;
	input	[12:0]  wraddress;
	input	  wrclock;
	input	  wren;
	output	[7:0]  q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri1	  rden;
	tri1	  wrclock;
	tri0	  wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire [7:0] sub_wire0;
	wire [7:0] q = sub_wire0[7:0];

	altsyncram	altsyncram_component (
				.address_a (wraddress),
				.address_b (rdaddress),
				.clock0 (wrclock),
				.clock1 (rdclock),
				.data_a (data),
				.rden_b (rden),
				.wren_a (wren),
				.q_b (sub_wire0),
				.aclr0 (1'b0),
				.aclr1 (1'b0),
				.addressstall_a (1'b0),
				.addressstall_b (1'b0),
				.byteena_a (1'b1),
				.byteena_b (1'b1),
				.clocken0 (1'b1),
				.clocken1 (1'b1),
				.clocken2 (1'b1),
				.clocken3 (1'b1),
				.data_b ({8{1'b1}}),
				.eccstatus (),
				.q_a (),
				.rden_a (1'b1),
				.wren_b (1'b0));
	defparam
		altsyncram_component.address_aclr_b = "NONE",
		altsyncram_component.address_reg_b = "CLOCK1",
		altsyncram_component.clock_enable_input_a = "BYPASS",
		altsyncram_component.clock_enable_input_b = "BYPASS",
		altsyncram_component.clock_enable_output_b = "BYPASS",
		altsyncram_component.intended_device_family = "MAX 10",
		altsyncram_component.lpm_type = "altsyncram",
		altsyncram_component.numwords_a = 8192,
		altsyncram_component.numwords_b = 8192,
		altsyncram_component.operation_mode = "DUAL_PORT",
		altsyncram_component.outdata_aclr_b = "NONE",
		altsyncram_component.outdata_reg_b = "CLOCK1",
		altsyncram_component.power_up_uninitialized = "FALSE",
		altsyncram_component.rdcontrol_reg_b = "CLOCK1",
		altsyncram_component.widthad_a = 13,
		altsyncram_component.widthad_b = 13,
		altsyncram_component.width_a = 8,
		altsyncram_component.width_b = 8,
		altsyncram_component.width_byteena_a = 1;


endmodule
module chain_delay(clk,start,stop,result);
input clk, start, stop;
parameter CHAIN_LEN = 200;
wire [CHAIN_LEN-2:0] input1 = {{CHAIN_LEN-2{1'b0}},start} /* synthesis keep */; // that's ...0000000 or ...00000001
wire [CHAIN_LEN-1:0] chain = {CHAIN_LEN-1{1'b1}} + input1 /* synthesis keep */; // that's 1111...1111, added to 1 or 0

// I think it works like this... 
// when start is 0:  011111111 + 0000 = 011111111
// when start goes to 1:  011111111 + 0001 = 100000000  i.e. 255+1=256
// before the operation completes: 011110000, so the more 0's, the longer it ran
// if it got to the end, the last bit should be a 1

output reg [CHAIN_LEN-1:0] result /* synthesis keep */;
always @(posedge stop) result<=chain;

endmodule
module ram1 (
	address,
	clock,
	data,
	wren,
	q);

	input	[10:0]  address;
	input	  clock;
	input	[11:0]  data;
	input	  wren;
	output	[11:0]  q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri1	  clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire [11:0] sub_wire0;
	wire [11:0] q = sub_wire0[11:0];

	altsyncram	altsyncram_component (
				.address_a (address),
				.clock0 (clock),
				.data_a (data),
				.wren_a (wren),
				.q_a (sub_wire0),
				.aclr0 (1'b0),
				.aclr1 (1'b0),
				.address_b (1'b1),
				.addressstall_a (1'b0),
				.addressstall_b (1'b0),
				.byteena_a (1'b1),
				.byteena_b (1'b1),
				.clock1 (1'b1),
				.clocken0 (1'b1),
				.clocken1 (1'b1),
				.clocken2 (1'b1),
				.clocken3 (1'b1),
				.data_b (1'b1),
				.eccstatus (),
				.q_b (),
				.rden_a (1'b1),
				.rden_b (1'b1),
				.wren_b (1'b0));
	defparam
		altsyncram_component.clock_enable_input_a = "BYPASS",
		altsyncram_component.clock_enable_output_a = "BYPASS",
		altsyncram_component.intended_device_family = "MAX 10",
		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
		altsyncram_component.lpm_type = "altsyncram",
		altsyncram_component.numwords_a = 2048,
		altsyncram_component.operation_mode = "SINGLE_PORT",
		altsyncram_component.outdata_aclr_a = "NONE",
		altsyncram_component.outdata_reg_a = "UNREGISTERED",
		altsyncram_component.power_up_uninitialized = "FALSE",
		altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
		altsyncram_component.widthad_a = 11,
		altsyncram_component.width_a = 12,
		altsyncram_component.width_byteena_a = 1;


endmodule