dakies/OSS_Verilog huggingface dataset:
module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
  parameter [63:0] INIT = 0;
  wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
  wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
  wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
  wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
  wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  assign O6 = I0 ? s1[1] : s1[0];

  wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
  wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
  wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
  wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
  assign O5 = I0 ? s5_1[1] : s5_1[0];
endmodule
module MUXCY(output O, input CI, DI, S);
  assign O = S ? CI : DI;
endmodule
module MUXF7(output O, input I0, I1, S);
  assign O = S ? I1 : I0;
endmodule
module MUXF8(output O, input I0, I1, S);
  assign O = S ? I1 : I0;
endmodule
module XORCY(output O, input CI, LI);
  assign O = CI ^ LI;
endmodule
module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
  assign O = S ^ {CO[2:0], CI | CYINIT};
  assign CO[0] = S[0] ? CI | CYINIT : DI[0];
  assign CO[1] = S[1] ? CO[0] : DI[1];
  assign CO[2] = S[2] ? CO[1] : DI[2];
  assign CO[3] = S[3] ? CO[2] : DI[3];
endmodule
module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S);
  parameter CYINIT_FABRIC = 0;
  wire CI_COMBINE;
  if(CYINIT_FABRIC) begin
    assign CI_COMBINE = CI_INIT;
  end else begin
    assign CI_COMBINE = CI;
  end
  assign CO_CHAIN = S ? CI_COMBINE : DI;
  assign CO_FABRIC = S ? CI_COMBINE : DI;
  assign O = S ^ CI_COMBINE;
endmodule
module CARRY(output CO_CHAIN, CO_FABRIC, O, input CI, DI, S);
  assign CO_CHAIN = S ? CI : DI;
  assign CO_FABRIC = S ? CI : DI;
  assign O = S ^ CI;
endmodule
module FDRE (output reg Q, input C, CE, D, R);
  parameter [0:0] INIT = 1'b0;
  parameter [0:0] IS_C_INVERTED = 1'b0;
  parameter [0:0] IS_D_INVERTED = 1'b0;
  parameter [0:0] IS_R_INVERTED = 1'b0;
  initial Q <= INIT;
  generate case (|IS_C_INVERTED)
    1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
    1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
  endcase endgenerate
endmodule
module FDSE (output reg Q, input C, CE, D, S);
  parameter [0:0] INIT = 1'b0;
  parameter [0:0] IS_C_INVERTED = 1'b0;
  parameter [0:0] IS_D_INVERTED = 1'b0;
  parameter [0:0] IS_S_INVERTED = 1'b0;
  initial Q <= INIT;
  generate case (|IS_C_INVERTED)
    1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
    1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
  endcase endgenerate
endmodule
module FDCE (output reg Q, input C, CE, D, CLR);
  parameter [0:0] INIT = 1'b0;
  parameter [0:0] IS_C_INVERTED = 1'b0;
  parameter [0:0] IS_D_INVERTED = 1'b0;
  parameter [0:0] IS_CLR_INVERTED = 1'b0;
  initial Q <= INIT;
  generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
    2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
    2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
    2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
    2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
  endcase endgenerate
endmodule
module FDPE (output reg Q, input C, CE, D, PRE);
  parameter [0:0] INIT = 1'b0;
  parameter [0:0] IS_C_INVERTED = 1'b0;
  parameter [0:0] IS_D_INVERTED = 1'b0;
  parameter [0:0] IS_PRE_INVERTED = 1'b0;
  initial Q <= INIT;
  generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
    2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
    2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
    2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
    2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
  endcase endgenerate
endmodule
module FDRE_1 (output reg Q, input C, CE, D, R);
  parameter [0:0] INIT = 1'b0;
  initial Q <= INIT;
  always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
endmodule
module FDSE_1 (output reg Q, input C, CE, D, S);
  parameter [0:0] INIT = 1'b1;
  initial Q <= INIT;
  always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
endmodule
module FDCE_1 (output reg Q, input C, CE, D, CLR);
  parameter [0:0] INIT = 1'b0;
  initial Q <= INIT;
  always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
endmodule
module FDPE_1 (output reg Q, input C, CE, D, PRE);
  parameter [0:0] INIT = 1'b1;
  initial Q <= INIT;
  always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
module RAM64X1D (
  output DPO, SPO,
  input  D, WCLK, WE,
  input  A0, A1, A2, A3, A4, A5,
  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
  parameter INIT = 64'h0;
  parameter IS_WCLK_INVERTED = 1'b0;
  wire [5:0] a = {A5, A4, A3, A2, A1, A0};
  wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
  reg [63:0] mem = INIT;
  assign SPO = mem[a];
  assign DPO = mem[dpra];
  wire clk = WCLK ^ IS_WCLK_INVERTED;
  always @(posedge clk) if (WE) mem[a] <= D;
endmodule
module RAM128X1D (
  output       DPO, SPO,
  input        D, WCLK, WE,
  input  [6:0] A, DPRA
);
  parameter INIT = 128'h0;
  parameter IS_WCLK_INVERTED = 1'b0;
  reg [127:0] mem = INIT;
  assign SPO = mem[A];
  assign DPO = mem[DPRA];
  wire clk = WCLK ^ IS_WCLK_INVERTED;
  always @(posedge clk) if (WE) mem[A] <= D;
endmodule
module SRL16E (
  output Q,
  input A0, A1, A2, A3, CE, CLK, D
);
  parameter [15:0] INIT = 16'h0000;
  parameter [0:0] IS_CLK_INVERTED = 1'b0;

  reg [15:0] r = INIT;
  assign Q = r[{A3,A2,A1,A0}];
  generate
    if (IS_CLK_INVERTED) begin
      always @(negedge CLK) if (CE) r <= { r[14:0], D };
    end
    else
        always @(posedge CLK) if (CE) r <= { r[14:0], D };
  endgenerate
endmodule
module SRLC32E (
  output Q,
  output Q31,
  input [4:0] A,
  input CE, CLK, D
);
  parameter [31:0] INIT = 32'h00000000;
  parameter [0:0] IS_CLK_INVERTED = 1'b0;

  reg [31:0] r = INIT;
  assign Q31 = r[31];
  assign Q = r[A];
  generate
    if (IS_CLK_INVERTED) begin
      always @(negedge CLK) if (CE) r <= { r[30:0], D };
    end
    else
      always @(posedge CLK) if (CE) r <= { r[30:0], D };
  endgenerate
endmodule
module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
	parameter [63:0]INIT = 64'bx;
	input CLK1;

	input [3:0] A1ADDR;
	output [3:0] A1DATA;

	input [3:0] B1ADDR;
	input [3:0] B1DATA;
	input B1EN;

	EG_LOGIC_DRAM16X4 #(
		`include "dram_init_16x4.vh"
	) _TECHMAP_REPLACE_ (
		.di(B1DATA),
		.waddr(B1ADDR),
		.wclk(CLK1),
		.we(B1EN),
		.raddr(A1ADDR),
		.do(A1DATA)
	);
endmodule
module AL_MAP_SEQ (
	output q,
	input ce,
	input clk,
	input sr,
	input d
);
	parameter DFFMODE = "FF"; //FF,LATCH
	parameter REGSET = "RESET"; //RESET/SET
	parameter SRMUX = "SR"; //SR/INV
	parameter SRMODE = "SYNC"; //SYNC/ASYNC
endmodule
module AL_MAP_LUT1 (
	output o,
	input a
);
	parameter [1:0] INIT = 2'h0;
	parameter EQN = "(A)";
	assign o = INIT >> a;
endmodule
module AL_MAP_LUT2 (
	output o,
	input a,
	input b
);
	parameter [3:0] INIT = 4'h0;
	parameter EQN = "(A)";
	assign o = INIT >> {b, a};
endmodule
module AL_MAP_LUT3 (
	output o,
	input a,
	input b,
	input c
);
	parameter [7:0] INIT = 8'h0;
	parameter EQN = "(A)";
	assign o = INIT >> {c, b, a};
endmodule
module AL_MAP_LUT4 (
	output o,
	input a,
	input b,
	input c,
	input d
);
	parameter [15:0] INIT = 16'h0;
	parameter EQN = "(A)";
	assign o = INIT >> {d, c, b, a};
endmodule
module AL_MAP_ADDER (
  input a,
  input b,
  input c,
  output [1:0] o
);
	parameter ALUTYPE = "ADD";
endmodule
module \$lut (A, Y);
   parameter WIDTH  = 0;
   parameter LUT    = 0;
   input [WIDTH-1:0] A;
   output 	     Y;
   generate
      if (WIDTH == 1) begin
	   // VT: This is not consistent and ACE will complain: assign Y = ~A[0];
         LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
           (.dout(Y), .din0(A[0]), .din1(1'b0), .din2(1'b0), .din3(1'b0));
      end else
      if (WIDTH == 2) begin
              LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
                (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0), .din3(1'b0));
      end else
      if(WIDTH == 3) begin
	      LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_
                (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(1'b0));
      end else
      if(WIDTH == 4) begin
             LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_
               (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
      end else
	   wire _TECHMAP_FAIL_ = 1;
   endgenerate
endmodule
module  \$_DFF_N_ (input D, C, output Q);
   parameter WYSIWYG="TRUE";
   parameter power_up=1'bx;
   dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
module  \$_DFF_P_ (input D, C, output Q);
   parameter WYSIWYG="TRUE";
   parameter power_up=1'bx;
   dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
module  \$_DFF_PN0_ (input D, C, R, output Q);
   parameter WYSIWYG="TRUE";
   parameter power_up=1'bx;
   dffeas #(.is_wysiwyg(WYSIWYG), .power_up("power_up")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
module  \$_DFF_PP0_ (input D, C, R, output Q);
   parameter WYSIWYG="TRUE";
   parameter power_up=1'bx;
   wire R_i = ~ R;
   dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
module  \$__DFFE_PP0 (input D, C, E, R, output Q);
   parameter WYSIWYG="TRUE";
   parameter power_up=1'bx;
   wire E_i = ~ E;
   dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
endmodule
module \$lut (A, Y);
   parameter WIDTH  = 0;
   parameter LUT    = 0;
   input [WIDTH-1:0] A;
   output            Y;
   generate
      if (WIDTH == 1) begin
	 assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
      end else
        if (WIDTH == 2) begin
           cycloneive_lcell_comb #(.lut_mask({4{LUT}}),
                                   .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
                                                                                .dataa(A[0]),
                                                                                .datab(A[1]),
                                                                                .datac(1'b1),
                                                                                .datad(1'b1));
        end else
          if(WIDTH == 3) begin
	     cycloneive_lcell_comb #(.lut_mask({2{LUT}}),
                                     .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
                                                                                  .dataa(A[0]),
                                                                                  .datab(A[1]),
                                                                                  .datac(A[2]),
                                                                                  .datad(1'b1));
          end else
            if(WIDTH == 4) begin
	       cycloneive_lcell_comb #(.lut_mask(LUT),
                                       .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
                                                                                    .dataa(A[0]),
                                                                                    .datab(A[1]),
                                                                                    .datac(A[2]),
                                                                                    .datad(A[3]));
            end else
	             wire _TECHMAP_FAIL_ = 1;
   endgenerate

endmodule
module \$lut (A, Y);
   parameter WIDTH  = 0;
   parameter LUT    = 0;
   input [WIDTH-1:0] A;
   output            Y;
   generate
      if (WIDTH == 1) begin
	   assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
      end else
      if (WIDTH == 2) begin
           cycloneiv_lcell_comb #(.lut_mask({4{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1));
      end else
      if(WIDTH == 3) begin
	   cycloneiv_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
      end else
      if(WIDTH == 4) begin
	   cycloneiv_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
      end else
	   wire _TECHMAP_FAIL_ = 1;
   endgenerate
endmodule //
module \$lut (A, Y);
   parameter WIDTH  = 0;
   parameter LUT    = 0;
   input [WIDTH-1:0] A;
   output            Y;
   generate
      if (WIDTH == 1) begin
	   assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
      end else
      if (WIDTH == 2) begin
           fiftyfivenm_lcell_comb #(.lut_mask({4{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1));
      end else
      if(WIDTH == 3) begin
	      fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
      end else
      if(WIDTH == 4) begin
         fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
      end else
	   wire _TECHMAP_FAIL_ = 1;
   endgenerate
endmodule //
module \$lut (A, Y);
   parameter WIDTH  = 0;
   parameter LUT    = 0;
   input [WIDTH-1:0] A;
   output            Y;
   generate
      if (WIDTH == 1) begin
	 assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
      end else
        if (WIDTH == 2) begin
           cyclone10lp_lcell_comb #(.lut_mask({4{LUT}}),
                                   .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
                                                                                .dataa(A[0]),
                                                                                .datab(A[1]),
                                                                                .datac(1'b1),
                                                                                .datad(1'b1));
        end else
          if(WIDTH == 3) begin
	     cyclone10lp_lcell_comb #(.lut_mask({2{LUT}}),
                                     .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
                                                                                  .dataa(A[0]),
                                                                                  .datab(A[1]),
                                                                                  .datac(A[2]),
                                                                                  .datad(1'b1));
          end else
            if(WIDTH == 4) begin
	       cyclone10lp_lcell_comb #(.lut_mask(LUT),
                                       .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
                                                                                    .dataa(A[0]),
                                                                                    .datab(A[1]),
                                                                                    .datac(A[2]),
                                                                                    .datad(A[3]));
            end else
	             wire _TECHMAP_FAIL_ = 1;
   endgenerate

endmodule
module \$__inpad (input I, output O);
    twentynm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
module \$__outpad (input I, output O);
    twentynm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
module \$lut (A, Y);
   parameter WIDTH  = 0;
   parameter LUT    = 0;
   input [WIDTH-1:0] A;
   output            Y;
   generate
      if (WIDTH == 1) begin
	   assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
      end else
      if (WIDTH == 2) begin
           twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
           _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1), .datae(1'b1), .dataf(1'b1), .datag(1'b1));
      end /*else
      if(WIDTH == 3) begin
	   fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
      end else
      if(WIDTH == 4) begin
	   fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
      end*/ else
	   wire _TECHMAP_FAIL_ = 1;
   endgenerate
endmodule //
module twentynm_io_ibuf (output o, input i, input ibar);
   assign ibar = ibar;
   assign o    = i;
endmodule // twentynm_io_ibuf
module twentynm_io_obuf (output o, input i, input oe);
   assign o  = i;
   assign oe = oe;
endmodule // twentynm_io_obuf
module twentynm_lcell_comb (output combout, cout, sumout,
                            input  dataa, datab, datac, datad,
                            input  datae, dataf, datag, cin,
                            input  sharein);

parameter lut_mask      = 64'hFFFFFFFFFFFFFFFF;
parameter dont_touch    = "off";
parameter lpm_type      = "twentynm_lcell_comb";
parameter shared_arith  = "off";
parameter extended_lut  = "off";

// TODO: This is still WIP
initial begin
  $display("Simulation model is still under investigation\n");
end

endmodule // twentynm_lcell_comb
module \$__inpad (input I, output O);
   cyclonev_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
module \$__outpad (input I, output O);
   cyclonev_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
module cyclonev_io_ibuf
  (output o, input i, input ibar);
   assign ibar = ibar;
   assign o    = i;
endmodule // cyclonev_io_ibuf
module cyclonev_io_obuf
  (output o, input i, input oe);
   assign o  = i;
   assign oe = oe;
endmodule // cyclonev_io_obuf
module displayNumber(in,out10,out1);
//input number
input [7:0]in;
//out10 mean 10's, out1 mean 1's
output [6:0]out10;
output [6:0]out1;
reg [6:0]out10;
reg [6:0]out1;

always@(in)
begin
    case(in%100-in%10)
            8'd0: out10=7'b1000000;
            8'd1: out10=7'b1111001;
            8'd2: out10=7'b0100100;
            8'd3: out10=7'b0110000;
            8'd4: out10=7'b0011001;
            8'd5: out10=7'b0010010;
            8'd6: out10=7'b0000010;
            8'd7: out10=7'b1011000;
            8'd8: out10=7'b0000000;
            8'd9: out10=7'b0010000;
    endcase
    case(in%10)
            8'd0: out1=7'b1000000;
            8'd1: out1=7'b1111001;
            8'd2: out1=7'b0100100;
            8'd3: out1=7'b0110000;
            8'd4: out1=7'b0011001;
            8'd5: out1=7'b0010010;
            8'd6: out1=7'b0000010;
            8'd7: out1=7'b1011000;
            8'd8: out1=7'b0000000;
            8'd9: out1=7'b0010000;
    endcase
end
endmodule
module window(reset,out1,out10,light,switch,finish);
input reset;
input [7:0] switch;

//display need to declear as output and wire
output [6:0]out1;
output [6:0]out10;
output [7:0]light;
output finish;

wire [6:0]out1;
wire [6:0]out10;
//

//logic counter neeed to declear as reg
reg [7:0]tries;
reg [7:0]light;
reg [3:0] i;
reg finish;
//

displayNumber DISNUM (.in(tries),.out10(out10),.out1(out1));

always@(reset)
begin
    if(reset)
    begin
        tries<=8'd0;
        finish<=1'b0;
        i=($random)%8;
        light=8'b00000000;
        light[i]=1'b1;
    end
end

always@(switch)
begin
    for(i=4'd0;i<4'd8;i++)
    begin
        if(switch[i]==1'b1)
        begin
            if(i>=1) light[i-4'd1]=~light[i-1];
            if(i<=6) light[i+1]=~light[i+1];
            light[i]=~light[i];
            tries<=tries+1'd1;
        end
    end
    if(light==8'b00000000) finish=1'b1;
end

endmodule
module displayNumber(in,out10,out1);
//input number
input [7:0]in;
//out10 mean 10's, out1 mean 1's
output [6:0]out10;
output [6:0]out1;
reg [6:0]out10;
reg [6:0]out1;

always@(in)
begin
    case((in%100-in%10)/10)
        8'd0: out10=7'b1000000;
        8'd1: out10=7'b1111001;
        8'd2: out10=7'b0100100;
        8'd3: out10=7'b0110000;
        8'd4: out10=7'b0011001;
        8'd5: out10=7'b0010010;
        8'd6: out10=7'b0000010;
        8'd7: out10=7'b1011000;
        8'd8: out10=7'b0000000;
        8'd9: out10=7'b0010000;
    endcase
    case(in%10)
        8'd0: out1=7'b1000000;
        8'd1: out1=7'b1111001;
        8'd2: out1=7'b0100100;
        8'd3: out1=7'b0110000;
        8'd4: out1=7'b0011001;
        8'd5: out1=7'b0010010;
        8'd6: out1=7'b0000010;
        8'd7: out1=7'b1011000;
        8'd8: out1=7'b0000000;
        8'd9: out1=7'b0010000;
    endcase
end
endmodule
module displayNumber(in,out10,out1);
//input number
input [7:0]in;
//out10 mean 10's, out1 mean 1's
output [6:0]out10;
output [6:0]out1;
reg [6:0]out10;
reg [6:0]out1;

always@(in)
begin
    case(in%100-in%10)
            5'd0: out10=7'b1000000;
            5'd1: out10=7'b1111001;
            5'd2: out10=7'b0100100;
            5'd3: out10=7'b0110000;
            5'd4: out10=7'b0011001;
            5'd5: out10=7'b0010010;
            5'd6: out10=7'b0000010;
            5'd7: out10=7'b1011000;
            5'd8: out10=7'b0000000;
            5'd9: out10=7'b0010000;
    endcase
    case(in%10)
            5'd0: out1=7'b1000000;
            5'd1: out1=7'b1111001;
            5'd2: out1=7'b0100100;
            5'd3: out1=7'b0110000;
            5'd4: out1=7'b0011001;
            5'd5: out1=7'b0010010;
            5'd6: out1=7'b0000010;
            5'd7: out1=7'b1011000;
            5'd8: out1=7'b0000000;
            5'd9: out1=7'b0010000;
    endcase
end
endmodule
module displayLight(safe,light);
input safe;
//display current LED light
output [2:0] light;
reg [2:0] light;

always@(safe)
begin
    //display one
    if(safe) light=3'b100;
    //display another one
    else light=3'b001;
end
endmodule
module countdown(reset,clk,out1,out10,light);
input reset,clk;

//display need to declear as output and wire
output [6:0]out1;
output [6:0]out10;
output [2:0]light;

wire [6:0]out1;
wire [6:0]out10;
wire [2:0]light;
//

//logic counter neeed to declear as reg
reg [31:0]count;
reg [7:0]second;
reg safe;
//

displayNumber DISNUM (.in(second),.out10(out10),.out1(out1));
displayLight DISLIT (.safe(safe),.light(light));

always@(posedge clk,negedge reset)
begin
    if(reset)
    begin
        count<=32'd0;
        second<=`countdownTime;
        safe<=1'b1;
    end
    else
    begin
        if(count==`TimeExpire)
        begin
            count<=32'd0;
            if(second==5'd0)
            begin
                second=5'd7;
                safe=1'b0;
            end
            else second=second-1'b1;
        end
        else count<=count+32'd1;
    end
end
endmodule
module vga(clk ,p1_pos,p2_pos,p1_size,p2_size,ball_posx,ball_posy ,VGA_r,VGA_g,VGA_b,hs,vs);
input clk;
input [9:0]p1_pos,p2_pos;
input [7:0]p1_size,p2_size;
input [10:0]ball_posx;//640
input [9:0]ball_posy;//480
output [3:0]VGA_r,VGA_g,VGA_b;
output hs,vs;
reg [19:0]vt;
reg [10:0]ht;

///////

reg [11:0] hc,hcount,r,g,b;  // VGA horizontal counter
reg [10:0] vc,vcount;  // VGA vertical counter

wire hcount_ov,vcount_ov,video_active;
// VGA mode parameters
parameter
    hsync_end   = 12'd119,
    hdat_begin  = 12'd242,
    hdat_end    = 12'd1266,
    hpixel_end  = 12'd1345,
    vsync_end   = 11'd5,
    vdat_begin  = 11'd32,
    vdat_end    = 11'd632,
    vline_end   = 11'd665;
always@(posedge clk) hcount<=(hcount_ov)? 12'd0:(hcount+12'd1);
always@(posedge clk) vcount<=(hcount_ov)? (vcount_ov)? 11'd0:(vcount+11'd1):vcount;
assign hcount_ov=hcount == hpixel_end;
assign vcount_ov=vcount == vline_end;
assign video_active=hdat_begin<=hcount&&hcount<hdat_end&&
                    vdat_begin<=vcount&&vcount<vdat_end;
assign hs=hcount>hsync_end;
assign vs=vcount>vsync_end;

assign VGA_r=(video_active)? r[3:0]:0;
assign VGA_g=(video_active)? g[3:0]:0;
assign VGA_b=(video_active)? b[3:0]:0;

// generate "image",p.s.:you can only use clk there,or it will too late to
// show image
always@(posedge clk)
begin
    vc<=vcount-vdat_begin;
    hc<=hcount-hdat_begin;
    //show ball
    if( (hc>=ball_posx)&&(hc<(ball_posx+`Ball_size))&&
        (vc>=ball_posy)&&(vc<(ball_posy+`Ball_size)))
    begin
        r<=12;
        g<=6;
        b<=0;
    end
    else
    begin
        r<=15;
        g<=15;
        b<=15;
    end
    //show player1
    if( hc>10'd30&&hc<=10'd62&&
        vc>=p1_pos&&vc<(p1_pos+p1_size))
    begin
        r<=r-((hc-30)>>1);
        g<=g-((hc-30)>>1);
    end
    else
    begin
        //show player2
        if( hc>10'd962&&hc<=10'd994&&
            vc>=p2_pos&&vc<(p2_pos+p2_size))
        begin
            g<=g-((962-hc)>>1);
            b<=b-((962-hc)>>1);
        end
    end
end
endmodule
module ball_pos(b_clk,b_rst,ball_posx,ball_posy,p1_pos,p2_pos,p1_size,p2_size);
input b_clk,b_rst;
input [9:0]p1_pos,p2_pos;
input [7:0]p1_size,p2_size;
output [10:0]ball_posx;
output [9:0]ball_posy;
reg [10:0]ball_posx;
reg [9:0]ball_posy;
reg [1:0]direction;//0:x,1:y//0:+,1:-

always@(posedge b_clk,negedge b_rst)
begin
    if(!b_rst)
    begin
        ball_posx<=11'd305;
        ball_posy<=10'd100;
        direction<=2'd0;
    end
    else
    begin
        //bounce
        if(ball_posy<=3)
            direction[1]<=0;
        if((ball_posy+`Ball_size)>=600)
            direction[1]<=1;
        if(ball_posx==62&&(ball_posy+`Ball_size)>=p1_pos&&ball_posy<(p1_pos+p1_size))
            direction[0]<=0;
        if((ball_posx+`Ball_size)==962&&(ball_posy+`Ball_size)>=p2_pos&&ball_posy<(p2_pos+p2_size))//player 2 defend
            direction[0]<=1;
        //ball move
        ball_posx<=ball_posx+((direction[0])? -1:1);
        ball_posy<=ball_posy+((direction[1])? -1:1);
    end
end
endmodule
module player_move(rst,clk,in,size,pos);
input rst,clk;
input [1:0]in;
input [7:0]size;
output [9:0]pos;
reg [9:0]pos;
reg [31:0]count;
always@(posedge clk,negedge rst)
begin
    if(!rst)
    begin
        pos<=10'd210;
        count<=32'd0;
    end
    else
    begin
        if(count==`Buttun_time)
        begin
            count<=32'd0;
            case(in)
                2'b01:pos<=pos+((pos+size)<=600);
                2'b10:pos<=pos-(pos!=0);
                default:pos<=pos;
            endcase
        end
        else count<=count+32'd1;
    end
end
endmodule
module game_rule_setter(rst,clk,p1_point,p2_point,rule ,p1_size,p2_size,b_clk);
input rst,clk;
input [3:0]p1_point,p2_point;
input [2:0]rule;//0:size,1:speed
output [7:0]p1_size,p2_size;
output b_clk;
reg [7:0]p1_size,p2_size;
reg b_clk;
reg [31:0]count,clock,shrink;
always@(posedge clk,negedge rst)
begin
    if(!rst)
    begin
        clock<=32'd100000;
        count<=32'd0;
        p1_size<=8'd200;
        p2_size<=8'd200;
    end
    else
    begin
        if(count==clock)
        begin
            count<=32'd0;
            //let ball move faster
            clock<=clock-(32'd4)*rule[1];
            b_clk<=1'b1;
            //let player smaller
            //(it may have bug when ball faster,player shrink faster,need fix)
            shrink<=shrink+1;
            if(!(shrink%40))
            begin
                p1_size<=p1_size-rule[0]*(p1_size>60);
                p2_size<=p2_size-rule[0]*(p2_size>60);
            end
        end
        else
        begin
            count<=count+32'd1;
            b_clk=1'b0;
        end
        //end game,player disappear
        if((rule[2]&&((p1_point+p2_point)>=5))||((p1_point+p2_point)>=3))
        begin
            if(p1_point>p2_point)
                p2_size<=0;
            else
                p1_size<=0;
        end
    end
end
endmodule
module seven_segment(clk,rst,point,out);
input clk,rst;
input [3:0]point;
output [6:0]out;
reg [6:0]out;
always@(posedge clk,negedge rst)
begin
    if(!rst)
    begin
        out=7'b0111111;
    end
    else
    begin
        case(point)
            4'h0:out=7'b1000000;
            4'h1:out=7'b1111001;
            4'h2:out=7'b0100100;
            4'h3:out=7'b0110000;
            4'h4:out=7'b0011001;
            4'h5:out=7'b0010010;
            4'h6:out=7'b0000010;
            4'h7:out=7'b1011000;
            4'h8:out=7'b0000000;
            4'h9:out=7'b0010000;
            4'ha:out=7'b0001000;
            4'hb:out=7'b0000011;
            4'hc:out=7'b1000110;
            4'hd:out=7'b0100001;
            4'he:out=7'b0000110;
            4'hf:out=7'b0001110;
        endcase
    end
end
endmodule
module referee(rst,clk ,ball_posx ,b_rst,seven_1,seven_2,seven_3,p1_point,p2_point);
input rst,clk;
input [10:0]ball_posx;
output b_rst;
output [6:0]seven_1,seven_2,seven_3;//seven segment
output [3:0]p1_point,p2_point;
reg b_rst;
reg [3:0]p1_point,p2_point;
seven_segment scorer_1 (.clk(clk),.rst(rst),.point(p1_point),.out(seven_1));//"p1"
seven_segment scorer_2 (.clk(clk),.rst(1'd0),.point(4'd0),.out(seven_2));//"-"
seven_segment scorer_3 (.clk(clk),.rst(rst),.point(p2_point),.out(seven_3));//"p2"
always@(posedge clk,negedge rst)
begin
    if(!rst)
    begin
        b_rst=1'd0;
        p1_point=4'd0;
        p2_point=4'd0;
    end
    else
    begin
        //player 2 got point
        if(ball_posx==0)
        begin
            b_rst=1'd0;
            p2_point=p2_point+1;
        end
        else
        begin
            //player 1 got point
            if(ball_posx+`Ball_size==1024)
            begin
                b_rst=1'd0;
                p1_point=p1_point+1;
            end
            else
                b_rst=1'd1;
        end
    end
end
endmodule
module pingpong(rst,clk ,rule,p1,p2,r,g,b,hs,vs,seven_1,seven_2,seven_3);
input rst,clk;
input [2:0]rule;
input [1:0]p1,p2;
output [3:0]r,g,b;
output hs,vs;
output [6:0]seven_1,seven_2,seven_3;//seven segment,//"p1" "-" "p2"
wire [7:0]p1_size,p2_size;
wire [3:0]p1_point,p2_point;
wire [9:0]p1_pos,p2_pos;
wire b_clk;
wire [10:0]ball_posx;
wire [9:0]ball_posy;

game_rule_setter rule_holder (.rst(b_rst),.clk(clk),.p1_point(p1_point),.p2_point(p2_point),.rule(rule),.p1_size(p1_size),.p2_size(p2_size),.b_clk(b_clk));
player_move player1 (.rst(rst),.clk(clk),.in(p1),.size(p1_size),.pos(p1_pos));
player_move player2 (.rst(rst),.clk(clk),.in(p2),.size(p2_size),.pos(p2_pos));
ball_pos ball (
    .b_clk(b_clk),.b_rst(b_rst),.ball_posx(ball_posx),.ball_posy(ball_posy),
    .p1_pos(p1_pos),.p2_pos(p2_pos),.p1_size(p1_size),.p2_size(p2_size));
vga DIS (
    .clk(clk),
    .p1_pos(p1_pos),.p2_pos(p2_pos),.p1_size(p1_size),.p2_size(p2_size),.ball_posx(ball_posx),.ball_posy(ball_posy),
    .VGA_r(r),.VGA_g(g),.VGA_b(b),.hs(hs),.vs(vs));
referee noob (.rst(rst),.clk(clk),.ball_posx(ball_posx),.b_rst(b_rst),.seven_1(seven_1),.seven_2(seven_2),.seven_3(seven_3),.p1_point(p1_point),.p2_point(p2_point));
endmodule
module displayGraph(safe,row,column,count);
//decide is green/yellow time or not
input safe;
input [31:0] count;
//display matrix
output [7:0] row;
output [7:0] column;

reg [7:0]row;
reg [7:0]column;

always@(safe)
begin
    if(safe)
    begin
        if(count%8==4'd0)
        begin
            row=8'b01111111;
            column=8'b00011000;
        end
        if(count%8==4'd1)
        begin
            row=8'b10111111;
            column=8'b00100100;
        end
        if(count%8==4'd2)
        begin
            row=8'b11011111;
            column=8'b01000010;
        end
        if(count%8==4'd3)
        begin
            row=8'b11101111;
            column=8'b11000011;
        end
        if(count%8==4'd4)
        begin
            row=8'b11110111;
            column=8'b01000010;
        end
        if(count%8==4'd5)
        begin
            row=8'b11111011;
            column=8'b01000010;
        end
        if(count%8==4'd6)
        begin
            row=8'b11111101;
            column=8'b01000010;
        end
        if(count%8==4'd7)
        begin
            row=8'b11111110;
            column=8'b01111110;
        end
    end
else
    begin
        if(count%8==4'd0)
        begin
            row=8'b01111111;
            column=8'b00011000;
        end
        if(count%8==4'd1)
        begin
            row=8'b10111111;
            column=8'b00011000;
        end
        if(count%8==4'd2)
        begin
            row=8'b11011111;
            column=8'b00111100;
        end
        if(count%8==4'd3)
        begin
            row=8'b11101111;
            column=8'b01111110;
        end
        if(count%8==4'd4)
        begin
            row=8'b11110111;
            column=8'b01011010;
        end
        if(count%8==4'd5)
        begin
            row=8'b11111011;
            column=8'b00011000;
        end
        if(count%8==4'd6)
        begin
            row=8'b11111101;
            column=8'b00100100;
        end
        if(count%8==4'd7)
        begin
            row=8'b11111110;
            column=8'b00100100;
        end
    end
end
endmodule
module displayLight(in,safe,light);
input [4:0] in;
input safe;
//display current LED light
output [2:0] light;
reg [2:0] light;

always@(in&&safe)
begin
    if(safe)
    begin
        //display green one
        if(in>=5'd13&&in<=5'd3) light=3'b100;
        //display yellow one
        else light=3'b010;
    end
    //display red one
    else light=3'b001;
end
endmodule
module lab11(reset,clk,out1,out10,row,column,light);
input reset,clk;

//display need to declear as output and wire
output [6:0]out1;
output [6:0]out10;
output [7:0]row;
output [7:0]column;
output [2:0]light;

wire [6:0]out1;
wire [6:0]out10;
wire [7:0]row;
wire [7:0]column;
wire [2:0]light;
//

//logic counter neeed to declear as reg
reg [31:0]count;
reg [4:0]second;
reg safe;
//

displayNumber DISNUM (.in(second),.out10(out10),.out1(out1));
displayGraph DISGPH (.safe(safe),.row(row),.column(column),.count(count));
displayLight DISLIT (.in(second),.safe(safe),.light(light));

always@(posedge clk,negedge reset)
begin
    if(reset)
    begin
        count<=32'd0;
        second<=5'd13;
        safe<=1'b1;
    end
    else
    begin
        if(count==`TimeExpire)
        begin
            count<=32'd0;
            if(second==5'd0&&safe==1'b1)
            begin
                second=5'd7;
                safe=1'b0;
            end
            else if(second==5'd0&&safe==1'b0)
            begin
                second=5'd13;
                safe=1'b1;
            end
            else
            begin
                second=second-1'b1;
            end
        end
        else count<=count+32'd1;
    end
end
endmodule
module adder_substractor (a,b,select,out);
input [3:0]a;
input [3:0]b;
input select;
output [4:0]out;
reg [4:0]out;
always @(select or a or b)
begin 
	if (select)
	begin 
		out = a+b;
	end
	else
	begin 
		out = a-b;
	end
end
endmodule
module encoder (in,out,valid);
input [7:0]in;
output valid;
output [2:0]out;
reg [2:0]out;
reg valid;
always @ (in)
begin 
	case (in)
		8'b00000001: begin
			out = 3'b000;
			valid = 1;
		end
		8'b00000010: begin
			out = 3'b001;
			valid = 1;
		end
		8'b00000100: begin
			out = 3'b010;
			valid = 1;
		end
		8'b00001000: begin
			out = 3'b011;
			valid = 1;
		end
		8'b00010000: begin
			out = 3'b100;
			valid = 1;
		end
		8'b00100000: begin
			out = 3'b101;
			valid = 1;
		end
		8'b01000000: begin
			out = 3'b110;
			valid = 1;
		end
		8'b10000000: begin
			out = 3'b111;
			valid = 1;
		end
		default: begin 
			out = 3'b000;
			valid = 0;
		end
	endcase
end
endmodule
module multiplexer (in,out);
input [3:0]in;
output [6:0]out;
reg [6:0]out;
always @(in)
begin 
	case (in)
	4'd0: out = 7'b1000000;
	4'd1: out = 7'b1111001;
	4'd2: out = 7'b0100100;
	4'd3: out = 7'b0010010;
	4'd4: out = 7'b1111000;
	4'd5: out = 7'b0010000;
	4'd6: out = 7'b0100001;
	4'd7: out = 7'b0001110;
	endcase
end
endmodule
module dot_matrix(clk,rst,btn_left,btn_right,move_left, move_right, dot_row,dot_col);
	input clk,rst,btn_left,btn_right;
	output reg [7:0] dot_row;
	output reg [15:0] dot_col;
	
	output move_left,move_right;

	reg [31:0] cnt_div,cnt_dot;
	reg [15:0] dot_col_buff[0:7];
	reg [2:0] row_count;
	wire clk_div,clk_dot;

	btn_control left_btn_control(clk,rst,btn_left,move_left);
	btn_control right_btn_control(clk,rst,btn_right,move_right);
	
	
	clk_divi myclk (clk,rst,32'd6250000, clk_div);
	clk_divi myclk2 (clk,rst,32'd5000, clk_dot);
	
	always@ (posedge clk_dot or negedge rst)
	begin
		if (~rst)
		begin
			dot_row <= 8'd0;
			dot_col <= 16'd0;
			row_count <= 3'd0;
		end
		else
		begin
		    row_count <= row_count + 1;
			dot_col <= dot_col_buff[row_count];
		    case (row_count)
				3'd0: dot_row <= 8'b01111111;
				3'd1: dot_row <= 8'b10111111;
				3'd2: dot_row <= 8'b11011111;
				3'd3: dot_row <= 8'b11101111;
				3'd4: dot_row <= 8'b11110111;
				3'd5: dot_row <= 8'b11111011;
				3'd6: dot_row <= 8'b11111101;
				3'd7: dot_row <= 8'b11111110;
			endcase
		end
	end

	always@ (posedge clk_div or negedge rst)
	begin
		if (~rst)
		begin 
				dot_col_buff[0] <= 16'b0001110000000000;
				dot_col_buff[1] <= 16'b0001011000000000;
				dot_col_buff[2] <= 16'b0001111000000000;
				dot_col_buff[3] <= 16'b0011100000000000;
				dot_col_buff[4] <= 16'b1111110000000000;
				dot_col_buff[5] <= 16'b1111100000000000;
				dot_col_buff[6] <= 16'b0111100000000000;
				dot_col_buff[7] <= 16'b0010100000000000;
		end
		else
			begin 
				if (move_left)
				begin 
					dot_col_buff[0] <= {dot_col_buff[0][14:0],dot_col_buff[0][15]};
					dot_col_buff[1] <= {dot_col_buff[1][14:0],dot_col_buff[1][15]};
					dot_col_buff[2] <= {dot_col_buff[2][14:0],dot_col_buff[2][15]};
					dot_col_buff[3] <= {dot_col_buff[3][14:0],dot_col_buff[3][15]};
					dot_col_buff[4] <= {dot_col_buff[4][14:0],dot_col_buff[4][15]};
					dot_col_buff[5] <= {dot_col_buff[5][14:0],dot_col_buff[5][15]};
					dot_col_buff[6] <= {dot_col_buff[6][14:0],dot_col_buff[6][15]};
					dot_col_buff[7] <= {dot_col_buff[7][14:0],dot_col_buff[7][15]};
				end
				else if (move_right)
				begin 
					dot_col_buff[0] <= {dot_col_buff[0][0],dot_col_buff[0][15:1]};
					dot_col_buff[1] <= {dot_col_buff[1][0],dot_col_buff[1][15:1]};
					dot_col_buff[2] <= {dot_col_buff[2][0],dot_col_buff[2][15:1]};
					dot_col_buff[3] <= {dot_col_buff[3][0],dot_col_buff[3][15:1]};
					dot_col_buff[4] <= {dot_col_buff[4][0],dot_col_buff[4][15:1]};
					dot_col_buff[5] <= {dot_col_buff[5][0],dot_col_buff[5][15:1]};
					dot_col_buff[6] <= {dot_col_buff[6][0],dot_col_buff[6][15:1]};
					dot_col_buff[7] <= {dot_col_buff[7][0],dot_col_buff[7][15:1]};
				end
				
		end
	end

endmodule
module btn_control(clk,rst,btn_signal,move);
	input clk,rst,btn_signal;
	output reg move;

	reg [31:0] cnt;

	always@(posedge clk or negedge rst)
	begin
		if (~rst)
		begin
			move <= 1'b0;
			cnt <= 32'd0;
		end
		else
		begin

			if (cnt == 12500000)
			begin
				move <= 1'b0;
				cnt <= 32'd0;
			end
			else if(cnt[7:0] == 8'd0)
			begin
				move <= (!btn_signal)? 1'b1 : move;
				cnt <= cnt + 32'b1;
			end
			else
			begin
				cnt <= cnt + 32'b1;
			end
		end
	end

endmodule
module clk_divi (clk,rst,counter,div_clk);
input clk,rst;
input [31:0]counter;
output div_clk;
reg div_clk;
reg [31:0]count;
always @ (posedge clk)
begin 
	if (!rst)
	begin 
	count <= 32'd0;
	div_clk <=1'b0;
	end
	else
	begin 
	if (count == counter)
	begin 
	count<=32'd0;
	div_clk <=~div_clk;
	end
	else
	begin 
		count <= count + 32'd1;
end
end
end
endmodule
module full_adder (cin, a,b, sum, cout);
input cin,a,b;
output sum,cout;
wire temp,store,result;
xor (temp,a,b);
xor (sum,temp,cin);
and (result,a,b);
and (store,temp,cin);
or (cout,result, store);
endmodule
module checkkeypad (clk,rst,keypadRow,keypadCol,keypadBuf);  // output keypad buffer
	input clk,rst;
	input [3:0]keypadCol;
	output reg[3:0]keypadRow;
	output reg [4:0]keypadBuf;
	reg [31:0]keypadDelay;
	
	always @(posedge clk or negedge rst)
	begin 
		if (!rst)
		begin
			keypadRow <= 4'b1110;
			keypadBuf <= 5'b11111;
			keypadDelay <= 31'd0;
		end
		else
		begin
			if (keypadDelay == 32'd250000) 
			begin 
				keypadDelay <= 31'd0;
				case ({keypadRow, keypadCol})
					8'b1110_1110: keypadBuf <= 5'h7;
					8'b1110_1101: keypadBuf <= 5'h4;
					8'b1110_1011: keypadBuf <= 5'h1;
					8'b1110_0111: keypadBuf <= 5'h0;
					8'b1101_1110: keypadBuf <= 5'h8;
					8'b1101_1101: keypadBuf <= 5'h5;
					8'b1101_1011: keypadBuf <= 5'h2;
					8'b1101_0111: keypadBuf <= 5'ha;
					8'b1011_1110: keypadBuf <= 5'h9;
					8'b1011_1101: keypadBuf <= 5'h6;
					8'b1011_1011: keypadBuf <= 5'h3;
					8'b1011_0111: keypadBuf <= 5'hb;
					8'b0111_1110: keypadBuf <= 5'hc;
					8'b0111_1101: keypadBuf <= 5'hd;
					8'b0111_1011: keypadBuf <= 5'he;
					8'b0111_0111: keypadBuf <= 5'hf;
					default: keypadBuf <= keypadBuf;
				endcase
				case (keypadRow)
					4'b1110: keypadRow <= 4'b1101;
					4'b1101: keypadRow <= 4'b1011;
					4'b1011: keypadRow <= 4'b0111;
					4'b0111: keypadRow <= 4'b1110;
					default: keypadRow <= 4'b1110;
				endcase
			end
			else
				keypadDelay <= keypadDelay + 1'b1;
		end
	end
endmodule
module clk_divi (clk,rst,counter,div_clk);
	input clk,rst;
	input [31:0]counter;
	output div_clk;
	reg div_clk;
	reg [31:0]count;
	always @ (posedge clk)
	begin 
		if (!rst)
		begin 
		count <= 32'd0;
		div_clk <=1'b0;
		end
		else
		begin 
			if (count == counter)
			begin 
			count<=32'd0;
			div_clk <=~div_clk;
			end
			else
			begin 
				count <= count + 32'd1;
			end
		end
   end
endmodule
module number_display (select,out1, out2, out3);
input [1:0]select;
output [6:0]out1;
output [6:0]out2;
output [6:0]out3;
reg [6:0]out1;
reg [6:0]out2;
reg [6:0]out3;
always @ (select)
begin 
	case (select)
	2'b00:begin
		out1 = 7'b1000000;
		out2 = 7'b1111001;
		out3 = 7'b0100100;
	end
	2'b01:begin
		out1 = 7'b0000010;
		out2 = 7'b1111000;
		out3 = 7'b0000000;
	end
	2'b10:begin
		out1 = 7'b0110000;
		out2 = 7'b0100100;
		out3 = 7'b1111001;
	end
	2'b11:begin
		out1 = 7'b0000110;
		out2 = 7'b0001000;
		out3 = 7'b0001000;
	end
	endcase
end
endmodule
module hold1clk(
clk,
reset,
stage_enable_in,
stage_enable_out
);


input clk;
input reset;
input stage_enable_in;
output  stage_enable_out;

reg stage_enable_out;


always @ (posedge clk or negedge reset)
begin
    if(!reset)
      begin
			    stage_enable_out <= 1'b0;
      end
    else
      begin
          if(stage_enable_in == 1'b1)
            begin
               stage_enable_out <= 1'b1;
            end
          else stage_enable_out <= 1'b0;
      end
end

























endmodule
module pll_clk(
   clk_125m_sys,
   clk_125m_core,
   clk_25m_core,
   clk_125m_tx0_7,
   clk_125m_tx8_15,
   clk_25m_tx,
	clk_12m_5_mdio
  );
  input clk_125m_sys;
  output clk_125m_tx0_7;
  output clk_125m_core;
  output clk_25m_core;
  output clk_125m_tx8_15;
  output clk_25m_tx;
  output clk_12m_5_mdio;
wire clk_125m_tx0_7;
wire clk_125m_core;
wire clk_25m_core;
wire clk_125m_tx8_15;
wire clk_25m_tx;
wire clk_12m_5_mdio;
pll_0 pll_0(
	.inclk0(clk_125m_sys),//125M  sys
	.c0(clk_125m_core),
	.c1(clk_25m_core),
	.c2(clk_125m_tx0_7),//port tx clk 0-7;
	.c3(clk_125m_tx8_15),//port tx clk 8-15;
	.c4(clk_25m_tx),
	.c5(clk_12m_5_mdio),
	.locked());   
endmodule
module alt_ddrx_decoder #
    ( parameter
        INPUT_DATA_WIDTH  = 72,
        OUTPUT_DATA_WIDTH = 64
    )
    (
        ctl_clk,
        input_data,
        err_corrected,
        err_detected,
	    err_fatal,
        output_data
    );

input  ctl_clk;
input  [INPUT_DATA_WIDTH  - 1 : 0] input_data;
output [OUTPUT_DATA_WIDTH - 1 : 0] output_data;
output err_corrected;
output err_detected;
output err_fatal;

wire   [OUTPUT_DATA_WIDTH - 1 : 0] output_data;
wire   err_corrected;
wire   err_detected;
wire   err_fatal;

generate
    if (INPUT_DATA_WIDTH == 40)
    begin
        // encoder only have 32/29 combination
        alt_ddrx_decoder_40 decoder_40_inst
            (
	            .clock         (ctl_clk),
	            .data          (input_data [INPUT_DATA_WIDTH - 2 : 0]),
                .err_corrected (err_corrected),
                .err_detected  (err_detected),
	            .err_fatal     (err_fatal),
	            .q             (output_data)
            );
    end
    else if (INPUT_DATA_WIDTH == 72)
    begin
        alt_ddrx_decoder_72 decoder_72_inst
            (
	            .clock         (ctl_clk),
	            .data          (input_data),
                .err_corrected (err_corrected),
                .err_detected  (err_detected),
	            .err_fatal     (err_fatal),
	            .q             (output_data)
            );
    end
endgenerate

endmodule
module ddr2_ex_lfsr8 (
clk, reset_n, enable, pause, load, data, ldata);

   parameter seed  = 32;
   input clk;
   input reset_n;
   input enable;
   input pause;
   input load;
   output[8 - 1:0] data;
   wire[8 - 1:0] data;
   input[8 - 1:0] ldata;

   reg[8 - 1:0] lfsr_data;

   assign data = lfsr_data ;

   always @(posedge clk or negedge reset_n)
   begin
      if (!reset_n)
      begin
         // Reset - asynchronously reset to seed value
         lfsr_data <= seed[7:0] ;
      end
      else
      begin
         if (!enable)
         begin
            lfsr_data <= seed[7:0];
         end
         else
         begin
            if (load)
            begin
               lfsr_data <= ldata ;
            end
            else
            begin
               // Registered mode - synchronous propagation of signals
               if (!pause)
               begin
                  lfsr_data[0] <= lfsr_data[7] ;
                  lfsr_data[1] <= lfsr_data[0] ;
                  lfsr_data[2] <= lfsr_data[1] ^ lfsr_data[7] ;
                  lfsr_data[3] <= lfsr_data[2] ^ lfsr_data[7] ;
                  lfsr_data[4] <= lfsr_data[3] ^ lfsr_data[7] ;
                  lfsr_data[5] <= lfsr_data[4] ;
                  lfsr_data[6] <= lfsr_data[5] ;
                  lfsr_data[7] <= lfsr_data[6] ;
               end
            end
         end
      end
   end
endmodule
module alt_ddrx_encoder #
    ( parameter
        INPUT_DATA_WIDTH  = 64,
        OUTPUT_DATA_WIDTH = 72
    )
    (
        ctl_clk,
        input_data,
        output_data
    );

input  ctl_clk;
input  [INPUT_DATA_WIDTH  - 1 : 0] input_data;
output [OUTPUT_DATA_WIDTH - 1 : 0] output_data;

wire   [OUTPUT_DATA_WIDTH - 1 : 0] output_data;

generate
    if (OUTPUT_DATA_WIDTH == 40)
    begin
        alt_ddrx_encoder_40 encoder_40_inst
            (
	            .clock (ctl_clk),
	            .data  (input_data),
	            .q     (output_data [OUTPUT_DATA_WIDTH - 2 : 0])
            );
        
        // encoder only have 32/29 combination, will have to hardcode MSB to '0'
        assign output_data [OUTPUT_DATA_WIDTH - 1] = 1'b0;
    end
    else if (OUTPUT_DATA_WIDTH == 72)
    begin
        alt_ddrx_encoder_72 encoder_72_inst
            (
	            .clock (ctl_clk),
	            .data  (input_data),
	            .q     (output_data)
            );
    end
endgenerate

endmodule
module ddr2_phy_alt_mem_phy_pll (
	areset,
	inclk0,
	phasecounterselect,
	phasestep,
	phaseupdown,
	scanclk,
	c0,
	c1,
	c2,
	c3,
	c4,
	c5,
	locked,
	phasedone);

	input	  areset;
	input	  inclk0;
	input	[3:0]  phasecounterselect;
	input	  phasestep;
	input	  phaseupdown;
	input	  scanclk;
	output	  c0;
	output	  c1;
	output	  c2;
	output	  c3;
	output	  c4;
	output	  c5;
	output	  locked;
	output	  phasedone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0	  areset;
	tri0	[3:0]  phasecounterselect;
	tri0	  phasestep;
	tri0	  phaseupdown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

endmodule