dakies/OSS_Verilog huggingface dataset:
module aibnd_nand_x64_delay_line ( out_p, so, code_valid, dll_reset_n,
     f_gray, i_gray, in_p, scan_rst_n, sck_in, se_n, si, sm_n,
     vcc_aibnd, vcc_io, vss_aibnd );

output  out_p, so;

input  code_valid, dll_reset_n, in_p, scan_rst_n, sck_in, se_n, si,
     sm_n, vcc_aibnd, vcc_io, vss_aibnd;

input [2:0]  i_gray;
input [6:0]  f_gray;

wire clk_buf0, clk_buf1, clk_prebuf, sm_n_buf, out_p, sck_in, nrst_mux, dll_reset_n, scan_rst_n, code_valid_sync, code_valid_buf, nrst, ck, se_n, se_n_buf, sm_n; // Conversion Sript Generated


// specify 
//     specparam CDS_LIBNAME  = "aibnd_lib";
//     specparam CDS_CELLNAME = "aibnd_nand_x64_delay_line";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign clk_buf1 = clk_buf0;
assign clk_buf0 = clk_prebuf;
assign clk_prebuf = sm_n_buf ? out_p : sck_in;
assign nrst_mux = sm_n_buf ? dll_reset_n : scan_rst_n;
aibnd_sync_ff xsync ( .vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd),
     .so(so_sync), .se_n(se_n_buf), .q(code_valid_sync), .rb(nrst),
     .clk(ck), .si(si), .d(code_valid));
aibnd_cmos_nand_x64 xcoarse ( .vss_aibnd(vss_aibnd),
     .vcc_aibnd(vcc_aibnd), .code_valid(code_valid_buf), .nrst(nrst),
     .ck(ck), .so(so_nand_x64), .se_n(se_n_buf), .si(so_sync),
     .vcc_io(vcc_io), .out_p(fout_p), .in_p(in_p), .gray(f_gray[6:0]));
assign code_valid_buf = code_valid_sync;
assign nrst = nrst_mux;
assign ck = clk_buf1;
assign se_n_buf = se_n;
assign sm_n_buf = sm_n;
aibnd_cmos_fine_dly xfine (.vss_aibnd(vss_aibnd), .vcc_aibnd(vcc_aibnd), .vcc_io(vcc_io),
     .code_valid(code_valid_buf), .so(so),
     .ck(ck), .nrst(nrst), .se_n(se_n_buf), .si(so_nand_x64),
     .gray(i_gray[2:0]), .out_p(out_p),
     .fout_p(fout_p));

endmodule
module aibnd_dcc_dly_inv ( a, o1, vcc_io, vss_io );

  input a;
  output o1;
  input vss_io;
  input vcc_io;


  assign o1 = ~a ;

endmodule
module aibnd_dcc_5b_b2tc_x1 ( therm, thermb, vcc_pl, vss_pl, q0, q1,
     q2, q3, q4, therm_p1 );

output  therm, thermb;

inout  vcc_pl, vss_pl;

input  q0, q1, q2, q3, q4, therm_p1;

wire net0353, q1, q0, therm, thermb, net0369, q4, q3, q2, net0565, therm_p1; // Conversion Sript Generated



assign net0353 = !(q1 & q0);
assign therm = !thermb;
assign net0369 = !(q4 & q3 & q2);
assign net0565 = !(net0369 | net0353);
assign thermb = !(net0565 | therm_p1);

endmodule
module aibnd_io_nand_delay_line_min_rep(
input         nfrzdrv,
input         in_p,
input         in_n,
output        out_p,
output        out_n
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter   NAND_DELAY = 20;

wire         fout_p;
wire         fout_n;
wire         osc_out_p;
wire         osc_out_n;

//---------------------------------------------------------------------------------------------------------------------------------------------
//  
//---------------------------------------------------------------------------------------------------------------------------------------------

io_cmos_nand_x1 xnandx1 (
.in_p       ( in_p	),
.in_n       ( in_n	),
.bk         ( 1'b0	),
.ci_p       ( 1'b1	),
.ci_n       ( 1'b1	),
.out_p      ( fout_p	),
.out_n      ( fout_n	),
.co_p       ( 		),
.co_n       ( 		)
);

aibnd_io_dly_interpolator_rep xinterp (
.nfrzdrv    ( nfrzdrv     ),
.fout_p     ( fout_p      ),
.fout_n     ( fout_n      ),
.gray       ( 3'b000      ),
.out_p      ( out_p       ),
.out_n      ( out_n       ),
.osc_out_p  ( osc_out_p   ),
.osc_out_n  ( osc_out_n   )
);

endmodule
module io_dq_clkdrv (
input          din_p,           	// 
input          din_n,           	//
output         dout_p,                  //
output         dout_n                  //
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter  INV_DELAY      = 15;  // 15ps

assign #(4 * INV_DELAY) dout_p = din_p;
assign #(4 * INV_DELAY) dout_n = din_n;

endmodule
module io_min_interp_mux (

input      [3:0] phy_clk_phs, // half of 8 phase 1.6GHz clock
input            svcc,        // for soft tie high
output           c_out        // 1 of the 3 output phases
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter  INVERTER_DELAY = 15;
parameter  FINGER_DELAY   = 45;

wire  out_vl;

//--------------------------------------------------------------------------------------------------
//  Finger Mux delay for phs[0]
//--------------------------------------------------------------------------------------------------

assign #FINGER_DELAY out_vl = phy_clk_phs[1];
assign #(2 * INVERTER_DELAY) c_out = out_vl;

endmodule
module io_min_ip16phs (
input        c_in,        // Clock in
input  [3:1] scp,         // filter_cap selection: 111 = 1.6 GHz, 110 = 1.2 GHz, 100 = 1.0 GHz, 000 = 0.8 GHz
input  [3:1] scn,         // filter_cap selection: 000 = 1.6 GHz, 001 = 1.2 GHz, 011 = 1.0 GHz, 111 = 0.8 GHz
output       c_out        // Clock out
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

`ifndef SYN
time        intrinsic;
time        c_time;
time        c_c_time;
time        calc_delay;
time        del_2x, rem_2x, del_1x, del_0x;
wire  [4:0] c_sig;
reg         pmx_2, pmx_1, pmx_0;

//--------------------------------------------------------------------------------------------------------------------------------------------
//--- Calculate the delay of the interpolator
//--------------------------------------------------------------------------------------------------------------------------------------------

always @(*)
  case (scn[3:1])
    3'b000 : intrinsic = 200;  // Supports 0.95 GHz - 1.9 GHz
    3'b001 : intrinsic = 260;  // Supports 0.75 GHz - 1.5 GHz
    3'b011 : intrinsic = 320;  // Supports 0.60 GHz - 1.2 GHz
    3'b111 : intrinsic = 400;  // Supports 0.50 GHz - 1.0 GHz
    default : intrinsic = 400;  // Supports 0.50 GHz - 1.0 GHz
  endcase

always @(posedge c_in)  c_time = $time;
always @(negedge c_in)
  begin
    #100                                 ;
    c_c_time = $time - c_time            ;
    calc_delay = intrinsic - (c_c_time/4);

    del_2x = calc_delay / 100;          // 100 ps
    rem_2x = calc_delay - (del_2x * 100);
    del_1x = rem_2x / 10;               // 10  ps
    del_0x = rem_2x - (del_1x * 10);    // 1   ps

  end

//--------------------------------------------------------------------------------------------------------------------------------------------
//---  Delay the signal
//--------------------------------------------------------------------------------------------------------------------------------------------

assign #10  c_sig[0] = c_in;
assign #100 c_sig[1] = c_sig[0];
assign #100 c_sig[2] = c_sig[1];
assign #100 c_sig[3] = c_sig[2];
assign #100 c_sig[4] = c_sig[3];

always @(*)
  case (del_2x)
    0 : pmx_2 =  c_sig[0];
    1 : pmx_2 =  c_sig[1];
    2 : pmx_2 =  c_sig[2];
    3 : pmx_2 =  c_sig[3];
    4 : pmx_2 =  c_sig[4];
    default : pmx_2 =  c_sig[4];
  endcase

always @(*)
  case (del_1x)
    0 : pmx_1 = #0  pmx_2;
    1 : pmx_1 = #10 pmx_2;
    2 : pmx_1 = #20 pmx_2;
    3 : pmx_1 = #30 pmx_2;
    4 : pmx_1 = #40 pmx_2;
    5 : pmx_1 = #50 pmx_2;
    6 : pmx_1 = #60 pmx_2;
    7 : pmx_1 = #70 pmx_2;
    8 : pmx_1 = #80 pmx_2;
    9 : pmx_1 = #90 pmx_2;
    default : pmx_1 = #90 pmx_2;
  endcase

always @(*)
  case (del_0x)
    0 : pmx_0 = #0 pmx_1;
    1 : pmx_0 = #1 pmx_1;
    2 : pmx_0 = #2 pmx_1;
    3 : pmx_0 = #3 pmx_1;
    4 : pmx_0 = #4 pmx_1;
    5 : pmx_0 = #5 pmx_1;
    6 : pmx_0 = #6 pmx_1;
    7 : pmx_0 = #7 pmx_1;
    8 : pmx_0 = #8 pmx_1;
    9 : pmx_0 = #9 pmx_1;
    default : pmx_0 = #9 pmx_1;
  endcase

assign c_out = pmx_0;

`else
assign c_out = c_in;
`endif

endmodule
module io_interp_latch_in (
input             l_reset_n,        	// Active low reset
input             clk,      	 	// clock for latch
input       [2:0] mux_sel_in,       	// The gray code to control (even) of the 8 to 1 phase multiplexer
output reg  [2:0] mux_sel_latch,    	// latched gray code to control (even) of the 8 to 1 phase multiplexer
output 	    [2:0] mux_sel_buf,    	// buffered gray code to control (even) of the 8 to 1 phase multiplexer
output 	    [2:0] mux_sel_inv    	// inverted gray code to control (even) of the 8 to 1 phase multiplexer
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter  INV_DELAY      = 15;  // 15ps
parameter  LATCH_DELAY    = 50;  // 50ps
parameter  BUF_DELAY      = 25;  // 25ps
parameter  MUX_DELAY      = 50;  // 50ps

//=========================================================================================================================================================================
// io_interpolator_mux selects 3 of the 8 input clock phases (A complimentary set) 
//=========================================================================================================================================================================

always @(*) 
  if (~l_reset_n)         mux_sel_latch[2:0] <= #LATCH_DELAY 3'h0;
  else if (clk) mux_sel_latch[2:0] <= #LATCH_DELAY mux_sel_in[2:0];

assign mux_sel_buf = mux_sel_latch[2:0];
assign mux_sel_inv = ~mux_sel_latch[2:0];

endmodule
module io_phs_check (
input            rst_n,
input            sample_clk,
input      [7:0] ph_in,
output 	   [7:0] ph_and_sample,
output     [3:0] ph_sample 
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

wire [7:0]  ph_and;       // and neighboring phases
wire [7:0]  ph_or;        // or neighboring phases

parameter  FF_DELAY = 100;

assign ph_and[7:0] = ph_in[7:0] & {ph_in[0],ph_in[7:1]};
assign ph_or[7:0] = {ph_in[3:0],ph_in[7:4]} | {ph_in[4:0],ph_in[7:5]};

io_phdet_ff_ln ph_sample_reg_0 (
.dp     ( ph_in[0] 	),
.dn     ( ph_in[4] 	),
.clk_p  ( sample_clk  	),
.rst_n  ( rst_n 	),
.q      ( ph_sample[0] 	)
);

io_phdet_ff_ln ph_sample_reg_1 (
.dp     ( ph_in[1] 	),
.dn     ( ph_in[5] 	),
.clk_p  ( sample_clk  	),
.rst_n  ( rst_n 	),
.q      ( ph_sample[1] 	)
);

io_phdet_ff_ln ph_sample_reg_2 (
.dp     ( ph_in[2] 	),
.dn     ( ph_in[6] 	),
.clk_p  ( sample_clk  	),
.rst_n  ( rst_n 	),
.q      ( ph_sample[2] 	)
);

io_phdet_ff_ln ph_sample_reg_3 (
.dp     ( ph_in[3] 	),
.dn     ( ph_in[7] 	),
.clk_p  ( sample_clk  	),
.rst_n  ( rst_n 	),
.q      ( ph_sample[3] 	)
);

io_phdet_ff_ln ph_and_sample_reg_0 (
.dp     ( ph_and[0]	 	),
.dn     ( ph_or[0]	 	),
.clk_p  ( sample_clk  		),
.rst_n  ( rst_n 		),
.q      ( ph_and_sample[0] 	)
);

io_phdet_ff_ln ph_and_sample_reg_1 (
.dp     ( ph_and[1]	 	),
.dn     ( ph_or[1]	 	),
.clk_p  ( sample_clk  		),
.rst_n  ( rst_n 		),
.q      ( ph_and_sample[1] 	)
);

io_phdet_ff_ln ph_and_sample_reg_2 (
.dp     ( ph_and[2]	 	),
.dn     ( ph_or[2]	 	),
.clk_p  ( sample_clk  		),
.rst_n  ( rst_n 		),
.q      ( ph_and_sample[2] 	)
);

io_phdet_ff_ln ph_and_sample_reg_3 (
.dp     ( ph_and[3]	 	),
.dn     ( ph_or[3]	 	),
.clk_p  ( sample_clk  		),
.rst_n  ( rst_n 		),
.q      ( ph_and_sample[3] 	)
);

io_phdet_ff_ln ph_and_sample_reg_4 (
.dp     ( ph_and[4]	 	),
.dn     ( ph_or[4]	 	),
.clk_p  ( sample_clk  		),
.rst_n  ( rst_n 		),
.q      ( ph_and_sample[4] 	)
);

io_phdet_ff_ln ph_and_sample_reg_5 (
.dp     ( ph_and[5]	 	),
.dn     ( ph_or[5]	 	),
.clk_p  ( sample_clk  		),
.rst_n  ( rst_n 		),
.q      ( ph_and_sample[5] 	)
);

io_phdet_ff_ln ph_and_sample_reg_6 (
.dp     ( ph_and[6]	 	),
.dn     ( ph_or[6]	 	),
.clk_p  ( sample_clk  		),
.rst_n  ( rst_n 		),
.q      ( ph_and_sample[6] 	)
);

io_phdet_ff_ln ph_and_sample_reg_7 (
.dp     ( ph_and[7]	 	),
.dn     ( ph_or[7]	 	),
.clk_p  ( sample_clk  		),
.rst_n  ( rst_n 		),
.q      ( ph_and_sample[7] 	)
);

endmodule
module io_cmos_nand_x64 (
input         b63,
input         d63,
input         in_p,
input         in_n,
input   [6:0] gray,
output        a63,
output        c63,
output        out_p,
output        out_n
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter   NAND_DELAY = 20;

wire [63:0]  bk;
wire [62:0]  a;
wire [62:0]  b;
wire [62:0]  c;
wire [62:0]  d;

io_cmos_nand_x64_decode xdec (
.gray	    ( gray[6:0]		),
.bk	    ( bk[63:0]		)
);

io_cmos_nand_x6 xnand_x6 [9:0] (
.in_p       ( {a[53],a[47],a[41],a[35],a[29],a[23],a[17],a[11],a[5],in_p}     	),
.in_n       ( {c[53],c[47],c[41],c[35],c[29],c[23],c[17],c[11],c[5],in_n}     	),
.bk5        ( {bk[59],bk[53],bk[47],bk[41],bk[35],bk[29],bk[23],bk[17],bk[11],bk[5]} ),
.bk4        ( {bk[58],bk[52],bk[46],bk[40],bk[34],bk[28],bk[22],bk[16],bk[10],bk[4]} ),
.bk3        ( {bk[57],bk[51],bk[45],bk[39],bk[33],bk[27],bk[21],bk[15],bk[9],bk[3]}  ),
.bk2        ( {bk[56],bk[50],bk[44],bk[38],bk[32],bk[26],bk[20],bk[14],bk[8],bk[2]}  ),
.bk1        ( {bk[55],bk[49],bk[43],bk[37],bk[31],bk[25],bk[19],bk[13],bk[7],bk[1]}  ),
.bk0        ( {bk[54],bk[48],bk[42],bk[36],bk[30],bk[24],bk[18],bk[12],bk[6],bk[0]}  ),
.ci_p       ( {b[59],b[53],b[47],b[41],b[35],b[29],b[23],b[17],b[11],b[5]}    	),
.ci_n       ( {d[59],d[53],d[47],d[41],d[35],d[29],d[23],d[17],d[11],d[5]}     	),
.out_p      ( {b[53],b[47],b[41],b[35],b[29],b[23],b[17],b[11],b[5],out_p}    	),
.out_n      ( {d[53],d[47],d[41],d[35],d[29],d[23],d[17],d[11],d[5],out_n}    	),
.co_p       ( {a[59],a[53],a[47],a[41],a[35],a[29],a[23],a[17],a[11],a[5]}     	),
.co_n       ( {c[59],c[53],c[47],c[41],c[35],c[29],c[23],c[17],c[11],c[5]}     	)
);

io_cmos_nand_x4 xnand_x4 (
.in_p       ( a[59]	),
.in_n       ( c[59]	),
.bk3        ( bk[63]	),
.bk2        ( bk[62]	),
.bk1        ( bk[61]	),
.bk0        ( bk[60]	),
.ci_p       ( b63	),
.ci_n       ( d63	),
.out_p      ( b[59]	),
.out_n      ( d[59]	),
.co_p       ( a63	),
.co_n       ( c63	)
);

endmodule
module io_pa_phs_gated (
input          nfrzdrv,           	// power down active low
input    [7:0] phy_clk_phs,             // 8 phase 1.6GHz local clock
output   [7:0] phy_clk_phs_gated        // gated 8 phase 1.6GHz local clock
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter  INV_DELAY      = 15;  // 15ps

assign #(2 * INV_DELAY) phy_clk_phs_gated[3:0] = phy_clk_phs[3:0] & {4{nfrzdrv}};
assign #(2 * INV_DELAY) phy_clk_phs_gated[7:4] = phy_clk_phs[7:4] | {4{~nfrzdrv}};

endmodule
module io_cmos_nand_x4 (
input         ci_p,
input         ci_n,
input         in_p,
input         in_n,
input         bk3,
input         bk2,
input         bk1,
input         bk0,
output        co_p,
output        co_n,
output        out_p,
output        out_n
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

wire [2:0]  a;
wire [2:0]  b;
wire [2:0]  c;
wire [2:0]  d;

parameter   NAND_DELAY = 20;

io_cmos_nand_x1 UD00 [3:0] (
.in_p       ( {a[2:0],in_p}     	),
.in_n       ( {c[2:0],in_n}     	),
.bk         ( {bk3,bk2,bk1,bk0} 	),
.ci_p       ( {ci_p,b[2:0]}      	),
.ci_n       ( {ci_n,d[2:0]}      	),
.out_p      ( {b[2:0],out_p}    	),
.out_n      ( {d[2:0],out_n}    	),
.co_p       ( {co_p,a[2:0]}      	),
.co_n       ( {co_n,c[2:0]}      	)
);

endmodule
module io_phs_gated (
input          nfrzdrv,           	// power down active low
input    [7:0] phy_clk_phs,             // 8 phase 1.6GHz local clock
output   [7:0] phy_clk_phs_gated        // gated 8 phase 1.6GHz local clock
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter  INV_DELAY      = 15;  // 15ps

assign #(2 * INV_DELAY) phy_clk_phs_gated[3:0] = phy_clk_phs[3:0] & {4{nfrzdrv}};
assign #(2 * INV_DELAY) phy_clk_phs_gated[7:4] = phy_clk_phs[7:4] | {4{~nfrzdrv}};

endmodule
module io_dly_interpclk (
input         nfrzdrv,
input         fout_p,
input         fout_n,
output        a_in_p,
output        b_in_p,
output        c_in_p,
output        a_in_n,
output        b_in_n,
output        c_in_n
);

`ifdef TIMESCALE_EN
		timeunit 1ps; 
		timeprecision 1ps; 
`endif

parameter   NAND_DELAY = 20;

assign #(0 * NAND_DELAY) a_in_p = nfrzdrv? fout_p : 1'b0;
assign #(2 * NAND_DELAY) b_in_p = nfrzdrv? fout_p : 1'b0;
assign #(4 * NAND_DELAY) c_in_p = nfrzdrv? fout_p : 1'b0;

assign #(0 * NAND_DELAY) a_in_n = nfrzdrv? fout_n : 1'b1;
assign #(2 * NAND_DELAY) b_in_n = nfrzdrv? fout_n : 1'b1;
assign #(4 * NAND_DELAY) c_in_n = nfrzdrv? fout_n : 1'b1;

/*
io_interp_basecap xxcapap (
.cin	(a_in_p	)
);

io_interp_basecap xxcapbp (
.cin	(b_in_p	)
);

io_interp_basecap xxcapcp (
.cin	(c_in_p	)
);

io_interp_basecap xxcapan (
.cin	(a_in_n	)
);

io_interp_basecap xxcapbn (
.cin	(b_in_n	)
);

io_interp_basecap xxcapcn (
.cin	(c_in_n	)
);

*/

endmodule
module io_filter_dec (
input	   [1:0] filter_code,      // 00 = 1.6 GHz, 01 = 1.2 GHz, 10 = 1.0 GHz, 11 = 0.8 GHz
output	   [3:1] scp,     
output reg [3:1] scn     
);

//filter code decode

always @(*)
  case (filter_code[1:0])
    2'b00 :  scn[3:1] = 3'b000;
    2'b01 :  scn[3:1] = 3'b001;
    2'b10 :  scn[3:1] = 3'b011;
    2'b11 :  scn[3:1] = 3'b111;
  endcase
assign scp[3:1] = ~scn[3:1];

endmodule
module io_nand_x128_delay_line (
input         nfrzdrv,
input         in_p,
input         in_n,
input         osc_mode,           // Mux control for the x64 ring oscillator
input         osc_in_p,           // input for the x64 ring oscillator
input         osc_in_n,           // input for the x64 ring oscillator
output        osc_out_p,          // output for the x64 ring oscillator
output        osc_out_n,          // output for the x64 ring oscillator
input   [6:0] f_gray,
input   [2:0] i_gray,
output        out_p,
output        out_n
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter   NAND_DELAY         = 20;

wire         fout_p;
wire         fout_n;
wire         x128_in_p;
wire         x128_in_n;

//---------------------------------------------------------------------------------------------------------------------------------------------
//  input mux
//---------------------------------------------------------------------------------------------------------------------------------------------

assign x128_in_p  = osc_mode ? osc_in_p : in_p;
assign x128_in_n  = osc_mode ? osc_in_n : in_n;

io_cmos_nand_x128 xnand128 (
.in_p        ( x128_in_p    ),
.in_n        ( x128_in_n    ),
.gray        ( f_gray[6:0]  ),
.out_p       ( fout_p       ),
.out_n       ( fout_n       )
);

io_dly_interpolator xinterp (
.nfrzdrv    ( nfrzdrv     ),
.fout_p     ( fout_p      ),
.fout_n     ( fout_n      ),
.gray       ( i_gray[2:0] ),
.out_p      ( out_p       ),
.out_n      ( out_n       ),
.osc_out_p  ( osc_out_p   ),
.osc_out_n  ( osc_out_n   )

);

endmodule
module io_interp_output (
input          clk_n_buf0,
input          clk_n_buf2,
input          clk_p_buf0,
input          clk_p_buf2,
input    [1:0] dirty_clk,        // The divided clock outputs with a duty cycle that is not 50%, The Interpolator will modify this clock to 50% duty cycle
input          enable,           // Active high enable    0 = Force interpolator_clk[1:0] to 2'b10
input    [1:0] interp_clk_x,     // interpolator clk after ip16phs
input          reset_n,          // Active low reset
input          test_enable_n,    // Active low test enable
input          pon,		 // cross coupling enable p finger
input          non,		 // cross coupling enable n finger
output   [1:0] int_clk_out,      // Complimentary Clock output sent to the dqs_lgc_pnr/ioereg_pnr
output   [1:0] interpolator_clk  // Complimentary Clock output sent to the ioereg
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter  INV_DELAY      = 15;  // 15ps
parameter  LATCH_DELAY    = 50;  // 50ps
parameter  BUF_DELAY      = 25;  // 25ps
parameter  MUX_DELAY      = 50;  // 50ps

reg  [1:0] dirty_clk_int;
reg  [1:0] dirty_clk_out;
wire [1:0] interp_clk;

//=========================================================================================================================================================================
// output merge, clock divider & interpolator
//=========================================================================================================================================================================

always @(*)
  if (~reset_n)          dirty_clk_int[0] <= #LATCH_DELAY 1'b0;
  else if (clk_n_buf0)   dirty_clk_int[0] <= #LATCH_DELAY ~dirty_clk[0];

always @(*)
  if (~reset_n)          dirty_clk_int[1] <= #LATCH_DELAY 1'b0;
  else if (clk_p_buf0)   dirty_clk_int[1] <= #LATCH_DELAY dirty_clk[1];

always @(*)
  if (~reset_n)          dirty_clk_out[0] <= #LATCH_DELAY 1'b0;
  else if (clk_n_buf2)   dirty_clk_out[0] <= #LATCH_DELAY dirty_clk_int[0];

always @(*)
  if (~reset_n)          dirty_clk_out[1] <= #LATCH_DELAY 1'b0;
  else if (clk_p_buf2)   dirty_clk_out[1] <= #LATCH_DELAY dirty_clk_int[1];

assign interp_clk = interp_clk_x[1:0];

an_io_double_edge_ff xdouble_edge_ff (
.clk_in      	( interp_clk[1:0]     ),
.reset_n     	( enable              ),
.test_enable_n  ( test_enable_n       ),
.data_in     	( {dirty_clk_out[1],~dirty_clk_out[0]} ),
.data_out    	( int_clk_out[1:0]    )
);

assign interpolator_clk[1:0] = int_clk_out[1:0];  // needs a balanced buffer to keep the matched timing for clk_out[1:0] signals

endmodule
module io_phdet_ff_ln (dp, dn, clk_p, rst_n, q);
input  dp, dn, clk_p, rst_n;
output q;
reg    q;

always @(posedge clk_p or negedge rst_n)
  if (~rst_n)           q <= 1'b0;
  else                  q <= dp;

endmodule // io_phdet_ff_ln
module io_nand_delay_line_min(
input         nfrzdrv,
input         in_p,
input         in_n,
output        out_p,
output        out_n
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter   NAND_DELAY = 20;

wire         fout_p;
wire         fout_n;
wire         osc_out_p;
wire         osc_out_n;

//---------------------------------------------------------------------------------------------------------------------------------------------
//  
//---------------------------------------------------------------------------------------------------------------------------------------------

io_cmos_nand_x1 xnandx1 (
.in_p       ( in_p	),
.in_n       ( in_n	),
.bk         ( 1'b0	),
.ci_p       ( 1'b1	),
.ci_n       ( 1'b1	),
.out_p      ( fout_p	),
.out_n      ( fout_n	),
.co_p       ( 		),
.co_n       ( 		)
);

io_dly_interpolator xinterp (
.nfrzdrv    ( nfrzdrv     ),
.fout_p     ( fout_p      ),
.fout_n     ( fout_n      ),
.gray       ( 3'b000      ),
.out_p      ( out_p       ),
.out_n      ( out_n       ),
.osc_out_p  ( osc_out_p   ),
.osc_out_n  ( osc_out_n   )
);

endmodule
module io_interp_mux_match (

input  [7:0] phy_clk_phs,   	// 8 phase 1.6GHz clock
input  [7:0] slow_clk_ph_p, 	// 8 phase 1.6GHz clock combined with reset
input  [7:0] slow_clk_ph_n, 	// 8 phase 1.6GHz clock combined with reset
input  [2:0] gray_a_buf,    	// Mux select A
input  [2:0] gray_a_inv,    	// inverted Mux select A
input  [2:0] gray_b_buf,    	// Mux select B
input  [2:0] gray_b_inv,    	// inverted Mux select B
input        nfrzdrv, 		// active low test enable
input        test_enable_n, 	// active low test enable
input        dft_mux_sel,   	// mux selection during test
output       int_clk_out     	// 1 of the 3 output phases, sent to the counter
);

wire	     int_clk_out_x;
wire	     mux_out_b;

io_interp_mux xinterp_mux ( 
.slow_clk_ph_p		(slow_clk_ph_p[7:0]	), 
.slow_clk_ph_n		(slow_clk_ph_n[7:0]	), 
.phy_clk_phs		(phy_clk_phs[7:0]	), 
.gray_a_buf		(gray_a_buf[2:0]	), 
.gray_b_buf		(gray_b_buf[2:0]	), 
.gray_a_inv		(gray_a_inv[2:0]	), 
.gray_b_inv		(gray_b_inv[2:0]	), 
.c_out			(			), 
.mux_out_b		(mux_out_b		), 
.test_enable_n		(test_enable_n		),  
.dft_mux_sel		(dft_mux_sel		)
);

assign int_clk_out_x = ~nfrzdrv | mux_out_b;
assign int_clk_out = int_clk_out_x;

endmodule
module io_min_pdn (
input          pdn,           		// power down active low
input    [7:0] phy_clk_phs,             // 8 phase 1.6GHz local clock
output   [7:0] phy_clk_phs_gated       // gated 8 phase 1.6GHz local clock
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter  INV_DELAY      = 15;  // 15ps

assign #(2 * INV_DELAY) phy_clk_phs_gated[3:0] = phy_clk_phs[3:0] & {4{pdn}};
assign #(2 * INV_DELAY) phy_clk_phs_gated[7:4] = phy_clk_phs[7:4] | {4{~pdn}};

endmodule
module io_ioereg_struct_out (
input  [1:0] interpolator_clk,   // Complimentary Clock output sent to io_ioereg_struct
input  [1:0] d_out_p_mux,        // I/O  : Output P transistor before the final output mux
input  [1:0] d_out_n_mux,        // I/O  : Output N transistor before the final output mux
output reg   codin_p,            // I/O  : The high speed data output sent to the P type transistor +
output reg   codin_pb,           // I/O  : The high speed data output sent to the P type transistor -
output reg   codin_n,            // I/O  : The high speed data output sent to the N type transistor +
output reg   codin_nb,           // I/O  : The high speed data output sent to the N type transistor -
input        latch_open_n,       // Static : 0 = force the latches open (GPIO & ATPG),  1 = clock the latches, Memory IF
input        nfrzdrv,            //  freez signal
input        loopback_p,         // I/O  : P-tran loopback
input        loopback_n,         // I/O  : N-tran loopback
input        loopback_en_n       // I/O  : Active low loopback enable
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter FF_DELAY    = 80;
parameter LATCH_DELAY = 70;
parameter MUX_DELAY   = 60;

wire [1:0] clk_bf;
reg  [1:0] latch_p;
reg  [1:0] latch_n;

//-----------------------------------------------------
// Output Mux
//-----------------------------------------------------
assign clk_bf[1:0] = nfrzdrv ? interpolator_clk[1:0] : 2'b10;

//always @(*)
always @(*)
  casez ({loopback_en_n,nfrzdrv,latch_open_n,clk_bf[1:0]})
   5'b0_?_?_?? : {latch_p[1:0],latch_n[1:0]} <= #LATCH_DELAY {loopback_p,loopback_p,loopback_n,loopback_n};
   5'b1_0_?_?? : {latch_p[1:0],latch_n[1:0]} <= #LATCH_DELAY {d_out_p_mux[1],d_out_p_mux[1],d_out_n_mux[1],d_out_n_mux[1]};
   5'b1_1_0_?? : {latch_p[1:0],latch_n[1:0]} <= #LATCH_DELAY {d_out_p_mux[1],d_out_p_mux[0],d_out_n_mux[1],d_out_n_mux[0]};
   5'b1_1_1_00 : {latch_p[1:0],latch_n[1:0]} <= #LATCH_DELAY {d_out_p_mux[1],d_out_p_mux[0],d_out_n_mux[1],d_out_n_mux[0]};
//   5'b1_1_1_01 : {latch_p[1:0],latch_n[1:0]} <= #LATCH_DELAY {d_out_p_mux[1],latch_p[0],d_out_n_mux[1],latch_n[0]};
//   5'b1_1_1_10 : {latch_p[1:0],latch_n[1:0]} <= #LATCH_DELAY {latch_p[1],d_out_p_mux[0],latch_n[1],d_out_n_mux[0]};
//   5'b1_1_1_11 : {latch_p[1:0],latch_n[1:0]} <= #LATCH_DELAY {latch_p[1],latch_p[0],latch_n[1],latch_n[0]};
   5'b1_1_1_01 : {latch_p[1],latch_n[1]} <= #LATCH_DELAY {d_out_p_mux[1],d_out_n_mux[1]};
   5'b1_1_1_10 : {latch_p[0],latch_n[0]} <= #LATCH_DELAY {d_out_p_mux[0],d_out_n_mux[0]};
   5'b1_1_1_11 : ;
  endcase

always @(*)
  casez ({nfrzdrv,interpolator_clk[1:0]})
   3'b0_?? : {codin_p,codin_pb,codin_n,codin_nb} = {latch_p[0],~latch_p[1],latch_n[0],~latch_n[1]};
   3'b1_00 : {codin_p,codin_pb,codin_n,codin_nb} = {latch_p[0],~latch_p[0],latch_n[0],~latch_n[0]};
   3'b1_01 : {codin_p,codin_pb,codin_n,codin_nb} = {latch_p[0],~latch_p[0],latch_n[0],~latch_n[0]};
   3'b1_10 : {codin_p,codin_pb,codin_n,codin_nb} = {latch_p[1],~latch_p[1],latch_n[1],~latch_n[1]};
   3'b1_11 : {codin_p,codin_pb,codin_n,codin_nb} = {latch_p[1],~latch_p[1],latch_n[1],~latch_n[1]};
  endcase

endmodule
module io_split_align (
input          din,           		// input
output         dout_p,           	// splitted output positive
output         dout_n           	// splitted output negative
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter  INV_DELAY      = 15;  // 15ps

assign #(2 * INV_DELAY) dout_p = din;
assign #(2 * INV_DELAY) dout_n = ~din;

endmodule
module io_min_misc (
input       [1:0] filter_code,      	// 00 = 1.6 GHz, 01 = 1.2 GHz, 10 = 1.0 GHz, 11 = 0.8 GHz
input       [1:0] c_out_x,      		// interpolator clock for pnr/dpa
input             couple_enable,    	// cross coupling enable
input             nfrzdrv,          	// for power domain crossing protection
input             test_enable,      	// Active high test enable    1: avoid tristate on output of interp_mux during testing
output      [1:0] c_out,			// interpolator clock for pnr/dpa
output            pon,        		// cross couple control for p fingers
output            non,        		// cross couple control for n fingers
output      [3:1] scp,              	// filter capacitance selection
output reg  [3:1] scn,              	// filter capacitance selection
output            svcc,        		// for test
output            test_enable_n      	// Active low test enable
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter  INV_DELAY      = 15;  // 15ps
parameter  LATCH_DELAY    = 50;  // 50ps
parameter  BUF_DELAY      = 25;  // 25ps
parameter  MUX_DELAY      = 50;  // 50ps

assign svcc = 1'b1;
assign test_enable_n        = ~test_enable;
assign #(2 * INV_DELAY) c_out[1:0] = c_out_x[1:0] & {2{nfrzdrv}};
assign non	    	    = couple_enable & test_enable_n;
assign pon	    	    = ~non;

//filter code decode
always @(*)
  case (filter_code[1:0])
    2'b00 :  scn[3:1] = 3'b000;
    2'b01 :  scn[3:1] = 3'b001;
    2'b10 :  scn[3:1] = 3'b011;
    2'b11 :  scn[3:1] = 3'b111;
  endcase
assign #INV_DELAY scp[3:1] = ~scn[3:1];

endmodule
module io_cmos_nand_x6 (
input         ci_p,
input         ci_n,
input         in_p,
input         in_n,
input         bk5,
input         bk4,
input         bk3,
input         bk2,
input         bk1,
input         bk0,
output        co_p,
output        co_n,
output        out_p,
output        out_n
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

wire [4:0]  a;
wire [4:0]  b;
wire [4:0]  c;
wire [4:0]  d;

parameter   NAND_DELAY = 20;

io_cmos_nand_x1 UD00 [5:0] (
.in_p       ( {a[4:0],in_p}     	),
.in_n       ( {c[4:0],in_n}     	),
.bk         ( {bk5,bk4,bk3,bk2,bk1,bk0} ),
.ci_p       ( {ci_p,b[4:0]}      	),
.ci_n       ( {ci_n,d[4:0]}      	),
.out_p      ( {b[4:0],out_p}    	),
.out_n      ( {d[4:0],out_n}    	),
.co_p       ( {co_p,a[4:0]}      	),
.co_n       ( {co_n,c[4:0]}      	)
);

endmodule
module io_dqs_clkdrv (
input          cin_p,           	// 
input          cin_n,           	//
output         cout_p,                  //
output         cout_n                  //
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter  INV_DELAY      = 15;  // 15ps

assign #(4 * INV_DELAY) cout_p = cin_p;
assign #(4 * INV_DELAY) cout_n = cin_n;

endmodule
module io_pa_phs_buf (
input          reset_n,          	// Active low reset
input          nfrzdrv,          	// Active low reset
input    [7:0] phy_clk_phs,      	// 8 phase 1.6GHz local clock
input          test_enable,      	// Active high test enable    1: avoid tristate on output of interp_mux during testing
input    [2:0] phx_sel_master_0,        // The gray code to control the first of the 8 to 1 phase multiplexer
input    [2:0] phx_sel_master_1,        // The gray code to control the first of the 8 to 1 phase multiplexer
input    [1:0] periphery_clk_x,         // periphery_clk from io_interpolator
input    [1:0] core_clk_x,              // core_clk from io_interpolator
output   [1:0] periphery_clk_out,       // Clock feedback to the periphery
output   [1:0] core_clk_out,            // Clock feedback to the core
output   [2:0] phx_master_0_buf,        // buffered gray code for interp_mux
output   [2:0] phx_master_1_buf,        // buffered gray code for interp_mux
output   [2:0] phx_master_0_inv,        // Inverted gray code for interp_mux
output   [2:0] phx_master_1_inv,        // Inverted gray code for interp_mux
output   [7:0] slow_clk_ph_p,           // buffered 8 phase 1.6GHz local clock
output   [7:0] slow_clk_ph_n,           // buffered 8 phase 1.6GHz local clock
output         test_enable_n,           // active low test enable
output         dft_mux_sel              // mux control during test
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter  INV_DELAY      = 15;  // 15ps

wire           test_rst_p;              // reset control for io_interp_mux
wire           test_rst_n;              // reset control for io_interp_mux
wire           test_enable_buf;         // active high test enable

assign test_enable_n        	= ~test_enable;
assign test_enable_buf      	= ~test_enable_n;
assign dft_mux_sel          	= ~(~phx_master_0_inv[0] & test_enable_buf);
assign test_rst_n           	= test_enable_n & reset_n;
assign test_rst_p           	= ~test_rst_n;
assign #(3 * INV_DELAY) slow_clk_ph_p[7:0] = phy_clk_phs[7:0] | {8{test_rst_p}};
assign #(3 * INV_DELAY) slow_clk_ph_n[7:0] = phy_clk_phs[7:0] & {8{test_rst_n}};
assign phx_master_0_buf   	= phx_sel_master_0[2:0];
assign phx_master_1_buf   	= phx_sel_master_1[2:0];
assign phx_master_0_inv   	= ~phx_sel_master_0[2:0];
assign phx_master_1_inv   	= ~phx_sel_master_1[2:0];
assign core_clk_out[1:0]        = {2{nfrzdrv}} & core_clk_x[1:0];
assign periphery_clk_out[1:0]   = {2{nfrzdrv}} & periphery_clk_x[1:0];

endmodule
module io_nand_x64_delay_line (
input         nfrzdrv,
input         in_p,
input         in_n,
input         osc_mode,           // Mux control for the x64 ring oscillator
input         osc_in_p,           // input for the x64 ring oscillator
input         osc_in_n,           // input for the x64 ring oscillator
output        osc_out_p,          // output for the x64 ring oscillator
output        osc_out_n,          // output for the x64 ring oscillator
input   [5:0] f_gray,
input   [2:0] i_gray,
output        out_p,
output        out_n
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter   NAND_DELAY = 20;

wire         x64_in_p;
wire         x64_in_n;
wire         fout_p;
wire         fout_n;
wire	     a63;
wire	     c63;


//---------------------------------------------------------------------------------------------------------------------------------------------
//  
//---------------------------------------------------------------------------------------------------------------------------------------------

assign x64_in_p   = osc_mode ? osc_in_p : in_p;
assign x64_in_n   = osc_mode ? osc_in_n : in_n;

io_cmos_nand_x64 xnand64 (
.b63        ( 1'b1         ),
.d63        ( 1'b1         ),
.in_p       ( x64_in_p         ),
.in_n       ( x64_in_n         ),
.gray       ( {1'b0, f_gray[5:0]}  ),
.a63        ( a63          ),
.c63        ( c63          ),
.out_p      ( fout_p       ),
.out_n      ( fout_n       )
);

io_dly_interpolator xinterp (
.nfrzdrv    ( nfrzdrv     ),
.fout_p     ( fout_p      ),
.fout_n     ( fout_n      ),
.gray       ( i_gray[2:0] ),
.out_p      ( out_p       ),
.out_n      ( out_n       ),
.osc_out_p  ( osc_out_p   ),
.osc_out_n  ( osc_out_n   )

);

endmodule
module io_cmos_nand_x1 (
input         in_p,
input         in_n,
input         bk,
input         ci_p,
input         ci_n,
output        out_p,
output        out_n,
output        co_p,
output        co_n
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter   NAND_DELAY = 20;

reg    tp;
reg    tn;

assign #NAND_DELAY co_p  = ~(in_p & bk);

always @(*)
  if (~in_p)    tp <= #NAND_DELAY 1'b1;
  else if (~bk) tp <= #NAND_DELAY 1'b0;

assign #NAND_DELAY out_p = ~(tp & ci_p);

assign #NAND_DELAY co_n  = ~(in_n & bk);

always @(*)
  if (~in_n)    tn <= #NAND_DELAY 1'b1;
  else if (~bk) tn <= #NAND_DELAY 1'b0;

assign #NAND_DELAY out_n = ~(tn & ci_n);

endmodule
module io_interp_misc (
input          reset_n,          	// Active low reset
input          test_enable,      	// Active high test enable    1: avoid tristate on output of interp_mux during testing
input          nfrzdrv,          	// for power domain crossing protection
input          couple_enable,    	// cross coupling enable
input          filter_code,      	// borrowed from filter_code[0] for test
input          clk_p_buf0,       	// Clock for pnr int_clk
input    [1:0] int_clk_out,      	// interpolator clock for pnr/dpa
input    [7:0] phy_clk_phs,      	// 8 phase 1.6GHz local clock
output   [7:0] slow_clk_ph_p,    	// 8 phase 1.6GHz local clock
output   [7:0] slow_clk_ph_n,    	// 8 phase 1.6GHz local clock
output         test_enable_buf,  	// Active high test enable    1: avoid tristate on output of interp_mux during testing
output         test_enable_frz,  	// Active high test enable    1: avoid tristate on output of interp_mux during testing
output         test_enable_n,    	// Active low test enable    0: avoid tristate on output of interp_mux during testing
output         l_reset_n,        	// Active low reset
output   [1:0] clk_out,			// interpolator clock for pnr/dpa
output         dft_mux_sel_n,        	// for test
output         dft_mux_sel_p,        	// for test
output         pon,        		// cross couple control for p fingers
output         non,        		// cross couple control for n fingers
output         int_clk	                // Clock for the counter
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter  INV_DELAY      = 15;  // 15ps
parameter  LATCH_DELAY    = 50;  // 50ps
parameter  BUF_DELAY      = 25;  // 25ps
parameter  MUX_DELAY      = 50;  // 50ps

wire	   test_rst_p;
wire	   test_rst_n;

assign #(2 * INV_DELAY) clk_out[1:0] = int_clk_out[1:0] & {2{nfrzdrv}};
assign #(2 * INV_DELAY) int_clk = clk_p_buf0 & nfrzdrv;
assign l_reset_n = reset_n;
assign test_enable_n        = ~test_enable;
assign test_enable_buf      = ~test_enable_n;
assign test_enable_frz      = ~(test_enable_n & nfrzdrv);
assign test_rst_n           = test_enable_n & reset_n;
assign test_rst_p           = ~test_rst_n;
assign #(3 * INV_DELAY) slow_clk_ph_p[7:0] = phy_clk_phs[7:0] | {8{test_rst_p}} | {8{~nfrzdrv}};
assign #(3 * INV_DELAY) slow_clk_ph_n[7:0] = phy_clk_phs[7:0] & {8{test_rst_n}} & {8{nfrzdrv}};
assign dft_mux_sel_p        = ~(~filter_code & test_enable_buf);
assign dft_mux_sel_n        = ~(filter_code & test_enable_buf);
assign non	    	    = couple_enable & test_enable_n;
assign pon	    	    = ~non;

endmodule
module io_interp_pdn (
input          pdn,           		// power down active low
input    [7:0] phy_clk_phs,             // 8 phase 1.6GHz local clock
output   [7:0] phy_clk_phs_gated       // gated 8 phase 1.6GHz local clock
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter  INV_DELAY      = 15;  // 15ps

assign #(2 * INV_DELAY) phy_clk_phs_gated[3:0] = phy_clk_phs[3:0] & {4{pdn}};
assign #(2 * INV_DELAY) phy_clk_phs_gated[7:4] = phy_clk_phs[7:4] | {4{~pdn}};

endmodule
module io_min_output (
input    [1:0] interp_clk_x,     // clock generated from min_ip16phs
input          test_enable_n,    // Active low test enable
input          pon,              // cross coupling enable p finger
input          non,              // cross coupling enable n finger
input          enable,           // latch enable
input          svcc,             // soft tie vcc
output   [1:0] int_clk_out       // 
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

wire  [1:0]  interp_clk;

//=================================================================================================================================================================================
// 
//=================================================================================================================================================================================

assign interp_clk = interp_clk_x[1:0];

an_io_double_edge_ff xdouble_edge_ff (
.clk_in     	( interp_clk[1:0]	),
.test_enable_n  ( test_enable_n   	),
.reset_n    	( enable         	),
.data_in    	( 2'b01          	),  // pass through
.data_out   	( int_clk_out[1:0]   	)
);

endmodule
module io_cmos_nand_x128_decode (
input   [6:0]   gray,
output  [127:0]  bk
);

wire [5:0]  b_gray;

assign b_gray[5] = ~gray[5] & gray[6];
assign b_gray[4:0] = gray[4:0] & {5{gray[6]}};

io_cmos_nand_x64_decode xdec_0 (
.gray	    ( gray[6:0]		),
.bk	    ( bk[63:0]		)
);

io_cmos_nand_x64_decode xdec_1 (
.gray	    ( {1'b0, b_gray[5:0]}	),
.bk	    ( bk[127:64]		)
);

endmodule
module io_delay_line_dcc (
input            c_in_p,
input            c_in_n,
input      [3:0] r_gray,
input      [3:0] f_gray,
output           c_out_p,
output           c_out_n 
);

`ifdef TIMESCALE_EN
                timeunit 1ps;
                timeprecision 1ps;
`endif

parameter STEP_DELAY = 40;

reg c_in_del;

wire  [15:0] c_in_p_f;
wire  [15:0] c_in_p_r;

assign #63  c_in_p_f[0] = c_in_p;
assign #67  c_in_p_f[1] = c_in_p;
assign #71  c_in_p_f[2] = c_in_p;
assign #75  c_in_p_f[3] = c_in_p;
assign #79  c_in_p_f[4] = c_in_p;
assign #83  c_in_p_f[5] = c_in_p;
assign #87  c_in_p_f[6] = c_in_p;
assign #91  c_in_p_f[7] = c_in_p;
assign #95  c_in_p_f[8] = c_in_p;
assign #99  c_in_p_f[9] = c_in_p;
assign #103  c_in_p_f[10] = c_in_p;
assign #107  c_in_p_f[11] = c_in_p;
assign #111  c_in_p_f[12] = c_in_p;
assign #115  c_in_p_f[13] = c_in_p;
assign #119  c_in_p_f[14] = c_in_p;
assign #123  c_in_p_f[15] = c_in_p;

assign #63  c_in_p_r[0] = c_in_p;
assign #67  c_in_p_r[1] = c_in_p;
assign #71  c_in_p_r[2] = c_in_p;
assign #75  c_in_p_r[3] = c_in_p;
assign #79  c_in_p_r[4] = c_in_p;
assign #83  c_in_p_r[5] = c_in_p;
assign #87  c_in_p_r[6] = c_in_p;
assign #91  c_in_p_r[7] = c_in_p;
assign #95  c_in_p_r[8] = c_in_p;
assign #99  c_in_p_r[9] = c_in_p;
assign #103  c_in_p_r[10] = c_in_p;
assign #107  c_in_p_r[11] = c_in_p;
assign #111  c_in_p_r[12] = c_in_p;
assign #115  c_in_p_r[13] = c_in_p;
assign #119  c_in_p_r[14] = c_in_p;
assign #123  c_in_p_r[15] = c_in_p;

always @(*)
  if (c_in_p == 1'b0)
    begin
      case (f_gray[3:0])
       4'b0000 : c_in_del =  c_in_p_f[0];
       4'b0001 : c_in_del =  c_in_p_f[1];
       4'b0011 : c_in_del =  c_in_p_f[2];
       4'b0010 : c_in_del =  c_in_p_f[3];
       4'b0110 : c_in_del =  c_in_p_f[4];
       4'b0111 : c_in_del =  c_in_p_f[5];
       4'b0101 : c_in_del =  c_in_p_f[6];
       4'b0100 : c_in_del =  c_in_p_f[7];
       4'b1100 : c_in_del =  c_in_p_f[8];
       4'b1101 : c_in_del =  c_in_p_f[9];
       4'b1111 : c_in_del =  c_in_p_f[10];
       4'b1110 : c_in_del =  c_in_p_f[11];
       4'b1010 : c_in_del =  c_in_p_f[12];
       4'b1011 : c_in_del =  c_in_p_f[13];
       4'b1001 : c_in_del =  c_in_p_f[14];
       4'b1000 : c_in_del =  c_in_p_f[15];
       default : c_in_del =  c_in_p_f[0];
       endcase
    end
  else if (c_in_p == 1'b1)
    begin
      case (r_gray[3:0])
       4'b0000 : c_in_del =   c_in_p_r[0];
       4'b0001 : c_in_del =   c_in_p_r[1];
       4'b0011 : c_in_del =   c_in_p_r[2];
       4'b0010 : c_in_del =   c_in_p_r[3];
       4'b0110 : c_in_del =   c_in_p_r[4];
       4'b0111 : c_in_del =   c_in_p_r[5];
       4'b0101 : c_in_del =   c_in_p_r[6];
       4'b0100 : c_in_del =   c_in_p_r[7];
       4'b1100 : c_in_del =   c_in_p_r[8];
       4'b1101 : c_in_del =   c_in_p_r[9];
       4'b1111 : c_in_del =   c_in_p_r[10];
       4'b1110 : c_in_del =   c_in_p_r[11];
       4'b1010 : c_in_del =   c_in_p_r[12];
       4'b1011 : c_in_del =   c_in_p_r[13];
       4'b1001 : c_in_del =   c_in_p_r[14];
       4'b1000 : c_in_del =   c_in_p_r[15];
       default : c_in_del =   c_in_p_r[0];
       endcase
    end

assign c_out_p =  c_in_del;
assign c_out_n = ~c_in_del;

endmodule
module io_dll_phdet (
   input  wire         i_del_p,            // phase detector input, from delay chain output
   input  wire         i_del_n,            // phase detector complementary input, from delay chain output
   input  wire         phase_clk,          // clock for phase detector
   input  wire         phase_clkb,         // complementary clock for phase detector
   input  wire         dll_reset_n,
   output wire         t_up,               // output of phase detector
   output wire         t_down              // output of phase detector
);

`ifdef TIMESCALE_EN
  timeunit 1ps;
  timeprecision 1ps;
`endif

/*
always @(posedge phase_clk or negedge dll_reset_n)
  if (~dll_reset_n)                         {t_up,t_down} <= #FF_DELAY 2'b00;
  else if ({i_del_p,i_del_n} == 2'b10)  {t_up,t_down} <= #FF_DELAY 2'b10;
  else if ({i_del_p,i_del_n} == 2'b01)  {t_up,t_down} <= #FF_DELAY 2'b01;
  else                                  {t_up,t_down} <= #FF_DELAY 2'b00;
*/

an_io_phdet_ff_ln xsampling_up (
      .dp(i_del_p),
      .dn(i_del_n),
      .clk_p(phase_clk),
      .rst_n(dll_reset_n),
      .q(t_up)
);

an_io_phdet_ff_ln xsampling_dn (
      .dp(phase_clkb),
      .dn(phase_clk),
      .clk_p(i_del_n),
      .rst_n(dll_reset_n),
      .q(t_down)
);

endmodule // io_dll_phdet
module io_clk_wkup (
input          enb,           		// 
output         drain_out                //
);

assign drain_out = enb ? 1'bz : 1'b1;

endmodule
module io_dly_interpolator (
input         nfrzdrv,
input         fout_p,
input         fout_n,
input   [2:0] gray,
output        out_p,
output        out_n,
output        osc_out_p,
output        osc_out_n
);

`ifdef TIMESCALE_EN
		timeunit 1ps; 
		timeprecision 1ps; 
`endif

parameter   NAND_DELAY = 20;

wire         a_in_p;
wire         b_in_p;
wire         c_in_p;
wire         a_in_n;
wire         b_in_n;
wire         c_in_n;
wire         out_pb;
wire         out_nb;
wire         x_p;
wire         x_n;
wire         x_pb;
wire         x_nb;
wire  [6:0]  sn;
reg   [6:0]  sp;

io_dly_interpclk xio_dly_interpclk (
.nfrzdrv	(nfrzdrv	),
.fout_p		(fout_p		),
.fout_n		(fout_n		),
.a_in_p		(a_in_p		),
.b_in_p		(b_in_p		),
.c_in_p		(c_in_p		),
.a_in_n		(a_in_n		),
.b_in_n		(b_in_n		),
.c_in_n		(c_in_n		)
);

always @(*)
  case (gray[2:0])
    3'b000 :  sp[6:0] = 7'b000_0000;
    3'b001 :  sp[6:0] = 7'b000_0001;
    3'b011 :  sp[6:0] = 7'b000_0011;
    3'b010 :  sp[6:0] = 7'b000_0111;
    3'b110 :  sp[6:0] = 7'b000_1111;
    3'b111 :  sp[6:0] = 7'b001_1111;
    3'b101 :  sp[6:0] = 7'b011_1111;
    3'b100 :  sp[6:0] = 7'b111_1111;
  endcase

assign sn[6:0] = ~sp[6:0];

io_ip8phs_3in xio_ip8phs_3in_n (
.a_in     ( a_in_n 		   ),
.b_in     ( b_in_n		   ),
.c_in     ( c_in_n		   ),
.svcc     ( 1'b1		   ),
.sp       ( sp[6:0]                ),
.sn       ( sn[6:0]                ),
.clk_outb ( out_nb                 )
);

io_ip8phs_3in xio_ip8phs_3in_p (
.a_in     ( a_in_p 		   ),
.b_in     ( b_in_p		   ),
.c_in     ( c_in_p		   ),
.svcc     ( 1'b1		   ),
.sp       ( sp[6:0]                ),
.sn       ( sn[6:0]                ),
.clk_outb ( out_pb                 )
);

assign x_p = ~out_pb;
assign x_n = ~out_nb;
//cross couple
assign x_pb = ~x_p;
assign x_nb = ~x_n;
assign out_p = ~x_pb;
assign out_n = ~x_nb;
assign osc_out_p = ~x_pb;
assign osc_out_n = ~x_nb;

/*
`ifdef LEC
assign x_p = ~x_n;
assign x_n = ~x_p;
`endif
*/

endmodule