dakies/OSS_Verilog huggingface dataset:
module
    compareRecFN#(parameter expWidth = 3, parameter sigWidth = 3) (
        input [(expWidth + sigWidth):0] a,
        input [(expWidth + sigWidth):0] b,
        input signaling,
        output lt,
        output eq,
        output gt,
        output unordered,
        output [4:0] exceptionFlags
    );

    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
    wire isNaNA, isInfA, isZeroA, signA;
    wire signed [(expWidth + 1):0] sExpA;
    wire [sigWidth:0] sigA;
    recFNToRawFN#(expWidth, sigWidth)
        recFNToRawFN_a(a, isNaNA, isInfA, isZeroA, signA, sExpA, sigA);
    wire isSigNaNA;
    isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_a(a, isSigNaNA);
    wire isNaNB, isInfB, isZeroB, signB;
    wire signed [(expWidth + 1):0] sExpB;
    wire [sigWidth:0] sigB;
    recFNToRawFN#(expWidth, sigWidth)
        recFNToRawFN_b(b, isNaNB, isInfB, isZeroB, signB, sExpB, sigB);
    wire isSigNaNB;
    isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_b(b, isSigNaNB);
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
    wire ordered = !isNaNA && !isNaNB;
    wire bothInfs  = isInfA  && isInfB;
    wire bothZeros = isZeroA && isZeroB;
    wire eqExps = (sExpA == sExpB);
    wire common_ltMags = (sExpA < sExpB) || (eqExps && (sigA < sigB));
    wire common_eqMags = eqExps && (sigA == sigB);
    wire ordered_lt =
        !bothZeros
            && ((signA && !signB)
                    || (!bothInfs
                            && ((signA && !common_ltMags && !common_eqMags)
                                    || (!signB && common_ltMags))));
    wire ordered_eq =
        bothZeros || ((signA == signB) && (bothInfs || common_eqMags));
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
    wire invalid = isSigNaNA || isSigNaNB || (signaling && !ordered);
    assign lt = ordered && ordered_lt;
    assign eq = ordered && ordered_eq;
    assign gt = ordered && !ordered_lt && !ordered_eq;
    assign unordered = !ordered;
    assign exceptionFlags = {invalid, 4'b0};

endmodule
module
    recFNToRecFN#(
        parameter inExpWidth = 3,
        parameter inSigWidth = 3,
        parameter outExpWidth = 3,
        parameter outSigWidth = 3
    ) (
        input [(`floatControlWidth - 1):0] control,
        input [(inExpWidth + inSigWidth):0] in,
        input [2:0] roundingMode,
        output [(outExpWidth + outSigWidth):0] out,
        output [4:0] exceptionFlags
    );

    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
    wire isNaN, isInf, isZero, sign;
    wire signed [(inExpWidth + 1):0] sExpIn;
    wire [inSigWidth:0] sigIn;
    recFNToRawFN#(inExpWidth, inSigWidth)
        inToRawIn(in, isNaN, isInf, isZero, sign, sExpIn, sigIn);
    wire isSigNaN;
    isSigNaNRecFN#(inExpWidth, inSigWidth) isSigNaNIn(in, isSigNaN);
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
    generate
        if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) begin
            /*----------------------------------------------------------------
            *----------------------------------------------------------------*/
            wire [(outExpWidth + outSigWidth):0] tentativeOut =
                in<<(outSigWidth - inSigWidth);
`ifdef HardFloat_propagateNaNPayloads
            assign out = tentativeOut | isNaN<<(outSigWidth - 2);
`else
            assign out =
                isNaN
                    ? {`HardFloat_signDefaultNaN, 3'b111}
                          <<(outExpWidth + outSigWidth - 3)
                          | `HardFloat_fractDefaultNaN(outSigWidth)
                    : tentativeOut;
`endif
            assign exceptionFlags = {isSigNaN, 4'b0000};
        end else begin
            /*----------------------------------------------------------------
            *----------------------------------------------------------------*/
            roundAnyRawFNToRecFN#(
                inExpWidth,
                inSigWidth,
                outExpWidth,
                outSigWidth,
                `flRoundOpt_sigMSBitAlwaysZero
            ) roundRawInToOut(
                    control,
                    isSigNaN,
                    1'b0,
                    isNaN,
                    isInf,
                    isZero,
                    sign,
                    sExpIn,
                    sigIn,
                    roundingMode,
                    out,
                    exceptionFlags
                );
        end
    endgenerate

endmodule
module test_mulRecF16;

    test_mulRecFN#(5, 11) test_mulRecF16();

endmodule
module test_mulRecF32;

    test_mulRecFN#(8, 24) test_mulRecF32();

endmodule
module test_mulRecF64;

    test_mulRecFN#(11, 53) test_mulRecF64();

endmodule
module test_mulRecF128;

    test_mulRecFN#(15, 113) test_mulRecF128();

endmodule
module
    compareRecF16 (
        input [16:0] a,
        input [16:0] b,
        input signaling,
        output lt,
        output eq,
        output gt,
        output unordered,
        output [4:0] exceptionFlags
    );

    compareRecFN#(5, 11)
        compareRecFN(a, b, signaling, lt, eq, gt, unordered, exceptionFlags);

endmodule
module
    compareRecF32 (
        input [32:0] a,
        input [32:0] b,
        input signaling,
        output lt,
        output eq,
        output gt,
        output unordered,
        output [4:0] exceptionFlags
    );

    compareRecFN#(8, 24)
        compareRecFN(a, b, signaling, lt, eq, gt, unordered, exceptionFlags);

endmodule
module
    compareRecF64 (
        input [64:0] a,
        input [64:0] b,
        input signaling,
        output lt,
        output eq,
        output gt,
        output unordered,
        output [4:0] exceptionFlags
    );

    compareRecFN#(11, 53)
        compareRecFN(a, b, signaling, lt, eq, gt, unordered, exceptionFlags);

endmodule
module
    compareRecF128 (
        input [128:0] a,
        input [128:0] b,
        input signaling,
        output lt,
        output eq,
        output gt,
        output unordered,
        output [4:0] exceptionFlags
    );

    compareRecFN#(15, 113)
        compareRecFN(a, b, signaling, lt, eq, gt, unordered, exceptionFlags);

endmodule
module test_recF16ToF16;

    test_recFNToFN#(5, 11) test_recF16ToF16();

endmodule
module test_recF32ToF32;

    test_recFNToFN#(8, 24) test_recF32ToF32();

endmodule
module test_recF64ToF64;

    test_recFNToFN#(11, 53) test_recF64ToF64();

endmodule
module test_recF128ToF128;

    test_recFNToFN#(15, 113) test_recF128ToF128();

endmodule
module test_mulAddRecF16_add;

    test_mulAddRecFN_add#(5, 11) test_mulAddRecF16_add();

endmodule
module test_mulAddRecF32_add;

    test_mulAddRecFN_add#(8, 24) test_mulAddRecF32_add();

endmodule
module test_mulAddRecF64_add;

    test_mulAddRecFN_add#(11, 53) test_mulAddRecF64_add();

endmodule
module test_mulAddRecF128_add;

    test_mulAddRecFN_add#(15, 113) test_mulAddRecF128_add();

endmodule
module
    divSqrtRecF16_small_div (
        input nReset,
        input clock,
        input [(`floatControlWidth - 1):0] control,
        output inReady,
        input inValid,
        input [16:0] a,
        input [16:0] b,
        input [2:0] roundingMode,
        output outValid,
        output [16:0] out,
        output [4:0] exceptionFlags
    );

    wire sqrtOpOut;
    divSqrtRecFN_small#(5, 11, 0)
        divSqrtRecFN(
            nReset,
            clock,
            control,
            inReady,
            inValid,
            1'b0,
            a,
            b,
            roundingMode,
            outValid,
            sqrtOpOut,
            out,
            exceptionFlags
        );

endmodule
module
    divSqrtRecF32_small_div (
        input nReset,
        input clock,
        input [(`floatControlWidth - 1):0] control,
        output inReady,
        input inValid,
        input [32:0] a,
        input [32:0] b,
        input [2:0] roundingMode,
        output outValid,
        output [32:0] out,
        output [4:0] exceptionFlags
    );

    wire sqrtOpOut;
    divSqrtRecFN_small#(8, 24, 0)
        divSqrtRecFN(
            nReset,
            clock,
            control,
            inReady,
            inValid,
            1'b0,
            a,
            b,
            roundingMode,
            outValid,
            sqrtOpOut,
            out,
            exceptionFlags
        );

endmodule
module
    divSqrtRecF64_small_div (
        input nReset,
        input clock,
        input [(`floatControlWidth - 1):0] control,
        output inReady,
        input inValid,
        input [64:0] a,
        input [64:0] b,
        input [2:0] roundingMode,
        output outValid,
        output [64:0] out,
        output [4:0] exceptionFlags
    );

    wire sqrtOpOut;
    divSqrtRecFN_small#(11, 53, 0)
        divSqrtRecFN(
            nReset,
            clock,
            control,
            inReady,
            inValid,
            1'b0,
            a,
            b,
            roundingMode,
            outValid,
            sqrtOpOut,
            out,
            exceptionFlags
        );

endmodule
module
    divSqrtRecF128_small_div (
        input nReset,
        input clock,
        input [(`floatControlWidth - 1):0] control,
        output inReady,
        input inValid,
        input [128:0] a,
        input [128:0] b,
        input [2:0] roundingMode,
        output outValid,
        output [128:0] out,
        output [4:0] exceptionFlags
    );

    wire sqrtOpOut;
    divSqrtRecFN_small#(15, 113, 0)
        divSqrtRecFN(
            nReset,
            clock,
            control,
            inReady,
            inValid,
            1'b0,
            a,
            b,
            roundingMode,
            outValid,
            sqrtOpOut,
            out,
            exceptionFlags
        );

endmodule
module
    divSqrtRecF16_small_sqrt (
        input nReset,
        input clock,
        input [(`floatControlWidth - 1):0] control,
        output inReady,
        input inValid,
        input [16:0] a,
        input [2:0] roundingMode,
        output outValid,
        output [16:0] out,
        output [4:0] exceptionFlags
    );

    wire sqrtOpOut;
    divSqrtRecFN_small#(5, 11, 0)
        divSqrtRecFN(
            nReset,
            clock,
            control,
            inReady,
            inValid,
            1'b1,
            a,
            17'b0,
            roundingMode,
            outValid,
            sqrtOpOut,
            out,
            exceptionFlags
        );

endmodule
module
    divSqrtRecF32_small_sqrt (
        input nReset,
        input clock,
        input [(`floatControlWidth - 1):0] control,
        output inReady,
        input inValid,
        input [32:0] a,
        input [2:0] roundingMode,
        output outValid,
        output [32:0] out,
        output [4:0] exceptionFlags
    );

    wire sqrtOpOut;
    divSqrtRecFN_small#(8, 24, 0)
        divSqrtRecFN(
            nReset,
            clock,
            control,
            inReady,
            inValid,
            1'b1,
            a,
            33'b0,
            roundingMode,
            outValid,
            sqrtOpOut,
            out,
            exceptionFlags
        );

endmodule
module
    divSqrtRecF64_small_sqrt (
        input nReset,
        input clock,
        input [(`floatControlWidth - 1):0] control,
        output inReady,
        input inValid,
        input [64:0] a,
        input [2:0] roundingMode,
        output outValid,
        output [64:0] out,
        output [4:0] exceptionFlags
    );

    wire sqrtOpOut;
    divSqrtRecFN_small#(11, 53, 0)
        divSqrtRecFN(
            nReset,
            clock,
            control,
            inReady,
            inValid,
            1'b1,
            a,
            65'b0,
            roundingMode,
            outValid,
            sqrtOpOut,
            out,
            exceptionFlags
        );

endmodule
module
    divSqrtRecF128_small_sqrt (
        input nReset,
        input clock,
        input [(`floatControlWidth - 1):0] control,
        output inReady,
        input inValid,
        input [128:0] a,
        input [2:0] roundingMode,
        output outValid,
        output [128:0] out,
        output [4:0] exceptionFlags
    );

    wire sqrtOpOut;
    divSqrtRecFN_small#(15, 113, 0)
        divSqrtRecFN(
            nReset,
            clock,
            control,
            inReady,
            inValid,
            1'b1,
            a,
            129'b0,
            roundingMode,
            outValid,
            sqrtOpOut,
            out,
            exceptionFlags
        );

endmodule
module
    ui32ToRecF16 (
        input [(`floatControlWidth - 1):0] control,
        input [31:0] in,
        input [2:0] roundingMode,
        output [16:0] out,
        output [4:0] exceptionFlags
    );

    iNToRecFN#(32, 5, 11)
        iNToRecFN(control, 0, in, roundingMode, out, exceptionFlags);

endmodule
module
    ui32ToRecF32 (
        input [(`floatControlWidth - 1):0] control,
        input [31:0] in,
        input [2:0] roundingMode,
        output [32:0] out,
        output [4:0] exceptionFlags
    );

    iNToRecFN#(32, 8, 24)
        iNToRecFN(control, 0, in, roundingMode, out, exceptionFlags);

endmodule
module
    ui32ToRecF64 (
        input [(`floatControlWidth - 1):0] control,
        input [31:0] in,
        input [2:0] roundingMode,
        output [64:0] out,
        output [4:0] exceptionFlags
    );

    iNToRecFN#(32, 11, 53)
        iNToRecFN(control, 0, in, roundingMode, out, exceptionFlags);

endmodule
module
    ui32ToRecF128 (
        input [(`floatControlWidth - 1):0] control,
        input [31:0] in,
        input [2:0] roundingMode,
        output [128:0] out,
        output [4:0] exceptionFlags
    );

    iNToRecFN#(32, 15, 113)
        iNToRecFN(control, 0, in, roundingMode, out, exceptionFlags);

endmodule
module
    ui64ToRecF16 (
        input [(`floatControlWidth - 1):0] control,
        input [63:0] in,
        input [2:0] roundingMode,
        output [16:0] out,
        output [4:0] exceptionFlags
    );

    iNToRecFN#(64, 5, 11)
        iNToRecFN(control, 0, in, roundingMode, out, exceptionFlags);

endmodule
module
    ui64ToRecF32 (
        input [(`floatControlWidth - 1):0] control,
        input [63:0] in,
        input [2:0] roundingMode,
        output [32:0] out,
        output [4:0] exceptionFlags
    );

    iNToRecFN#(64, 8, 24)
        iNToRecFN(control, 0, in, roundingMode, out, exceptionFlags);

endmodule
module
    ui64ToRecF64 (
        input [(`floatControlWidth - 1):0] control,
        input [63:0] in,
        input [2:0] roundingMode,
        output [64:0] out,
        output [4:0] exceptionFlags
    );

    iNToRecFN#(64, 11, 53)
        iNToRecFN(control, 0, in, roundingMode, out, exceptionFlags);

endmodule
module
    ui64ToRecF128 (
        input [(`floatControlWidth - 1):0] control,
        input [63:0] in,
        input [2:0] roundingMode,
        output [128:0] out,
        output [4:0] exceptionFlags
    );

    iNToRecFN#(64, 15, 113)
        iNToRecFN(control, 0, in, roundingMode, out, exceptionFlags);

endmodule
module
    i32ToRecF16 (
        input [(`floatControlWidth - 1):0] control,
        input [31:0] in,
        input [2:0] roundingMode,
        output [16:0] out,
        output [4:0] exceptionFlags
    );

    iNToRecFN#(32, 5, 11)
        iNToRecFN(control, 1, in, roundingMode, out, exceptionFlags);

endmodule
module
    i32ToRecF32 (
        input [(`floatControlWidth - 1):0] control,
        input [31:0] in,
        input [2:0] roundingMode,
        output [32:0] out,
        output [4:0] exceptionFlags
    );

    iNToRecFN#(32, 8, 24)
        iNToRecFN(control, 1, in, roundingMode, out, exceptionFlags);

endmodule
module
    i32ToRecF64 (
        input [(`floatControlWidth - 1):0] control,
        input [31:0] in,
        input [2:0] roundingMode,
        output [64:0] out,
        output [4:0] exceptionFlags
    );

    iNToRecFN#(32, 11, 53)
        iNToRecFN(control, 1, in, roundingMode, out, exceptionFlags);

endmodule
module
    i32ToRecF128 (
        input [(`floatControlWidth - 1):0] control,
        input [31:0] in,
        input [2:0] roundingMode,
        output [128:0] out,
        output [4:0] exceptionFlags
    );

    iNToRecFN#(32, 15, 113)
        iNToRecFN(control, 1, in, roundingMode, out, exceptionFlags);

endmodule
module
    i64ToRecF16 (
        input [(`floatControlWidth - 1):0] control,
        input [63:0] in,
        input [2:0] roundingMode,
        output [16:0] out,
        output [4:0] exceptionFlags
    );

    iNToRecFN#(64, 5, 11)
        iNToRecFN(control, 1, in, roundingMode, out, exceptionFlags);

endmodule
module
    i64ToRecF32 (
        input [(`floatControlWidth - 1):0] control,
        input [63:0] in,
        input [2:0] roundingMode,
        output [32:0] out,
        output [4:0] exceptionFlags
    );

    iNToRecFN#(64, 8, 24)
        iNToRecFN(control, 1, in, roundingMode, out, exceptionFlags);

endmodule
module
    i64ToRecF64 (
        input [(`floatControlWidth - 1):0] control,
        input [63:0] in,
        input [2:0] roundingMode,
        output [64:0] out,
        output [4:0] exceptionFlags
    );

    iNToRecFN#(64, 11, 53)
        iNToRecFN(control, 1, in, roundingMode, out, exceptionFlags);

endmodule
module
    i64ToRecF128 (
        input [(`floatControlWidth - 1):0] control,
        input [63:0] in,
        input [2:0] roundingMode,
        output [128:0] out,
        output [4:0] exceptionFlags
    );

    iNToRecFN#(64, 15, 113)
        iNToRecFN(control, 1, in, roundingMode, out, exceptionFlags);

endmodule
module test_addRecF16_add;

    test_addRecFN_add#(5, 11) test_addRecF16_add();

endmodule
module test_addRecF32_add;

    test_addRecFN_add#(8, 24) test_addRecF32_add();

endmodule
module test_addRecF64_add;

    test_addRecFN_add#(11, 53) test_addRecF64_add();

endmodule
module test_addRecF128_add;

    test_addRecFN_add#(15, 113) test_addRecF128_add();

endmodule
module
    recF16ToUi32 (
        input [(`floatControlWidth - 1):0] control,
        input [16:0] in,
        input [2:0] roundingMode,
        output [31:0] out,
        output [2:0] exceptionFlags
    );

    recFNToIN#(5, 11, 32)
        recFNToIN(control, in, roundingMode, 0, out, exceptionFlags);

endmodule
module
    recF16ToUi64 (
        input [(`floatControlWidth - 1):0] control,
        input [16:0] in,
        input [2:0] roundingMode,
        output [63:0] out,
        output [2:0] exceptionFlags
    );

    recFNToIN#(5, 11, 64)
        recFNToIN(control, in, roundingMode, 0, out, exceptionFlags);

endmodule
module
    recF16ToI32 (
        input [(`floatControlWidth - 1):0] control,
        input [16:0] in,
        input [2:0] roundingMode,
        output [31:0] out,
        output [2:0] exceptionFlags
    );

    recFNToIN#(5, 11, 32)
        recFNToIN(control, in, roundingMode, 1, out, exceptionFlags);

endmodule
module
    recF16ToI64 (
        input [(`floatControlWidth - 1):0] control,
        input [16:0] in,
        input [2:0] roundingMode,
        output [63:0] out,
        output [2:0] exceptionFlags
    );

    recFNToIN#(5, 11, 64)
        recFNToIN(control, in, roundingMode, 1, out, exceptionFlags);

endmodule
module
    recF32ToUi32 (
        input [(`floatControlWidth - 1):0] control,
        input [32:0] in,
        input [2:0] roundingMode,
        output [31:0] out,
        output [2:0] exceptionFlags
    );

    recFNToIN#(8, 24, 32)
        recFNToIN(control, in, roundingMode, 0, out, exceptionFlags);

endmodule
module
    recF32ToUi64 (
        input [(`floatControlWidth - 1):0] control,
        input [32:0] in,
        input [2:0] roundingMode,
        output [63:0] out,
        output [2:0] exceptionFlags
    );

    recFNToIN#(8, 24, 64)
        recFNToIN(control, in, roundingMode, 0, out, exceptionFlags);

endmodule
module
    recF32ToI32 (
        input [(`floatControlWidth - 1):0] control,
        input [32:0] in,
        input [2:0] roundingMode,
        output [31:0] out,
        output [2:0] exceptionFlags
    );

    recFNToIN#(8, 24, 32)
        recFNToIN(control, in, roundingMode, 1, out, exceptionFlags);

endmodule
module
    recF32ToI64 (
        input [(`floatControlWidth - 1):0] control,
        input [32:0] in,
        input [2:0] roundingMode,
        output [63:0] out,
        output [2:0] exceptionFlags
    );

    recFNToIN#(8, 24, 64)
        recFNToIN(control, in, roundingMode, 1, out, exceptionFlags);

endmodule
module
    recF64ToUi32 (
        input [(`floatControlWidth - 1):0] control,
        input [64:0] in,
        input [2:0] roundingMode,
        output [31:0] out,
        output [2:0] exceptionFlags
    );

    recFNToIN#(11, 53, 32)
        recFNToIN(control, in, roundingMode, 0, out, exceptionFlags);

endmodule
module
    recF64ToUi64 (
        input [(`floatControlWidth - 1):0] control,
        input [64:0] in,
        input [2:0] roundingMode,
        output [63:0] out,
        output [2:0] exceptionFlags
    );

    recFNToIN#(11, 53, 64)
        recFNToIN(control, in, roundingMode, 0, out, exceptionFlags);

endmodule
module
    recF64ToI32 (
        input [(`floatControlWidth - 1):0] control,
        input [64:0] in,
        input [2:0] roundingMode,
        output [31:0] out,
        output [2:0] exceptionFlags
    );

    recFNToIN#(11, 53, 32)
        recFNToIN(control, in, roundingMode, 1, out, exceptionFlags);

endmodule
module
    recF64ToI64 (
        input [(`floatControlWidth - 1):0] control,
        input [64:0] in,
        input [2:0] roundingMode,
        output [63:0] out,
        output [2:0] exceptionFlags
    );

    recFNToIN#(11, 53, 64)
        recFNToIN(control, in, roundingMode, 1, out, exceptionFlags);

endmodule
module
    recF128ToUi32 (
        input [(`floatControlWidth - 1):0] control,
        input [128:0] in,
        input [2:0] roundingMode,
        output [31:0] out,
        output [2:0] exceptionFlags
    );

    recFNToIN#(15, 113, 32)
        recFNToIN(control, in, roundingMode, 0, out, exceptionFlags);

endmodule
module
    recF128ToUi64 (
        input [(`floatControlWidth - 1):0] control,
        input [128:0] in,
        input [2:0] roundingMode,
        output [63:0] out,
        output [2:0] exceptionFlags
    );

    recFNToIN#(15, 113, 64)
        recFNToIN(control, in, roundingMode, 0, out, exceptionFlags);

endmodule
module
    recF128ToI32 (
        input [(`floatControlWidth - 1):0] control,
        input [128:0] in,
        input [2:0] roundingMode,
        output [31:0] out,
        output [2:0] exceptionFlags
    );

    recFNToIN#(15, 113, 32)
        recFNToIN(control, in, roundingMode, 1, out, exceptionFlags);

endmodule
module
    recF128ToI64 (
        input [(`floatControlWidth - 1):0] control,
        input [128:0] in,
        input [2:0] roundingMode,
        output [63:0] out,
        output [2:0] exceptionFlags
    );

    recFNToIN#(15, 113, 64)
        recFNToIN(control, in, roundingMode, 1, out, exceptionFlags);

endmodule
module test_recF16ToI32;

    test_recFNToIN#(5, 11, 32) test_recF16ToI32();

endmodule
module test_recF32ToI32;

    test_recFNToIN#(8, 24, 32) test_recF32ToI32();

endmodule
module test_recF64ToI32;

    test_recFNToIN#(11, 53, 32) test_recF64ToI32();

endmodule
module test_recF128ToI32;

    test_recFNToIN#(15, 113, 32) test_recF128ToI32();

endmodule
module test_recF16ToI64;

    test_recFNToIN#(5, 11, 64) test_recF16ToI64();

endmodule
module test_recF32ToI64;

    test_recFNToIN#(8, 24, 64) test_recF32ToI64();

endmodule
module test_recF64ToI64;

    test_recFNToIN#(11, 53, 64) test_recF64ToI64();

endmodule
module test_recF128ToI64;

    test_recFNToIN#(15, 113, 64) test_recF128ToI64();

endmodule
module
    sameRecFN#(parameter expWidth = 3, parameter sigWidth = 3) (
        input [(expWidth + sigWidth):0] a,
        input [(expWidth + sigWidth):0] b,
        output out
    );

    wire [3:0] top4A = a[(expWidth + sigWidth):(expWidth + sigWidth - 3)];
    wire [3:0] top4B = b[(expWidth + sigWidth):(expWidth + sigWidth - 3)];
    assign out =
        (top4A[2:0] == 'b000) || (top4A[2:0] == 'b111)
            ? (top4A == top4B) && (a[(sigWidth - 2):0] == b[(sigWidth - 2):0])
            : (top4A[2:0] == 'b110) ? (top4A == top4B) : (a == b);

endmodule
module
    mulAddRecF16_add (
        input [(`floatControlWidth - 1):0] control,
        input [16:0] a,
        input [16:0] b,
        input [2:0] roundingMode,
        output [16:0] out,
        output [4:0] exceptionFlags
    );

    wire [16:0] recF16_1 = 'h08000;
    mulAddRecFN#(5, 11)
        mulAddRecFN(
            control, 2'b0, a, recF16_1, b, roundingMode, out, exceptionFlags);

endmodule
module
    mulAddRecF32_add (
        input [(`floatControlWidth - 1):0] control,
        input [32:0] a,
        input [32:0] b,
        input [2:0] roundingMode,
        output [32:0] out,
        output [4:0] exceptionFlags
    );

    wire [32:0] recF32_1 = 33'h080000000;
    mulAddRecFN#(8, 24)
        mulAddRecFN(
            control, 2'b0, a, recF32_1, b, roundingMode, out, exceptionFlags);

endmodule
module
    mulAddRecF64_add (
        input [(`floatControlWidth - 1):0] control,
        input [64:0] a,
        input [64:0] b,
        input [2:0] roundingMode,
        output [64:0] out,
        output [4:0] exceptionFlags
    );

    wire [64:0] recF64_1 = 65'h08000000000000000;
    mulAddRecFN#(11, 53)
        mulAddRecFN(
            control, 2'b0, a, recF64_1, b, roundingMode, out, exceptionFlags);

endmodule
module
    mulAddRecF128_add (
        input [(`floatControlWidth - 1):0] control,
        input [128:0] a,
        input [128:0] b,
        input [2:0] roundingMode,
        output [128:0] out,
        output [4:0] exceptionFlags
    );

    wire [128:0] recF128_1 = 129'h080000000000000000000000000000000;
    mulAddRecFN#(15, 113)
        mulAddRecFN(
            control, 2'b0, a, recF128_1, b, roundingMode, out, exceptionFlags
        );

endmodule
module
    mulAddRecF16_mul (
        input [(`floatControlWidth - 1):0] control,
        input [16:0] a,
        input [16:0] b,
        input [2:0] roundingMode,
        output [16:0] out,
        output [4:0] exceptionFlags
    );

    wire [16:0] zeroAddend = {a[16] ^ b[16], 16'b0};
    mulAddRecFN#(5, 11)
        mulAddRecFN(
            control, 2'b0, a, b, zeroAddend, roundingMode, out, exceptionFlags
        );

endmodule
module
    mulAddRecF32_mul (
        input [(`floatControlWidth - 1):0] control,
        input [32:0] a,
        input [32:0] b,
        input [2:0] roundingMode,
        output [32:0] out,
        output [4:0] exceptionFlags
    );

    wire [32:0] zeroAddend = {a[32] ^ b[32], 32'b0};
    mulAddRecFN#(8, 24)
        mulAddRecFN(
            control, 2'b0, a, b, zeroAddend, roundingMode, out, exceptionFlags
        );

endmodule
module
    mulAddRecF64_mul (
        input [(`floatControlWidth - 1):0] control,
        input [64:0] a,
        input [64:0] b,
        input [2:0] roundingMode,
        output [64:0] out,
        output [4:0] exceptionFlags
    );

    wire [64:0] zeroAddend = {a[64] ^ b[64], 64'b0};
    mulAddRecFN#(11, 53)
        mulAddRecFN(
            control, 2'b0, a, b, zeroAddend, roundingMode, out, exceptionFlags
        );

endmodule
module
    mulAddRecF128_mul (
        input [(`floatControlWidth - 1):0] control,
        input [128:0] a,
        input [128:0] b,
        input [2:0] roundingMode,
        output [128:0] out,
        output [4:0] exceptionFlags
    );

    wire [128:0] zeroAddend = {a[128] ^ b[128], 128'b0};
    mulAddRecFN#(15, 113)
        mulAddRecFN(
            control, 2'b0, a, b, zeroAddend, roundingMode, out, exceptionFlags
        );

endmodule
module
    mulAddRecF16 (
        input [(`floatControlWidth - 1):0] control,
        input [1:0] op,
        input [16:0] a,
        input [16:0] b,
        input [16:0] c,
        input [2:0] roundingMode,
        output [16:0] out,
        output [4:0] exceptionFlags
    );

    mulAddRecFN#(5, 11)
        mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags);

endmodule
module
    mulAddRecF32 (
        input [(`floatControlWidth - 1):0] control,
        input [1:0] op,
        input [32:0] a,
        input [32:0] b,
        input [32:0] c,
        input [2:0] roundingMode,
        output [32:0] out,
        output [4:0] exceptionFlags
    );

    mulAddRecFN#(8, 24)
        mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags);

endmodule
module
    mulAddRecF64 (
        input [(`floatControlWidth - 1):0] control,
        input [1:0] op,
        input [64:0] a,
        input [64:0] b,
        input [64:0] c,
        input [2:0] roundingMode,
        output [64:0] out,
        output [4:0] exceptionFlags
    );

    mulAddRecFN#(11, 53)
        mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags);

endmodule
module
    mulAddRecF128 (
        input [(`floatControlWidth - 1):0] control,
        input [1:0] op,
        input [128:0] a,
        input [128:0] b,
        input [128:0] c,
        input [2:0] roundingMode,
        output [128:0] out,
        output [4:0] exceptionFlags
    );

    mulAddRecFN#(15, 113)
        mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags);

endmodule
module test_mulAddRecF16_mul;

    test_mulAddRecFN_mul#(5, 11) test_mulAddRecF16_mul();

endmodule
module test_mulAddRecF32_mul;

    test_mulAddRecFN_mul#(8, 24) test_mulAddRecF32_mul();

endmodule
module test_mulAddRecF64_mul;

    test_mulAddRecFN_mul#(11, 53) test_mulAddRecF64_mul();

endmodule
module test_mulAddRecF128_mul;

    test_mulAddRecFN_mul#(15, 113) test_mulAddRecF128_mul();

endmodule
module f16ToRecF16 (input [15:0] in, output [16:0] out);

    fNToRecFN#(5, 11) fNToRecFN(in, out);

endmodule
module f32ToRecF32 (input [31:0] in, output [32:0] out);

    fNToRecFN#(8, 24) fNToRecFN(in, out);

endmodule
module f64ToRecF64 (input [63:0] in, output [64:0] out);

    fNToRecFN#(11, 53) fNToRecFN(in, out);

endmodule
module f128ToRecF128 (input [127:0] in, output [128:0] out);

    fNToRecFN#(15, 113) fNToRecFN(in, out);

endmodule
module
    addRecF16_add (
        input [(`floatControlWidth - 1):0] control,
        input [16:0] a,
        input [16:0] b,
        input [2:0] roundingMode,
        output [16:0] out,
        output [4:0] exceptionFlags
    );

    addRecFN#(5, 11)
        addRecFN(control, 1'b0, a, b, roundingMode, out, exceptionFlags);

endmodule
module
    addRecF32_add (
        input [(`floatControlWidth - 1):0] control,
        input [32:0] a,
        input [32:0] b,
        input [2:0] roundingMode,
        output [32:0] out,
        output [4:0] exceptionFlags
    );

    addRecFN#(8, 24)
        addRecFN(control, 1'b0, a, b, roundingMode, out, exceptionFlags);

endmodule
module
    addRecF64_add (
        input [(`floatControlWidth - 1):0] control,
        input [64:0] a,
        input [64:0] b,
        input [2:0] roundingMode,
        output [64:0] out,
        output [4:0] exceptionFlags
    );

    addRecFN#(11, 53)
        addRecFN(control, 1'b0, a, b, roundingMode, out, exceptionFlags);

endmodule
module
    addRecF128_add (
        input [(`floatControlWidth - 1):0] control,
        input [128:0] a,
        input [128:0] b,
        input [2:0] roundingMode,
        output [128:0] out,
        output [4:0] exceptionFlags
    );

    addRecFN#(15, 113)
        addRecFN(control, 1'b0, a, b, roundingMode, out, exceptionFlags);

endmodule
module
    addRecF16_sub (
        input [(`floatControlWidth - 1):0] control,
        input [16:0] a,
        input [16:0] b,
        input [2:0] roundingMode,
        output [16:0] out,
        output [4:0] exceptionFlags
    );

    addRecFN#(5, 11)
        addRecFN(control, 1'b1, a, b, roundingMode, out, exceptionFlags);

endmodule
module
    addRecF32_sub (
        input [(`floatControlWidth - 1):0] control,
        input [32:0] a,
        input [32:0] b,
        input [2:0] roundingMode,
        output [32:0] out,
        output [4:0] exceptionFlags
    );

    addRecFN#(8, 24)
        addRecFN(control, 1'b1, a, b, roundingMode, out, exceptionFlags);

endmodule
module
    addRecF64_sub (
        input [(`floatControlWidth - 1):0] control,
        input [64:0] a,
        input [64:0] b,
        input [2:0] roundingMode,
        output [64:0] out,
        output [4:0] exceptionFlags
    );

    addRecFN#(11, 53)
        addRecFN(control, 1'b1, a, b, roundingMode, out, exceptionFlags);

endmodule
module
    addRecF128_sub (
        input [(`floatControlWidth - 1):0] control,
        input [128:0] a,
        input [128:0] b,
        input [2:0] roundingMode,
        output [128:0] out,
        output [4:0] exceptionFlags
    );

    addRecFN#(15, 113)
        addRecFN(control, 1'b1, a, b, roundingMode, out, exceptionFlags);

endmodule
module test_i32ToRecF16;

    test_iNToRecFN#(32, 5, 11) test_i32ToRecF16();

endmodule
module test_i32ToRecF32;

    test_iNToRecFN#(32, 8, 24) test_i32ToRecF32();

endmodule
module test_i32ToRecF64;

    test_iNToRecFN#(32, 11, 53) test_i32ToRecF64();

endmodule
module test_i32ToRecF128;

    test_iNToRecFN#(32, 15, 113) test_i32ToRecF128();

endmodule
module test_i64ToRecF16;

    test_iNToRecFN#(64, 5, 11) test_i64ToRecF16();

endmodule
module test_i64ToRecF32;

    test_iNToRecFN#(64, 8, 24) test_i64ToRecF32();

endmodule
module test_i64ToRecF64;

    test_iNToRecFN#(64, 11, 53) test_i64ToRecF64();

endmodule
module test_i64ToRecF128;

    test_iNToRecFN#(64, 15, 113) test_i64ToRecF128();

endmodule
module recF16ToF16 (input [16:0] in, output [15:0] out);

    recFNToFN#(5, 11) recFNToFN(in, out);

endmodule
module recF32ToF32 (input [32:0] in, output [31:0] out);

    recFNToFN#(8, 24) recFNToFN(in, out);

endmodule
module recF64ToF64 (input [64:0] in, output [63:0] out);

    recFNToFN#(11, 53) recFNToFN(in, out);

endmodule
module recF128ToF128 (input [128:0] in, output [127:0] out);

    recFNToFN#(15, 113) recFNToFN(in, out);

endmodule
module test_recF16ToRecF32;

    test_recFNToRecFN#(5, 11, 8, 24) test_recF16ToRecF32();

endmodule
module test_recF16ToRecF64;

    test_recFNToRecFN#(5, 11, 11, 53) test_recF16ToRecF64();

endmodule
module test_recF16ToRecF128;

    test_recFNToRecFN#(5, 11, 15, 113) test_recF16ToRecF128();

endmodule
module test_recF32ToRecF16;

    test_recFNToRecFN#(8, 24, 5, 11) test_recF32ToRecF16();

endmodule
module test_recF32ToRecF64;

    test_recFNToRecFN#(8, 24, 11, 53) test_recF32ToRecF64();

endmodule
module test_recF32ToRecF128;

    test_recFNToRecFN#(8, 24, 15, 113) test_recF32ToRecF128();

endmodule
module test_recF64ToRecF16;

    test_recFNToRecFN#(11, 53, 5, 11) test_recF64ToRecF16();

endmodule
module test_recF64ToRecF32;

    test_recFNToRecFN#(11, 53, 8, 24) test_recF64ToRecF32();

endmodule
module test_recF64ToRecF128;

    test_recFNToRecFN#(11, 53, 15, 113) test_recF64ToRecF128();

endmodule
module test_recF128ToRecF16;

    test_recFNToRecFN#(15, 113, 5, 11) test_recF128ToRecF16();

endmodule
module test_recF128ToRecF32;

    test_recFNToRecFN#(15, 113, 8, 24) test_recF128ToRecF32();

endmodule
module test_recF128ToRecF64;

    test_recFNToRecFN#(15, 113, 11, 53) test_recF128ToRecF64();

endmodule
module test_compareRecF16;

    test_compareRecFN#(5, 11) test_compareRecF16();

endmodule
module test_compareRecF32;

    test_compareRecFN#(8, 24) test_compareRecF32();

endmodule
module test_compareRecF64;

    test_compareRecFN#(11, 53) test_compareRecF64();

endmodule
module test_compareRecF128;

    test_compareRecFN#(15, 113) test_compareRecF128();

endmodule
module
    mulRecF16 (
        input [(`floatControlWidth - 1):0] control,
        input [16:0] a,
        input [16:0] b,
        input [2:0] roundingMode,
        output [16:0] out,
        output [4:0] exceptionFlags
    );

    mulRecFN#(5, 11)
        mulRecFN(control, a, b, roundingMode, out, exceptionFlags);

endmodule
module
    mulRecF32 (
        input [(`floatControlWidth - 1):0] control,
        input [32:0] a,
        input [32:0] b,
        input [2:0] roundingMode,
        output [32:0] out,
        output [4:0] exceptionFlags
    );

    mulRecFN#(8, 24)
        mulRecFN(control, a, b, roundingMode, out, exceptionFlags);

endmodule
module
    mulRecF64 (
        input [(`floatControlWidth - 1):0] control,
        input [64:0] a,
        input [64:0] b,
        input [2:0] roundingMode,
        output [64:0] out,
        output [4:0] exceptionFlags
    );

    mulRecFN#(11, 53)
        mulRecFN(control, a, b, roundingMode, out, exceptionFlags);

endmodule
module
    mulRecF128 (
        input [(`floatControlWidth - 1):0] control,
        input [128:0] a,
        input [128:0] b,
        input [2:0] roundingMode,
        output [128:0] out,
        output [4:0] exceptionFlags
    );

    mulRecFN#(15, 113)
        mulRecFN(control, a, b, roundingMode, out, exceptionFlags);

endmodule
module test_mulAddRecF16;

    test_mulAddRecFN#(5, 11) test_mulAddRecF16();

endmodule
module test_mulAddRecF32;

    test_mulAddRecFN#(8, 24) test_mulAddRecF32();

endmodule
module test_mulAddRecF64;

    test_mulAddRecFN#(11, 53) test_mulAddRecF64();

endmodule
module test_mulAddRecF128;

    test_mulAddRecFN#(15, 113) test_mulAddRecF128();

endmodule
module test_addRecF16_sub;

    test_addRecFN_sub#(5, 11) test_addRecF16_sub();

endmodule
module test_addRecF32_sub;

    test_addRecFN_sub#(8, 24) test_addRecF32_sub();

endmodule
module test_addRecF64_sub;

    test_addRecFN_sub#(11, 53) test_addRecF64_sub();

endmodule
module test_addRecF128_sub;

    test_addRecFN_sub#(15, 113) test_addRecF128_sub();

endmodule
module
    recF32ToRecF16 (
        input [(`floatControlWidth - 1):0] control,
        input [32:0] in,
        input [2:0] roundingMode,
        output [16:0] out,
        output [4:0] exceptionFlags
    );

    recFNToRecFN#(8, 24, 5, 11)
        recFNToRecFN(control, in, roundingMode, out, exceptionFlags);

endmodule
module
    recF64ToRecF16 (
        input [(`floatControlWidth - 1):0] control,
        input [64:0] in,
        input [2:0] roundingMode,
        output [16:0] out,
        output [4:0] exceptionFlags
    );

    recFNToRecFN#(11, 53, 5, 11)
        recFNToRecFN(control, in, roundingMode, out, exceptionFlags);

endmodule
module
    recF128ToRecF16 (
        input [(`floatControlWidth - 1):0] control,
        input [128:0] in,
        input [2:0] roundingMode,
        output [16:0] out,
        output [4:0] exceptionFlags
    );

    recFNToRecFN#(15, 113, 5, 11)
        recFNToRecFN(control, in, roundingMode, out, exceptionFlags);

endmodule
module
    recF16ToRecF32 (
        input [(`floatControlWidth - 1):0] control,
        input [16:0] in,
        input [2:0] roundingMode,
        output [32:0] out,
        output [4:0] exceptionFlags
    );

    recFNToRecFN#(5, 11, 8, 24)
        recFNToRecFN(control, in, roundingMode, out, exceptionFlags);

endmodule
module
    recF64ToRecF32 (
        input [(`floatControlWidth - 1):0] control,
        input [64:0] in,
        input [2:0] roundingMode,
        output [32:0] out,
        output [4:0] exceptionFlags
    );

    recFNToRecFN#(11, 53, 8, 24)
        recFNToRecFN(control, in, roundingMode, out, exceptionFlags);

endmodule
module
    recF128ToRecF32 (
        input [(`floatControlWidth - 1):0] control,
        input [128:0] in,
        input [2:0] roundingMode,
        output [32:0] out,
        output [4:0] exceptionFlags
    );

    recFNToRecFN#(15, 113, 8, 24)
        recFNToRecFN(control, in, roundingMode, out, exceptionFlags);

endmodule
module
    recF16ToRecF64 (
        input [(`floatControlWidth - 1):0] control,
        input [16:0] in,
        input [2:0] roundingMode,
        output [64:0] out,
        output [4:0] exceptionFlags
    );

    recFNToRecFN#(5, 11, 11, 53)
        recFNToRecFN(control, in, roundingMode, out, exceptionFlags);

endmodule
module
    recF32ToRecF64 (
        input [(`floatControlWidth - 1):0] control,
        input [32:0] in,
        input [2:0] roundingMode,
        output [64:0] out,
        output [4:0] exceptionFlags
    );

    recFNToRecFN#(8, 24, 11, 53)
        recFNToRecFN(control, in, roundingMode, out, exceptionFlags);

endmodule
module
    recF128ToRecF64 (
        input [(`floatControlWidth - 1):0] control,
        input [128:0] in,
        input [2:0] roundingMode,
        output [64:0] out,
        output [4:0] exceptionFlags
    );

    recFNToRecFN#(15, 113, 11, 53)
        recFNToRecFN(control, in, roundingMode, out, exceptionFlags);

endmodule
module
    recF16ToRecF128 (
        input [(`floatControlWidth - 1):0] control,
        input [16:0] in,
        input [2:0] roundingMode,
        output [128:0] out,
        output [4:0] exceptionFlags
    );

    recFNToRecFN#(5, 11, 15, 113)
        recFNToRecFN(control, in, roundingMode, out, exceptionFlags);

endmodule
module
    recF32ToRecF128 (
        input [(`floatControlWidth - 1):0] control,
        input [32:0] in,
        input [2:0] roundingMode,
        output [128:0] out,
        output [4:0] exceptionFlags
    );

    recFNToRecFN#(8, 24, 15, 113)
        recFNToRecFN(control, in, roundingMode, out, exceptionFlags);

endmodule
module
    recF64ToRecF128 (
        input [(`floatControlWidth - 1):0] control,
        input [64:0] in,
        input [2:0] roundingMode,
        output [128:0] out,
        output [4:0] exceptionFlags
    );

    recFNToRecFN#(11, 53, 15, 113)
        recFNToRecFN(control, in, roundingMode, out, exceptionFlags);

endmodule
module
    iNFromException#(parameter width = 1) (
        input signedOut,
        input isNaN,
        input sign,
        output [(width - 1):0] out
    );

    assign out =
        {!isNaN && (signedOut == sign), {(width - 1){!isNaN && !sign}}};

endmodule
module
    propagateFloatNaN_add#(parameter sigWidth = 3) (
        input [(`floatControlWidth - 1):0] control,
        input subOp,
        input isNaNA,
        input signA,
        input [(sigWidth - 2):0] fractA,
        input isNaNB,
        input signB,
        input [(sigWidth - 2):0] fractB,
        output signNaN,
        output [(sigWidth - 2):0] fractNaN
    );

    wire selectA =
        isNaNA && (!isNaNB || !fractA[sigWidth - 2] || fractB[sigWidth - 2]);
    wire selectB =
        isNaNB && (!isNaNA || (!fractB[sigWidth - 2] && fractA[sigWidth - 2]));
    assign signNaN = (selectA && signA) || (selectB && signB);
    assign fractNaN =
        {1'b1,
           (selectA ? fractA[(sigWidth - 3):0] : 1'b0)
         | (selectB ? fractB[(sigWidth - 3):0] : 1'b0)};

endmodule
module
    propagateFloatNaN_mul#(parameter sigWidth = 3) (
        input [(`floatControlWidth - 1):0] control,
        input isNaNA,
        input signA,
        input [(sigWidth - 2):0] fractA,
        input isNaNB,
        input signB,
        input [(sigWidth - 2):0] fractB,
        output signNaN,
        output [(sigWidth - 2):0] fractNaN
    );

    wire selectA =
        isNaNA && (!isNaNB || !fractA[sigWidth - 2] || fractB[sigWidth - 2]);
    wire selectB =
        isNaNB && (!isNaNA || (!fractB[sigWidth - 2] && fractA[sigWidth - 2]));
    assign signNaN = (selectA && signA) || (selectB && signB);
    assign fractNaN =
        {1'b1,
           (selectA ? fractA[(sigWidth - 3):0] : 1'b0)
         | (selectB ? fractB[(sigWidth - 3):0] : 1'b0)};

endmodule
module
    propagateFloatNaN_mulAdd#(parameter sigWidth = 3) (
        input [(`floatControlWidth - 1):0] control,
        input [1:0] op,
        input isNaNA,
        input signA,
        input [(sigWidth - 2):0] fractA,
        input isNaNB,
        input signB,
        input [(sigWidth - 2):0] fractB,
        input invalidProd,
        input isNaNC,
        input signC,
        input [(sigWidth - 2):0] fractC,
        output signNaN,
        output [(sigWidth - 2):0] fractNaN
    );

    wire isSigNaNC = isNaNC && !fractC[sigWidth - 2];
    wire selectA =
        isNaNA && !isSigNaNC
            && (!isNaNB || !fractA[sigWidth - 2] || fractB[sigWidth - 2]);
    wire selectB =
        isNaNB && !isSigNaNC
            && (!isNaNA || (!fractB[sigWidth - 2] && fractA[sigWidth - 2]));
    wire isNaNProd = isNaNA || isNaNB || invalidProd;
    wire selectC = isNaNC && (!isNaNProd || !fractC[sigWidth - 2]);
    assign signNaN =
        (selectA && signA) || (selectB && signB) || (selectC && signC);
    assign fractNaN =
        {1'b1,
           (selectA ? fractA[(sigWidth - 3):0] : 1'b0)
         | (selectB ? fractB[(sigWidth - 3):0] : 1'b0)
         | (selectC ? fractC[(sigWidth - 3):0] : 1'b0)};

endmodule
module
    propagateFloatNaN_divSqrt#(parameter sigWidth = 3) (
        input [(`floatControlWidth - 1):0] control,
        input sqrtOp,
        input isNaNA,
        input signA,
        input [(sigWidth - 2):0] fractA,
        input isNaNB,
        input signB,
        input [(sigWidth - 2):0] fractB,
        output signNaN,
        output [(sigWidth - 2):0] fractNaN
    );

    wire isTrueNaNB = !sqrtOp && isNaNB;
    wire selectA =
        isNaNA
            && (!isTrueNaNB || !fractA[sigWidth - 2] || fractB[sigWidth - 2]);
    wire selectB =
        isTrueNaNB
            && (!isNaNA || (!fractB[sigWidth - 2] && fractA[sigWidth - 2]));
    assign signNaN = (selectA && signA) || (selectB && signB);
    assign fractNaN =
        {1'b1,
           (selectA ? fractA[(sigWidth - 3):0] : 1'b0)
         | (selectB ? fractB[(sigWidth - 3):0] : 1'b0)};

endmodule
module
    iNFromException#(parameter width = 1) (
        input signedOut,
        input isNaN,
        input sign,
        output [(width - 1):0] out
    );

    wire maxInt = isNaN || !sign;
    assign out = {signedOut ^ maxInt, {(width - 1){maxInt}}};

endmodule
module
    iNFromException#(parameter width = 1) (
        input signedOut,
        input isNaN,
        input sign,
        output [(width - 1):0] out
    );

    assign out = {1'b1, {(width - 1){!signedOut}}};

endmodule
module
    propagateFloatNaN_add#(parameter sigWidth = 3) (
        input [(`floatControlWidth - 1):0] control,
        input subOp,
        input isNaNA,
        input signA,
        input [(sigWidth - 2):0] fractA,
        input isNaNB,
        input signB,
        input [(sigWidth - 2):0] fractB,
        output signNaN,
        output [(sigWidth - 2):0] fractNaN
    );

    assign signNaN = isNaNA ? signA : isNaNB ? signB : 1;
    assign fractNaN =
        {1'b1,
         isNaNA ? fractA[(sigWidth - 3):0] : isNaNB ? fractB[(sigWidth - 3):0]
             : 1'b0};

endmodule
module
    propagateFloatNaN_mul#(parameter sigWidth = 3) (
        input [(`floatControlWidth - 1):0] control,
        input isNaNA,
        input signA,
        input [(sigWidth - 2):0] fractA,
        input isNaNB,
        input signB,
        input [(sigWidth - 2):0] fractB,
        output signNaN,
        output [(sigWidth - 2):0] fractNaN
    );

    assign signNaN = isNaNA ? signA : isNaNB ? signB : 1;
    assign fractNaN =
        {1'b1,
         isNaNA ? fractA[(sigWidth - 3):0]
             : isNaNB ? fractB[(sigWidth - 3):0] : 1'b0};

endmodule
module
    propagateFloatNaN_mulAdd#(parameter sigWidth = 3) (
        input [(`floatControlWidth - 1):0] control,
        input [1:0] op,
        input isNaNA,
        input signA,
        input [(sigWidth - 2):0] fractA,
        input isNaNB,
        input signB,
        input [(sigWidth - 2):0] fractB,
        input invalidProd,
        input isNaNC,
        input signC,
        input [(sigWidth - 2):0] fractC,
        output signNaN,
        output [(sigWidth - 2):0] fractNaN
    );

    wire notNaNAOrB_propagateC = !invalidProd && isNaNC;
    assign signNaN =
        isNaNA ? signA : isNaNB ? signB : notNaNAOrB_propagateC ? signC : 1;
    assign fractNaN =
        {1'b1,
         isNaNA ? fractA[(sigWidth - 3):0]
             : isNaNB ? fractB[(sigWidth - 3):0]
                   : notNaNAOrB_propagateC ? fractC[(sigWidth - 3):0] : 1'b0};

endmodule