module mac_sgmii_0002 (
		input  wire         clk,              // control_port_clock_connection.clk
		input  wire         reset,            //              reset_connection.reset
		output wire [31:0]  reg_data_out,     //                  control_port.readdata
		input  wire         reg_rd,           //                              .read
		input  wire [31:0]  reg_data_in,      //                              .writedata
		input  wire         reg_wr,           //                              .write
		output wire         reg_busy,         //                              .waitrequest
		input  wire [7:0]   reg_addr,         //                              .address
		input  wire         ff_rx_clk,        //      receive_clock_connection.clk
		input  wire         ff_tx_clk,        //     transmit_clock_connection.clk
		output wire [31:0]  ff_rx_data,       //                       receive.data
		output wire         ff_rx_eop,        //                              .endofpacket
		output wire [5:0]   rx_err,           //                              .error
		output wire [1:0]   ff_rx_mod,        //                              .empty
		input  wire         ff_rx_rdy,        //                              .ready
		output wire         ff_rx_sop,        //                              .startofpacket
		output wire         ff_rx_dval,       //                              .valid
		input  wire [31:0]  ff_tx_data,       //                      transmit.data
		input  wire         ff_tx_eop,        //                              .endofpacket
		input  wire         ff_tx_err,        //                              .error
		input  wire [1:0]   ff_tx_mod,        //                              .empty
		output wire         ff_tx_rdy,        //                              .ready
		input  wire         ff_tx_sop,        //                              .startofpacket
		input  wire         ff_tx_wren,       //                              .valid
		input  wire         ff_tx_crc_fwd,    //           mac_misc_connection.ff_tx_crc_fwd
		output wire         ff_tx_septy,      //                              .ff_tx_septy
		output wire         tx_ff_uflow,      //                              .tx_ff_uflow
		output wire         ff_tx_a_full,     //                              .ff_tx_a_full
		output wire         ff_tx_a_empty,    //                              .ff_tx_a_empty
		output wire [17:0]  rx_err_stat,      //                              .rx_err_stat
		output wire [3:0]   rx_frm_type,      //                              .rx_frm_type
		output wire         ff_rx_dsav,       //                              .ff_rx_dsav
		output wire         ff_rx_a_full,     //                              .ff_rx_a_full
		output wire         ff_rx_a_empty,    //                              .ff_rx_a_empty
		input  wire         ref_clk,          //  pcs_ref_clk_clock_connection.clk
		output wire         led_crs,          //         status_led_connection.crs
		output wire         led_link,         //                              .link
		output wire         led_panel_link,   //                              .panel_link
		output wire         led_col,          //                              .col
		output wire         led_an,           //                              .an
		output wire         led_char_err,     //                              .char_err
		output wire         led_disp_err,     //                              .disp_err
		output wire         rx_recovclkout,   //     serdes_control_connection.rx_recovclkout
		input  wire [139:0] reconfig_togxb,   //                              .reconfig_togxb
		output wire [91:0]  reconfig_fromgxb, //                              .reconfig_fromgxb
		input  wire         rxp,              //             serial_connection.rxp
		output wire         txp               //                              .txp
	);

	wire   [31:0] avalon_arbiter_av_mac_master_0_readdata;                // i_tse_mac:reg_data_out -> avalon_arbiter:mac_readdata_0
	wire          avalon_arbiter_av_mac_master_0_waitrequest;             // i_tse_mac:reg_busy -> avalon_arbiter:mac_waitrequest_0
	wire    [7:0] avalon_arbiter_av_mac_master_0_address;                 // avalon_arbiter:mac_address_0 -> i_tse_mac:reg_addr
	wire          avalon_arbiter_av_mac_master_0_read;                    // avalon_arbiter:mac_read_0 -> i_tse_mac:reg_rd
	wire   [31:0] avalon_arbiter_av_mac_master_0_writedata;               // avalon_arbiter:mac_writedata_0 -> i_tse_mac:reg_data_in
	wire          avalon_arbiter_av_mac_master_0_write;                   // avalon_arbiter:mac_write_0 -> i_tse_mac:reg_wr
	wire          i_tse_pcs_0_sd_loopback_export;                         // i_tse_pcs_0:sd_loopback -> i_phyip_terminator_0:sd_loopback
	wire    [0:0] i_custom_phyip_0_rx_clkout_export;                      // i_custom_phyip_0:rx_clkout -> i_tse_pcs_0:rx_pcs_clk
	wire    [0:0] i_custom_phyip_0_rx_disperr_export;                     // i_custom_phyip_0:rx_disperr -> i_tse_pcs_0:rx_disp_err
	wire    [0:0] i_custom_phyip_0_tx_clkout_export;                      // i_custom_phyip_0:tx_clkout -> i_tse_pcs_0:tx_pcs_clk
	wire    [0:0] i_custom_phyip_0_rx_runningdisp_export;                 // i_custom_phyip_0:rx_runningdisp -> i_tse_pcs_0:rx_runningdisp
	wire    [7:0] i_custom_phyip_0_rx_parallel_data_export;               // i_custom_phyip_0:rx_parallel_data -> i_tse_pcs_0:rx_frame
	wire    [0:0] i_custom_phyip_0_rx_rlv_export;                         // i_custom_phyip_0:rx_rlv -> i_tse_pcs_0:rx_runlengthviolation
	wire    [0:0] i_custom_phyip_0_rx_errdetect_export;                   // i_custom_phyip_0:rx_errdetect -> i_tse_pcs_0:rx_char_err_gx
	wire    [7:0] i_tse_pcs_0_tx_frame_export;                            // i_tse_pcs_0:tx_frame -> i_custom_phyip_0:tx_parallel_data
	wire    [0:0] i_custom_phyip_0_rx_patterndetect_export;               // i_custom_phyip_0:rx_patterndetect -> i_tse_pcs_0:rx_patterndetect
	wire    [0:0] i_custom_phyip_0_rx_datak_export;                       // i_custom_phyip_0:rx_datak -> i_tse_pcs_0:rx_kchar
	wire    [0:0] i_custom_phyip_0_rx_syncstatus_export;                  // i_custom_phyip_0:rx_syncstatus -> i_tse_pcs_0:rx_syncstatus
	wire    [4:0] i_custom_phyip_0_rx_bitslipboundaryselectout_export;    // i_custom_phyip_0:rx_bitslipboundaryselectout -> i_tse_pcs_0:wa_boundary
	wire          i_tse_pcs_0_tx_kchar_export;                            // i_tse_pcs_0:tx_kchar -> i_custom_phyip_0:tx_datak
	wire          i_custom_phyip_0_tx_ready_export;                       // i_custom_phyip_0:tx_ready -> i_phyip_terminator_0:tx_ready
	wire    [0:0] i_custom_phyip_0_tx_serial_data_export;                 // i_custom_phyip_0:tx_serial_data -> i_phyip_terminator_0:tx_serial_data
	wire  [139:0] i_phyip_terminator_0_reconfig_to_xcvr_reconfig_to_xcvr; // i_phyip_terminator_0:reconfig_to_xcvr -> i_custom_phyip_0:reconfig_to_xcvr
	wire    [0:0] i_custom_phyip_0_pll_locked_export;                     // i_custom_phyip_0:pll_locked -> i_phyip_terminator_0:pll_locked
	wire   [91:0] i_custom_phyip_0_reconfig_from_xcvr_reconfig_from_xcvr; // i_custom_phyip_0:reconfig_from_xcvr -> i_phyip_terminator_0:reconfig_from_xcvr
	wire          i_custom_phyip_0_rx_ready_export;                       // i_custom_phyip_0:rx_ready -> i_phyip_terminator_0:rx_ready
	wire          i_phyip_terminator_0_rx_serial_data_export;             // i_phyip_terminator_0:rx_serial_data -> i_custom_phyip_0:rx_serial_data
	wire    [0:0] i_custom_phyip_0_rx_recovered_clk_export;               // i_custom_phyip_0:rx_recovered_clk -> i_phyip_terminator_0:rx_recovered_clk
	wire   [31:0] i_phyip_terminator_0_av_dummy_master_readdata;          // i_custom_phyip_0:phy_mgmt_readdata -> i_phyip_terminator_0:readdata
	wire          i_phyip_terminator_0_av_dummy_master_waitrequest;       // i_custom_phyip_0:phy_mgmt_waitrequest -> i_phyip_terminator_0:waitrequest
	wire    [8:0] i_phyip_terminator_0_av_dummy_master_address;           // i_phyip_terminator_0:address -> i_custom_phyip_0:phy_mgmt_address
	wire          i_phyip_terminator_0_av_dummy_master_read;              // i_phyip_terminator_0:read -> i_custom_phyip_0:phy_mgmt_read
	wire   [31:0] i_phyip_terminator_0_av_dummy_master_writedata;         // i_phyip_terminator_0:writedata -> i_custom_phyip_0:phy_mgmt_writedata
	wire          i_phyip_terminator_0_av_dummy_master_write;             // i_phyip_terminator_0:write -> i_custom_phyip_0:phy_mgmt_write
	wire   [15:0] avalon_arbiter_av_pcs_master_0_readdata;                // i_tse_pcs_0:reg_data_out -> avalon_arbiter:pcs_readdata_0
	wire          avalon_arbiter_av_pcs_master_0_waitrequest;             // i_tse_pcs_0:reg_busy -> avalon_arbiter:pcs_waitrequest_0
	wire    [4:0] avalon_arbiter_av_pcs_master_0_address;                 // avalon_arbiter:pcs_address_0 -> i_tse_pcs_0:reg_addr
	wire          avalon_arbiter_av_pcs_master_0_read;                    // avalon_arbiter:pcs_read_0 -> i_tse_pcs_0:reg_rd
	wire   [15:0] avalon_arbiter_av_pcs_master_0_writedata;               // avalon_arbiter:pcs_writedata_0 -> i_tse_pcs_0:reg_data_in
	wire          avalon_arbiter_av_pcs_master_0_write;                   // avalon_arbiter:pcs_write_0 -> i_tse_pcs_0:reg_wr
	wire          i_tse_pcs_0_pcs_transmit_clock_connection_clk;          // i_tse_pcs_0:tx_clk -> [i_tse_mac:tx_clk, rst_controller:clk]
	wire          i_tse_pcs_0_pcs_receive_clock_connection_clk;           // i_tse_pcs_0:rx_clk -> [i_tse_mac:rx_clk, rst_controller_001:clk]
	wire    [7:0] i_tse_pcs_0_gmii_connection_gmii_rx_d;                  // i_tse_pcs_0:gmii_rx_d -> i_tse_mac:gm_rx_d
	wire          i_tse_pcs_0_gmii_connection_gmii_rx_err;                // i_tse_pcs_0:gmii_rx_err -> i_tse_mac:gm_rx_err
	wire          i_tse_pcs_0_gmii_connection_gmii_rx_dv;                 // i_tse_pcs_0:gmii_rx_dv -> i_tse_mac:gm_rx_dv
	wire    [7:0] i_tse_mac_mac_gmii_connection_gmii_tx_d;                // i_tse_mac:gm_tx_d -> i_tse_pcs_0:gmii_tx_d
	wire          i_tse_mac_mac_gmii_connection_gmii_tx_en;               // i_tse_mac:gm_tx_en -> i_tse_pcs_0:gmii_tx_en
	wire          i_tse_mac_mac_gmii_connection_gmii_tx_err;              // i_tse_mac:gm_tx_err -> i_tse_pcs_0:gmii_tx_err
	wire          i_tse_mac_mac_mii_connection_mii_tx_en;                 // i_tse_mac:m_tx_en -> i_tse_pcs_0:mii_tx_en
	wire    [3:0] i_tse_pcs_0_mii_connection_mii_rx_d;                    // i_tse_pcs_0:mii_rx_d -> i_tse_mac:m_rx_d
	wire          i_tse_pcs_0_mii_connection_mii_col;                     // i_tse_pcs_0:mii_col -> i_tse_mac:m_rx_col
	wire    [3:0] i_tse_mac_mac_mii_connection_mii_tx_d;                  // i_tse_mac:m_tx_d -> i_tse_pcs_0:mii_tx_d
	wire          i_tse_mac_mac_mii_connection_mii_tx_err;                // i_tse_mac:m_tx_err -> i_tse_pcs_0:mii_tx_err
	wire          i_tse_pcs_0_mii_connection_mii_crs;                     // i_tse_pcs_0:mii_crs -> i_tse_mac:m_rx_crs
	wire          i_tse_pcs_0_mii_connection_mii_rx_err;                  // i_tse_pcs_0:mii_rx_err -> i_tse_mac:m_rx_err
	wire          i_tse_pcs_0_mii_connection_mii_rx_dv;                   // i_tse_pcs_0:mii_rx_dv -> i_tse_mac:m_rx_en
	wire          i_tse_pcs_0_sgmii_status_connection_set_1000;           // i_tse_pcs_0:set_1000 -> i_tse_mac:set_1000
	wire          i_tse_pcs_0_sgmii_status_connection_set_10;             // i_tse_pcs_0:set_10 -> i_tse_mac:set_10
	wire          i_tse_pcs_0_clock_enable_connection_tx_clkena;          // i_tse_pcs_0:tx_clkena -> i_tse_mac:tx_clkena
	wire          i_tse_pcs_0_clock_enable_connection_rx_clkena;          // i_tse_pcs_0:rx_clkena -> i_tse_mac:rx_clkena
	wire          rst_controller_reset_out_reset;                         // rst_controller:reset_out -> i_tse_pcs_0:reset_tx_clk
	wire          rst_controller_001_reset_out_reset;                     // rst_controller_001:reset_out -> i_tse_pcs_0:reset_rx_clk

	altera_eth_tse_mac #(
		.ING_ADDR                 (9),
		.ENABLE_MAC_RX_VLAN       (0),
		.ENABLE_SUP_ADDR          (0),
		.DEVICE_FAMILY            ("STRATIXV"),
		.INSERT_TA                (0),
		.ING_FIFO                 (512),
		.ENABLE_ECC               (0),
		.CRC32DWIDTH              (8),
		.ENABLE_ENA               (32),
		.SYNCHRONIZER_DEPTH       (3),
		.ENABLE_MAC_TX_VLAN       (0),
		.RESET_LEVEL              (1),
		.STAT_CNT_ENA             (1),
		.CUST_VERSION             (0),
		.CRC32S1L2_EXTERN         (0),
		.MBIT_ONLY                (1),
		.EG_ADDR                  (9),
		.CORE_VERSION             (3840),
		.CRC32GENDELAY            (6),
		.EG_FIFO                  (512),
		.REDUCED_INTERFACE_ENA    (0),
		.ENABLE_MAGIC_DETECT      (0),
		.ENABLE_MDIO              (0),
		.ENABLE_MAC_TXADDR_SET    (1),
		.RAM_TYPE                 ("AUTO"),
		.CRC32CHECK16BIT          (0),
		.ENABLE_LGTH_CHECK        (1),
		.ENABLE_MAC_FLOW_CTRL     (0),
		.ENABLE_SHIFT16           (0),
		.USE_SYNC_RESET           (1),
		.REDUCED_CONTROL          (0),
		.MDIO_CLK_DIV             (40),
		.ENABLE_PADDING           (1),
		.ENABLE_GMII_LOOPBACK     (0),
		.GBIT_ONLY                (1),
		.ENA_HASH                 (0),
		.ENABLE_EXTENDED_STAT_REG (1),
		.ENABLE_HD_LOGIC          (0)
	) i_tse_mac (
		.clk             (clk),                                           // control_port_clock_connection.clk
		.reset           (reset),                                         //              reset_connection.reset
		.reg_addr        (avalon_arbiter_av_mac_master_0_address),        //                  control_port.address
		.reg_data_out    (avalon_arbiter_av_mac_master_0_readdata),       //                              .readdata
		.reg_rd          (avalon_arbiter_av_mac_master_0_read),           //                              .read
		.reg_data_in     (avalon_arbiter_av_mac_master_0_writedata),      //                              .writedata
		.reg_wr          (avalon_arbiter_av_mac_master_0_write),          //                              .write
		.reg_busy        (avalon_arbiter_av_mac_master_0_waitrequest),    //                              .waitrequest
		.ff_tx_clk       (ff_tx_clk),                                     //     transmit_clock_connection.clk
		.ff_rx_clk       (ff_rx_clk),                                     //      receive_clock_connection.clk
		.ff_rx_data      (ff_rx_data),                                    //                       receive.data
		.ff_rx_eop       (ff_rx_eop),                                     //                              .endofpacket
		.rx_err          (rx_err),                                        //                              .error
		.ff_rx_mod       (ff_rx_mod),                                     //                              .empty
		.ff_rx_rdy       (ff_rx_rdy),                                     //                              .ready
		.ff_rx_sop       (ff_rx_sop),                                     //                              .startofpacket
		.ff_rx_dval      (ff_rx_dval),                                    //                              .valid
		.ff_tx_data      (ff_tx_data),                                    //                      transmit.data
		.ff_tx_eop       (ff_tx_eop),                                     //                              .endofpacket
		.ff_tx_err       (ff_tx_err),                                     //                              .error
		.ff_tx_mod       (ff_tx_mod),                                     //                              .empty
		.ff_tx_rdy       (ff_tx_rdy),                                     //                              .ready
		.ff_tx_sop       (ff_tx_sop),                                     //                              .startofpacket
		.ff_tx_wren      (ff_tx_wren),                                    //                              .valid
		.ff_tx_crc_fwd   (ff_tx_crc_fwd),                                 //           mac_misc_connection.export
		.ff_tx_septy     (ff_tx_septy),                                   //                              .export
		.tx_ff_uflow     (tx_ff_uflow),                                   //                              .export
		.ff_tx_a_full    (ff_tx_a_full),                                  //                              .export
		.ff_tx_a_empty   (ff_tx_a_empty),                                 //                              .export
		.rx_err_stat     (rx_err_stat),                                   //                              .export
		.rx_frm_type     (rx_frm_type),                                   //                              .export
		.ff_rx_dsav      (ff_rx_dsav),                                    //                              .export
		.ff_rx_a_full    (ff_rx_a_full),                                  //                              .export
		.ff_rx_a_empty   (ff_rx_a_empty),                                 //                              .export
		.gm_rx_d         (i_tse_pcs_0_gmii_connection_gmii_rx_d),         //           mac_gmii_connection.gmii_rx_d
		.gm_rx_dv        (i_tse_pcs_0_gmii_connection_gmii_rx_dv),        //                              .gmii_rx_dv
		.gm_rx_err       (i_tse_pcs_0_gmii_connection_gmii_rx_err),       //                              .gmii_rx_err
		.gm_tx_d         (i_tse_mac_mac_gmii_connection_gmii_tx_d),       //                              .gmii_tx_d
		.gm_tx_en        (i_tse_mac_mac_gmii_connection_gmii_tx_en),      //                              .gmii_tx_en
		.gm_tx_err       (i_tse_mac_mac_gmii_connection_gmii_tx_err),     //                              .gmii_tx_err
		.m_rx_d          (i_tse_pcs_0_mii_connection_mii_rx_d),           //            mac_mii_connection.mii_rx_d
		.m_rx_en         (i_tse_pcs_0_mii_connection_mii_rx_dv),          //                              .mii_rx_dv
		.m_rx_err        (i_tse_pcs_0_mii_connection_mii_rx_err),         //                              .mii_rx_err
		.m_tx_d          (i_tse_mac_mac_mii_connection_mii_tx_d),         //                              .mii_tx_d
		.m_tx_en         (i_tse_mac_mac_mii_connection_mii_tx_en),        //                              .mii_tx_en
		.m_tx_err        (i_tse_mac_mac_mii_connection_mii_tx_err),       //                              .mii_tx_err
		.m_rx_crs        (i_tse_pcs_0_mii_connection_mii_crs),            //                              .mii_crs
		.m_rx_col        (i_tse_pcs_0_mii_connection_mii_col),            //                              .mii_col
		.set_10          (i_tse_pcs_0_sgmii_status_connection_set_10),    //         mac_status_connection.set_10
		.set_1000        (i_tse_pcs_0_sgmii_status_connection_set_1000),  //                              .set_1000
		.rx_clkena       (i_tse_pcs_0_clock_enable_connection_rx_clkena), //         mac_clkena_connection.rx_clkena
		.tx_clkena       (i_tse_pcs_0_clock_enable_connection_tx_clkena), //                              .tx_clkena
		.tx_clk          (i_tse_pcs_0_pcs_transmit_clock_connection_clk), //   pcs_mac_tx_clock_connection.clk
		.rx_clk          (i_tse_pcs_0_pcs_receive_clock_connection_clk),  //   pcs_mac_rx_clock_connection.clk
		.magic_sleep_n   (1'b1),                                          //                   (terminated)
		.xon_gen         (1'b0),                                          //                   (terminated)
		.xoff_gen        (1'b0),                                          //                   (terminated)
		.magic_wakeup    (),                                              //                   (terminated)
		.mac_eccstatus   (),                                              //                   (terminated)
		.mdc             (),                                              //                   (terminated)
		.mdio_in         (1'b0),                                          //                   (terminated)
		.mdio_out        (),                                              //                   (terminated)
		.mdio_oen        (),                                              //                   (terminated)
		.rgmii_out1_aclr (),                                              //                   (terminated)
		.rgmii_out1_din  (),                                              //                   (terminated)
		.rgmii_in1_dout  (2'b00),                                         //                   (terminated)
		.rgmii_in1_ck    (),                                              //                   (terminated)
		.rgmii_out4_din  (),                                              //                   (terminated)
		.rgmii_out4_ck   (),                                              //                   (terminated)
		.rgmii_in1_pad   (),                                              //                   (terminated)
		.rgmii_out4_aclr (),                                              //                   (terminated)
		.rgmii_out1_pad  (1'b0),                                          //                   (terminated)
		.rgmii_out1_ck   (),                                              //                   (terminated)
		.rgmii_in4_dout  (8'b00000000),                                   //                   (terminated)
		.rgmii_in4_pad   (),                                              //                   (terminated)
		.rgmii_out4_pad  (4'b0000),                                       //                   (terminated)
		.rgmii_in4_ck    (),                                              //                   (terminated)
		.rgmii_in        (4'b0000),                                       //                   (terminated)
		.rgmii_out       (),                                              //                   (terminated)
		.rx_control      (1'b0),                                          //                   (terminated)
		.tx_control      (),                                              //                   (terminated)
		.eth_mode        (),                                              //                   (terminated)
		.ena_10          ()                                               //                   (terminated)
	);

	altera_eth_tse_avalon_arbiter #(
		.MAX_CHANNELS     (1),
		.MAC_ONLY         (0),
		.SLAVE_ADDR_WIDTH (8)
	) avalon_arbiter (
		.clk                (clk),                                        //             clk.clk
		.reset              (reset),                                      //           reset.reset
		.reg_data_out       (reg_data_out),                               //        av_slave.readdata
		.reg_rd             (reg_rd),                                     //                .read
		.reg_data_in        (reg_data_in),                                //                .writedata
		.reg_wr             (reg_wr),                                     //                .write
		.reg_busy           (reg_busy),                                   //                .waitrequest
		.reg_addr           (reg_addr),                                   //                .address
		.mac_address_0      (avalon_arbiter_av_mac_master_0_address),     // av_mac_master_0.address
		.mac_readdata_0     (avalon_arbiter_av_mac_master_0_readdata),    //                .readdata
		.mac_read_0         (avalon_arbiter_av_mac_master_0_read),        //                .read
		.mac_writedata_0    (avalon_arbiter_av_mac_master_0_writedata),   //                .writedata
		.mac_write_0        (avalon_arbiter_av_mac_master_0_write),       //                .write
		.mac_waitrequest_0  (avalon_arbiter_av_mac_master_0_waitrequest), //                .waitrequest
		.pcs_address_0      (avalon_arbiter_av_pcs_master_0_address),     // av_pcs_master_0.address
		.pcs_readdata_0     (avalon_arbiter_av_pcs_master_0_readdata),    //                .readdata
		.pcs_read_0         (avalon_arbiter_av_pcs_master_0_read),        //                .read
		.pcs_writedata_0    (avalon_arbiter_av_pcs_master_0_writedata),   //                .writedata
		.pcs_write_0        (avalon_arbiter_av_pcs_master_0_write),       //                .write
		.pcs_waitrequest_0  (avalon_arbiter_av_pcs_master_0_waitrequest), //                .waitrequest
		.mac_address_1      (),                                           //     (terminated)
		.mac_readdata_1     (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_1         (),                                           //     (terminated)
		.mac_writedata_1    (),                                           //     (terminated)
		.mac_write_1        (),                                           //     (terminated)
		.mac_waitrequest_1  (1'b0),                                       //     (terminated)
		.pcs_address_1      (),                                           //     (terminated)
		.pcs_readdata_1     (16'b0000000000000000),                       //     (terminated)
		.pcs_read_1         (),                                           //     (terminated)
		.pcs_writedata_1    (),                                           //     (terminated)
		.pcs_write_1        (),                                           //     (terminated)
		.pcs_waitrequest_1  (1'b0),                                       //     (terminated)
		.mac_address_2      (),                                           //     (terminated)
		.mac_readdata_2     (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_2         (),                                           //     (terminated)
		.mac_writedata_2    (),                                           //     (terminated)
		.mac_write_2        (),                                           //     (terminated)
		.mac_waitrequest_2  (1'b0),                                       //     (terminated)
		.pcs_address_2      (),                                           //     (terminated)
		.pcs_readdata_2     (16'b0000000000000000),                       //     (terminated)
		.pcs_read_2         (),                                           //     (terminated)
		.pcs_writedata_2    (),                                           //     (terminated)
		.pcs_write_2        (),                                           //     (terminated)
		.pcs_waitrequest_2  (1'b0),                                       //     (terminated)
		.mac_address_3      (),                                           //     (terminated)
		.mac_readdata_3     (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_3         (),                                           //     (terminated)
		.mac_writedata_3    (),                                           //     (terminated)
		.mac_write_3        (),                                           //     (terminated)
		.mac_waitrequest_3  (1'b0),                                       //     (terminated)
		.pcs_address_3      (),                                           //     (terminated)
		.pcs_readdata_3     (16'b0000000000000000),                       //     (terminated)
		.pcs_read_3         (),                                           //     (terminated)
		.pcs_writedata_3    (),                                           //     (terminated)
		.pcs_write_3        (),                                           //     (terminated)
		.pcs_waitrequest_3  (1'b0),                                       //     (terminated)
		.mac_address_4      (),                                           //     (terminated)
		.mac_readdata_4     (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_4         (),                                           //     (terminated)
		.mac_writedata_4    (),                                           //     (terminated)
		.mac_write_4        (),                                           //     (terminated)
		.mac_waitrequest_4  (1'b0),                                       //     (terminated)
		.pcs_address_4      (),                                           //     (terminated)
		.pcs_readdata_4     (16'b0000000000000000),                       //     (terminated)
		.pcs_read_4         (),                                           //     (terminated)
		.pcs_writedata_4    (),                                           //     (terminated)
		.pcs_write_4        (),                                           //     (terminated)
		.pcs_waitrequest_4  (1'b0),                                       //     (terminated)
		.mac_address_5      (),                                           //     (terminated)
		.mac_readdata_5     (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_5         (),                                           //     (terminated)
		.mac_writedata_5    (),                                           //     (terminated)
		.mac_write_5        (),                                           //     (terminated)
		.mac_waitrequest_5  (1'b0),                                       //     (terminated)
		.pcs_address_5      (),                                           //     (terminated)
		.pcs_readdata_5     (16'b0000000000000000),                       //     (terminated)
		.pcs_read_5         (),                                           //     (terminated)
		.pcs_writedata_5    (),                                           //     (terminated)
		.pcs_write_5        (),                                           //     (terminated)
		.pcs_waitrequest_5  (1'b0),                                       //     (terminated)
		.mac_address_6      (),                                           //     (terminated)
		.mac_readdata_6     (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_6         (),                                           //     (terminated)
		.mac_writedata_6    (),                                           //     (terminated)
		.mac_write_6        (),                                           //     (terminated)
		.mac_waitrequest_6  (1'b0),                                       //     (terminated)
		.pcs_address_6      (),                                           //     (terminated)
		.pcs_readdata_6     (16'b0000000000000000),                       //     (terminated)
		.pcs_read_6         (),                                           //     (terminated)
		.pcs_writedata_6    (),                                           //     (terminated)
		.pcs_write_6        (),                                           //     (terminated)
		.pcs_waitrequest_6  (1'b0),                                       //     (terminated)
		.mac_address_7      (),                                           //     (terminated)
		.mac_readdata_7     (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_7         (),                                           //     (terminated)
		.mac_writedata_7    (),                                           //     (terminated)
		.mac_write_7        (),                                           //     (terminated)
		.mac_waitrequest_7  (1'b0),                                       //     (terminated)
		.pcs_address_7      (),                                           //     (terminated)
		.pcs_readdata_7     (16'b0000000000000000),                       //     (terminated)
		.pcs_read_7         (),                                           //     (terminated)
		.pcs_writedata_7    (),                                           //     (terminated)
		.pcs_write_7        (),                                           //     (terminated)
		.pcs_waitrequest_7  (1'b0),                                       //     (terminated)
		.mac_address_8      (),                                           //     (terminated)
		.mac_readdata_8     (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_8         (),                                           //     (terminated)
		.mac_writedata_8    (),                                           //     (terminated)
		.mac_write_8        (),                                           //     (terminated)
		.mac_waitrequest_8  (1'b0),                                       //     (terminated)
		.pcs_address_8      (),                                           //     (terminated)
		.pcs_readdata_8     (16'b0000000000000000),                       //     (terminated)
		.pcs_read_8         (),                                           //     (terminated)
		.pcs_writedata_8    (),                                           //     (terminated)
		.pcs_write_8        (),                                           //     (terminated)
		.pcs_waitrequest_8  (1'b0),                                       //     (terminated)
		.mac_address_9      (),                                           //     (terminated)
		.mac_readdata_9     (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_9         (),                                           //     (terminated)
		.mac_writedata_9    (),                                           //     (terminated)
		.mac_write_9        (),                                           //     (terminated)
		.mac_waitrequest_9  (1'b0),                                       //     (terminated)
		.pcs_address_9      (),                                           //     (terminated)
		.pcs_readdata_9     (16'b0000000000000000),                       //     (terminated)
		.pcs_read_9         (),                                           //     (terminated)
		.pcs_writedata_9    (),                                           //     (terminated)
		.pcs_write_9        (),                                           //     (terminated)
		.pcs_waitrequest_9  (1'b0),                                       //     (terminated)
		.mac_address_10     (),                                           //     (terminated)
		.mac_readdata_10    (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_10        (),                                           //     (terminated)
		.mac_writedata_10   (),                                           //     (terminated)
		.mac_write_10       (),                                           //     (terminated)
		.mac_waitrequest_10 (1'b0),                                       //     (terminated)
		.pcs_address_10     (),                                           //     (terminated)
		.pcs_readdata_10    (16'b0000000000000000),                       //     (terminated)
		.pcs_read_10        (),                                           //     (terminated)
		.pcs_writedata_10   (),                                           //     (terminated)
		.pcs_write_10       (),                                           //     (terminated)
		.pcs_waitrequest_10 (1'b0),                                       //     (terminated)
		.mac_address_11     (),                                           //     (terminated)
		.mac_readdata_11    (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_11        (),                                           //     (terminated)
		.mac_writedata_11   (),                                           //     (terminated)
		.mac_write_11       (),                                           //     (terminated)
		.mac_waitrequest_11 (1'b0),                                       //     (terminated)
		.pcs_address_11     (),                                           //     (terminated)
		.pcs_readdata_11    (16'b0000000000000000),                       //     (terminated)
		.pcs_read_11        (),                                           //     (terminated)
		.pcs_writedata_11   (),                                           //     (terminated)
		.pcs_write_11       (),                                           //     (terminated)
		.pcs_waitrequest_11 (1'b0),                                       //     (terminated)
		.mac_address_12     (),                                           //     (terminated)
		.mac_readdata_12    (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_12        (),                                           //     (terminated)
		.mac_writedata_12   (),                                           //     (terminated)
		.mac_write_12       (),                                           //     (terminated)
		.mac_waitrequest_12 (1'b0),                                       //     (terminated)
		.pcs_address_12     (),                                           //     (terminated)
		.pcs_readdata_12    (16'b0000000000000000),                       //     (terminated)
		.pcs_read_12        (),                                           //     (terminated)
		.pcs_writedata_12   (),                                           //     (terminated)
		.pcs_write_12       (),                                           //     (terminated)
		.pcs_waitrequest_12 (1'b0),                                       //     (terminated)
		.mac_address_13     (),                                           //     (terminated)
		.mac_readdata_13    (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_13        (),                                           //     (terminated)
		.mac_writedata_13   (),                                           //     (terminated)
		.mac_write_13       (),                                           //     (terminated)
		.mac_waitrequest_13 (1'b0),                                       //     (terminated)
		.pcs_address_13     (),                                           //     (terminated)
		.pcs_readdata_13    (16'b0000000000000000),                       //     (terminated)
		.pcs_read_13        (),                                           //     (terminated)
		.pcs_writedata_13   (),                                           //     (terminated)
		.pcs_write_13       (),                                           //     (terminated)
		.pcs_waitrequest_13 (1'b0),                                       //     (terminated)
		.mac_address_14     (),                                           //     (terminated)
		.mac_readdata_14    (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_14        (),                                           //     (terminated)
		.mac_writedata_14   (),                                           //     (terminated)
		.mac_write_14       (),                                           //     (terminated)
		.mac_waitrequest_14 (1'b0),                                       //     (terminated)
		.pcs_address_14     (),                                           //     (terminated)
		.pcs_readdata_14    (16'b0000000000000000),                       //     (terminated)
		.pcs_read_14        (),                                           //     (terminated)
		.pcs_writedata_14   (),                                           //     (terminated)
		.pcs_write_14       (),                                           //     (terminated)
		.pcs_waitrequest_14 (1'b0),                                       //     (terminated)
		.mac_address_15     (),                                           //     (terminated)
		.mac_readdata_15    (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_15        (),                                           //     (terminated)
		.mac_writedata_15   (),                                           //     (terminated)
		.mac_write_15       (),                                           //     (terminated)
		.mac_waitrequest_15 (1'b0),                                       //     (terminated)
		.pcs_address_15     (),                                           //     (terminated)
		.pcs_readdata_15    (16'b0000000000000000),                       //     (terminated)
		.pcs_read_15        (),                                           //     (terminated)
		.pcs_writedata_15   (),                                           //     (terminated)
		.pcs_write_15       (),                                           //     (terminated)
		.pcs_waitrequest_15 (1'b0),                                       //     (terminated)
		.mac_address_16     (),                                           //     (terminated)
		.mac_readdata_16    (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_16        (),                                           //     (terminated)
		.mac_writedata_16   (),                                           //     (terminated)
		.mac_write_16       (),                                           //     (terminated)
		.mac_waitrequest_16 (1'b0),                                       //     (terminated)
		.pcs_address_16     (),                                           //     (terminated)
		.pcs_readdata_16    (16'b0000000000000000),                       //     (terminated)
		.pcs_read_16        (),                                           //     (terminated)
		.pcs_writedata_16   (),                                           //     (terminated)
		.pcs_write_16       (),                                           //     (terminated)
		.pcs_waitrequest_16 (1'b0),                                       //     (terminated)
		.mac_address_17     (),                                           //     (terminated)
		.mac_readdata_17    (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_17        (),                                           //     (terminated)
		.mac_writedata_17   (),                                           //     (terminated)
		.mac_write_17       (),                                           //     (terminated)
		.mac_waitrequest_17 (1'b0),                                       //     (terminated)
		.pcs_address_17     (),                                           //     (terminated)
		.pcs_readdata_17    (16'b0000000000000000),                       //     (terminated)
		.pcs_read_17        (),                                           //     (terminated)
		.pcs_writedata_17   (),                                           //     (terminated)
		.pcs_write_17       (),                                           //     (terminated)
		.pcs_waitrequest_17 (1'b0),                                       //     (terminated)
		.mac_address_18     (),                                           //     (terminated)
		.mac_readdata_18    (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_18        (),                                           //     (terminated)
		.mac_writedata_18   (),                                           //     (terminated)
		.mac_write_18       (),                                           //     (terminated)
		.mac_waitrequest_18 (1'b0),                                       //     (terminated)
		.pcs_address_18     (),                                           //     (terminated)
		.pcs_readdata_18    (16'b0000000000000000),                       //     (terminated)
		.pcs_read_18        (),                                           //     (terminated)
		.pcs_writedata_18   (),                                           //     (terminated)
		.pcs_write_18       (),                                           //     (terminated)
		.pcs_waitrequest_18 (1'b0),                                       //     (terminated)
		.mac_address_19     (),                                           //     (terminated)
		.mac_readdata_19    (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_19        (),                                           //     (terminated)
		.mac_writedata_19   (),                                           //     (terminated)
		.mac_write_19       (),                                           //     (terminated)
		.mac_waitrequest_19 (1'b0),                                       //     (terminated)
		.pcs_address_19     (),                                           //     (terminated)
		.pcs_readdata_19    (16'b0000000000000000),                       //     (terminated)
		.pcs_read_19        (),                                           //     (terminated)
		.pcs_writedata_19   (),                                           //     (terminated)
		.pcs_write_19       (),                                           //     (terminated)
		.pcs_waitrequest_19 (1'b0),                                       //     (terminated)
		.mac_address_20     (),                                           //     (terminated)
		.mac_readdata_20    (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_20        (),                                           //     (terminated)
		.mac_writedata_20   (),                                           //     (terminated)
		.mac_write_20       (),                                           //     (terminated)
		.mac_waitrequest_20 (1'b0),                                       //     (terminated)
		.pcs_address_20     (),                                           //     (terminated)
		.pcs_readdata_20    (16'b0000000000000000),                       //     (terminated)
		.pcs_read_20        (),                                           //     (terminated)
		.pcs_writedata_20   (),                                           //     (terminated)
		.pcs_write_20       (),                                           //     (terminated)
		.pcs_waitrequest_20 (1'b0),                                       //     (terminated)
		.mac_address_21     (),                                           //     (terminated)
		.mac_readdata_21    (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_21        (),                                           //     (terminated)
		.mac_writedata_21   (),                                           //     (terminated)
		.mac_write_21       (),                                           //     (terminated)
		.mac_waitrequest_21 (1'b0),                                       //     (terminated)
		.pcs_address_21     (),                                           //     (terminated)
		.pcs_readdata_21    (16'b0000000000000000),                       //     (terminated)
		.pcs_read_21        (),                                           //     (terminated)
		.pcs_writedata_21   (),                                           //     (terminated)
		.pcs_write_21       (),                                           //     (terminated)
		.pcs_waitrequest_21 (1'b0),                                       //     (terminated)
		.mac_address_22     (),                                           //     (terminated)
		.mac_readdata_22    (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_22        (),                                           //     (terminated)
		.mac_writedata_22   (),                                           //     (terminated)
		.mac_write_22       (),                                           //     (terminated)
		.mac_waitrequest_22 (1'b0),                                       //     (terminated)
		.pcs_address_22     (),                                           //     (terminated)
		.pcs_readdata_22    (16'b0000000000000000),                       //     (terminated)
		.pcs_read_22        (),                                           //     (terminated)
		.pcs_writedata_22   (),                                           //     (terminated)
		.pcs_write_22       (),                                           //     (terminated)
		.pcs_waitrequest_22 (1'b0),                                       //     (terminated)
		.mac_address_23     (),                                           //     (terminated)
		.mac_readdata_23    (32'b00000000000000000000000000000000),       //     (terminated)
		.mac_read_23        (),                                           //     (terminated)
		.mac_writedata_23   (),                                           //     (terminated)
		.mac_write_23       (),                                           //     (terminated)
		.mac_waitrequest_23 (1'b0),                                       //     (terminated)
		.pcs_address_23     (),                                           //     (terminated)
		.pcs_readdata_23    (16'b0000000000000000),                       //     (terminated)
		.pcs_read_23        (),                                           //     (terminated)
		.pcs_writedata_23   (),                                           //     (terminated)
		.pcs_write_23       (),                                           //     (terminated)
		.pcs_waitrequest_23 (1'b0)                                        //     (terminated)
	);

	altera_eth_tse_pcs_pma_phyip #(
		.ENABLE_TIMESTAMPING (0),
		.DEV_VERSION         (3840),
		.ENABLE_ECC          (0),
		.DEVICE_FAMILY       ("STRATIXV"),
		.SYNCHRONIZER_DEPTH  (3),
		.ENABLE_CLK_SHARING  (0),
		.ENABLE_SGMII        (1),
		.PHY_IDENTIFIER      (0)
	) i_tse_pcs_0 (
		.clk                   (clk),                                                 // control_port_clock_connection.clk
		.reset                 (reset),                                               //              reset_connection.reset
		.reg_addr              (avalon_arbiter_av_pcs_master_0_address),              //                  control_port.address
		.reg_data_out          (avalon_arbiter_av_pcs_master_0_readdata),             //                              .readdata
		.reg_rd                (avalon_arbiter_av_pcs_master_0_read),                 //                              .read
		.reg_data_in           (avalon_arbiter_av_pcs_master_0_writedata),            //                              .writedata
		.reg_wr                (avalon_arbiter_av_pcs_master_0_write),                //                              .write
		.reg_busy              (avalon_arbiter_av_pcs_master_0_waitrequest),          //                              .waitrequest
		.ref_clk               (ref_clk),                                             //  pcs_ref_clk_clock_connection.clk
		.rx_pcs_clk            (i_custom_phyip_0_rx_clkout_export),                   //                    rx_pcs_clk.export
		.sd_loopback           (i_tse_pcs_0_sd_loopback_export),                      //                   sd_loopback.export
		.rx_disp_err           (i_custom_phyip_0_rx_disperr_export),                  //                   rx_disp_err.export
		.tx_pcs_clk            (i_custom_phyip_0_tx_clkout_export),                   //                    tx_pcs_clk.export
		.rx_runningdisp        (i_custom_phyip_0_rx_runningdisp_export),              //                rx_runningdisp.export
		.rx_frame              (i_custom_phyip_0_rx_parallel_data_export),            //                      rx_frame.export
		.rx_runlengthviolation (i_custom_phyip_0_rx_rlv_export),                      //         rx_runlengthviolation.export
		.rx_char_err_gx        (i_custom_phyip_0_rx_errdetect_export),                //                rx_char_err_gx.export
		.tx_frame              (i_tse_pcs_0_tx_frame_export),                         //                      tx_frame.export
		.rx_patterndetect      (i_custom_phyip_0_rx_patterndetect_export),            //              rx_patterndetect.export
		.rx_kchar              (i_custom_phyip_0_rx_datak_export),                    //                      rx_kchar.export
		.rx_syncstatus         (i_custom_phyip_0_rx_syncstatus_export),               //                 rx_syncstatus.export
		.tx_kchar              (i_tse_pcs_0_tx_kchar_export),                         //                      tx_kchar.export
		.tx_clkena             (i_tse_pcs_0_clock_enable_connection_tx_clkena),       //       clock_enable_connection.tx_clkena
		.rx_clkena             (i_tse_pcs_0_clock_enable_connection_rx_clkena),       //                              .rx_clkena
		.gmii_rx_dv            (i_tse_pcs_0_gmii_connection_gmii_rx_dv),              //               gmii_connection.gmii_rx_dv
		.gmii_rx_d             (i_tse_pcs_0_gmii_connection_gmii_rx_d),               //                              .gmii_rx_d
		.gmii_rx_err           (i_tse_pcs_0_gmii_connection_gmii_rx_err),             //                              .gmii_rx_err
		.gmii_tx_en            (i_tse_mac_mac_gmii_connection_gmii_tx_en),            //                              .gmii_tx_en
		.gmii_tx_d             (i_tse_mac_mac_gmii_connection_gmii_tx_d),             //                              .gmii_tx_d
		.gmii_tx_err           (i_tse_mac_mac_gmii_connection_gmii_tx_err),           //                              .gmii_tx_err
		.mii_rx_dv             (i_tse_pcs_0_mii_connection_mii_rx_dv),                //                mii_connection.mii_rx_dv
		.mii_rx_d              (i_tse_pcs_0_mii_connection_mii_rx_d),                 //                              .mii_rx_d
		.mii_rx_err            (i_tse_pcs_0_mii_connection_mii_rx_err),               //                              .mii_rx_err
		.mii_tx_en             (i_tse_mac_mac_mii_connection_mii_tx_en),              //                              .mii_tx_en
		.mii_tx_d              (i_tse_mac_mac_mii_connection_mii_tx_d),               //                              .mii_tx_d
		.mii_tx_err            (i_tse_mac_mac_mii_connection_mii_tx_err),             //                              .mii_tx_err
		.mii_col               (i_tse_pcs_0_mii_connection_mii_col),                  //                              .mii_col
		.mii_crs               (i_tse_pcs_0_mii_connection_mii_crs),                  //                              .mii_crs
		.set_10                (i_tse_pcs_0_sgmii_status_connection_set_10),          //       sgmii_status_connection.set_10
		.set_1000              (i_tse_pcs_0_sgmii_status_connection_set_1000),        //                              .set_1000
		.tx_clk                (i_tse_pcs_0_pcs_transmit_clock_connection_clk),       // pcs_transmit_clock_connection.clk
		.rx_clk                (i_tse_pcs_0_pcs_receive_clock_connection_clk),        //  pcs_receive_clock_connection.clk
		.reset_tx_clk          (rst_controller_reset_out_reset),                      // pcs_transmit_reset_connection.reset
		.reset_rx_clk          (rst_controller_001_reset_out_reset),                  //  pcs_receive_reset_connection.reset
		.led_crs               (led_crs),                                             //         status_led_connection.export
		.led_link              (led_link),                                            //                              .export
		.led_panel_link        (led_panel_link),                                      //                              .export
		.led_col               (led_col),                                             //                              .export
		.led_an                (led_an),                                              //                              .export
		.led_char_err          (led_char_err),                                        //                              .export
		.led_disp_err          (led_disp_err),                                        //                              .export
		.wa_boundary           (i_custom_phyip_0_rx_bitslipboundaryselectout_export), //                   wa_boundary.export
		.rx_rmfifodatadeleted  (1'b0),                                                //                   (terminated)
		.rx_rmfifodatainserted (1'b0),                                                //                   (terminated)
		.set_100               (),                                                    //                   (terminated)
		.hd_ena                (),                                                    //                   (terminated)
		.pcs_phase_measure_clk (1'b0),                                                //                   (terminated)
		.rx_latency_adj        (),                                                    //                   (terminated)
		.tx_latency_adj        (),                                                    //                   (terminated)
		.tx_ptp_alignment      (),                                                    //                   (terminated)
		.pcs_eccstatus         ()                                                     //                   (terminated)
	);

	altera_xcvr_custom #(
		.device_family                         ("Stratix V"),
		.protocol_hint                         ("gige"),
		.operation_mode                        ("Duplex"),
		.lanes                                 (1),
		.bonded_group_size                     (1),
		.bonded_mode                           ("xN"),
		.pma_bonding_mode                      ("x1"),
		.pcs_pma_width                         (10),
		.ser_base_factor                       (8),
		.ser_words                             (1),
		.data_rate                             ("1250 Mbps"),
		.base_data_rate                        ("2500 Mbps"),
		.en_synce_support                      (0),
		.tx_bitslip_enable                     ("false"),
		.rx_use_coreclk                        ("false"),
		.tx_use_coreclk                        ("false"),
		.use_8b10b                             ("true"),
		.use_8b10b_manual_control              ("false"),
		.std_tx_pcfifo_mode                    ("low_latency"),
		.std_rx_pcfifo_mode                    ("low_latency"),
		.word_aligner_mode                     ("sync_state_machine"),
		.word_aligner_state_machine_datacnt    (3),
		.word_aligner_state_machine_errcnt     (4),
		.word_aligner_state_machine_patterncnt (4),
		.word_aligner_pattern_length           (7),
		.word_align_pattern                    ("1111100"),
		.run_length_violation_checking         (5),
		.use_rate_match_fifo                   (0),
		.rate_match_pattern1                   ("11010000111010000011"),
		.rate_match_pattern2                   ("00101111000101111100"),
		.byte_order_mode                       ("none"),
		.byte_order_pattern                    ("111111011"),
		.byte_order_pad_pattern                ("000000000"),
		.coreclk_0ppm_enable                   ("false"),
		.pll_refclk_cnt                        (1),
		.pll_refclk_freq                       ("125.0 MHz"),
		.pll_refclk_select                     ("0"),
		.cdr_refclk_select                     (0),
		.plls                                  (1),
		.pll_type                              ("ATX"),
		.pll_select                            (0),
		.pll_reconfig                          (0),
		.pll_external_enable                   (0),
		.gxb_analog_power                      ("AUTO"),
		.pll_lock_speed                        ("AUTO"),
		.tx_analog_power                       ("AUTO"),
		.tx_slew_rate                          ("OFF"),
		.tx_termination                        ("OCT_100_OHMS"),
		.tx_use_external_termination           ("false"),
		.tx_preemp_pretap                      (0),
		.tx_preemp_pretap_inv                  ("false"),
		.tx_preemp_tap_1                       (0),
		.tx_preemp_tap_2                       (0),
		.tx_preemp_tap_2_inv                   ("false"),
		.tx_vod_selection                      (2),
		.tx_common_mode                        ("0.65V"),
		.rx_pll_lock_speed                     ("AUTO"),
		.rx_common_mode                        ("0.82V"),
		.rx_termination                        ("OCT_100_OHMS"),
		.rx_use_external_termination           ("false"),
		.rx_eq_dc_gain                         (1),
		.rx_eq_ctrl                            (16),
		.mgmt_clk_in_mhz                       (250),
		.embedded_reset                        (1),
		.channel_interface                     (0)
	) i_custom_phyip_0 (
		.phy_mgmt_clk                (clk),                                                    //                phy_mgmt_clk.clk
		.phy_mgmt_clk_reset          (reset),                                                  //          phy_mgmt_clk_reset.reset
		.phy_mgmt_address            (i_phyip_terminator_0_av_dummy_master_address),           //                    phy_mgmt.address
		.phy_mgmt_read               (i_phyip_terminator_0_av_dummy_master_read),              //                            .read
		.phy_mgmt_readdata           (i_phyip_terminator_0_av_dummy_master_readdata),          //                            .readdata
		.phy_mgmt_waitrequest        (i_phyip_terminator_0_av_dummy_master_waitrequest),       //                            .waitrequest
		.phy_mgmt_write              (i_phyip_terminator_0_av_dummy_master_write),             //                            .write
		.phy_mgmt_writedata          (i_phyip_terminator_0_av_dummy_master_writedata),         //                            .writedata
		.tx_ready                    (i_custom_phyip_0_tx_ready_export),                       //                    tx_ready.export
		.rx_ready                    (i_custom_phyip_0_rx_ready_export),                       //                    rx_ready.export
		.pll_ref_clk                 (ref_clk),                                                //                 pll_ref_clk.clk
		.tx_serial_data              (i_custom_phyip_0_tx_serial_data_export),                 //              tx_serial_data.export
		.pll_locked                  (i_custom_phyip_0_pll_locked_export),                     //                  pll_locked.export
		.rx_serial_data              (i_phyip_terminator_0_rx_serial_data_export),             //              rx_serial_data.export
		.rx_runningdisp              (i_custom_phyip_0_rx_runningdisp_export),                 //              rx_runningdisp.export
		.rx_disperr                  (i_custom_phyip_0_rx_disperr_export),                     //                  rx_disperr.export
		.rx_errdetect                (i_custom_phyip_0_rx_errdetect_export),                   //                rx_errdetect.export
		.rx_patterndetect            (i_custom_phyip_0_rx_patterndetect_export),               //            rx_patterndetect.export
		.rx_syncstatus               (i_custom_phyip_0_rx_syncstatus_export),                  //               rx_syncstatus.export
		.rx_bitslipboundaryselectout (i_custom_phyip_0_rx_bitslipboundaryselectout_export),    // rx_bitslipboundaryselectout.export
		.rx_rlv                      (i_custom_phyip_0_rx_rlv_export),                         //                      rx_rlv.export
		.rx_recovered_clk            (i_custom_phyip_0_rx_recovered_clk_export),               //            rx_recovered_clk.export
		.tx_clkout                   (i_custom_phyip_0_tx_clkout_export),                      //                   tx_clkout.export
		.rx_clkout                   (i_custom_phyip_0_rx_clkout_export),                      //                   rx_clkout.export
		.tx_parallel_data            (i_tse_pcs_0_tx_frame_export),                            //            tx_parallel_data.export
		.tx_datak                    (i_tse_pcs_0_tx_kchar_export),                            //                    tx_datak.export
		.rx_parallel_data            (i_custom_phyip_0_rx_parallel_data_export),               //            rx_parallel_data.export
		.rx_datak                    (i_custom_phyip_0_rx_datak_export),                       //                    rx_datak.export
		.reconfig_from_xcvr          (i_custom_phyip_0_reconfig_from_xcvr_reconfig_from_xcvr), //          reconfig_from_xcvr.reconfig_from_xcvr
		.reconfig_to_xcvr            (i_phyip_terminator_0_reconfig_to_xcvr_reconfig_to_xcvr), //            reconfig_to_xcvr.reconfig_to_xcvr
		.tx_forceelecidle            (1'b0),                                                   //                 (terminated)
		.tx_bitslipboundaryselect    (5'b00000),                                               //                 (terminated)
		.rx_is_lockedtoref           (),                                                       //                 (terminated)
		.rx_is_lockedtodata          (),                                                       //                 (terminated)
		.rx_signaldetect             (),                                                       //                 (terminated)
		.rx_enabyteord               (1'b0),                                                   //                 (terminated)
		.rx_bitslip                  (1'b0),                                                   //                 (terminated)
		.rx_rmfifodatainserted       (),                                                       //                 (terminated)
		.rx_rmfifodatadeleted        (),                                                       //                 (terminated)
		.rx_byteordflag              (),                                                       //                 (terminated)
		.tx_coreclkin                (1'b0),                                                   //                 (terminated)
		.rx_coreclkin                (1'b0),                                                   //                 (terminated)
		.cdr_ref_clk                 (1'b0),                                                   //                 (terminated)
		.tx_dispval                  (1'b0),                                                   //                 (terminated)
		.tx_forcedisp                (1'b0),                                                   //                 (terminated)
		.pll_powerdown               (1'b0),                                                   //                 (terminated)
		.tx_digitalreset             (1'b0),                                                   //                 (terminated)
		.tx_analogreset              (1'b0),                                                   //                 (terminated)
		.tx_cal_busy                 (),                                                       //                 (terminated)
		.rx_digitalreset             (1'b0),                                                   //                 (terminated)
		.rx_analogreset              (1'b0),                                                   //                 (terminated)
		.rx_cal_busy                 (),                                                       //                 (terminated)
		.ext_pll_clk                 (1'b0)                                                    //                 (terminated)
	);

	altera_eth_tse_phyip_terminator #(
		.RECONFIG_TO_WIDTH   (140),
		.RECONFIG_FROM_WIDTH (92),
		.ENABLE_TIMESTAMPING (0)
	) i_phyip_terminator_0 (
		.clk                        (clk),                                                    //                       clk.clk
		.reset                      (reset),                                                  //                     reset.reset
		.address                    (i_phyip_terminator_0_av_dummy_master_address),           //           av_dummy_master.address
		.readdata                   (i_phyip_terminator_0_av_dummy_master_readdata),          //                          .readdata
		.read                       (i_phyip_terminator_0_av_dummy_master_read),              //                          .read
		.writedata                  (i_phyip_terminator_0_av_dummy_master_writedata),         //                          .writedata
		.write                      (i_phyip_terminator_0_av_dummy_master_write),             //                          .write
		.waitrequest                (i_phyip_terminator_0_av_dummy_master_waitrequest),       //                          .waitrequest
		.rxp                        (rxp),                                                    //         serial_connection.export
		.txp                        (txp),                                                    //                          .export
		.rx_recovclkout             (rx_recovclkout),                                         // serdes_control_connection.export
		.reconfig_togxb             (reconfig_togxb),                                         //                          .export
		.reconfig_fromgxb           (reconfig_fromgxb),                                       //                          .export
		.tx_ready                   (i_custom_phyip_0_tx_ready_export),                       //                  tx_ready.export
		.tx_serial_data             (i_custom_phyip_0_tx_serial_data_export),                 //            tx_serial_data.export
		.sd_loopback                (i_tse_pcs_0_sd_loopback_export),                         //               sd_loopback.export
		.rx_recovered_clk           (i_custom_phyip_0_rx_recovered_clk_export),               //          rx_recovered_clk.export
		.pll_locked                 (i_custom_phyip_0_pll_locked_export),                     //                pll_locked.export
		.rx_ready                   (i_custom_phyip_0_rx_ready_export),                       //                  rx_ready.export
		.rx_serial_data             (i_phyip_terminator_0_rx_serial_data_export),             //            rx_serial_data.export
		.reconfig_to_xcvr           (i_phyip_terminator_0_reconfig_to_xcvr_reconfig_to_xcvr), //          reconfig_to_xcvr.reconfig_to_xcvr
		.reconfig_from_xcvr         (i_custom_phyip_0_reconfig_from_xcvr_reconfig_from_xcvr), //        reconfig_from_xcvr.reconfig_from_xcvr
		.cdr_ref_clk_out            (),                                                       //               (terminated)
		.cdr_ref_clk_in             (1'b0),                                                   //               (terminated)
		.terminate_rx_recovered_clk (1'b0)                                                    //               (terminated)
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (reset),                                         // reset_in0.reset
		.clk            (i_tse_pcs_0_pcs_transmit_clock_connection_clk), //       clk.clk
		.reset_out      (rst_controller_reset_out_reset),                // reset_out.reset
		.reset_req      (),                                              // (terminated)
		.reset_req_in0  (1'b0),                                          // (terminated)
		.reset_in1      (1'b0),                                          // (terminated)
		.reset_req_in1  (1'b0),                                          // (terminated)
		.reset_in2      (1'b0),                                          // (terminated)
		.reset_req_in2  (1'b0),                                          // (terminated)
		.reset_in3      (1'b0),                                          // (terminated)
		.reset_req_in3  (1'b0),                                          // (terminated)
		.reset_in4      (1'b0),                                          // (terminated)
		.reset_req_in4  (1'b0),                                          // (terminated)
		.reset_in5      (1'b0),                                          // (terminated)
		.reset_req_in5  (1'b0),                                          // (terminated)
		.reset_in6      (1'b0),                                          // (terminated)
		.reset_req_in6  (1'b0),                                          // (terminated)
		.reset_in7      (1'b0),                                          // (terminated)
		.reset_req_in7  (1'b0),                                          // (terminated)
		.reset_in8      (1'b0),                                          // (terminated)
		.reset_req_in8  (1'b0),                                          // (terminated)
		.reset_in9      (1'b0),                                          // (terminated)
		.reset_req_in9  (1'b0),                                          // (terminated)
		.reset_in10     (1'b0),                                          // (terminated)
		.reset_req_in10 (1'b0),                                          // (terminated)
		.reset_in11     (1'b0),                                          // (terminated)
		.reset_req_in11 (1'b0),                                          // (terminated)
		.reset_in12     (1'b0),                                          // (terminated)
		.reset_req_in12 (1'b0),                                          // (terminated)
		.reset_in13     (1'b0),                                          // (terminated)
		.reset_req_in13 (1'b0),                                          // (terminated)
		.reset_in14     (1'b0),                                          // (terminated)
		.reset_req_in14 (1'b0),                                          // (terminated)
		.reset_in15     (1'b0),                                          // (terminated)
		.reset_req_in15 (1'b0)                                           // (terminated)
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_001 (
		.reset_in0      (reset),                                        // reset_in0.reset
		.clk            (i_tse_pcs_0_pcs_receive_clock_connection_clk), //       clk.clk
		.reset_out      (rst_controller_001_reset_out_reset),           // reset_out.reset
		.reset_req      (),                                             // (terminated)
		.reset_req_in0  (1'b0),                                         // (terminated)
		.reset_in1      (1'b0),                                         // (terminated)
		.reset_req_in1  (1'b0),                                         // (terminated)
		.reset_in2      (1'b0),                                         // (terminated)
		.reset_req_in2  (1'b0),                                         // (terminated)
		.reset_in3      (1'b0),                                         // (terminated)
		.reset_req_in3  (1'b0),                                         // (terminated)
		.reset_in4      (1'b0),                                         // (terminated)
		.reset_req_in4  (1'b0),                                         // (terminated)
		.reset_in5      (1'b0),                                         // (terminated)
		.reset_req_in5  (1'b0),                                         // (terminated)
		.reset_in6      (1'b0),                                         // (terminated)
		.reset_req_in6  (1'b0),                                         // (terminated)
		.reset_in7      (1'b0),                                         // (terminated)
		.reset_req_in7  (1'b0),                                         // (terminated)
		.reset_in8      (1'b0),                                         // (terminated)
		.reset_req_in8  (1'b0),                                         // (terminated)
		.reset_in9      (1'b0),                                         // (terminated)
		.reset_req_in9  (1'b0),                                         // (terminated)
		.reset_in10     (1'b0),                                         // (terminated)
		.reset_req_in10 (1'b0),                                         // (terminated)
		.reset_in11     (1'b0),                                         // (terminated)
		.reset_req_in11 (1'b0),                                         // (terminated)
		.reset_in12     (1'b0),                                         // (terminated)
		.reset_req_in12 (1'b0),                                         // (terminated)
		.reset_in13     (1'b0),                                         // (terminated)
		.reset_req_in13 (1'b0),                                         // (terminated)
		.reset_in14     (1'b0),                                         // (terminated)
		.reset_req_in14 (1'b0),                                         // (terminated)
		.reset_in15     (1'b0),                                         // (terminated)
		.reset_req_in15 (1'b0)                                          // (terminated)
	);

endmodule