module transceiver_bank(
    input         mgmt_clk,
    input   [1:0] powerup_channel,

    input         preemp_0p0,
    input         preemp_3p5,
    input         preemp_6p0,
           
    input         swing_0p4,
    input         swing_0p6,
    input         swing_0p8,

    output  [1:0] tx_running,

    input         refclk0,
    input         refclk1,

    output        tx_symbol_clk,
    input  [79:0] tx_symbols,
           
    output  [1:0] gtptx_p,
    output  [1:0] gtptx_n
);

    reg  [1:0] ref_clk_fabric;
    wire       pll0lock;
    reg        resetsel;
    reg  [4:0] preemp_level;
    reg  [3:0] swing_level;

    localparam PLL0_FBDIV_IN      = 4;
    localparam PLL1_FBDIV_IN      = 1;
    localparam PLL0_FBDIV_45_IN   = 5;
    localparam PLL1_FBDIV_45_IN   = 4;
    localparam PLL0_REFCLK_DIV_IN = 1;
    localparam PLL1_REFCLK_DIV_IN = 1;
                   
    
    wire       pll0clk;
    wire       pll0refclk;
    wire       pll1clk;
    wire       pll1refclk;

    wire [1:0] txusrclk;
    wire [1:0] txusrclk2;


    wire [1:0] tx_out_clk;
    wire [1:0] pll_pd;
    wire [1:0] pll_reset;
    wire [1:0] pll_locken;
    wire       tx_symbol_clk_i;

    assign tx_symbol_clk = tx_symbol_clk_i;

    wire  [7:0] ignore_dmonitorout;
    wire [15:0] ignore_drpdo;
    wire        ignore_drprdy;
    wire        ignore_pll0fbclklost;
    wire        ignore_pll0refclklost;
    wire        ignore_pll1fbclklost;
    wire        ignore_pll1lock;
    wire        ignore_pll1refclklost;
    wire        ignore_refclkoutmonitor0;
    wire        ignore_refclkoutmonitor1;
    wire [15:0] ignore_pmarsvdout;

BUFG i_bufg(
    .I (tx_out_clk[0]),
    .O (tx_symbol_clk_i)
);

always @(*) begin    
    if(preemp_6p0  == 1'b1) begin
        preemp_level <= 5'b10100;   // +6.0 db
    end else if(preemp_3p5 == 1'b1) begin
        preemp_level <= 5'b01101;   // +3.5 db; 
    end else begin
        preemp_level <= 5'b00000;   // +0.0 db
    end
    
    if(swing_0p8 == 1'b1) begin
        swing_level  <= 4'b1000;      // 0.8 V  
    end else if(swing_0p6 == 1'b1) begin
        swing_level  <= 4'b0101;      // 0.6 V
    end else begin
        swing_level  <= 4'b0010;      // 0.4 V    
    end
end
  
  
GTPE2_COMMON #(
        .PLL0_FBDIV           (PLL0_FBDIV_IN),	
        .PLL0_FBDIV_45        (PLL0_FBDIV_45_IN),	
        .PLL0_REFCLK_DIV      (PLL0_REFCLK_DIV_IN),	
        .PLL1_FBDIV           (PLL1_FBDIV_IN),
        .PLL1_FBDIV_45        (PLL1_FBDIV_45_IN),	
        .PLL1_REFCLK_DIV      (PLL1_REFCLK_DIV_IN),	            


       //----------------COMMON BLOCK Attributes---------------
        .BIAS_CFG                                (64'h0000000000050001),
        .COMMON_CFG                              (32'h00000000),

       //--------------------------PLL Attributes----------------------------
        .PLL0_CFG                                (28'h01F03DC),
        .PLL0_DMON_CFG                           (1'b0),
        .PLL0_INIT_CFG                           (24'h00001E),
        .PLL0_LOCK_CFG                           (12'h1E8),
        .PLL1_CFG                                (28'h01F03DC),
        .PLL1_DMON_CFG                           (1'b0),
        .PLL1_INIT_CFG                           (24'h00001E),
        .PLL1_LOCK_CFG                           (12'h1E8),
        .PLL_CLKOUT_CFG                          (8'h00),

        //---------------------------Reserved Attributes----------------------------
        .RSVD_ATTR0                              (16'h0000),
        .RSVD_ATTR1                              (16'h0000))
    i_gtpe2_common
    (
        .DMONITOROUT                     (ignore_dmonitorout),	
        //----------- Common Block  - Dynamic Reconfiguration Port (DRP) -----------
        .DRPADDR                         (8'b00000000),
        .DRPCLK                          (1'b0),
        .DRPDI                           (16'h0000),
        .DRPDO                           (ignore_drpdo),
        .DRPEN                           (1'b0),
        .DRPRDY                          (ignore_drprdy),
        .DRPWE                           (1'b0),
        //--------------- Common Block - GTPE2_COMMON Clocking Ports ---------------
        .GTEASTREFCLK0                   (1'b0),
        .GTEASTREFCLK1                   (1'b0),
        .GTGREFCLK1                      (1'b0),
        .GTREFCLK0                       (refclk0),
        .GTREFCLK1                       (refclk1),
        .GTWESTREFCLK0                   (1'b0),
        .GTWESTREFCLK1                   (1'b0),
        .PLL0OUTCLK                      (pll0clk),
        .PLL0OUTREFCLK                   (pll0refclk),
        .PLL1OUTCLK                      (pll1clk),
        .PLL1OUTREFCLK                   (pll1refclk),
        //------------------------ Common Block - PLL Ports ------------------------
        .PLL0FBCLKLOST                   (ignore_pll0fbclklost),
        .PLL0LOCK                        (pll0lock),
        .PLL0LOCKDETCLK                  (mgmt_clk),
        .PLL0LOCKEN                      (1'b1),
        .PLL0PD                          (pll_pd[0]),
        .PLL0REFCLKLOST                  (ignore_pll0refclklost),
        .PLL0REFCLKSEL                   (3'b001),  // ref clock 0
        .PLL0RESET                       (pll_reset[0]),
        .PLL1FBCLKLOST                   (ignore_pll1fbclklost),
        .PLL1LOCK                        (ignore_pll1lock),
        .PLL1LOCKDETCLK                  (1'b0),
        .PLL1LOCKEN                      (1'b1),
        .PLL1PD                          (1'b1),
        .PLL1REFCLKLOST                  (ignore_pll1refclklost),
        .PLL1REFCLKSEL                   (3'b001),
        .PLL1RESET                       (1'b0),
        //-------------------------- Common Block - Ports --------------------------
        .BGRCALOVRDENB                   (1'b1),
        .GTGREFCLK0                      (1'b0),
        .PLLRSVD1                        (16'b0000000000000000),
        .PLLRSVD2                        (5'b00000),
        .REFCLKOUTMONITOR0               (ignore_refclkoutmonitor0),
        .REFCLKOUTMONITOR1               (ignore_refclkoutmonitor1),
         //---------------------- Common Block - RX AFE Ports -----------------------
        .PMARSVDOUT                      (ignore_pmarsvdout),
         //------------------------------- QPLL Ports -------------------------------
        .BGBYPASSB                       (1'b1),
        .BGMONITORENB                    (1'b1),
        .BGPDB                           (1'b1),
        .BGRCALOVRD                      (5'b11111),
        .PMARSVD                         (8'b00000000),
        .RCALENB                         (1'b1)
    );


transceiver tx0(
       .mgmt_clk        (mgmt_clk),
       .powerup_channel (powerup_channel[0]),

       .preemp_level    (preemp_level),
       .swing_level     (swing_level),

       .tx_running      (tx_running[0]),

       .pll0clk         (pll0clk),
       .pll0refclk      (pll0refclk),
       .pll1clk         (pll1clk),
       .pll1refclk      (pll1refclk),
       
       .pll_pd          (pll_pd[0]),
       .pll_reset       (pll_reset[0]),
       .pll_locken      (pll_locken[0]),
       .pll_lock        (pll0lock),

       .tx_out_clk      (tx_out_clk[0]),

       .tx_symbol_clk   (tx_symbol_clk_i),
       .tx_symbol       (tx_symbols[19:0]),
    
       .gtptx_p         (gtptx_p[0]),
       .gtptx_n         (gtptx_n[0])
   );

transceiver tx1( 
       .mgmt_clk        (mgmt_clk),
       .powerup_channel (powerup_channel[1]),

       .preemp_level    (preemp_level),
       .swing_level     (swing_level),

       .tx_running      (tx_running[1]),

       .pll0clk         (pll0clk),
       .pll0refclk      (pll0refclk),

       .pll1clk         (pll1clk),
       .pll1refclk      (pll1refclk),

       .pll_pd          (pll_pd[1]),
       .pll_reset       (pll_reset[1]),
       .pll_locken      (pll_locken[1]),
       .pll_lock        (pll0lock),

       .tx_out_clk      (tx_out_clk[1]),
       .tx_symbol_clk   (tx_symbol_clk_i),
       .tx_symbol       (tx_symbols[39:20]),
   
       .gtptx_p         (gtptx_p[1]),
       .gtptx_n         (gtptx_n[1])
   );

endmodule