dakies/OSS_Verilog huggingface dataset:
module spl_pt_mem #(
    parameter DATA_WIDTH = 32,
    parameter ADDR_WIDTH = 8
) (
    input  wire                     clk,
    
    // port 0, read/write
    input  wire                     we0,
	input  wire                     re0, 
    input  wire [ADDR_WIDTH-1:0]    addr0,  
    input  wire [DATA_WIDTH-1:0]    din0,	
    output reg  [DATA_WIDTH-1:0]    dout0,
    
    // port 1, read only
	input  wire                     re1,
    input  wire [ADDR_WIDTH-1:0]    addr1,
    output reg  [DATA_WIDTH-1:0]    dout1    
);


`ifdef VENDOR_XILINX
    (* ram_extract = "yes", ram_style = "block" *)
    reg  [DATA_WIDTH-1:0]         mem[0:2**ADDR_WIDTH-1];
`else
    (* ramstyle = "AUTO, no_rw_check" *) 
    reg  [DATA_WIDTH-1:0]         mem[0:2**ADDR_WIDTH-1];
`endif

    always @(posedge clk) begin
        if (we0)
            mem[addr0] <= din0;  
        
		if (re0)
        	dout0 <= mem[addr0];
			
		if (re1)			
        	dout1 <= mem[addr1];             			
    end    
	
endmodule
module RetimeShiftRegister
#(
    parameter WIDTH = 1,
    parameter STAGES = 1)
(
    input clock,
    input reset,
    input flow,
    input [WIDTH-1:0] in,
    output reg [WIDTH-1:0] out
);
  integer i;
  reg [WIDTH-1:0] sr[0:STAGES]; // Create 'STAGES' number of register, each 'WIDTH' bits wide

   /* synopsys dc_tcl_script_begin
    set_ungroup [current_design] true
    set_flatten true -effort high -phase true -design [current_design]
    set_dont_retime [current_design] false
    set_optimize_registers true -design [current_design]
    */
  always @(posedge clock) begin
    if (reset) begin
      for(i=0; i<STAGES; i=i+1) begin
        sr[i] <= {WIDTH{1'b0}};
      end
    end else begin
      if (flow) begin
        sr[0] <= in;
        for(i=1; i<STAGES; i=i+1) begin
          sr[i] <= sr[i-1];
        end
      end
    end
  end

  always @(*) begin
    out <= sr[STAGES-1];
  end
endmodule
module SRAMVerilogAWS
#(
    parameter WORDS = 1024,
    parameter AWIDTH = 10,
    parameter DWIDTH = 32)
(
    input clk,
    input [AWIDTH-1:0] raddr,
    input [AWIDTH-1:0] waddr,
    input raddrEn,
    input waddrEn,
    input wen,
    input [DWIDTH-1:0] wdata,
    input flow,
    output reg [DWIDTH-1:0] rdata
);

    reg [DWIDTH-1:0] mem [0:WORDS-1];

    always @(posedge clk) begin
      if (wen) mem[waddr] <= wdata;
      if (flow) rdata <= mem[raddr];
    end

endmodule
module RetimeShiftRegister
#(
    parameter WIDTH = 1,
    parameter STAGES = 1)
(
    input clock,
    input reset,
    input flow,
    input [WIDTH-1:0] in,
    output reg [WIDTH-1:0] out
);
  integer i;
  reg [WIDTH-1:0] sr[0:STAGES-1]; // Create 'STAGES' number of register, each 'WIDTH' bits wide

   /* synopsys dc_tcl_script_begin
    set_ungroup [current_design] true
    set_flatten true -effort high -phase true -design [current_design]
    set_dont_retime [current_design] false
    set_optimize_registers true -design [current_design]
    */
  always @(posedge clock) begin
    if (reset) begin
      for(i=0; i<STAGES; i=i+1) begin
        sr[i] <= {WIDTH{1'b0}};
      end
    end else begin
      if (flow) begin
        sr[0] <= in;
        for(i=1; i<STAGES; i=i+1) begin
          sr[i] <= sr[i-1];
        end
      end
    end
  end

  always @(*) begin
    out <= sr[STAGES-1];
  end
endmodule
module SRAMVerilogSim
#(
    parameter WORDS = 1024,
    parameter AWIDTH = 10,
    parameter DWIDTH = 32)
(
    input clk,
    input [AWIDTH-1:0] raddr,
    input [AWIDTH-1:0] waddr,
    input raddrEn,
    input waddrEn,
    input wen,
    input flow,
    input [DWIDTH-1:0] wdata,
    output reg [DWIDTH-1:0] rdata
);

    reg [DWIDTH-1:0] mem [0:WORDS-1];

    always @(negedge clk) begin
      if (wen) begin
        mem[waddr] <= wdata;
      end
    end

    always @(posedge clk) begin
        if (flow) rdata <= mem[raddr];
    end

endmodule
module SRAMVerilogDE1SoC
#(
    parameter WORDS = 1024,
    parameter AWIDTH = 10,
    parameter DWIDTH = 32)
(
    input clk,
    input [AWIDTH-1:0] raddr,
    input [AWIDTH-1:0] waddr,
    input raddrEn,
    input waddrEn,
    input wen,
    input [DWIDTH-1:0] wdata,
    output reg [DWIDTH-1:0] rdata
);

    reg [DWIDTH-1:0] mem [0:WORDS-1];

    always @(posedge clk) begin
      if (wen) mem[waddr] <= wdata;
      rdata <= mem[raddr];
    end

endmodule
module RetimeShiftRegister
#(
    parameter WIDTH = 1,
    parameter STAGES = 1)
(
    input clock,
    input reset,
    input [WIDTH-1:0] in,
    output reg [WIDTH-1:0] out
);
  integer i;
  reg [WIDTH-1:0] sr[STAGES]; // Create 'STAGES' number of register, each 'WIDTH' bits wide

   /* synopsys dc_tcl_script_begin
    set_ungroup [current_design] true
    set_flatten true -effort high -phase true -design [current_design]
    set_dont_retime [current_design] false
    set_optimize_registers true -design [current_design]
    */
  always @(posedge clock) begin
    if (reset) begin
      for(i=0; i<STAGES; i=i+1) begin
        sr[i] <= {WIDTH{1'b0}};
      end
    end else begin
      sr[0] <= in;
      for(i=1; i<STAGES; i=i+1) begin
        sr[i] <= sr[i-1];
      end
    end
  end

  always @(*) begin
    out <= sr[STAGES-1];
  end
endmodule
module RetimeShiftRegisterBool
#(
    parameter WIDTH = 1,
    parameter STAGES = 1)
(
    input clock,
    input reset,
    input  in,
    output reg out
);
  integer i;
  reg sr[STAGES]; // Create 'STAGES' number of register, each 'WIDTH' bits wide

   /* synopsys dc_tcl_script_begin
    set_ungroup [current_design] true
    set_flatten true -effort high -phase true -design [current_design]
    set_dont_retime [current_design] false
    set_optimize_registers true -design [current_design]
    */
  always @(posedge clock) begin
    if (reset) begin
      for(i=0; i<STAGES; i=i+1) begin
        sr[i] <= {WIDTH{1'b0}};
      end
    end else begin
      sr[0] <= in;
      for(i=1; i<STAGES; i=i+1) begin
        sr[i] <= sr[i-1];
      end
    end
  end

  always @(*) begin
    out <= sr[STAGES-1];
  end
endmodule
module SRAMVerilogSim
#(
    parameter WORDS = 1024,
    parameter AWIDTH = 10,
    parameter DWIDTH = 32)
(
    input clk,
    input [AWIDTH-1:0] raddr,
    input [AWIDTH-1:0] waddr,
    input raddrEn,
    input waddrEn,
    input wen,
    input [DWIDTH-1:0] wdata,
    output reg [DWIDTH-1:0] rdata
);

    reg [DWIDTH-1:0] mem [0:WORDS-1];

    always @(negedge clk) begin
      if (wen) begin
        mem[waddr] <= wdata;
      end
    end

    always @(posedge clk) begin
        rdata <= mem[raddr];
    end

endmodule
module pdo
(
	i, oein, o, obar, oebout, oeout 
);

input i;
input oein;
output o;
output obar;
output wire oebout;
output wire oeout;

twentynm_pseudo_diff_out pdo_wys
(
	.i(i),
	.oein(oein),
	.o(o),
	.oebout(oebout),
	.oeout(oeout),
	.dtc(),
	.dtcbar(),
	.dtcin(),
	.obar(obar)
);

endmodule
module buslvds(
	doutp,
	oe,
	din,
	p,
	n
);


input wire	doutp;
input wire	oe;
output wire	din;
inout wire	p;
inout wire	n;
wire oebout;
wire oeout;

wire	[0:0] SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;
wire	SYNTHESIZED_WIRE_3;





pdo	b2v_inst(
	.i(doutp),
	.oein(oe),
	.o(SYNTHESIZED_WIRE_2),
	.obar(SYNTHESIZED_WIRE_3),
	.oebout(oebout),
	.oeout(oeout));

assign	din = SYNTHESIZED_WIRE_0 & SYNTHESIZED_WIRE_1;

assign	SYNTHESIZED_WIRE_1 =  ~oe;


twentynm_io_obuf	b2v_inst3(
	.i(SYNTHESIZED_WIRE_2),
	.oe(oeout),
	.o(p),
	.obar());


twentynm_io_obuf	b2v_inst4(
	.i(SYNTHESIZED_WIRE_3),
	.oe(oebout),
	.o(n),
	.obar());


diffin	b2v_inst5(
	.datain(p),
	.datain_b(n),
	.dataout(SYNTHESIZED_WIRE_0));


endmodule
module pr_region_default_mm_bridge_0 #(
		parameter DATA_WIDTH        = 32,
		parameter SYMBOL_WIDTH      = 8,
		parameter HDL_ADDR_WIDTH    = 10,
		parameter BURSTCOUNT_WIDTH  = 1,
		parameter PIPELINE_COMMAND  = 1,
		parameter PIPELINE_RESPONSE = 1
	) (
		input  wire                        clk,              //   clk.clk
		input  wire                        m0_waitrequest,   //    m0.waitrequest
		input  wire [DATA_WIDTH-1:0]       m0_readdata,      //      .readdata
		input  wire                        m0_readdatavalid, //      .readdatavalid
		output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount,    //      .burstcount
		output wire [DATA_WIDTH-1:0]       m0_writedata,     //      .writedata
		output wire [HDL_ADDR_WIDTH-1:0]   m0_address,       //      .address
		output wire                        m0_write,         //      .write
		output wire                        m0_read,          //      .read
		output wire [3:0]                  m0_byteenable,    //      .byteenable
		output wire                        m0_debugaccess,   //      .debugaccess
		input  wire                        reset,            // reset.reset
		output wire                        s0_waitrequest,   //    s0.waitrequest
		output wire [DATA_WIDTH-1:0]       s0_readdata,      //      .readdata
		output wire                        s0_readdatavalid, //      .readdatavalid
		input  wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount,    //      .burstcount
		input  wire [DATA_WIDTH-1:0]       s0_writedata,     //      .writedata
		input  wire [HDL_ADDR_WIDTH-1:0]   s0_address,       //      .address
		input  wire                        s0_write,         //      .write
		input  wire                        s0_read,          //      .read
		input  wire [3:0]                  s0_byteenable,    //      .byteenable
		input  wire                        s0_debugaccess    //      .debugaccess
	);
endmodule
module pr_region_default_clock_in (
		input  wire  in_clk,  //  in_clk.clk
		output wire  out_clk  // out_clk.clk
	);
endmodule
module pr_region_default_sysid_qsys_0 (
		input  wire        clock,    //           clk.clk
		output wire [31:0] readdata, // control_slave.readdata
		input  wire        address,  //              .address
		input  wire        reset_n   //         reset.reset_n
	);
endmodule
module pr_region_default_onchip_memory2_0 (
		input  wire        clk,        //   clk1.clk
		input  wire        reset,      // reset1.reset
		input  wire        reset_req,  //       .reset_req
		input  wire [6:0]  address,    //     s1.address
		input  wire        clken,      //       .clken
		input  wire        chipselect, //       .chipselect
		input  wire        write,      //       .write
		output wire [31:0] readdata,   //       .readdata
		input  wire [31:0] writedata,  //       .writedata
		input  wire [3:0]  byteenable  //       .byteenable
	);
endmodule
module pr_region_default_reset_in (
		input  wire  clk,       //       clk.clk
		input  wire  in_reset,  //  in_reset.reset
		output wire  out_reset  // out_reset.reset
	);
endmodule
module pr_region_default_mm_bridge_1 #(
		parameter DATA_WIDTH        = 512,
		parameter SYMBOL_WIDTH      = 8,
		parameter HDL_ADDR_WIDTH    = 32,
		parameter BURSTCOUNT_WIDTH  = 5,
		parameter PIPELINE_COMMAND  = 1,
		parameter PIPELINE_RESPONSE = 1
	) (
		input  wire                        clk,              //   clk.clk
		input  wire                        m0_waitrequest,   //    m0.waitrequest
		input  wire [DATA_WIDTH-1:0]       m0_readdata,      //      .readdata
		input  wire                        m0_readdatavalid, //      .readdatavalid
		output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount,    //      .burstcount
		output wire [DATA_WIDTH-1:0]       m0_writedata,     //      .writedata
		output wire [HDL_ADDR_WIDTH-1:0]   m0_address,       //      .address
		output wire                        m0_write,         //      .write
		output wire                        m0_read,          //      .read
		output wire [63:0]                 m0_byteenable,    //      .byteenable
		output wire                        m0_debugaccess,   //      .debugaccess
		input  wire                        reset,            // reset.reset
		output wire                        s0_waitrequest,   //    s0.waitrequest
		output wire [DATA_WIDTH-1:0]       s0_readdata,      //      .readdata
		output wire                        s0_readdatavalid, //      .readdatavalid
		input  wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount,    //      .burstcount
		input  wire [DATA_WIDTH-1:0]       s0_writedata,     //      .writedata
		input  wire [HDL_ADDR_WIDTH-1:0]   s0_address,       //      .address
		input  wire                        s0_write,         //      .write
		input  wire                        s0_read,          //      .read
		input  wire [63:0]                 s0_byteenable,    //      .byteenable
		input  wire                        s0_debugaccess    //      .debugaccess
	);
endmodule
module pr_region_default_clock_in (
		input  wire  in_clk,  //  in_clk.clk
		output wire  out_clk  // out_clk.clk
	);

	assign out_clk = in_clk;

endmodule
module pr_region_default_sysid_qsys_0 (
		input  wire        clock,    //           clk.clk
		output wire [31:0] readdata, // control_slave.readdata
		input  wire        address,  //              .address
		input  wire        reset_n   //         reset.reset_n
	);

	altera_avalon_sysid_qsys #(
		.ID_VALUE  (-87110914),
		.TIMESTAMP (0)
	) sysid_qsys_0 (
		.clock    (clock),    //   input,   width = 1,           clk.clk
		.reset_n  (reset_n),  //   input,   width = 1,         reset.reset_n
		.readdata (readdata), //  output,  width = 32, control_slave.readdata
		.address  (address)   //   input,   width = 1,              .address
	);

endmodule
module altera_avalon_sysid_qsys #(
    parameter ID_VALUE   = 1,
    parameter TIMESTAMP  = 1
)(
    // inputs:
     address,
     clock,
     reset_n,
    
    // outputs:
     readdata
)
;

  output  [ 31: 0] readdata;
  input            address;
  input            clock;
  input            reset_n;

  wire    [ 31: 0] readdata;
  //control_slave, which is an e_avalon_slave
  assign readdata = address ? TIMESTAMP : ID_VALUE;

endmodule
module pr_region_default_onchip_memory2_0 (
		input  wire        clk,        //   clk1.clk
		input  wire        reset,      // reset1.reset
		input  wire        reset_req,  //       .reset_req
		input  wire [6:0]  address,    //     s1.address
		input  wire        clken,      //       .clken
		input  wire        chipselect, //       .chipselect
		input  wire        write,      //       .write
		output wire [31:0] readdata,   //       .readdata
		input  wire [31:0] writedata,  //       .writedata
		input  wire [3:0]  byteenable  //       .byteenable
	);

	pr_region_default_onchip_memory2_0_altera_avalon_onchip_memory2_171_z7z2goy onchip_memory2_0 (
		.clk        (clk),        //   input,   width = 1,   clk1.clk
		.address    (address),    //   input,   width = 7,     s1.address
		.clken      (clken),      //   input,   width = 1,       .clken
		.chipselect (chipselect), //   input,   width = 1,       .chipselect
		.write      (write),      //   input,   width = 1,       .write
		.readdata   (readdata),   //  output,  width = 32,       .readdata
		.writedata  (writedata),  //   input,  width = 32,       .writedata
		.byteenable (byteenable), //   input,   width = 4,       .byteenable
		.reset      (reset),      //   input,   width = 1, reset1.reset
		.reset_req  (reset_req),  //   input,   width = 1,       .reset_req
		.freeze     (1'b0)        // (terminated),                     
	);

endmodule
module pr_region_default_onchip_memory2_0_altera_avalon_onchip_memory2_171_z7z2goy (
                                                                                     // inputs:
                                                                                      address,
                                                                                      byteenable,
                                                                                      chipselect,
                                                                                      clk,
                                                                                      clken,
                                                                                      freeze,
                                                                                      reset,
                                                                                      reset_req,
                                                                                      write,
                                                                                      writedata,

                                                                                     // outputs:
                                                                                      readdata
                                                                                   )
;

  output  [ 31: 0] readdata;
  input   [  6: 0] address;
  input   [  3: 0] byteenable;
  input            chipselect;
  input            clk;
  input            clken;
  input            freeze;
  input            reset;
  input            reset_req;
  input            write;
  input   [ 31: 0] writedata;


wire             clocken0;
wire    [ 31: 0] readdata;
wire             wren;
  assign wren = chipselect & write;
  assign clocken0 = clken & ~reset_req;
  altsyncram the_altsyncram
    (
      .address_a (address),
      .byteena_a (byteenable),
      .clock0 (clk),
      .clocken0 (clocken0),
      .data_a (writedata),
      .q_a (readdata),
      .wren_a (wren)
    );

  defparam the_altsyncram.byte_size = 8,
           the_altsyncram.init_file = "UNUSED",
           the_altsyncram.lpm_type = "altsyncram",
           the_altsyncram.maximum_depth = 128,
           the_altsyncram.numwords_a = 128,
           the_altsyncram.operation_mode = "SINGLE_PORT",
           the_altsyncram.outdata_reg_a = "UNREGISTERED",
           the_altsyncram.ram_block_type = "AUTO",
           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
           the_altsyncram.read_during_write_mode_port_a = "DONT_CARE",
           the_altsyncram.width_a = 32,
           the_altsyncram.width_byteena_a = 4,
           the_altsyncram.widthad_a = 7;

  //s1, which is an e_avalon_slave
  //s2, which is an e_avalon_slave

endmodule
module pr_region_default_reset_in (
		input  wire  clk,       //       clk.clk
		input  wire  in_reset,  //  in_reset.reset
		output wire  out_reset  // out_reset.reset
	);

	assign out_reset = in_reset;

endmodule
module pr_region_alternate_sysid_qsys_0 (
		input  wire        clock,    //           clk.clk
		output wire [31:0] readdata, // control_slave.readdata
		input  wire        address,  //              .address
		input  wire        reset_n   //         reset.reset_n
	);
endmodule
module pr_region_alternate_mm_bridge_0 #(
		parameter DATA_WIDTH        = 32,
		parameter SYMBOL_WIDTH      = 8,
		parameter HDL_ADDR_WIDTH    = 10,
		parameter BURSTCOUNT_WIDTH  = 1,
		parameter PIPELINE_COMMAND  = 1,
		parameter PIPELINE_RESPONSE = 1
	) (
		input  wire                        clk,              //   clk.clk
		input  wire                        m0_waitrequest,   //    m0.waitrequest
		input  wire [DATA_WIDTH-1:0]       m0_readdata,      //      .readdata
		input  wire                        m0_readdatavalid, //      .readdatavalid
		output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount,    //      .burstcount
		output wire [DATA_WIDTH-1:0]       m0_writedata,     //      .writedata
		output wire [HDL_ADDR_WIDTH-1:0]   m0_address,       //      .address
		output wire                        m0_write,         //      .write
		output wire                        m0_read,          //      .read
		output wire [3:0]                  m0_byteenable,    //      .byteenable
		output wire                        m0_debugaccess,   //      .debugaccess
		input  wire                        reset,            // reset.reset
		output wire                        s0_waitrequest,   //    s0.waitrequest
		output wire [DATA_WIDTH-1:0]       s0_readdata,      //      .readdata
		output wire                        s0_readdatavalid, //      .readdatavalid
		input  wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount,    //      .burstcount
		input  wire [DATA_WIDTH-1:0]       s0_writedata,     //      .writedata
		input  wire [HDL_ADDR_WIDTH-1:0]   s0_address,       //      .address
		input  wire                        s0_write,         //      .write
		input  wire                        s0_read,          //      .read
		input  wire [3:0]                  s0_byteenable,    //      .byteenable
		input  wire                        s0_debugaccess    //      .debugaccess
	);
endmodule
module pr_region_alternate_clock_in (
		input  wire  in_clk,  //  in_clk.clk
		output wire  out_clk  // out_clk.clk
	);
endmodule
module pr_region_alternate_reset_in (
		input  wire  clk,       //       clk.clk
		input  wire  in_reset,  //  in_reset.reset
		output wire  out_reset  // out_reset.reset
	);
endmodule
module pr_region_alternate_sysid_qsys_0 (
		input  wire        clock,    //           clk.clk
		output wire [31:0] readdata, // control_slave.readdata
		input  wire        address,  //              .address
		input  wire        reset_n   //         reset.reset_n
	);

	altera_avalon_sysid_qsys #(
		.ID_VALUE  (-1161889074),
		.TIMESTAMP (0)
	) sysid_qsys_0 (
		.clock    (clock),    //   input,   width = 1,           clk.clk
		.reset_n  (reset_n),  //   input,   width = 1,         reset.reset_n
		.readdata (readdata), //  output,  width = 32, control_slave.readdata
		.address  (address)   //   input,   width = 1,              .address
	);

endmodule
module pr_region_alternate_clock_in (
		input  wire  in_clk,  //  in_clk.clk
		output wire  out_clk  // out_clk.clk
	);

	assign out_clk = in_clk;

endmodule
module pr_region_alternate_reset_in (
		input  wire  clk,       //       clk.clk
		input  wire  in_reset,  //  in_reset.reset
		output wire  out_reset  // out_reset.reset
	);

	assign out_reset = in_reset;

endmodule
module ghrd_10as066n2_avlmm_pr_freeze_bridge_0 (
		input  wire        clock,                               //            clock.clk
		input  wire        freeze_conduit_freeze,               //   freeze_conduit.freeze
		output wire        freeze_conduit_illegal_request,      //                 .illegal_request
		input  wire        reset_n,                             //          reset_n.reset_n
		output wire        slv_bridge_to_pr_read,               // slv_bridge_to_pr.read
		input  wire        slv_bridge_to_pr_waitrequest,        //                 .waitrequest
		output wire        slv_bridge_to_pr_write,              //                 .write
		output wire [9:0]  slv_bridge_to_pr_address,            //                 .address
		output wire [3:0]  slv_bridge_to_pr_byteenable,         //                 .byteenable
		output wire [31:0] slv_bridge_to_pr_writedata,          //                 .writedata
		input  wire [31:0] slv_bridge_to_pr_readdata,           //                 .readdata
		output wire [2:0]  slv_bridge_to_pr_burstcount,         //                 .burstcount
		input  wire        slv_bridge_to_pr_readdatavalid,      //                 .readdatavalid
		output wire        slv_bridge_to_pr_beginbursttransfer, //                 .beginbursttransfer
		output wire        slv_bridge_to_pr_debugaccess,        //                 .debugaccess
		input  wire [1:0]  slv_bridge_to_pr_response,           //                 .response
		output wire        slv_bridge_to_pr_lock,               //                 .lock
		input  wire        slv_bridge_to_pr_writeresponsevalid, //                 .writeresponsevalid
		input  wire        slv_bridge_to_sr_read,               // slv_bridge_to_sr.read
		output wire        slv_bridge_to_sr_waitrequest,        //                 .waitrequest
		input  wire        slv_bridge_to_sr_write,              //                 .write
		input  wire [9:0]  slv_bridge_to_sr_address,            //                 .address
		input  wire [3:0]  slv_bridge_to_sr_byteenable,         //                 .byteenable
		input  wire [31:0] slv_bridge_to_sr_writedata,          //                 .writedata
		output wire [31:0] slv_bridge_to_sr_readdata,           //                 .readdata
		input  wire [2:0]  slv_bridge_to_sr_burstcount,         //                 .burstcount
		output wire        slv_bridge_to_sr_readdatavalid,      //                 .readdatavalid
		input  wire        slv_bridge_to_sr_beginbursttransfer, //                 .beginbursttransfer
		input  wire        slv_bridge_to_sr_debugaccess,        //                 .debugaccess
		output wire [1:0]  slv_bridge_to_sr_response,           //                 .response
		input  wire        slv_bridge_to_sr_lock,               //                 .lock
		output wire        slv_bridge_to_sr_writeresponsevalid  //                 .writeresponsevalid
	);
endmodule
module ghrd_10as066n2_led_pio (
		input  wire        clk,        //                 clk.clk
		input  wire [3:0]  in_port,    // external_connection.in_port
		output wire [3:0]  out_port,   //                    .out_port
		input  wire        reset_n,    //               reset.reset_n
		input  wire [1:0]  address,    //                  s1.address
		input  wire        write_n,    //                    .write_n
		input  wire [31:0] writedata,  //                    .writedata
		input  wire        chipselect, //                    .chipselect
		output wire [31:0] readdata    //                    .readdata
	);
endmodule
module ghrd_10as066n2_clk_0 (
		input  wire  in_clk,  //  in_clk.clk
		output wire  out_clk  // out_clk.clk
	);
endmodule
module ghrd_10as066n2_issp_0 (
		input  wire       source_clk, // source_clk.clk
		output wire [2:0] source      //    sources.source
	);
endmodule
module ghrd_10as066n2_pr_region_controller_0 (
		input  wire        avl_csr_read,                   //        avl_csr.read
		input  wire        avl_csr_write,                  //               .write
		input  wire [1:0]  avl_csr_address,                //               .address
		input  wire [31:0] avl_csr_writedata,              //               .writedata
		output wire [31:0] avl_csr_readdata,               //               .readdata
		output wire        bridge_freeze0_freeze,          // bridge_freeze0.freeze
		input  wire        bridge_freeze0_illegal_request, //               .illegal_request
		output wire        bridge_freeze1_freeze,          // bridge_freeze1.freeze
		input  wire        bridge_freeze1_illegal_request, //               .illegal_request
		input  wire        clock_clk,                      //          clock.clk
		output wire        pr_handshake_start_req,         //   pr_handshake.start_req
		input  wire        pr_handshake_start_ack,         //               .start_ack
		output wire        pr_handshake_stop_req,          //               .stop_req
		input  wire        pr_handshake_stop_ack,          //               .stop_ack
		input  wire        reset_reset,                    //          reset.reset
		output wire        reset_source_reset              //   reset_source.reset
	);
endmodule
module ghrd_10as066n2_avlmm_pr_freeze_bridge_1 (
		input  wire        clock,                               //            clock.clk
		input  wire        freeze_conduit_freeze,               //   freeze_conduit.freeze
		output wire        freeze_conduit_illegal_request,      //                 .illegal_request
		input  wire        mst_bridge_to_pr_read,               // mst_bridge_to_pr.read
		output wire        mst_bridge_to_pr_waitrequest,        //                 .waitrequest
		input  wire        mst_bridge_to_pr_write,              //                 .write
		input  wire [31:0] mst_bridge_to_pr_address,            //                 .address
		input  wire [3:0]  mst_bridge_to_pr_byteenable,         //                 .byteenable
		input  wire [31:0] mst_bridge_to_pr_writedata,          //                 .writedata
		output wire [31:0] mst_bridge_to_pr_readdata,           //                 .readdata
		input  wire [2:0]  mst_bridge_to_pr_burstcount,         //                 .burstcount
		output wire        mst_bridge_to_pr_readdatavalid,      //                 .readdatavalid
		input  wire        mst_bridge_to_pr_beginbursttransfer, //                 .beginbursttransfer
		input  wire        mst_bridge_to_pr_debugaccess,        //                 .debugaccess
		output wire [1:0]  mst_bridge_to_pr_response,           //                 .response
		input  wire        mst_bridge_to_pr_lock,               //                 .lock
		output wire        mst_bridge_to_pr_writeresponsevalid, //                 .writeresponsevalid
		output wire        mst_bridge_to_sr_read,               // mst_bridge_to_sr.read
		input  wire        mst_bridge_to_sr_waitrequest,        //                 .waitrequest
		output wire        mst_bridge_to_sr_write,              //                 .write
		output wire [31:0] mst_bridge_to_sr_address,            //                 .address
		output wire [3:0]  mst_bridge_to_sr_byteenable,         //                 .byteenable
		output wire [31:0] mst_bridge_to_sr_writedata,          //                 .writedata
		input  wire [31:0] mst_bridge_to_sr_readdata,           //                 .readdata
		output wire [2:0]  mst_bridge_to_sr_burstcount,         //                 .burstcount
		input  wire        mst_bridge_to_sr_readdatavalid,      //                 .readdatavalid
		output wire        mst_bridge_to_sr_beginbursttransfer, //                 .beginbursttransfer
		output wire        mst_bridge_to_sr_debugaccess,        //                 .debugaccess
		input  wire [1:0]  mst_bridge_to_sr_response,           //                 .response
		output wire        mst_bridge_to_sr_lock,               //                 .lock
		input  wire        mst_bridge_to_sr_writeresponsevalid, //                 .writeresponsevalid
		input  wire        reset_n                              //          reset_n.reset_n
	);
endmodule
module ghrd_10as066n2_emif_hps (
		input  wire          global_reset_n, // global_reset_reset_sink.reset_n
		input  wire [4095:0] hps_to_emif,    //    hps_emif_conduit_end.hps_to_emif
		output wire [4095:0] emif_to_hps,    //                        .emif_to_hps
		input  wire [1:0]    hps_to_emif_gp, //                        .gp_to_emif
		output wire [0:0]    emif_to_hps_gp, //                        .emif_to_gp
		output wire [0:0]    mem_ck,         //         mem_conduit_end.mem_ck
		output wire [0:0]    mem_ck_n,       //                        .mem_ck_n
		output wire [16:0]   mem_a,          //                        .mem_a
		output wire [0:0]    mem_act_n,      //                        .mem_act_n
		output wire [1:0]    mem_ba,         //                        .mem_ba
		output wire [0:0]    mem_bg,         //                        .mem_bg
		output wire [0:0]    mem_cke,        //                        .mem_cke
		output wire [0:0]    mem_cs_n,       //                        .mem_cs_n
		output wire [0:0]    mem_odt,        //                        .mem_odt
		output wire [0:0]    mem_reset_n,    //                        .mem_reset_n
		output wire [0:0]    mem_par,        //                        .mem_par
		input  wire [0:0]    mem_alert_n,    //                        .mem_alert_n
		inout  wire [3:0]    mem_dqs,        //                        .mem_dqs
		inout  wire [3:0]    mem_dqs_n,      //                        .mem_dqs_n
		inout  wire [31:0]   mem_dq,         //                        .mem_dq
		inout  wire [3:0]    mem_dbi_n,      //                        .mem_dbi_n
		input  wire          oct_rzqin,      //         oct_conduit_end.oct_rzqin
		input  wire          pll_ref_clk     //  pll_ref_clk_clock_sink.clk
	);
endmodule
module ghrd_10as066n2_rst_in (
		input  wire  clk,         //       clk.clk
		input  wire  in_reset_n,  //  in_reset.reset_n
		output wire  out_reset_n  // out_reset.reset_n
	);
endmodule
module ghrd_10as066n2_button_pio (
		input  wire        clk,        //                 clk.clk
		input  wire [3:0]  in_port,    // external_connection.export
		output wire        irq,        //                 irq.irq
		input  wire        reset_n,    //               reset.reset_n
		input  wire [1:0]  address,    //                  s1.address
		input  wire        write_n,    //                    .write_n
		input  wire [31:0] writedata,  //                    .writedata
		input  wire        chipselect, //                    .chipselect
		output wire [31:0] readdata    //                    .readdata
	);
endmodule
module ghrd_10as066n2_f2sdram2_m (
		input  wire        clk_clk,              //          clk.clk
		input  wire        clk_reset_reset,      //    clk_reset.reset
		output wire [31:0] master_address,       //       master.address
		input  wire [31:0] master_readdata,      //             .readdata
		output wire        master_read,          //             .read
		output wire        master_write,         //             .write
		output wire [31:0] master_writedata,     //             .writedata
		input  wire        master_waitrequest,   //             .waitrequest
		input  wire        master_readdatavalid, //             .readdatavalid
		output wire [3:0]  master_byteenable,    //             .byteenable
		output wire        master_reset_reset    // master_reset.reset
	);
endmodule
module ghrd_10as066n2_sys_id (
		input  wire        clock,    //           clk.clk
		output wire [31:0] readdata, // control_slave.readdata
		input  wire        address,  //              .address
		input  wire        reset_n   //         reset.reset_n
	);
endmodule
module ghrd_10as066n2_hps_m (
		input  wire        clk_clk,              //          clk.clk
		input  wire        clk_reset_reset,      //    clk_reset.reset
		output wire [31:0] master_address,       //       master.address
		input  wire [31:0] master_readdata,      //             .readdata
		output wire        master_read,          //             .read
		output wire        master_write,         //             .write
		output wire [31:0] master_writedata,     //             .writedata
		input  wire        master_waitrequest,   //             .waitrequest
		input  wire        master_readdatavalid, //             .readdatavalid
		output wire [3:0]  master_byteenable,    //             .byteenable
		output wire        master_reset_reset    // master_reset.reset
	);
endmodule
module ghrd_10as066n2_fpga_m (
		input  wire        clk_clk,              //          clk.clk
		input  wire        clk_reset_reset,      //    clk_reset.reset
		output wire [31:0] master_address,       //       master.address
		input  wire [31:0] master_readdata,      //             .readdata
		output wire        master_read,          //             .read
		output wire        master_write,         //             .write
		output wire [31:0] master_writedata,     //             .writedata
		input  wire        master_waitrequest,   //             .waitrequest
		input  wire        master_readdatavalid, //             .readdatavalid
		output wire [3:0]  master_byteenable,    //             .byteenable
		output wire        master_reset_reset    // master_reset.reset
	);
endmodule
module ghrd_10as066n2_ocm_0 (
		input  wire        clk,        //   clk1.clk
		input  wire        reset,      // reset1.reset
		input  wire        reset_req,  //       .reset_req
		input  wire [17:0] address,    //     s1.address
		input  wire        clken,      //       .clken
		input  wire        chipselect, //       .chipselect
		input  wire        write,      //       .write
		output wire [7:0]  readdata,   //       .readdata
		input  wire [7:0]  writedata   //       .writedata
	);
endmodule
module ghrd_10as066n2_rst_bdg (
		input  wire  clk,       //       clk.clk
		input  wire  in_reset,  //  in_reset.reset
		output wire  out_reset  // out_reset.reset
	);
endmodule
module ghrd_10as066n2_dipsw_pio (
		input  wire        clk,        //                 clk.clk
		input  wire [3:0]  in_port,    // external_connection.export
		output wire        irq,        //                 irq.irq
		input  wire        reset_n,    //               reset.reset_n
		input  wire [1:0]  address,    //                  s1.address
		input  wire        write_n,    //                    .write_n
		input  wire [31:0] writedata,  //                    .writedata
		input  wire        chipselect, //                    .chipselect
		output wire [31:0] readdata    //                    .readdata
	);
endmodule
module ghrd_10as066n2_pb_lwh2f #(
		parameter DATA_WIDTH        = 32,
		parameter SYMBOL_WIDTH      = 8,
		parameter HDL_ADDR_WIDTH    = 12,
		parameter BURSTCOUNT_WIDTH  = 1,
		parameter PIPELINE_COMMAND  = 1,
		parameter PIPELINE_RESPONSE = 1
	) (
		input  wire                        clk,              //   clk.clk
		input  wire                        m0_waitrequest,   //    m0.waitrequest
		input  wire [DATA_WIDTH-1:0]       m0_readdata,      //      .readdata
		input  wire                        m0_readdatavalid, //      .readdatavalid
		output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount,    //      .burstcount
		output wire [DATA_WIDTH-1:0]       m0_writedata,     //      .writedata
		output wire [HDL_ADDR_WIDTH-1:0]   m0_address,       //      .address
		output wire                        m0_write,         //      .write
		output wire                        m0_read,          //      .read
		output wire [3:0]                  m0_byteenable,    //      .byteenable
		output wire                        m0_debugaccess,   //      .debugaccess
		input  wire                        reset,            // reset.reset
		output wire                        s0_waitrequest,   //    s0.waitrequest
		output wire [DATA_WIDTH-1:0]       s0_readdata,      //      .readdata
		output wire                        s0_readdatavalid, //      .readdatavalid
		input  wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount,    //      .burstcount
		input  wire [DATA_WIDTH-1:0]       s0_writedata,     //      .writedata
		input  wire [HDL_ADDR_WIDTH-1:0]   s0_address,       //      .address
		input  wire                        s0_write,         //      .write
		input  wire                        s0_read,          //      .read
		input  wire [3:0]                  s0_byteenable,    //      .byteenable
		input  wire                        s0_debugaccess    //      .debugaccess
	);
endmodule
module ghrd_10as066n2_ILC (
		input  wire [5:0]  avmm_addr,   // avalon_slave.address
		input  wire [31:0] avmm_wrdata, //             .writedata
		input  wire        avmm_write,  //             .write
		input  wire        avmm_read,   //             .read
		output wire [31:0] avmm_rddata, //             .readdata
		input  wire        clk,         //          clk.clk
		input  wire [1:0]  irq,         //          irq.irq
		input  wire        reset_n      //      reset_n.reset_n
	);
endmodule
module ghrd_10as066n2_f2sdram0_m (
		input  wire        clk_clk,              //          clk.clk
		input  wire        clk_reset_reset,      //    clk_reset.reset
		output wire [31:0] master_address,       //       master.address
		input  wire [31:0] master_readdata,      //             .readdata
		output wire        master_read,          //             .read
		output wire        master_write,         //             .write
		output wire [31:0] master_writedata,     //             .writedata
		input  wire        master_waitrequest,   //             .waitrequest
		input  wire        master_readdatavalid, //             .readdatavalid
		output wire [3:0]  master_byteenable,    //             .byteenable
		output wire        master_reset_reset    // master_reset.reset
	);
endmodule
module ghrd_10as066n2_mm_bridge_0 #(
		parameter DATA_WIDTH        = 512,
		parameter SYMBOL_WIDTH      = 8,
		parameter HDL_ADDR_WIDTH    = 32,
		parameter BURSTCOUNT_WIDTH  = 5,
		parameter PIPELINE_COMMAND  = 1,
		parameter PIPELINE_RESPONSE = 1
	) (
		input  wire                        clk,              //   clk.clk
		input  wire                        m0_waitrequest,   //    m0.waitrequest
		input  wire [DATA_WIDTH-1:0]       m0_readdata,      //      .readdata
		input  wire                        m0_readdatavalid, //      .readdatavalid
		output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount,    //      .burstcount
		output wire [DATA_WIDTH-1:0]       m0_writedata,     //      .writedata
		output wire [HDL_ADDR_WIDTH-1:0]   m0_address,       //      .address
		output wire                        m0_write,         //      .write
		output wire                        m0_read,          //      .read
		output wire [63:0]                 m0_byteenable,    //      .byteenable
		output wire                        m0_debugaccess,   //      .debugaccess
		input  wire                        reset,            // reset.reset
		output wire                        s0_waitrequest,   //    s0.waitrequest
		output wire [DATA_WIDTH-1:0]       s0_readdata,      //      .readdata
		output wire                        s0_readdatavalid, //      .readdatavalid
		input  wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount,    //      .burstcount
		input  wire [DATA_WIDTH-1:0]       s0_writedata,     //      .writedata
		input  wire [HDL_ADDR_WIDTH-1:0]   s0_address,       //      .address
		input  wire                        s0_write,         //      .write
		input  wire                        s0_read,          //      .read
		input  wire [63:0]                 s0_byteenable,    //      .byteenable
		input  wire                        s0_debugaccess    //      .debugaccess
	);
endmodule
module ghrd_10as066n2_led_pio (
		input  wire        clk,        //                 clk.clk
		input  wire [3:0]  in_port,    // external_connection.in_port
		output wire [3:0]  out_port,   //                    .out_port
		input  wire        reset_n,    //               reset.reset_n
		input  wire [1:0]  address,    //                  s1.address
		input  wire        write_n,    //                    .write_n
		input  wire [31:0] writedata,  //                    .writedata
		input  wire        chipselect, //                    .chipselect
		output wire [31:0] readdata    //                    .readdata
	);

	ghrd_10as066n2_led_pio_altera_avalon_pio_171_yz2rppa led_pio (
		.clk        (clk),        //   input,   width = 1,                 clk.clk
		.reset_n    (reset_n),    //   input,   width = 1,               reset.reset_n
		.address    (address),    //   input,   width = 2,                  s1.address
		.write_n    (write_n),    //   input,   width = 1,                    .write_n
		.writedata  (writedata),  //   input,  width = 32,                    .writedata
		.chipselect (chipselect), //   input,   width = 1,                    .chipselect
		.readdata   (readdata),   //  output,  width = 32,                    .readdata
		.in_port    (in_port),    //   input,   width = 4, external_connection.export
		.out_port   (out_port)    //  output,   width = 4,                    .export
	);

endmodule
module ghrd_10as066n2_led_pio_altera_avalon_pio_171_yz2rppa (
                                                              // inputs:
                                                               address,
                                                               chipselect,
                                                               clk,
                                                               in_port,
                                                               reset_n,
                                                               write_n,
                                                               writedata,

                                                              // outputs:
                                                               out_port,
                                                               readdata
                                                            )
;

  output  [  3: 0] out_port;
  output  [ 31: 0] readdata;
  input   [  1: 0] address;
  input            chipselect;
  input            clk;
  input   [  3: 0] in_port;
  input            reset_n;
  input            write_n;
  input   [ 31: 0] writedata;


wire             clk_en;
wire    [  3: 0] data_in;
reg     [  3: 0] data_out;
wire    [  3: 0] out_port;
wire    [  3: 0] read_mux_out;
reg     [ 31: 0] readdata;
  assign clk_en = 1;
  //s1, which is an e_avalon_slave
  assign read_mux_out = {4 {(address == 0)}} & data_in;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          readdata <= 0;
      else if (clk_en)
          readdata <= {32'b0 | read_mux_out};
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_out <= 0;
      else if (chipselect && ~write_n && (address == 0))
          data_out <= writedata[3 : 0];
    end


  assign out_port = data_out;
  assign data_in = in_port;

endmodule
module ghrd_10as066n2_clk_0 (
		input  wire  in_clk,  //  in_clk.clk
		output wire  out_clk  // out_clk.clk
	);

	assign out_clk = in_clk;

endmodule
module ghrd_10as066n2_issp_0 (
		input  wire       source_clk, // source_clk.clk
		output wire [2:0] source      //    sources.source
	);

	altsource_probe_top #(
		.sld_auto_instance_index ("YES"),
		.sld_instance_index      (0),
		.instance_id             ("RST"),
		.probe_width             (0),
		.source_width            (3),
		.source_initial_value    ("0"),
		.enable_metastability    ("YES")
	) issp_0 (
		.source     (source),     //  output,  width = 3,    sources.source
		.source_clk (source_clk), //   input,  width = 1, source_clk.clk
		.source_ena (1'b1)        // (terminated),                        
	);

endmodule
module altsource_probe_top
#(
    parameter lpm_type = "altsource_probe",     // required by the coding standard
    parameter lpm_hint = "UNUSED",              // required by the coding standard 

    parameter sld_auto_instance_index = "YES",  // Yes, if the instance index should be automatically assigned.
    parameter sld_instance_index = 0,           // unique identifier for the altsource_probe instance.
    parameter sld_node_info_parameter = 4746752 + sld_instance_index,   // The NODE ID to uniquely identify this node on the hub.  Type ID: 9 Version: 0 Inst: 0 MFG ID 110 -- ***NOTE*** this parameter cannot be called SLD_NODE_INFO or Quartus Standard will think it's an ISSP impl.
    parameter sld_ir_width = 4,                 
                                        
    parameter instance_id = "UNUSED",           // optional name for the instance.
    parameter probe_width = 1,                  // probe port width
    parameter source_width= 1,                  // source port width
    parameter source_initial_value = "0",       // initial source port value
    parameter enable_metastability = "NO"       // yes to add two register
)
(
    input [probe_width - 1 : 0] probe,       // probe inputs
    output [source_width - 1 : 0] source,    // source outputs
    input source_clk,                        // clock of the registers used to metastabilize the source output
    input tri1 source_ena                    // enable of the registers used to metastabilize the source output
);

    altsource_probe #(
        .lpm_type(lpm_type),
        .lpm_hint(lpm_hint),   
        .sld_auto_instance_index(sld_auto_instance_index),
        .sld_instance_index(sld_instance_index),
        .SLD_NODE_INFO(sld_node_info_parameter),
        .sld_ir_width(sld_ir_width),                          
        .instance_id(instance_id),
        .probe_width(probe_width),
        .source_width(source_width),
        .source_initial_value(source_initial_value),
        .enable_metastability(enable_metastability)
    )issp_impl
    (
        .probe(probe),
        .source(source),
        .source_clk(source_clk),
        .source_ena(source_ena)
    );
    
endmodule
module ghrd_10as066n2_rst_in (
		input  wire  clk,         //       clk.clk
		input  wire  in_reset_n,  //  in_reset.reset_n
		output wire  out_reset_n  // out_reset.reset_n
	);

	assign out_reset_n = in_reset_n;

endmodule