dakies/OSS_Verilog huggingface dataset:
module tri_plat(vd, gd, nclk, flush, din, q);
   parameter                      WIDTH = 1;
   parameter                      OFFSET = 0;
   parameter                      INIT = 0;		// will be converted to the least signficant 31 bits of init_v
   parameter                      SYNTHCLONEDLATCH = "";

   inout                          vd;
   inout                          gd;
   input  [0:`NCLK_WIDTH-1]       nclk;
   input                          flush;
   input  [OFFSET:OFFSET+WIDTH-1] din;
   output [OFFSET:OFFSET+WIDTH-1] q;

   // tri_plat
   reg  [OFFSET:OFFSET+WIDTH-1]  int_dout;

   (* analysis_not_referenced="true" *)
   wire                          unused;
   assign unused = | {vd, gd, nclk[1:`NCLK_WIDTH-1]};


   always @ (posedge nclk[0])
     begin
 	int_dout <= din;
     end

   assign q = (flush == 1'b1) ? din : int_dout ;

endmodule
module tri_csa22(
   a,
   b,
   car,
   sum
);
   input   a;
   input   b;
   output  car;
   output  sum;

   wire    car_b;
   wire    sum_b;

   assign car_b = (~(a & b));
   assign sum_b = (~(car_b & (a | b)));      // this is equiv to an xnor
   assign car = (~car_b);
   assign sum = (~sum_b);

endmodule
module tri_fu_mul_bthmux(
   x,
   sneg,
   sx,
   sx2,
   right,
   left,
   q
);
   input   x;
   input   sneg;		// do not flip the input (add)
   input   sx;		// shift by 1
   input   sx2;		// shift by 2
   input   right;		// bit from the right (lsb)
   output  left;		// bit from the left
   output  q;		// final output

   wire    center;
   wire    q_b;

   assign center = x ^ sneg;

   assign left = center;		//output-- rename, no gate

   assign q_b = (~((sx & center) | (sx2 & right)));

   assign q = (~q_b);		// output--

endmodule
module tri_lcbcntl_array_mac(
   vdd,
   gnd,
   sg,
   nclk,
   scan_in,
   scan_diag_dc,
   thold,
   clkoff_dc_b,
   delay_lclkr_dc,
   act_dis_dc,
   d_mode_dc,
   mpw1_dc_b,
   mpw2_dc_b,
   scan_out
);
   inout        vdd;
   inout        gnd;
   input        sg;
   input [0:`NCLK_WIDTH-1] nclk;
   input        scan_in;
   input        scan_diag_dc;
   input        thold;
   output       clkoff_dc_b;
   output [0:4] delay_lclkr_dc;
   output       act_dis_dc;
   output       d_mode_dc;
   output [0:4] mpw1_dc_b;
   output       mpw2_dc_b;
   output       scan_out;

   // tri_lcbcntl_array_mac

    (* analysis_not_referenced="true" *)
   wire         unused;

   assign clkoff_dc_b = 1'b1;
   assign delay_lclkr_dc = 5'b00000;
   assign act_dis_dc = 1'b0;
   assign d_mode_dc = 1'b0;
   assign mpw1_dc_b = 5'b11111;
   assign mpw2_dc_b = 1'b1;
   assign scan_out = 1'b0;

   assign unused = vdd | gnd | sg | (|nclk) | scan_in | scan_diag_dc | thold;
endmodule
module tri_oai21(
   y,
   a0,
   a1,
   b0
);
   parameter                      WIDTH = 1;
   parameter                      BTR = "OAI21_X2M_NONE";  //Specify full BTR name, else let tool select
   output [0:WIDTH-1]  y;
   input [0:WIDTH-1]   a0;
   input [0:WIDTH-1]   a1;
   input [0:WIDTH-1]   b0;

   // tri_oai21
   genvar 	       i;
   wire [0:WIDTH-1]    outA;

   generate
      begin : t
	 for (i = 0; i < WIDTH; i = i + 1)
	   begin : w

	      or   I0(outA[i], a0[i], a1[i]);
	      nand I2(y[i], outA[i], b0[i]);

	   end // block: w
      end

   endgenerate
endmodule
module tri_st_popcnt_byte(
   b0,
   y,
   vdd,
   gnd
);
   input [0:7]  b0;
   output [0:3] y;
   inout        vdd;
   inout        gnd;

   wire [0:2]   s0;
   wire [0:3]   c1;
   wire [0:0]   s1;
   wire [0:1]   c2;

   // Level 0

   tri_csa32 csa_l0_0(
      .vd(vdd),
      .gd(gnd),
      .a(b0[0]),
      .b(b0[1]),
      .c(b0[2]),
      .sum(s0[0]),
      .car(c1[0])
   );


   tri_csa32 csa_l0_1(
      .vd(vdd),
      .gd(gnd),
      .a(b0[3]),
      .b(b0[4]),
      .c(b0[5]),
      .sum(s0[1]),
      .car(c1[1])
   );


   tri_csa22 csa_l0_2(
      .a(b0[6]),
      .b(b0[7]),
      .sum(s0[2]),
      .car(c1[2])
   );


   tri_csa32 csa_l0_3(
      .vd(vdd),
      .gd(gnd),
      .a(s0[0]),
      .b(s0[1]),
      .c(s0[2]),
      .sum(y[3]),
      .car(c1[3])
   );

   // Level 1

   tri_csa32 csa_l1_0(
      .vd(vdd),
      .gd(gnd),
      .a(c1[0]),
      .b(c1[1]),
      .c(c1[2]),
      .sum(s1[0]),
      .car(c2[0])
   );


   tri_csa22 csa_l1_1(
      .a(c1[3]),
      .b(s1[0]),
      .sum(y[2]),
      .car(c2[1])
   );

   // Level 2/3

   tri_csa22 csa_l2_0(
      .a(c2[0]),
      .b(c2[1]),
      .sum(y[1]),
      .car(y[0])
   );


endmodule
module tri_nlat(
   vd,
   gd,
   d1clk,
   d2clk,
   lclk,
   scan_in,
   din,
   q,
   q_b,
   scan_out
);
   parameter                      OFFSET = 0;
   parameter                      SCAN = 0;                     //SCAN = normal;
                                                                //0=normal,1=interleaved,2=reversed,3=reverse_interleaved
   parameter                      RESET_INVERTS_SCAN = 1'b1;
   parameter                      WIDTH = 1;
   parameter                      INIT = 0;
   parameter                      L2_LATCH_TYPE = 2;            //L2_LATCH_TYPE = slave_latch;
                                                                //0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4
   parameter                      SYNTHCLONEDLATCH = "";
   parameter                      NEEDS_SRESET = 1;		// for inferred latches
   parameter                      DOMAIN_CROSSING = 0;		// 0 - Internal Flop, 1 - Domain Crossing Input Flop (requires extra logic for ASICs)

   inout                          vd;
   inout                          gd;
   input                          d1clk;
   input                          d2clk;
   input [0:`NCLK_WIDTH-1]        lclk;
   input                          scan_in;
   input [OFFSET:OFFSET+WIDTH-1]  din;
   output [OFFSET:OFFSET+WIDTH-1] q;
   output [OFFSET:OFFSET+WIDTH-1] q_b;
   output                         scan_out;

   // tri_nlat

   parameter [0:WIDTH-1]          init_v = INIT;

   generate
   begin
      wire                          sreset;
      wire [0:WIDTH-1]              int_din;
      reg [0:WIDTH-1]               int_dout;
      wire [0:WIDTH-1]              vact;
      wire [0:WIDTH-1]              vact_b;
      wire [0:WIDTH-1]              vsreset;
      wire [0:WIDTH-1]              vsreset_b;
      wire [0:WIDTH-1]              vthold;
      wire [0:WIDTH-1]              vthold_b;
       (* analysis_not_referenced="true" *)
      wire                          unused;

      if (NEEDS_SRESET == 1)
      begin : rst
        assign sreset = lclk[1];
      end
      if (NEEDS_SRESET != 1)
      begin : no_rst
        assign sreset = 1'b0;
      end

      assign vsreset = {WIDTH{sreset}};
      assign vsreset_b = {WIDTH{~sreset}};
      assign int_din = (vsreset_b & din) | (vsreset & init_v);

      assign vact = {WIDTH{d1clk}};
      assign vact_b = {WIDTH{~d1clk}};

      assign vthold_b = {WIDTH{d2clk}};
      assign vthold = {WIDTH{~d2clk}};


      always @(posedge lclk[0])
      begin: l
        int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
      end
      assign q = int_dout;
      assign q_b = (~int_dout);
      assign scan_out = 1'b0;

      assign unused = | {vd, gd, lclk, scan_in};
   end
   endgenerate
endmodule
module tri_nand4(
   y,
   a,
   b,
   c,
   d
);
   parameter                      WIDTH = 1;
   parameter                      BTR = "NAND4_X2M_NONE";  //Specify full BTR name, else let tool select
   output [0:WIDTH-1]  y;
   input [0:WIDTH-1]   a;
   input [0:WIDTH-1]   b;
   input [0:WIDTH-1]   c;
   input [0:WIDTH-1]   d;
   // tri_nand3
   genvar 	       i;

   generate
      begin : t
	 for (i = 0; i < WIDTH; i = i + 1)
	   begin : w

      	      nand I0(y[i], a[i], b[i], c[i], d[i]);


	   end // block: w
      end

   endgenerate
endmodule
module tri_csa42(
   a,
   b,
   c,
   d,
   ki,
   ko,
   car,
   sum,
   vd,
   gd
);
   input   a;
   input   b;
   input   c;
   input   d;
   input   ki;
   output  ko;
   output  car;
   output  sum;
   (* ANALYSIS_NOT_ASSIGNED="TRUE" *)
   (* ANALYSIS_NOT_REFERENCED="TRUE" *)
   inout   vd;
   (* ANALYSIS_NOT_ASSIGNED="TRUE" *)
   (* ANALYSIS_NOT_REFERENCED="TRUE" *)
   inout   gd;

   wire    s1;

   wire    carn1;
   wire    carn2;
   wire    carn3;
   wire    kon1;
   wire    kon2;
   wire    kon3;

//   assign  s1 = b ^ c ^ d;
   tri_xor3 CSA42_XOR3_1(s1,b,c,d);

//   assign sum = s1 ^ a ^ ki;
   tri_xor3 CSA42_XOR3_2(sum,s1,a,ki);

//   assign car = (s1 & a) | (s1 & ki) | (a & ki);
   tri_nand2 CSA42_NAND2_1(carn1,s1,a);
   tri_nand2 CSA42_NAND2_2(carn2,s1,ki);
   tri_nand2 CSA42_NAND2_3(carn3,a,ki);
   tri_nand3 CSA42_NAND3_4(car,carn1,carn2,carn3);

//   assign ko = (b & c) | (b & d) | (c & d);
   tri_nand2 CSA42_NAND2_5(kon1,b,c);
   tri_nand2 CSA42_NAND2_6(kon2,b,d);
   tri_nand2 CSA42_NAND2_7(kon3,c,d);
   tri_nand3 CSA42_NAND3_8(ko,kon1,kon2,kon3);


endmodule
module tri_inv(
   y,
   a
);
   parameter                      WIDTH = 1;
   parameter                      BTR = "INV_X2M_NONE";  //Specify full BTR name, else let tool select
   output [0:WIDTH-1]  y;
   input [0:WIDTH-1]   a;

   // tri_nand2
   genvar 	       i;

   generate
      begin : t
	 for (i = 0; i < WIDTH; i = i + 1)
	   begin : w

	      not I0(y[i], a[i]);

	   end // block: w
      end

   endgenerate
endmodule
module tri_csa32(
   a,
   b,
   c,
   car,
   sum,
   vd,
   gd
);
   input   a;
   input   b;
   input   c;
   output  car;
   output  sum;
   (* ANALYSIS_NOT_ASSIGNED="TRUE" *)
   (* ANALYSIS_NOT_REFERENCED="TRUE" *)
   inout   vd;
   (* ANALYSIS_NOT_ASSIGNED="TRUE" *)
   (* ANALYSIS_NOT_REFERENCED="TRUE" *)
   inout   gd;

   wire    carn1;
   wire    carn2;
   wire    carn3;

//   assign sum = a ^ b ^ c;
   tri_xor3 CSA42_XOR3_1(sum, a, b, c);

//   assign car = (a & b) | (a & c) | (b & c);
   tri_nand2 CSA42_NAND2_1(carn1, a, b);
   tri_nand2 CSA42_NAND2_2(carn2, a, c);
   tri_nand2 CSA42_NAND2_3(carn3, b, c);
   tri_nand3 CSA42_NAND3_4(car, carn1, carn2, carn3);


endmodule
module tri_regk(
   vd,
   gd,
   nclk,
   act,
   force_t,
   thold_b,
   d_mode,
   sg,
   delay_lclkr,
   mpw1_b,
   mpw2_b,
   scin,
   din,
   scout,
   dout
);
   parameter                      WIDTH = 4;
   parameter                      OFFSET = 0;		//starting bit
   parameter                      INIT = 0;		// will be converted to the least signficant
                                                        // 31 bits of init_v
   parameter                      SYNTHCLONEDLATCH = "";
   parameter                      NEEDS_SRESET = 1;		// for inferred latches
   parameter                      DOMAIN_CROSSING = 0;

   inout                          vd;
   inout                          gd;
   input [0:`NCLK_WIDTH-1]        nclk;
   input                          act;                  // 1: functional, 0: no clock
   input                          force_t;		// 1: force LCB active
   input                          thold_b;		// 1: functional, 0: no clock
   input                          d_mode;		// 1: disable pulse mode, 0: pulse mode
   input                          sg;                   // 0: functional, 1: scan
   input                          delay_lclkr;		// 0: functional
   input                          mpw1_b;		// pulse width control bit
   input                          mpw2_b;		// pulse width control bit
   input [OFFSET:OFFSET+WIDTH-1]  scin;                 // scan in
   input [OFFSET:OFFSET+WIDTH-1]  din;                  // data in
   output [OFFSET:OFFSET+WIDTH-1] scout;
   output [OFFSET:OFFSET+WIDTH-1] dout;

   parameter [0:WIDTH-1]          init_v = INIT;
   parameter [0:WIDTH-1]          ZEROS = {WIDTH{1'b0}};

   // tri_regk

   generate
   begin
     wire                         sreset;
     wire [0:WIDTH-1]             int_din;
     reg [0:WIDTH-1]              int_dout;
     wire [0:WIDTH-1]             vact;
     wire [0:WIDTH-1]             vact_b;
     wire [0:WIDTH-1]             vsreset;
     wire [0:WIDTH-1]             vsreset_b;
     wire [0:WIDTH-1]             vthold;
     wire [0:WIDTH-1]             vthold_b;
       (* analysis_not_referenced="true" *)
     wire                         unused;

     if (NEEDS_SRESET == 1)
     begin : rst
       assign sreset = nclk[1];
     end
     if (NEEDS_SRESET != 1)
     begin : no_rst
       assign sreset = 1'b0;
     end

     assign vsreset = {WIDTH{sreset}};
     assign vsreset_b = {WIDTH{~sreset}};
     assign int_din = (vsreset_b & din) | (vsreset & init_v);

     assign vact = {WIDTH{act | force_t}};
     assign vact_b = {WIDTH{~(act | force_t)}};

     assign vthold_b = {WIDTH{thold_b}};
     assign vthold = {WIDTH{~thold_b}};


     always @(posedge nclk[0])
     begin: l
       int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
     end
     assign dout = int_dout;

     assign scout = ZEROS;

     assign unused = | {vd, gd, nclk, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin};
   end
   endgenerate
endmodule
module tri_fu_mul_bthdcd(
   i0,
   i1,
   i2,
   s_neg,
   s_x,
   s_x2
);
   input   i0;
   input   i1;
   input   i2;
   output  s_neg;
   output  s_x;
   output  s_x2;

   //  ATTRIBUTE btr_name   OF tri_fu_mul_bthdcd          : ENTITY IS "tri_fu_mul_bthdcd";

   wire    s_add;
   wire    sx1_a0_b;
   wire    sx1_a1_b;
   wire    sx1_t;
   wire    sx1_i;
   wire    sx2_a0_b;
   wire    sx2_a1_b;
   wire    sx2_t;
   wire    sx2_i;
   wire    i0_b;
   wire    i1_b;
   wire    i2_b;

   // i0:2      booth recode table
   //--------------------------------
   // 000  add  sh1=0 sh2=0  sub_adj=0
   // 001  add  sh1=1 sh2=0  sub_adj=0
   // 010  add  sh1=1 sh2=0  sub_adj=0
   // 011  add  sh1=0 sh2=1  sub_adj=0
   // 100  sub  sh1=0 sh2=1  sub_adj=1
   // 101  sub  sh1=1 sh2=0  sub_adj=1
   // 110  sub  sh1=1 sh2=0  sub_adj=1
   // 111  sub  sh1=0 sh2=0  sub_adj=0

   // logically correct
   //----------------------------------
   //  s_neg <= (i0);
   //  s_x   <= (       not i1 and     i2) or (           i1 and not i2);
   //  s_x2  <= (i0 and not i1 and not i2) or (not i0 and i1 and     i2);

   assign i0_b = (~(i0));
   assign i1_b = (~(i1));
   assign i2_b = (~(i2));

   assign s_add = (~(i0));
   assign s_neg = (~(s_add));

   assign sx1_a0_b = (~(i1_b & i2));
   assign sx1_a1_b = (~(i1 & i2_b));
   assign sx1_t = (~(sx1_a0_b & sx1_a1_b));
   assign sx1_i = (~(sx1_t));
   assign s_x = (~(sx1_i));

   assign sx2_a0_b = (~(i0 & i1_b & i2_b));
   assign sx2_a1_b = (~(i0_b & i1 & i2));
   assign sx2_t = (~(sx2_a0_b & sx2_a1_b));
   assign sx2_i = (~(sx2_t));
   assign s_x2 = (~(sx2_i));

endmodule
module tri_lcbnd(
   vd,
   gd,
   act,
   delay_lclkr,
   mpw1_b,
   mpw2_b,
   nclk,
   force_t,
   sg,
   thold_b,
   d1clk,
   d2clk,
   lclk
);
   parameter                      DOMAIN_CROSSING = 0;

   inout      vd;
   inout      gd;
   input      act;
   input      delay_lclkr;
   input      mpw1_b;
   input      mpw2_b;
   input[0:`NCLK_WIDTH-1]  nclk;
   input      force_t;
   input      sg;
   input      thold_b;
   output     d1clk;
   output     d2clk;
   output[0:`NCLK_WIDTH-1]  lclk;

   // tri_lcbnd
   wire       gate_b;
    (* analysis_not_referenced="true" *)
   wire       unused;

   assign unused = vd | gd | delay_lclkr | mpw1_b | mpw2_b | sg;

   assign gate_b = force_t | act;

   assign d1clk = gate_b;
   assign d2clk = thold_b;
   assign lclk = nclk;
endmodule
module tri_st_mult_boothdcd(
   i0,
   i1,
   i2,
   s_neg,
   s_x,
   s_x2
);
   input   i0;
   input   i1;
   input   i2;
   output  s_neg;
   output  s_x;
   output  s_x2;

   wire    s_add;
   wire    sx1_a0_b;
   wire    sx1_a1_b;
   wire    sx1_t;
   wire    sx1_i;
   wire    sx2_a0_b;
   wire    sx2_a1_b;
   wire    sx2_t;
   wire    sx2_i;
   wire    i0_b;
   wire    i1_b;
   wire    i2_b;


   // i0:2      booth recode table
   //--------------------------------
   // 000  add  sh1=0 sh2=0  sub_adj=0
   // 001  add  sh1=1 sh2=0  sub_adj=0
   // 010  add  sh1=1 sh2=0  sub_adj=0
   // 011  add  sh1=0 sh2=1  sub_adj=0
   // 100  sub  sh1=0 sh2=1  sub_adj=1
   // 101  sub  sh1=1 sh2=0  sub_adj=1
   // 110  sub  sh1=1 sh2=0  sub_adj=1
   // 111  sub  sh1=0 sh2=0  sub_adj=0

   // logically correct
   //----------------------------------
   //  s_neg <= (i0);
   //  s_x   <= (       not i1 and     i2) or (           i1 and not i2);
   //  s_x2  <= (i0 and not i1 and not i2) or (not i0 and i1 and     i2);

   assign i0_b = (~(i0));
   assign i1_b = (~(i1));
   assign i2_b = (~(i2));

   assign s_add = (~(i0));
   assign s_neg = (~(s_add));

   assign sx1_a0_b = (~(i1_b & i2));
   assign sx1_a1_b = (~(i1 & i2_b));
   assign sx1_t = (~(sx1_a0_b & sx1_a1_b));
   assign sx1_i = (~(sx1_t));
   assign s_x = (~(sx1_i));

   assign sx2_a0_b = (~(i0 & i1_b & i2_b));
   assign sx2_a1_b = (~(i0_b & i1 & i2));
   assign sx2_t = (~(sx2_a0_b & sx2_a1_b));
   assign sx2_i = (~(sx2_t));
   assign s_x2 = (~(sx2_i));

endmodule
module tri_pri(
   cond,
   pri,
   or_cond
);
   parameter                  SIZE = 32;	// Size of "cond", range 3 - 32
   parameter                  REV = 0;		// 0 = 0 is highest,   1 = 0 is lowest
   parameter                  CMP_ZERO = 0;	// 1 = include comparing cond to zero in pri vector, 0 = don't
   input [0:SIZE-1]           cond;
   output [0:SIZE-1+CMP_ZERO] pri;
   output                     or_cond;

   // tri_pri

   parameter                  s = SIZE - 1;
   wire [0:s]                 l0;
   wire [0:s]                 or_l1;
   wire [0:s]                 or_l2;
   wire [0:s]                 or_l3;
   wire [0:s]                 or_l4;
   wire [0:s]                 or_l5;

   generate
   begin
     if (REV == 0)
     begin
       assign l0[0:s] = cond[0:s];
     end
     if (REV == 1)
     begin
       assign l0[0:s] = cond[s:0];
     end

     // Odd Numbered Levels are inverted

     assign or_l1[0] = ~l0[0];
     assign or_l1[1:s] = ~(l0[0:s - 1] | l0[1:s]);

     if (s >= 2)
     begin
       assign or_l2[0:1] = ~or_l1[0:1];
       assign or_l2[2:s] = ~(or_l1[2:s] & or_l1[0:s - 2]);
     end
     if (s < 2)
     begin
       assign or_l2 = ~or_l1;
     end

     if (s >= 4)
     begin
       assign or_l3[0:3] = ~or_l2[0:3];
       assign or_l3[4:s] = ~(or_l2[4:s] | or_l2[0:s - 4]);
     end
     if (s < 4)
     begin
       assign or_l3 = ~or_l2;
     end

     if (s >= 8)
     begin
       assign or_l4[0:7] = ~or_l3[0:7];
       assign or_l4[8:s] = ~(or_l3[8:s] & or_l3[0:s - 8]);
     end
     if (s < 8)
     begin
       assign or_l4 = ~or_l3;
     end

     if (s >= 16)
     begin
       assign or_l5[0:15] = ~or_l4[0:15];
       assign or_l5[16:s] = ~(or_l4[16:s] | or_l4[0:s - 16]);
     end
     if (s < 16)
     begin
       assign or_l5 = ~or_l4;
     end

     //assert SIZE > 32 report "Maximum Size of 32 Exceeded!" severity error;

     assign pri[0] = cond[0];
     assign pri[1:s] = cond[1:s] & or_l5[0:s - 1];

     if (CMP_ZERO == 1)
     begin
       assign pri[s + 1] = or_l5[s];
     end

     assign or_cond = ~or_l5[s];
   end
   endgenerate

//!! [fail; tri_pri;  "Priority not zero or one hot!!"] : (pri1 ) <= not zero_or_one_hot(pri);

endmodule
module tri_scom_addr_decode(
   sc_addr,
   scaddr_dec,
   sc_req,
   sc_r_nw,
   scaddr_nvld,
   sc_wr_nvld,
   sc_rd_nvld,
   vd,
   gd
);

//=====================================================================
// I/O and Signal Declarations
//=====================================================================
   parameter				ADDR_SIZE      = 64;
   parameter				SATID_NOBITS   = 5; 	// should not be set by user

//  Set the USE_ADDR, ADDR_IS_RDABLE, ADDR_IS_WRABLE vectors to generate a SCOM address
//                                  	HEX  >>>>>          "0000000000000000111111111111111122222222222222223333333333333333"
//                                  	ADDR >>>>>          "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF"
//
//                                  	DEC  >>>>>          "0000000000111111111122222222223333333333444444444455555555556666"
//                                  	ADDR >>>>>          "0123456789012345678901234567890123456789012345678901234567890123"
   parameter [0:ADDR_SIZE-1]        	USE_ADDR       = 64'b1000000000000000000000000000000000000000000000000000000000000000;
   parameter [0:ADDR_SIZE-1]        	ADDR_IS_RDABLE = 64'b1000000000000000000000000000000000000000000000000000000000000000;
   parameter [0:ADDR_SIZE-1]        	ADDR_IS_WRABLE = 64'b1000000000000000000000000000000000000000000000000000000000000000;

   input  [0:11-SATID_NOBITS-1]		sc_addr;	// binary coded scom address
   output [0:ADDR_SIZE-1]      		scaddr_dec;	// one hot coded scom address; not latched

   input                       		sc_req;		// scom request
   input                       		sc_r_nw;	// read / not write bit
   output                      		scaddr_nvld;	// scom address not valid; not latched
   output                      		sc_wr_nvld;	// scom write not allowed; not latched
   output                      		sc_rd_nvld;	// scom read  not allowed; not latched

   inout                       		vd;
   inout                       		gd;



//=====================================================================
   wire   [0:ADDR_SIZE-1]       	address;


// Don't reference unused inputs:
(* analysis_not_referenced="true" *)
   wire                   		unused;
   assign unused = vd | gd;


//=====================================================================
   generate
     begin : decode_it
	 genvar    i;
	 for (i=0; i<ADDR_SIZE; i=i+1)
	 begin : decode_it
            assign address[i] = ({{32-SATID_NOBITS{1'b0}},sc_addr} == i) & USE_ADDR[i];
    	 end
     end
   endgenerate

      assign scaddr_dec  = address;
      assign scaddr_nvld = sc_req & (~|address);
      assign sc_wr_nvld  = (~(|(address & ADDR_IS_WRABLE)) & sc_req & (~sc_r_nw));
      assign sc_rd_nvld  = (~(|(address & ADDR_IS_RDABLE)) & sc_req &   sc_r_nw );

endmodule
module tri_st_add_glbloc(
   g01,
   t01,
   g08,
   t08
);
   input [0:7] g01;		// after xor
   input [0:7] t01;
   output      g08;
   output      t08;

   wire [0:3]  g02_b;
   wire [0:3]  t02_b;
   wire [0:1]  g04;
   wire [0:1]  t04;
   wire        g08_b;
   wire        t08_b;

   assign g02_b[0] = (~(g01[0] | (t01[0] & g01[1])));
   assign g02_b[1] = (~(g01[2] | (t01[2] & g01[3])));
   assign g02_b[2] = (~(g01[4] | (t01[4] & g01[5])));
   assign g02_b[3] = (~(g01[6] | (t01[6] & g01[7])));

   assign t02_b[0] = (~(t01[0] & t01[1]));
   assign t02_b[1] = (~(t01[2] & t01[3]));
   assign t02_b[2] = (~(t01[4] & t01[5]));
   assign t02_b[3] = (~(t01[6] & t01[7]));

   assign g04[0] = (~(g02_b[0] & (t02_b[0] | g02_b[1])));
   assign g04[1] = (~(g02_b[2] & (t02_b[2] | g02_b[3])));

   assign t04[0] = (~(t02_b[0] | t02_b[1]));
   assign t04[1] = (~(t02_b[2] | t02_b[3]));

   assign g08_b = (~(g04[0] | (t04[0] & g04[1])));

   assign t08_b = (~((t04[0] & t04[1])));

   assign g08 = (~(g08_b));		// output

   assign t08 = (~(t08_b));		// output


endmodule
module tri_st_popcnt_word(
   b0,
   b1,
   b2,
   b3,
   y,
   vdd,
   gnd
);
   input [0:3]  b0;
   input [0:3]  b1;
   input [0:3]  b2;
   input [0:3]  b3;
   output [0:5] y;
   inout        vdd;
   inout        gnd;

   wire [0:0]   s0;
   wire [0:1]   c1;
   wire [0:1]   s1;
   wire [0:2]   c2;
   wire [0:1]   s2;
   wire [0:2]   c3;
   wire [0:1]   s3;
   wire [0:2]   c4;

   // Level 0

   tri_csa32 csa_l0_0(
      .vd(vdd),
      .gd(gnd),
      .a(b0[0]),
      .b(b0[1]),
      .c(b0[2]),
      .sum(s0[0]),
      .car(c1[0])
   );


   tri_csa22 csa_l0_1(
      .a(b0[3]),
      .b(s0[0]),
      .sum(y[5]),
      .car(c1[1])
   );

   // Level 1

   tri_csa32 csa_l1_0(
      .vd(vdd),
      .gd(gnd),
      .a(b1[0]),
      .b(b1[1]),
      .c(b1[2]),
      .sum(s1[0]),
      .car(c2[0])
   );


   tri_csa32 csa_l1_1(
      .vd(vdd),
      .gd(gnd),
      .a(b1[3]),
      .b(c1[0]),
      .c(c1[1]),
      .sum(s1[1]),
      .car(c2[1])
   );


   tri_csa22 csa_l1_2(
      .a(s1[0]),
      .b(s1[1]),
      .sum(y[4]),
      .car(c2[2])
   );

   // Level 2

   tri_csa32 csa_l2_0(
      .vd(vdd),
      .gd(gnd),
      .a(b2[0]),
      .b(b2[1]),
      .c(b2[2]),
      .sum(s2[0]),
      .car(c3[0])
   );


   tri_csa32 csa_l2_1(
      .vd(vdd),
      .gd(gnd),
      .a(b2[3]),
      .b(c2[0]),
      .c(c2[1]),
      .sum(s2[1]),
      .car(c3[1])
   );


   tri_csa32 csa_l2_2(
      .vd(vdd),
      .gd(gnd),
      .a(c2[2]),
      .b(s2[0]),
      .c(s2[1]),
      .sum(y[3]),
      .car(c3[2])
   );

   // Level 3

   tri_csa32 csa_l3_0(
      .vd(vdd),
      .gd(gnd),
      .a(b3[0]),
      .b(b3[1]),
      .c(b3[2]),
      .sum(s3[0]),
      .car(c4[0])
   );


   tri_csa32 csa_l3_1(
      .vd(vdd),
      .gd(gnd),
      .a(b3[3]),
      .b(c3[0]),
      .c(c3[1]),
      .sum(s3[1]),
      .car(c4[1])
   );


   tri_csa32 csa_l3_2(
      .vd(vdd),
      .gd(gnd),
      .a(c3[2]),
      .b(s3[0]),
      .c(s3[1]),
      .sum(y[2]),
      .car(c4[2])
   );

   // Level 4

   tri_csa32 csa_l4_0(
      .vd(vdd),
      .gd(gnd),
      .a(c4[0]),
      .b(c4[1]),
      .c(c4[2]),
      .sum(y[1]),
      .car(y[0])
   );

endmodule
module tri_lcbs(
   vd,
   gd,
   delay_lclkr,
   nclk,
   force_t,
   thold_b,
   dclk,
   lclk
);
   inout      vd;
   inout      gd;
   input      delay_lclkr;
   input[0:`NCLK_WIDTH-1]  nclk;
   input      force_t;
   input      thold_b;
   output     dclk;
   output[0:`NCLK_WIDTH-1]  lclk;

   //  tri_lcbs

   (* analysis_not_referenced="true" *)
   wire       unused;

   assign unused = vd | gd | delay_lclkr | force_t;

   // No scan chain in this methodology
   assign dclk = thold_b;
   assign lclk = nclk;
endmodule
module tri_direct_err_rpt(
   vd,
   gd,
   err_in,
   err_out
);
   parameter          WIDTH = 1;		// use to bundle error reporting checkers of the same exact type
   inout              vd;
   inout              gd;

   input [0:WIDTH-1]  err_in;
   output [0:WIDTH-1] err_out;

   // tri_direct_err_rpt

    (* analysis_not_referenced="true" *)
   wire               unused;

   assign unused = vd | gd;

   assign err_out = err_in;
endmodule
module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin, din, scout, dout);
   parameter             INIT = 0;		// will be converted to the least signficant
                                                // 31 bits of init_v
   parameter             IBUF = 1'b0;		//inverted latch IOs, if set to true.
   parameter             DUALSCAN = "";		// if "S", marks data ports as scan for Moebius
   parameter             NEEDS_SRESET = 1;	// for inferred latches
   parameter             DOMAIN_CROSSING = 0;

   inout                        vd;
   inout                        gd;
   input [0:`NCLK_WIDTH-1]      nclk;
   input                        act;		// 1: functional, 0: no clock
   input                        force_t;	// 1: force LCB active
   input                        thold_b;	// 1: functional, 0: no clock
   input                        d_mode;		// 1: disable pulse mode, 0: pulse mode
   input                        sg;		// 0: functional, 1: scan
   input                        delay_lclkr;	// 0: functional
   input                        mpw1_b;		// pulse width control bit
   input                        mpw2_b;		// pulse width control bit
   input                        scin;		// scan in
   input                        din;		// data in
   output                       scout;		// scan out
   output                       dout;		// data out

   parameter             WIDTH = 1;
   parameter [0:WIDTH-1] init_v = INIT;

   // tri_rlmlatch_p

   generate
   begin
     wire                  sreset;
     wire                  int_din;
     reg                   int_dout;
       (* analysis_not_referenced="true" *)
     wire                  unused;

     if (NEEDS_SRESET == 1)
     begin : rst
       assign sreset = nclk[1];
     end
     if (NEEDS_SRESET != 1)
     begin : no_rst
       assign sreset = 1'b0;
     end

     if (IBUF == 1'b1)
     begin : cib
       assign int_din = ((~sreset) & (~din)) | (sreset & init_v[0]);
     end
     if (IBUF == 1'b0)
     begin : cnib
       assign int_din = ((~sreset) & din) | (sreset & init_v[0]);
     end

     always @(posedge nclk[0])
     begin: l
       int_dout <= ((((act | force_t) & thold_b) | sreset) & int_din) | ((((~act) & (~force_t)) | (~thold_b)) & (~sreset) & int_dout);
     end

     if (IBUF == 1'b1)
     begin : cob
       assign dout = (~int_dout);
     end

     if (IBUF == 1'b0)
     begin : cnob
       assign dout = int_dout;
     end

     assign scout = 1'b0;

     assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | scin | vd | gd | (|nclk);
   end
   endgenerate
endmodule
module tri_nor2(
   y,
   a,
   b
);
   parameter                      WIDTH = 1;
   parameter                      BTR = "NOR2_X2M_NONE";  //Specify full BTR name, else let tool select
   output [0:WIDTH-1]  y;
   input [0:WIDTH-1]   a;
   input [0:WIDTH-1]   b;

   // tri_nor2
   genvar 	       i;

   generate
      begin : t
	 for (i = 0; i < WIDTH; i = i + 1)
	   begin : w

	      nor I0(y[i], a[i], b[i]);

	   end // block: w
      end

   endgenerate
endmodule
module tri_addrcmp(
   enable_lsb,
   d0,
   d1,
   eq
);

   input        enable_lsb;		// when "0" the LSB is disabled
   input [0:35] d0;
   input [0:35] d1;
   output       eq;

   // tri_addrcmp

      parameter    tiup = 1'b1;
      parameter    tidn = 1'b0;

      wire [0:35]  eq01_b;
      wire [0:18]  eq02;
      wire [0:9]   eq04_b;
      wire [0:4]   eq08;
      wire [0:1]   eq24_b;

      assign eq01_b[0:35] = (d0[0:35] ^ d1[0:35]);

      assign eq02[0] = (~(eq01_b[0] | eq01_b[1]));
      assign eq02[1] = (~(eq01_b[2] | eq01_b[3]));
      assign eq02[2] = (~(eq01_b[4] | eq01_b[5]));
      assign eq02[3] = (~(eq01_b[6] | eq01_b[7]));
      assign eq02[4] = (~(eq01_b[8] | eq01_b[9]));
      assign eq02[5] = (~(eq01_b[10] | eq01_b[11]));
      assign eq02[6] = (~(eq01_b[12] | eq01_b[13]));
      assign eq02[7] = (~(eq01_b[14] | eq01_b[15]));
      assign eq02[8] = (~(eq01_b[16] | eq01_b[17]));
      assign eq02[9] = (~(eq01_b[18] | eq01_b[19]));
      assign eq02[10] = (~(eq01_b[20] | eq01_b[21]));
      assign eq02[11] = (~(eq01_b[22] | eq01_b[23]));
      assign eq02[12] = (~(eq01_b[24] | eq01_b[25]));
      assign eq02[13] = (~(eq01_b[26] | eq01_b[27]));
      assign eq02[14] = (~(eq01_b[28] | eq01_b[29]));
      assign eq02[15] = (~(eq01_b[30] | eq01_b[31]));
      assign eq02[16] = (~(eq01_b[32] | eq01_b[33]));
      assign eq02[17] = (~(eq01_b[34]));
      assign eq02[18] = (~(eq01_b[35] & enable_lsb));

      assign eq04_b[0] = (~(eq02[0] & eq02[1]));
      assign eq04_b[1] = (~(eq02[2] & eq02[3]));
      assign eq04_b[2] = (~(eq02[4] & eq02[5]));
      assign eq04_b[3] = (~(eq02[6] & eq02[7]));
      assign eq04_b[4] = (~(eq02[8] & eq02[9]));
      assign eq04_b[5] = (~(eq02[10] & eq02[11]));
      assign eq04_b[6] = (~(eq02[12] & eq02[13]));
      assign eq04_b[7] = (~(eq02[14] & eq02[15]));
      assign eq04_b[8] = (~(eq02[16] & eq02[17]));
      assign eq04_b[9] = (~(eq02[18]));

      assign eq08[0] = (~(eq04_b[0] | eq04_b[1]));
      assign eq08[1] = (~(eq04_b[2] | eq04_b[3]));
      assign eq08[2] = (~(eq04_b[4] | eq04_b[5]));
      assign eq08[3] = (~(eq04_b[6] | eq04_b[7]));
      assign eq08[4] = (~(eq04_b[8] | eq04_b[9]));

      assign eq24_b[0] = (~(eq08[0] & eq08[1] & eq08[2]));
      assign eq24_b[1] = (~(eq08[3] & eq08[4]));

      assign eq = (~(eq24_b[0] | eq24_b[1]));		// output
endmodule
module tri_fu_csa22_h2(
   a,
   b,
   car,
   sum
);
   input   a;
   input   b;
   output  car;
   output  sum;

   wire    car_b;
   wire    sum_b;

   assign car_b = (~(a & b));
   assign sum_b = (~(car_b & (a | b)));		// this is equiv to an xnor
   assign car = (~car_b);
   assign sum = (~sum_b);

endmodule
module tri_inv_nlats(
   vd,
   gd,
   lclk,
   d1clk,
   d2clk,
   scanin,
   scanout,
   d,
   qb
);
   parameter                      OFFSET = 0;
   parameter                      WIDTH = 1;
   parameter                      INIT = 0;
   parameter                      L2_LATCH_TYPE = 2;            //L2_LATCH_TYPE = slave_latch;
                                                                //0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4
   parameter                      SYNTHCLONEDLATCH = "";
   parameter                      BTR = "NLI0001_X1_A12TH";
   parameter                      NEEDS_SRESET = 1;		// for inferred latches
   parameter                      DOMAIN_CROSSING = 0;

   inout                          vd;
   inout                          gd;
   input [0:`NCLK_WIDTH-1]        lclk;
   input                          d1clk;
   input                          d2clk;
   input [OFFSET:OFFSET+WIDTH-1]  scanin;
   output [OFFSET:OFFSET+WIDTH-1] scanout;
   input [OFFSET:OFFSET+WIDTH-1]  d;
   output [OFFSET:OFFSET+WIDTH-1] qb;

   // tri_inv_nlats

   parameter [0:WIDTH-1]          init_v = INIT;
   parameter [0:WIDTH-1]          ZEROS = {WIDTH{1'b0}};

   generate
   begin
      wire                          sreset;
      wire [0:WIDTH-1]              int_din;
      reg [0:WIDTH-1]               int_dout;
      wire [0:WIDTH-1]              vact;
      wire [0:WIDTH-1]              vact_b;
      wire [0:WIDTH-1]              vsreset;
      wire [0:WIDTH-1]              vsreset_b;
      wire [0:WIDTH-1]              vthold;
      wire [0:WIDTH-1]              vthold_b;
      wire [0:WIDTH-1]              din;
       (* analysis_not_referenced="true" *)
      wire                          unused;

      if (NEEDS_SRESET == 1)
      begin : rst
        assign sreset = lclk[1];
      end
      if (NEEDS_SRESET != 1)
      begin : no_rst
        assign sreset = 1'b0;
      end

      assign vsreset = {WIDTH{sreset}};
      assign vsreset_b = {WIDTH{~sreset}};
      assign din = d;		// Output is inverted, so don't invert here
      assign int_din = (vsreset_b & din) | (vsreset & init_v);

      assign vact = {WIDTH{d1clk}};
      assign vact_b = {WIDTH{~d1clk}};

      assign vthold_b = {WIDTH{d2clk}};
      assign vthold = {WIDTH{~d2clk}};


      always @(posedge lclk[0])
      begin: l
        int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
      end
      assign qb = (~int_dout);
      assign scanout = ZEROS;

      assign unused = | {vd, gd, lclk, scanin};
   end
   endgenerate
endmodule
module tri_bthmx(x, sneg, sx, sx2, right, left, q, vd, gd);

input          x;
input          sneg;
input          sx;
input          sx2;
input          right;
output         left;
output         q;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
(* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout          vd;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
(* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout          gd;



wire center, xn, spos;

assign xn      = ~x;
assign spos    = ~sneg;

assign center  = ~(( xn & spos ) |
                   ( x  & sneg ));

assign left    = center; // output


assign q       = ( center &  sx  ) |
                 ( right  &  sx2 ) ;

endmodule
module tri_fu_tblmul_bthdcd(
   i0,
   i1,
   i2,
   s_neg,
   s_x,
   s_x2
);
   input   i0;
   input   i1;
   input   i2;
   output  s_neg;
   output  s_x;
   output  s_x2;

   wire    s_add;
   wire    sx1_a0_b;
   wire    sx1_a1_b;
   wire    sx1_t;
   wire    sx1_i;
   wire    sx2_a0_b;
   wire    sx2_a1_b;
   wire    sx2_t;
   wire    sx2_i;
   wire    i0_b;
   wire    i1_b;
   wire    i2_b;


   ////    -- 000  add  sh1=0 sh2=0  sub_adj=0
   ////    -- 001  add  sh1=1 sh2=0  sub_adj=0
   ////    -- 010  add  sh1=1 sh2=0  sub_adj=0
   ////    -- 011  add  sh1=0 sh2=1  sub_adj=0
   ////    -- 100  sub  sh1=0 sh2=1  sub_adj=1
   ////    -- 101  sub  sh1=1 sh2=0  sub_adj=1
   ////    -- 110  sub  sh1=1 sh2=0  sub_adj=1
   ////    -- 111  sub  sh1=0 sh2=0  sub_adj=0
   ////
   ////    s_neg    <= (     i0                       );
   ////
   ////    s_x      <= (            not i1 and     i2 ) or
   ////                (                i1 and not i2 );
   ////    s_x2     <= (     i0 and not i1 and not i2 ) or
   ////                ( not i0 and     i1 and     i2 );
   ////
   ////    sub_adj  <= i0 and not( i1 and i2 );
   ////

   // logically correct
   //----------------------------------
   //  s_neg <= (i0);
   //  s_x   <= (       not i1 and     i2) or (           i1 and not i2);
   //  s_x2  <= (i0 and not i1 and not i2) or (not i0 and i1 and     i2);

   assign i0_b = (~(i0));
   assign i1_b = (~(i1));
   assign i2_b = (~(i2));

   assign s_add = (~(i0));
   assign s_neg = (~(s_add));

   assign sx1_a0_b = (~(i1_b & i2));
   assign sx1_a1_b = (~(i1 & i2_b));
   assign sx1_t = (~(sx1_a0_b & sx1_a1_b));
   assign sx1_i = (~(sx1_t));
   assign s_x = (~(sx1_i));

   assign sx2_a0_b = (~(i0 & i1_b & i2_b));
   assign sx2_a1_b = (~(i0_b & i1 & i2));
   assign sx2_t = (~(sx2_a0_b & sx2_a1_b));
   assign sx2_i = (~(sx2_t));
   assign s_x2 = (~(sx2_i));


endmodule
module tri_nand3(
   y,
   a,
   b,
   c
);
   parameter                      WIDTH = 1;
   parameter                      BTR = "NAND3_X2M_NONE";  //Specify full BTR name, else let tool select
   output [0:WIDTH-1]  y;
   input [0:WIDTH-1]   a;
   input [0:WIDTH-1]   b;
   input [0:WIDTH-1]   c;

   // tri_nand3
   genvar 	       i;

   generate
      begin : t
	 for (i = 0; i < WIDTH; i = i + 1)
	   begin : w

      	      nand I0(y[i], a[i], b[i], c[i]);


	   end // block: w
      end

   endgenerate
endmodule
module tri_ser_rlmreg_p(
   vd,
   gd,
   nclk,
   act,
   force_t,
   thold_b,
   d_mode,
   sg,
   delay_lclkr,
   mpw1_b,
   mpw2_b,
   scin,
   din,
   scout,
   dout
);
   parameter                      WIDTH = 1;
   parameter                      OFFSET = 0;
   parameter                      INIT = 0;
   parameter                      IBUF = 1'b0;
   parameter                      DUALSCAN = "";
   parameter                      NEEDS_SRESET = 1;
   parameter                      DOMAIN_CROSSING = 0;

   inout                          vd;
   inout                          gd;
   input [0:`NCLK_WIDTH-1]        nclk;
   input                          act;
   input                          force_t;
   input                          thold_b;
   input                          d_mode;
   input                          sg;
   input                          delay_lclkr;
   input                          mpw1_b;
   input                          mpw2_b;
   input [OFFSET:OFFSET+WIDTH-1]  scin;
   input [OFFSET:OFFSET+WIDTH-1]  din;
   output [OFFSET:OFFSET+WIDTH-1] scout;
   output [OFFSET:OFFSET+WIDTH-1] dout;

   // tri_ser_rlmreg_p

   wire [OFFSET:OFFSET+WIDTH-1]   dout_b;
   wire [OFFSET:OFFSET+WIDTH-1]   act_buf;
   wire [OFFSET:OFFSET+WIDTH-1]   act_buf_b;
   wire [OFFSET:OFFSET+WIDTH-1]   dout_buf;

   assign act_buf = {WIDTH{act}};
   assign act_buf_b = {WIDTH{~(act)}};
   assign dout_buf = (~dout_b);
   assign dout = dout_buf;

   tri_aoi22_nlats_wlcb #(.WIDTH(WIDTH), .OFFSET(OFFSET), .INIT(INIT), .IBUF(IBUF), .DUALSCAN(DUALSCAN), .NEEDS_SRESET(NEEDS_SRESET)) tri_ser_rlmreg_p(
         .nclk(nclk),
         .vd(vd),
         .gd(gd),
         .act(act),
         .force_t(force_t),
         .d_mode(d_mode),
         .delay_lclkr(delay_lclkr),
         .mpw1_b(mpw1_b),
         .mpw2_b(mpw2_b),
         .thold_b(thold_b),
         .sg(sg),
         .scin(scin),
         .scout(scout),
         .a1(din),
         .a2(act_buf),
         .b1(dout_buf),
         .b2(act_buf_b),
         .qb(dout_b)
   );
endmodule
module tri_st_cntlz(
   dword,
   a,
   y
);
   input        dword;
   input [0:63] a;
   output [0:6] y;

   wire [0:23]  ys;
   wire [0:7]   z;
   wire [0:7]   zh;
   wire [0:2]   yh;
   wire [0:2]   yh_sel;
   wire         zero_b;

   assign y[0] = (dword == 1'b1) ? (~zero_b) :
                 1'b0;

   assign y[1] = (dword == 1'b1) ? yh[0] :
                 (~zero_b);
   assign y[2:3] = yh[1:2];

   // Force the select to the lower half for word ops
   assign yh_sel[0] = yh[0] | (~dword);
   assign yh_sel[1:2] = yh[1:2];

   // Force the select to be in the lower half for word
   assign y[4:6] = (yh_sel[0:2] == 3'b000) ? ys[0:2] :
                   (yh_sel[0:2] == 3'b001) ? ys[3:5] :
                   (yh_sel[0:2] == 3'b010) ? ys[6:8] :
                   (yh_sel[0:2] == 3'b011) ? ys[9:11] :
                   (yh_sel[0:2] == 3'b100) ? ys[12:14] :
                   (yh_sel[0:2] == 3'b101) ? ys[15:17] :
                   (yh_sel[0:2] == 3'b110) ? ys[18:20] :
                   ys[21:23];
   assign zh[0:3] = z[0:3] & {4{dword}};
   assign zh[4:7] = z[4:7];


   tri_st_cntlz_8b clz_h(
      .a(zh[0:7]),
      .y(yh[0:2]),
      .z_b(zero_b)
   );


   tri_st_cntlz_8b clz_l0(
      .a(a[0:7]),
      .y(ys[0:2]),
      .z_b(z[0])
   );


   tri_st_cntlz_8b clz_l1(
      .a(a[8:15]),
      .y(ys[3:5]),
      .z_b(z[1])
   );


   tri_st_cntlz_8b clz_l2(
      .a(a[16:23]),
      .y(ys[6:8]),
      .z_b(z[2])
   );


   tri_st_cntlz_8b clz_l3(
      .a(a[24:31]),
      .y(ys[9:11]),
      .z_b(z[3])
   );


   tri_st_cntlz_8b clz_l4(
      .a(a[32:39]),
      .y(ys[12:14]),
      .z_b(z[4])
   );


   tri_st_cntlz_8b clz_l5(
      .a(a[40:47]),
      .y(ys[15:17]),
      .z_b(z[5])
   );


   tri_st_cntlz_8b clz_l6(
      .a(a[48:55]),
      .y(ys[18:20]),
      .z_b(z[6])
   );


   tri_st_cntlz_8b clz_l7(
      .a(a[56:63]),
      .y(ys[21:23]),
      .z_b(z[7])
   );

endmodule
module tri_slat_scan(
   vd,
   gd,
   dclk,
   lclk,
   scan_in,
   scan_out,
   q,
   q_b
);
   parameter                      WIDTH = 1;
   parameter                      OFFSET = 0;
   parameter                      INIT = 0;
   parameter                      SYNTHCLONEDLATCH = "";
   parameter                      BTR = "c_slat_scan";
   parameter                      RESET_INVERTS_SCAN = 1'b1;

   inout                          vd;
   inout                          gd;
   input                          dclk;
   input [0:`NCLK_WIDTH-1]        lclk;
   input [OFFSET:OFFSET+WIDTH-1]  scan_in;
   output [OFFSET:OFFSET+WIDTH-1] scan_out;
   output [OFFSET:OFFSET+WIDTH-1] q;
   output [OFFSET:OFFSET+WIDTH-1] q_b;

   // tri_slat_scan

   parameter [0:WIDTH-1]          ZEROS = {WIDTH{1'b0}};
   parameter [0:WIDTH-1]          initv = INIT;

   (* analysis_not_referenced="true" *)
   wire                           unused;

   assign unused = | {vd, gd, dclk, lclk, scan_in};

   assign scan_out = ZEROS;
   assign q = initv;
   assign q_b = (~initv);
endmodule
module tri_agecmp(
   a,
   b,
   a_newer_b
);
   parameter        SIZE = 8;

   input [0:SIZE-1] a;
   input [0:SIZE-1] b;
   output           a_newer_b;

   // tri_agecmp

   wire             a_lt_b;
   wire             a_gte_b;
   wire             cmp_sel;

   assign a_lt_b = (a[1:SIZE - 1] < b[1:SIZE - 1]) ? 1'b1 :
   1'b0;

   assign a_gte_b = (~a_lt_b);

   assign cmp_sel = a[0] ~^ b[0];

   assign a_newer_b = (a_lt_b & (~cmp_sel)) | (a_gte_b & cmp_sel);
endmodule
module tri_lcbcntl_mac(
   vdd,
   gnd,
   sg,
   nclk,
   scan_in,
   scan_diag_dc,
   thold,
   clkoff_dc_b,
   delay_lclkr_dc,
   act_dis_dc,
   d_mode_dc,
   mpw1_dc_b,
   mpw2_dc_b,
   scan_out
);
   inout        vdd;
   inout        gnd;
   input        sg;
   input [0:`NCLK_WIDTH-1] nclk;
   input        scan_in;
   input        scan_diag_dc;
   input        thold;
   output       clkoff_dc_b;
   output [0:4] delay_lclkr_dc;
   output       act_dis_dc;
   output       d_mode_dc;
   output [0:4] mpw1_dc_b;
   output       mpw2_dc_b;
   output       scan_out;

   // tri_lcbcntl_mac

    (* analysis_not_referenced="true" *)
   wire         unused;

   assign clkoff_dc_b = 1'b1;
   assign delay_lclkr_dc = 5'b00000;
   assign act_dis_dc = 1'b0;
   assign d_mode_dc = 1'b0;
   assign mpw1_dc_b = 5'b11111;
   assign mpw2_dc_b = 1'b1;
   assign scan_out = 1'b0;

   assign unused = vdd | gnd | sg | (|nclk) | scan_in | scan_diag_dc | thold;
endmodule
module tri_regs(
   vd,
   gd,
   nclk,
   force_t,
   thold_b,
   delay_lclkr,
   scin,
   scout,
   dout
);
   parameter                      WIDTH = 4;
   parameter                      OFFSET = 0;		//starting bit
   parameter                      INIT = 0;		// will be converted to the least signficant
                                                        // 31 bits of init_v
   parameter                      IBUF = 1'b0;		//inverted latch IOs, if set to true.
   parameter                      DUALSCAN = "";		// if "S", marks data ports as scan for Moebius
   parameter                      NEEDS_SRESET = 1;		// for inferred latches
   parameter                      DOMAIN_CROSSING = 0;

   inout                          vd;
   inout                          gd;
   input [0:`NCLK_WIDTH-1]        nclk;
   input                          force_t;		// 1: force LCB active
   input                          thold_b;		// 1: functional, 0: no clock
   input                          delay_lclkr;		// 0: functional
   input [OFFSET:OFFSET+WIDTH-1]  scin;		// scan in
   output [OFFSET:OFFSET+WIDTH-1] scout;
   output [OFFSET:OFFSET+WIDTH-1] dout;

   parameter [0:WIDTH-1]          init_v = INIT;
   parameter [0:WIDTH-1]          ZEROS = {WIDTH{1'b0}};

   // tri_regs

   generate
   begin
      wire                        sreset;
      wire [0:WIDTH-1]            int_din;
      reg [0:WIDTH-1]             int_dout;
      wire [0:WIDTH-1]            vact;
      wire [0:WIDTH-1]            vact_b;
      wire [0:WIDTH-1]            vsreset;
      wire [0:WIDTH-1]            vsreset_b;
      wire [0:WIDTH-1]            vthold;
      wire [0:WIDTH-1]            vthold_b;
       (* analysis_not_referenced="true" *)
      wire                        unused;

      if (NEEDS_SRESET == 1)
      begin : rst
        assign sreset = nclk[1];
      end
      if (NEEDS_SRESET != 1)
      begin : no_rst
        assign sreset = 1'b0;
      end

      assign vsreset = {WIDTH{sreset}};
      assign vsreset_b = {WIDTH{~sreset}};

      assign int_din = (vsreset_b & int_dout) | (vsreset & init_v);

      assign vact = {WIDTH{force_t}};
      assign vact_b = {WIDTH{~force_t}};

      assign vthold_b = {WIDTH{thold_b}};
      assign vthold = {WIDTH{~thold_b}};


      always @(posedge nclk[0])
      begin: l
        int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
      end

      if (IBUF == 1'b1)
      begin : cob
        assign dout = (~int_dout);
      end

      if (IBUF == 1'b0)
      begin : cnob
        assign dout = int_dout;
      end

      assign scout = ZEROS;

      assign unused = | {vd, gd, nclk, delay_lclkr, scin};
   end
   endgenerate
endmodule
module tri_xor3(
   y,
   a,
   b,
   c
);
   parameter                      WIDTH = 1;
   parameter                      BTR = "XOR2_X2M_NONE";  //Specify full BTR name, else let tool select
   output [0:WIDTH-1]  y;
   input [0:WIDTH-1]   a;
   input [0:WIDTH-1]   b;
   input [0:WIDTH-1]   c;
   genvar 	       i;

   generate
      begin : t
	 for (i = 0; i < WIDTH; i = i + 1)
	   begin : w

	      xor I0(y[i], a[i], b[i], c[i]);

	   end // block: w
      end

   endgenerate
endmodule
module xu0_bprm(
   a,
   s,
   y
);
// IOs
input [0:63] a;
input [0:7]  s;
output       y;
// Signals
wire [0:7]   mh;
wire [0:7]   ml;
wire [0:63]  a1;
wire [0:63]  a2;

assign mh[0:7] = (s[0:4] == 5'b00000) ? 8'b10000000 :
                 (s[0:4] == 5'b00001) ? 8'b01000000 :
                 (s[0:4] == 5'b00010) ? 8'b00100000 :
                 (s[0:4] == 5'b00011) ? 8'b00010000 :
                 (s[0:4] == 5'b00100) ? 8'b00001000 :
                 (s[0:4] == 5'b00101) ? 8'b00000100 :
                 (s[0:4] == 5'b00110) ? 8'b00000010 :
                 (s[0:4] == 5'b00111) ? 8'b00000001 :
                                        8'b00000000 ;

assign ml[0:7] = (s[5:7] == 3'b000) ? 8'b10000000 :
                 (s[5:7] == 3'b001) ? 8'b01000000 :
                 (s[5:7] == 3'b010) ? 8'b00100000 :
                 (s[5:7] == 3'b011) ? 8'b00010000 :
                 (s[5:7] == 3'b100) ? 8'b00001000 :
                 (s[5:7] == 3'b101) ? 8'b00000100 :
                 (s[5:7] == 3'b110) ? 8'b00000010 :
                                      8'b00000001;

genvar i;
generate for (i=0; i<=7; i=i+1)
   begin : msk
      assign a1[8*i:8*i+7] =  a[8*i:8*i+7] & ml[0:7];
      assign a2[8*i:8*i+7] = a1[8*i:8*i+7] & {8{mh[i]}};
   end
endgenerate

assign y = |a2;

endmodule