module  add32_add_sub_nq7
	( 
	dataa,
	datab,
	result) /* synthesis synthesis_clearbox=1 */;
	input   [7:0]  dataa;
	input   [7:0]  datab;
	output   [7:0]  result;

	wire  [7:0]   wire_add_sub_cella_combout;
	wire  [0:0]   wire_add_sub_cella_0cout;
	wire  [0:0]   wire_add_sub_cella_1cout;
	wire  [0:0]   wire_add_sub_cella_2cout;
	wire  [0:0]   wire_add_sub_cella_3cout;
	wire  [0:0]   wire_add_sub_cella_4cout;
	wire  [0:0]   wire_add_sub_cella_5cout;
	wire  [0:0]   wire_add_sub_cella_6cout;
	wire  [7:0]   wire_add_sub_cella_dataa;
	wire  [7:0]   wire_add_sub_cella_datab;

	stratix_lcell   add_sub_cella_0
	( 
	.cin(1'b0),
	.combout(wire_add_sub_cella_combout[0:0]),
	.cout(wire_add_sub_cella_0cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[0:0]),
	.datab(wire_add_sub_cella_datab[0:0]));
	defparam
		add_sub_cella_0.cin_used = "true",
		add_sub_cella_0.lut_mask = "96e8",
		add_sub_cella_0.operation_mode = "arithmetic",
		add_sub_cella_0.sum_lutc_input = "cin",
		add_sub_cella_0.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_1
	( 
	.cin(wire_add_sub_cella_0cout[0:0]),
	.combout(wire_add_sub_cella_combout[1:1]),
	.cout(wire_add_sub_cella_1cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[1:1]),
	.datab(wire_add_sub_cella_datab[1:1]));
	defparam
		add_sub_cella_1.cin_used = "true",
		add_sub_cella_1.lut_mask = "96e8",
		add_sub_cella_1.operation_mode = "arithmetic",
		add_sub_cella_1.sum_lutc_input = "cin",
		add_sub_cella_1.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_2
	( 
	.cin(wire_add_sub_cella_1cout[0:0]),
	.combout(wire_add_sub_cella_combout[2:2]),
	.cout(wire_add_sub_cella_2cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[2:2]),
	.datab(wire_add_sub_cella_datab[2:2]));
	defparam
		add_sub_cella_2.cin_used = "true",
		add_sub_cella_2.lut_mask = "96e8",
		add_sub_cella_2.operation_mode = "arithmetic",
		add_sub_cella_2.sum_lutc_input = "cin",
		add_sub_cella_2.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_3
	( 
	.cin(wire_add_sub_cella_2cout[0:0]),
	.combout(wire_add_sub_cella_combout[3:3]),
	.cout(wire_add_sub_cella_3cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[3:3]),
	.datab(wire_add_sub_cella_datab[3:3]));
	defparam
		add_sub_cella_3.cin_used = "true",
		add_sub_cella_3.lut_mask = "96e8",
		add_sub_cella_3.operation_mode = "arithmetic",
		add_sub_cella_3.sum_lutc_input = "cin",
		add_sub_cella_3.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_4
	( 
	.cin(wire_add_sub_cella_3cout[0:0]),
	.combout(wire_add_sub_cella_combout[4:4]),
	.cout(wire_add_sub_cella_4cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[4:4]),
	.datab(wire_add_sub_cella_datab[4:4]));
	defparam
		add_sub_cella_4.cin_used = "true",
		add_sub_cella_4.lut_mask = "96e8",
		add_sub_cella_4.operation_mode = "arithmetic",
		add_sub_cella_4.sum_lutc_input = "cin",
		add_sub_cella_4.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_5
	( 
	.cin(wire_add_sub_cella_4cout[0:0]),
	.combout(wire_add_sub_cella_combout[5:5]),
	.cout(wire_add_sub_cella_5cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[5:5]),
	.datab(wire_add_sub_cella_datab[5:5]));
	defparam
		add_sub_cella_5.cin_used = "true",
		add_sub_cella_5.lut_mask = "96e8",
		add_sub_cella_5.operation_mode = "arithmetic",
		add_sub_cella_5.sum_lutc_input = "cin",
		add_sub_cella_5.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_6
	( 
	.cin(wire_add_sub_cella_5cout[0:0]),
	.combout(wire_add_sub_cella_combout[6:6]),
	.cout(wire_add_sub_cella_6cout[0:0]),
	.dataa(wire_add_sub_cella_dataa[6:6]),
	.datab(wire_add_sub_cella_datab[6:6]));
	defparam
		add_sub_cella_6.cin_used = "true",
		add_sub_cella_6.lut_mask = "96e8",
		add_sub_cella_6.operation_mode = "arithmetic",
		add_sub_cella_6.sum_lutc_input = "cin",
		add_sub_cella_6.lpm_type = "stratix_lcell";
	stratix_lcell   add_sub_cella_7
	( 
	.cin(wire_add_sub_cella_6cout[0:0]),
	.combout(wire_add_sub_cella_combout[7:7]),
	.dataa(wire_add_sub_cella_dataa[7:7]),
	.datab(wire_add_sub_cella_datab[7:7]));
	defparam
		add_sub_cella_7.cin_used = "true",
		add_sub_cella_7.lut_mask = "9696",
		add_sub_cella_7.operation_mode = "normal",
		add_sub_cella_7.sum_lutc_input = "cin",
		add_sub_cella_7.lpm_type = "stratix_lcell";
	assign
		wire_add_sub_cella_dataa = dataa,
		wire_add_sub_cella_datab = datab;
	assign
		result = wire_add_sub_cella_combout;
endmodule //add32_add_sub_nq7