dakies/OSS_Verilog huggingface dataset:
module vga_mouse(
	input clk,rst_n,
	inout ps2c,ps2d,
	output reg[4:0] vga_out_r,
	output reg[5:0] vga_out_g,
	output reg[4:0] vga_out_b,
	output vga_out_vs,vga_out_hs
    );
	 localparam SIZE=16; //mouse pointer width and height
	 
	 wire[8:0] x,y;
	 wire[2:0] btn;
	 wire m_done_tick;
	 wire video_on;
	 wire mouse_on;
	 wire[11:0] pixel_x,pixel_y;
	 reg[9:0] mouse_x_q=0,mouse_x_d; //stores x-value(left part) of mouse, 
	 reg[9:0] mouse_y_q=0,mouse_y_d; //stores y-value(upper part) of mouse, 
	 reg[2:0] mouse_color_q=0,mouse_color_d; //stores current mouse color and can be changed by right/left click 
	 
	 //register operation
	 always @(posedge clk,negedge rst_n) begin
		if(!rst_n) begin
			mouse_x_q<=0;
			mouse_y_q<=0;
			mouse_color_q<=0;
		end
		else begin
			mouse_x_q<=mouse_x_d;
			mouse_y_q<=mouse_y_d;
			mouse_color_q<=mouse_color_d;
		end
	 end
	 
	 //logic for updating mouse location(by dragging the mouse) and mouse pointer color(by left/right click)
	 always @* begin
		mouse_x_d=mouse_x_q;
		mouse_y_d=mouse_y_q;
		mouse_color_d=mouse_color_q;
		if(m_done_tick) begin
			mouse_x_d=x[8]? mouse_x_q - 1 -{~{x[7:0]}} : mouse_x_q+x[7:0] ; //new x value of pointer
			mouse_y_d=y[8]? mouse_y_q + 1 +{~{y[7:0]}} : mouse_y_q-y[7:0] ; //new y value of pointer
			
			mouse_x_d=(mouse_x_d>640)? (x[8]? 640:0): mouse_x_d; //wraps around when reaches border
			mouse_y_d=(mouse_y_d>480)? (y[8]? 0:480): mouse_y_d; //wraps around when reaches border
			
			
			if(btn[1]) mouse_color_d=mouse_color_q+1;//right click to change color(increment)
			else if(btn[0]) mouse_color_d=mouse_color_q-1;//left click to change color(decrement)
		end
	 end
	 
	 assign mouse_on = (mouse_x_q<=pixel_x) && (pixel_x<=mouse_x_q+SIZE) && (mouse_y_q<=pixel_y) && (pixel_y<=mouse_y_q+SIZE);
	 
	 //display logic
	 always @* begin
				vga_out_r=0;
				vga_out_g=0;
				vga_out_b=0;
		if(video_on) begin
			if(mouse_on) begin //mouse color
				vga_out_r={5{mouse_color_q[0]}};
				vga_out_g={6{mouse_color_q[1]}};
				vga_out_b={5{mouse_color_q[2]}};
			end
			else begin //background color
				vga_out_g=6'b111_111;
				vga_out_b=5'b111_11;
			end
		end
	 end
	 

	 
	 //module instantiations
	 
	 dcm_25MHz m0
   (// Clock in ports
    .clk(clk),      // IN
    // Clock out ports
    .clk_out(clk_out),     // OUT
    // Status and control signals
    .RESET(RESET),// IN
    .LOCKED(LOCKED));      // OUT
	 
	 
	 mouse m1
	(
		.clk(clk),
		.rst_n(rst_n),
		.ps2c(ps2c),
		.ps2d(ps2d),
		.x(x),
		.y(y),
		.btn(btn),
		.m_done_tick(m_done_tick)
    );
	 
	vga_core m2 //clock must be 25MHz for 640x480 
	(
		.clk(clk_out),
		.rst_n(rst_n), 
		.hsync(vga_out_hs),
		.vsync(vga_out_vs),
		.video_on(video_on),
		.pixel_x(pixel_x),
		.pixel_y(pixel_y)
    );	
	 


endmodule
module babbage_diff_TB;

	// Inputs
	reg clk;
	reg rst_n;
	reg start;
	reg [5:0] i;
	integer index;
	// Outputs
	wire [17:0] ans;
	wire ready;
	wire done_tick;
	// Instantiate the Unit Under Test (UUT)
	babbage_diff uut (
		.clk(clk), 
		.rst_n(rst_n), 
		.start(start), 
		.i(i), 
		.ans(ans), 
		.ready(ready), 
		.done_tick(done_tick)
	);
	always begin
	clk=0;
	#5;
	clk=1;
	#5;
	end

	initial begin
		clk = 0;
		rst_n = 1;
		start = 0;
		i = 0;

		@(negedge clk);
		for(index=0;index<=63;index=index+1) begin
			start=1;
			i=index;
			wait(done_tick);
			start=0;
			@(negedge clk);
			$display("f(%0d) -> %0d",index,ans);
			repeat(5)@(negedge clk);
		 end
		$stop;
		

	end
      
endmodule
module babbage_diff_TEST(
	input clk,rst_n,
	input sw0,sw1, //active low
	output[7:0] seg_out,
	output[5:0] sel_out
    );
	 //FSM state declarations
	 localparam[1:0] idle=2'd0,
							babbage=2'd1,
							bin2bcd=2'd2;
	 reg[1:0] state_reg,state_nxt;
	 reg[5:0] mod64_reg,mod64_nxt;
	 reg start_babbage,start_bin2bcd;
	 wire done_babbage,done_bin2bcd;
	 wire sw_redg;
	 wire[17:0] bin;
	 wire[3:0] dig0,dig1,dig2,dig3,dig4,dig5;
	 wire[3:0] mod_dig0,mod_dig1;
	 reg[3:0] in0,in1,in2,in3,in4,in5;
	 wire sw0_hi;
	 assign sw0_hi=!sw0;
	 
	 //FSM register operations
	 always @(posedge clk,negedge rst_n) begin
		if(!rst_n) begin
			state_reg<=idle;
			mod64_reg<=0;
		end
		else begin
			state_reg<=state_nxt;
			mod64_reg<=mod64_nxt;
		end
	 end
	 //FSM next-state logics
	 always @* begin
		state_nxt=state_reg;
		mod64_nxt=mod64_reg;
		start_babbage=0;
		start_bin2bcd=0;
		case(state_reg)
			   idle: begin
							if(sw_redg) begin
								mod64_nxt=mod64_reg+1;
								start_babbage=1;
								state_nxt=babbage;
							end
						end
			babbage: if(done_babbage) begin
							start_bin2bcd=1;
							state_nxt=bin2bcd;
						end
			bin2bcd: if(done_bin2bcd) state_nxt=idle;
			default: state_nxt=idle;		
		endcase	
	 end
	 
	 //debounce
	debounce_explicit deb(
		.clk(clk),
		.rst_n(rst_n),
		.sw(sw0_hi),
		.db_level(),
		.db_tick(sw_redg)
    );
	 
	 //module instantiations
	babbage_diff m0
	(
		.clk(clk),
		.rst_n(rst_n),
		.start(start_babbage),
		.i(mod64_reg), //6 bit value f "n"	
		.ans(bin),
		.ready(),
		.done_tick(done_babbage)
    );	
	bin2bcd m1 //for mod64 counter value
	(
		.clk(clk),
		.rst_n(rst_n),
		.start(start_bin2bcd),
		.bin(mod64_reg),//limit is 6 digit of bcd
		.ready(),
		.done_tick(),
		.dig0(mod_dig0),
		.dig1(mod_dig1),
		.dig2(),
		.dig3(),
		.dig4(),
		.dig5()
    );
	 bin2bcd m2 //for babbage value
	(
		.clk(clk),
		.rst_n(rst_n),
		.start(start_bin2bcd),
		.bin(bin),//limit is 6 digit of bcd
		.ready(),
		.done_tick(done_bin2bcd),
		.dig0(dig0),
		.dig1(dig1),
		.dig2(dig2),
		.dig3(dig3),
		.dig4(dig4),
		.dig5(dig5)
    );
	LED_mux m3
	(
		.clk(clk),
		.rst(rst_n),
		.in0({1'b0,in0}),
		.in1({1'b0,in1}),
		.in2({1'b0,in2}),
		.in3({1'b0,in3}),
		.in4({1'b0,in4}),
		.in5({1'b0,in5}), //format: {dp,hex[3:0]}
		.seg_out(seg_out),
		.sel_out(sel_out)
    );
	 
	 //sw1 chooses which value to display: babbage value or counter(n) value
	 always  @* begin
		if(sw1) begin
			in0=mod_dig0;
			in1=mod_dig1;
			in2=0;
			in3=0;
			in4=0;
			in5=0;
		end
		else begin
			in0=dig0;
			in1=dig1;
			in2=dig2;
			in3=dig3;
			in4=dig4;
			in5=dig5;
		end
	 end
	 
	 
	 
	 
	 
endmodule
module babbage_diff(
	input clk,rst_n,
	input start,
	input[5:0] i, //6 bit value f "n"	
	output[17:0] ans,
	output reg ready,done_tick
    );
	 //babbage function values(3-order polynomial)
	 localparam f0=1,
					g1=5,
					h2=10,
					c=6;
	 //FSM state declarations
	 localparam[1:0] idle=2'd0,
							op=2'd1,
							done=2'd2;
	 reg[1:0] state_reg,state_nxt;
	 reg[17:0] f_reg,f_nxt;
	 reg[17:0] g_reg,g_nxt;
	 reg[17:0] h_reg,h_nxt;
	 reg[5:0] n_reg,n_nxt;
	 //FSM register operations
	 always @(posedge clk,negedge rst_n) begin
		 if(!rst_n) begin
			state_reg<=idle;
			f_reg<=0;
			g_reg<=0;
			h_reg<=0;
			n_reg<=0;		
		 end
		 else begin
			state_reg<=state_nxt;
			f_reg<=f_nxt;
			g_reg<=g_nxt;
			h_reg<=h_nxt;
			n_reg<=n_nxt;	
		 end	 
	 end
	 //FSM next-state logics
	 always @* begin
		state_nxt=state_reg;
		f_nxt=f_reg;
		g_nxt=g_reg;
		h_nxt=h_reg;
		n_nxt=n_reg;
		ready=0;
		done_tick=0;
		case(state_reg)
			  idle: begin
							ready=1;
							if(start==1) begin
								f_nxt=f0;
								g_nxt=0;
								h_nxt=0;
								n_nxt=0;
								state_nxt=op;
							end
					  end
			    op: begin
							if(n_reg==i) state_nxt=done;
							else begin
								n_nxt=n_reg+1;
								case(n_nxt)
									1: begin
											g_nxt=g1;
											f_nxt=g_nxt+f_reg;
										 end
									2: begin
											h_nxt=h2;
											g_nxt=h_nxt+g_reg;
											f_nxt=g_nxt+f_reg;
										end
									default: begin
											h_nxt=c+h_reg;
											g_nxt=h_nxt+g_reg;
											f_nxt=g_nxt+f_reg;
									end
								endcase
							end
					  end
			  done: begin
							done_tick=1;
							state_nxt=idle;
					  end
			default: state_nxt=idle;
		endcase
	 end
	 assign ans=f_reg;


endmodule
module soc_fpga_ram(
  PortAClk,
  PortAAddr,
  PortADataIn,
  PortAWriteEnable,
//  PortAChipEnable,
  PortADataOut
);

parameter  DATAWIDTH = 2;
parameter  ADDRWIDTH = 2;

input                     PortAClk;
input   [(ADDRWIDTH-1):0] PortAAddr;
input   [(DATAWIDTH-1):0] PortADataIn;
input                     PortAWriteEnable;
//input                     PortAChipEnable;
output  [(DATAWIDTH-1):0] PortADataOut; 

parameter  MEMDEPTH = 2**(ADDRWIDTH);

reg [(DATAWIDTH-1):0] mem [(MEMDEPTH-1):0] /* synthesis syn_ramstyle = "no_rw_check" */;
reg [(DATAWIDTH-1):0] PortADataOut;

always @(posedge PortAClk)
begin
  if(PortAWriteEnable)
  begin
    mem[PortAAddr]  <= PortADataIn;
  end
  else
  begin
    PortADataOut    <= mem[PortAAddr];
  end
end

//wire [(DATAWIDTH-1):0] tt;
//assign t = mem[PortAAddr];
//always @(posedge PortAClk)
//begin
//  if(PortAWriteEnable)
//  begin
//    PortADataOut    <= PortADataIn;
//  end
//  else
//  begin
//    PortADataOut    <= mem[PortAAddr];
//  end
//end

endmodule
module soc_gated_clk_cell(
  clk_in,
  external_en,
  SE,
  clk_out
);

input  clk_in;
input  external_en ;
input  SE;
output clk_out;

//reg    clk_en_af_latch;
//always @(clk_in or external_en)
//begin
//  if(!clk_in)
//    clk_en_af_latch <= external_en;
//end
//
//reg clk_en ;
//always @ (SE or clk_en_af_latch )
//begin
//    clk_en <= clk_en_af_latch || SE ;
//end
assign clk_out = clk_in;
   
endmodule
module cr_pwrm_top_dummy(
  pwrm_cpu_bus_peak_power_limit_en
);

// &Ports; @23
output       pwrm_cpu_bus_peak_power_limit_en; 

// &Regs; @24

// &Wires; @25
wire         pwrm_cpu_bus_peak_power_limit_en; 


//assign pwrm_cpu_avrg_power_inst_issue = 1'b1;
//assign pwrm_cpu_peak_power_limit_en   = 1'b0;

assign pwrm_cpu_bus_peak_power_limit_en = 1'b0;
//assign pwrm_cpu_inst_peak_power_limit_en = 1'b0;

// &ModuleEnd; @33
endmodule
module cr_cp0_randclk(
  randclk_psr_mod_en_w13
);

// &Ports; @25
output       randclk_psr_mod_en_w13; 

// &Regs; @26

// &Wires; @27
wire         randclk_psr_mod_en_w13; 


// &Force("bus","seu_cp0_randclk_mod_en",31,0); @31

//assign randclk_oreg_vec_mod_en_w22 = 1'b0;
//assign randclk_psr_c_mod_en_w2     = 1'b0;
assign randclk_psr_mod_en_w13      = 1'b0;
//assign randclk_psr_epsr_mod_en_w46 = 1'b0;


// &ModuleEnd; @47
endmodule
module cr_clkrst_top(
  cpurst_b,
  forever_cpuclk,
  forever_cpuclk_nogated,
  forever_jtgclk,
  hadrst_b,
  pad_cpu_rst_b,
  pad_had_jtg_tclk,
  pad_had_jtg_trst_b,
  pad_had_rst_b,
  pad_yy_test_mode,
  pll_core_cpuclk,
  trst_b
);

// &Ports; @23
input        pad_cpu_rst_b;         
input        pad_had_jtg_tclk;      
input        pad_had_jtg_trst_b;    
input        pad_had_rst_b;         
input        pad_yy_test_mode;      
input        pll_core_cpuclk;       
output       cpurst_b;              
output       forever_cpuclk;        
output       forever_cpuclk_nogated; 
output       forever_jtgclk;        
output       hadrst_b;              
output       trst_b;                

// &Regs; @24

// &Wires; @25
wire         cpurst_b;              
wire         forever_cpuclk;        
wire         forever_cpuclk_nogated; 
wire         forever_jtgclk;        
wire         hadrst_b;              
wire         pad_cpu_rst_b;         
wire         pad_had_jtg_tclk;      
wire         pad_had_jtg_trst_b;    
wire         pad_had_rst_b;         
wire         pad_yy_test_mode;      
wire         pll_core_cpuclk;       
wire         trst_b;                


// &Force("output", "forever_cpuclk"); @27
// &Force("output", "forever_cpuclk_nogated"); @29

//----------------------------------------------------------
// clock top
//----------------------------------------------------------
// &Instance("cr_clk_top"); @35
cr_clk_top  x_cr_clk_top (
  .forever_cpuclk         (forever_cpuclk        ),
  .forever_cpuclk_nogated (forever_cpuclk_nogated),
  .forever_jtgclk         (forever_jtgclk        ),
  .pad_had_jtg_tclk       (pad_had_jtg_tclk      ),
  .pad_yy_test_mode       (pad_yy_test_mode      ),
  .pll_core_cpuclk        (pll_core_cpuclk       )
);


//----------------------------------------------------------
// reset top
//----------------------------------------------------------
// &Instance("cr_rst_top"); @40
cr_rst_top  x_cr_rst_top (
  .cpurst_b           (cpurst_b          ),
  .hadrst_b           (hadrst_b          ),
  .pad_cpu_rst_b      (pad_cpu_rst_b     ),
  .pad_had_jtg_trst_b (pad_had_jtg_trst_b),
  .pad_had_rst_b      (pad_had_rst_b     ),
  .pad_yy_test_mode   (pad_yy_test_mode  ),
  .trst_b             (trst_b            )
);

// &ModuleEnd; @41
endmodule
module_en,
  local_en,
  external_en,
  pad_yy_gate_clk_en_b,
  clk_out
);

input  clk_in;
input  global_en;
input  module_en;
input  local_en;
input  external_en;
input  pad_yy_gate_clk_en_b;
output clk_out;

wire   clk_en_bf_latch;
wire   SE;

assign clk_en_bf_latch = (global_en && (module_en || local_en)) || external_en ;

// SE driven from primary input, held constant
assign SE	       = pad_yy_gate_clk_en_b;
 
// //   &Connect(    .clk_in           (clk_in), @50
// //                .SE               (SE), @51
// //                .external_en      (clk_en_bf_latch), @52
// //                .clk_out          (clk_out) @53
// //                ) ; @54
assign clk_out = clk_in;

endmodule
module cr_clk_top(
  forever_cpuclk,
  forever_cpuclk_nogated,
  forever_jtgclk,
  pad_had_jtg_tclk,
  pad_yy_test_mode,
  pll_core_cpuclk
);

// &Ports; @24
input        pad_had_jtg_tclk;      
input        pad_yy_test_mode;      
input        pll_core_cpuclk;       
output       forever_cpuclk;        
output       forever_cpuclk_nogated; 
output       forever_jtgclk;        

// &Regs; @25

// &Wires; @26
wire         forever_cpuclk;        
wire         forever_cpuclk_nogated; 
wire         forever_jtgclk;        
wire         pad_had_jtg_tclk;      
wire         pad_yy_test_mode;      
wire         pll_core_cpuclk;       


assign forever_jtgclk = pad_had_jtg_tclk;
assign forever_cpuclk = pad_yy_test_mode ? pad_had_jtg_tclk : pll_core_cpuclk;
assign forever_cpuclk_nogated = pad_yy_test_mode ? pad_had_jtg_tclk : pll_core_cpuclk;

// &ModuleEnd; @34
endmodule
module cr_iu_gated_clk_reg_timing(
  cp0_yy_clk_en,
  forever_cpuclk,
  pad_yy_gate_clk_en_b,
  write_data,
  x_randclk_reg_mod_en_w32,
  x_reg_dout,
  x_write_en
);

// &Ports; @24
input           cp0_yy_clk_en;           
input           forever_cpuclk;          
input           pad_yy_gate_clk_en_b;    
input   [31:0]  write_data;              
input           x_randclk_reg_mod_en_w32; 
input           x_write_en;              
output  [31:0]  x_reg_dout;              

// &Regs; @25
reg     [31:0]  x_reg_dout;              

// &Wires; @26
wire            cp0_yy_clk_en;           
wire            forever_cpuclk;          
wire            pad_yy_gate_clk_en_b;    
wire            reg_clk_en;              
wire            reg_cpuclk;              
wire    [31:0]  write_data;              
wire    [31:0]  write_in_data;           
wire            write_in_en;             
wire            x_randclk_reg_mod_en_w32; 
wire            x_write_en;              


//==============================================================================
//                      register with only 1 write port
//==============================================================================
assign reg_clk_en = write_in_en;
// &Instance("gated_clk_cell", "x_reg_gated_clk"); @32
gated_clk_cell  x_reg_gated_clk (
  .clk_in                   (forever_cpuclk          ),
  .clk_out                  (reg_cpuclk              ),
  .external_en              (1'b0                    ),
  .global_en                (cp0_yy_clk_en           ),
  .local_en                 (reg_clk_en              ),
  .module_en                (x_randclk_reg_mod_en_w32),
  .pad_yy_gate_clk_en_b     (pad_yy_gate_clk_en_b    )
);

// &Connect(.clk_in      (forever_cpuclk), @33
//          .external_en (1'b0), @34
//          .global_en   (cp0_yy_clk_en), @35
//          .module_en   (x_randclk_reg_mod_en_w32), @36
//          .local_en    (reg_clk_en), @37
//          .i_tst_en    (i_tst_en), @38
//          .clk_out     (reg_cpuclk)); @39

//==========================================================
//                    Write Port
//==========================================================
assign write_in_en = x_write_en;
assign write_in_data[31:0] = write_data[31:0];

// &Force("output", "x_reg_dout"); @54

always @(posedge reg_cpuclk)
begin
  if(write_in_en)
    x_reg_dout[31:0] <= write_in_data[31:0];
  else
    x_reg_dout[31:0] <= x_reg_dout[31:0];
end

// &Force("output", "x_reg_verify"); @66

// &Force("output", "x_reg_dout_pol"); @79

// &ModuleEnd; @90
endmodule
module cr_iu_randclk(
  randclk_mad_mod_en_w2,
  randclk_oper_gpr_mod_en_w32,
  randclk_pcgen_mod_en_w32,
  randclk_retire_mod_en_w2,
  randclk_wb_buf_mod_en_w32,
  randclk_wb_ctrl_mod_en_w2,
  randclk_wb_idx_mod_en_w5
);

// &Ports; @25
output          randclk_mad_mod_en_w2;      
output  [20:0]  randclk_oper_gpr_mod_en_w32; 
output          randclk_pcgen_mod_en_w32;   
output          randclk_retire_mod_en_w2;   
output          randclk_wb_buf_mod_en_w32;  
output          randclk_wb_ctrl_mod_en_w2;  
output          randclk_wb_idx_mod_en_w5;   

// &Regs; @26

// &Wires; @27
wire            randclk_mad_mod_en_w2;      
wire    [20:0]  randclk_oper_gpr_mod_en_w32; 
wire            randclk_pcgen_mod_en_w32;   
wire            randclk_retire_mod_en_w2;   
wire            randclk_wb_buf_mod_en_w32;  
wire            randclk_wb_ctrl_mod_en_w2;  
wire            randclk_wb_idx_mod_en_w5;   


// &Force("bus","seu_iu_randclk_mod_en",31,0); @31

//assign randclk_branch_mod_en_w2          = 1'b0;
assign randclk_mad_mod_en_w2             = 1'b0;
assign randclk_oper_gpr_mod_en_w32[20:0] = 21'b0;
assign randclk_pcgen_mod_en_w32          = 1'b0;
assign randclk_retire_mod_en_w2          = 1'b0;
//assign randclk_vector_mod_en_w3          = 1'b0;
assign randclk_wb_buf_mod_en_w32         = 1'b0;
assign randclk_wb_ctrl_mod_en_w2         = 1'b0;
assign randclk_wb_idx_mod_en_w5          = 1'b0;
//assign randclk_wb_pc_mod_en_w31          = 1'b0;


// &ModuleEnd; @82
endmodule
module cr_iu_gated_clk_reg(
  cp0_yy_clk_en,
  forever_cpuclk,
  pad_yy_gate_clk_en_b,
  write_data,
  x_randclk_reg_mod_en_w32,
  x_reg_dout,
  x_write_en
);

// &Ports; @24
input           cp0_yy_clk_en;           
input           forever_cpuclk;          
input           pad_yy_gate_clk_en_b;    
input   [31:0]  write_data;              
input           x_randclk_reg_mod_en_w32; 
input           x_write_en;              
output  [31:0]  x_reg_dout;              

// &Regs; @25
reg     [31:0]  x_reg_dout;              

// &Wires; @26
wire            cp0_yy_clk_en;           
wire            forever_cpuclk;          
wire            pad_yy_gate_clk_en_b;    
wire            reg_clk_en;              
wire            reg_cpuclk;              
wire    [31:0]  write_data;              
wire    [31:0]  write_in_data;           
wire            write_in_en;             
wire            x_randclk_reg_mod_en_w32; 
wire            x_write_en;              


//==============================================================================
//                      register with only 1 write port
//==============================================================================
assign reg_clk_en = write_in_en;
// &Instance("gated_clk_cell", "x_reg_gated_clk"); @32
gated_clk_cell  x_reg_gated_clk (
  .clk_in                   (forever_cpuclk          ),
  .clk_out                  (reg_cpuclk              ),
  .external_en              (1'b0                    ),
  .global_en                (cp0_yy_clk_en           ),
  .local_en                 (reg_clk_en              ),
  .module_en                (x_randclk_reg_mod_en_w32),
  .pad_yy_gate_clk_en_b     (pad_yy_gate_clk_en_b    )
);

// &Connect(.clk_in      (forever_cpuclk), @33
//          .external_en (1'b0), @34
//          .global_en   (cp0_yy_clk_en), @35
//          .module_en   (x_randclk_reg_mod_en_w32), @36
//          .local_en    (reg_clk_en), @37
//          .i_tst_en    (i_tst_en), @38
//          .clk_out     (reg_cpuclk)); @39

//==========================================================
//                    Write Port
//==========================================================
assign write_in_en = x_write_en;
assign write_in_data[31:0] = write_data[31:0];

// &Force("output", "x_reg_dout"); @54

always @(posedge reg_cpuclk)
begin
  if(write_in_en)
    x_reg_dout[31:0] <= write_in_data[31:0];
  else
    x_reg_dout[31:0] <= x_reg_dout[31:0];
end

// &Force("output", "x_reg_verify"); @66

// &Force("output", "x_reg_dout_pol"); @79

// &ModuleEnd; @90
endmodule
module cr_iu_hs_split(
  hs_split_iu_ctrl_inst_vld,
  hs_split_iu_dp_inst_op,
  hs_split_iu_hs_retire_mask,
  hs_split_iu_hs_switch_se,
  hs_split_iu_nsinst_gpr_rst_b,
  hs_split_iu_unstack_chgflw,
  iu_hs_split_ex_stall,
  iu_ifu_spcu_int_en,
  split_ifctrl_hs_stall,
  split_ifctrl_hs_stall_part
);

// &Ports; @23
input           iu_hs_split_ex_stall;        
input           iu_ifu_spcu_int_en;          
output          hs_split_iu_ctrl_inst_vld;   
output  [31:0]  hs_split_iu_dp_inst_op;      
output          hs_split_iu_hs_retire_mask;  
output          hs_split_iu_hs_switch_se;    
output          hs_split_iu_nsinst_gpr_rst_b; 
output          hs_split_iu_unstack_chgflw;  
output          split_ifctrl_hs_stall;       
output          split_ifctrl_hs_stall_part;  

// &Regs; @24

// &Wires; @25
wire            hs_split_iu_ctrl_inst_vld;   
wire    [31:0]  hs_split_iu_dp_inst_op;      
wire            hs_split_iu_hs_retire_mask;  
wire            hs_split_iu_hs_switch_se;    
wire            hs_split_iu_nsinst_gpr_rst_b; 
wire            hs_split_iu_unstack_chgflw;  
wire            split_ifctrl_hs_stall;       
wire            split_ifctrl_hs_stall_part;  


//==============================================================================
//                      input value when no configuration
//==============================================================================
// &Force("output","split_ifctrl_hs_stall"); @30
// &Force("input","iu_ifu_spcu_int_en"); @31
// &Instance("gated_clk_cell", "x_split_cnt_upd_clkhdr"); @36
// &Connect(.clk_in(forever_cpuclk), @37
//          .external_en(1'b0), @38
//          .global_en(cp0_yy_clk_en), @39
//          .module_en(1'b0), @40
//          .local_en(split_cnt_upd_en), @41
//          .clk_out(split_cnt_upd_clk) @42
//         ); @43
// &Instance("gated_clk_cell", "x_sm_upd_clkhdr"); @46
// &Connect(.clk_in(forever_cpuclk), @47
//          .external_en(1'b0), @48
//          .global_en(cp0_yy_clk_en), @49
//          .module_en(1'b0), @50
//          .local_en(sm_upd_en), @51
//          .clk_out(sm_upd_clk) @52
//         ); @53
// &CombBeg; @156
// &CombEnd; @263
// &CombBeg; @363
// &CombEnd; @371
assign hs_split_iu_nsinst_gpr_rst_b = 1'b1; 
assign hs_split_iu_hs_retire_mask   = 1'b0; 
assign hs_split_iu_unstack_chgflw   = 1'b0;
assign hs_split_iu_hs_switch_se     = 1'b0;
assign split_ifctrl_hs_stall_part   = 1'b0;
assign split_ifctrl_hs_stall        = 1'b0;
assign hs_split_iu_ctrl_inst_vld    = 1'b0;
//assign hs_split_iu_ex_cr_oper       = 1'b0;
//assign hs_split_iu_hs_retire_mask   = 1'b0;
assign hs_split_iu_dp_inst_op[31:0] = 32'b0;
// &Force("input","iu_hs_split_ex_stall"); @417
// 1. check fail, stall ibuf
// 2. speculation fail, stall ibuf
//assign split_ifctrl_int_acc_stall = int_spcu_check_fail 
//                                 || iu_ifu_spcu_error_without_misalign 
//                                    && int_spcu_sm_not_idle; 

//==========================================================
//               Interface to IF Data Path
//==========================================================
//the data path signal
// &ModuleEnd; @429
endmodule
module cr_ifu_randclk(
  randclk_ibuf_entry_data_mod_en_w16,
  randclk_ibuf_pop_mod_en_w3,
  randclk_ibuf_push_mod_en_w3
);

// &Ports; @25
output  [3:0]  randclk_ibuf_entry_data_mod_en_w16; 
output         randclk_ibuf_pop_mod_en_w3;        
output         randclk_ibuf_push_mod_en_w3;       

// &Regs; @26

// &Wires; @27
wire    [3:0]  randclk_ibuf_entry_data_mod_en_w16; 
wire           randclk_ibuf_pop_mod_en_w3;        
wire           randclk_ibuf_push_mod_en_w3;       


// &Force("bus","seu_ifu_randclk_mod_en",31,0); @31

assign randclk_ibuf_push_mod_en_w3             = 1'b0;
assign randclk_ibuf_pop_mod_en_w3              = 1'b0;
assign randclk_ibuf_entry_data_mod_en_w16[3:0] = 4'b0;
//assign randclk_ibuf_acc_err_mod_en_w3          = 1'b0;



// &ModuleEnd; @77
endmodule
module clic_kid_golden_ports(
  pad_clic_int_vld
);

// &Wires; @3

// &Ports; @4
input   [63:0]  pad_clic_int_vld; 

// &Force("input", "pad_clic_int_vld"); &Force("bus", "pad_clic_int_vld", `CLIC_INTNUM-17, 0); @6
// &ModuleEnd; @8
endmodule
module cr_coretim_top_dummy(
  iu_yy_xx_dbgon
);

// &Ports; @24
input        iu_yy_xx_dbgon; 

// &Regs; @25

// &Wires; @26



// //&Force("input", "pad_ctim_refclk"); @29
// &Force("input", "iu_yy_xx_dbgon"); @30
// //&Force("output", "ctim_pad_int_vld"); @31

// &ModuleEnd; @33
endmodule
module cr_rst_top(
  cpurst_b,
  hadrst_b,
  pad_cpu_rst_b,
  pad_had_jtg_trst_b,
  pad_had_rst_b,
  pad_yy_test_mode,
  trst_b
);

// &Ports; @23
input        pad_cpu_rst_b;     
input        pad_had_jtg_trst_b; 
input        pad_had_rst_b;     
input        pad_yy_test_mode;  
output       cpurst_b;          
output       hadrst_b;          
output       trst_b;            

// &Regs; @24

// &Wires; @25
wire         cpurst_b;          
wire         hadrst_b;          
wire         pad_cpu_rst_b;     
wire         pad_had_jtg_trst_b; 
wire         pad_had_rst_b;     
wire         pad_yy_test_mode;  
wire         trst_b;            


//cpu reset 
assign cpurst_b = pad_yy_test_mode ? pad_had_jtg_trst_b : pad_cpu_rst_b;

//had reset
//signal for reset cpuclk domain reg in HAD
assign hadrst_b = pad_yy_test_mode ? pad_had_jtg_trst_b : pad_had_rst_b;
//signal for reset JTAG in HAD
assign trst_b = pad_had_jtg_trst_b;

// &ModuleEnd; @36
endmodule
module cr_lsu_randclk(
  randclk_dp_size_buf_mod_en_w5
);

// &Ports; @25
output       randclk_dp_size_buf_mod_en_w5; 

// &Regs; @26

// &Wires; @27
wire         randclk_dp_size_buf_mod_en_w5; 


// &Force("input","seu_lsu_randclk_mod_en"); @31
// &Force("bus","seu_lsu_randclk_mod_en",31,0); @32
//assign randclk_ctrl_req_mod_en_w2 = 1'b0;

assign randclk_dp_size_buf_mod_en_w5 = 1'b0;


// &ModuleEnd; @76
endmodule
module cr_clic_sel(
  // input
  data_in,
  sel_in_onehot,
  // output
  data_out
);

parameter DATA_WIDTH   = 32;
parameter SEL_NUM      = 256;

input  [DATA_WIDTH*SEL_NUM-1:0] data_in;
input  [SEL_NUM-1:0]            sel_in_onehot;

output [DATA_WIDTH-1:0]         data_out;

wire   [DATA_WIDTH-1:0]         data_in_2d[SEL_NUM-1:0];
wire   [SEL_NUM-1:0]            data_in_2d_rev[DATA_WIDTH-1:0];
wire   [DATA_WIDTH-1:0]         data_out;

//==========================================================
//                  Generate 2D signal
//==========================================================
genvar i;
genvar j;

generate
  for (i = 0; i < SEL_NUM; i = i+1) begin: EXPAND
    assign data_in_2d[i][DATA_WIDTH-1:0] = data_in[i*DATA_WIDTH+:DATA_WIDTH] & {DATA_WIDTH{sel_in_onehot[i]}};
  end
endgenerate

//==========================================================
//                   Reverse 2D signal
//==========================================================
generate
  for (i = 0; i < SEL_NUM; i = i+1) begin: REVERSEI
    for (j = 0; j < DATA_WIDTH; j = j+1) begin: REVERSEJ
      assign data_in_2d_rev[j][i] = data_in_2d[i][j];
    end
  end
endgenerate

//==========================================================
//                     Do or to sel
//==========================================================
generate
  for (i = 0; i < DATA_WIDTH; i = i+1) begin: OR_SEL
    assign data_out[i] = |data_in_2d_rev[i][SEL_NUM-1:0];
  end
endgenerate


endmodule
module cr_clic_arb_kernel(
  // input
  prio_in_vec,
  // output
  sel_out_onehot
);

parameter PRIO_WIDTH   = 6;
parameter INT_NUM     = 32;
parameter PRIO_EXP_NUM = 1 <<< PRIO_WIDTH;

input  [PRIO_WIDTH*INT_NUM-1:0] prio_in_vec;

output [INT_NUM-1:0]            sel_out_onehot;

wire   [INT_NUM-1:0]            sel_out_onehot;

wire   [PRIO_EXP_NUM-1:0]    prio_in_2d[INT_NUM-1:0];
wire   [INT_NUM-1:0]         prio_in_2d_rev[PRIO_EXP_NUM-1:0];

genvar i;
genvar j;
genvar k;

//==========================================================
//                   Generate 2D prio
//==========================================================
generate
  for (k = 0; k < INT_NUM; k = k+1)
  begin: EXPEND_PRIO
    assign prio_in_2d[k][PRIO_EXP_NUM-1:0] = {{(PRIO_EXP_NUM-1){1'b0}}, 1'b1} << prio_in_vec[PRIO_WIDTH*k+:PRIO_WIDTH];
  end
endgenerate

//==========================================================
//                   Reverse 2D signal
//==========================================================
generate
  for (i = 0; i < INT_NUM; i = i+1) begin: REVERSEI
    for (j = 0; j < PRIO_EXP_NUM; j = j+1) begin: REVERSEJ
      assign prio_in_2d_rev[j][i] = prio_in_2d[i][j];
    end
  end
endgenerate

wire   [PRIO_EXP_NUM-1:0]         high_prio_onehot;
wire   [PRIO_EXP_NUM-1:0]         prio_out;
//==========================================================
//                     Do or to sel
//==========================================================
generate
  for (i = 0; i < PRIO_EXP_NUM; i = i+1) begin: OR_SEL
    assign prio_out[i] = |prio_in_2d_rev[i][INT_NUM-1:0];
  end
endgenerate

cr_clic_ff1_onehot #(PRIO_EXP_NUM) x_cr_clic_high_prio(
  .data_in        (prio_out),
  .ff1_out_onehot (high_prio_onehot)
);

wire   [PRIO_EXP_NUM-1:0]    prio_after_mask_2d[INT_NUM-1:0];
wire   [INT_NUM-1:0]         int_hit_prio;
generate
  for (k = 0; k < INT_NUM; k = k+1)
  begin: PRIO_MASK
    assign prio_after_mask_2d[k][PRIO_EXP_NUM-1:0] = prio_in_2d[k][PRIO_EXP_NUM-1:0] & high_prio_onehot[PRIO_EXP_NUM-1:0];
    assign int_hit_prio[k] = |prio_after_mask_2d[k][PRIO_EXP_NUM-1:0];
  end
endgenerate

wire   [INT_NUM-1:0]          int_sel_onehot;

cr_clic_ff1_onehot #(INT_NUM) x_cr_clic_num(
  .data_in        (int_hit_prio),
  .ff1_out_onehot (int_sel_onehot)
);

assign sel_out_onehot[INT_NUM-1:0] = int_sel_onehot[INT_NUM-1:0];

endmodule
module cr_clic_ff1_onehot(
  data_in,
  ff1_out_onehot
);

parameter WIDTH = 32;

input  [WIDTH-1:0] data_in;
output [WIDTH-1:0] ff1_out_onehot;

wire [WIDTH:0] ff1_tmp;

assign ff1_tmp[WIDTH] = 1'b0;
genvar i;

generate
  for (i = 0; i < WIDTH; i = i+1)
  begin: FF1_ONEHOT
    assign ff1_tmp[i] = data_in[i] || ff1_tmp[i+1];
  end
endgenerate

assign ff1_out_onehot[WIDTH-1:0] = ff1_tmp[WIDTH:1] ^ ff1_tmp[WIDTH-1:0];

endmodule
module cr_had_sync_level(
  clk1,
  clk2,
  rst1_b,
  rst2_b,
  sync_in,
  sync_out
);

// &Ports; @25
input        clk1;         
input        clk2;         
input        rst1_b;       
input        rst2_b;       
input        sync_in;      
output       sync_out;     

// &Regs; @26
reg          sync_ff1_clk1; 
reg          sync_ff2_clk1; 
reg          sync_ff_clk2; 

// &Wires; @27
wire         clk1;         
wire         clk2;         
wire         rst1_b;       
wire         rst2_b;       
wire         sync_in;      
wire         sync_out;     


//==============================================================================
// sync logic from clk2 to clk1
// step 1. flop once in clk2 domain
// step 2. flop twice in clk1 domain
// constraint: slow clock --> fast clock
//==============================================================================

always @(posedge clk2 or negedge rst2_b)
begin
  if (!rst2_b)
    sync_ff_clk2 <= 1'b0;
  else
    sync_ff_clk2 <= sync_in;
end

always @(posedge clk1 or negedge rst1_b)
begin
  if (!rst1_b) begin
    sync_ff1_clk1 <= 1'b0;
    sync_ff2_clk1 <= 1'b0;
  end
  else begin
    sync_ff1_clk1 <= sync_ff_clk2;
    sync_ff2_clk1 <= sync_ff1_clk1;
  end   
end

assign sync_out = sync_ff2_clk1;

// &ModuleEnd; @58
endmodule
module cr_had_sync(
  clk1,
  clk2,
  rst1_b,
  rst2_b,
  sync_in,
  sync_out
);

// &Ports; @25
input        clk1;         
input        clk2;         
input        rst1_b;       
input        rst2_b;       
input        sync_in;      
output       sync_out;     

// &Regs; @26
reg          sync_ff1_clk1; 
reg          sync_ff2_clk1; 
reg          sync_ff3_clk1; 
reg          sync_ff_clk2; 

// &Wires; @27
wire         clk1;         
wire         clk2;         
wire         rst1_b;       
wire         rst2_b;       
wire         sync_in;      
wire         sync_out;     


//==============================================================================
// sync logic from clk2 to clk1
// step 1. flop once in clk2 domain
// step 2. flop twice in clk1 domain
// result: a pulse signal in clk1 domain
// constraint: slow clock --> fast clock
//==============================================================================

always @(posedge clk2 or negedge rst2_b)
begin
  if (!rst2_b)
    sync_ff_clk2 <= 1'b0;
  else
    sync_ff_clk2 <= sync_in;
end

always @(posedge clk1 or negedge rst1_b)
begin
  if (!rst1_b) begin
    sync_ff1_clk1 <= 1'b0;
    sync_ff2_clk1 <= 1'b0;
  end
  else begin
    sync_ff1_clk1 <= sync_ff_clk2;
    sync_ff2_clk1 <= sync_ff1_clk1;
  end   
end

// generates a pulse signal in clk1 domain
always @(posedge clk1 or negedge rst1_b)
begin
  if (!rst1_b)
    sync_ff3_clk1 <= 1'b0;
  else
    sync_ff3_clk1 <= sync_ff2_clk1;
end

assign sync_out = !sync_ff3_clk1 && sync_ff2_clk1;

// &ModuleEnd; @68
endmodule
module seven_segment_4_digits
(
    input             clock,
    input             reset,
    input      [15:0] number,

    output reg [ 7:0] abcdefgh,
    output reg [ 3:0] digit
);

    function [7:0] bcd_to_seg (input [3:0] bcd);

        case (bcd)

        'h0: bcd_to_seg = 'b00000011;  // a b c d e f g h
        'h1: bcd_to_seg = 'b10011111;
        'h2: bcd_to_seg = 'b00100101;  //   --a--
        'h3: bcd_to_seg = 'b00001101;  //  |     |
        'h4: bcd_to_seg = 'b10011001;  //  f     b
        'h5: bcd_to_seg = 'b01001001;  //  |     |
        'h6: bcd_to_seg = 'b01000001;  //   --g--
        'h7: bcd_to_seg = 'b00011111;  //  |     |
        'h8: bcd_to_seg = 'b00000001;  //  e     c
        'h9: bcd_to_seg = 'b00011001;  //  |     |
        'ha: bcd_to_seg = 'b00010001;  //   --d--  h
        'hb: bcd_to_seg = 'b11000001;
        'hc: bcd_to_seg = 'b01100011;
        'hd: bcd_to_seg = 'b10000101;
        'he: bcd_to_seg = 'b01100001;
        'hf: bcd_to_seg = 'b01110001;

        endcase

    endfunction

    reg [15:0] cnt;

    always @ (posedge clock or posedge reset)
        if (reset)
            cnt <= 16'd0;
        else
            cnt <= cnt + 16'd1;

    reg [1:0] i;

    always @ (posedge clock or posedge reset)
    begin
        if (reset)
        begin
            abcdefgh <=   bcd_to_seg (0);
            digit    <= ~ 4'b1;

            i <= 0;
        end
        else if (cnt == 16'b0)
        begin
            abcdefgh <=   bcd_to_seg (number [i * 4 +: 4]);
            digit    <= ~ (4'b1 << i);

            i <= i + 1;
        end
    end

endmodule
module sync_and_debounce
# (
    parameter w = 1, depth = 8
)
(   
    input            clk,
    input            reset,
    input  [w - 1:0] sw_in,
    output [w - 1:0] sw_out
);

    genvar sw_cnt;

    generate
        for (sw_cnt = 0; sw_cnt < w; sw_cnt = sw_cnt + 1)
        begin : gen_sync_and_debounce
           
           sync_and_debounce_one
           # (.depth (depth))
           i_sync_and_debounce_one
           (    
              .clk    ( clk             ),
              .reset  ( reset           ),
              .sw_in  ( sw_in  [sw_cnt] ),
              .sw_out ( sw_out [sw_cnt] )
           );

        end
    endgenerate 

endmodule
module seven_segment_8_digits
(
    input             clock,
    input             reset,
    input      [31:0] number,

    output reg [ 7:0] abcdefgh,
    output reg [ 7:0] digit
);

    function [7:0] bcd_to_seg (input [3:0] bcd);

        case (bcd)

        'h0: bcd_to_seg = 'b00000011;  // a b c d e f g h
        'h1: bcd_to_seg = 'b10011111;
        'h2: bcd_to_seg = 'b00100101;  //   --a--
        'h3: bcd_to_seg = 'b00001101;  //  |     |
        'h4: bcd_to_seg = 'b10011001;  //  f     b
        'h5: bcd_to_seg = 'b01001001;  //  |     |
        'h6: bcd_to_seg = 'b01000001;  //   --g--
        'h7: bcd_to_seg = 'b00011111;  //  |     |
        'h8: bcd_to_seg = 'b00000001;  //  e     c
        'h9: bcd_to_seg = 'b00011001;  //  |     |
        'ha: bcd_to_seg = 'b00010001;  //   --d--  h
        'hb: bcd_to_seg = 'b11000001;
        'hc: bcd_to_seg = 'b01100011;
        'hd: bcd_to_seg = 'b10000101;
        'he: bcd_to_seg = 'b01100001;
        'hf: bcd_to_seg = 'b01110001;

        endcase

    endfunction

    reg [15:0] cnt;

    always @ (posedge clock or posedge reset)
        if (reset)
            cnt <= 16'd0;
        else
            cnt <= cnt + 16'd1;

    reg [2:0] i;

    always @ (posedge clock or posedge reset)
    begin
        if (reset)
        begin
            abcdefgh <=   bcd_to_seg (0);
            digit    <= ~ 8'b1;

            i <= 0;
        end
        else if (cnt == 16'b0)
        begin
            abcdefgh <=   bcd_to_seg (number [i * 4 +: 4]);
            digit    <= ~ (8'b1 << i);

            i <= i + 1;
        end
    end

endmodule
module seven_segment_digit
(
    input      [3:0] dig,
    output reg [6:0] gfedcba
);

    always @*
        case (dig)
        'h0: gfedcba = 'b1000000;  // g f e d c b a
        'h1: gfedcba = 'b1111001;
        'h2: gfedcba = 'b0100100;  //   --a--
        'h3: gfedcba = 'b0110000;  //  |     |
        'h4: gfedcba = 'b0011001;  //  f     b
        'h5: gfedcba = 'b0010010;  //  |     |
        'h6: gfedcba = 'b0000010;  //   --g--
        'h7: gfedcba = 'b1111000;  //  |     |
        'h8: gfedcba = 'b0000000;  //  e     c
        'h9: gfedcba = 'b0011000;  //  |     |
        'ha: gfedcba = 'b0001000;  //   --d-- 
        'hb: gfedcba = 'b0000011;
        'hc: gfedcba = 'b1000110;
        'hd: gfedcba = 'b0100001;
        'he: gfedcba = 'b0000110;
        'hf: gfedcba = 'b0001110;
        endcase

endmodule
module seven_segment
# (
    parameter w              = 32,
              bits_per_digit = 4,
              n_digits       = w / bits_per_digit
)
(
    input                   clk,
    input                   reset,
    input                   en,
    input  [w        - 1:0] num,
    input  [n_digits - 1:0] dots,
    output [6:0]            abcdefg,
    output                  dot,
    output [n_digits - 1:0] anodes
);

    function [6:0] dig_to_seg (input [3:0] dig);

        case (dig)
        'h0: dig_to_seg = 'b0000001;  // a b c d e f g
        'h1: dig_to_seg = 'b1001111;
        'h2: dig_to_seg = 'b0010010;  //   --a--
        'h3: dig_to_seg = 'b0000110;  //  |     |
        'h4: dig_to_seg = 'b1001100;  //  f     b
        'h5: dig_to_seg = 'b0100100;  //  |     |
        'h6: dig_to_seg = 'b0100000;  //   --g--
        'h7: dig_to_seg = 'b0001111;  //  |     |
        'h8: dig_to_seg = 'b0000000;  //  e     c
        'h9: dig_to_seg = 'b0001100;  //  |     |
        'ha: dig_to_seg = 'b0001000;  //   --d-- 
        'hb: dig_to_seg = 'b1100000;
        'hc: dig_to_seg = 'b0110001;
        'hd: dig_to_seg = 'b1000010;
        'he: dig_to_seg = 'b0110000;
        'hf: dig_to_seg = 'b0111000;
        endcase

    endfunction

    //------------------------------------------------------------------------

    reg [n_digits - 1:0] anodes_d, anodes_q;

    always @*
        anodes_d <= { anodes_q [0], anodes_q [n_digits - 1 : 1] };

    always @ (posedge clk or posedge reset)
        if (reset)
            anodes_q <= { { n_digits - 1 { 1'b1 } }, 1'b0 };
        else if (en)
            anodes_q <= anodes_d;
    
    assign anodes = anodes_q;
    
    //------------------------------------------------------------------------

    wire [bits_per_digit - 1:0] dig;

    selector # (.w (bits_per_digit), .n (n_digits)) i_sel_dig
        (.d (num), .sel (~ anodes_d), .y (dig));

    register_no_rst # (7) i_abcdefg
    (
        .clk ( clk              ),
        .en  ( en               ),
        .d   ( dig_to_seg (dig) ),
        .q   ( abcdefg          )
    ); 

    //------------------------------------------------------------------------

    wire dot_d;

    selector # (.w (1), .n (n_digits)) i_sel_dot
        (.d (dots), .sel (~ anodes_d), .y (dot_d));

    register_no_rst i_dot
    (
        .clk (   clk   ),
        .en  (   en    ),
        .d   ( ~ dot_d ),
        .q   (   dot   )
    ); 

endmodule
module sync_and_debounce_one
# (
    parameter depth = 8
)
(   
    input      clk,
    input      reset,
    input      sw_in,
    output reg sw_out
);

    reg  [depth - 1:0] cnt;
    reg  [        2:0] sync;
    wire               sw_in_s;

    assign sw_in_s = sync [2];

    always @ (posedge clk or posedge reset)
        if (reset)
            sync <= 3'b0;
        else
            sync <= { sync [1:0], sw_in };

    always @ (posedge clk or posedge reset)
        if (reset)
            cnt <= { depth { 1'b0 } };
        else if (sw_out ^ sw_in_s)
            cnt <= cnt + 1'b1;
        else
            cnt <= { depth { 1'b0 } };

    always @ (posedge clk or posedge reset)
        if (reset)
            sw_out <= 1'b0;
        else if (cnt == { depth { 1'b1 } })
            sw_out <= sw_in_s;

endmodule
module AXILITE_V_v1_0 #
	(
		parameter C_S00_BASEADDR        = 0,
		// Parameters of Axi Slave Bus Interface S00_AXI
		parameter C_S00_AXI_DATA_WIDTH	= 32,
		parameter C_S00_AXI_ADDR_WIDTH	= 32
	)
	(
		// Ports of Axi Slave Bus Interface S00_AXI
		input wire  s00_axi_aclk,
		input wire  s00_axi_aresetn,
		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
		input wire  s00_axi_awvalid,
		output wire  s00_axi_awready,
		input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
		input wire  s00_axi_wvalid,
		output wire  s00_axi_wready,
		output wire [1 : 0] s00_axi_bresp,
		output wire  s00_axi_bvalid,
		input wire  s00_axi_bready,
		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
		input wire  s00_axi_arvalid,
		output wire  s00_axi_arready,
		output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
		output wire [1 : 0] s00_axi_rresp,
		output wire  s00_axi_rvalid,
		input wire  s00_axi_rready
	);
// Instantiation of Axi Bus Interface S00_AXI
	AXILITE_V_v1_0_S00_AXI # ( 
		.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
		.C_S_AXI_BASEADDR(C_S00_BASEADDR),
		.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
	) AXILITE_V_v1_0_S00_AXI_inst (
		.S_AXI_ACLK(s00_axi_aclk),
		.S_AXI_ARESETN(s00_axi_aresetn),
		.S_AXI_AWADDR(s00_axi_awaddr),
		.S_AXI_AWVALID(s00_axi_awvalid),
		.S_AXI_AWREADY(s00_axi_awready),
		.S_AXI_WDATA(s00_axi_wdata),
		.S_AXI_WVALID(s00_axi_wvalid),
		.S_AXI_WREADY(s00_axi_wready),
		.S_AXI_BRESP(s00_axi_bresp),
		.S_AXI_BVALID(s00_axi_bvalid),
		.S_AXI_BREADY(s00_axi_bready),
		.S_AXI_ARADDR(s00_axi_araddr),
		.S_AXI_ARVALID(s00_axi_arvalid),
		.S_AXI_ARREADY(s00_axi_arready),
		.S_AXI_RDATA(s00_axi_rdata),
		.S_AXI_RRESP(s00_axi_rresp),
		.S_AXI_RVALID(s00_axi_rvalid),
		.S_AXI_RREADY(s00_axi_rready)
	);
	endmodule
module fifo_simple
#(
  parameter   FIFO_DEPTH      = 4,
              FIFO_DATA_WIDTH = 8
)
(
  input                            clk,
  input                            clk_enable,
  input                            reset,

  input                            write,
  input                            read,

  input      [FIFO_DATA_WIDTH-1:0] write_data,
  output reg [FIFO_DATA_WIDTH-1:0] read_data,

  output                           empty,
  output                           full
);

  localparam  FIFO_PTR_WIDTH  = $clog2(FIFO_DEPTH) + 1;
  
  reg [FIFO_DATA_WIDTH-1:0] fifo_array [FIFO_DEPTH-1:0];

  reg [FIFO_PTR_WIDTH-1:0]  rd_ptr;
  reg [FIFO_PTR_WIDTH-1:0]  wr_ptr;

  //------------------------------------------------
  // Write Pointer Logic
  //------------------------------------------------
  always @ (posedge clk)
  begin
    if (reset)
      wr_ptr <= {FIFO_PTR_WIDTH{1'b0}};
    else if (clk_enable)
      if (write & !full)
        wr_ptr <= wr_ptr + 1'b1;
  end

  //------------------------------------------------
  // Read Pointer Logic
  //------------------------------------------------
  always @ (posedge clk)
  begin
    if (reset)
      rd_ptr <= {FIFO_PTR_WIDTH{1'b0}};
    else if (clk_enable)
      if (read & !empty)
        rd_ptr <= rd_ptr + 1'b1;
  end

  //------------------------------------------------
  // Full and Empty flags
  //------------------------------------------------
  assign full = (wr_ptr[FIFO_PTR_WIDTH-1] ^ rd_ptr[FIFO_PTR_WIDTH-1]) & 
                (wr_ptr[FIFO_PTR_WIDTH-2:0] == rd_ptr[FIFO_PTR_WIDTH-2:0]);
  assign empty = (wr_ptr == rd_ptr);

  //-----------------------------------------------
  // FIFO Write
  //-----------------------------------------------
  always @ (posedge clk)
  begin
    if (reset)
      fifo_array[wr_ptr] <= {FIFO_DATA_WIDTH{1'b0}};
    else if (clk_enable)
      if (write & !full)
        fifo_array[wr_ptr] <= write_data;
  end

  //-----------------------------------------------
  // FIFO Read
  //-----------------------------------------------
  always @ (posedge clk)
  begin
    if (reset)
      read_data <= {FIFO_DATA_WIDTH{1'b0}};
    else if (clk_enable)
      if (read & !empty)
        read_data <= fifo_array[rd_ptr];
  end

endmodule
module fifo_1(
  clk,
  rst_n,

  write,
  read,
  
  write_data,
  read_data,

  empty,
  full
);

  parameter FIFO_PTR_WIDTH   = 3;
  parameter FIFO_DATA_WIDTH  = 8;
  parameter FIFO_DEPTH       = 2**(FIFO_PTR_WIDTH - 1);

  input                            clk;
  input                            rst_n;

  input                            write;
  input                            read;

  input      [FIFO_DATA_WIDTH-1:0] write_data;
  output reg [FIFO_DATA_WIDTH-1:0] read_data;

  output                           empty;
  output                           full;

  reg [FIFO_DATA_WIDTH-1:0] fifo_array [FIFO_DEPTH-1:0];

  reg [FIFO_PTR_WIDTH-1:0]  rd_ptr;
  reg [FIFO_PTR_WIDTH-1:0]  wr_ptr;

  //------------------------------------------------
  // Write Pointer Logic
  //------------------------------------------------
  always @(posedge clk or negedge rst_n)
  begin: p_wr_ptr
    if (!rst_n)
      wr_ptr <= {FIFO_PTR_WIDTH{1'b0}};
    else if (write & !full)
      wr_ptr <= wr_ptr + 1'b1;
  end

  //------------------------------------------------
  // Read Pointer Logic
  //------------------------------------------------
  always @(posedge clk or negedge rst_n)
  begin: p_rd_ptr
    if (!rst_n)
      rd_ptr <= {FIFO_PTR_WIDTH{1'b0}};
    else if (read & !empty)
      rd_ptr <= rd_ptr + 1'b1;
  end

  //------------------------------------------------
  // Full and Empty flags
  //------------------------------------------------
  assign full = (wr_ptr[FIFO_PTR_WIDTH-1] ^ rd_ptr[FIFO_PTR_WIDTH-1]) & (wr_ptr[FIFO_PTR_WIDTH-2:0] == rd_ptr[FIFO_PTR_WIDTH-2:0]);
  assign empty = (wr_ptr == rd_ptr);

  //-----------------------------------------------
  // FIFO Write
  //-----------------------------------------------
  always @(posedge clk or negedge rst_n)
  begin: p_fifo_write
  integer int_i;
    if (!rst_n)
      for (int_i = 0; int_i < FIFO_DEPTH - 1; int_i = int_i + 1)
        fifo_array[int_i] <= {FIFO_DATA_WIDTH{1'b0}};
    else if (write & !full)
      fifo_array[wr_ptr] <= write_data;
  end

  //-----------------------------------------------
  // FIFO Read
  //-----------------------------------------------
  always @(posedge clk or negedge rst_n)
  begin: p_fifo_read
    if (!rst_n)
      read_data <= {FIFO_DATA_WIDTH{1'b0}};
    else if (read & !empty)
      read_data <= fifo_array[rd_ptr];
  end

endmodule
module tb_sender
(
    input            clk,
    input            rst,
    output reg [3:0] data,
    output reg       en,

    input      [7:0] gap_from,
    input      [7:0] gap_to
);

    reg [7:0] cnt;

    always @ (posedge clk or posedge rst)
        if (rst)
        begin
            data <= 0;
            en   <= 0;
            cnt  <= 0;
        end
        else if (cnt != 0)
        begin
            cnt  <= cnt - 1;
            en   <= 0;
        end
        else
        begin
            $display ("Sending %d", data + 1);

            data <= data + 1;
            en   <= 1;

            cnt  <= $urandom_range (gap_from, gap_to);
        end

endmodule