dakies/OSS_Verilog huggingface dataset:
module regymm_funnyblinky(
	input [7:0] io_in, 
	output [7:0] io_out
);
	wire clk25 = io_in[0];
	wire rst = io_in[1];

	wire sw_switch = io_in[7];

	// for funny
	wire [2:0]sw1 = io_in[4:2];

	// for counter
	wire [1:0]sw_outctrl = io_in[5:4];
	wire sw_pause = io_in[6];
	wire signal1 = io_in[2];
	wire signal2 = io_in[3];
	reg sig1r;
	reg sig2r;
	reg sig1rr;
	reg sig2rr;

	reg [13:0]cnt = 0;
	reg [13:0]cnt2 = 0;
	always @ (posedge clk25) begin
		sig1r <= signal1;
		sig2r <= signal2;
		sig1rr <= sig1r;
		sig2rr <= sig2r;
		if (sw_switch) begin
			if (rst) begin
				cnt <= 0;
				cnt2 <= 0;
			end else begin
				if (!sw_pause) begin
					if (sig1r != sig1rr) cnt <= cnt + 1;
					if (sig2r != sig2rr) cnt2 <= cnt2 + 1;
				end
			end
		end else begin
			cnt <= cnt + 1;
		end
	end
	wire clkslow = cnt[3 + sw1];
	reg [6:0]cntslow = 0;
	reg [2:0]cntf = 0;
	always @ (posedge clkslow) begin
		cntslow <= cntslow == 105 ? 0 : cntslow + 1;
		if (!cntslow[0]) begin
			if (cntslow >= 73) begin
				cntf <= cntf == 4 ? 0 : cntf + 1;
			end else
				cntf <= 0;
		end
	end
	reg	[2:0]finalpos;
	always @ (*) begin
		finalpos = 0;
		case (cntf)
			0: finalpos = 2;
			1: finalpos = 6;
			2: finalpos = 0;
			3: finalpos = 3;
			4: finalpos = 5;
		endcase
	end
	reg [7:0]io_out_funny;
	reg [7:0]io_out_cnter;
	always @ (*) begin
		io_out_funny = 0;
		if (cntslow >= 1 && cntslow <= 8) io_out_funny = 8'b11111111 << (8 - cntslow);
		else if (cntslow >= 9 && cntslow <= 17) io_out_funny = 8'b11111111 << (cntslow - 9);
		else if (cntslow >= 18 && cntslow <= 25) io_out_funny = 8'b10000000 >> (cntslow - 18);
		else if (cntslow >= 26 && cntslow <= 33) io_out_funny = 8'b00000001 << (cntslow - 26);
		else if (cntslow >= 35 && cntslow <= 55) io_out_funny = cntslow[0] ? 8'b00000000 : 8'b11111111;
		else if (cntslow >= 56 && cntslow <= 72) io_out_funny = cntslow[0] ? 8'b11110000 : 8'b00001111;
		else if (cntslow >= 73 && cntslow[0] == 0) io_out_funny = 8'b10000000 >> finalpos;

		io_out_cnter = 0;
		case (sw_outctrl)
			2'b00: io_out_cnter = cnt[7:0];
			2'b01: io_out_cnter = {2'b0, cnt[13:8]};
			2'b10: io_out_cnter = cnt2[7:0];
			2'b11: io_out_cnter = {2'b0, cnt2[13:8]};
		endcase
	end
	assign io_out = sw_switch ? io_out_cnter : io_out_funny;
endmodule
module rc5_top (
  input [7:0] io_in,
  output [7:0] io_out
);
    
    wire clk = io_in[0];
    wire reset = io_in[1];
    wire ir = io_in[2];
    wire [6:0] led_out;
    assign io_out[6:0] = led_out;

    wire valid;
    wire [5:0] command;
    wire control;
    reg control_d;
    localparam [5:0] RC5_INCR_VOLUME=16;
    localparam [5:0] RC5_DECR_VOLUME=17;

    rc5 rc5(
        .i_clk(clk),
        .i_rst(reset),

        .i_rc5(ir),

        .o_valid(valid),
        .o_command(command),
        .o_control(control)
    );

    reg [3:0] counter;
    always @(posedge clk) begin
        if (reset) begin
            counter <= 0;
            control_d <= 1'b0;
        end else begin
            if (valid) begin
                control_d <= control;

                if (control != control_d) begin
                    if (command == RC5_INCR_VOLUME) begin
                        counter <= counter+1;
                    end else if (command == RC5_DECR_VOLUME) begin
                        counter <= counter-1;
                    end
                end
            end
        end
    end

    // instantiate segment display
    seg7 seg7(.counter(counter), .segments(led_out));

endmodule
module aidan_McCoy(
    input [7:0] io_in,
    output [7:0] io_out);

    // map i/o to proper labels
    wire clk = io_in[0];
    wire reset = io_in[1];
    wire [5:0] instr = io_in[7:2];
    
    // decode signals
    wire bez;
    wire ja;
    //wire aluFun;
    wire op1Sel;
    wire op2Sel;
    wire writeReg;
    wire writex8;
    wire [1:0] x8Sel;
    
    // Other wires
    wire [7:0] pc;
    wire [7:0] pc1;
    wire [7:0] nextPC;
    wire pcSel;
    wire [7:0] aluOut;
    wire [7:0] x8;
    wire [7:0] newx8;
    wire [7:0] op1;
    wire [7:0] op2;
    wire [7:0] regOut;
    wire [7:0] imm;
    wire [7:0] notx8;

    /* Misc. blocks */ 
    
    decoder decoderBlock( .opcode(instr[2:0]), .bez(bez), .ja(ja), /*.aluFun(aluFun),*/ .op1(op1Sel), .op2(op2Sel),
                            .writeReg(writeReg), .writex8(writex8), .x8Sel(x8Sel));
                            
    iSign signBlock( .imm(instr[5:3]), .out(imm));
    
    /* PC related blocks */
    
    mux2 pcMux( .in0(aluOut), .in1(pc1), .sel(pcSel), .out(nextPC));
    
    pc pcBlock( .clk(clk), .reset(reset), .nextPC(nextPC), .PC(pc));
    
    add1 adder( .in(pc), .out(pc1));
    
    branch branchBlock( .x8(x8), .bez(bez), .ja(ja), .reset(reset), .pcSel(pcSel));
    
    /* ALU blocks */
    
    mux2 op1Mux( .in0(regOut), .in1(x8), .sel(op1Sel), .out(op1));
    
    mux2 op2Mux( .in0(regOut), .in1(pc), .sel(op2Sel), .out(op2));
    
    alu aluBlock( .op1(op1), .op2(op2), /*.aluFun(aluFun),*/ .aluOut(aluOut));
    
    /* x8 and other register blocks */
    
    register regBlock( .clk(clk), .reset(reset), .regAddr(instr[5:3]), .x8(x8), .writeReg(writeReg),
                        .out(regOut));
                        
    x8 x8Block( .clk(clk), .writex8(writex8), .newx8(newx8), .x8(x8));
    
    notx8 nx8( .x8(x8), .out(notx8));
    
    mux4 x8Mux( .in0(regOut), .in1(imm), .in2(aluOut), .in3(notx8), .sel(x8Sel), .out(newx8));
    
    
    assign io_out = clk ?  pc : x8;

    
endmodule
module user_module_349047610915422802(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[6];
  wire net6 = io_in[7];
  wire net7;
  wire net8;
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13 = 1'b0;
  wire net14 = 1'b1;
  wire net15 = 1'b1;
  wire net16;
  wire net17;
  wire net18;
  wire net19;
  wire net20;
  wire net21;
  wire net22;
  wire net23;
  wire net24;
  wire net25;
  wire net26;
  wire net27;
  wire net28;
  wire net29;
  wire net30;
  wire net31;
  wire net32;
  wire net33;
  wire net34;

  assign io_out[0] = net7;
  assign io_out[1] = net8;
  assign io_out[2] = net9;
  assign io_out[3] = net10;
  assign io_out[4] = net11;
  assign io_out[7] = net12;

  dff_cell flipflop2 (
    .d (net5),
    .clk (net6),
    .q (net16),
    .notq (net17)
  );
  dff_cell flipflop3 (
    .d (net17),
    .clk (net6),
    .q (net18),
    .notq (net19)
  );
  dff_cell flipflop4 (
    .d (net19),
    .clk (net6),
    .q (net20),
    .notq (net21)
  );
  dff_cell flipflop5 (
    .d (net21),
    .clk (net6),
    .q (net22),
    .notq (net12)
  );
  xor_cell gate7 (
    .a (net1),
    .b (net16),
    .out (net7)
  );
  xor_cell gate8 (
    .a (net2),
    .b (net18),
    .out (net23)
  );
  xor_cell gate9 (
    .a (net3),
    .b (net20),
    .out (net24)
  );
  xor_cell gate10 (
    .a (net4),
    .b (net22),
    .out (net25)
  );
  and_cell gate11 (
    .a (net23),
    .b (net26),
    .out (net27)
  );
  and_cell gate12 (
    .a (net2),
    .b (net18),
    .out (net28)
  );
  and_cell gate13 (
    .a (net3),
    .b (net20),
    .out (net29)
  );
  and_cell gate14 (
    .a (net4),
    .b (net22),
    .out (net30)
  );
  and_cell gate16 (
    .a (net1),
    .b (net16),
    .out (net26)
  );
  xor_cell gate17 (
    .a (net23),
    .b (net26),
    .out (net8)
  );
  and_cell gate18 (
    .a (net24),
    .b (net31),
    .out (net32)
  );
  xor_cell gate19 (
    .a (net25),
    .b (net33),
    .out (net10)
  );
  and_cell gate20 (
    .a (net25),
    .b (net33),
    .out (net34)
  );
  or_cell gate21 (
    .a (net34),
    .b (net30),
    .out (net11)
  );
  or_cell gate22 (
    .a (net32),
    .b (net29),
    .out (net33)
  );
  or_cell gate25 (
    .a (net27),
    .b (net28),
    .out (net31)
  );
  xor_cell gate26 (
    .a (net24),
    .b (net31),
    .out (net9)
  );
endmodule
module stevenmburns_toplevel(
  input [7:0] io_in,
  output [7:0] io_out
);
  
ScanBinary u0(.clock(io_in[0]),
	.reset(io_in[1]),
	.io_ld(io_in[2]),
	.io_u_bit(io_in[3]),
	.io_v_bit(io_in[4]),
	.io_z_bit(io_out[0]),
	.io_done(io_out[1]));

assign io_out[7:2] = 6'b0;

endmodule
module rdffe(input clk,d,en,rst, output q);
  `ifdef COCOTB_SIM
    reg rq;
    assign #0.1 q = rq;
    always @(posedge clk or posedge rst)
      rq <= rst ? 1'b0 : ( en ? d : q);
  `else
    wire b;
    assign b = en ? d : q;
    sky130_fd_sc_hd__dfrtp_4 dfrtp(
        .D(b),
        .RESET_B(~rst),
        .CLK(clk),
        .Q(q)
    );
  `endif
endmodule
module sdffe(input clk,d,en,pre, output q);
  `ifdef COCOTB_SIM 
    reg rq;
    assign #0.1 q = rq;
    always @(posedge clk or posedge pre)
      rq <= pre ? 1'b1 : ( en ? d : q);
  `else
    wire b;
    assign b = en ? d : q;
    sky130_fd_sc_hd__dfstp_4 dfstp(
        .D(b),
        .SET_B(~pre),
        .CLK(clk),
        .Q(q)
    );
  `endif
endmodule
module inv_with_delay(input A,output Y);
  `ifdef COCOTB_SIM
  assign #0.02 Y = ~A; // pick a fairly quick delay from the tt_025C_1v80 liberty file
                       // the actualy delay per stage is going to be slower
  `else
  sky130_fd_sc_hd__inv_2 inv(.A(A),.Y(Y));
  `endif
endmodule
module nand2_with_delay(input A,input B,output Y);
  `ifdef COCOTB_SIM
  assign #0.05 Y = ~(A & B);
  `else
  sky130_fd_sc_hd__nand2_2 nand2(.A(A),.B(B),.Y(Y));
  `endif
endmodule
module ring_osc(input nrst,output osc);
  // We count for 1 scan_clk period which expected at 166uS (6KHz).
  // If the delay of one inverter is 20ps and the ring is 150 inverters long,
  // then the ring period is 6nS (2*150inv*20pS/inv)
  // This is 166MHz so expect a count of 166*166 nominally. 
  // For more time resolution make scan_clk slower but that requires more
  // counter depth. 
  // scan clk slowing can be done externally to the TT IC or with the clk div. 

  localparam NUM_INVERTERS = 150; //  must be an even number
  
  // setup loop of inverters
  // http://svn.clairexen.net/handicraft/2015/ringosc/ringosc.v
  wire [NUM_INVERTERS-1:0] delay_in, delay_out;
  wire osc_out;
  inv_with_delay idelay [NUM_INVERTERS-1:0] (
        .A(delay_in),
        .Y(delay_out)
    );
  assign delay_in = {delay_out[NUM_INVERTERS-2:0], osc_out};
  nand2_with_delay nand2_with_delay(.A(nrst),.B(delay_out[NUM_INVERTERS-1]),.Y(osc_out));
  assign osc = osc_out;
endmodule
module  ring_with_counter #(parameter WIDTH=24) (input nrst, ring_en, count_en, output [WIDTH-1:0] count);

  wire [WIDTH:0] value;
  wire rst,count_en_s0,count_en_s1,osc,nosc_buf;
  genvar i;

  ring_osc ring_osc(.nrst(ring_en),.osc(osc));

  inv_with_delay inv_r(.A(nrst),.Y(rst));

  // logic in this module should minimize loading the ring, so buffer the ring output
  inv_with_delay inv_b(.A(osc),.Y(nosc_buf)); 

  // synchronize the counter enable time to the ring oscillator frequency 
  // so metastability doesnt corrupt the count.  note: we count on the ring frequency domain

  rdffe ds0(.clk(nosc_buf),.rst(rst),.en(1'b1), .d(count_en),    .q(count_en_s0));
  rdffe ds1(.clk(nosc_buf),.rst(rst),.en(1'b1), .d(count_en_s0), .q(count_en_s1));

  // Count down toward zero from (signed)-1

  assign value[0] = nosc_buf;

  generate
		for (i = 1; i < WIDTH; i = i + 1) 
          sdffe dcg(.clk(value[i-1]),.pre(rst),.en(count_en_s1),.d(~value[i]),.q(value[i]));
  endgenerate

  // value[WIDTH] is the overflow bit.  Make it sticky.  
  // This bit should never be cleared if the measurement is designed correctly.

  sdffe dcg(.clk(value[WIDTH-1]),.pre(rst),.en(count_en_s1),.d(1'b0),.q(value[WIDTH]));

  assign count[WIDTH-1:0] = value[WIDTH:1];
  
endmodule
module ericsmi_speed_test(
  input [7:0] io_in,
  output [7:0] io_out
);

parameter WIDTH=24;
localparam COUNTER_WIDTH = 23; // TinyTapeout is small, so find a value that fits by trial and error

wire force_trig, fired, count_en;
wire [2:0] sel;
wire [2:0] trig_q;
wire [1:0] ring_en;
wire [WIDTH-1:0] value0,value1;
wire [COUNTER_WIDTH-1:0] count0,count1;

wire clk  = io_in[0];
wire nrst = io_in[1];
wire trig = io_in[2];

assign sel[2:0]     = io_in[5:3];
assign ring_en[1:0] = io_in[7:6];

assign force_trig = &sel; // force the oscillators and counters to run to test their operation
                          // not really a controlled measurement.  Only for debug. 

inv_with_delay inv_r(.A(nrst),.Y(rst));

// Enable the counters for one clk period upon trig rising edge. 
// Asserting nrst arms the measurements.  Clear nrst before fire. 

rdffe dt0(.clk(clk),.rst(rst),.en(1'b1), .d(trig ),     .q(trig_q[0]));
rdffe dt1(.clk(clk),.rst(rst),.en(1'b1), .d(trig_q[0]), .q(trig_q[1]));

rdffe dt2(
    .clk(clk),
    .rst(rst),
    .en(1'b1),
    .d((trig_q[0] & ~trig_q[1])),
    .q(trig_q[2])
);

rdffe dt3(
    .clk(clk),
    .rst(rst),
    .en(1'b1),
    .d(trig_q[2] | fired),
    .q(fired)
);

assign count_en = force_trig | trig_q[2];

ring_with_counter #(.WIDTH(COUNTER_WIDTH)) ring0(
    .nrst(nrst),
    .ring_en(ring_en[0]),
    .count_en(count_en),
    .count(count0[COUNTER_WIDTH-1:0])
);

assign value0[WIDTH-1:0] = {{WIDTH-COUNTER_WIDTH{count0[COUNTER_WIDTH-1]}},count0[COUNTER_WIDTH-1:0]};

ring_with_counter #(.WIDTH(COUNTER_WIDTH)) ring1(
    .nrst(nrst),
    .ring_en(ring_en[1]),
    .count_en(count_en),
    .count(count1[COUNTER_WIDTH-1:0])
);

assign value1[WIDTH-1:0] = {{WIDTH-COUNTER_WIDTH{count1[COUNTER_WIDTH-1]}},count1[COUNTER_WIDTH-1:0]};

wire [7:0] status;

// when force_trigger is asserted put the status byte on the output, everything is free running. 
assign status[7:0] = {1'b1, 
                      fired, 
                      value1[COUNTER_WIDTH-1], // overflow
                      value0[COUNTER_WIDTH-1], // overflow
                      value1[COUNTER_WIDTH-2],
                      value0[COUNTER_WIDTH-2],
                      value1[16], // 16=Ceiling@Log2[166*166]+1
                      value0[16]};

assign io_out[7:0] = sel[2:0] == 3'b000 ? 8'd0 : 
                     sel[2:0] == 3'b001 ? {value0[7:0]} :
                     sel[2:0] == 3'b010 ? {value0[15:8]} :
                     sel[2:0] == 3'b011 ? {value0[23:16]} : 
                     sel[2:0] == 3'b100 ? {value1[7:0]} :
                     sel[2:0] == 3'b101 ? {value1[15:8]} :
                     sel[2:0] == 3'b110 ? {value1[23:16]} :
                                          status[7:0] ;

endmodule
module loxodes_sequencer (
  input [7:0] io_in,
  output [7:0] io_out
);
    
    wire clk = io_in[0];
    wire reset = io_in[1];
    wire enable = io_in[2];
    wire [4:0] delay;
    assign delay = io_in[7:3];
    
    wire [7:0] channel;
    assign io_out[7:0] = channel;
    assign channel = channel_state;

    reg [4:0] counter;
    reg [7:0] channel_state;
    reg [3:0] channel_index;

    always @(posedge clk) begin
        // if reset, set counter to 0
        if (reset) begin
            counter <= 0;
            channel_state <= 0;
            channel_index <= 0;
        end else begin
            if (enable) begin
                if (counter == delay && channel_index < 8) begin
                    counter <= 0;
                    channel_index <= channel_index + 1'b1;
                    channel_state <= channel_state + (1'b1 << channel_index);
                end else begin
                    counter <= counter + 1'b1;
                end
            end else begin
                if (counter == delay && channel_index > 0) begin
                    counter <= 0;
                    channel_index <= channel_index - 1'b1;
                    channel_state <= (channel_state >> 1);
                end else begin
                    counter <= counter + 1'b1;
                end

            end
        end
    end
endmodule
module github_com_proppy_tt02_xls_counter(
  input wire [7:0] io_in,
  output wire [7:0] io_out
);
  wire 	    rdy = 1;
  wire 	    vld;
  user_module counter0(io_in[0], io_in[1], rdy, io_out, vld);
endmodule
module tholin_avalonsemi_tbb1143(
	input [7:0] io_in,
	output [7:0] io_out
);
	wire s_A0 = io_in[6];
	wire s_CLK = io_in[0];
	wire s_D0 = io_in[2];
	wire s_D1 = io_in[3];
	wire s_D2 = io_in[4];
	wire s_D3 = io_in[5];
	wire s_RST = io_in[1];
	wire s_WR = io_in[7];
	wire [5:0] s_SOUT;
	wire LED0;
	wire LED1;

	assign io_out[5:0] = s_SOUT;
	assign io_out[6] = LED0;
	assign io_out[7] = LED1;

	reg [4:0] shifter;

	always @(posedge s_CLK)
	begin
		shifter[4:1] <= shifter[3:0];
		shifter[0]   <= ~s_RST;
	end

	wire c2_1, c2_2, c2_3, c2_4, c2_5;
	assign c2_1 = c2_5 & shifter[0];
	assign c2_2 = c2_1 & shifter[1];
	assign c2_3 = c2_2 & shifter[2];
	assign c2_4 = c2_3 & shifter[3];
	assign c2_5 = c2_4 & shifter[4];

	main   CIRCUIT_0 (.A0(s_A0),
							.CLK(s_CLK),
							.D0(s_D0),
							.D1(s_D1),
							.D2(s_D2),
							.D3(s_D3),
							.FCLK(c2_5),
							.RST(s_RST),
							.WR(s_WR),
							.S0(s_SOUT[0]),
							.S1(s_SOUT[1]),
							.S2(s_SOUT[2]),
							.S3(s_SOUT[3]),
							.S4(s_SOUT[4]),
							.S5(s_SOUT[5]),
							.LED0(LED0),
							.LED1(LED1)
							);
endmodule
module user_module_346916357828248146(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7 = io_in[6];
  wire net8 = io_in[7];
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13;
  wire net14;
  wire net15;
  wire net16;
  wire net17 = 1'b0;
  wire net18 = 1'b1;
  wire net19 = 1'b1;

  assign io_out[0] = net9;
  assign io_out[1] = net10;
  assign io_out[2] = net11;
  assign io_out[3] = net12;
  assign io_out[4] = net13;
  assign io_out[5] = net14;
  assign io_out[6] = net15;
  assign io_out[7] = net16;

  xor_cell gate3 (
    .a (net9),
    .b (net4),
    .out (net10)
  );
  nand_cell gate4 (
    .a (net10),
    .b (net15),
    .out (net11)
  );
  mux_cell mux1 (
    .a (net1),
    .b (net2),
    .sel (net3),
    .out (net9)
  );
  nand_cell nand1 (
    .a (net14),
    .b (net11),
    .out (net15)
  );
  mux_cell mux2 (
    .a (net5),
    .b (net6),
    .sel (net7),
    .out (net13)
  );
  xor_cell xor1 (
    .a (net13),
    .b (net8),
    .out (net14)
  );
  dff_cell flop1 (
    .d (net14),
    .clk (net10),
    .q (net12),
    .notq (net16)
  );
endmodule
module user_module_349813388252021330(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[6];
  wire net5 = io_in[7];
  wire net6;
  wire net7;
  wire net8;
  wire net9 = 1'b1;
  wire net10;
  wire net11;
  wire net12;
  wire net13;
  wire net14;
  wire net15;
  wire net16;

  assign io_out[0] = net6;
  assign io_out[1] = net7;
  assign io_out[2] = net8;

  and_cell gate1 (
    .a (net10),
    .b (net3),
    .out (net11)
  );
  or_cell gate2 (
    .a (net11),
    .b (net12),
    .out (net6)
  );
  xor_cell gate3 (
    .a (net10),
    .b (net3),
    .out (net13)
  );
  xor_cell gate7 (
    .a (net1),
    .b (net2),
    .out (net10)
  );
  and_cell gate4 (
    .a (net1),
    .b (net3),
    .out (net12)
  );
  and_cell gate5 (
    .a (net14),
    .b (net5),
    .out (net15)
  );
  or_cell gate6 (
    .a (net15),
    .b (net16),
    .out (net7)
  );
  xor_cell gate8 (
    .a (net14),
    .b (net5),
    .out (net8)
  );
  xor_cell gate9 (
    .a (net13),
    .b (net4),
    .out (net14)
  );
  and_cell gate10 (
    .a (net13),
    .b (net5),
    .out (net16)
  );
endmodule
module thezoq2_yafpga (
    input [7:0] io_in,
    output [7:0] io_out
    );

    wire[3:0] dummy;

    e_main main
        ( .clk_i(io_in[0])
        , .cfg_value_i(io_in[1])
        , .cfg_clk_i(io_in[2])
        , .inputs_unsync_i(io_in[7:3])
        , .output__({dummy, io_out[3:0]})
        );
endmodule
module prog_melody_gen (
  input [7:0] io_in,
  output [7:0] io_out
);
    reg [9:0] div_tmr = 0;
    reg tick;
    reg state;
    reg [7:0] curr_tone;

    reg [5:0] tone_seq;
    wire [3:0] rom_rdata;

    wire clock = io_in[0];
    wire reload = io_in[1];
    wire restart = io_in[2];

    wire pgm_data = io_in[3];
    wire pgm_strobe = io_in[4];

    assign io_out[7:1] = 1'b0;

    always @(posedge clock, posedge restart) begin
        if (restart) begin
            div_tmr <= 0;
            tone_seq <= 0;
            curr_tone <= 0;
            tick <= 1'b0;
            state <= 1'b0;
        end else begin
            {tick, div_tmr} <= div_tmr + 1'b1;
            if (tick) begin
                if (!state) begin
                    tone_seq <= tone_seq + 1'b1;
                    if (rom_rdata == 15)
                        curr_tone <= 0; // silence
                    else
                        curr_tone <= 12 + rom_rdata; // note
                end else begin
                    curr_tone <= 0; // gap between notes
                end
                state <= ~state;
            end
        end
    end

    reg [7:0] mel_gen = 0;
    reg mel_out;
    always @(posedge clock) begin
        if (mel_gen >= curr_tone)
            mel_gen <= 0;
        else 
            mel_gen <= mel_gen + 1'b1;
        mel_out <= mel_gen > (curr_tone / 2);
    end

    assign io_out[0] = mel_out;

    localparam C = 4'd11, CS = 4'd10, D = 4'd9, E = 4'd7, F = 4'd6, FS = 4'd5, G = 4'd4, GS = 4'd3, A = 4'd2, AS = 4'd1, B = 4'd0, S = 4'd15;
    localparam [4*64:0] JINGLE_BELS = {
        E, E, E, S, E, E, E, S,
        E, G, C, D, E, S, F, F,
        F, F, F, E, E, E, E, E,
        D, D, E, D, S, G, S, E,
        E, E, S, E, E, E, S, E,
        G, C, D, E, S, F, F, F,
        F, F, E, E, E, E, F, F,
        E, D, C, S, S, S, S, S
    };

    wire [3:0] tone_rom[0:63];

    // program shift register
    reg [10:0] write_sr;
    always @(posedge clock)
        write_sr <= {pgm_data, write_sr[10:1]};

    wire [5:0] pgm_word_sel = write_sr[10:5];
    wire [3:0] pgm_write_data = write_sr[3:0];

    // the tone RAM
    generate
        genvar ii;
        genvar jj;
        for (ii = 0; ii < 64; ii = ii + 1'b1) begin : words
            wire word_we;
            sky130_fd_sc_hd__and2_1 word_we_i ( // make sure this is really glitch free
                .A(pgm_word_sel == ii),
                .B(pgm_strobe),
                .X(word_we)
            );
            for (jj = 0; jj < 4; jj = jj + 1'b1) begin : bits
                localparam pgm_bit = JINGLE_BELS[(63 - ii) * 4 + jj];
                wire lat_o;
                sky130_fd_sc_hd__dlrtp_1 rfbit_i (
                    .GATE(word_we),
                    .RESET_B(reload),
                    .D(pgm_write_data[jj]),
                    .Q(lat_o)
                );
                assign tone_rom[ii][jj] = lat_o ^ pgm_bit;
            end
        end
    endgenerate

    assign rom_rdata = tone_rom[tone_seq];

endmodule
module sky130_fd_sc_hd__and2_1(input A, B, output X);
    assign X = A & B;
endmodule
module seven_segment_seconds #( parameter MAX_COUNT = 1000 ) (
  input [7:0] io_in,
  output [7:0] io_out
);
    
    wire clk = io_in[0];
    wire reset = io_in[1];
    wire [6:0] led_out;
    assign io_out[6:0] = led_out;

    // external clock is 1000Hz, so need 10 bit counter
    reg [9:0] second_counter;
    reg [3:0] digit;

    always @(posedge clk) begin
        // if reset, set counter to 0
        if (reset) begin
            second_counter <= 0;
            digit <= 0;
        end else begin
            // if up to 16e6
            if (second_counter == MAX_COUNT) begin
                // reset
                second_counter <= 0;

                // increment digit
                digit <= digit + 1'b1;

                // only count from 0 to 9
                if (digit == 9)
                    digit <= 0;

            end else
                // increment counter
                second_counter <= second_counter + 1'b1;
        end
    end

    // instantiate segment display
    seg7 seg7(.counter(digit), .segments(led_out));

endmodule
module aramsey118_freq_counter #(
    parameter DEPTH = 200
) (
  input wire [7:0] io_in,
  output wire [7:0] io_out
);

    // Precalculate the boundaries
    localparam integer freq_0 = $ceil(DEPTH * 0.0); // not used, here for completeness
    localparam integer freq_1 = $ceil(DEPTH * 0.1);
    localparam integer freq_2 = $ceil(DEPTH * 0.2);
    localparam integer freq_3 = $ceil(DEPTH * 0.3);
    localparam integer freq_4 = $ceil(DEPTH * 0.4);
    localparam integer freq_5 = $ceil(DEPTH * 0.5);
    localparam integer freq_6 = $ceil(DEPTH * 0.6);
    localparam integer freq_7 = $ceil(DEPTH * 0.7);
    localparam integer freq_8 = $ceil(DEPTH * 0.8);
    localparam integer freq_9 = $ceil(DEPTH * 0.9);

    wire clk = io_in[0];
    wire reset = io_in[1];
    wire sig = io_in[2];
    wire [6:0] led_out;
    assign io_out[6:0] = led_out;
    assign io_out[7] = sig;

    wire [$clog2(DEPTH)-1:0] avg;
    reg sig_d1;
    reg diff;
    reg [3:0] digit;


    always @(posedge clk) begin
        // if reset, set counter to 0
        if (reset) begin
            sig_d1 <= 0;
            diff <= 0;
            digit <= 0;
        end else begin
            sig_d1 <= sig;
            diff <= (sig ^ sig_d1);
            if ((avg <= $unsigned(freq_1))) begin
                digit <= 0;
            end else if ((avg > $unsigned(freq_1)) && (avg <= $unsigned(freq_2))) begin
                digit <= 1;
            end else if ((avg > $unsigned(freq_2)) && (avg <= $unsigned(freq_3))) begin
                digit <= 2;
            end else if ((avg > $unsigned(freq_3)) && (avg <= $unsigned(freq_4))) begin
                digit <= 3;
            end else if ((avg > $unsigned(freq_4)) && (avg <= $unsigned(freq_5))) begin
                digit <= 4;
            end else if ((avg > $unsigned(freq_5)) && (avg <= $unsigned(freq_6))) begin
                digit <= 5;
            end else if ((avg > $unsigned(freq_6)) && (avg <= $unsigned(freq_7))) begin
                digit <= 6;
            end else if ((avg > $unsigned(freq_7)) && (avg <= $unsigned(freq_8))) begin
                digit <= 7;
            end else if ((avg > $unsigned(freq_8)) && (avg <= $unsigned(freq_9))) begin
                digit <= 8;
            end else begin
                digit <= 9;
            end
        end
    end

    // instantiate segment display
    seg7 seg7(.counter(digit), .segments(led_out));

    // instantiate moving average
    moving_avg #(.DEPTH(DEPTH)) moving_avg(.data_i(diff), .reset, .clk, .avg_o(avg));
endmodule
module razhas_top_level 
  (
    input   [7:0] io_in, 
    output  [7:0] io_out
  );

  wire        w_clk = io_in[0];
  wire        w_rst = io_in[1];
  wire  [3:0] w_duty = io_in[5:2]; // selects pwm signal duty cycle: 0% to 100% in increments of 10%. Values of 11-15 treated as 100%.
  wire  [1:0] w_freq = io_in[7:6]; // selects pwm signal frequency: 156.25 Hz, 312.5 Hz, 625 Hz, or 1250 Hz.
  wire        w_pwm; // pwm signal

  assign io_out = {7'b0000000, w_pwm};

  pwm_gen   u0 (.i_clk(w_clk), .i_rst(w_rst), .i_duty(w_duty), .i_freq(w_freq), .o_pwm(w_pwm));

endmodule
module vaishnavachath_rotary_toplevel (
  input [7:0] io_in,
  output [7:0] io_out
);
    
    wire clk_in = io_in[0];
    wire reset = io_in[1];
    wire rt_a;
    wire rt_b;
    wire tm_enable = io_in[4];
    wire [6:0] led_out;
    assign io_out[6:0] = led_out;
    reg [3:0] enc_byte = 0;
    reg [3:0] counter = 0;
    reg rt_a_delayed, rt_b_delayed, clk_msb_delayed;
    assign rt_a = tm_enable ? counter[3] : io_in[2];
    assign rt_b = tm_enable ? clk_msb_delayed : io_in[3];
    wire count_enable = rt_a ^ rt_a_delayed ^ rt_b ^ rt_b_delayed;
    wire count_direction = rt_a ^ rt_b_delayed;

    always @(posedge clk_in) rt_a_delayed <= rt_a;
    always @(posedge clk_in) rt_b_delayed <= rt_b;
    always @(posedge clk_in) clk_msb_delayed <= counter[3];

    always @(posedge clk_in) begin
         if(count_enable) begin
            if(count_direction) enc_byte<=enc_byte+1; else enc_byte<=enc_byte-1;
        end
    end


    always @(posedge clk_in) begin
        if (reset) begin
            counter <= 0;
        end else begin
            counter <= counter + 1'b1;
        end
    end

    seg7 seg7(.counter(enc_byte), .segments(led_out));

endmodule
module user_module_341614374571475540(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7 = io_in[6];
  wire net8 = io_in[7];
  wire net9;
  wire net10;
  wire net11 = 1'b0;
  wire net12 = 1'b1;
  wire net13 = 1'b1;
  wire net14;
  wire net15;
  wire net16;
  wire net17;
  wire net18;
  wire net19;
  wire net20;
  wire net21;
  wire net22;
  wire net23;
  wire net24;

  assign io_out[0] = net9;
  assign io_out[1] = net10;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (
    .a (net14),
    .b (net8),
    .out (net10)
  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (
    .d (net15),
    .clk (net1),
    .q (net16)
  );
  and_cell gate7 (
    .a (net6),
    .b (net7),
    .out (net17)
  );
  and_cell gate8 (
    .a (net4),
    .b (net18),
    .out (net19)
  );
  and_cell gate9 (
    .a (net3),
    .b (net6),
    .out (net20)
  );
  and_cell gate10 (
    .a (net3),
    .b (net4),
    .out (net21)
  );
  not_cell gate11 (
    .in (net7),
    .out (net18)
  );
  xor_cell gate12 (
    .a (net5),
    .b (net19),
    .out (net15)
  );
  xor_cell gate13 (
    .a (net20),
    .b (net5),
    .out (net22)
  );
  dff_cell flipflop2 (
    .d (net22),
    .clk (net1),
    .q (net23)
  );
  xor_cell gate14 (
    .a (net21),
    .b (net23),
    .out (net24)
  );
  xor_cell gate15 (
    .a (net16),
    .b (net17),
    .out (net14)
  );
  xor_cell gate16 (
    .a (net2),
    .b (net24),
    .out (net9)
  );
endmodule
module udxs_sqrt_top(
	input [7:0] io_in, 
	output [7:0] io_out
);

	wire [10:0] result;
	assign io_out = result[7:0];

  	udxs_sqrt sqrt_core(
		.clk(io_in[0]),
		.query({io_in[7:1], 4'b0}),
		.result(result)
  	);

endmodule
module udxs_sqrtiu (
	input [10:0] prev_att,
	input [10:0] prev_eps,
	input [10:0] prev_res,

	output [10:0] this_att,
	output [10:0] this_eps,
	output [10:0] this_res
);

	assign this_att = {1'b0, prev_att[10:1]};

	wire [10:0] this_delta_term1_half;
	wire [10:0] this_delta;
	reg [3:0] this_att_msb;
	wire [4:0] this_att_sq_exp;
	wire [10:0] this_att_sq;

	assign this_att_sq_exp = {this_att_msb, 1'b0};
	assign this_att_sq = 11'b1 << this_att_sq_exp;

	assign this_delta_term1_half = prev_res << this_att_msb;
	assign this_delta = {this_delta_term1_half[9:0], 1'b0} + this_att_sq;

	wire cond_met;
	assign cond_met = this_delta <= prev_eps;
	assign this_eps = cond_met ? prev_eps - this_delta : prev_eps; 
	assign this_res = cond_met ? prev_res | this_att : prev_res; 

	integer msb_idx;
	always @* begin
		this_att_msb = 0;

		for (msb_idx=0; msb_idx < 11; msb_idx++) begin
			if(this_att == (1 << msb_idx))
				this_att_msb = msb_idx[3:0];
		end

	end

endmodule
module udxs_sqrt(
	input clk,
	input [10:0] query,
	output reg [10:0] result
);

	reg [10:0] att;
	reg [10:0] eps;
	reg [10:0] res;

	wire [10:0] att_mid;
	wire [10:0] res_mid;
	wire [10:0] eps_mid;

	wire [10:0] att_next;
	wire [10:0] res_next;
	wire [10:0] eps_next;

	udxs_sqrtiu iteratorA(
						.prev_att(att),
						.prev_eps(eps), 
						.prev_res(res),
						.this_att(att_mid),
						.this_eps(eps_mid),
						.this_res(res_mid)
						);

	udxs_sqrtiu iteratorB(
						.prev_att(att_mid),
						.prev_eps(eps_mid), 
						.prev_res(res_mid),
						.this_att(att_next),
						.this_eps(eps_next),
						.this_res(res_next)
						);

	reg [1:0] iteration;
	
	always @(posedge clk) begin
		if (iteration != 3) begin
				att <= att_next;
				eps <= eps_next;
				res <= res_next;
				iteration <= iteration + 1;
			end else begin
				result <= res;
				eps <= query;
				att <= 1 << 6;
				res <= 0;
				iteration <= 0;
			end
	end

endmodule
module user_module_341535056611770964(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2 = io_in[1];
  wire net3 = io_in[2];
  wire net4 = io_in[3];
  wire net5 = io_in[4];
  wire net6 = io_in[5];
  wire net7 = io_in[6];
  wire net8 = io_in[7];
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13;
  wire net14;
  wire net15;
  wire net16;
  wire net17 = 1'b0;
  wire net18 = 1'b1;
  wire net19 = 1'b1;

  assign io_out[0] = net9;
  assign io_out[1] = net10;
  assign io_out[2] = net11;
  assign io_out[3] = net12;
  assign io_out[4] = net13;
  assign io_out[5] = net14;
  assign io_out[6] = net15;
  assign io_out[7] = net16;

  not_cell not1 (
    .in (net1),
    .out (net9)
  );
  not_cell not2 (
    .in (net2),
    .out (net10)
  );
  not_cell not3 (
    .in (net3),
    .out (net11)
  );
  not_cell not4 (
    .in (net4),
    .out (net12)
  );
  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  not_cell not5 (
    .in (net5),
    .out (net13)
  );
  not_cell not6 (
    .in (net6),
    .out (net14)
  );
  not_cell not7 (
    .in (net7),
    .out (net15)
  );
  not_cell not8 (
    .in (net8),
    .out (net16)
  );
endmodule
module thunderbird_taillight_ctrl #(
    parameter MAX_COUNT = 1000,
    parameter SYSTEM_FREQ = 6250,
    parameter HZ = 8
) (
    input  [7:0] io_in,
    output [7:0] io_out
);

  wire clk = io_in[0];
  wire reset = io_in[1];
  wire left = io_in[2];
  wire right = io_in[3];
  wire haz = io_in[4];

  wire [5:0] lights = state;
  assign io_out[7:0] = {2'b00, lights};

  wire div;
  divider #(
      .SYSTEM_FREQ(SYSTEM_FREQ),
      .HZ         (HZ)
  ) divider_i (
      .clk    (clk),
      .reset  (reset),
      .divider(div)
  );

  localparam IDLE = 6'b000_000;
  localparam L3 = 6'b111_000;
  localparam L2 = 6'b011_000;
  localparam L1 = 6'b001_000;
  localparam R3 = 6'b000_111;
  localparam R2 = 6'b000_110;
  localparam R1 = 6'b000_100;
  localparam LR3 = 6'b111_111;

  reg [5:0] state, next_state;

  always @(posedge clk) begin
    if (reset) begin
      state <= IDLE;
    end else begin
      if (div) begin
        state <= next_state;
      end
    end
  end

  always @(*) begin
    next_state = state;

    case (state)
      IDLE: begin
        case (1'b1)
          haz | (left & right): next_state = LR3;
          left: next_state = L1;
          right: next_state = R1;
          default: next_state = IDLE;
        endcase
      end

      L1: next_state = haz ? LR3 : L2;
      L2: next_state = haz ? LR3 : L3;
      L3: next_state = haz ? LR3 : IDLE;

      R1: next_state = haz ? LR3 : R2;
      R2: next_state = haz ? LR3 : R3;
      R3: next_state = haz ? LR3 : IDLE;

      LR3: next_state = IDLE;

      default: next_state = state;
    endcase
  end

endmodule
module divider #(
    parameter SYSTEM_FREQ = 6250,
    parameter HZ = 8
) (
    input  clk,
    input  reset,
    output divider
);
  localparam CYCLES = SYSTEM_FREQ / HZ;
  reg [$clog2(CYCLES) -1:0] cnt;
  always @(posedge clk) begin
    if (reset) begin
      cnt <= 0;
    end else begin
      cnt <= cnt + 1;
      /* verilator lint_off WIDTH */
      if (cnt >= (CYCLES - 1)) begin
        cnt <= 0;
      end
      /* verilator lint_on WIDTH */
    end
  end
  assign divider = cnt == 0;
endmodule
module rolfmobile99_alu_fsm_top(
  input [7:0] io_in,
  output [7:0] io_out
);

  wire clk = io_in[7];
  wire reset = io_in[6];
  wire ctl_in = io_in[5];
  wire notused = io_in[4];
  wire [3:0] databus = io_in[3:0];

  assign io_out[4] = aluCout;
  assign io_out[3:0] = aluOut[3:0];

  wire [2:0] state_out;
  wire enA, enB, enM, enC, selC;
  wire rst_out;

  wire [3:0] aluA, aluB;	// tmp: to alu A input
  wire aluCout;
  wire aluZ;				// notused
  wire [3:0] aluOut;
  wire [3:0] aluOp;			// bit0: add=0, sub=1  bit1: enCin  bit2,3: unused
  wire op0;					// bit0 of above

  assign op0 = aluOp[0];


  // connect modules

  alu_fsm alu_fsm(
    .ctl(ctl_in),
    .curstate(state_out),
    .rst_out(rst_out),
    .enA(enA),
    .enB(enB),
    .enM(enM),
    .enC(enC),
    .selC(selC),
    .reset(reset),
    .clk(clk) );	// clk with 'clk' signal

  flop_4 regA(
    .dd(databus),
    .qq(aluA),
    .qEn(1'b1),		// always enable output
    .reset(rst_out),// clear on reset state
    .cEn(enA),
    .clk(clk) );	// clk with 'clk' signal

  flop_4 regB(
    .dd(databus),
    .qq(aluB),
    .qEn(1'b1),		// always enable output
    .reset(rst_out),// clear on reset state
    .cEn(enB),
    .clk(clk) );	// clk with 'clk' signal

  flop_4 regM(
    .dd(databus),
    .qq(aluOp),		// note: regM drives aluOp lines
    .qEn(1'b1),		// always enable output
    .reset(rst_out),// clear on reset state
    .cEn(enM),
    .clk(clk) );	// clk with 'clk' signal

  alu_4 alu(
    .op(op0),	// controls add/sub
    .a(aluA),
    .b(aluB),
    .cin(1'b0),		// tmp: carryin=0
    .out(aluOut),
    .z(aluZ),		// alu zero (notused)
    .cout(aluCout),
    .outEn(1'b1) );	// always enable output

endmodule
module migcorre_pwm (
    input  [7:0] io_in,
    output [7:0] io_out
);

  wire clk = io_in[0];  // clock input 12.5KHz 
  wire reset = io_in[1];  // reset active high
  wire increase_duty_in = io_in[2];  // increase duty cycle by 10%
  wire decrease_duty_in = io_in[3];  // decrease duty cycle by 10%
  wire disable_debouncer_in = io_in[4];
  wire pwm_out;  // 1.2kHz PWM output signal 

  wire increase_duty_sync;
  wire decrease_duty_sync;
  wire disable_debouncer_sync;
  wire increase_duty_deb;
  wire decrease_duty_deb;
  wire increase_duty;
  wire decrease_duty;

  // Sinchronizers ------------------------/
  synchronizer #(
      .NUM_STAGES(2)
  ) synchronizer_increase_duty (
      .clk(clk),
      .async_in(increase_duty_in),
      .sync_out(increase_duty_sync)
  );

  synchronizer #(
      .NUM_STAGES(2)
  ) synchronizer_decrease_duty (
      .clk(clk),
      .async_in(decrease_duty_in),
      .sync_out(decrease_duty_sync)
  );

  synchronizer #(
      .NUM_STAGES(2)
  ) synchronizer_sisable_debouncer (
      .clk(clk),
      .async_in(disable_debouncer_in),
      .sync_out(disable_debouncer_sync)
  );

  // Debuncers ------------------------/
  debouncer #(
      .N(8)
  ) increase_debuncer (
      .clk(clk),
      .reset(reset),
      .signal_in(increase_duty_sync),
      .signal_out(increase_duty_deb)
  );

  debouncer #(
      .N(8)
  ) decrease_debuncer (
      .clk(clk),
      .reset(reset),
      .signal_in(decrease_duty_sync),
      .signal_out(decrease_duty_deb)
  );

  assign increase_duty = disable_debouncer_sync == 1 ? increase_duty_sync : increase_duty_deb;
  assign decrease_duty = disable_debouncer_sync == 1 ? decrease_duty_sync : decrease_duty_deb;

  // PWM ------------------------/
  pwm #(
      .INITIAL_DUTY(5)
  ) pwm_dc (
      .clk(clk), 
      .reset(reset), 
      .increase_duty_in(increase_duty),
      .decrease_duty_in(decrease_duty),
      .pwm_out(pwm_out) 
  );

  assign io_out[0] = pwm_out;
  assign io_out[1] = ~pwm_out;
  assign io_out[2] = increase_duty_sync;
  assign io_out[3] = decrease_duty_sync;

endmodule
module davidsiaw_stackcalc (
  input wire [7:0] io_in,
  output wire [7:0] io_out
);
  stack_cpu cpu(.io_in(io_in), .io_out(io_out));
endmodule
module user_module_349886696875098706(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2;
  wire net3;
  wire net4;
  wire net5;
  wire net6 = 1'b1;
  wire net7;
  wire net8 = 1'b0;
  wire net9 = 1'b0;
  wire net10 = 1'b1;
  wire net11 = 1'b1;
  wire net12;
  wire net13;
  wire net14;
  wire net15 = 1'b0;
  wire net16 = 1'b0;

  assign io_out[0] = net2;
  assign io_out[1] = net3;
  assign io_out[2] = net3;
  assign io_out[3] = net4;
  assign io_out[4] = net5;
  assign io_out[5] = net6;
  assign io_out[6] = net7;
  assign io_out[7] = net8;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  dff_cell flipflop2 (
    .d (net12),
    .clk (net1),
    .q (net3),
    .notq (net13)
  );
  dff_cell flipflop3 (
    .d (net13),
    .clk (net1),
    .q (net12),
    .notq (net14)
  );
  nand_cell gate7 (
    .a (net13),
    .b (net12),
    .out (net2)
  );
  nand_cell gate8 (
    .a (net3),
    .b (net12),
    .out (net4)
  );
  nand_cell gate9 (
    .a (net3),
    .b (net14),
    .out (net5)
  );
  nand_cell gate10 (
    .a (net13),
    .b (net14),
    .out (net7)
  );
endmodule
module cchan_fp8_multiplier (
  input [7:0] io_in,
  output [7:0] io_out
);
    wire clk = io_in[0];
    wire [2:0] ctrl = io_in[3:1];
    wire [3:0] data = io_in[7:4];
    // wire [6:0] led_out;
    // assign io_out[6:0] = led_out;
    // wire [5:0] seed_input = io_in[7:2];

    reg [8:0] operand1;
    reg [8:0] operand2;
    // For now we're commenting this out and leaving the results unbuffered.
    // reg [8:0] result_out;
    // assign io_out = result_out;

    always @(posedge clk) begin
        if (!ctrl[0]) begin  // if first CTRL bit is off, we're in STORE mode
            if (!ctrl[1]) begin  // second CTRL bit controls whether it's the first or second operand
                if (!ctrl[2]) begin  // third CTRL bit controls whether it's the upper or lower half
                    operand1[3:0] <= data;
                end else begin
                    operand1[7:4] <= data;
                end
            end else begin
                if (!ctrl[2]) begin
                    operand2[3:0] <= data;
                end else begin
                    operand2[7:4] <= data;
                end
            end
        end else begin  // if first CTRL bit is on, this is reserved.
            // TODO
            // if (!ctrl[1] && !ctrl[2]) begin
            //     result_out[7:0] <= 0;
            // end
        end
    end

    // Compute result_out in terms of operand1, operand2
    fp8mul mul1(
        .sign1(operand1[7]),
        .exp1(operand1[6:3]),
        .mant1(operand1[2:0]),
        .sign2(operand2[7]),
        .exp2(operand2[6:3]),
        .mant2(operand2[2:0]),
        .sign_out(io_out[7]),
        .exp_out(io_out[6:3]),
        .mant_out(io_out[2:0])
    );
endmodule
module fp8mul (
  input sign1,
  input [3:0] exp1,
  input [2:0] mant1,

  input sign2,
  input [3:0] exp2,
  input [2:0] mant2,

  output sign_out,
  output [3:0] exp_out,
  output [2:0] mant_out
);
    parameter EXP_BIAS = 7;
    wire isnan = (sign1 == 1 && exp1 == 0 && mant1 == 0) || (sign2 == 1 && exp2 == 0 && mant2 == 0);
    wire [7:0] full_mant = ({exp1 != 0, mant1} * {exp2 != 0, mant2});
    wire overflow_mant = full_mant[7];
    wire [6:0] shifted_mant = overflow_mant ? full_mant[6:0] : {full_mant[5:0], 1'b0};
    // is the mantissa overflowing up to the next exponent?
    wire roundup = (exp1 + exp2 + overflow_mant < 1 + EXP_BIAS) && (shifted_mant[6:0] != 0)
                   || (shifted_mant[6:4] == 3'b111 && shifted_mant[3]);
    wire underflow = (exp1 + exp2 + overflow_mant) < 1 - roundup + EXP_BIAS;
    wire is_zero = exp1 == 0 || exp2 == 0 || isnan || underflow;
    // note: you can't use negative numbers reliably. just keep things positive during compares.
    wire [4:0] exp_out_tmp = (exp1 + exp2 + overflow_mant + roundup) < EXP_BIAS ? 0 : (exp1 + exp2 + overflow_mant + roundup - EXP_BIAS);
    assign exp_out = exp_out_tmp > 15 ? 4'b1111 : (is_zero) ? 0 : exp_out_tmp[3:0];  // Exponent bias is 7
    assign mant_out = exp_out_tmp > 15 ? 3'b111 : (is_zero || roundup) ? 0 : (shifted_mant[6:4] + (shifted_mant[3:0] > 8 || (shifted_mant[3:0] == 8 && shifted_mant[4])));
    assign sign_out = ((sign1 ^ sign2) && !(is_zero)) || isnan;
endmodule
module luthor2k_top_tto
  #(parameter CLOCK_RATE=9600)
  (
   input [7:0]  io_in,
   output [7:0] io_out
   );
  
  // INPUTS
  wire                      clk_ascii   = io_in[0];
  wire                      clk_baudot = io_in[1];
  wire                      baudot_input = io_in[2];
  
  // OUTPUTS
  wire                      ascii_serial_output;
  wire                      baudot_ready_out;
  wire               [4:0]  baudot_byte_out;

  assign io_out[0] = ascii_serial_output;
  assign io_out[1] = baudot_ready_out;  
  //assign io_out[2] = 
  assign io_out[3] = baudot_byte_out[0];
  assign io_out[4] = baudot_byte_out[1];
  assign io_out[5] = baudot_byte_out[2];
  assign io_out[6] = baudot_byte_out[3];
  assign io_out[7] = baudot_byte_out[4];

  // instatiate converter  .function_pin(top_pin)
  main main(.v65b531(clk_ascii), .v3c4a34(clk_baudot), .vcb44a7(baudot_input), .v7c2fea(ascii_serial_output), .v40cda4(baudot_ready_out), .v4d3fdd(baudot_byte_out));
  
endmodule
module fraserbc_simon (
	io_in,
	io_out
);

	input  wire [7:0] io_in;
	output wire [7:0] io_out;

	assign io_out[7:4] = 4'b0;

	/* Instantiate main module */
	simon simon0 (
		.i_clk(io_in[0]),
		.i_shift(io_in[1]),
		.i_data(io_in[5:2]),
		.o_data(io_out[3:0])
	);

endmodule
module lfsr_z0(
	i_clk,
	i_rst,
	o_data
);

	input  wire i_clk;
	input  wire i_rst;
	output wire o_data;

	reg [4:0] r_lfsr;
	assign o_data = r_lfsr[0];

	always @(posedge i_clk)
		if(i_rst)
			r_lfsr <= 5'b00001;
		else begin
			r_lfsr[4] <= r_lfsr[3];
			r_lfsr[3] <= r_lfsr[2];
			r_lfsr[2] <= r_lfsr[4] ^ r_lfsr[1];
			r_lfsr[1] <= r_lfsr[0];
			r_lfsr[0] <= r_lfsr[4] ^ r_lfsr[0];
		end

endmodule
module simon (
	i_clk,
	i_shift,
	i_data,
	o_data
);

	input  wire       i_clk;
	input  wire       i_shift;
	input  wire [3:0] i_data;
	output wire [3:0] o_data;

	assign o_data = r_round[3:0];

	/* z0 Sequence */
	wire w_z0;
	lfsr_z0 lfsr0 (
		.i_clk(i_clk),
		.i_rst(i_shift),
		.o_data(w_z0)
	);

	/* Key Schedule */
	reg [63:0] r_key;
	wire [15:0] w_temp = r_key[31:16] ^ {r_key[50:48],r_key[63:51]};	// Right circular shift
	always @(posedge i_clk) begin
		if (i_shift)
			r_key <= {i_data, r_key[63:4]};
		else begin
			r_key[15:0] <= r_key[31:16];
			r_key[31:16] <= r_key[47:32];
			r_key[47:32] <= r_key[63:48];
			r_key[63:48] <= (2**16 - 4) ^ {{15{1'b0}}, w_z0} ^ w_temp ^ r_key[15:0] ^ {w_temp[0],w_temp[15:1]};
		end
	end

	/* Encrypt */
	reg [31:0] r_round;
	always @(posedge i_clk) begin
		if (i_shift)
			r_round <= {r_key[3:0], r_round[31:4]};
		else begin
			r_round[15:0] <= r_round[31:16];
			r_round[31:16] <= (({r_round[30:16],r_round[31]} & {r_round[23:16],r_round[31:24]})) ^ {r_round[29:16],r_round[31:30]} ^ r_key[15:0] ^ r_round[15:0];
		end
	end

endmodule
module jglim_7seg(  
    input [7:0] io_in,
    output [7:0] io_out
);

hex7seg seg7(
    .counter(io_in[3:0]), 
    .dot(io_in[4]), 
    .inv(io_in[5]), 
    .segments(io_out[7:0])
);

endmodule
module tt2_tholin_multiplier(
    input [7:0] io_in,
    output [7:0] io_out
);
   wire s_A0 = io_in[0];
   wire s_A1 = io_in[1];
   wire s_A2 = io_in[2];
   wire s_A3 = io_in[3];
   wire s_B0 = io_in[4];
   wire s_B1 = io_in[5];
   wire s_B2 = io_in[6];
   wire s_B3 = io_in[7];
   wire s_R0;
   wire s_R1;
   wire s_R2;
   wire s_R3;
   wire s_R4;
   wire s_R5;
   wire s_R6;
   wire s_R7;
   assign io_out[0] = s_R0;
   assign io_out[1] = s_R1;
   assign io_out[2] = s_R2;
   assign io_out[3] = s_R3;
   assign io_out[4] = s_R4;
   assign io_out[5] = s_R5;
   assign io_out[6] = s_R6;
   assign io_out[7] = s_R7;
   main   CIRCUIT_0 (.A0(s_A0),
                     .A1(s_A1),
                     .A2(s_A2),
                     .A3(s_A3),
                     .B0(s_B0),
                     .B1(s_B1),
                     .B2(s_B2),
                     .B3(s_B3),
                     .R0(s_R0),
                     .R1(s_R1),
                     .R2(s_R2),
                     .R3(s_R3),
                     .R4(s_R4),
                     .R5(s_R5),
                     .R6(s_R6),
                     .R7(s_R7));
endmodule
module asic_multiplier_wrapper (
    input  [7:0] io_in ,
    output [7:0] io_out
);

    // Instantiate the multiplier
    asic_multiplier asic_multiplier_top (
        .clk        (io_in[0]   ),
        .reset      (io_in[1]   ),
        .i_factor_a (io_in[4:2] ),
        .i_factor_b (io_in[7:5] ),
        .o_segments (io_out[6:0]),
        .o_lsb_digit(io_out[7]  )
    );

endmodule
module tt2_tholin_namebadge (
	input [7:0] io_in,
	output [7:0] io_out
);
	wire CLK = io_in[0];
	wire RST = io_in[1];
	wire EF0 = io_in[2];
	wire EF1 = io_in[3];
	wire EF2 = io_in[4];
	wire RS;
	wire E;
	wire D4;
	wire D5;
	wire D6;
	wire D7;
	wire LED0;
	wire LED1;
	assign io_out[0] = RS;
	assign io_out[1] = E;
	assign io_out[2] = D4;
	assign io_out[3] = D5;
	assign io_out[4] = D6;
	assign io_out[5] = D7;
	assign io_out[6] = LED0;
	assign io_out[7] = LED1;
	
	lcd lcd (
		.CLK(CLK),
		.RST(RST),
		.EF0(EF0),
		.EF1(EF1),
		.EF2(EF2),
		.RS(RS),
		.E(E),
		.D4(D4),
		.D5(D5),
		.D6(D6),
		.D7(D7),
		.LED0(LED0),
		.LED1(LED1)
		);
endmodule