dakies/OSS_Verilog huggingface dataset:
module bus_delay(
  paddr,
  pclk,
  penable,
  prdata,
  presetn,
  psel,
  pwdata,
  pwrite,
  bus_delay_counter
);


input   [15:0]  paddr;                 
input           pclk;                  
input           penable;               
input           presetn;               
input           psel;                  
input   [31:0]  pwdata;
input           pwrite;
output  [31:0]  prdata;                
output  [31:0]  bus_delay_counter;


reg     [31:0]  prdata;                
reg     [31:0]  bus_delay_counter;


wire    [15:0]  paddr;                 
wire            pclk;                  
wire            presetn;               
wire            psel;                  
wire    [31:0]  pwdata;                
wire            pwrite;  












always @(posedge pclk or negedge presetn)
begin
  if(!presetn)
  begin
    bus_delay_counter <= 32'b0;
  end
  else if(psel && pwrite && penable && (~|paddr[7:2])) begin
    bus_delay_counter <= pwdata;
  end
end
    



always @(posedge pclk)
begin
  if(psel && !pwrite && !penable && (~|paddr[7:0])) begin
    prdata <= bus_delay_counter;
  end
  else begin
	prdata <= 32'b0;
  end
end

endmodule
module axi_fifo_entry(
  create_en,
  data_in,
  data_out,
  entry_clk,
  entry_rst_b
);


input           create_en;  
input   [70:0]  data_in;    
input           entry_clk;  
input           entry_rst_b; 
output  [70:0]  data_out;   


reg     [70:0]  data_out;   


wire            create_en;  
wire    [70:0]  data_in;    
wire            entry_clk;  
wire            entry_rst_b; 


always @(posedge entry_clk or negedge entry_rst_b)
begin
  if (!entry_rst_b)
    data_out[70:0] <= 71'b0;
  else if (create_en)
    data_out[70:0] <= data_in[70:0];
  else
    data_out[70:0] <= data_out[70:0];
end







endmodule
module clint_top(
  apb_clk_en,
  ciu_clk,
  clint_core0_ms_int,
  clint_core0_mt_int,
  clint_core0_ss_int,
  clint_core0_st_int,
  clint_core0_time,
  cpurst_b,
  forever_apbclk,
  pad_yy_icg_scan_en,
  paddr,
  penable,
  perr_clint,
  pprot,
  prdata_clint,
  pready_clint,
  psel_clint,
  pwdata,
  pwrite,
  sysio_clint_mtime
);

// &Ports; @25
input           apb_clk_en;        
input           ciu_clk;           
input           cpurst_b;          
input           forever_apbclk;    
input           pad_yy_icg_scan_en; 
input   [31:0]  paddr;             
input           penable;           
input   [1 :0]  pprot;             
input           psel_clint;        
input   [31:0]  pwdata;            
input           pwrite;            
input   [63:0]  sysio_clint_mtime; 
output          clint_core0_ms_int; 
output          clint_core0_mt_int; 
output          clint_core0_ss_int; 
output          clint_core0_st_int; 
output  [63:0]  clint_core0_time;  
output          perr_clint;        
output  [31:0]  prdata_clint;      
output          pready_clint;      

// &Regs; @26

// &Wires; @27
wire            apb_clk_en;        
wire            ciu_clk;           
wire            clint_core0_ms_int; 
wire            clint_core0_mt_int; 
wire            clint_core0_ss_int; 
wire            clint_core0_st_int; 
wire    [63:0]  clint_core0_time;  
wire            cpurst_b;          
wire            forever_apbclk;    
wire            pad_yy_icg_scan_en; 
wire    [31:0]  paddr;             
wire            penable;           
wire            perr_clint;        
wire    [1 :0]  pprot;             
wire    [31:0]  prdata_clint;      
wire            pready_clint;      
wire            psel_clint;        
wire    [31:0]  pwdata;            
wire            pwrite;            
wire    [63:0]  sysio_clint_mtime; 


//==========================================================
// Instance clint func
//==========================================================
// &Instance("clint_func"); @32
clint_func  x_clint_func (
  .apb_clk_en         (apb_clk_en        ),
  .ciu_clk            (ciu_clk           ),
  .clint_core0_ms_int (clint_core0_ms_int),
  .clint_core0_mt_int (clint_core0_mt_int),
  .clint_core0_ss_int (clint_core0_ss_int),
  .clint_core0_st_int (clint_core0_st_int),
  .clint_core0_time   (clint_core0_time  ),
  .cpurst_b           (cpurst_b          ),
  .forever_apbclk     (forever_apbclk    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en),
  .paddr              (paddr             ),
  .penable            (penable           ),
  .perr_clint         (perr_clint        ),
  .pprot              (pprot             ),
  .prdata_clint       (prdata_clint      ),
  .pready_clint       (pready_clint      ),
  .psel_clint         (psel_clint        ),
  .pwdata             (pwdata            ),
  .pwrite             (pwrite            ),
  .sysio_clint_mtime  (sysio_clint_mtime )
);



// &ModuleEnd; @35
endmodule
module aq_rtu_int(
  cp0_rtu_int_vld,
  dp_int_ex2_inst_split,
  dtu_rtu_int_mask,
  int_retire_int_vec,
  int_retire_int_vld
);


// &Ports; @25
input   [14:0]  cp0_rtu_int_vld;      
input           dp_int_ex2_inst_split; 
input           dtu_rtu_int_mask;     
output  [4 :0]  int_retire_int_vec;   
output          int_retire_int_vld;   

// &Regs; @26
reg     [4 :0]  int_vec;              

// &Wires; @27
wire    [14:0]  cp0_rtu_int_vld;      
wire            dp_int_ex2_inst_split; 
wire            dtu_rtu_int_mask;     
wire    [4 :0]  int_retire_int_vec;   
wire            int_retire_int_vld;   
wire            int_vld;              
wire    [14:0]  int_vld_raw;          



//==========================================================
//                        Int Source
//==========================================================
assign int_vld_raw[14:0] = cp0_rtu_int_vld[14:0];

// &CombBeg; @35
always @( int_vld_raw[14:0])
begin
casez(int_vld_raw[14:0])
  15'b1?????????????? : int_vec[4:0] = 5'd16; // mcip
  15'b01????????????? : int_vec[4:0] = 5'd18; // mhip
  15'b001???????????? : int_vec[4:0] = 5'd11; // meip
  15'b0001??????????? : int_vec[4:0] = 5'd3;  // msip
  15'b00001?????????? : int_vec[4:0] = 5'd7;  // mtip
  15'b000001????????? : int_vec[4:0] = 5'd9;  // seip
  15'b0000001???????? : int_vec[4:0] = 5'd1;  // ssip
  15'b00000001??????? : int_vec[4:0] = 5'd5;  // stip
  15'b000000001?????? : int_vec[4:0] = 5'd17; // moip
  15'b0000000001????? : int_vec[4:0] = 5'd16; // mcip
  15'b00000000001???? : int_vec[4:0] = 5'd18; // mhip
  15'b000000000001??? : int_vec[4:0] = 5'd9;  // seip
  15'b0000000000001?? : int_vec[4:0] = 5'd1;  // ssip
  15'b00000000000001? : int_vec[4:0] = 5'd5;  // stip
  15'b000000000000001 : int_vec[4:0] = 5'd17; // moip
  default      : int_vec[4:0] = {5{1'bx}};
endcase
// &CombEnd; @54
end

//==========================================================
//                        Int Judge
//==========================================================
assign int_vld = |int_vld_raw[14:0]
                 && !dtu_rtu_int_mask
                 && !dp_int_ex2_inst_split;

//==========================================================
//                          Output
//==========================================================
assign int_retire_int_vld     = int_vld;
assign int_retire_int_vec[4:0] = int_vec[4:0];

// &ModuleEnd; @69
endmodule
module aq_vdsp_8_bit_ff1(
  out,
  rem,
  src,
  zero
);

// &Ports; @18
input   [7:0]  src;   
output  [4:0]  out;   
output         rem;   
output         zero;  

// &Regs; @19
reg            rem_1; 
reg     [4:0]  result; 

// &Wires; @20
wire    [4:0]  out;   
wire           rem;   
wire    [7:0]  src;   
wire           zero;  


// &CombBeg; @22
always @( src[7:0])
begin
casez(src[7:0])
  8'b1???_????: begin rem_1 = &src[6:0]; result[4:0] = 5'b11111; end 
  8'b01??_????: begin rem_1 = &src[5:0]; result[4:0] = 5'b00000; end
  8'b001?_????: begin rem_1 = &src[4:0]; result[4:0] = 5'b00001; end
  8'b0001_????: begin rem_1 = &src[3:0]; result[4:0] = 5'b00010; end
  8'b0000_1???: begin rem_1 = &src[2:0]; result[4:0] = 5'b00011; end
  8'b0000_01??: begin rem_1 = &src[1:0]; result[4:0] = 5'b00100; end
  8'b0000_001?: begin rem_1 =  src[0]  ; result[4:0] = 5'b00101; end
  8'b0000_0001: begin rem_1 = 1'b1     ; result[4:0] = 5'b00110; end
  8'b0000_0000: begin rem_1 = 1'b1     ; result[4:0] = 5'b00111; end
  default     : begin rem_1 = 1'bx     ; result[4:0] ={5{1'bx}}; end
endcase
// &CombEnd; @35
end

assign out[4:0] = result[4:0];
assign rem      = rem_1;
assign zero     = (src[7:0]==8'b0000_0000);

// &ModuleEnd; @41
endmodule
module aq_cp0_vector_inst(
  iui_special_rs1_x0,
  iui_special_vsetvl,
  iui_special_vsetvl_dp,
  iui_special_vsetvl_rs1,
  iui_special_vsetvl_rs2,
  special_iui_vsetvl_wdata,
  special_regs_vsetvl_dp
);


// &Ports; @25
input           iui_special_rs1_x0;      
input           iui_special_vsetvl;      
input           iui_special_vsetvl_dp;   
input   [63:0]  iui_special_vsetvl_rs1;  
input   [11:0]  iui_special_vsetvl_rs2;  
output  [63:0]  special_iui_vsetvl_wdata; 
output          special_regs_vsetvl_dp;  

// &Regs; @26

// &Wires; @27
wire    [63:0]  special_iui_vsetvl_wdata; 
wire            special_regs_vsetvl_dp;  


// &Force("bus", "iui_special_vsetvl_rs2", 11, 0); @36
// &CombBeg; @85
// &CombEnd; @113
// &Force("output","special_vsetvl_illegal"); @141
// &CombBeg; @142
// &CombEnd; @155
assign special_iui_vsetvl_wdata[63:0] = 64'b0;
// &Force("input", "iui_special_vsetvl_rs1"); &Force("bus", "iui_special_vsetvl_rs1", 63, 0); @178
// &Force("input", "iui_special_vsetvl_rs2"); &Force("bus", "iui_special_vsetvl_rs2", 11, 0); @179
// &Force("input", "iui_special_rs1_x0"); @180
// &Force("input", "iui_special_vsetvl"); @181
// &Force("input", "iui_special_vsetvl_dp"); @182
assign special_regs_vsetvl_dp = 1'b0;

// &ModuleEnd; @186
endmodule
module aq_cp0_cache_inst(
  iui_special_cache,
  iui_special_cache_func,
  special_cacheop_op,
  special_cacheop_type,
  special_dcacheop_req,
  special_icacheop_req
);


// &Ports; @25
input          iui_special_cache;     
input   [5:0]  iui_special_cache_func; 
output  [1:0]  special_cacheop_op;    
output  [1:0]  special_cacheop_type;  
output         special_dcacheop_req;  
output         special_icacheop_req;  

// &Regs; @26

// &Wires; @27
wire    [5:0]  cache_func;            
wire    [1:0]  inst_dst;              
wire    [1:0]  inst_op;               
wire    [1:0]  inst_type;             
wire           iui_special_cache;     
wire    [5:0]  iui_special_cache_func; 
wire    [1:0]  special_cacheop_op;    
wire    [1:0]  special_cacheop_type;  
wire           special_dcacheop_req;  
wire           special_icacheop_req;  


//==========================================================
//                    Cache Inst Decode
//==========================================================
parameter NOP    = 2'b00;
parameter DCHE   = 2'b01;
parameter ICHE   = 2'b10;

parameter ALL    = 2'b00;
parameter SW     = 2'b01;
parameter VA     = 2'b10;
parameter PA     = 2'b11;

parameter INV    = 2'b01;
parameter CLN    = 2'b10;
parameter CI     = 2'b11;

//==========================================================
//                   Cache Inst Decode
//==========================================================
assign cache_func[5:0] = iui_special_cache_func[5:0];
assign inst_dst[1:0]  = cache_func[1:0];
assign inst_op[1:0]   = cache_func[3:2];
assign inst_type[1:0] = cache_func[5:4];

assign special_dcacheop_req = iui_special_cache && inst_dst[0];
assign special_icacheop_req = iui_special_cache && inst_dst[1];

assign special_cacheop_type[1:0] = inst_type[1:0];
assign special_cacheop_op[1:0]   = inst_op[1:0];

// &ModuleEnd; @59
endmodule
module aq_mmu_sysmap_hit(
  addr_ge_bottom_x,
  addr_ge_upaddr_x,
  sysmap_comp_hit_x,
  sysmap_mmu_hit_x
);

// &Ports; @27
input        addr_ge_bottom_x; 
input        sysmap_comp_hit_x; 
output       addr_ge_upaddr_x; 
output       sysmap_mmu_hit_x; 

// &Regs; @28

// &Wires; @29
wire         addr_ge_bottom_x; 
wire         addr_ge_upaddr_x; 
wire         addr_ls_top;      
wire         sysmap_comp_hit_x; 
wire         sysmap_mmu_hit_x; 



assign addr_ls_top      = sysmap_comp_hit_x;

assign addr_ge_upaddr_x = !addr_ls_top;
assign sysmap_mmu_hit_x = addr_ge_bottom_x && addr_ls_top;

// &ModuleEnd; @37
endmodule
module_en,
  local_en,
  external_en,
  pad_yy_icg_scan_en,
  clk_out
);

input  clk_in;
input  global_en;
input  module_en;
input  local_en;
input  external_en;
input  pad_yy_icg_scan_en;
output clk_out;

wire   clk_en_bf_latch;
wire   SE;

assign clk_en_bf_latch = (global_en && (module_en || local_en)) || external_en ;

// SE driven from primary input, held constant
assign SE	       = pad_yy_icg_scan_en;
 
// //   &Connect(    .clk_in           (clk_in), @50
// //                .SE               (SE), @51
// //                .external_en      (clk_en_bf_latch), @52
// //                .clk_out          (clk_out) @53
// //                ) ; @54

assign clk_out = clk_in;

endmodule
module aq_mp_clk_top(
  apb_clk,
  apb_clk_en,
  axim_clk_en,
  axim_clk_en_f,
  clkgen_rst_b,
  forever_cpuclk,
  pad_yy_scan_mode,
  pll_core_cpuclk
);

// &Ports; @24
input        axim_clk_en;      
input        clkgen_rst_b;     
input        pad_yy_scan_mode; 
input        pll_core_cpuclk;  
output       apb_clk;          
output       apb_clk_en;       
output       axim_clk_en_f;    
output       forever_cpuclk;   

// &Regs; @25
reg          apb_clk_en_f;     
reg          axim_clk_en_f;    
reg          peripheral_clk_en; 

// &Wires; @26
wire         apb_clk_en;       
wire         axim_clk_en;      
wire         clkgen_rst_b;     
wire         forever_cpuclk;   
wire         pad_yy_scan_mode; 
wire         pll_core_cpuclk;  


// &Depend("BUFGCE.v"); @28
// &Force("output","forever_cpuclk"); @29

assign forever_cpuclk = pll_core_cpuclk;

//================================================
//            APB CLOCK
//================================================
// &Force("output", "apb_clk_en"); @36

always@(posedge forever_cpuclk or negedge clkgen_rst_b)
begin
  if (!clkgen_rst_b)
    peripheral_clk_en <= 1'b0;
  else
    peripheral_clk_en <= ~peripheral_clk_en;
end

always@(posedge forever_cpuclk)
begin
  apb_clk_en_f <= peripheral_clk_en;
end

assign apb_clk_en = pad_yy_scan_mode ? 1'b1 : apb_clk_en_f;

// &Force("output","apb_clk"); @54

BUFGCE apb_clk_buf
(.O   (apb_clk),
 .I   (forever_cpuclk),
 .CE  (apb_clk_en_f)
);
// &Instance("gated_clk_cell", "x_apb_gated_clk"); @62
// &Connect(.clk_in      (forever_cpuclk), @63
//          .external_en (1'b0          ), @64
//          .global_en   (1'b1          ), @65
//          .module_en   (1'b0          ), @66
//          .local_en    (apb_clk_en_f  ), @67
//          .clk_out     (apb_clk       ) @68
//          .pad_yy_icg_scan_en (1'b0) @69
// ); @70


//================================================
//           AXIM CLK_EN
//================================================
// &Force("output", "axim_clk_en_f"); @77

always@(posedge forever_cpuclk)
begin
  axim_clk_en_f <= axim_clk_en;
end

////================================================
////            JTAG_CLOCK
////================================================
//
//assign forever_jtgclk = pad_had_jtg_tclk;

// &ModuleEnd; @90
endmodule
module aq_dtu_cdc_pulse(
  dst_clk,
  dst_pulse,
  dst_rstn,
  src_clk,
  src_pulse,
  src_rstn
);

// &Ports; @21
input        dst_clk;      
input        dst_rstn;     
input        src_clk;      
input        src_pulse;    
input        src_rstn;     
output       dst_pulse;    

// &Regs; @22
reg          dst_sync1;    
reg          dst_sync2;    
reg          dst_sync3;    
reg          dst_sync4;    
reg          src_lvl;      
reg          src_sync1;    
reg          src_sync2;    
reg          src_sync3;    
reg          src_sync4;    

// &Wires; @23
wire         clear_src_lvl; 
wire         dst_clk;      
wire         dst_pulse;    
wire         dst_rstn;     
wire         src_clk;      
wire         src_pulse;    
wire         src_rstn;     


always @(posedge src_clk or negedge src_rstn)
begin
  if(!src_rstn)
    src_lvl <= 1'b0;
  else if(src_pulse)
    src_lvl <= 1'b1;
  else if(clear_src_lvl)
    src_lvl <= 1'b0;
end

always @(posedge dst_clk or negedge dst_rstn)
begin
  if(!dst_rstn)
    begin
      dst_sync1 <= 1'b0;
      dst_sync2 <= 1'b0;
      dst_sync3 <= 1'b0;
      dst_sync4 <= 1'b0;
    end
  else
    begin
      dst_sync1 <= src_lvl;
      dst_sync2 <= dst_sync1;
      dst_sync3 <= dst_sync2;
      dst_sync4 <= dst_sync3;
    end
end

always @(posedge src_clk or negedge src_rstn)
begin
  if(!src_rstn)
    begin
      src_sync1 <= 1'b0;
      src_sync2 <= 1'b0;
      src_sync3 <= 1'b0;
      src_sync4 <= 1'b0;
    end
  else
    begin
      src_sync1 <= dst_sync3;
      src_sync2 <= src_sync1;
      src_sync3 <= src_sync2;
      src_sync4 <= src_sync3;
    end
end
assign clear_src_lvl = src_sync3 && !src_sync4;

assign dst_pulse = dst_sync3 && !dst_sync4;

// &ModuleEnd; @74
endmodule
module aq_dtu_cdc_lvl(
  clk,
  dst_lvl,
  rst_n,
  src_lvl
);

// &Ports; @21
input        clk;    
input        rst_n;  
input        src_lvl; 
output       dst_lvl; 

// &Regs; @22
reg          sync1;  
reg          sync2;  
reg          sync3;  

// &Wires; @23
wire         clk;    
wire         dst_lvl; 
wire         rst_n;  
wire         src_lvl; 


always @(posedge clk or negedge rst_n)
begin
  if(!rst_n)
    begin
      sync1 <= 1'b0;
      sync2 <= 1'b0;
      sync3 <= 1'b0;
    end
  else 
    begin
      sync1 <= src_lvl;
      sync2 <= sync1;  
      sync3 <= sync2;
    end
end
assign dst_lvl = sync3;

// &ModuleEnd; @42
endmodule
module prio_sel(
  //input
  data_in,
  sel_in,
  //out
  data_out,
  pos_out
);
parameter DATA    = 4;
parameter SEL     = 32;
parameter SEL_BIT = 5;

input   [DATA*SEL-1:0]  data_in;
input   [SEL-1:0]       sel_in;

output  [DATA-1:0]      data_out;
output  [SEL_BIT-1:0]   pos_out;

//wire definition

wire    [SEL-1:0]             tmp_sel; 
wire    [SEL:0]               tmp_sel2; 
wire    [SEL-1:0]             onehot_sel;
wire    [(SEL+1)*DATA-1:0]    tmp_out;
wire    [(SEL+1)*SEL_BIT-1:0] tmp_pos_out;
wire    [SEL:0]               sel_in_exp;

//**************************************
//  make the select to all ones
//  01100   -> 01111
//**************************************
assign sel_in_exp[SEL:0]  = {1'b0,sel_in[SEL-1:0]};
genvar k;
generate 
  for(k=0;k<SEL;k=k+1)
  begin:ALL_ONE_SEL
  assign tmp_sel[k] = |sel_in_exp[SEL:k];
  end
endgenerate
//**************************************
//  make the select to  one hot
//  01111   -> 01000
//**************************************

assign tmp_sel2[SEL:0] = {1'b0,tmp_sel[SEL-1:0]};
genvar m;
generate 
  for(m=0;m<SEL;m=m+1)
  begin:ONE_HOT_SEL
  assign onehot_sel[m] = tmp_sel[m] && !tmp_sel2[m+1];
  end
endgenerate
assign tmp_out[DATA-1:0] = {DATA{1'b0}};
assign tmp_pos_out[SEL_BIT-1:0] = {SEL_BIT{1'b0}};
genvar n;
generate 
  for(n=0;n<SEL;n=n+1)
  begin:OUT_SEL
  assign tmp_out[(n+1)*DATA+:DATA] = ({DATA{onehot_sel[n]}} & data_in[n*DATA+:DATA])
                                    | tmp_out[n*DATA+:DATA];
  assign tmp_pos_out[(n+1)*SEL_BIT+:SEL_BIT] = ({SEL_BIT{onehot_sel[n]}} & n)
                                                | tmp_pos_out[n*SEL_BIT+:SEL_BIT];  
  end
endgenerate

assign data_out[DATA-1:0]   = tmp_out[(SEL+1)*DATA-1:SEL*DATA];
assign pos_out[SEL_BIT-1:0] = tmp_pos_out[(SEL+1)*SEL_BIT-1:SEL*SEL_BIT];
endmodule
module instance_reg_flog(
  //input
  clk,
  rst_b,
  en,
  data_in,
  //output
  data_out
);
parameter DATA = 32;

input             clk;
input             rst_b;
input             en;
input  [DATA-1:0] data_in;

output [DATA-1:0] data_out;

reg    [DATA-1:0] data_flop;

always @(posedge clk or negedge rst_b)
begin
  if(!rst_b)
    data_flop[DATA-1:0] <= {DATA{1'b0}};
  else if(en)
    data_flop[DATA-1:0] <= data_in[DATA-1:0];
end
assign data_out[DATA-1:0] = data_flop[DATA-1:0];
endmodule
module nor_sel(
  //input
  data_in,
  sel_in,
  //out
  data_out
);
parameter    SEL_BIT  = 5;
parameter    SEL_NUM  = 32;
parameter    DATA     = 10;

input   [SEL_NUM*DATA-1:0]        data_in;
input   [SEL_BIT-1:0]                 sel_in;

output  [DATA-1:0]                data_out;


//wire definition
wire [SEL_NUM-1:0]          sel_onehot;
wire [(SEL_NUM+1)*DATA-1:0] tmp_sel_out; 
//reg definition


assign tmp_sel_out[DATA-1:0]  = {DATA{1'b0}};
generate
genvar i;
for(i=0;i<SEL_NUM;i=i+1)
begin: SEL_OUT
  assign sel_onehot[i]                 = sel_in[SEL_BIT-1:0] == i;
  assign tmp_sel_out[(i+1)*DATA+:DATA] = ({DATA{sel_onehot[i]}} & data_in[DATA*i+:DATA])
                                        | tmp_sel_out[DATA*i+:DATA];
end
endgenerate
assign data_out[DATA-1:0]             = tmp_sel_out[DATA*SEL_NUM+:DATA];

endmodule
module booth_code_33_bit(
  A,
  code,
  h,
  product,
  sn
);

// &Ports; @22
input   [32:0]  A;      
input   [2 :0]  code;   
output  [1 :0]  h;      
output  [32:0]  product; 
output          sn;     

// &Regs; @23
reg     [1 :0]  h;      
reg     [32:0]  product; 
reg             sn;     

// &Wires; @24
wire    [32:0]  A;      
wire    [2 :0]  code;   


parameter SRC_WIDTH = 33;

// &CombBeg; @28
always @( A[32:0]
       or code[2:0])
begin
case(code[2:0])
3'b000 : product[SRC_WIDTH-1:0] =    {SRC_WIDTH{1'b0}};
3'b001 : product[SRC_WIDTH-1:0] =  {A[SRC_WIDTH-1:0]};
3'b010 : product[SRC_WIDTH-1:0] =  {A[SRC_WIDTH-1:0]};
3'b011 : product[SRC_WIDTH-1:0] =  {A[SRC_WIDTH-2:0],1'b0};
3'b100 : product[SRC_WIDTH-1:0] = {~A[SRC_WIDTH-2:0],1'b0};
3'b101 : product[SRC_WIDTH-1:0] = {~A[SRC_WIDTH-1:0]};
3'b110 : product[SRC_WIDTH-1:0] = {~A[SRC_WIDTH-1:0]};
3'b111 : product[SRC_WIDTH-1:0] =    {SRC_WIDTH{1'b0}};
default: product[SRC_WIDTH-1:0] =    {SRC_WIDTH{1'bx}};
endcase
// &CombEnd; @40
end

// &CombBeg; @42
always @( A[32]
       or code[2:0])
begin
case(code[2:0])
3'b000 : sn =  1'b1;
3'b001 : sn = ~A[SRC_WIDTH-1];
3'b010 : sn = ~A[SRC_WIDTH-1];
3'b011 : sn = ~A[SRC_WIDTH-1];
3'b100 : sn =  A[SRC_WIDTH-1];
3'b101 : sn =  A[SRC_WIDTH-1];
3'b110 : sn =  A[SRC_WIDTH-1];
3'b111 : sn =  1'b1;
default: sn =  1'bx;
endcase
// &CombEnd; @54
end

// &CombBeg; @56
always @( code[2:0])
begin
case(code[2:0])
3'b000 : h[1:0] = 2'b00;
3'b001 : h[1:0] = 2'b00;
3'b010 : h[1:0] = 2'b00;
3'b011 : h[1:0] = 2'b00;
3'b100 : h[1:0] = 2'b10;
3'b101 : h[1:0] = 2'b01;
3'b110 : h[1:0] = 2'b01;
3'b111 : h[1:0] = 2'b00;
default: h[1:0] = {2{1'bx}};
endcase
// &CombEnd; @68
end

// &ModuleEnd; @70
endmodule
module aq_iu_addr_gen(
  ag_bju_pc,
  bju_ag_cur_pc,
  bju_ag_offset,
  bju_ag_offset_sel,
  bju_ag_use_pc,
  idu_bju_ex1_gateclk_sel,
  idu_iu_ex1_src0,
  idu_iu_ex1_src2,
  mmu_xx_mmu_en
);

// &Ports; @24
input   [39:0]  bju_ag_cur_pc;          
input   [63:0]  bju_ag_offset;          
input           bju_ag_offset_sel;      
input           bju_ag_use_pc;          
input           idu_bju_ex1_gateclk_sel; 
input   [63:0]  idu_iu_ex1_src0;        
input   [63:0]  idu_iu_ex1_src2;        
input           mmu_xx_mmu_en;          
output  [63:0]  ag_bju_pc;              

// &Regs; @25

// &Wires; @26
wire    [63:0]  ag_adder_res;           
wire    [63:0]  ag_adder_rs1;           
wire    [63:0]  ag_adder_rs1_raw;       
wire    [63:0]  ag_adder_rs2;           
wire    [63:0]  ag_bju_pc;              
wire            ag_rs1_use_pc;          
wire            ag_src_operand_mux;     
wire    [39:0]  bju_ag_cur_pc;          
wire    [63:0]  bju_ag_offset;          
wire            bju_ag_offset_sel;      
wire            bju_ag_use_pc;          
wire            idu_bju_ex1_gateclk_sel; 
wire    [63:0]  idu_iu_ex1_src0;        
wire    [63:0]  idu_iu_ex1_src2;        
wire            mmu_xx_mmu_en;          


// &Force("bus", "bju_ag_cur_pc", 39, 0); @28
//==========================================================
//                   Address Generator
//==========================================================
// Address Generator generate address for:
//   1. jump, branch inst;
//   2. auipc inst;

//----------------------------------------------------------
//                  BJU Address Generator
//----------------------------------------------------------
//----------- Oper Prepare -------------
// branch inst, auipc inst use pc as rs1.
assign ag_src_operand_mux     = idu_bju_ex1_gateclk_sel;
assign ag_rs1_use_pc          = bju_ag_use_pc;

assign ag_adder_rs1_raw[63:0] = {64{ag_src_operand_mux}} & idu_iu_ex1_src0[63:0];
assign ag_adder_rs1[63:0]     = ag_rs1_use_pc ? {{24{mmu_xx_mmu_en & bju_ag_cur_pc[39]}}, bju_ag_cur_pc[39:1], 1'b0}
                                              : ag_adder_rs1_raw[63:0];

// bju entry inst, calculate tar pc
assign ag_adder_rs2[63:0]     = bju_ag_offset_sel ? bju_ag_offset[63:0] : {64{ag_src_operand_mux}} & idu_iu_ex1_src2[63:0];

//-------------- Adder -----------------
assign ag_adder_res[63:0]     = ag_adder_rs2[63:0] + ag_adder_rs1[63:0];

//---------- Rename for output ---------
assign ag_bju_pc[63:0]    = ag_adder_res[63:0];



// &ModuleEnd; @59
endmodule
module BUFGCE(
  I,
  CE,
  O
);

input  I;
input  CE ;
output O;

reg    clk_en_af_latch;
always @(I or CE)
begin
  if(!I)
    clk_en_af_latch <= CE;
end

reg clk_en ;
always @ (clk_en_af_latch )
begin
    clk_en <= clk_en_af_latch;
end
assign O = I && clk_en ;
   
endmodule
module sync_level2level(
  clk,
  rst_b,
  sync_in,
  sync_out
);

parameter SIGNAL_WIDTH = 1;
parameter FLOP_NUM     = 3;

input          clk;
input          rst_b;
input   [SIGNAL_WIDTH-1:0]   sync_in;
output  [SIGNAL_WIDTH-1:0]   sync_out;

reg     [SIGNAL_WIDTH-1:0]  sync_ff[FLOP_NUM-1:0];

wire           clk;
wire           rst_b;
wire    [SIGNAL_WIDTH-1:0]   sync_in;
wire    [SIGNAL_WIDTH-1:0]   sync_out;


genvar i;

always @ (posedge clk or negedge rst_b)
begin
  if (!rst_b)
    sync_ff[0][SIGNAL_WIDTH-1:0] <= {SIGNAL_WIDTH{1'b0}};
  else
    sync_ff[0][SIGNAL_WIDTH-1:0] <= sync_in[SIGNAL_WIDTH-1:0];
end


generate
for (i = 1; i < FLOP_NUM; i = i+1)
begin: FLOP_GEN
  always @ (posedge clk or negedge rst_b)
  begin
    if (!rst_b)
      sync_ff[i][SIGNAL_WIDTH-1:0] <= {SIGNAL_WIDTH{1'b0}};
    else
      sync_ff[i][SIGNAL_WIDTH-1:0] <= sync_ff[i-1][SIGNAL_WIDTH-1:0];
  end
end
endgenerate

assign sync_out[SIGNAL_WIDTH-1:0] = sync_ff[FLOP_NUM-1][SIGNAL_WIDTH-1:0];


endmodule
module aq_fadd_shift_sub_single(
  data_in,
  data_out,
  shift_cnt
);

// &Ports; @23
input   [27:0]  data_in;       
input   [4 :0]  shift_cnt;     
output  [27:0]  data_out;      

// &Regs; @24
reg     [27:0]  data_shift;    

// &Wires; @25
wire    [4 :0]  cnt;           
wire    [27:0]  data_in;       
wire    [27:0]  data_out;      
wire    [27:0]  data_shift_pre; 
wire    [4 :0]  shift_cnt;     


assign data_shift_pre[27:0] = data_in[27:0];
assign data_out[27:0]       = data_shift[27:0];
assign cnt[4:0]             = shift_cnt[4:0];


// &CombBeg; @32
always @( cnt[4:0]
       or data_shift_pre[27:0])
begin
case(cnt[4:0])
  5'd0 : data_shift[27:0]   = data_shift_pre[27:0];
  5'd1 : data_shift[27:0]   = {data_shift_pre[26:0], 1'b0};
  5'd2 : data_shift[27:0]   = {data_shift_pre[25:0], 2'b0};
  5'd3 : data_shift[27:0]   = {data_shift_pre[24:0], 3'b0};
  5'd4 : data_shift[27:0]   = {data_shift_pre[23:0], 4'b0};
  5'd5 : data_shift[27:0]   = {data_shift_pre[22:0], 5'b0};
  5'd6 : data_shift[27:0]   = {data_shift_pre[21:0], 6'b0};
  5'd7 : data_shift[27:0]   = {data_shift_pre[20:0], 7'b0};
  5'd8 : data_shift[27:0]   = {data_shift_pre[19:0], 8'b0};
  5'd9 : data_shift[27:0]   = {data_shift_pre[18:0], 9'b0};
  5'd10 : data_shift[27:0]  = {data_shift_pre[17:0],10'b0};
  5'd11 : data_shift[27:0]  = {data_shift_pre[16:0],11'b0};
  5'd12 : data_shift[27:0]  = {data_shift_pre[15:0],12'b0};
  5'd13 : data_shift[27:0]  = {data_shift_pre[14:0],13'b0};
  5'd14 : data_shift[27:0]  = {data_shift_pre[13:0],14'b0};
  5'd15 : data_shift[27:0]  = {data_shift_pre[12:0],15'b0};
  5'd16 : data_shift[27:0]  = {data_shift_pre[11:0],16'b0};
  5'd17 : data_shift[27:0]  = {data_shift_pre[10:0],17'b0};
  5'd18 : data_shift[27:0]  = {data_shift_pre[9:0],18'b0};
  5'd19 : data_shift[27:0]  = {data_shift_pre[8:0],19'b0};
  5'd20 : data_shift[27:0]  = {data_shift_pre[7:0],20'b0};
  5'd21 : data_shift[27:0]  = {data_shift_pre[6:0],21'b0};
  5'd22 : data_shift[27:0]  = {data_shift_pre[5:0],22'b0};
  5'd23 : data_shift[27:0]  = {data_shift_pre[4:0],23'b0};
  5'd24 : data_shift[27:0]  = {data_shift_pre[3:0],24'b0};
  5'd25 : data_shift[27:0]  = {data_shift_pre[2:0],25'b0};
  5'd26 : data_shift[27:0]  = {data_shift_pre[1:0],26'b0};
  5'd27 : data_shift[27:0]  = {data_shift_pre[0],27'b0};
  default: data_shift[27:0] = 28'b0;
endcase
// &CombEnd; @64
end





// &ModuleEnd; @70
endmodule
module aq_fcnvt_xtoh_sh(
  xtoh_sh_cnt,
  xtoh_sh_f_v,
  xtoh_sh_f_x,
  xtoh_sh_src
);

// &Ports; @17
input   [11:0]  xtoh_sh_cnt; 
input   [51:0]  xtoh_sh_src; 
output  [10:0]  xtoh_sh_f_v; 
output  [53:0]  xtoh_sh_f_x; 

// &Regs; @18
reg     [10:0]  xtoh_sh_f_v; 
reg     [53:0]  xtoh_sh_f_x; 

// &Wires; @19
wire    [11:0]  xtoh_sh_cnt; 
wire    [51:0]  xtoh_sh_src; 



// &CombBeg; @22
always @( xtoh_sh_src[51:0]
       or xtoh_sh_cnt[11:0])
begin
case(xtoh_sh_cnt[11:0])
  12'hff1: begin //-15
  xtoh_sh_f_v[10:0] = {2'b1,xtoh_sh_src[51:43]};
  xtoh_sh_f_x[53:0] = {xtoh_sh_src[42:0],11'b0};
  end
  12'hff0: begin //-16
  xtoh_sh_f_v[10:0] = {3'b1,xtoh_sh_src[51:44]};
  xtoh_sh_f_x[53:0] = {xtoh_sh_src[43:0],10'b0};
  end
  12'hfef: begin //-17
  xtoh_sh_f_v[10:0] = {4'b1,xtoh_sh_src[51:45]};
  xtoh_sh_f_x[53:0] = {xtoh_sh_src[44:0],9'b0};
  end
  12'hfee: begin //-18
  xtoh_sh_f_v[10:0] = {5'b1,xtoh_sh_src[51:46]};
  xtoh_sh_f_x[53:0] = {xtoh_sh_src[45:0],8'b0};
  end
  12'hfed: begin //-19
  xtoh_sh_f_v[10:0] = {6'b1,xtoh_sh_src[51:47]};
  xtoh_sh_f_x[53:0] = {xtoh_sh_src[46:0],7'b0};
  end
  12'hfec: begin //-20
  xtoh_sh_f_v[10:0] = {7'b1,xtoh_sh_src[51:48]};
  xtoh_sh_f_x[53:0] = {xtoh_sh_src[47:0],6'b0};
  end
  12'hfeb: begin //-21
  xtoh_sh_f_v[10:0] = {8'b1,xtoh_sh_src[51:49]};
  xtoh_sh_f_x[53:0] = {xtoh_sh_src[48:0],5'b0};
  end
  12'hfea: begin //-22
  xtoh_sh_f_v[10:0] = {9'b1,xtoh_sh_src[51:50]};
  xtoh_sh_f_x[53:0] = {xtoh_sh_src[49:0],4'b0};
  end
  12'hfe9: begin //-135
  xtoh_sh_f_v[10:0] = {10'b1,xtoh_sh_src[51]};
  xtoh_sh_f_x[53:0] = {xtoh_sh_src[50:0],3'b0};
  end
  12'hfe8: begin //-136
  xtoh_sh_f_v[10:0] = {11'b1};
  xtoh_sh_f_x[53:0] = {xtoh_sh_src[51:0],2'b0};
  end
  12'hfe7: begin //-137
  xtoh_sh_f_v[10:0] = 11'b0;
  xtoh_sh_f_x[53:0] = {1'b1,xtoh_sh_src[51:0],1'b0};
  end
  12'hfe6: begin //-138
  xtoh_sh_f_v[10:0] = 11'b0;
  xtoh_sh_f_x[53:0] = {2'b1,xtoh_sh_src[51:0]};
  end
  default: begin
  xtoh_sh_f_v[10:0] = 11'b0;
  xtoh_sh_f_x[53:0] = {3'b1,51'b0};
  end
endcase
// &CombEnd; @77
end


// &ModuleEnd; @80
endmodule
module aq_ifu_ras_entry(
  cp0_ifu_icg_en,
  cp0_yy_clk_en,
  cpurst_b,
  forever_cpuclk,
  pad_yy_icg_scan_en,
  ras_entry_pc,
  ras_entry_upd,
  ras_upd_pc
);

// &Ports; @24
input           cp0_ifu_icg_en;    
input           cp0_yy_clk_en;     
input           cpurst_b;          
input           forever_cpuclk;    
input           pad_yy_icg_scan_en; 
input           ras_entry_upd;     
input   [23:0]  ras_upd_pc;        
output  [23:0]  ras_entry_pc;      

// &Regs; @25
reg     [23:0]  entry_pc;          

// &Wires; @26
wire            cp0_ifu_icg_en;    
wire            cp0_yy_clk_en;     
wire            cpurst_b;          
wire            entry_clk;         
wire            entry_clk_en;      
wire            forever_cpuclk;    
wire            pad_yy_icg_scan_en; 
wire    [23:0]  ras_entry_pc;      
wire            ras_entry_upd;     
wire    [23:0]  ras_upd_pc;        


//==========================================================
// IFU Ras Entry Module
// 1. Instance ICG Cell
// 2. Entry PC
//==========================================================

//------------------------------------------------
// 1. Instance ICG Cell
//------------------------------------------------
assign entry_clk_en = ras_entry_upd;
// &Instance("gated_clk_cell", "x_ras_entry_icg_cell"); @38
gated_clk_cell  x_ras_entry_icg_cell (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (entry_clk         ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (entry_clk_en      ),
  .module_en          (cp0_ifu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);

// &Connect(.clk_in      (forever_cpuclk), @39
//          .external_en (1'b0), @40
//          .global_en   (cp0_yy_clk_en), @41
//          .module_en ( cp0_ifu_icg_en), @42
//          .local_en    (entry_clk_en), @43
//          .clk_out     (entry_clk) @44
//         ); @45

//------------------------------------------------
// 2. Entry PC
//------------------------------------------------
always @(posedge entry_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
  begin
    entry_pc[23:0] <= 24'b0;
  end
  else if(ras_entry_upd)
  begin
    entry_pc[23:0] <= ras_upd_pc[23:0];
  end
  else
  begin
    entry_pc[23:0] <= entry_pc[23:0];
  end
end


//==========================================================
// Rename for Output
//==========================================================
assign ras_entry_pc[23:0] = entry_pc[23:0];


// &ModuleEnd; @73
endmodule
module aq_cpuio_top(
  biu_cp0_coreid,
  biu_cp0_me_int,
  biu_cp0_ms_int,
  biu_cp0_mt_int,
  biu_cp0_rvba,
  biu_cp0_se_int,
  biu_cp0_ss_int,
  biu_cp0_st_int,
  biu_hpcp_time,
  clint_cpuio_time,
  cp0_biu_lpmd_b,
  cpuio_sysio_lpmd_b,
  pad_biu_coreid,
  sysio_cpuio_me_int,
  sysio_cpuio_ms_int,
  sysio_cpuio_mt_int,
  sysio_cpuio_se_int,
  sysio_cpuio_ss_int,
  sysio_cpuio_st_int,
  sysio_xx_rvba
);

// &Ports; @20
input   [63:0]  clint_cpuio_time;  
input   [1 :0]  cp0_biu_lpmd_b;    
input   [2 :0]  pad_biu_coreid;    
input           sysio_cpuio_me_int; 
input           sysio_cpuio_ms_int; 
input           sysio_cpuio_mt_int; 
input           sysio_cpuio_se_int; 
input           sysio_cpuio_ss_int; 
input           sysio_cpuio_st_int; 
input   [39:0]  sysio_xx_rvba;     
output  [2 :0]  biu_cp0_coreid;    
output          biu_cp0_me_int;    
output          biu_cp0_ms_int;    
output          biu_cp0_mt_int;    
output  [39:0]  biu_cp0_rvba;      
output          biu_cp0_se_int;    
output          biu_cp0_ss_int;    
output          biu_cp0_st_int;    
output  [63:0]  biu_hpcp_time;     
output  [1 :0]  cpuio_sysio_lpmd_b; 

// &Regs; @21

// &Wires; @22
wire    [2 :0]  biu_cp0_coreid;    
wire            biu_cp0_me_int;    
wire            biu_cp0_ms_int;    
wire            biu_cp0_mt_int;    
wire    [39:0]  biu_cp0_rvba;      
wire            biu_cp0_se_int;    
wire            biu_cp0_ss_int;    
wire            biu_cp0_st_int;    
wire    [63:0]  biu_hpcp_time;     
wire    [63:0]  clint_cpuio_time;  
wire    [1 :0]  cp0_biu_lpmd_b;    
wire    [1 :0]  cpuio_sysio_lpmd_b; 
wire    [2 :0]  pad_biu_coreid;    
wire            sysio_cpuio_me_int; 
wire            sysio_cpuio_ms_int; 
wire            sysio_cpuio_mt_int; 
wire            sysio_cpuio_se_int; 
wire            sysio_cpuio_ss_int; 
wire            sysio_cpuio_st_int; 
wire    [39:0]  sysio_xx_rvba;     


assign biu_cp0_coreid[2:0] = pad_biu_coreid[2:0];
assign biu_cp0_me_int      = sysio_cpuio_me_int;
assign biu_cp0_ms_int      = sysio_cpuio_ms_int;  
assign biu_cp0_mt_int      = sysio_cpuio_mt_int;
assign biu_cp0_se_int      = sysio_cpuio_se_int;
assign biu_cp0_ss_int      = sysio_cpuio_ss_int;
assign biu_cp0_st_int      = sysio_cpuio_st_int;
assign biu_hpcp_time[63:0] = clint_cpuio_time[63:0];
assign biu_cp0_rvba[39:0]  = sysio_xx_rvba[39:0];
assign cpuio_sysio_lpmd_b[1:0] = cp0_biu_lpmd_b[1:0];
// &ModuleEnd; @37
endmodule
module aq_vidu_vid_gpr_reg_fp(
  cp0_idu_icg_en,
  cp0_yy_clk_en,
  forever_cpuclk,
  pad_yy_icg_scan_en,
  read_data_y,
  vpu_vidu_fp_wb_data,
  wb_vld_x
);

// &Ports; @24
input           cp0_idu_icg_en;     
input           cp0_yy_clk_en;      
input           forever_cpuclk;     
input           pad_yy_icg_scan_en; 
input   [63:0]  vpu_vidu_fp_wb_data; 
input           wb_vld_x;           
output  [63:0]  read_data_y;        

// &Regs; @25
reg     [63:0]  reg_dout;           

// &Wires; @26
wire            cp0_idu_icg_en;     
wire            cp0_yy_clk_en;      
wire            forever_cpuclk;     
wire            pad_yy_icg_scan_en; 
wire    [63:0]  read_data_y;        
wire            reg_clk;            
wire            reg_clk_en;         
wire    [63:0]  vpu_vidu_fp_wb_data; 
wire            wb_vld_x;           
wire    [63:0]  write_data;         
wire            write_en;           



//==========================================================
//                 Instance of Gated Cell  
//==========================================================
assign reg_clk_en = write_en;
// &Instance("gated_clk_cell", "x_reg_gated_clk"); @33
gated_clk_cell  x_reg_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (reg_clk           ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (reg_clk_en        ),
  .module_en          (cp0_idu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);

// &Connect(.clk_in      (forever_cpuclk), @34
//          .external_en (1'b0), @35
//          .global_en   (cp0_yy_clk_en), @36
//          .module_en   (cp0_idu_icg_en), @37
//          .local_en    (reg_clk_en), @38
//          .clk_out     (reg_clk)); @39

//==========================================================
//                     Write Port
//==========================================================
assign write_en = wb_vld_x;

assign write_data[63:0] = wb_vld_x ? vpu_vidu_fp_wb_data[63:0] : reg_dout[63:0];

//==========================================================
//                     Preg Register
//==========================================================
always @(posedge reg_clk)
begin
    reg_dout[63:0] <= write_data[63:0];
end

assign read_data_y[63:0] = write_data[63:0];

// &ModuleEnd; @58
endmodule
module aq_idu_id_gpr_gated_reg(
  cp0_idu_icg_en,
  cp0_yy_clk_en,
  forever_cpuclk,
  pad_yy_icg_scan_en,
  read_data_y,
  rtu_idu_wb0_data,
  rtu_idu_wb1_data,
  wb0_vld_x,
  wb1_vld_x
);

// &Ports; @24
input           cp0_idu_icg_en;    
input           cp0_yy_clk_en;     
input           forever_cpuclk;    
input           pad_yy_icg_scan_en; 
input   [63:0]  rtu_idu_wb0_data;  
input   [63:0]  rtu_idu_wb1_data;  
input           wb0_vld_x;         
input           wb1_vld_x;         
output  [63:0]  read_data_y;       

// &Regs; @25
reg     [63:0]  reg_dout;          
reg     [63:0]  write_data;        

// &Wires; @26
wire            cp0_idu_icg_en;    
wire            cp0_yy_clk_en;     
wire            forever_cpuclk;    
wire            pad_yy_icg_scan_en; 
wire    [63:0]  read_data_y;       
wire            reg_clk;           
wire            reg_clk_en;        
wire    [63:0]  rtu_idu_wb0_data;  
wire    [63:0]  rtu_idu_wb1_data;  
wire            wb0_vld_x;         
wire            wb1_vld_x;         
wire            write_en;          



//==========================================================
//                 Instance of Gated Cell  
//==========================================================
assign reg_clk_en = write_en;
// &Instance("gated_clk_cell", "x_reg_gated_clk"); @33
gated_clk_cell  x_reg_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (reg_clk           ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (reg_clk_en        ),
  .module_en          (cp0_idu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);

// &Connect(.clk_in      (forever_cpuclk), @34
//          .external_en (1'b0), @35
//          .global_en   (cp0_yy_clk_en), @36
//          .module_en   (cp0_idu_icg_en), @37
//          .local_en    (reg_clk_en), @38
//          .clk_out     (reg_clk)); @39

//==========================================================
//                     Write Port
//==========================================================
assign write_en = wb0_vld_x || wb1_vld_x;
// &CombBeg; @45
always @( rtu_idu_wb1_data[63:0]
       or rtu_idu_wb0_data[63:0]
       or wb1_vld_x
       or wb0_vld_x
       or reg_dout[63:0])
begin
  case ({wb1_vld_x,wb0_vld_x})
    2'b01  : write_data[63:0] = rtu_idu_wb0_data[63:0];
    2'b10  : write_data[63:0] = rtu_idu_wb1_data[63:0];
    default: write_data[63:0] = reg_dout[63:0];
  endcase
// &CombEnd; @51
end

//==========================================================
//                     Preg Register
//==========================================================
always @(posedge reg_clk)
begin
    reg_dout[63:0] <= write_data[63:0];
end

assign read_data_y[63:0] = write_data[63:0];

// &ModuleEnd; @63
endmodule
module aq_idu_expand_32(
  x_num,
  x_num_expand
);

// &Ports; @25
input   [4 :0]  x_num;       
output  [31:0]  x_num_expand; 

// &Regs; @26

// &Wires; @27
wire    [4 :0]  x_num;       
wire    [31:0]  x_num_expand; 


//==========================================================
//       expand 5 bits number to 32 bits one-hot number
//==========================================================
assign x_num_expand[0]  = (x_num[4:0] == 5'd0);
assign x_num_expand[1]  = (x_num[4:0] == 5'd1);
assign x_num_expand[2]  = (x_num[4:0] == 5'd2);
assign x_num_expand[3]  = (x_num[4:0] == 5'd3);
assign x_num_expand[4]  = (x_num[4:0] == 5'd4);
assign x_num_expand[5]  = (x_num[4:0] == 5'd5);
assign x_num_expand[6]  = (x_num[4:0] == 5'd6);
assign x_num_expand[7]  = (x_num[4:0] == 5'd7);
assign x_num_expand[8]  = (x_num[4:0] == 5'd8);
assign x_num_expand[9]  = (x_num[4:0] == 5'd9);
assign x_num_expand[10] = (x_num[4:0] == 5'd10);
assign x_num_expand[11] = (x_num[4:0] == 5'd11);
assign x_num_expand[12] = (x_num[4:0] == 5'd12);
assign x_num_expand[13] = (x_num[4:0] == 5'd13);
assign x_num_expand[14] = (x_num[4:0] == 5'd14);
assign x_num_expand[15] = (x_num[4:0] == 5'd15);
assign x_num_expand[16] = (x_num[4:0] == 5'd16);
assign x_num_expand[17] = (x_num[4:0] == 5'd17);
assign x_num_expand[18] = (x_num[4:0] == 5'd18);
assign x_num_expand[19] = (x_num[4:0] == 5'd19);
assign x_num_expand[20] = (x_num[4:0] == 5'd20);
assign x_num_expand[21] = (x_num[4:0] == 5'd21);
assign x_num_expand[22] = (x_num[4:0] == 5'd22);
assign x_num_expand[23] = (x_num[4:0] == 5'd23);
assign x_num_expand[24] = (x_num[4:0] == 5'd24);
assign x_num_expand[25] = (x_num[4:0] == 5'd25);
assign x_num_expand[26] = (x_num[4:0] == 5'd26);
assign x_num_expand[27] = (x_num[4:0] == 5'd27);
assign x_num_expand[28] = (x_num[4:0] == 5'd28);
assign x_num_expand[29] = (x_num[4:0] == 5'd29);
assign x_num_expand[30] = (x_num[4:0] == 5'd30);
assign x_num_expand[31] = (x_num[4:0] == 5'd31);

// &ModuleEnd; @65
endmodule
module aq_fdsu_right_shift(
  frac_num_in,
  frac_shift_cnt,
  frac_shift_num
);

// &Ports; @23
input   [15:0]  frac_num_in;   
input   [2 :0]  frac_shift_cnt; 
output  [15:0]  frac_shift_num; 

// &Regs; @24
reg     [15:0]  frac_shift_num; 

// &Wires; @25
wire    [15:0]  frac_num_in;   
wire    [2 :0]  frac_shift_cnt; 

// &Force("bus","frac_num_in",15,0); @26
// &CombBeg; @27
always @( frac_num_in[15:1]
       or frac_shift_cnt[2:0])
begin
casez(frac_shift_cnt[2:0])
  3'b111:  frac_shift_num[15:0] = {1'b0,frac_num_in[15:1]};
  3'b110:  frac_shift_num[15:0] = {2'b0,frac_num_in[15:2]};
  3'b101:  frac_shift_num[15:0] = {3'b0,frac_num_in[15:3]};
  3'b100:  frac_shift_num[15:0] = {4'b0,frac_num_in[15:4]};
  3'b011:  frac_shift_num[15:0] = {5'b0,frac_num_in[15:5]};
  3'b010:  frac_shift_num[15:0] = {6'b0,frac_num_in[15:6]};
  3'b001:  frac_shift_num[15:0] = {7'b0,frac_num_in[15:7]};
  3'b000:  frac_shift_num[15:0] = {8'b0,frac_num_in[15:8]};
  default: frac_shift_num[15:0] = {16{1'b0}};
endcase
// &CombEnd; @39
end

// &ModuleEnd; @41
endmodule
module aq_mp_rst_top(
  ciu_rst_b,
  clkgen_rst_b,
  core0_rst_b,
  forever_cpuclk,
  pad_cpu_rst_b,
  pad_yy_dft_clk_rst_b,
  pad_yy_mbist_mode,
  pad_yy_scan_mode,
  pad_yy_scan_rst_b,
  sync_sys_apb_rst_b,
  sys_apb_clk,
  sys_apb_rst_b
);

// &Ports; @23
input        forever_cpuclk;      
input        pad_cpu_rst_b;       
input        pad_yy_dft_clk_rst_b; 
input        pad_yy_mbist_mode;   
input        pad_yy_scan_mode;    
input        pad_yy_scan_rst_b;   
input        sys_apb_clk;         
input        sys_apb_rst_b;       
output       ciu_rst_b;           
output       clkgen_rst_b;        
output       core0_rst_b;         
output       sync_sys_apb_rst_b;  

// &Regs; @24
reg          ciu_rst_ff_1st;      
reg          ciu_rst_ff_2nd;      
reg          ciu_rst_ff_3rd;      
reg          sys_apb_rst_ff_1st;  

// &Wires; @25
wire         async_apb_rst_b;     
wire         async_ciu_rst_b;     
wire         ciu_rst_b;           
wire         clkgen_rst_b;        
wire         core0_rst_b;         
wire         forever_cpuclk;      
wire         pad_cpu_rst_b;       
wire         pad_yy_dft_clk_rst_b; 
wire         pad_yy_mbist_mode;   
wire         pad_yy_scan_mode;    
wire         pad_yy_scan_rst_b;   
wire         sync_sys_apb_rst_b;  
wire         sys_apb_clk;         
wire         sys_apb_rst_b;       


//assign ciu_rre[3:0] = 4'b1;
////cpu reset 
//assign cpu0_rst_b = pad_core0_rst_b & ciu_rre[0] | pad_yy_mbist_mode;
//
//always @(posedge forever_cpuclk or negedge cpu0_rst_b)
//begin
//  if(!cpu0_rst_b)
//  begin
//    cpu0_rst_ff_1st <= 1'b0;
//    cpu0_rst_ff_2nd <= 1'b0;
//    cpu0_rst_ff_3rd <= 1'b0;
//  end
//  else
//  begin
//    cpu0_rst_ff_1st <= 1'b1;
//    cpu0_rst_ff_2nd <= cpu0_rst_ff_1st;
//    cpu0_rst_ff_3rd <= cpu0_rst_ff_2nd;
//  end
//end
//
//assign core0_rst_b =  pad_yy_scan_mode ? pad_yy_scan_rst_b : cpu0_rst_ff_3rd;
//
//
//
//

assign async_ciu_rst_b = pad_cpu_rst_b & !pad_yy_mbist_mode;

always @(posedge forever_cpuclk or negedge async_ciu_rst_b)
begin
  if (!async_ciu_rst_b)
  begin
    ciu_rst_ff_1st <= 1'b0;
    ciu_rst_ff_2nd <= 1'b0;
    ciu_rst_ff_3rd <= 1'b0;
  end
  else
  begin
    ciu_rst_ff_1st <= 1'b1;
    ciu_rst_ff_2nd <= ciu_rst_ff_1st;
    ciu_rst_ff_3rd <= ciu_rst_ff_2nd;
  end
end

assign async_apb_rst_b = sys_apb_rst_b & !pad_yy_mbist_mode;

always @(posedge sys_apb_clk or negedge async_apb_rst_b)
begin
  if (!async_apb_rst_b)
    sys_apb_rst_ff_1st <= 1'b0;
  else
    sys_apb_rst_ff_1st <= 1'b1;
end

// &Force("output","ciu_rst_b"); @149
assign ciu_rst_b   = pad_yy_scan_mode ? pad_yy_scan_rst_b : ciu_rst_ff_3rd;
assign core0_rst_b = ciu_rst_b;

assign sync_sys_apb_rst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : sys_apb_rst_ff_1st;

assign clkgen_rst_b = pad_yy_scan_mode ? pad_yy_dft_clk_rst_b : ciu_rst_ff_3rd;

//assign jtg_trst_b_bf_flop = async_ciu_rst_b & pad_had_jtg_trst_b ;
//assign trst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : jtg_trst_b_bf_flop;

// &ModuleEnd; @160
endmodule