cyanic-selkie/wikianc huggingface dataset:
Riverlea
Dit lê nagenoeg tussen Longdale en Hoofrifweg in die noorde, Nasrecweg in die ooste (hoewel enkele straatblokke ook oos van die pad geleë is), die N17 in die suide en die N1 in die weste. Die grootste gedeelte van Riverlea lê noord van die hoofspoorlyn en ’n kleiner gedeelte suid daarvan.
Die voorstad is op die plaas Langlaagte aangelê en in 1967 geproklameer, toe dit 'n sogenaamde bruin groepsgebied was. Die naam is afgelei van ’n stroompie wat op die suidelike grens van die voorstad vloei. "Lea" kom uit Ou Engels en het eers "boomryke gebied" beteken, maar later "’n oopte in die woud" en eindelik net "oop gebied".
Demografie
Riverlea het volgens die sensus van 2001 destyds 14 873 inwoners gehad, van wie 61,7% (9 171) bruin was en 36,5% (5 426) swart. Afrikaans was die huistaal van 35,3% van die inwoners en Engels 29,4% s’n. Tien jaar later het die bevolking toegeneem tot 16 226, van wie 67,3% (10 917) bruin was en 29,6% (4 794) swart, maar die grense is anders getrek sodat die plakkerskamp suid van Longdale vir die 2011-sensus se doeleindes by dié nywerheidsgebied ingesluit is, en nie by Riverlea nie. Die persentasie Afrikaanssprekendes sowel as Engelssprekendes het toegeneem, onderskeidelik tot 37,7% en 36,4%.
GVVV
GVVV is 'n amateur sokkerspan in die Nederlandse dorp Veenendaal, wat in die Saterdag-Topklasse speel. Die klub verwerf nasionale bekendheid deur in 2012 die kwarteindstryd van die KNVB-Beker te bereik.
Erica numidica
Erica numidica is 'n plant wat tot die genus Erica behoort en is inheems aan Algerië.
Priapos
Priapos of Priapus (Grieks: Πρίαπος) was in die Griekse mitologie die kind van Dionysos en Afrodite. Hy was ’n mindere god van vrugbaarheid en die beskermer van vrugteplante, vee, tuine en manlike geslagsdele. Hy word kenmerkend uitgebeeld met ’n belaglike groot, permanente ereksie en sy naam het gelei tot die mediese term priapisme.
Verhouding met ander gode
Priapos word, afhangend van die bron, beskryf as die seun van Afrodite en Dionysos, of van Dioysos en Chione, dalk die pa of seun van Hermes, of die seun van Zeus of Pan Volgens die legendes het Hera hom vervloek met impotensie, lelikheid en vuil gedagtes terwyl Afrodite hom verwag het omdat die held Paris gemeen het Afrodite is mooier as sy (Hera). Die ander gode het geweier dat hy saam met hulle op Berg Olimpus woon en het hom afgegooi aarde toe. Hy is eindelik deur herders gevind wat hom grootgemaak het. Priapos het by Pan en die saters aangesluit as ’n gees van vrugbaarheid en groei, maar hy was voortdurend gefrustreer deur sy impotensie. Volgens Ovidius het hy probeer om die nimf Lotis te verkrag, maar ’n donkie se gebalk het veroorsaak dat hy sy ereksie verloor en Lotus wakker word. Hy het die nimf agtervolg totdat die gode haar jammer gekry en in ’n lotusstruik verander het. Priapos her donkies daarna gehaat en wou hê hulle moes tot sy eer vernietig word.
Sy permanente ereksie en groot penis was die embleem van sy wellustige natuur.
Toyota Belta
Die Toyota Belta, ook bekend as Toyota Yaris in Noord-Amerika, Australië en Suid-Afrika, is 'n gesinsmotor wat deur die Japannese motorvervaardiger Toyota vervaardig word.
Sentrale verwerkingseenheid
'n Sentrale verwerkingseenheid (SVE), of hoofverwerkingseenheid is die komponent in 'n digitale rekenaars wat instruksies en data in rekenaarprogramme vervat vertaal en verwerk SVE's verleen die fundamentele eienskap van programeerbaarheid aan rekenaars saam met primêre stoorgeheue en toevoer/afvoer fasiliteite. 'n SVE wat vervaardig word deur van geïntegreerde stroombane gebruik te maak staan ook as 'n mikroverwerker bekend. Sedert die middel sewentigs het enkelskyf mikroverwerkers byna alle ander soorte SVE's vervang.
Die vorm, ontwerp en implementering van SVE's het dramaties verander sedert die vroegste voorbeelde, maar hul fundamentele bedryf is basies nog dieselfde.
Vroeë SVE's was pasgemaakte dele van 'n groter en gewoonlik unieke rekenaar. Pasgemaakte SVE's word deesdae min gebruik en word gestandaardiseerde veeldoelige verwerkers eerder gebruik. Hierdie neiging tot standardisasie het reeds begin in die tydperk van transistor hoofraam- en minirekenaars en het vinnig versnel vandat geïntegreerde stroombane bekend gestel is.
Geskiedenis
Die eerste rekenaars soos ENIAC moes fisies herbedraad word om verskillende take uit te voer. Hierdie masjiene is dikwels na verwys as vaste-program rekenaars, aangesien hulle fisies heropgestel moes word om 'n ander program te kon uitvoer. Sedertdien word die begrip SVE gebruik om te verwys na 'n toestel vir die uitvoer van programmatuur. Die vroegste toestelle wat met reg SVE's genoem kon word, kon eers aangetref word in die eerste rekenaars met gestoorde programme.
Die idee van 'n gestoordeprogramrekenaar was reeds teenwoordig in die ENIAC se ontwerp, maar is aanvanklik uitgelaat sodat die masjien vroeër klaargemaak kon word. Op 30 Junie 1945 selfs voordat ENIAC voltooi is, het John von Neumann 'n konsepverslag versprei oor die EDVAC. Daarin het hy die ontwerp van 'n gestoordeprogramrekenaar se ontwerp beskryf wat toe uiteindelik in Augustus van 1949 voltooi is. EDVAC is ontwerp om 'n verskeidenheid soorte instruksies (of verwerkinge) uit te voer. Hierdie instruksies kon gekombineer word om nuttige programme te vorm. 'n Buitengewone eienskap van die ontwerp was dat die programme wat vir die EDVAC geskryf is, in hoēspoed-rekenaargeheue gestoor is eerder as om die bedrading van die rekenaar aan te pas. Hierdie eienskap het die ernstige beperking van die ENIAC oorkom, waarvolgens baie inspanning geverg is om die rekenaar van voor af op te stel sodat dit ander take kon uitvoer. Met Von Neuman se ontwerp, kon die programmatuur wat EDVAC uitgevoer het, eenvoudig verander word deur die inhoud van die rekenaargeheue aan te pas.
SVE's is digitale toestelle wat slegs met diskrete toestande werk en vereis daarom skakelelemente om tussen hierdie toestande te kan onderskei. Voor die kommersiële aanvaarding van die transistor is elektriese wisselaars en vakuumbuise algemeen gebruik as skakelelemente. Al het hierdie elemente besliste voordele bo vroeëre suiwer meganiese ontwerpe gehad was hulle om verskeie redes onbetroubaar en was die vroeëre elektroniese rekenaars oor die algemeen minder betroubaar as elektromeganiese rekenaars al was hulle baie vinniger. Vakuumbuisrekenaars soos EDVAC was geneig om net ongeveer agt uur lank te werk voor hulle gefaal het en weer moes herstel word, terwyl die elektromeganiese masjiene soos die Harvard Mark I baie selde gefaal het. Uiteindelik het vakuumbuisgebaseerde rekenaars egter die oorhand gekry omdat die spoedvoordele die betroubaarheidsprobleme ver oorskry het. Die klokfrekwensie van hierdie vroeë sinkrone SVE's was egter baie laag in vergelyking met vandag se moderne rekenaars. Klokseinfrekwensies wat gewissel het tussen 100 kHz tot 4 MHz was algemeen op dié stadium en is hoofsaaklik beperk deur die skakelspoed van die komponente waarmee hulle gebou is.
Diskrete transistor en Geïntegreerde stroombaan SVE's
Die kompleksiteit van SVE-ontwerpe het toegeneem soos wat verskeie nuwe tegnologieë dit moontlik gemaak het om kleiner en meer betroubare elektroniese toestelle te bou. Die eerste sodanige verbetering het plaasgevind met die aankoms van die transistor. Transistor-SVE's het dit moontlik gemaak om betroubare SVE's op een of verskeie gedrukte stroombaanborde met diskrete komponente daarop te bou. Die volgende groot ontwikkeling was die geïntegreerde stroombaan wat dit moontlik gemaak het om 'n groot aantal transistors op 'n enkele halfgeleiergebaseerde skyf te vervaardig. Eers was dit slegs moontlik om baie basiese nie-gespesialiseerde digitale stroombane soos NOF-hekke te vervaardig.
SVE's wat uit sulke boublokke saamgestel is, word kleinskaalse integrasietoestelle genoem. Kleinskaalse geïntegreerde stroombane soos dié wat in die Apollo begeleidingsrekenaars gebruik is, het bestaan uit tiene transistors. Om 'n volle SVE uit kleinskaal geïntegreerde stroombane te bou het steeds duisende indiwiduele skyfies geverg maar was nogtans 'n groot sprong bo die transistorgebaseerde SVE's in terme van die kragverbruik en spasieverbruik. Tegnologiese vordering in die vervaardiging van geïntegreerde stroombane het daartoe gelei dat honderde en later duisende transistors (Mediumskaal- en grootskaalse integrasie) op 'n enkele silikonskyf geplaas kon word en meegebring dat die aantal nodige geïntegreerde stroombane (GS) om 'n SVE te bou, verminder kon word.
In 1964 het IBM hulle System/360 rekenaarargitektuur bekendgestel wat in 'n reeks rekenaars gebruik is wat dieselfde programme met verskillende snelheid en verrigting kon uitvoer. Dit was 'n betekenisvolle stap op daardie tydstip toe die meeste elektroniese rekenaars nie met mekaar versoenbaar was nie, selfs al is hulle deur dieselfde vervaardiger gebou. Om hierdie verbetering moontlik te maak, het IBM die konsep van 'n mikroprogram gebruik, wat steeds in moderne SVE's gebruik word. Die System/360 argitektuur was so gewild dat dit die hoofraamrekenaarmark vir die daaropvolgende dekades gedomineer het en 'n nalatenskap daargelaat het wat voortgesit is in soortgelyke moderne rekenaars soos die IBM zSeries.
In daardie selfde jaar (1964) het Digital Equipment Corporation (DEC) 'n ander invloedryke rekenaar bekendgestel wat gemik was op die wetenskaplike en navorsingsmarkte, naamlik die PDP-8. DEC sou later die baie gewilde PDP-11-reeks bekendstel wat aanvanklik gebou is met behulp van Kleinskaalintegrasie Geïntegreerde stroombane maar toe later met Grootskaalse integrasie stroombane gebou is toe dit beskikbaar geword het. In skrille kontras met sy Kleinskaalse- en Mediumskaalse ingegrasie voorgangers, het die eerste Grootskaalse integrasie weergawe van die PDP-11 'n SVE bevat wat slegs uit vier geïntegreerde stroombane (GIS) bestaan het.
Transistorgebaseerde rekenaars het verskeie beduidende voordele bo hul voorgangers gehad. Buiten dat hulle verhoogde betroubaarheid en laer kragverbruik in die hand gewerk het, het transistors dit ook vir SVE's moontlik gemaak om teen baie hoër snelhede te werk vanweë die korter skakeltyd van 'n transistor vergeleke met 'n buis of relê. Danksy die verhoogde betroubaarheid en die dramatiese verhoogde snelheid van die skakelelemente, is SVE's met kloksnelhede van etlike tien megahertz in die tydperk verkry. Terwyl diskrete transistor- en GIS-SVE's al meer alledaags geword het, het nuwe hoë werkverrigtingontwerpe soos Enkelinstruksie Veelvuldige Data vektorverwerkers ook hul verskyning begin maak. Hierdie vroeëre eksperimentele ontwerpe het later gelei tot die era van gespesialiseerde superrekenaars soos dié wat deur Cray Inc. vervaardig word.
Mikroverwerkers
Die bekendstelling van die mikroverwerker in die 1970's het die ontwerp van SVE's beduidend beïnvloed. Sedert die bekendstelling van die eerste mikroverwerker (die Intel 4004) in 1970 en die eerste algemeen gebruikte mikroverwerker (die Intel 8080) in 1974, het hierdie klas SVE's bykans alle implementerings van verwerkingseenhede vervang. Soos al hoe kleiner transistors op GIS'e gebou kon word, het die kompleksiteit en aantal transistors op 'n enkele SVE dramaties toegeneem. Hierdie waargenome neiging staan alom bekend as Moore se wet, wat tot op datum 'n akkurate vooruitskatting was vir die groeiende vermoëns van SVE's (en ander GIS'e).
Terwyl die kompleksiteit, grootte, bou en algemene vorm van SVE's drasties verander het oor die afgelope sestig jaar, is dit interessant dat die basiese ontwerp en funksie nie veel verander het nie. Bykans alle algemene SVE's van vandag kan baie noukeurig as Von Neumann gestoordeprogrammasjiene beskryf word. <!--
Moet nog vertaal word!!!
Microprocessors
As the aforementioned Moore's law continues to hold true, concerns have arisen about the limits of integrated circuit transistor technology. Extreme miniaturization of electronic gates is causing the effects of phenomena like electromigration and subthreshold leakage to become much more significant. These newer concerns are among the many factors causing researchers to investigate new methods of computing such as the quantum computer, as well as to expand the usage of parallelism and other methods that extend the usefulness of the classical Von Neumann model.
CPU operation
The fundamental operation of most CPUs, regardless of the physical form they take, is to execute a sequence of stored instructions called a program. Discussed here are devices that conform to the common Von Neumann architecture. The program is represented by a series of numbers that are kept in some kind of computer memory. There are four steps that nearly all Von Neumann CPUs use in their operation: fetch, decode, execute, and writeback.
The first step, fetch, involves retrieving an instruction (which is represented by a number or sequence of numbers) from program memory. The location in program memory is determined by a program counter (PC), which stores a number that identifies the current position in the program. In other words, the program counter keeps track of the CPU's place in the current program. After an instruction is fetched, the PC is incremented by the length of the instruction word in terms of memory units. Often the instruction to be fetched must be retrieved from relatively slow memory, causing the CPU to stall while waiting for the instruction to be returned. This issue is largely addressed in modern processors by caches and pipeline architectures (see below).
The instruction that the CPU fetches from memory is used to determine what the CPU is to do. In the decode step, the instruction is broken up into parts that have significance to other portions of the CPU. The way in which the numerical instruction value is interpreted is defined by the CPU's instruction set architecture (ISA). Often, one group of numbers in the instruction, called the opcode, indicates which operation to perform. The remaining parts of the number usually provide information required for that instruction, such as operands for an addition operation. Such operands may be given as a constant value (called an immediate value), or as a place to locate a value: a register or a memory address, as determined by some addressing mode. In older designs the portions of the CPU responsible for instruction decoding were unchangeable hardware devices. However, in more abstract and complicated CPUs and ISAs, a microprogram is often used to assist in translating instructions into various configuration signals for the CPU. This microprogram is sometimes rewritable so that it can be modified to change the way the CPU decodes instructions even after it has been manufactured.
After the fetch and decode steps, the execute step is performed. During this step, various portions of the CPU are connected so they can perform the desired operation. If, for instance, an addition operation was requested, an arithmetic logic unit (ALU) will be connected to a set of inputs and a set of outputs. The inputs provide the numbers to be added, and the outputs will contain the final sum. The ALU contains the circuitry to perform simple arithmetic and logical operations on the inputs (like addition and bitwise operations). If the addition operation produces a result too large for the CPU to handle, an arithmetic overflow flag in a flags register may also be set (see the discussion of integer range below).
The final step, writeback, simply "writes back" the results of the execute step to some form of memory. Very often the results are written to some internal CPU register for quick access by subsequent instructions. In other cases results may be written to slower, but cheaper and larger, main memory. Some types of instructions manipulate the program counter rather than directly produce result data. These are generally called "jumps" and facilitate behavior like loops, conditional program execution (through the use of a conditional jump), and functions in programs. Many instructions will also change the state of digits in a "flags" register. These flags can be used to influence how a program behaves, since they often indicate the outcome of various operations. For example, one type of "compare" instruction considers two values and sets a number in the flags register according to which one is greater. This flag could then be used by a later jump instruction to determine program flow.
After the execution of the instruction and writeback of the resulting data, the entire process repeats, with the next instruction cycle normally fetching the next-in-sequence instruction because of the incremented value in the program counter. If the completed instruction was a jump, the program counter will be modified to contain the address of the instruction that was jumped to, and program execution continues normally. In more complex CPUs than the one described here, multiple instructions can be fetched, decoded, and executed simultaneously. This section describes what is generally referred to as the "Classic RISC pipeline," which in fact is quite common among the simple CPUs used in many electronic devices (often called microcontrollers).
Integer range
The way a CPU represents numbers is a design choice that affects the most basic ways in which the device functions. Some early digital computers used an electrical model of the common decimal (base ten) numeral system to represent numbers internally. A few other computers have used more exotic numeral systems like ternary (base three). Nearly all modern CPUs represent numbers in binary form, with each digit being represented by some two-valued physical quantity such as a "high" or "low" voltage.
James Arnold Taylor
James Arnold Taylor (gebore 22 Julie 1969) is 'n Amerikaanse akteur, vervaardiger, en skrywer. Hy is bekend vir sy rolle in die rolprente TMNT (2007) en Star Wars: The Clone Wars (2008), en in die televisiereeks Star Wars: The Clone Wars (2008).
Sentrale verwerkingseenheid
Integer range
Related to number representation is the size and precision of numbers that a CPU can represent. In the case of a binary CPU, a bit refers to one significant place in the numbers a CPU deals with. The number of bits (or numeral places) a CPU uses to represent numbers is often called "word size", "bit width", "data path width", or "integer precision" when dealing with strictly integer numbers (as opposed to floating point). This number differs between architectures, and often within different parts of the very same CPU. For example, an 8-bit CPU deals with a range of numbers that can be represented by eight binary digits (each digit having two possible values), that is, 28 or 256 discrete numbers. In effect, integer size sets a hardware limit on the range of integers the software run by the CPU can utilize.
Integer range can also affect the number of locations in memory the CPU can address (locate). For example, if a binary CPU uses 32 bits to represent a memory address, and each memory address represents one octet (8 bits), the maximum quantity of memory that CPU can address is 232 octets, or 4 GiB. This is a very simple view of CPU address space, and many modern designs use much more complex addressing methods like paging in order to locate more memory than their integer range would allow with a flat address space.
Higher levels of integer range require more structures to deal with the additional digits, and therefore more complexity, size, power usage, and generally expense. It is not at all uncommon, therefore, to see 4- or 8-bit microcontrollers used in modern applications, even though CPUs with much higher range (such as 16, 32, 64, even 128-bit) are available. The simpler microcontrollers are usually cheaper, use less power, and therefore dissipate less heat, all of which can be major design considerations for electronic devices. However, in higher-end applications, the benefits afforded by the extra range (most often the additional address space) are more significant and often affect design choices. To gain some of the advantages afforded by both lower and higher bit lengths, many CPUs are designed with different bit widths for different portions of the device. For example, the IBM System/370 used a CPU that was primarily 32 bit, but it used 128-bit precision inside its floating point units to facilitate greater accuracy and range in floating point numbers. Many later CPU designs use similar mixed bit width, especially when the processor is meant for general-purpose usage where a reasonable balance of integer and floating point capability is required.
Clock rate
Most CPUs, and indeed most sequential logic devices, are synchronous in nature. That is, they are designed and operate on assumptions about a synchronization signal. This signal, known as a clock signal, usually takes the form of a periodic square wave. By calculating the maximum time that electrical signals can move in various branches of a CPU's many circuits, the designers can select an appropriate period for the clock signal.
This period must be longer than the amount of time it takes for a signal to move, or propagate, in the worst-case scenario. In setting the clock period to a value well above the worst-case propagation delay, it is possible to design the entire CPU and the way it moves data around the "edges" of the rising and falling clock signal. This has the advantage of simplifying the CPU significantly, both from a design perspective and a component-count perspective. However, it also carries the disadvantage that the entire CPU must wait on its slowest elements, even though some portions of it are much faster. This limitation has largely been compensated for by various methods of increasing CPU parallelism (see below).
One method of dealing with the switching of unneeded components is called clock gating, which involves turning off the clock signal to unneeded components (effectively disabling them). However, this is often regarded as difficult to implement and therefore does not see common usage outside of very low-power designs. Another method of addressing some of the problems with a global clock signal is the removal of the clock signal altogether. While removing the global clock signal makes the design process considerably more complex in many ways, asynchronous (or clockless) designs carry marked advantages in power consumption and heat dissipation in comparison with similar synchronous designs. While somewhat uncommon, entire CPUs have been built without utilizing a global clock signal. Two notable examples of this are the ARM compliant AMULET and the MIPS R3000 compatible MiniMIPS. Rather than totally removing the clock signal, some CPU designs allow certain portions of the device to be asynchronous, such as using asynchronous ALUs in conjunction with superscalar pipelining to achieve some arithmetic performance gains. While it is not altogether clear whether totally asynchronous designs can perform at a comparable or better level than their synchronous counterparts, it is evident that they do at least excel in simpler math operations. This, combined with their excellent power consumption and heat dissipation properties, makes them very suitable for embedded computers.
Parallelism
The description of the basic operation of a CPU offered in the previous section describes the simplest form that a CPU can take. This type of CPU, usually referred to as subscalar, operates on and executes one instruction on one or two pieces of data at a time.
This process gives rise to an inherent inefficiency in subscalar CPUs. Since only one instruction is executed at a time, the entire CPU must wait for that instruction to complete before proceeding to the next instruction. As a result the subscalar CPU gets "hung up" on instructions which take more than one clock cycle to complete execution. Even adding a second execution unit (see below) does not improve performance much; rather than one pathway being hung up, now two pathways are hung up and the number of unused transistors is increased. This design, wherein the CPU's execution resources can operate on only one instruction at a time, can only possibly reach scalar performance (one instruction per clock). However, the performance is nearly always subscalar (less than one instruction per cycle).
Attempts to achieve scalar and better performance have resulted in a variety of design methodologies that cause the CPU to behave less linearly and more in parallel. When referring to parallelism in CPUs, two terms are generally used to classify these design techniques. Instruction level parallelism (ILP) seeks to increase the rate at which instructions are executed within a CPU (that is, to increase the utilization of on-die execution resources), and thread level parallelism (TLP) purposes to increase the number of threads (effectively individual programs) that a CPU can execute simultaneously. Each methodology differs both in the ways in which they are implemented, as well as the relative effectiveness they afford in increasing the CPU's performance for an application.
ILP: Instruction pipelining and superscalar architecture
One of the simplest methods used to accomplish increased parallelism is to begin the first steps of instruction fetching and decoding before the prior instruction finishes executing. This is the simplest form of a technique known as instruction pipelining, and is utilized in almost all modern general-purpose CPUs. Pipelining allows more than one instruction to be executed at any given time by breaking down the execution pathway into discrete stages. This separation can be compared to an assembly line, in which an instruction is made more complete at each stage until it exits the execution pipeline and is retired.
Pipelining does, however, introduce the possibility for a situation where the result of the previous operation is needed to complete the next operation; a condition often termed data dependency conflict. To cope with this, additional care must be taken to check for these sorts of conditions and delay a portion of the instruction pipeline if this occurs. Naturally, accomplishing this requires additional circuitry, so pipelined processors are more complex than subscalar ones (though not very significantly so). A pipelined processor can become very nearly scalar, inhibited only by pipeline stalls (an instruction spending more than one clock cycle in a stage).
Further improvement upon the idea of instruction pipelining led to the development of a method that decreases the idle time of CPU components even further. Designs that are said to be superscalar include a long instruction pipeline and multiple identical execution units. In a superscalar pipeline, multiple instructions are read and passed to a dispatcher, which decides whether or not the instructions can be executed in parallel (simultaneously). If so they are dispatched to available execution units, resulting in the ability for several instructions to be executed simultaneously. In general, the more instructions a superscalar CPU is able to dispatch simultaneously to waiting execution units, the more instructions will be completed in a given cycle.
Most of the difficulty in the design of a superscalar CPU architecture lies in creating an effective dispatcher. The dispatcher needs to be able to quickly and correctly determine whether instructions can be executed in parallel, as well as dispatch them in such a way as to keep as many execution units busy as possible. This requires that the instruction pipeline is filled as often as possible and gives rise to the need in superscalar architectures for significant amounts of CPU cache. It also makes hazard-avoiding techniques like branch prediction, speculative execution, and out-of-order execution crucial to maintaining high levels of performance. By attempting to predict which branch (or path) a conditional instruction will take, the CPU can minimize the number of times that the entire pipeline must wait until a conditional instruction is completed. Speculative execution often provides modest performance increases by executing portions of code that may or may not be needed after a conditional operation completes. Out-of-order execution somewhat rearranges the order in which instructions are executed to reduce delays due to data dependencies.
In the case where a portion of the CPU is superscalar and part is not, the part which is not suffers a performance penalty due to scheduling stalls. The original Intel Pentium (P5) had two superscalar ALUs which could accept one instruction per clock each, but its FPU could not accept one instruction per clock. Thus the P5 was integer superscalar but not floating point superscalar. Intel's successor to the Pentium architecture, P6, added superscalar capabilities to its floating point features, and therefore afforded a significant increase in floating point instruction performance.
Both simple pipelining and superscalar design increase a CPU's ILP by allowing a single processor to complete execution of instructions at rates surpassing one instruction per cycle (IPC). Most modern CPU designs are at least somewhat superscalar, and nearly all general purpose CPUs designed in the last decade are superscalar. In later years some of the emphasis in designing high-ILP computers has been moved out of the CPU's hardware and into its software interface, or ISA. The strategy of the very long instruction word (VLIW) causes some ILP to become implied directly by the software, reducing the amount of work the CPU must perform to boost ILP and thereby reducing the design's complexity.
TLP: Simultaneous thread execution
The CMP and SMP methods of parallelism are similar to one another and the most straightforward. These involve little more conceptually than the utilization of two or more complete and independent CPUs. In the case of CMP, multiple processor "cores" are included in the same package, sometimes on the very same integrated circuit. SMP, on the other hand, includes multiple independent packages. NUMA is somewhat similar to SMP but uses a nonuniform memory access model. This is important for computers with many CPUs because each processor's access time to memory is quickly exhausted with SMP's shared memory model, resulting in significant delays due to CPUs waiting for memory. Therefore, NUMA is considered a much more scalable model, successfully allowing many more CPUs to be used in one computer than SMP can feasibly support. SMT differs somewhat from other TLP improvements in that it attempts to duplicate as few portions of the CPU as possible. While considered a TLP strategy, its implementation actually more resembles superscalar design, and indeed is often used in superscalar microprocessors (such as IBM's POWER5). Rather than duplicating the entire CPU, SMT designs only duplicate parts needed for instruction fetching, decoding, and dispatch, as well as things like general-purpose registers. This allows an SMT CPU to keep its execution units busy more often by providing them instructions from two different software threads. Again, this is very similar to the ILP superscalar method, but simultaneously executes instructions from multiple threads rather than executing multiple instructions from the same thread concurrently.
Vector processors and SIMD
A less common but increasingly important paradigm of CPUs (and indeed, computing in general) deals with vectors. The processors discussed earlier are all referred to as some type of scalar device. As the name implies, vector processors deal with multiple pieces of data in the context of one instruction. This contrasts with scalar processors, which deal with one piece of data for every instruction. These two schemes of dealing with data are generally referred to as SISD (single instruction, single data) and SIMD (single instruction, multiple data), respectively. The great utility in creating CPUs that deal with vectors of data lies in optimizing tasks that tend to require the same operation (for example, a sum or a dot product) to be performed on a large set of data. Some classic examples of these types of tasks are multimedia applications (images, video, and sound), as well as many types of scientific and engineering tasks. Whereas a scalar CPU must complete the entire process of fetching, decoding, and executing each instruction and value in a set of data, a vector CPU can perform a single operation on a comparatively large set of data with one instruction. Of course, this is only possible when the application tends to require many steps which apply one operation to a large set of data.
Most early vector CPUs, such as the Cray-1, were associated almost exclusively with scientific research and cryptography applications. However, as multimedia has largely shifted to digital media, the need for some form of SIMD in general-purpose CPUs has become significant. Shortly after floating point execution units started to become commonplace to include in general-purpose processors, specifications for and implementations of SIMD execution units also began to appear for general-purpose CPUs. Some of these early SIMD specifications like Intel's MMX were integer-only. This proved to be a significant impediment for some software developers, since many of the applications that benefit from SIMD primarily deal with floating point numbers. Progressively, these early designs were refined and remade into some of the common, modern SIMD specifications, which are usually associated with one ISA. Some notable modern examples are Intel's SSE and the PowerPC-related AltiVec (also known as VMX).
References
last = Hennessy | first = John A. | coauthors = Goldberg, David | title = Computer Architecture: A Quantitative Approach | publisher = Morgan Kaufmann Publishers | year = 1996 | id = ISBN 1-55-860329-8 }}
Universiteit van Exeter
Die Universiteit van Exeter (ook bekend as Exeter-universiteit) is 'n universiteit in Exeter, suidwestelike Engeland.
Ala
’n Ala of chala (Serwies en Macedonies: ала; Bulgaars: хала; meervoud ale, chali) is ’n mitologiese bose gees in die volksverhale van die Bulgare, Macedoniërs en Serwiërs.
Ale word beskou as demone van slegte weer wie se hoofdoel dit is om hael en donderstorms na boere se landerye te bring om hul gewasse te verwoes. Hulle eet nie net graag kinders nie, maar ook die son en maan (wat verduisterings tot gevolg het). As iemand ’n ala teenkom, is hulle geestelike of fisieke gesondheid, of selfs hulle lewe, in gevaar. As sy jou goedgesind is, kan sy jou egter ryk maak en jou lewe red in tye van gevaar.
Die voorkoms van ale is taamlik uiteenlopend en vaag in volksverhale. ’n Sekere ala kan soos ’n swart wind, ’n reuse skepsel met ’n onduidelike vorm, ’n mensagtige of slangagtige monster, ’n vroulike draak, ’n kraai, ens. wees. Hulle kan in der waarheid verskeie menslike en dierlike vorms aanneem en selfs in ’n mens se liggaam invaar.
Wanneer ’n ala in menslike vorm in ’n volksverhaal voorkom, is haar persoonlikheid baie soos dié van die Russiese Baba Jaga. Ale kan glo in die wolke, ’n meer, woud, groot boom of op ’n verafgeleë plek woon.
Terwyl ale die mens se vyand is, het hulle ook magtige vyande wat hulle kan verslaan, veral drake. In Christelike verhale neem Elia dikwels die rol van die drake oor as die ale se grootste vyand. In sommige verhale veg Elia en die drake saam teen die ale. Valke word ook soms beskou as ale se vyande – hulle jaag hulle van die landerye af weg en keer hulle dus om dit oor die landerye te laat hael.
Frans II
Frans II uit die dinastie Habsburg, volle naam Franz II Joseph Karl, (* 12 Februarie 1768 in Florence, Italië; † 2 Maart 1835 in Wene, Oostenryk) het tussen 1792 en 1806 as laaste Keiser van die Heilige Romeinse Ryk en tussen 1804 en 1835 as die eerste Keiser van Oostenryk geregeer.
Frans was die kleinseun van die keiser Franz I Stephan en die seun van die keiser Leopold II. Sy regeringstyd was deur sy teenstander Napoléon Bonaparte oorheers. Frans II moes die Heilige Romeinse Ryk ontbind, nadat hy deur Napoléon gedwing is om te abdikeer, waarna Frans homself as keiser van Oostenryk laat kroon het.
Erica nutans
Erica nutans is 'n plant wat tot die genus Erica behoort en is deel van die fynbos. Die plant is inheems aan die Oos-Kaap en Wes-Kaap.
Spoegbakkie
'n Spoegbakkie of kwispedoor is 'n bakkie waarin gespoeg word om van vloeistof of 'n oormaat speeksel en slym uit die mond ontslae te raak.
Die woord kwispedoor is afgelei van die Portugese woord 'cuspidor', wat spoegpot beteken. Die gebruik van spoegbakkies het via die VOC na Nederland en later na Suid-Afrika oorgewaai. Dit is aanvanklik gebruik deur persone wat tabak gesnuif of gepruim het.
In moderne etiket is dit ongeskik om in die openbaar te spoeg en moet dit liefs in 'n toe badkamer in 'n wasbak of toilet gedoen word. 'n Uitsondering op die reël is die gebruik van spoegbakkies tydens wynproesessies.
Armeense alfabet
Die Armeense alfabet (Հայկական Այբուբեն) word sedert die jaar 405 of 406 gebruik vir die skryf van Armeens. Dit is geskep deur st. Mesrop Masjtots, ’n Armeense taalkundige en godsdiensleier, en het oorspronklik 36 letters bevat. Nog twee, օ en ֆ, is in die Middeleeue bygevoeg. Tot in die 19de eeu was Klassieke Armeens die amptelike taal, en sedertdien word die Armeense alfabet gebruik om die twee amptelike dialekte, Oos-Armeens en Wes-Armeens, te skryf. Die Armeense woord vir "alfabet" is այբուբեն (aiboeben) en is genoem na die eerste twee letters, Ա (այբ, aib) en Բ (բեն, ben). Die alfabet word van links na regs geskryf.
Geskiedenis en ontwikkeling
Die Armeense alfabet is in 405 n.C deur st. Mesrop Masjtots, ’n Armeense taalkundige godsdiensleier, en sint Isak van Armenië geskep, hoofsaaklik vir die vertaling van die Bybel in Armeens. Middeleeuse Armeense bronne beweer Masjtots het omstreeks dieselfde tyd die Georgiese en die Kaukasiese Albanese alfabet geskep.
Daar is vier vorms van die skrif. Erkatagir ("gepantserde" letters) word beskou as Mesrop se oorspronklike skrif en is gebruik in manuskripte van die 5de tot die 13de eeu. Dit word steeds verkies vir epigrafiese inskripsies. Bolorgir ("kursief") is in die 10de eeu geskep en het in die 13de eeue gewild geword. Dit was van die 16de eeu af die standaard-drukletters. Notrgir ("kleinletters") is geskep vir spoed en is tussen die 16de en 18de eeu baie gebruik, en later in drukwerk. Sheghagir ("skuins skrif") is nou die mees algemene vorm.
Hoewel Oos- en Wes-Armeens dieselfde alfabet gebruik, word sommige letters verskillend uitgespreek vanweë die klankverskuiwing in Wes-Armeens:
Die aantal en volgorde van die letters het mettertyd verander. Die letters օ [o] en ֆ [f] is in die Middeleeue bygevoeg vir nie-Armeense klanke en die letters het toe van 36 tot 38 vermeerder. Van 1922 tot 1924 het Armeens in die Sowjetunie ’n spelhervorming ondergaan. Die uitspraak van die meeste letters het egter dieselfde gebly. Die hervorming is wyd verwerp (onder andere deur Armeniërs in Libanon en Iran). Hulle het beweer daar is politieke motiewe daaragter.
Unicode
Die Armeense alfabet is ingesluit in die Unicode-standaard sedert weergawe 4.0. Die Unicode-blok daarvoor is U+0530–U+058F. Vyf Armeense koppelletters kom voor in die "Alfabetiese voostellingsvorms"-blok, U+FB13–U+FB17.
Melville
duimnael|links|200px|Die [[NG gemeente Melville (Melville-kruiskerk) se gebou op die hoek van Vierde Laan en Vierde Straat.]]
Melville is 'n boheemse voorstad sowat 5 km wes van Johannesburg se middestad waar sommige van die Goudstad se gewildste kuierplekke geleë is. Melville se kroeë en restaurante lok veral studente van die Universiteit van Johannesburg se nabygeleë Aucklandparkkampus asook studente van die Universiteit van die Witwatersrand in naburige Braamfontein.
In teenstelling met die meeste ander noordelike voorstede is Melville saam met Parkhurst en Greenside een van min plekke waar koffiehuise, restaurante en winkels langs strate geleë en nie tot winkelsentrums beperk is nie. Sy besondere atmosfeer en sy ligging naby die historiese voorstad Sophiatown maak van Melville ook 'n toeristetrekpleister. Die Melvillekoppies, golwende heuwels temidde van 'n grasveld in die gelyknamige natuurreservaat, is nie net 'n belangrike opgrawingsplek nie, maar bied ook 'n goeie uitsig oor Johannesburg.
Dan O'Bannon
Dan O'Bannon (30 September 1946 – 17 Desember 2009) was 'n Amerikaanse skrywer en akteur. Hy was bekend vir sy rolle in die rolprente Dark Star (1974), Alien (1979), The Return of the Living Dead (1985), en Aliens (1986).
Melville
Geskiedenis
Die voorstad is op 5 Oktober 1896 geproklameer en genoem na die landmeter Edward Harker Vincent Melvill. In die openbare verkoopskennisgewing is Melville beskryf as 'n "skilderagtige en gesonde plek in die nabyheid van Johannesburg, met 'n uitstekende uitsig oor die beboste landskap in die noorde, met die blou bergreekse van Pretoria wat soos lyne van staal teen die gesigseinder uitstrek".
Langs Melville se strate het koffiekroeë, restaurante en winkels ontstaan. Die meerderheid eetplekke is langs 7de Straat geleë, hoewel enkele nuwe restaurante en nagklubs langs Hoofstraat gevestig is. Met meer as dertig gastehuise in die nabye omgewing is Melville 'n gewilde verblyfplek vir toeriste. Die Afrikaanse sepie 7de Laan het tot 2015 bygedra tot Melville se landswye bekendheid met openingstonele van sepia-getinte winkels langs 7de Straat, maar dit is in daardie jaar vervang deur beelde van moderne winkels wat niks met Melville te doen het nie
In 2015 het 'n ongewone nuwe winkelsentrum sy deure in Melville geopen. 27Boxes bestaan uit sowat tagtig skeepshouers wat in meer as 100 winkels omskep is. Die inspirasie vir die sentrum, wat deur die firma Citiq gebou is, het soortgelyke projekte in Engeland en Frankryk gelewer.
Rolstoelrugby
Rolstoelrugby is 'n spansport vir atlete met 'n liggaamsgebrek. Dit word in meer as twintig lande beoefen en word ook op die Paralimpiese Spele verteenwoordig.
Die sport is laat in die 1977 oorspronklik in Kanada ontwikkel deur die vyf rolstoelatlete Jerry Terwin, Duncan Campbell, Randy Dueck, Paul LeJeune en Chris Sargent. Dit het oorspronklik murderball ("moordbal") geheet, as gevolg van die aggressiewe, vol-kontak karakter van die sport en is bedag om kwadruplegiese atlete met 'n wye reeks funksionele vermoëvlakke die kans te bied om integrale offensiewe en verdedigende posisies te speel.
In die VSA staan die sport ook bekend as kwadrugby, wat verwys na die feit dat dit deur kwadrupleë gespeel word: al die deelnemende atlete het 'n gebrek wat beide hulle boonste en onderste ledemate affekteer. Rolstoelrugby is 'n gemengde sport, met mans en vroue wat in dieselfde spanne meeding. Wedstryde word binnemuurs op houtvloere gespeel. Die spelreëls bevat elemente van onder andere rolstoelbasketbal, yshokkie en handbal. Dit is 'n kontaksport en fisiese kontak tussen spelers is 'n integrale gedeelte van die spel.
Rolstoelrugby word bestuur deur die Internasionale Rolstoelrugbyfederasie, wat in 1993 gestig is.
Dirk Ziervogel
Dirk Ziervogel (*12 November 1917, Ermelo – †26 Maart 1977, Belfast, Mpumalanga) was ’n akademikus en kenner van Bantoetale.
Ziervogel was die seun van Carl Frederik Ziervogel en sy vrou, Cecilia Johanna Kemp. Ziervogel het op Ermelo skoolgegaan en in 1935 aan die Hoërskool Ermelo gematrikuleer. Hierna het hy onder prof. J.A. Engelbrecht, hoogleraar in Bantoekunde aan die Universiteit van Pretoria gestudeer en die volgende grade behaal: B.A. (1938), M.A. (1941) en D.Litt. in 1948. Terwyl hy nog student was, is hy reeds in 'n tydelike hoedanigheid aan die universiteit aangestel en in 1941 is hy as lektor in Bantoetale aangestel. In 1945 was hy ook as lokasiesuperintendent van die Pretoriase stadsraad werksaam, terwyl hy nog deeltyds klas aan die UP gegee het. Dit was egter net 'n gedeeltelike onderbreking van sy akademiese werk, want in 1947 het hy 'n senior lektoraat in Bantoetale aan die UP aanvaar. In 1954 het hy die akademiese wêreld verlaat toe hy as navorsingsbeampte by die destydse Departement Naturellesake aangestel is. In dieselfde jaar nog het hy egter 'n aanstelling as hoogleraar en hoof van die Departement Bantoetale aan die Universiteit van Suid-Afrika aanvaar en was tot sy dood aan hierdie inrigting verbonde.
Ziervogel het 'n deeglike kennis van die Ngunitale, veral Swazi, gehad en daarnaas van die Sothotale, veral Noord-Sotho. Hy het later ook 'n besondere studie van die Vendataal gemaak. Onder sy leiding het die dosering van die Bantoetale aan Unisa uitgebrei om al die erkende Bantoetale van Suid-Afrika in te sluit. Die departement het in die 23 jaar wat hy daaraan verbonde was, voortdurend uitgebrei, sodat daar met sy afsterwe 'n personeel van sowat 77 was. Hy het as hoof van die departement tot 1973 gedien, toe sy menigvuldige aktiwiteite hom genoodsaak het om dit in te perk. Hy was lid van verskeie belangrike komitees van Unisa en het van 1971 tot 1973 as dekaan van die Fakulteit Lettere en Wysbegeerte gedien.
Deur sy toedoen is die Mqhayi-prys vir Bantoeletterkunde ingestel en hy het 'n belangrike aandeel gehad in die keuring van die publikasies wat vir dié toekenning in aanmerking gekom het. Hy was ook jare lank betrokke by die werk van die Gemeenskaplike Matrikulasieraad en was by sy afsterwe die verteenwoordiger van Unisa in hierdie raad. Hy het 'n aansienlike bydrae gelewer tot die uitbouing van die leergange van die Bantoetale op skoolvlak. Hy was ook lid van die destydse Bantoetaalraad en van sommige van die raad se taalkomitees, en het 'n besondere aandeel gehad in die saamstelling van die ortografieë van die Sothotale. Verder was hy vanaf die instelling daarvan, lid van die Inboorlingtaalraad van Suidwes-Afrika/Namibië. By sy afsterwe was hy reeds geruime tyd lank lid van die raad van die Universiteit van die Noorde.
Ferdinand I van Oostenryk
Ferdinand I uit die dinastie Habsburg, volle naam Ferdinand I Karl Leopold Joseph Franz Marcellin, (* 19 April 1793 in Wene, Oostenryk; † 29 Junie 1875 in Praag, Tsjeggië) het tussen 1830 en 1848 as Koning van Hongarye en Kroasië en tussen 1835 en 1848 as Keiser van Oostenryk geregeer.
Ferdinand I was die kleinseun van die keiser Leopold II en die seun van die keiser Frans II. Ná die Rewolusie van 1848 het hy abdikeer en Frans Joseph I word Keiser.
Erica nyassana
Erica nyassana is 'n plant wat tot die genus Erica behoort en is inheems aan Malawi.