Microprogrammed State Machine Design

PREFACE. Acknowledgments. INTRODUCTION. THE PROBLEM. SOLUTION. Solution-Continuous or Discrete? Solution-Continuous. Solution-Discrete. THE ALGORITHMIC STATE MACHINE. THE INSTRUCTION SET PROCESSOR. REPRESENTATION OF NUMBERS. REPRESENTATION. Unsigned Binary Integers. Signed Binary Integers. TWO's Complement Signed Binary Integers. ADDITION OF SIGNED AND UNSIGNED BINARY NUMBERS. Overflow. CONVERSION BETWEEN TWO'S COMPLEMENT AND SIGN/MAGNITUDE NOTATIONS. SUBTRACTION OF SIGNED AND UNSIGNED BINARY INTEGERS. ENCODED BINARY NOTATIONS. FIXED POINT NOTATION. THE FLOATING POINT REPRESENTATION. The IEEE 754 Floating Point Representation. Floating Point Addition and Subtraction. Floating Point Multiplication. Floating Point Overflow. Summary of Floating Point Representation. ARCHITECTURAL COMPONENTS. REVIEW OF BASIC DIGITAL ELEMENTS. SIMPLE COMBINATIONAL STRUCTURES. THE SIMPLEST ARITHMETIC STRUCTURE-THE ADDER. COMBINATIONAL NETWORKS FORMED BY COMBINING SIMPLE NETWORKS. The Multibit Full Adder. The Shifter. The Arithmetic/Logic Unit (ALU). MEMORY ELEMENTS. Flip-Flops. Registers. Complex Register Structures. COMPLEX REGISTER STRUCTURES WITH DATA COMBINATION CAPABILITY. The Accumulator. The Register Arithmetic/Logic Unit (RALU). Real RALUs. TABLE DRIVEN ARITHMETIC OPERATIONS. MULTIPLICATION. FLOATING POINT ARITHMETIC UNITS. SOME REAL ARCHITECTURAL UNITS. Real Register Arithmetic Logic Units. Real Integer Multipliers and MACs. Real Floating Point Units. CONTROLLERS. ALGORITHMIC STATE MACHINE DESIGN. ROM-LATCH MICROPROGRAMMED ASM IMPLEMENTATION. REGISTER BASED ADVANCED MICROPROGRAMMED CONTROLLERS. REGISTER BASED CONTROLLER WITH ALL OF THE BELLS AND WHISTLES. INTEGRATED CIRCUIT MICROPROGRAMMED CONTROLLERS. Examples of the Next Address Generator. Integrated Microprogrammed Controllers. ASSEMBLERS. THE MICROPROGRAM WORD. THE SYMBOLIC MICROINSTRUCTION FORMAT. THE DEFINITION PROCESS. THE ASSEMBLY PROCESS. OPERATION OF THE MICROCODE ASSEMBLER SYSTEM. AN ASSEMBLER FOR THE SECOND-LEVEL MACHINE-INTRODUCTION. THE FORMAT OF AN ASSEMBLER LANGUAGE STATEMENT. ASSEMBLER IMPLEMENTATION METHODS. THE CROSS ASSEMBLER. AN ASSEMBLER ALGORITHM DETAIL. METHOD USED TO ADAPT A MACROASSEMBLER. EXTENDED USE OF MACROS. PLACING THE ASSEMBLER PROGRAM IN THE TARGET ISP. A SHAREWARE ASSEMBLER. Examples of Microcoding with A68K. Examples Showing A68K Used as a Second Level Cross Assembler. APPENDIX A: User's Manual for the Microtec Meta Assembler. APPENDIX B: User's Manual for the Modified A68K Macro Cross Assembler. APPENDIX C: Data Transmission Formats for Object Files. HARDWARE DESCRIPTION LANGUAGE AND SIMULATION. PROGRAM DESIGN LANGUAGE. REGISTER TRANSFER LANGUAGE. SIMULATION OF THE SECOND LEVEL OF CONTROL. The Fetch/Execute Cycle Based Simulator. Macro Based Simulator. SIMULATION OF THE FIRST LEVEL OF CONTROL. The Register Transfer Language as a Simulator. Behavioral Simulation of Architectural Components. ALGORITHMS AND ARCHITECTURES. DESIGNS USING ONE LEVEL OF CONTROL. Some Introductory Designs. Accumulation. Multiplication of Unsigned Binary Numbers. Multiplication of 2's Complement Binary Numbers. Division of Unsigned Binary Numbers. The Arithmetic Sum of Products. The Power Series Expansion. REPLACEMENT OF ALGORITHMIC MODULES BY COMBINATIONAL MODULES. COPROCESSORS. MEMORY MAPPED COPROCESSOR. Independent Coprocessors. FINAL EXAMPLE. A MICROPROGRAMMED COMPUTER. BASIC ARCHITECTURE. The Instruction Set. The Addressing Modes. The Programming Model. THE SECOND LEVEL MACHINE INSTRUCTION FORMAT. MAJOR LOGICAL SECTIONS OF THE COMPUTER. MAJOR PHYSICAL SECTIONS IN THE COMPUTER EXAMPLE. IMPLEMENTATION OF THE FIRST LEVEL MACHINE. SOME IMPORTANT SEQUENCES. THE RESET SEQUENCE. THE INSTRUCTION FETCH SEQUENCE. THE BASIC ADDRESS MODE SEQUENCES. ADDITIONAL ADDRESS MODES. DEALING WITH MICROWORD SYMBOLICALLY. EXECUTION SEQUENCES. DETAILED DESCRIPTION OF THE BASIC COMPUTER EXAMPLE. APPENDIX A: Microcode Bit Field Definitions for the Basic Computer Example. APPENDIX B: Multiplexer Select Definitions. APPENDIX C: Parsed MICROCODE Display. APPENDIX D: Instruction Set Reference. Sweet/16 Instruction Set User's Manual. APPENDIX E1: Sweet 16 Macro Definition File. APPENDIX E2: Sweet 16 MONITOR Program. APPENDIX G: First Level Definition File for Basic Computer Example. APPENDIX H: First Level Assembler Source Program for the Basic Computer Example. APPENDIX I: Demonstration. IMPROVEMENTS, VARIATIONS, AND CONCLUSION. IMPROVEMENTS. IMPROVEMENTS. The Memory Address Register Bus. Byte/Word Addressing. Interrupts to the Second Level of Control. Memory Access by Controllers Other than the CPU. Instruction and Data Pipelines and Caching. VARIATIONS. Traditional Controller Implementation. Reduced Instruction Set Computer (RISC) Architecture. Digital Signal Processors (DSP). Video Processors. Pseudo Second Level Machine. INDEX. due February 1993, ISBN 0-8493-4464-6