The Realization of Uniform and Reliable Intrinsic Gettering in 200mm p- and p/p- Wafers for a Low Thermal Budget 0.18μm Advanced CMOS Logic Process

Ppolished and P/Pepitaxial wafers with and without an MDZ® (Magic Denuded Zone) heat-treatment have been processed through a low thermal budget 0.18μm advanced CMOS Logic process. Measurements at key stages in the process clearly demonstrate that very little precipitation (below detection limit) occurs in the standard Por P/Pwafers. In contrast, very uniform precipitation with consistent BMD (bulk micro-defect) and PFZ (precipitate-free zones) are observed for wafers that received the prior MDZ® heat-treatment. This was demonstrated by subjecting the wafers to an additional 16 hour 1000°C anneal designed to grow precipitates to a size where they become detectable by the cleave and etch technique. In addition, nickel haze gettering tests clearly demonstrated that reliable gettering of nickel (up to 4x10 cm) could be obtained early in the device process for wafers which received the MDZ® heattreatment without the need for the additional 16 hour 1000°C anneal. However, nickel haze was observed for standard Ppolished and P/Pepitaxial wafers even at the end of the process indicating the complete lack of any intrinsic gettering. Introduction With the move to smaller device geometries and low thermal budget processing, there has been a lot of renewed interest in the intrinsic gettering (IG) capability of silicon wafer substrates. Although P/P+ wafers generally have sufficient amounts of oxygen precipitation through a device process due to the fact that high boron concentrations enhance oxygen precipitation, this is clearly not the case for lightly doped Pand P/Pwafers. For intrinsic gettering to be effective, the density and size of oxygen precipitates in the wafer bulk needs to be greater than some critical value [1]. During wafer cooling, metals such as nickel or copper, which may have been inadvertently introduced during device processing, precipitate at the oxygen precipitates in the wafer bulk since the solubility of these metals decreases with decreasing temperature. In addition to the requirement for decreasing metal solubility with temperature, there is usually sufficient time during conventional furnace ramps to allow the metal to diffuse from the surface to the bulk. This is the so called “relaxation” model of intrinsic gettering which is generally now widely accepted [2]. It is also essential to have a region close to the wafer surface that is essentially free of precipitates (a “denuded” or “precipitatefree” zone) since nearsurface precipitates can cause device leakage problems. The traditional method of achieving this IG structure in Por P/Pwafers has been to anneal the wafers at high temperatures (T>1050°C) for several hours to allow oxygen out-diffusion in the near surface region. This is usually followed by a low temperature (T~650°C) anneal to nucleate precipitates in the wafer bulk followed by growth of these precipitates at high temperatures (T>800°C). Unfortunately, it is no longer possible or cost effective to incorporate these steps into advanced processes because of the need to maintain a low thermal budget to prevent excessive dopant diffusion. For these reasons, several new approaches including nitrogen and carbon doping (with/without epi and with/without high temperature anneals) have been developed to achieve reliable intrinsic gettering in these advanced processes. Nitrogen and carbon have been found to be effective in enhancing oxygen precipitation for a given thermal cycle [3,4,]. Both nitrogen and carbon doping, however, introduce an added complexity into crystal growth since the axial and radial concentrations of both the added impurity as well as the oxygen concentration need to be controlled for reproducible IG performance. A very effective alternative method is to use MDZ® (Magic Denuded Zone) technology [5,6]. Unlike nitrogen and carbon doping, MDZ® is applied at the wafer level and has been demonstrated to produce consistent BMD densities and PFZ depths which are largely independent of initial (Oi), crystal section and of the device process. During the MDZ® process, a vacancy template is created which basically leads to the formation of an ideal IG structure with BMDs >1x10 cm and a PFZ > 50μm during a subsequent device process. Title of Publication (to be inserted by the publisher) In this paper, the BMD and PFZ characteristics of Pand P/Pepi-wafers with and without an MDZ® pre-treatment will be compared at key stages in a low thermal budget 0.18μm advanced CMOS logic process. Oxygen measurements are reported using the “New ASTM” calibration factor (4.9α0; units of ppma)