Physical Layout Design of Directed Self-Assembly Guiding Alphabet for IC Contact Hole/via Patterning

The continued scaling of feature size has brought increasingly significant challenges to conventional optical lithography.[1-3] The rising cost and limited resolution of current lithography technologies have opened up opportunities for alternative patterning approaches. Among the emerging patterning approaches, block copolymer self-assembly for device fabrication has been envisioned for over a decade. Block copolymer DSA is a result of spontaneous microphase separation of block copolymer films, forming periodic microdomains including cylinders, spheres, and lamellae, in the same way that snowflakes and clamshells are formed in nature - by self-assembly due to forces of nature (Fig. 1a). DSA can generate closely packed and well controlled sub-20 nm features with low cost and high throughput, therefore stands out among other emerging lithographic solutions, including extreme ultraviolet lithography (EUV), electron beam lithography (e-beam), and multiple patterning lithography (MPL).[2;6]Previous research has shown a high degree of dimensional control of the self-assembled features over large areas with long range ordering and periodic structures.[5; 6] The exquisite dimensional control at nanometer-scale feature sizes is one of the most attractive properties of block copolymer self-assembly. At the same time, device and circuit fabrication for the semiconductor industry requires accurate placement of desired features at irregular positions on the chip. The need to coax the self-assembled features into circuit layout friendly location is a roadblock for introducing self-assembly into semiconductor manufacturing. Directed self-assembly (DSA) and the use of topography to direct the self-assembly (graphoepitaxy) have shown great potential in overcoming the current lithography limits.[4]Recognizing that typical circuit layouts do not require long range order, we adopt a lithography sub-division approach akin to double-patterning and spacer patterning, using small guiding topographical templates. Guiding topographical templates with sizes of the order of the natural pitch of the block copolymer can effectively guide the self-assembly of block polymer (Fig. 1b-c). Therefore, circuit contact hole patterns can be placed at arbitrary location by first patterning a coarse guiding template using conventional lithography.[7; 8] This procedure enables generating a higher resolution feature at a location determined by the coarse lithographic pattern. The size and registration of the features are determined by parameters of the template as well as the block copolymer itself.Using this technique, we have proposed a general template design strategy that relates the block copolymer material properties to the target technology node requirements, and demonstrated contact hole patterning at the technology node from 22 nm to 7 nm, for both memory circuits and random logic circuits.[11] The critical dimension of DSA patterns is highly uniform, with their position controlled precisely. As technology scales down, the contact/via density scales up, which simultaneously opens the possibility of using multiple-hole DSA patterns for contact hole patterning and brings in the challenge of printing guiding templates at a small pitch. Using DSA for patterning IC contacts requires further knowledge of the placement of contacts in an IC layout, as the placement of contacts in the IC layout determines the shape and size of the required templates.We hypothesize that there exists a limited set of guiding templates analogous to the letters of an alphabet that can cover all the possible contact hole patterns of a full chip contact layer.[12] This alphabet approach would significantly simplify DSA contact hole patterning when the total number of letters of the alphabet is small and would allow us to focus on fully characterizing only the design spaces for the letters of the alphabet. By positioning these letters in various locations we would be able to pattern the full chip contact layer in the same way that the 26 letters of the English alphabet is sufficient to compose an English newspaper. Some of the most basic letters, such as circular templates for 1-hole DSA patterns and elliptical templates for 2- and 3-hole DSA patterns, have been studied extensively.[12] To establish a complete alphabet, though, requires the examination of the entire standard cell library, as well as the optimization of the layout to further reduce the number of letters in the alphabet.[5]The broad community of DSA researchers has made tremendous progress in the past few years. However to make DSA fully qualified for large-scale semiconductor manufacturing, technical issues such as defectivity reduction and overlay optimization must be solved. While many researchers are developing new block copolymer materials for better chemical properties, there remains more works to be accomplished from the circuit and system design level, including IC layouts optimization for the improvement of DSA process yield and DSA full-chip hotspot detection. Challenges such as optimizing and tuning the template design based on overlay, defectivity, and lithography requirements will need to be further investigated in order for practical implementation in industry.