Tutorial T6B: Embedded Memory Design for Future Technologies: Challenges and Solutions

Conventional CMOS memory i.e., Static Random Access Memory (SRAM) has been the popular choice for embedded memory application for last several decades. However, SRAM seems to be approaching a brick wall. On one hand process variability and leakage power is posing severe obstruction towards SRAM scaling to future nodes and on the other hand, emerging energy-constrained and bandwidth hungry electronic gadgets demand for larger as well as energy-efficient on-chip cache which cannot be satisfied with SRAM. To address the changing landscape of consumer market, there is a corresponding need of changing the design paradigm. What is really needed is a memory technology that is at least 50-100X denser, 1000X energy-efficient and as fast as SRAM. Several emerging memory technologies are on the horizon but there is no clear universal choice for embedded application. This tutorial will explore the latest trends in the embedded memory segment and discuss the fundamental limitations of SRAM in meeting the new needs of the electronic systems. The complex (and not very well understood) interrelationships between memory density, bandwidth, latency, power and speed will be elaborated in the context of emerging graphics applications. Next the tutorial will discuss few promising emerging memory technologies where storage element is based on charge, spin and resistance. Specifically, the tutorial will focus on the operating principles, design challenges and solutions of volatile memory such as embedded Dynamic Random Access Memory (eDRAM) and non-volatile memories (NVM) such as Domain Wall Memory (DWM) and memrister. The eDRAM section of the tutorial will present the trade-offs such as low-power peripherals (e.g., wordline driver, sense amplifier) and its impact on random access time (tRC) and retention. The relationship between noise sources (e.g., process variations, coupling effects) and retention power will also be described. Design techniques such as pulsed sense amplifier, peripheral sleep etc. will be introduced to control and mitigate the effect of noise in high speed eDRAM arrays for future technology nodes. Next the tutorial will describe DWM which is a spin-based memory technology. Various design metrics such as read/write power, speed, reliability and retention will be discussed in detail. The tutorial will address the modeling and simulation methodology for design and analysis of DWM arrays. Various design challenges such as reliable shift circuitry, positioning of read/write head, impact of process variations on sense margin, reliability of nanowire etc. will be described. Design techniques to improve robustness, operating speed and array density will also be presented. The last part of this tutorial will describe memrister where the storage element is resistive in nature. Typically memrister suffer from high access power. Design techniques to lower the power consumption such as data encoding, write pause etc. will be discussed to mitigate the power while maintaining required robustness. The audiences will be able to takeaway following key points from this tutorial (a) changing landscape of emerging electronic systems and inability of SRAM to cater to these new needs in scaled technologies, (b) emerging memory technologies for embedded applications and their relative merits in terms of density, power, speed and reliability, (c) design methodologies, challenges and potential solutions to enable these emerging memories for embedded applications.