Power and ground co-referencing for high speed 10–28Gbps transceivers in FPGA and ASIC devices

Signal integrity and power integrity are treated as separate issues in conventional package electrical designs. There is no intended coupling between power and signal nets. High speed IO trace routing and vias are shielded with ground planes and ground vias as return current paths. Power nets are typically routed on separated planes shielded with ground planes to provide low impedance path for power distribution from die to PCB system. However, as package cost driven down with silicon process advanced to 20nm node and beyond, package designs require new IO-PDN (power distribution networks) configurations, in which high speed IO are implemented to reference to both power and ground as return path. As a result, IO and PDN are directly coupled to each other. It is crucial for design engineers to understand the impacts of the co-referenced IO-PDN system and associated performance trade-off in system noise and timing requirements. Previous publications studied the effects in rather simple transmission line structure [ref 1]. Other work has been focus on single ended DDR memory interface for date rate less than 3Gbps [ref 2]. This paper presents analysis on high speed 10-28Gbps package that deployed co-referenced power network as return path to transmission lines, in contrast to conventional ground return. The study covers physical mechanism investigation to non-ideal return path to signal and power supply performance impact. We expect to rectify the use of power reference in product development for 10's Gbps serdes applications. The study is carried out by analytical, model, simulation and hardware validations. It is the first study to our best knowledge in the package design field that takes on the power-ground co-referencing for transceiver at date rate of 28Gbps. The study of co-referenced IO-PDN system will be carried out to address three main areas of concerns as listed below. Furthermore, We will introduce the enabling methodology for combined modeling and simulation of power and signal capturing the power to signal, signal to single and vertical return current. - Signal transmission impact in insertion/return loss, crosstalk and associated channel jitter - PDN impedance impact and its effect on power supply induced jitter - PDN and signal mutual coupling and induced jitter We have strategized two design scenarios to compare to ideal ground only reference, firstly co-referencing in ball/PCB breakout region only, and secondly to add co-referencing in power/ground planes inside package. The cost saving comes from replacing ground balls with power balls to guard transceiver channels for adequate performance. This will lead to more balls (originally allocated for transceiver powers) available for more serdes and DDR IOs in the same package. In addition to spare balls, the second scenario saves layer count, which is one of the dominant cost factors in today's high end packages. Throughout the study, the author will provide mitigation guidelines for such design practice to be applied in the real world devices. Furthermore, the authors have made sure the abovementioned recommendations validated in a 28nm test device specifically built for this purpose.