A Universal Test Fixture For Characterizing MM-Wave Solid State Devices Using A Novel Deembedding Procedure

ABSTRACT The design and evaluation of a novel fixturing technique for characterizing mm-wave solid state devices, including monolithic microwave integrated circuits, is presented. The technique utilizes a cosine tapered ridge guide fixture and a one-tier deembedding procedure to provide accurate and repeatable device level data. Advanced features include "nondestructive" testing, full waveguide bandwidth operation, a high degree of universal ism, and rapid yet repeatable chip-level characteriza­ tion. Furthermore, only one set of calibration standards is required regardless of device geometry. INTRODUCTION Accurate characterization of solid state devices at millimeter wavelengths is hindered by limited metrological techniques due to unpredictable parasitics, diminutive physical dimensions, and inconvenient interface methods (1). Typically, devices are characterized by S-parameters using an automatic network analyzer (ANA). To be accessible to the ANA and amenable to characterization, the device must be mounted in a fixture. This fixture introduces substantial insertion and return loss effects, both in magnitude and phase, often masking the true device characteristics. Hence, it would be desirable to devise a mathematical scheme to reposi­ tion the reference (measurement) plane adjacent to the device terminals. This procedure is known as deembedding and requires chip level microstrip stan­ dards to shift the reference plane from the fixture- to-ANA interface to the device area.Drawbacks of existing fixtures include non- repeatability, fixturing and calibration complexity, and limited bandwidth. Most techniques require cum­ bersome device mounting arrangements and are labor intensive. The fixture presented here utilizes a cosine tapered ridge guide transition to match the high waveguide impedance to the 50 Q microstrip. The taper length and profile have been analytically determined to provide maximum bandwidth and minimum insertion loss. Discrete devices and integrated circuits are mounted on a customized carrier which is inserted between the bottom of the ridge and the base of the waveguide. The electric field is con­ centrated by the ridge and launched onto the carrier by direct pressure contact. Control voltages are applied to the carrier using a self-aligned bias module with integral spring loaded contacts. Deem­ bedding is accomplished using a modified "through, short, delay" (TSD) calibration algorithm.DESIGNSince the fixture itself is mechanically rigid, the required versatility was built into the carrier.A 0.020 in. alumina substrate was chosen for ease of manufacturability, good dielectric properties, and relatively good thermal and mechanical characteris­ tics. The thickness was constrained to a narrow range due to certain electrical features and a con­ cern about the generation of higher order modes. DC blocks are required since the carrier microstrip is in contact with the fixture body. A coupled line section 0.032 in. long with 0.0029 in. wide fingers and 0.002 in. gaps was found to be optimum (2,3). Bias can be fed directly to the chip input and out­ put microstrip lines through two high RF impedance bias filters. The chip is mounted in a laser machined well in the center of the carrier and is supported by a gold plated kovar subcarrier.The ridge waveguide transition can be described by dividing the design into three calculations, first outlined in (4). First, the ridge waveguide cutoff wavelength must be obtained. At cutoff, propagation may be considered to be restricted to a wave traveling transversely across the guide with no longitudinal component. The cutoff wavelength is derived by solving for the input impedance of a simple equivalent network (5). Next, the ridge thickness is determined by evaluating the infinite frequency characteristic impedance for the TE10 mode as given in (6). Finally, the profile of the physi­ cal taper must be determined. A sinusoidal varia­ tion is assumed since this geometry outperforms most other candidates in terms of optimizing return loss in the shortest electrical length. Based on the above calculations, a taper length of 1.366 in. and a ridge thickness of 0.0695 in. was chosen.Due to its practical implementation in micro- strip, a TSD calibration routine was chosen for deembedding. The technique, first proposed by Franzen and Special (7) used a one-tier calibration approach and assumes an eight term error model. Based on measurements of the three standards, all 16 terms (magnitude and phase) of the error net­ works can be determined. The topography of the model consists of three cascaded two port networks; hence, the S-parameters of the error networks and device are converted to T-parameters for mathemati­ cal convenience. The T-matrix of the model is equal to the product of the individual T matrices; there­ fore, the matrix of the deembedded device can be extracted and reconverted to S-parameters (8). Sub­ sequent to the initial calibration, the ancillary reference plane is mathematically shifted to the device boundaries through the translation exp(-y&). Gamma (y), the complex propagation constant, is determined from the "through" and "delay" measure­ ments. The physical length of the device, Q,, must be known. It is this feature which permits the use of only one set of calibration standards.