Hardware/software design implementation of feature detection for a reconfigurable processor

ABSTRACT Image processing algorithms are suitable for reconfigurable architectures due to their matrix structures, inherentparallelism and need for flexibility and processing speed. This paper describes a method to implement feature detectionon the ReConfigurable Processor (RCP). The RCP is an FPGA-based system, which was built by the VLSI-RCPResearch Group at UCSD and L3 Communications. The design is based on the Altera FLEX 10K70. The architectureused to implement feature detector on RCP, software and hardware implementation will be discussed.Keywords: FPGA, reconfigurable computing, image processing. I. INTRODUCTION Image segmentation is an important area in image processing. It is one of the most commonly used operations in imageanalysis. In the analysis of the objects in image, the objects of interest are segmented from the background. A varietyof techniques for image segmentation have been introduced. They can be categorized by three methods. The firstmethod is based upon image thresholding technique, which uses a predetermined graylevel as a decision criterion. Thismethod separates an image into different regions based upon the graylevels of the pixels. The second method uses thediscontinuities between graylevel regions to detect contours within an image. The third method of image segmentationis to separate an image into several regions based upon desired criteria. For example, pixels, which are connected andhave same graylevel, can be grouped together to form one region.Feature detection is an important part of image segmentation. An edge is the boundary between an object and thebackground. Edges indicate the boundary between overlapping objects. This implies that if the edges in an image canbe identified accurately, all objects can be located and some basic properties such as area, perimeter, and shape can bemeasured. Since computer vision involves the identification and classification of objects in an image, edge detection isan essential tool for computer vision. Real time feature detection requires manipulating massive amount of data at highspeeds. Field Programmable Gate Arrays (FPGAs) enable a new approach for board designs for computer vision. Therate of the feature detection operations will be increased when they are performed in a dedicate hardware such asFPGAs. This technology provides the horsepower necessary to implement real-time image processing productssuccessfully and cost effectively.This paper describes one of image processing applications that we are working on the ReConfigurable Processor (RCP).RCP is an FPGA-based system, which was built by the VLSI-RCP Research Group at UCSD and L3 Communications.ReConfigurable Processor is a co-processor for an IBM compatible personal computer system. RCP system has beendesigned to be a flexible processor and internal interconnects reconfigurable application-specific embedded computer.Current and forthcoming algorithms incorporated into the RCP include variable constraint length convolution ForwardError Correction (FEC), data encryption/decryption, and common signal and image processing algorithms such as FastFourier Transform, Discrete Cosine Transform, and Wavelet Transform. The remainder of this paper is organized as