EUV lithography: prospects and challenges

Integrated circuit scaling as codified in Moore's Law has been enabled through the tremendous advances in lithographic patterning technology over multiple process generations. Optical lithography has been the mainstay of patterning technology to date. Its imminent demise has been oft proclaimed over the years but clever engineering has consistently been able to extend it through many lens size and wavelength changes. NA has increased steadily from about 0.3 to 1.35 today with improvements in lens design and the use of immersion lithography. Simultaneously, the illumination wavelength has been reduced from 436nm about 20 years ago to 193nm for state-of-the-art scanners today. However, this approach has reached its limits. The 22nm technology node, targeted for HVM in 2011, represents the last instance of using standard 1.35NA immersion lithography-based patterning for the critical layers with a ki hovering right around the 0.3 value that is considered acceptable for manufacturability For the 14nm node with a HVM date of 2013, one has to resort to double patterning to achieve a manufacturable. k 1 For the 10nm technology node with a 2015 HVM date, double patterning will also be insufficient. While further ArF extension schemes are being considered, the industry is working towards lowering the wavelength from 193nm to Extreme Ultraviolet Lithography with a λ of 13.5nm. EUV offers the prospect of operating at significantly higher ki and as a consequence, much simpler design rules and potentially simpler OPC. However, the technical challenges are formidable. EUV lithography requires the re-engineering of every subsystem in the optical path — source, collector and projection optics, reticles and photoresists. A huge industry-wide effort is under way to solve these technical issues and bring 13.5nm EUV lithography to production. Two main approaches are being considered for EUV sources — Laser Produced Plasma (LPP) and Discharge Produced Plasma (DPP). Both approaches appear to be heading towards production and it remains to be seen if one approach is more scalable to higher power levels. Currently however, neither approach is close to the power levels required to deliver runrates that will have a reasonable Cost of Ownership (COO). Clearly, a lot of development is ahead to make this happen. Photoresists have also seen a significant amount of technical development, primarily using small field Micro Exposure Tools (MET). Photoresist companies are working on developing the chemical platforms needed for EUV photoresists. While much progress has been made on photospeed, resolution and linewidth roughness, further improvements are required to meet the needs of the 14nm and 10nm process nodes. Since EUV employs reflective optics, EUV reticles are reflective as well and this poses several challenges. Apart from the obvious complexities of EUV reticle manufacturing, defectivity is a major concern, both from the standpoint of making defect-free masks as well as from the requirement of detecting the defects and repairing them. A significant industry-wide effort is being driven both among individual companies and through consortia like SEMATECH to develop both the manufacturing techniques required to make high-quality masks and the inspection and repair capabilities needed. Probably the most complex technical challenge and one largely untested in an HVM sense is the scanner itself. The current state of the art is the ASML Alpha Demo Tool (ADT) currently in use at SEMATECH and IMEC. This 0.25NA tool has a low runrate and limited technical capabilities but can print full fields and has been a valuable tool in the early demonstration of integrated device and circuit fabrication using EUV lithography. Working SRAM cells and other circuits have been demonstrated with very promising results. The first development-quality EUV scanners are targeted to ship to end users in 2011, while the HVM versions with high targeted runrates and low targeted COO are slated for delivery beginning in mid-2012. The delivery of these tools at the end users' fab and their subsequent integration into the process flow will pose the greatest challenge and is expected to require a significant outlay of engineering effort and resources in the next 2 years. EUV presents its own challenges in terms of non-idealities that would need to be quantified and corrected for. While conventional OPC may be minimal, EUV has other sources of variability including flare and mask shadowing that would need to be compensated for. Moreover, the likelihood of defects on EUV masks brings up the possibility of pattern shifting to place the defects in benign areas of the reticle. All of these new challenges require OPC, synthesis or other data manipulation methodologies to be developed for EUV. This paper will attempt to highlight the key technical challenges of EUV lithography and where the industry will need to focus its efforts over the next 2 years to make EUV manufacturing successful and cost-effective.