Guest Editorial: Special Issue on Analog, Mixed-Signal, RF, and MEMS Testing

Test cost has gradually become a major portion of the overall product cost for System-on-Chips (SoCs). Developing efficient methods to test and debug analog, mixed-signal, and radiofrequency (RF) circuitries is of particular interest due to their lengthy test times and increased complexity. In the past, mixedsignal/RF circuits were built as stand-alone chips, so test developments were geared toward characterizing individual building blocks. With increased integration, the controllability and observability to these mixed-signal/RF circuits has become limited. As a result, built-in self-test (BIST) and design-fortestability (DfT) modifications that can help reduce test time and facilitate silicon debug have gained more attention. This special issue collects 16 state-of-the-art solutions for testing various mixed-signal, RF, and MEMS circuits. The first four papers propose BIST techniques for on-chip mixed-signal, RF, and MEMS modules. In paper 1, Zhang et al. develop an amplitude detector that transforms highfrequency signals into DC/low-frequency components. They then infer high-frequency circuit performance from detectors’ output and show that both the systemand component-level performances can be tested with great accuracy. In paper 2, Hung and Hong propose a BIST scheme for ADCs where the control signals are wirelessly transmitted from an HOY tester. They show that the BIST test results align well with those produced by conventional methods. In paper 3, Kim and Abraham propose a BIST scheme for testing the setup and hold time of the memory interface. They use a static mode test method to determine pass/fail on the timing specifications, as well as a dynamic mode test method to measure the amount of timing mismatch. In paper 4, Sarraf et al. develop an adaptive technique based on pseudo-random sequences for testing and calibrating MEMS-based accelerometers and gyroscopes. Papers 5 to 7 focus on techniques for generating accurate and low-cost test signals. In paper 5, Duan et al. incorporate the “stimulus error identification and removal” (SEIR) algorithm into their BIST solution so that they can test high-resolution ADCs without using high precision stimuli, thereby saving cost. For applications that require time or frequency domain test stimulus, in paper 6, Tsai et al. develop a time/frequency-domain signal generator using a sigma-delta modulator, a digital-to-frequency or a digital-totime converter, and a phase locked-loop. Testing ADCs usually requires high-precision signal generation. In paper 7, Wakabayashi et al. propose an algorithm for generating low distortion sine-wave signals using low-resolution (hence, low cost) waveform generators. Papers 8 to 12 enhance observability of internal analog signals. In paper 8, Kulovic and Margala introduce a technique for on-chip voltage measurement. On-chip voltages are first converted to the time domain, and subsequently, to the frequency domain using a centralized time-to-digital converter. The distributed manner of voltage-to-time conversion enables concurrent voltage measurement. In paper 9, Maltabas et al. propose a current sensor that is suitable for IDDQ measurement. In paper 10, Gomez et al. exploit the relationship between device transconductance and static power dissipation to observe process variations. In paper 11, Dasnurkar and Abraham propose a built-in current sensor that is suitable for measuring internal bias currents. Responsible Editor: H.-M. Chang