Adaptive Test Methods for High IC Quality and Reliability

The wide variation in process parameters now being observed in advanced semiconductor processes can sometimes cause the electrical impact of subtle manufacturing defects on observed signals during post manufacturing tests to remain within the acceptable range set to ensure viable manufacturing yields, thereby masking defect detection. Such undetected manufacturing flaws can potentially cause functional failure under inputs and/or operating conditions not tested during test; they can also behave as latent reliability defects that "grow" over time to cause early life failure. Test methodologies that target the "zero-defect" product quality requirements being pushed by automotive and an increasing number of other applications must address such test escapes by using innovative statistical methods and adaptive testing because of the prohibitive costs of extensive functional and stress/burn-in testing of all parts. The basic idea here is similar to "zero-defect" security screening at airports: parts that pass the initial tests but appear to be "suspect" is some respect are separated out for more extensive tests. Also, additional specialized tests are adaptively added to the test flow to target the suspected failure mode; this requires both the feeding forward and feeding back of results from different stages of the testing process. A few seriously suspect but passing parts may even be discarded outright to ensure quality, if the resulting yield loss is acceptable.Advanced statistical screening methods fall into two broad categories: those that exploit the statistics of defect distribution on wafers - e.g. passing die in "bad" wafer neighborhoods are suspect parts; and those that exploit the correlation in performance parameters in lots and wafers - passing die that are performance outliers relative to matched parts are suspect. This tutorial presents screening methodologies that span both these categories, for both digital and analog parts. We illustrate their effectiveness using results from a number of published experimental studies on production circuits from IBM, Intel, LSI Logic, NXP Semiconductors, and MediaTek. The examples discussed focus on studies where the tests target classical stuck-at faults, as well as IDDQ testing, TDF and path delay timing tests, and also the newly introduced cell aware fault models.Recently, adaptive test methods have been more broadly defined to also include test time reduction techniques based on dynamic test reordering, adaptive scan shift frequency selection for each die, etc. The benefits and challenges of employing these methods are also discussed.Several new companies have emerged targeting the "Adaptive Test" space in recent years. Their commercial offerings are also presented and discussed. Broadly, these aim to provide the software infrastructure and tools needed to support the feed forward and feedback sharing of results from the different test insertions in the test flow for effective test adaptation and optimization. These test results are then utilized by customizable templates to generate automated test selection algorithms that can dynamically apply the most effective test at each test insertion/stage in the test flow, and also perform statistical binning once all testing is complete.