Aggressive SiGe Channel Gate Stack Scaling by Remote Oxygen Scavenging: Gate-First pFET Performance and Reliability

Biaxially strained SiGe channels (cSiGe) on Si for pchannel MOSFETs (pFETs) have recently received much attention for their ability to reduce the threshold voltage (Vt) of hafnium-based high-k/metal gate (HKMG) transistors [1-5]. Herein, we demonstrate for the first time that aggressive gate dielectric scaling in cSiGe pFETs can be achieved in gate-first integration via remote interfacial SiO2 layer (IL) scavenging by metal-doped TiN gates, analogous to cSi nFETs [6,7], rendering remote IL scavenging an attractive scaling option for dual-channel CMOS. We show that an inversion thickness (Tinv) of 0.86 nm (equivalent oxide thickness EOT ~ 0.45-0.5 nm) can be reached. We then provide a detailed study of ILscaling-induced pFET Vt increase and hole mobility reduction, and we establish an exponential IL thickness dependence of charge trapping under negative bias temperature instability (NBTI) stress. Transistors were fabricated as follows: After well implant and activation (10 cm), epitaxial cSiGe with optional Si cap was grown by chemical vapor deposition (CVD), followed by a chemical oxide IL, HfO2, and an optional Al2O3 cap for Vt adjustment. Then, TiN was deposited, remotely doped with a highoxidation-affinity metal (M) as in our nFET work [6,7], and capped with Si, followed by a self-aligned process with 1000°C rapid thermal anneal (RTA) and forming gas anneal (FGA) or a special cSiGe anneal [1]. Transmission electron microscopy (TEM, Fig. 1) of Si-capped low-Ge-content cSiGe pFETs with Al2O3 cap shows progressive IL scavenging with increasing amount of M dopant, resulting in an inversion capacitance boost (Fig. 2a) and thus Tinv scaling from 1.41 to 0.86 nm (EOT ~ 0.45-0.5 nm, Fig. 2b), among the lowest reported values for cSiGe transistors [2,3]. Fig. 2b further shows that Si caps prevent undesirable IL regrowth on cSiGe (confirmed by TEM, not shown), rendering Tinv nearly independent of channel Ge content. Stacks without Al2O3 cap require less M dopant for the same Tinv (Fig. 2b). cSiGe successfully reduces pFET Vt (Fig. 3a). However, we find that Vt of Al2O3-capped stacks on cSiGe increases when Tinv is scaled aggressively, unlike for uncapped stacks. This is analogous to La-capped nFETs [8], suggesting that the Vt tuning dipole caused by Al diffused to the IL diminishes for thinner IL. Increased channel Ge content may be used to retarget Vt at low Tinv. In addition to the Vt benefit, biaxially strained cSiGe further provides a hole mobility boost (Fig. 3b) and reduced hysteresis / charge trapping under NBTI stress compared to Si channels (Fig. 3c) [1,2]. Aggressive IL thinning reduces high-field mobility by 5.5 cm/Vs per 0.1 nm Tinv scaling, likely due to enhanced remote phonon or charge scattering. This sensitivity is lower than for nFETs, for which we have reported electron mobility loss of 20 cm/Vs per 0.1 nm Tinv scaling [7]. Finally, we find that charge trapping during NBTI stress increases exponentially when thinning the IL (Fig. 3c). This results in shrinking reliability margins, requiring careful HKMG optimization and possibly reductions in operating voltage to enable scaling at future technology nodes.