Complementary heterostructure FET readout technology for infrared focal plane arrays

ABSTRACTThis paper describes a CMOS-like readout technology using GaAs heterostructure field effect transistors. Bandgapengineering techniques are described which provide complementaiy p-channel and n-channel GaAs FETs attractive forperforming advanced signal processing functions with minimal power consumption and with precision operation in harsh environments. At 77 K, n&p channel CHFETs exhibit amplification ftors of 6.7 and 2.3 mA/V2, respectively, with nearly ideal sub-threshold characteristics and no I-V kinks or hysteresis. CHFET ring oscillatorsat 77 K attain propagation delays under 200 pS/gate while maintaining standby power dissipation under 1 iW/gateand switching power of0.1 W/gatefMHz. A simple operational amplifier exhibited 100 dB open loop gain at 65 Kwith 80 pA input leakage and 500 j.LW total power consumption.2. INTRODUCTIONComplementary Heterostructure Field Effect Transistor (CHFET) technology was pioneered by Honeywell in 1985as a way to implement CMOS-like logic circuits in GaAs material1 .Ideally,this would combine the advantages ofCMOS circuitry (low standby power, high IC density and complexity, flexible mixed-mode functions) with theadvantages of GaAs transistors (higher digital speed/power ratio and analog gain-bandwidth, reliability in radiationand cryogenic environments, optoelectronic integration). CHFET technology has been developed extensively fordigital circuits operating at room temperawre, demonstrating several fully complementary LSI-level ICs with state-of-the-art speed/power However, the cryogenic and analog aspects of CHFET are not as welldeveloped. In this paper, we present the first CHFET device and circuit characteristics at 77 Kelvin and explore theirpotential for future development of IRFPA readout electronics.3. CHFET STRUCTURE AND FABRICATIONA true GaAs CMOS technology has been sought after for many years3. The stumbling block has always been intrying to grow or deposit a suitable gate insulator (chemically stable, with minimal trap density). CHFET takes adifferent approh, seeking to implement the CMOS device structure in Ill-V material using heterostructureengineering. A simple comparison between CHFET and CMOS is shown in Figure 1 . TheCHFET heterostructureconsists of 3 layers: an undoped GaAs buffer to isolate tive layers from the substrate, a 200A undopedIn.GaAs channel where the carriers move from source to drain, and a 250A Alrj.75GaAs gate barrier layer(analagous to the SiO gate insulator in Silicon MOS). A thin GaAs cap layer ontop protects the heterostructureduring IC processing. It is grown by Molecular Beam Epitaxy (MBE) on commercial 3-inch GaAs substrates.The CHFET fabrication process is planar and self-aligned, employing automated 10: 1 optical lithographythroughout. After hetemsiructure growth, refractory WS1 gate metal is sputter deposited and delineated to a nominal1 I.tm gate length using reactive ion etching. Selective ion implantation creates self-aligned source/drain regions forn-channel and p-channel FETs. A rapid optical anneal activates the implants without damaging the heterostructure.Adjacent transistors are isolated by ion implantation. Ohmic contacts are formed with sintered Au-basedmetalizations for both n&p type transistors. Circuits are wired using a two-level Au-based interconnect system withplugged was. Both interconnect levels are off-substrate to reduce leakage and radiation sensitivity. Polyimideprovides passivation for completed ICs. Die are separated by diamond blade sawing and mounted into standard ICpackages.