A comparison of scalable superscalar processors

The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path lengths of many components in existing implementations grow as O(n’) where n is the fetch width, the issue width, or the window size. This paper describes two scalable processor architectures, the Ultrascalar I and the Ultrascalar II, and compares their VLSI complexities (gate delays, wire-length delays, and area.) Both processors are implemented by a large collection of ALUs with controllers (together called execution stations) connected together by a network of parallel-prefix tree circuits. A fattree network connects an interleaved cache to the execution stations. These networks provide the full functionality of superscalar processors including renaming, out-of-order execution, and speculative execution. The difference between the processors is in the mechanism used to transmit register values from one execution station to another. Both architectures use a parallel-prefix tree to communicate the register values between the execution stations. The Ultrascalar I transmits an entire copy of the register file to each station, and the station chooses which register values it needs based on the instruction. The Ultrascalar I uses an H-tree layout. The Ultrascalar II uses a mesh-of-trees and carefully sends only the register values that will actually be needed by each subtree to reduce the number of wires required on the chip. The complexity results are as follows: The complexity is described for a processor which has an instruction-set architecture containing L logical registers and can execute n instructions in parallel. The chip provides enough memory bandwidth to execute up to M(n) memory operations per cycle. (M is assumed to have a certain regularity property.) In all the processors, the VLSI area is the square of the wire delay. The Ultrascalar I has gate delay O(log n) and wire-delay i @(da if M(n) is O(nl/‘+), 7wires = O(fi(L + logn)) if M(n) is O(n’j2), and O(fiL + M(n)) if M(n) is 0(nli2+‘) ‘This work was partially supported by NSF Career Grants CCR-9702980 (Kuszmaul) and MIP-9702281 (Henry) and by an equipment grant from Intel. Permission to make digital or hard copies of all or part of this work for personal or classroom USC is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the tirst page. To copy otherwise, to republish, to post on servers or to redistribute to lists. requires prior specific permission and/or a fee. SPAA ‘99 Saint Malo, France Copyright ACM 1999 I-581 13-124-0/99/06...$5.00 for e > 0. The Ultrascalar II has gate delay @(log L + log n). The wire delay is O(n), which is optimal for n = O(L). Thus, the Ultrascalar II dominates the Ultrascalar I for n = O(L2), otherwise the Ultrascalar I dominates the Ultrascalar II. We introduce a hybrid ultrascalar that uses a two-level layout scheme: Clusters of execution stations are layed out using the Ultrascalar II mesh-of-trees layout, and then the clusters are connected together using the H-tree layout of the Ultrascalar I. For the hybrid (in which n > L) the wire delay is @(a + M(n)), which is optimal. For n 1 L the hybrid dominates both the Ultrascalar I and Ultrascalar II. We also present an empirical comparison of the Ultrascalar I and the hybrid, both layed out using the Magic VLSI editor. For a processor that has 32 32-bit registers and a simple integer ALU, the hybrid requires about 11 times less area.