Coupling Of Synthesis And Layout: Challenges And Solutions

As the IC technologies move into deep submicron designs, many physical design effects, such as the delay and noise associated with interconnects, are becoming significant, often dominating, factors in determining the overall circuit performance and reliability. Therefore, it is critical to consider layout design during high-level and logic-level synthesis in order to meet tight design constraints and achieve the best possible performance in deep submicron designs. This session starts with an embedded tutorial on "Logical-Physical Co-design for Deep Submicron Circuits: Solutions and Challenges" by Prof. Massoud Pedram, followed by discussions by a panel of experts from industry and academia on the following issues: 1. Reality and Needs: Why the conventional design flow with separated synthesis and physical design fail to work well for today’s designs? How bad is the convergence problem using the conventional design flow for today’s high-performance designs? Can the conventional design flow be fixed with incremental enhancements, or a revolutionary change in the design flow and design methodology is needed? 2. Challenges: How synthesis tools can consider detailed physical effects, such as interconnect delay, coupling noise, ground bounce, electro-migration failure, etc. early in the design cycle? If merging logic synthesis and physical design is inevitable, how can we to handle over 100 million transistor designs, while each design step itself is already facing serious challenges to meet the design complexity? 3. Possible Solutions: What models and metrics should be used by the future synthesis tools? What are the design and optimization techniques available to handle the complexity and constraint of the merged synthesis and layout problem? What are enabling technologies and directions that we need to devote much more research? 4. Impact and Implications: How will the merging of synthesis and layout, impact the overall design flow and other design tools, such as parasitic extraction, simulation, and verification? How will the new methodology impact the EDA industry? Organizer/Moderator; Jason Cong (Univ. of California, Los Angels, USA) Panel members; Edward Hsieh (Avant!, USA) Joe Hutt (Synopsys, USA) George Janac (Cadence, USA) Takashi Mitsuhashi (Toshiba Corp., Japan) Massoud Pedram (Univ. of Southern California, USA) Malgorzata Marek-Sadowska (Univ. of California, Santa Barbara, USA) BIOGRAPHIES OF THE PANELISTS Edward Hsieh is Director of Layout Products at Avant! Corporation in Freemont, CA. His current focus is on physical design products for deep submicron chip designs at 0.25um and below technologies. Prior to joining Avant!, he was a Senior Engineering Manager at IBM Microelectronics responsible for developing advanced design tools for deep submicron chips. Dr. Hsieh received his PhD in Electrical Engineering and Computer Science from Columbia University. Joe Hutt recently joined the Advanced Technology group at Synopsys after a 31 year career with IBM. Currently responsible for the integration of the System on a chip strategy for Synopsys. Positions at IBM included the management of the design tools group for the development of the Power PC. Joe was responsible for the development of the design methodology for the Somerset project and established the initial design system for the IBM-Motorola project. His technical career spanned twenty two years and included the development of routing engines for IBM technology and a US patent for timing driven placement algorithms. He has a BSEE from Union College in New York. George Janac is Chief Technical Officer in Cadence Design Systems managing engineering for the DSM business unit. Technical work is focused on RTL Design Planning and Optimization and the next generation in Floorplanning. Founder and President of High Level Design Systems where he helped create and develop the Design Planning into an important EDA area. George comes from a long background in IC micro-processor design at Bell Labs/Apple, as well as EDA tool development background with both technical and management experience. Takashi Mitsuhashi received B.S. and M.S. degrees in electrical engineering from Keio University, Yokohama, Japan, in 1972 and 1974, respectively. Since 1974, he has been with the Toshiba Corporation, Kawasaki, Japan, where he is currently a senior manager of the DA Development Dept., Semiconductor DA & Test Engineering Center. He was a visiting scholar in the Electrical Engineering Department, University of California, Berkeley, from 1990 to 1992. His research interests include LSI layout, layout verification, low power LSI design technology, and deep sub-micron issues. Mr. Mitsuhashi is a member of the Institute of Electronic, Information and Communication Engineers and the Information Processing Society of Japan. Massoud Pedram is an associate professor of Electrical Engineering Systems at the University of Southern California. He is a recipient of the National Science Foundation’s Young Investigator Award in 1994 and the Presidential Early Career Award for Scientists and Engineers (a.k.a. the Presidential Faculty Fellows Award) in 1996. His research has received a number of awards including an ICCD Best Paper Award, a DAC Best Paper Award, and an IEEE Transactions on VLSI Systems Best Paper Award. He has served on the technical program committees of a number of CAD conferences and acted as the technical co-chair and general co-chair of the International Symposium on Low Power Electronics and Design in 1996 and 1997, respectively. Dr. Pedram’s research interests span many aspects of design and synthesis of VLSI circuits, with particular emphasis on layout-driven synthesis and design methodologies and tools for low power. Malgorzata Marek-Sadowska received M.S. degree in Applied Mathematics (1971) and a Ph.D. degree in Electrical Engineering (1976) from Politechnika Warszawska ( Technical University of Warsaw ), Poland. From 1976 to 1982 she was Assistant Professor at the Institute of Electron Technology at the Technical University of Warsaw. She was a Visiting Professor in the Electrical Engineering Department of the University of California at Berkeley from 1979-80. She became a Research Engineer at the U.C.Berkeley Electronics Research Laboratory in 1979 and continued there until 1990, when she joined the Department of Electrical and Computer Engineering at the University of California, Santa Barbara, as a Professor. From 1989 to 1993 she was Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and Editor-In-Chief from 1993 to 1995. She is an IEEE Fellow.