HALT to qualify electronic packages: a proof of concept

A proof of concept of the Highly Accelerated Life Testing (HALT) technique was explored to assess and optimize electronic packaging designs for long duration deep space missions in a wide temperature range (–150°C to +125°C). HALT is a custom hybrid package suite of testing techniques using environments such as extreme temperatures and dynamic shock step processing from 0g up to 50g of acceleration. HALT testing used in this study implemented repetitive shock on the test vehicle components at various temperatures to precipitate workmanship and/or manufacturing defects to show the weak links of the designs. The purpose is to reduce the product development cycle time for improvements to the packaging design qualification. A test article was built using advanced electronic package designs and surface mount technology processes, which are considered useful for a variety of JPL and NASA projects, i.e. (surface mount packages such as ball grid arrays (BGA), plastic ball grid arrays (PBGA), very thin chip array ball grid array (CVBGA), quad flat-pack (QFP), micro-lead-frame (MLF) packages, several passive components, etc.). These packages were daisy-chained and independently monitored during the HALT test. The HALT technique was then implemented to predict reliability and assess survivability of these advanced packaging techniques for long duration deep space missions in much shorter test durations. Test articles were built using advanced electronic package designs that are considered useful in various NASA projects. All the advanced electronic packages were daisychained independently to monitor the continuity of the individual electronic packages. Continuity of the daisy chain packages was monitored during the HALT testing using a data logging system. We were able to test the boards up to 40g to 50g shock levels at temperatures ranging from +125°C to -150°C. The HALT system can deliver 50g shock levels at room temperature. Several tests were performed by subjecting the test boards to various g levels ranging from 5g to 50g, test durations of 10 minutes to 60 minutes, hot temperatures of up to +125°C and cold temperatures down to -150°C. During the HALT test, electrical continuity measurements of the PBGA package showed an open-circuit, whereas the BGA, MLF, and QFPs showed signs of small variations of electrical continuity measurements. The electrical continuity anomaly of the PBGA occurred in the test board within 12 hours of commencing the accelerated test. Similar test boards were assembled, thermal cycled independently from -150°C to +125°C and monitored for electrical continuity through each package design. The PBGA package on the test board showed an anomalous electrical continuity behavior after 959 thermal cycles. Each thermal cycle took around 2.33 hours, so that a total test time to failure of the PBGA was 2,237 hours (or ~3.1 months) due to thermal cycling alone. The accelerated technique (thermal cycling + shock) required only 12 hours to cause a failure in the PBGA electronic package. Compared to the thermal cycle only test, this was an acceleration of ~186 times (more than 2 orders of magnitude). This acceleration process can save significant time and resources for predicting the life of a package component in a given environment, assuming the failure mechanisms are similar in both the tests. Further studies are in progress to make systematic evaluations of the HALT technique on various other advanced electronic packaging components on the test board. With this information one will be able to estimate the number of mission thermal cycles to failure with a much shorter test program. Further studies are in progress to make systematic study of various components, constant temperature range for both the tests. Therefore, one can estimate the number of hours to fail in a given thermal and shock levels for a given test board physical properties.