Pentium 4 processor package design and development

Intel Pentium 4 ushered a new IA-32 architecture with a jump in performance from the previous generation microprocessors. Higher core frequency, higher bus speed and new architecture features needed very competitive package designs. The demand on packaging tu match such product performance necessitated development of new technologies. This paper describes development and implementation of package technologies for two generations of silicon processes of Pentium 4 as well as for intra-process shrink variations of the die for various applications. Pentium 4 is the new IA-32 architecture processor for use in multiple platforms. In addition to Desktop and Mobile segments, enhanced versions are for use in workstation and server systems also. The Mobile market segment is further divided into Full Feature, Thin & Light and Mini-Note sub-segments with the respective Performance and Value subdivisions. Likewise, the Desktop segment is divided into Performance, Mainstream and Value subsegments whereas the IA-32 Server segment is subdivided into UP (Uni-Processor), DP (Dual-Processor) & MP (Multi-Processor) catering different market sub-segments. Pentium 4 debuted in 0.18 p Si process with successive migration to 0.13 p process. It had a roadmap of progressively higher clock frequencies and bus frequencies. The initial packaging for 0.18 pm process Pentium 4 was done using an Interposer type package. which consisted of an OLGA substrate with (flipchipattached die) surface mounted on a (through-pin type) PGA interposer at 1.27 mm diagonal pitch. This twc-part solution looked unattractive from overall package parasitics as well as line item management perspectives. Therefore, a new organic PGA package called FCPGA was employed with surface mount attached pins at 1.27 mm square pitch. This enabled achieving a socketahle package with a single piece part. In addition to eliminating 2 piece parts for packaging, this new package allowed the body size reduction from 53.3 mm to 35.0 mm. It also dramatically improved the package and pin parasitics to allow more robust electrical performance. The product architecture employs the Nethurst architecture for turbo performance. The overall power associated with the processor, along with the dddt posed a challenge for the package design. The methodology of designing decoupliig capacitor schemes for the packages is described. Power delivery improvement was a major part of the design analysis activities with the package and system level issues considered. VO performance was analyzed for different design feature parameters ensuring signal integrity. Optimization of design rules for balancing the layout and cost drivers is described. b The product performance and cost in the 0.18 pn Si process were optimized by successive die shrinks. The packaging approach to address such cases is also discussed. The socket parameters for the two package types are also compared. The package model and simulation results for package parameter variation are shown. The thermal-electrical reliability aspects of the package parameters were considered to ensure that the package would perform reliably both on a global and local basis. This was especially important in view of the significant power density variation and current demand variation over the die area. Thermal power management was challenging due to the system level cost constraints. Thermal interface material development done for improved thermal resistances is described with the thermal solutions of the packages described briefly. Finally, the future direction of packaging for Intel processors is discussed.