Sphere detection and ldpc decoding algorithms and architectures for wireless systems

Ever increasing demand for high data rate wireless transmissions with high spectral efficiency leads to utilization of communication systems with multiple transmit and receive antennas. In addition, excellent error-rate performance can be achieved with iterative receiver structure composed of inner detection and outer decoding. In this work we design algorithms and architectures for iterative wireless receivers with multiple antennas applied for both downlink and uplink scenarios. Our goal is to develop wireless receivers with implementable hardware cost and excellent error-rate performance while supporting data rates of emerging and future wireless systems in the order of tens and hundreds of MBits/sec. Soft sphere detection algorithm with reduced computational complexity based on probabilistically bounded candidate-search process is proposed as an inner detection solution. The error-rate performance are improved compare to the state-of-the-art bounded soft sphere detection schemes with similar implementation costs. Partial candidate-search algorithm called QRD-QLD detection is also developed for fast mobile downlink receivers. It has significantly smaller detection latency than the well-known QRD-M algorithm proposed for several emerging wireless systems. In the same time, the error-rate performance are equivalent for identical utilization of hardware resources. We also apply bounded soft sphere detection after the MMSE channel equalization at the uplink receiver (base-station site) in the single-carrier frequency division multiple access (FDMA) system supported by the 3GPP-LTE standard. The interference from multiple users is better suppressed compare to other multiuser detection schemes with affordable increase of computational complexity. Cost-efficient high-speed architecture design of soft sphere detector that supports candidate-search with variable search bounds per transmit antenna has been also proposed. The LDPC decoding based on layered belief propagation is used for outer decoding. The block-structured LDPC codes are utilized. These codes have error-correcting abilities close to excellent fully random codes, and also they support modular decoders where a single processor core can be utilized for a broad range of code rates and codeword sizes, which is a crucial feature for the evolution of standards. Different levels of processing parallelism for structured semi-parallel LDPC decoders are evaluated. We propose estimation methodology that quickly and accurately determines decoder architecture with optimal tradeoff between area cost, decoding throughput and error-rate performance. Non-pipelined and pipelined versions of the structured semi-parallel LDPC decoder architecture with different levels of processing parallelism are also implemented. Furthermore, we are first to design block-structured LDPC codes for particular inner soft sphere detection and channel fading environment while supporting modular high-speed decoder architectures with moderate (implementable) codeword sizes. Finally, we propose methodology to estimate level of processing parallelism at the physical layer part of the iterative receiver necessary to achieve real-time data-rates of future wireless systems, such as 1 Gbps downlink data-rate.