Proceedings of the 2013 ACM international symposium on International symposium on physical design

On behalf of the organizing committee, we are delighted to welcome you to the 2013 ACM International Symposium on Physical Design (ISPD), held at the Ridge Tahoe Resort in Stateline, Nevada. Continuing the great tradition established by its twenty-one predecessors, which includes a series of five ACM/SIGDA Physical Design Workshops held intermittently in 1987-1996 and sixteen editions of ISPD in the current form since 1997, the 2013 ISPD provides a premier forum to present leading-edge research results, exchange ideas, and promote research on critical areas related to the physical design of VLSI and other related systems. We received 57 submissions from all around the world. After a rigorous, month-long, double-blind review process, the Technical Program Committee (TPC) met face-to-face to select papers to be included in the technical program based on over 250 reviews provided by 21 TPC members and 56 external reviewers. Finally, mthe committee accepted 17 papers to be presented in the symposium. These papers exhibit latest advancements in floorplanning, clocking, placement as well as routing, address challenges in advanced processes, identify opportunities in emerging technologies such as VeSFET, biochips, and e-beam, and offer new 3D solutions for physical design. The ISPD 2013 program is complemented by a ISPD keynote speech as well as a TAU/ISPD joint keynote speech, thirteen ISPD invited talks, and five TAU/ISPD joint invited talks, all of which are delivered by distinguished researchers in both industry and academia. Mr. Liam Madden, corporate vice president of FPGA development and silicon technology at Xilinx, will present in the keynote speech future directions of next generation 3D technologies. A commemorative session on Monday afternoon allows us to pay tributes to Professor Yoji Kajitani, one of the most influential pioneers in EDA and a great educator. His collaborators and former students will share with us Professor Kajitani's exceptional works in graph theory and their applications to rectangle packing as well as place-and-route, and his recent research in the area of beyond-die co-design and integration. Professor Kajitani will conclude the commemoration session with a talk about how the concept of permutation links the problems in channel routing, packing, placement, and various other PD areas. Other invited talks will be interspersed with the presentations of accepted papers. The topics covered include the impacts of electromigration on PD, debug, verification and test, lithography advancement and challenges in the advanced technology nodes, new breakthroughs in synchronous designs, system-level PD, and next generation device design and architectures. This year, we are happy to announce 3 joint sessions with the International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU). The joint sessions have extended the technical program of ISPD by half a day. The joint TAU/ISPD keynote, given by Dr. Ruchir Puri, IBM fellow and adjunct professor at Columbia University, showcases the challenges and opportunities in EDA for high-performance microprocessors. We are excited to have a joint TAU/ISPD session dedicated to both the ISPD's discrete gate sizing contest and TAU's variability aware timing analysis contest. On Wednesday afternoon, there is a special joint invited session on hierarchical PD and timing. Another special addition to ISPD's program in 2013 is the Expert Designer/User Session (EDS), which contains six invited presentations followed by a poster session. All EDS speakers are carefully selected to cover a wide range of PD topics. This brings the perspectives from the designer/user community to PD researchers, and encourages discussions and future research collaborations. Since 2005, ISPD has organized highly competitive contests to promote and advance research in placement, global routing, clock network synthesis, and discrete gate sizing. This year's discrete gate sizing contest, which includes realistic interconnect delay calculation, continues to attract a large number of participants from all over the world. The contest results will be announced by the ISPD Contest Chair on Wednesday morning. Continuing the tradition of all the past contests, a new large-scale real-world benchmark suite for gate sizing with discrete gate library will be released in ISPD website: http://www.ispd.cc