Three-dimensional capacitance modeling of advanced multilayer interconnection technologies

Abstract A recently developed 3-D capacitance calculator is used to achieve accurate values for dense multilevel VLSI in-terconnects embedded in both uniform and complex dielectric structures. Data are presented of total and crosstalkcapacitances versus wire pitch, width, thickness, and level spacing. As the dielectric structure will vary considerablywith process technology and metallurgy, impacts from a number of realistic possibilities are calculated. Leverageis provided by low-permittivity dielectrics, but often processes involve additional materials that may incur largepenalties. Progress in capacitance and very high-speed waveform measurements for multilayer on-chip interconnectsis outlined. Introduction Driven by ever-increasing circuit density required for advanced logic and memory chips, electrical performanceof the on-chip wiring becomes increasingly significant. Increasing the level of integration brings more circuit inter-connections onto the chip, and although the device and wire dimensions are scaled down, the chip size is actuallyincreasing. For long lines the parasitic impedances will thus increase, and the time is rapidly approaching whenon-chip wiring delays will reach 50% of total circuit delay for the fastest logic chips. The wiring capacitance alreadyrepresents a major circuit load which will increase as longer lines with higher aspect ratios (to limit resistance andcurrent density) are required. Capacitively coupled noise between neighboring lines will become very severe, re-quiring design changes in layout and/or deliberate degradation of circuit performance to meet the noise margins. Inorder to mediate some of the problems associated with increased wiring density, increasing numbers of wiring levelsare being employed'. both for increased connectivity and to allow more volume per wire and space, thus decreasingRC parasitics. This work addresses these concerns as they relate to the Back End of the Line (BEOL), or on-chipinterconnection structure. In particular, the capacitances are studied for global (long-run) lines in a fully planarizedmultilevel wiring structure with design rules in the single- and submicron regime. Data are presented for total andcrosstalk capacitances versus wire pitch, width, thickness, and level spacing. These results are general and scalableto other dimensions. The dielectric structure will vary considerably with process technology and metallurgy, and soimpacts from a number of realistic possibilities are calculated, and this allows further extendability of these calcu-lations. The leverage of low-permittivity dielectrics is clear for decreasing total and coupling capacitances, but real-istic processes involve additional materials, many of which have higher dielectric constants. It will be shown thateven very thin layers of these may incur disproportionately large penalties in capacitance. Finally, a brief descriptionis given of the measurement capabilities which have been established to verify both the modeling and process tech-nology for advanced BEOL structures in high-speed environments.From a fabrication standpoint, new difficulties arise in addition to lithography and patterning as groundrules arereduced. Metal liftoff becomes unreliable for micron and submicron lines, so some form of dry etching (RIE) mustbe employed, and a process must be developed for aluminum alloys which are difficult to etch2. Increased aspectratios are required to limit resistance and current density in the conductors and provide more tolerance for con-necting between vertical wiring levels; this places even more demand on the etching for vertical sidewalls, reasonableetch rates and selectivity, and removal of debris. Switching from Al-based metallurgy to the higher-conductivitymetals (Au, Cu, Ag) is desireable from an electrical standpoint, but these are difficult to RIE pattern, while poly-imides, desireable as low-dielectric constant insulators, may absorb etch gases and cause subsequent corrosion. Al-ternate to etching the metal, the insulator can be patterned and the slots and holes refilled with the metal. For highaspect ratios this requires a process more conformal than evaporation or even sputtering, such as plating orCVD.A number of reports on CVD and plating processes for Au and Cu have been reported37.Patterning the dielectric rather than the metal necessarily leaves any required etch-stop layers embedded in thedielectric, whereas in the former case the etch-stop may be removed from between the metal lines after they aredefmed. These etch-stop layers may be necessary for additional process reasons, such as a mask for the dielectric,