Verilog HDL: Digital Design and Modeling

PREFACE INTRODUCTION History of HDL Verilog HDL IEEE Standard Features Assertion Levels OVERVIEW Design Methodologies Modulo-16 Synchronous Counter Four-Bit Ripple Adder Modules and Ports Designing a Test Bench for Simulation Construct Definitions Introduction to Dataflow Modeling Two-Input Exclusive-OR Gate Four 2-Input AND Gates With Delay Introduction to Behavioral Modeling Three-Input OR Gate Four-Bit Adder Modulo-16 Synchronous Counter Introduction to Structural Modeling Sum-of-Products Implementation Full Adder Four-Bit Ripple Adder Introduction to Mixed-Design Modeling Full Adder Problems LANGUAGE ELEMENTS Comments Identifiers Keywords Bidirectional Gates Charge Storage Strengths CMOS Gates Combinational Logic Gates Continuous Assignment Data Types Module Declaration MOS Switches Multiple-Way Branching Named Event Parameters Port Declaration Procedural Constructs Procedural Continuous Assignment Procedural Flow Control Pull Gates Signal Strengths Specify Block Tasks and Functions Three-State Gates Timing Control User-Defined Primitives Value Set Data Types Net Data Types Register Data Types Compiler Directives Problems EXPRESSIONS Operands Constant Parameter Net Register Bit-Select Part-Select Memory Element Operators Arithmetic Logical Relational Equality Bitwise Reduction Shift Conditional Concatenation Replication Problems GATE-LEVEL MODELING Multiple-Input Gates Gate Delays Inertial Delay Transport Delay Module Path Delay Additional Design Examples Iterative Networks Priority Encoder Problems USER-DEFINED PRIMITIVES Defining a User-Defined Primitive Combinational User-Defined Primitives Map-Entered Variables Sequential User-Defined Primitives Level-Sensitive User-Defined Primitives Edge-Sensitive User-Defined Primitives Problems DATAFLOW MODELING Continuous Assignment Three-Input AND Gate Sum Of Products Reduction Operators Octal-To-Binary Encoder Four-To-One Multiplexer Four-To-One Multiplexer Using The Conditional Operator Four-Bit Adder Carry Lookahead Adder Asynchronous Sequential Machine Pulse-Mode Asynchronous Sequential Machine Implicit Continuous Assignment Delays Problems BEHAVIORAL MODELING Procedural Constructs Initial Statement Always Statement Procedural Assignments Intrastatement Delay Interstatement Delay Blocking Assignments Nonblocking Assignments Conditional Statement Case Statement Loop Statements For Loop While Loop Repeat Loop Forever Loop Block Statements Sequential Blocks Parallel Blocks Procedural Continuous Assignment Assign ... Deassign Force ... Release Problems STRUCTURAL MODELING Module Instantiation Ports Unconnected Ports Port Connection Rules Design Examples Gray-To-Binary Code Converter BCD-To-Decimal Decoder Modulo-10 Counter Adder/Subtractor Four-Function ALU Adder and High-Speed Shifter Array Multiplier Moore-Mealy Synchronous Sequential Machine Moore Synchronous Sequential Machine Moore Asynchronous Sequential Machine Moore Pulse-Mode Asynchronous Sequential Machine Problems TASKS AND FUNCTIONS Tasks Task Declaration Task Invocation Functions Function Declaration Function Invocation Problems ADDITIONAL DESIGN EXAMPLES Johnson Counter Counter-Shifter Universal Shift Register Hamming Code Error Detection and Correction Booth Algorithm Moore Synchronous Sequential Machine Mealy Pulse-Mode Asynchronous Sequential Machine Mealy One-Hot Machine BCD Adder/Subtractor BCD Addition BCD Subtraction Pipelined RISC Processor Instruction Cache Instruction Unit Decode Unit Execution Unit Register File Data Cache RISC CPU Top System Top Problems APPENDIX A Event Queue Event Handling for Dataflow Constructs Event Handling for Blocking Assignments Event Handling for Nonblocking Assignments Event Handline for Mixed Blocking and Nonblocking Assignments APPENDIX B Verilog Project Procedure APPENDIX C Answers to Selected Problems Overview Language Elements Expressions Gate Level Modeling User-Defined Primitives Dataflow Modeling Behavioral Modeling Structural Modeling Tasks and Functions Additional Design Examples INDEX