VLSI Architectures for Modern Error-Correcting Codes

Preface List of Figures List of Tables Finite Field Arithmetic Definitions, Properties and Element Representations Finite Field Arithmetic Multiplications Using Basis Representations Inversions Using Basis Representations Mapping Between Finite Field Element Representations Mapping Between Standard Basis and Composite Field Representations Mapping Between Power and Standard Basis Representations Mapping Between Standard and Normal Basis Representations VLSI Architecture Design Fundamentals Definitions and Graph Representation Pipelining and Retiming Parallel Processing and Unfolding Folding Root Computations for Polynomials Over Finite Fields Root Computation for General Polynomials Root Computation for Linearized and Affine Polynomials Root Computation for Polynomials of Degree Two or Three Reed-Solomon Encoder and Hard-Decision and Erasure Decoder Architectures Reed-Solomon Codes Reed-Solomon Encoder Architectures Hard-Decision Reed-Solomon Decoding Algorithms and Architectures Peterson-Gorenstein-Zierler Algorithm Berlekamp-Massey Algorithm Reformulated Inversionless Berlekamp-Massey Algorithm and Architectures Syndrome, Error Location, and Magnitude Computation Architectures Pipelined Decoder Architecture Error-and-Erasure Reed-Solomon Decoders Algebraic Soft-Decision Reed-Solomon Decoder Architectures Algebraic Soft-Decision Decoding Algorithms Re-Encoded Algebraic Soft-Decision Decoder Re-Encoding Algorithms and Architectures Interpolation Algorithms and Architectures Kotter's Interpolation Algorithm and Architectures Lee-O'Sullivan Interpolation Algorithm and Architectures Kotter's and Lee-O'Sullivan Interpolation Comparisons Factorization Algorithm and Architectures Prediction-Based Factorization Architecture Partial-Parallel Factorization Architecture Interpolation-Based Chase and Generalized Minimum Distance Decoders Interpolation-Based Chase Decoder Backward-Forward Interpolation Algorithms and Architectures Eliminated Factorization Polynomial Selection Schemes Chien-Search-Based Codeword Recovery Systematic Re-Encoding Generalized Minimum Distance Decoder Kotter's One-Pass GMD Decoder Interpolation-Based One-Pass GMD Decoder BCH Encoder and Decoder Architectures BCH Codes BCH Encoder Architectures Hard-Decision BCH Decoding Algorithms and Architectures Peterson's Algorithm The Berlekamp's Algorithm and Implementation Architectures 3-Error-Correcting BCH Decoder Architectures Chase BCH Decoder Based on Berlekamp's Algorithm Interpolation-Based Chase BCH Decoder Architectures Binary LDPC Codes and Decoder Architectures LDPC Codes LDPC Decoding Algorithms Belief Propagation Algorithm Min-Sum Algorithm Majority-Logic and Bit-Flipping Algorithms Finite Alphabet Iterative Decoding Algorithm LDPC Decoder Architectures Scheduling Schemes VLSI Architectures for CNUs and VNUs Low-Power LDPC Decoder Design Non-Binary LDPC Decoder Architectures Non-Binary LDPC Codes and Decoding Algorithms Belief Propagation Decoding Algorithms Extended Min-Sum and Min-Max Algorithms Iterative Reliability-Based Majority-Logic Decoding Min-Max Decoder Architectures Forward-Backward Min-Max Check Node Processing Trellis-Based Path-Construction Min-Max Check Node Processing Simplified Min-Max Check Node Processing Syndrome-Based Min-Max Check Node Processing Basis-Construction Min-Max Check Node Processing Variable Node Unit Architectures Overall NB-LDPC Decoder Architectures Extended Min-Sum Decoder Architectures Extended Min-Sum Elementary Step Architecture Trellis-Based Path-Construction Extended Min-Sum Check Node Processing Iterative Majority-Logic Decoder Architectures IHRB Decoders for QCNB-LDPC Codes IHRB Decoders for Cyclic NB-LDPC Codes Enhanced IHRB Decoding Scheme and Architectures Bibliography Index