Synthesis of blind source separation algorithms on reconfigurable FPGA platforms

ABSTRACT Recent advances in intelligence technology have boosted the development of micro- Unmanned Air Vehicles(UAVs) including Sliver Fox, Shadow, and Scan Eagle for various surveillance and reconnaissance applications.These ao rdable and reusable devices have to t a serie s of size, weight, and power constraints. Cameras usedon such micro-UAVs are therefore mounted directly at a xed angle without any motion-compensated gimbals.This mounting scheme has resulted in the so-called jitter eect in which jitter is dened as sub-pixel or smallamplitude vibrations. The jitter blur caused by the jitter eect needs to be corrected before any other processingalgorithms can be practically applied. Jitter restoration has been solved by various optimization techniques,including Wiener approximation, maximum a-posteriori probability (MAP), etc. However, these algorithmsnormally assume a spatial-invariant blur model that is not the case with jitter blur. Szu et al. developed asmart real-time algorithm based on auto-regression (AR) with its natural generalization of unsupervised ar-ticial neural network (ANN) learning to achieve restoration accuracy at the sub-pixel level. This algorithmresembles the capability of the human visual system, in which an agreement between the pair of eyes indicatessignal, otherwise, the jitter noise. Using this non-statis tical method, for each single pixel, a deterministic blindsources separation (BSS) process can then be carried out independently based on a deterministic minimum of theHelmholtz free energy with a generalization of Shannons information theory applied to open dynamic systems.From a hardware implementation point of view, the process of jitter restorationof an image using Szus algorithmcan be optimized by pixel-based parallelization. In our previous work, a parallelly structured independent com-ponent analysis (ICA) algorithm has been implemented on both Field Programmable Gate Array (FPGA) andApplication-Specic Integrated Circuit (ASIC) using standard-height cells. ICA is an algorithm that can solveBSS problems by carrying out the all-order statistical, decorrelation-based transforms, in which an assumptionthat neighborhood pixels share the same but unknown mixing matrix A is made. In this paper, we continueour investigation on the design challenges of rmware approaches to smart algorithms. We think two levels ofparallelization can be explored, including pixel-based par allelization and the parallelization of the restorationalgorithm performed at each pixel. This paper focuses on the latter and we use ICA as an example to explainthe design and implementation methods. It is well know n that the capacity constraints of single FPGA havelimited the implementation of many complex algorithms including ICA. Using the recongurability of FPGA,we show, in this paper, how to manipulate the FPGA-based system to provide extra computing power for theparallelized ICA algorithm with limited FPGA resources. The synthesis aiming at the pilchard re-congurableFPGA platform is reported. The pilchard board i s embedded with single X ilinx VIRTEX 1000E FPGA andtransfers data directly to CPU on the 64-bit memory bus at the maximum frequency of 133MHz. Both thefeasibility performance evaluations and experimental results validate the eectiveness and practicality of thissynthesis, which can be extended to the spatial-variant jitter restoration for micro-UAV deployment.Keywords: jitter restoration, micro-UAV, FPGA, Re-congurable, Xilinx