A quantitative defense framework against power attacks on multi-tenant FPGA

The development and application of various Machine Learning algorithms demand high computing capabilities. As a result, field-programmable gate arrays (FPGAs) are being used as hardware accelerators, and more recently deployed in cloud servers by leading vendors to provide reconfigurable computing capabilities. Although such cloud-FPGA platform is bringing significant performance benefits, it also creates a unique attack surface where the hardware resources of an FPGA are shared by multiple users. Power attack targeting the power distribution network (PDN) is among the most threatening ones against multi-tenant FPGAs. In such attack, the malicious users leverage power plundering circuits to manipulate the PDN and cause a voltage drop, thus injecting timing faults to the victim applications. Besides, since most cloud-FPGAs are being used for computing-intensive tasks that consume a large amount of power, therefore, typical FPGA applications may still encounter timing faults even without power attacks. Unlike power attacks, we classify this problem as a reliability issue. To comprehensively mitigate the reliability and security issues caused by a non-malicious or malicious voltage drop, in this paper, we introduce a quantitative defense framework. The proposed framework provides a two-fold defense method: static and dynamic frequency scaling, to manage the clock frequency of the FPGA applications. The frequency scaling strategy is based on quantifying the relationship between the adversarial circuit and the voltage drop that can be injected. The proposed framework provides a delay-frequency pair table, which can be pre-configured to control the run-time clock frequency of the FPGA application. For practical applicability, the proposed framework utilizes the existing on-chip clock management components like mixed-model clock manager (MMCM) and phase-locked loop (PLL). Additionally, to assist the frequency scaling, we propose an on-chip sensor that can accurately quantify the real-time voltage drop. The performance of the proposed framework is validated with open-source benchmarks and real-world Advanced Encryption Standard (AES) implementation on an Xilinx NetFPGA. The experimental results demonstrate the effectiveness of the proposed method in mitigating security and reliability issues caused by a voltage drop. To comprehensively mitigate the reliability and security issues caused by a non-malicious or malicious voltage drop, in this paper, we introduce a quantitative defense framework. The proposed framework provides a two-fold defense method: static and dynamic frequency scaling, to manage the clock frequency of the FPGA applications. The frequency scaling strategy is based on quantifying the relationship between the adversarial circuit and the voltage drop that can be injected. The proposed framework provides a delay-frequency pair table, which can be pre-configured to control the run-time clock frequency of the FPGA application. For practical applicability, the proposed framework utilizes the existing on-chip clock management components like mixed-model clock manager (MMCM) and phase-locked loop (PLL). Additionally, to assist the frequency scaling, we propose an on-chip sensor that can accurately quantify the real-time voltage drop. The performance of the proposed framework is validated with open-source benchmarks and real-world Advanced Encryption Standard (AES) implementation on an Xilinx NetFPGA. The experimental results demonstrate the effectiveness of the proposed method in mitigating security and reliability issues caused by a voltage drop.