Study of thread-level parallelism in a video encoding application for chip multiprocessor design

StudyofThreadLevelParallelisminaVideoEnco dingApplicationforChipMultipro cessorDesignEric Deb es,Greg KaineMediaSystems,Micropro cessorResearch,Intel Labs2200 Mission College Blvd.Santa Clara,CA95052ABSTRACTInmedia applicationsthere isahighlevel ofavailable thread level parallelism (TLP).thispap er we studytheintra TLP in a video enco der.We showthat a well-distributed highly optimized enco der running on a symmetricmultipro cessor (SMP) system can run 3.2 faster on a 4-way SMP machine than on a single pro cessor.The multi-threaded enco der running on an SMP system is then used to understand the requirements of a chip multipro cessor(CMP)architecture,whichisonep ossiblehitectural directiontob etterexploitTLP.Intheframework ofthisstudy,weuseasoftareapproachtoevaluatethedataobeteenpro cessors forvideoenco derrunningonan SMP system.An estimation ofthe dataow is done withL2 cache miss eventcounters using IntelrVTuneTMp erformance analyzer.The exp erimental measurements are compared to theoretical results.Keywords:Chip Multipro cessor, Symmetric Multipro cessor, Bandwidth, L2 Cache misses, Video Enco ding, Thread-Level Parallelism, Load Balancing1.INTRODUCTIONComplexmultimediaapplicationshaveahighdegreeofailablethreadlevelparallelismthatisnoterywellexploitedbycurrentpro cessors.First,eachmediastreamcanbeenco dedseparatelyanddi erenthreadsareusually synchronized with communication layer threads.Wecall thistyp e of parallelism inter thread level parallelism(inter-TLP). Even though it is the most widely used TLP in software implementations, it do es not provide a go o dload balancing.Therefore it is interesting to lo ok at the parallelism available inside each media or communicationfunction.Wecallthistyp eofparallelismintrathreadlevel(intra-TLP).Inpap erwstudytheintra-TLP in a video enco der and the asso ciated dataowbetween pro cessors.2.METHODOLOGYIn the last few decades, computer architecture has evolved to exploit instruction and data-level parallelism.Recentworkshothatitisdiculttoexp ectmuchmoregainfromthiskindofparallelism.Thereforefuturegenera-tionofpro cessorarchitectureswilladdsupp orttoexploitthreadlevelparallelism.Manyhave b een recently prop osed to exploit this typ e of parallelism, ranging from clustered VLIW architectures1to chipmultipro cessor (CMP)2or simultaneous multithreading (SMT)34architectures.Inthispap erwe consider a CMParchitecture with four sup erscalar pro cessors with theirprivate level 1cache and shared level 2 caches.This kindof architecture can eciently exploit inter TLP, b ecause of its coarse granularity.However it less obvious whetheritcan takeadvantageof intra TLP.To design CMParchitectures thatare ecientformedia andcommunicationapplications, the crucial parameters to determine are the computational requirements for each pro cessor, the band-width needed b etween pro cessors and the cache requirements.To understand the bandwidth requirements, we studythe communication b etween pro cessors when running a multithreaded video enco der on a symmetric multipro cessorsystem comp osed of four PentiumrIII.Followingthecurrenttrendincircuitdesign,itwillbep ossiblelessthan10yearsfromnowtotegratefour pro cessors on a single chip with their private 2MB L1 cache and a 10MB shared L2 cache.This con gurationcorresp onds to a current4-way SMP system,withprivate 2MB L2 cache and a shared RAM,as shown in Fig.1.Indeed the 10MB shared L2 is large enough to contain the same working set currently saved in the main memory.Thereforethecurrentdataowevaluationforavideoenco derrunningon4-wySMPsystemcanbeusedto