Primitives for the CMS Cathode Strip Muon Trigger

The endcap muon detector for CMS uses Cathode Strip Chambers (CSCs) to deliver precise muon position and timing information in a high background rate environment[1]. Trigger electronics for this system need to reliably identify the bunch crossing in spite of drift times spanning several crossings, and need to precisely measure the muon bend plane coordinate in each station to allow momentum measurement in spite of limited magnetic bending power. Prototypes were placed in test beams at CERN in the summers of 1998 and 1999. Results from these tests on pattern identification, timing efficiency, and spatial resolution are presented. Plans for future developments are also described. 1. CMS ENDCAP MUON CSC SYSTEM Before discussing the details of the electronics, it is useful to review the general layout of the Cathode Strip Chamber system used in the CMS Endcap Muon detector. This detector is planned for 4 stations, however, at present construction money for only 3 stations is assured. There are 432 CSC chambers, each 10or 20degree trapezoidal 6-layer chambers in the 3-station detector as shown in Figure 1. Figure 1 CSC stations for one of the CMS endcaps. The iron disks between the stations are not shown. In each of the six layers of a chamber, some 1000 anode wires supply gas amplification. Charges on orthogonal radial strips are read by precision electronics and are used offline for precision position measurement in the solenoid bend plane, i.e. the φ coordinate. Since the wire signals are larger, they are amplified by faster electronics and are mainly used to indicate the 25ns LHC bunch crossing from which a muon came. 2. CSC TRIGGER PRIMITIVES Simulations indicate that at maximum luminosity, several background clusters exist within each CSC at any given time. To reduce the otherwise huge background rate, CSC trigger primitives are formed from the spatial coincidence of clusters in the 6 layers of the chamber. The cathode strip cluster position is determined for triggering to one-half of a strip width in each layer[2]. This is done with a 16-channel 'comparator' ASIC that inputs amplified and shaped signals and compares the charges on all adjacent and next-toadjacent strips. If a strip charge is found to be larger than those on its neighbors, a hit is assigned to the strip. Also, comparison of left versus right neighbour strip charges allows assignment of the hit to the right or left side of the central strip, effectively doubling the resolution. The six layers are then brought into coincidence in 'Local Charged Track' (LCT) pattern circuitry (see Figure 2) to establish position of the muon to an RMS accuracy of 0.10-0.15 strip widths. Strip widths range from 6-16mm. Because of the slow 150ns rise-time of the cathode amplifier/shapers, the cathodes cannot uniquely identify the bunch crossing. The anode wires are ganged 10-15 to a group, and their signals are fed into amplifier/constant-fraction discriminators. Since the drift time can be as large as 50ns, a multi-layer coincidence technique in the anode LCT pattern circuitry is used to identify the bunch crossing. For each spatial pattern of anode hits, a low coincidence level, typically 2 layers, is used to establish timing, whereas a high coincidence level, typically 4 layers, is used to establish the existence of a muon track. The algorithm is illustrated in Figure 2. Figure 2 Algorithms for trigger primitives for cathodes and anode planes of CSC chambers. 3. 1998 PROTOTYPES AND RESULTS Electronics prototypes were tested on a full-size prototype of the largest CSC chamber in the summer of 1998 at CERN. Tests were done first at the H2 beam line, where a Silicon beam telescope was used for resolution studies. Later tests were done at the GIF (Gamma Irradiation Facility), where LHC-like backgrounds were provided by an intense gamma source. The chamber is shown at the H2 beam line in Figure 3. Figure 3 CSC chamber in the CERN H2 beam line during Summer 1998. 3.1 Cathode Comparator ASIC Tests The 16-channel cathode comparator ASICs that were tested during summer 1998 had 32 half-strip output bits. Six of these chips were mounted on a 96-channel comparator board (Figure 4) that attached directly through connectors to the cathode front-end board. The 192 half-strip bits were converted from TTL levels to differential LVDS and 96 of these signals were driven on cables to a cathode LCT card in a CAMAC crate, where they were recorded. Figure 4 Comparator ASICs (center) mounted on the comparator board used in 1998 tests. The efficiency of the comparator ASICs for identifying the correct half-strip was determined in two ways. First, the half-strip bits were compared to bits predicted by the precision charge determination of the front-end DAQ cards[3]. These cards employ switched-capacitor arrays (SCAs) for charge storage, and ADCs for digitization. Typical noise levels on the DAQ data were 1.6fC (1.6mV after the amplifier/shapers), while typically the total cathode charge read out was 100fC. The efficiency was found to be 90.4±0.2% for exact half-strip match, while a match window of ±1 half-strips yielded an efficiency of 98.3±0.1%. The second way to determine the comparator match efficiency is less biased but gives lower statistics. This method uses the precision DAQ data to track muons through the chamber, leaving out one layer (#3) from the fit. The extrapolated position in this layer is then compared to the half-strip bit found by the comparator ASIC. By this method, the efficiency for exact match is measured to be 88.2±0.7% for exact half-strip match, while a widened match window of ±1 half-strips yields an efficiency of 94.9±0.4%. 3.2 Cathode LCT Tests The half-strip bits found by the comparator ASICs were sent to the cathode LCT card (Figure 5), which identified the multi-layer patterns of valid muon trajectories. A mezzanine card converted LVDS signals to TTL levels. These signals were distributed by a "front" Altera 10K50 FPGA to Cypress 128Kx8bit SRAMs, which found the patterns, while a "rear" Altera 10K20 FPGA collected the patterns (if any) found by the SRAMs and selected the best according to pattern number. Higher numbers corresponded to larger numbers of hit layers and straighter tracks. The CAMAC interface was implemented in another Altera 10K20 FPGA. Output trigger information was fed through a National Instruments Channel-Link to a "Trigger Motherboard" which sorted LCTs in the case of multiple candidates, and performed a time coincidence between cathode LCTs and anode LCTs. Figure 5 The cathode LCT card on an extender card. Patterns having four or more hits corresponding to a straight line within a particular angular range were allowed. An additional feature of the cathode LCT card was the ability to trigger on high-angle tracks, which could be very low-momentum tracks in the case of CMS. This was done by grouping the half-strips 4:1 into di-strip units. At 40 MHz, the cathode LCT module searched for low-Pt patterns. When such a pattern was found, four subsequent clock cycles followed in which the module searched for patterns using half-strip bits. If di-strip patterns and half-strip were both found, the half-strip patterns were always favoured, except in the case of a 6-hit di-strip pattern and a 4-hit half-strip pattern. The efficiency of the cathode LCT card for identifying muons was measured in one case by comparison with the precision DAQ data, and in the other by comparison to external muon tracking provided by a Silicon telescope. The position reported by the cathode LCT card corresponded to the track position at chamber layer 3. When DAQ data was found in Layer 3, the position of the cathode LCT was compared to the Layer 3 cluster center. Of these events, 95% were found as half-strip patterns, 4% were found as di-strip patterns only, and 0.8% were not found by the cathode LCT card. The deviations in position between the DAQ data and the cathode LCT trigger are shown in Figure 6, in halfstrip units. Figure 6 Position resolution of cathode LCT as compared to DAQ data: on top for half-strip patterns, on bottom for distrip patterns found. The "overflow" bin is for missing cathode LCTs. The second method for estimating the efficiency, as well as resolution, of the cathode LCT card, is by using the Silicon tracking telescope. This telescope defines tracks to an accuracy of about 100 μm after 100cm extrapolation to the chamber. Halfstrip cathode patterns were found for 96% of the tracks, with position residuals (Figure 7) very close to a box distribution onehalf strip wide. Another 3.7% of tracks were found as di-strip patterns by the cathode LCT logic. The positions of these tracks in di-strip units (Figure 8), shows that di-strip patterns occur at the boundaries between half-strips, where the half-strip pattern tables were not optimally tuned. Another 0.25% of tracks were not found by the cathode LCT logic. The tracks for these events point mainly to the boundaries between di-strip units, where again the pattern tables were not optimally tuned. The net cathode LCT efficiency is found to be 99.75±0.04% in this study. Figure 7 Residuals from Silicon-based tracking versus the cathode LCT half-strip pattern position. Figure 8 Positions of Silicon-based tracks for muons found as di-strip patterns but not half-strip patterns.