Co-simulations of electromagnetic and thermal effects in electronic circuits using non-conformal numerical methods

Advances in interconnect technologies, such as the increase of the number of metal layers and 3-D stacking technique, have paved the way for higher functionality and superior performance while reducing size, power, and cost in today's integrated circuits and package products. With the increase of clock frequency and edge rates as well as the continuously downscaling of feature size and 3-D interconnect technologies in high-speed systems, signal integrity (SI) effects such as signal delay, reflection, attenuation, dispersion and crosstalk have become one of the dominant factors in current deep sub-micrometer CMOS technologies limiting overall performance of high-speed systems.Another major difficulty is the power integrity (PI) issue. For example, IR drop is caused by the finite resistivity (R) of metals and current (I) drawn off from the power/ground planes. Chip designs are susceptible to IR drop, especially when the integrated circuit (IC) supply voltage Vdd decreases with the scaling of silicon processes. IR drop is proportional to the resistance of the power/ground plane. When the resistance of power/ground plane increases, with the shrinking of complex geometries, the IR drops will in turn increase as well. To further confound the difficult issue, the rise of the thermal temperature due to the current carrying interconnects also has tremendous impact on the IC performance and reliability. Current flow in a VLSI interconnect can cause a power dissipation, which is referred to as Joule heating or self-heating. The Joule heating effects are becoming increasingly significant with the shrinking scale of silicon process because of the increase of on-chip power density, inclusion of more metal layers with higher densities, and the use of dielectric materials with lower thermal conductivities. Subsequently, the temperature effects on the electrical performance of 3D systems should be carefully considered as well in the electrical designs.Unfortunately, almost all practical SI and PI problems are multi-physics in nature, and various physical phenomena are usually interacting and coupling to each other. For instance, the resistivity of most conducting metals increases linearly with the increases of the surrounding temperature resulting from the Joule heating by electric currents flowing through the conductors. Therefore, in order to accurately characterize the performance of high power integrated circuits (ICs), packages and printed circuit boards (PCBs), it is essential to account for both electric and thermal effects and the intimate couplings between them.In this paper, we propose to use non-conformal, non-overlapping domain decomposition methods (DDMs) for the signal integrity analyses and thermal-aware DC IR drop co-analysis of high-power IC-Package-PCBs. The proposed DDM starts by partitioning the composite device into inhomogeneous sub-regions with temperature dependent material properties. Subsequently, each sub-domain is meshed independently according to its own characteristic features. As a result, the troublesome mesh generation task for complex ICs can be greatly subdued. Moreover, the proposed thermal-aware DC IR drop co-analysis applies the non-conformal DDMs for both conduction and steady state heat transfer analyses with a two-way coupling between them. Furthermore, we extend the non-conformal DDM to study transient thermal temperature distribution within complex ICs. Numerical examples, including an IC package and an IC-Package-PCB, demonstrate the flexibility and potentials of the proposed non-conformal DDMs for SI analyses and thermal-aware DC IR-drop co-analysis.