The impact of MOSFET technology evolution and scaling on electrostatic discharge protection

Abstract MOSFET (metal-oxide silicon field effect transistor) evolution and technology scaling impacts electrostatic discharge (ESD) protection networks, design and strategy. The continous evolution of semiconductor processing forces new issues to arise for each technology generation and the evolution of MOSFET structures in each generation requires re-addressing of the scaling implications on ESD robustness. This paper addresses the impact of semiconductor technology evolution and scaling of the epitaxial film, well design, isolation technology, MOSFET junctions, silicides, and interconnects on ESD robustness. The scaling of the epitaxial film thickness and p++ vs p− substrate influences the ESD robustness of n-channel MOSFET and diode-based ESD protection networks. ESD diode elements show a 2× to 3× improvement in thin p− epitaxy on a p++ wafer compared to p−substrates. The evolution from diffused wells to MeV-implanted retrograde well designs have shown that the parasitic vertical bipolar transistor plays a lesser role in ESD protection networks compared to the diode action. A 3× HBM (human body model) ESD improvement is demonstrated using advanced high dose MeV retrograde well implants. Isolation technology has an influence on the high voltage electrical parametrics, lateral parasitics, thermal transport and semiconductor process integration with the MOSFET junction and silicide film. The transition from LOCOS to STI (shallow trench isolation) significantly altered the electrical parametrics, failure mechanisms, and ESD networks. The MOSFET-junction evolution from Ldd, dual-Ldd, abrupt junctions to “extension implants” and how this influenced integration and ESD robustness is discussed. MOSFET junctions, salicide, and STI integration issues, such as STI pull-down, can influence the ESD robustness of ESD diode structures. Althernative salicide processes (e.g. cobalt), deep B11 implants and novel poly-silicon-bound diode structures demonstrate 3× improvement in HBM ESD robustness. As technology transitions from aluminum- to copper-based interconnect systems, interconnect wire (2× improvement) and via (3× improvement) ESD improvements are demonstrated. As a result of power supply scaling, the impact of technology scaling on ESD networks, peripheral I/O driver circuits and receiver networks, and how it influences the ESD protection of advanced semiconductor chips is shown. Power-supply scaling, noise issues and multichip systems has led to increasing complexity and importance of sequence-independent ESD networks, ESD networks between power supplies and ESD power clamps. Receiver and I/O driver designs have also evolved due to the MOSFET dielectric scaling and ESD robustness requirements. Technology generation evolution of peripheral driver circuits evolution demonstrates the need for local resistor ballasting of driver circuits. With MOSFET scaling, receiver circuit pass transistors, keeper feedback and zero-Vt devices introduce new ESD issues and receiver design complexity. MOSFET scaling requires ESD power clamps across core and peripheral supplies to reduce the current loop impedance for high frequency applications. MOSFET scaling also has led technology to have a future interest in high-frequency semiconductor devices, such as rf-CMOS, silicon-on-insulator, and SiGe-based devices. Novel SOI ESD networks, such as polysilicon-bound diodes and body- and gate-coupled SOI ESD networks, demonstrate excellent ESD results in advanced CMOS-on-SOI technologies.