Si nanowire MOSFET with gate-all-around electrode

Beyond 2011, when the channel length of a MOSFET transistor is projected to be 16 nm, effective scaling of classical planar bulk MOSFETs is expected to come to an end. Below 16 nm channel length, achieving adequate electrostatic control of short channel effects poses the most serious challenge. Non-classical double-gate, ultrathin-body transistors offer to minimize short-channel effects and allow for more aggressive scaling. Several three-dimensional (3-D) multigate structures such as FinFET, Trigate, MIGFET, ITFET [1] have been demonstrated with good electrical characteristics down to gate lengths of 12 nm. It is known from theoretical investigations that the ultimate MOSFET is realized as a nanowire (NW)-MOSFET transistor with a gate-all-around gate electrode shown in Fig. 1. In this work, a top-down approach has been adopted for the first-time to pattern single-crystalline Si NW on SOI substrates using planar technology processes. The two critical parameters of the nanowire are defined by the thickness of Si active layer and the width of a masking spacer, see Fig. 2. The NW has an elliptical cross-section having a semimajor axis less than 150 nm and the semiminor axis depending on process conditions. A complete mask set has been developed for the NW-MOSFET defining mesa island on Si and channel area of length between 5–20 µm, along with the location of the critical spacer deposition, see Fig.3. An additional mask has been fabricated to obtain channel length of about 800 nm using i-line photolithography. Solid source diffusion of phosphorus is being used to dope source/drain regions, providing at the same time a PSG glass masking layer to protect source/drain regions during subsequent process steps. A masking nitride layer of 200 nm proved sufficient to protect channel region from P doping, see Fig. 4. Because of the thinness of our active Si layer of only 88nm, our structures lend themselves to study phosphorus diffusion in two dimensional membranes and one-dimensional nanowires. Deposition and reactive ion etch recipes with appropriate selectivities have been developed to form a masking spacer of widths down to 150 nm range and to pattern the Si nanowire. Fig.5 shows an SEM picture of sub-200 nm twin oxide spacers. The spacer width can be modified by varying the initial oxide thickness deposited over the nitride mask. After the patterning of the active Si layer, the buried oxide layer BOX is underetched to provide all around access to the suspended Si nanorod. In parallel to the Si NW-MOSFET flow, the gate stack electrode has been developed using atomic layer deposition (ALD) method. Because of its nearly perfect uniformity, ALD is ideally suited to deposit a high-k dielectric HfO 2 of 25 A–40A shown in Fig.5 followed by Pt metal deposition also by ALD. Pt deposition on planar surfaces results in grain formation as seen in Fig.6. The roughness of the Pt surface could be controlled within 1 nm range. Such HfO 2 and Al 2 O 3 ALD high-k gate stacks have been applied successfully to grown Si nanowires and have been integrated subsequently into a Si nanowire non-volatile memory (NVM) process [2]. The present NW MOSFET structure can be used for NVM device applications with a gate-all-around gate structure. Currently, similar efforts are expended to fabricate a Ge NW MOSFET. Epitaxial deposition of high mobility III–V semiconductors on Si and Ge nanowires will be pursued in future work.