Levo - A scalable processor with high IPC

UHT, MORANO, KHALAFI & KAELI 2 description of the microarchitecture, a description of the physical layout (a floorplan), and many new simulation results. The paper is organized as follows. In Section 2 we review major impediments to high IPC realization. Section 3 provides the Levo logical description, and discusses Levo’s solutions to the high IPC problems. Other implementation issues are addressed in Section 4. Section 5 describes the physical operation of Levo and presents a possible Levo single-chip floorplan. In Section 6 we discuss other related work. Section 7 gives our experimental methodology, while Section 8 presents and discusses our simulation results. We conclude in Section 9. 2. High IPC Problems There are three major impediments to high IPC: 1) high and/or unscalable hardware cost; 2) degradation of (increase in) cycle time, negating IPC performance gains; and 3) lack of high-IPC extraction methods. Prior work has shown that there is much ILP (Instruction Level Parallelism) in typical GP code [18]. Large instruction windows and reorder buffers are necessary to realize a fraction of this ILP [37]; these structures greatly exacerbate the first two high-IPC impediments. We define “cost” as the transistor count or equivalent chip area. Note that this is not the same as “complexity,” a measure of the randomness of a system’s design. The prior art tends to use complex structures; Levo uses simple ones, easier to lay out, etc. A system is said to be “scalable” if its cost grows linearly or less with an increase in the number of Processing Elements or other key elements. 2.1. High Cost Typical microarchitectures, such as the Pentium P6 [27] and the Alpha EV8 [31], use a large reorder buffer to maintain the logical correctness of the code executing out-of-order (OOO). The cost of reorder buffers and other dependency checking/maintaining types of structures [44] is large and does not scale with the number of entries; the typical cost is O(k2) where k is the number of entries in the reorder buffer and/or instruction window, since elements of each entry must be compared to elements of every other entry. In particular, for a reorder buffer, as the machine size increases the number of both executing and reorder-buffer register results grows. Each executing register result’s address and window position must be compared with all of those in the reorder buffer, hence O(k2) cost growth. Large pipeline depths also have issues: for a dynamically scheduled high-performance pipeline O(p) forwarding paths are necessary to reduce or eliminate the ill performance effects of data dependencies between data in different stages, where p is the number of pipeline stages. In general, for each additional pipeline stage, forwarding paths must be added to all preceding stages; this is O(p) cost growth. 1 As many researchers have observed over the years, no system is truly scalable by this definition: as the system grows, eventually some element grows visibly faster than O(k), often at O(k*log(k)). Within some large values of k, Levo is effectively scalable by our original definition, that is, the multiplier constant for the k*log(k) term is much less than that for the k term; the k term dominates. In traditional systems, the k term(s) dominate. LEVO A SCALABLE PROCESSOR WITH HIGH IPC 3 2.2. Unscalable Microarchitecture As chip feature sizes shrink, buses become electrically long (high RC time). This leads to longer cycle times and hence reduced overall performance, as does the unscalable hardware mentioned in Section 2.1. Centralized resources such as architectural register files exacerbate the problem. They exhibit longer bus delays and a prohibitively high number of register ports [31]. The latter can increase the size of the register file substantially, further slowing the system. 2.3. Low IPC The high ILP promised over the years has not translated into high IPC or overall performance in a realistic processor, even in machines that did well, such as [20]. Part of the problem is that highILP methods and combinations of such methods have not been included in realistic designs. 3. Levo High IPC Solutions and Description Levo consists of distributed and scalable hardware. A high-level logical block diagram of Levo is shown in Figure 1. The major novel part of Levo is the n X m instruction Execution Window (Ewindow).