PREFACE: Guest Editorial – New Trends in Neural Network Implementations

In the last decade, the efforts of the neural network research community have been concentrated on investigating the abilities and limits of neural networks in general. This focus was both necessary and timely. Before trying to use a tool, we must understand its possibilities and limits. A necessary and essential step in continuing the diffusion of this paradigm in our day by day use is their hardware implementation. The ability of the neural systems to be implemented in hardware is crucial because the normal requirements for many applications include: i) a small volume, ii) a reduced weight, iii) a high resistance to shocks, vibrations and adverse environmental conditions and iv) a high execution speed. Furthermore, the hardware implementation is by far the most cost effective solution for large scale use. This special issue of the International Journal of Neural Systems is dedicated to New Trends in Neural Network Implementations. The 8 papers selected went through a careful review process in order to ensure the high quality of the issue. Approximatively 50% of the manuscripts submitted were accepted for publication. Each paper was reviewed by 3 independent reviewers and the editor of this issue. After this first round of reviews, the accepted papers went back to the authors together with the comments of the reviewers. The final versions of the papers were reviewed again before publication for compliance with the reviewers' requests. The first paper, by Anguita, Boni and Ridella present some algorithms and architectures for a digital VLSI implementation of support vector machines (SVM). The structural risk minimization approach with its most common implementation in the form of SVMs has shown to be able to provide very good performance in various application. This paper discusses the main aspects concerning the SVM learning in hardware. Issues like the effects of fixed point computation and the storage are addressed in this context. The second paper, by Waldemark, Millberg, Lindblad, Waldemark and Becanovic presents a biologically inspired neural network for image analysis applications. The Pulse Coupled Neural Network (PCNN) is an image pre-processor that can be combined with other application specific parts to form a complete system. This paper presents a VHDL implementation of the PCNN targeting field-programmable gate arrays (FPGA). The next paper is this issue deals with a similar type of image processing application. The paper by Serrano-Gotarredona, Andreou and Linares-Barranco presents an architecture for the realization of real-time edge extraction filtering in an Address-Event-Representation (AER) vision system. In fact, the approach presented here is valid for any 2-dimensional filtering system using a kernel in which the x-axis and y-axis can be separated. This paper presents a circuit implementation using MOS transistors operated in weak inversion. The proposed architecture is representative of the success of the Boundary-Contour-System and Feature-Contour-System vision model developed over the years by the research group lead by Stephen Grossberg at Boston University. The paper by Wilamowski, Binfet and Kaynak presents two neural networks designed in 1.2/xm CMOS technology. Interesting aspects addressed by this paper include compensating for imperfect activation functions and using quantized weights with limited precision. The paper by Duong presents a so called VLSI-friendly algorithm i.e. an algorithm that has certain properties that allow it to be implemented efficiently in VLSI hardware. The Cascade Error Projection (CEP) is a constructive algorithm inspired by Fahlman's Cascade Correlation. The paper includes a convergence analysis