High linearity analog and mixed-signal integrated circuit design

Linearity is one of the most important specifications in electrical circuits. Designing a high linear analog circuit is always a challenging task and it is becoming even more difficult with the shrinking feature size and reducing supply voltage of modern standard CMOS process. Furthermore, the behavior characteristics of the transistor below sub-micro are not accurately described by the traditional BISM models. All those tendencies increase the difficulty to build the high performance analog circuits with satisfied distortion level, especially when the linearity relies mostly on active elements. In this dissertation, our research for achieving high linear analog circuits will be presented including a high linear analog active filter, a linear current mode digital to analog converter and a comprehensive study of calibration algorithms for improving the linearity of pipeline analog to digital converters. There are total 6 Chapters in this thesis to conduct the research of high linearity analog integrated circuit design. In Chapter 1, a ladder-based transconductance networks has been adopted first time to build a low distortion analog filters for low frequency applications. Polysilicon resistors have been known for its attractive linearity and have been used to build high linear analog active filters for medium frequency applications. However, due to the prohibit area for implementing the polysilicon resistors, there are very seldom applications of poly resistors in low frequency range. This new technique eliminated the limitation of the application with the traditional passive resistors for low frequency applications. We investigated the relationships between the transconductance networks and the opamp design so that with other circuit vi components. Based on the understanding of this relationship, a strategy for designing high linear analog continuous-time filters has been developed. According to our strategy, a prototype analog integrated filter has been designed and fabricated with AMI05 0.5 um standard CMOS process. Experimental results proved this technique has the ability to provide excellent linearity with very limited active area and thus show the high agreements with our research works. In Chapter 2, the relationships between the transconductance networks and major circuit specifications have been explored. The analysis reveals the trade off between the silicon area saved by the transconductance networks and the some other important specifications such as linearity, noise level and the process variations of the overall circuit. Further study of the trade off behavior, the mapping between the performance space and parameter space has been addressed. The close form expressions provide the systematic guide for using those transconductance networks with other specifications considerations. Experimental results of discrete component circuit matched very well with our analytical outcomes to predict the change of linearity and noise performance associated with different transconductance networks. The Chapter 3 contains the analysis and mathematical proves of the optimum passive area allocations for several most popular analog active filters. Because the total area is now manageable by the technique introduced in the Chapter 1, the further reduce of the total area will be very important and useful for efficient utilizing the silicon area, especially with the today’s fast growing area efficiency of the highly density digital circuits. This study presents the mathematical conclusion that the minimum passive area will be achieved with the equalized resistor and capacitor. vii In the Chapter 4, a well recognized and highly honored current division circuit has been studied. Although it was claimed to be “inherently linear” and there are over 60 published works reported with high linearity based on this technique, our study discovered that this current division circuit can achieve, if proper circuit condition being managed, very limited linearity and all the experimental verified performance actually based on more general circuit principle. By pointing out what really support the high linearity, the circuit and system design community will eventually benefit from this research. Besides its limitation, our extended work, however, invented a novel current division digital to analog converter (DAC) based on this technique. Benefiting from the simple circuit structure and moderate good linearity, a prototype 8-bit DAC was designed in TSMC018 0.2 um CMOS process and the post layout simulations exhibited the good linearity with very low power consumption and extreme small active area. As the part of study of the output stage for the current division DAC discussed in the Chapter 4, a current mirror is expected to amplify the output current to drive the low resistive load. The strategy of achieving the optimum bandwidth of the cascode current mirror with fixed total current gain is discussed in the Chapter 5. Our analysis provides an efficient way to improve the total bandwidth without adding any extra hardware. Simulations proved our strategy can efficiently increase the current mirror bandwidth by 10 to 25 percent compared to the previous works. Analog to digital converter (ADC) is known as the largest volume mix-signal circuit in the world. Pipeline structure is one of the most popular structures in the ADC market for its high resolution and fast operation speed. It has been widely used in data acquisition system, communication system, etc. Improving the linearity of pipeline ADC has been the viii hottest and hardest topic in solid-state circuit community for decade. Due to the physical limitation inherent in the semiconductor process, the linearity of the pipeline ADC is always limited within 14 bit level without calibrations. Thus lots of research activities have involved in the pipeline ADC design focusing on the calibration job to break this limitation. There are many published works to discuss different calibration schemes in the last 15 years and no real effective one really appeared. In the Chapter 6, a comprehensive study focus on the existing calibration algorithms for pipeline ADCs is presented. The benefits and limitations of different calibration algorithms have been discussed. Based on the understanding of those reported works, a new model-based calibration is delivered. The simulation results demonstrate that the model-based algorithms are vulnerable to the model accuracy and this weakness is very hard to be removed. From there, we predict the future developments of calibration algorithms that can break the linearity limitations for pipelined ADC.