Reduction of Average Cycle Time at a Wafer Fabrication Facility

This paper is concerned with the development of effective solutions for the reduction of average cycle time at a wafer fabrication facility. The wafer fabrication environment is quite different from the usual flow shop or job shop environments, with a distinguishing feature being the reentrant flow of the lots through the system. Lots at different stages of their manufacturing cycle may revisit the machines. This gives rise to the need of effective policies to sequence lots through the system. Two methodologies have been developed to effect a reduction in the cycle time. The first methodology is a heuristic procedure based on the idea of reducing idle time on the bottleneck machine. The second methodology is based on mathematical programming. The proposed methodologies are implemented using the data obtained from the M/A-COM’s wafer fabrication facility in Roanoke, Virginia. The facility consists of ninety-two machines and its products can be classified into six different types. The performance of one of the proposed methodologies is compared with that of the policies currently followed at the M/A-COM facility in Roanoke, Virginia and the results are presented. INTRODUCTION AND PROBLEM DEFINITION The importance of semiconductor wafer fabrication scheduling has been increasing steadily over the past decade. Wafer fabrication is the most technologically complex and capital intensive phase in semiconductor manufacturing. It involves the processing of wafers of silicon and gallium arsenide in order to build up the layers and patterns of metal and wafer material. Many operations have to be performed in a clean room environment to prevent particulate contamination of wafers. Also, since the machines on which the wafers are processed are expensive, service contention is an important concern. All these factors underline the importance of seeking policies to optimize the performance with respect to some objective. M/A-COM is one such group of companies which has various wafer fabrication facilities in the U.S. M/A-COM Inc., at its Virginia based Roanoke facility, provides Gallium Arsenide (GaAs) integrated circuit solutions (IC) to the commercial and military wireless and radar markets. M/A-COM designs and manufactures a broad line of GaAs microwave and millimeter wave products using wafer fabrication techniques. M/A-COM’s clean room manufacturing environment consists of 5 different areas. These are Photolithography, Process I, Process II, Materials, and Implant, which are shown in Figure 1. Typically, wafers are prepared for manufacturing and introduced to manufacturing in the Materials area. Wafers are then transported to Photolithography Area to apply the desired circuit patterns with a substance called photoresist. The patterns are cleared from photoresist in the Process I Area. These patterns are then implanted with the desired ions to give the necessary properties to the pattern at the Implant Area. In the Process II area, metal is deposited to obtain the “Gate” metal. This is a typical sequence to form certain properties on a circuit. Depending on the type of circuit design, a wafer goes through 100 to 200 process steps over a period of a few weeks. Another unique property of wafer fabrication is that the fabrication is not linear through the facility but wafers may revisit machines during different stages of their manufacturing. Wafer fabrication planning and control is complicated by random disturbances, namely, the reentrant flow of operations, random yields due to the special nature of the operations, random machine breakdowns and random repair times. Presently it is observed that the lots spend a substantial portion of their cycle time waiting in queue for a machine. This leads to an increase in the overall WorkIn-Process (WIP) and a reduction in throughput. The main areas for the analysis of this problem can be identified as follows: Copyright © 2001, GaAs MANTECH, Inc.