Unfortunately, complex algorithms are often difficult to implement in hardware logic and may require many gates. Partition the high-level design task into software and hardware and then select appropriate technologies and tools within each of these areas. The challenge of integrating this SOC is in combining the physical elements of the software system with the rest of the hardware blocks. Each design phase requires extensive effort. You must select a processor, design a bus, interface to all blocks, place and route all bus signals, and still meet timing constraints.
Software development can start immediately with a complete, working, and stable physical platform.
A major portion of the hardware integration is complete. You interface to the bus by defining the local configuration of some simple synchronous interface elements called selectors. These selectors are already distributed throughout the chip, providing localized bus interfaces. The Triscend E5 and A7 families are single-chip systems with processor, memory, bus, DMA controller, and logic that may be configured and reconfigured by the user in the field. All pins connect to the CSL and have various drive strength and register configuration options.