Synchronous design is popular because it simplifies timing relationships, allowing the designer to focus on circuit functionality. Of course, every ideal solution has a few practical problems. One of the first problems one encounters is clock skew. Clock skew is the result of minor variations in the time at which clock signals arrive at their destinations, usually register clock pins. If the variations become large, then data may not be transferred reliably between registers.
Shift registers are most sensitive because of their very short data path between register bits.
Clock skew also limits maximum clock frequency because it subtracts time from the available clock time budget. While each of these elements may add small amounts of phase delay, the concern is that the differential delay or skew should be less than the minimum data path delay minus the register hold time. The buffered tree is routinely used on FPGA devices because the register clock multiplexer input pins create a fixed, regular load. Clock-tree synthesis is popular in ASIC designs because it optimizes performance, power, and area. Elements that exhibit significant delay are put inside of a feedback loop, such that the effective delay can be minimized or nulled.