The BIM is distributed with an example test bench, including memory models, example programs and scripts, to run co-verification. With it, a designer can be up and running programs in a matter of minutes. The PSPs are created and can then be downloaded from the Tensilica Web site, enabling embedded system developers to optimize software and processor hardware for speed, power and feature requirements. Engineers report that there are many design alternatives to consider within the realm of configurable processors, making co-verification tools vital to quickly evaluate the various designs. Using configurable processors also presents a few twists.
Some tasks are easy, like determining the width of the interface to external memory.
But others are more difficult, like deciding which functions to build as a dedicated hardware block and those to implement as custom instructions in the processor. Adding four instructions to the Xtensa processor leads to an improved DES algorithm that runs between 40 times and 80 times faster than a highly tuned software implementation on the same processor. The new instructions add about 5,000 gates to the core and do not affect the cycle time of the processor. Configurable processors attract designers who are pushing technology limits and want better performance at a lower cost. But there is less impetus to change to a configurable solution if a designer is running a low-performance application or has a vested interest in a different processor.