Synthesis first Input to FPGA Stuffer consists of RTL Verilog code, with VHDL support to follow later. The product then builds a database, decomposes the design and kicks of FPGA synthesis. The EDIF file can go into Xilinx placement and routing tools. FPGA Stuffer also spits out an EDIF file for board-level interconnect between the FPGAs. The initial release supports Synopsys FPGA Compiler II and FPGA Express, and Synplicity's Synplify synthesis tools.
Users can add other synthesis tools that have a scripted interface.
The product runs on Sun Solaris platforms. SpeedGate intends to sell partially through OEM deals, and has one with emulation startup AppNet Inc., which provides the Proteus prototyping platform. All rights reserved.