The results presented in this paper were obtained with a parameterizable code reorganization and simulation system. The discussion of machine parallelism is based on the concepts of superscalar and superpipelined machines.
Superscalar machines can issue several instructions per cycle.
Superpipelined machines can issue only one instruction per cycle, but they have cycle times shorter than the latencies of their functional units. These two techniques are shown to be roughly equivalent ways of exploiting instruction-level parallelism. The average degree of superpipelining metric is introduced to account for the non-unit operation latencies present in most machines. In this paper a methodology for quickly estimating machine performance is developed. A first order estimate is based on the average degree of superpipelining.