After transactions are verified, the RMM says designers can verify that the block behaves correctly for all values of data and all sequences of data it will receive in an actual operation. The RMM advocates a functional models for all blocks except the block under test, which is represented in a full RTL design. Real code is compiled and loaded into the RAM model, and the processor model executes this code. The full RTL model is used as the simulation model for most of the functional blocks. The manual goes on to emphasize the importance of rapid prototyping.
Some simple math makes the point very eloquently.
Emulation is suggested for large chips, especially if the entire design can be placed in the emulation engine. He noted that it's useful early in the design cycle to prove concepts, as well as later for system verification. But the trick is knowing when to do it. The manual suggests that the bug rate from simulation testing should have peaked, and be on its way down. One response is RTL signoff, although most ASIC vendors still require manufacturing test vectors.