In addition, because of unanticipated situations, you may have a combination of events occur that the testbench does not check. Use behavioral VHDL and Verilog, because they allow you to rapidly produce a very complex model from which you can automate all subsequent design processes. Rapid coding of your design may also result in unintentional circuit behavior. Statement coverage tracks assignments. You apply this technique to the signal and variable assignments for HDL code coverage.
Statement coverage measures how many times a simulation executes each assignment.
When a simulation never executes an assignment, a design error may remain undetected. A good verification tool should highlight nonexecuted assignments in the code to show that they are a source of potential design errors. For example, simulation has not executed the statement in Listing 1 . The design or test engineer should now create extra tests to check the assignments that the verification tool highlights. Further options for code include branch coverage and branch-subcondition coverage.