The third extra stage is used to monitor the select output. In the buffer stage a reset transistor has been implemented in the design to reduce noise and crosstalk during the pixel write period. The noise due to the displacement current is discharged through the new transistor when data is being loaded onto the storage capacitor by the pixels of a selected gate line. This allows more OAR compared to storage capacitor built on a separate independent line parallel to the row lines. Display yield is another major contributor to display cost.
Yield is a function of processing line defect density.