The purpose of this memorandum is to take the reader through a complete cycle of using Altera s VHDL compiler and simulator. It is meant to be only a thumbnail sketch of the process. The tools used will include the Text Editor , the Compiler , the Waveform Editor and the Simulator . Once it has passed through these stages, the project under design can then be downloaded to an appropriate Altera part.
Some jargon is used in the following.
Click on or hit the button means to click the left mouse button. Creating the VHDL File Start the Altera tool set by clicking on the appropriate icon. Since it takes a while to come up, close the application only when you are done. It s best to iconicize it if you want to do something else temporarily. A ssign, O ptions and H elp.