Simulation is performed by a separate program, often a commercial product.
Verischemelog compiles to Verilog, an industry standard language accepted by several commercial and public domain simulators. Because many design elements are easily parameterized, design engineers currently write scripts which generate hardware description code in Verilog. These scripts work by textual substitution, and are typically ad-hoc and quite limited. Preprocessors for Verilog, on the other hand, are hampered by their macro-expansion languages, which support few data types and lack procedures. Verischemelog obviates the need for scripts and preprocessors by providing a hardware description language with list-based syntax, and Scheme to manipulate it.