Some recent RISC chips have memory models which allow for stores and loads to be re-ordered from what the programmer intended, in order to gain performance. We are shown how RISC chips have mechanisms to force the correct results for implementing locks and accessing data in critical sections. Even when memory requests are issued in the order they were programmed, cache consistency is a serious issue in multiprocessor systems. The final chapters of the book address the interactions that must be dealt with by a serious system designer. This book is written as a textbook, with questions and references at the end of each chapter.
Selected questions have answers provided in an appendix.
Another appendex summarizes a dozen popular chips found in Unix systems.