Debussy compiles the original Verilog and VHDL source files to extract knowledge of the design such as flip-flops, latches, and muxes. Drag and drop lets users rapidly change the current view of the design to see exactly the information they need to understand a problem. The Debussy system is the only debugging system that lets engineers maintain a consistent view of the design throughout the design and verification process as they debug results from simulation, synthesis, formal verification and timing analysis. The Debussy system is tightly integrated with simulators from Axis, Cadence, IKOS, Mentor, Model Technology, and Synopsys, formal verification tools from Verplex, and emulators from Quickturn. Open interfaces provide integration with all popular Verilog and VHDL simulators as well as formal verification and timing analysis tools.
Users can integrate their own tools through tcl and C APIs.
Verification results are placed directly on the source, schematic, and bubble-diagram views. This greatly enhances comprehension of the design because users can immediately see not only results, but causes as well. This information allows the Debussy system to correlate simulation and other verification results with the design and to generate schematics that automatically indicate sequential register boundaries. The figure to the right shows the architecture of the system. The Debussy system includes the Open FSDB fast signal database, which enhances large simulations through fast generation of highly compressed signal value dump files.