Some people consider state-diagrams and statecharts as specification languages.
A program, hardware model, state-machine, and statechart all define one particular output sequence that is generated per input sequence. This is determinism, which is part of any implementation. In contrast, a specification can say whenever a request arrives, an acknowledgement should be generated within a millisecond , which is not deterministic because many possible output sequences satisfy this requirement, as long as a request is indeed generated within a millisecond of a request . Temporal Logic provides the capability of specifying requirements without having to describe deterministic scenarios. Any one of those allowable sequences of system outputs can be generated by a correct implementation.