In many cases the vector unit cannot take advantage of it and execution speed may even be unfavourably affected because of frequent cache overflow. This usually does not impair the speed of operations while providing much more flexibility in gathering operands and manipulation with intermediate results. Because of the generic nature of Figure 1 no details of the interconnection between the VPU and the memory are shown. Schematic diagram of a vector addition. In fact, in the vector systems marketed today this high bandwidth thus not occur any longer.
Vendors rather rely on additional caches and other tricks to hide the lack of bandwidth.
The VPUs are shown as a single block in Figure 1 . Yet, again there is a considerable diversity in the structure of VPUs. Every VPU will have pipes that are designated to perform memory access functions, thus assuring the timely delivery of operands to the arithmetic pipes and of storing the results in memory again. Division is performed by an iterative procedure, table look-up, or a combination of both using the add and multiply pipe. In addition, there will almost always be a mask pipe to enable operation on a selected subset of elements in a vector of operands.