In an asynchronous circuit, those delays influence the functioning of the circuit. In the propagation delay model , a fixed delay is associated with each gate. In the inertial delay model, the input pulse must have a minimal width to generate an output, or no switching takes place. This can be combined with both the other two delay models. Switch-Level Model Models transistors as swiches for digital signals, but includes features that can be associated to annalog resistance and capacitance.
Signal flow is discrete and bidirectional through the switch.
The model is kore accurate than a Gate-Level model, but computationally less intensive then a Circuit Model. Capacitances and resistances enter indirectly as strenghts . A signal is the same s in Gate Model, but might take other discrete values, also. The exchange of signals between these subcircuits is simulated with an event driven model. Static partitioning can be done in time linear to network size by doing a depth- first seach over all source and drain childs of a transiostor, but skipping gate or input net connections.