Designed for general logic implementation, FPGAs lack specific features of rapid reprogrammability as well as dedicated internal buses, and often have too little interconnect to ensure that even a small change in the programming can be accomplished without altering the chip's entire configuration. The unified cell is divided into a memory region of eight cells and a column circuit with a crosspoint switch and a read circuit for logic. That scheme is similar to the four-input lookup table used in FPGAs, but is much more sophisticated. In particular, the unified cell is able to allocate its resources as either logic or interconnect, whichever is most needed at that point. In a sense, the unified cell can be used for logic and as an interconnect switch.
Some circuits require a lot of logic but only a small amount of interconnect.
With this, the cell can either be logic or a switch by changing the context. On the prototype device, the area required to store the eight contexts saved is 35 percent greater than the area of an equivalent FPGA, but NEC claims the benefit is eight times more usable gates. And in the future, using DRAM instead of SRAM cells to save context, the company can potentially pack 256 contexts together instead of eight, Motomura said. The experimental chip eats more than 100 mW for every 10 mega-reconfigurations per second. The chip is still in the early evaluation stage, but initial performance tests hold promise.