This is one reason why it is hard to design high-performance pipelines. A hazard occurs exactly when an instruction tries to read a register in its ID stage that an earlier instruction intends to write in its WB stage. If the instruction in the ID stage is stalled, then the instruction in the IF stage must also be stalled, otherwise we would lose the fetched instruction. In fact, Figure 6.32 is a shorthand representation of what really happens in the hardware. Another kind of pipeline hazard involves branches.
Simplest approach is to stall the next instruction until the branch instruction is complete.
Many times a conditional branch will decide against branching. If the branch is taken, the instructions that are being fetched and decoded must be discarded. Execution continues at the branch target. If branches are taken half the time, this optimization halves the cost of the control hazards. To discard the instructions, we merely change the original control values to 0s much as in the stall approach.