This is deliberate. What we are usually looking for is an organized, coherent discussion of the issues raised in the question. Completeness is a factor but is not the most important consideration. In other words we want to see if you can analyze the subject and determine what is important and what is not important and write reasonably about it. This problem is concerned with addressing modes for memory access and program control.
Shorter instructions are preferred.
Another factor that you should consider is the relative frequency with which your set of addressing modes will be used. For simplicity, assume that all registers are one word long, and that all memory accesses are to word-size quantities. Defend your design. In computing systems which use a cache between the CPU and MM, the object is to make MM almost as fast as the cache. Thus the cache has almost the same relation to MM as MM has to SM, and conversely.