The continuing lack of automatic circuit synthesis and layout tools for these applications remains a huge bottleneck. This research involves work on numerical algorithms to translate specifications into circuits, on optimization algorithms to improve the performance and manufacturability of these circuits, and on combinatorial algorithms to translate these circuits into final integrated circuit mask geometry. This work focuses on high-performance digital ICs, where it is necessary to handle both large problems and subtle electrical interactions.
Work here involves a mix of combinatorial algorithms and electrical circuit verification algorithms.
222-231, June 1998. 499-518, June 1998. 273-294, March 1996. 226-237, March 1994.