For example, using this feature, you can select the FIFO's data input to be 36 bits wide and its output to be 9 or 18 bits wide. However, this approach requires extra control logic. You must make the bus-size selection one cycle before the selection takes effect. This one-cycle latency lets the FIFO set up the control logic before the next transfer, resulting in shorter setup and hold times for these inputs. Other choices you must make when selecting a FIFO device include the number and direction of datapaths.
Vendors typically specify the direction of data flow as unidirectional or bidirectional.
Higher integration is making it easier for vendors to include more than one FIFO buffer within a device. Dual FIFOs are common. Data-transfer mechanisms are also important when choosing a buffer. Except in low-performance systems, synchronous devices have all but replaced their asynchronous counterparts, because synchronous devices offer far better noise immunity than do the asynchronous versions. In systems lacking a clock, designers can use strobed FIFO devices, which accept or output a data word at every rising or falling edge of the write or read clock, respectively.