After the exposure the CCD is clocked backwards then forwards a specified number of lines for a specified number of times and then the CCD is read out in normal fashion. The backwards then forwards clocking sequence causes the signal charge to build up or be pumped at the trapping site. The size of the trap site can be calculated by dividing the excess charge at the trap site by the number of cycles. Those effects are often due to channel width variation, polysilicon edge lifting, and typical boron lateral diffusion. As fast as parallel clock electrodes grow longer, additional electrodes are added in parallel, so that total resistance is invariant with size.
Total capacitance scales with area, of course.
Big chips need to be clocked as slowly as 1-5 KHz because of their internal time coinstants. If the pixels read rate is 100 KHz this is ok, but at 1 MHz the parallel shift time becomes a serious overhead. You can easily do your own sums, but I can dig up my spreadsheet for this if anyone is interested. Even at 50-100 KHz read rates, parallel shifts dominate readout times for Regions of Interest. The preprint contains graphs showing the relative contributions of line transfer time, pixel skip, and pixel read times versus ROI size.