Most general purpose bus designs are asynchronous because asynchrony is more flexible in accomodating a wider range of devices. Asynchronous bus designs also adapt more readily to technological advances. In a synchronous bus design, there is an assumption of a basic clock rate and increasing that rate can cause older devices to fail to operate properly. In an asynchronous design, older devices may simply reduce performance. However, an asynchronous protocol is usually more complex, requiring both more hardware and more overhead for each transaction.
Synchronous buses can operate with lower latency and higher bandwidth for a given number of signals.
Thus, synchronous buses are usually developed for applications in which maximum performance is required and the usage is constrained to devices with a narrow range of timing characteristics. From this we can deduce that the two types of buses have different applications for which they are best. Modern systems often employ both types of buses. The CPU connects to a synchronous memory bus containing the cache, main memory, and a bus adapter. In some cases, the CPU and Cache are connected by a dedicated synchronous link, and the cache controller connects to the memory bus.