I2, meanwhile, is being fetched. After 5 clock cycles, processing of I1 is complete. When the pipeline is fully loaded, an average of one instruction per clock cycle can be output from the pipeline, like cars rolling off an assembly line. The Pentium's superscalar design incorporating two independent pipelines nominally doubles the processor's instruction throughput. Pipelining allows more than one microprocessor instruction to be serviced at once.
Time moves from left to right in units of a clock cycle.
Follow the first instruction, I1, from left to right, and you can see that other operations enter the pipeline before I1 is finished. This allows the microprocessor to average 1 clock cycle for each instruction.