One disadvantage is that the devices in a DRAM process are not as robust in performance as the devices in a logic process. This can be overcome in many applications by rearchitecture, creating the same final logical function by using the wide internal bus width available from the DRAM and doing more of the logical operations in parallel. Rearchitecting and doing more in parallel versus serial is a change and requires a lot of planning and thought on the part of the system architect. There have been many publications over the past several years, both from industry and academia, on the use of internal bus widths of 256 and up. One of the essential items that needs to be planned ahead is testing.
Testing can quickly become a dominant part of a product's cost.
When memory is embedded behind a lot of logic, you can't always assess the true performance of the memory. And area is lost through the multiplexing and extra wiring required to connect to the external chip pads. It's especially important to keep in mind two-dimensional redundancy calculation and processor base to allow quick changes to test patterns and sequence. Dr. Jack Lipovski Dr. Jack Lipovski, Chairman Linden Technology, which produces merged DRAM and logic chips. There is a design called a dynamic associative access memory.