The class has been modified according to opinions of industrial students. More practical examples were added, less about language syntax. More various types of student homeworks and mini-projects. One large project is no longer mandatory, but still possible for volunteers. Grading is based on two homeworks and project.
Volunteers can have one larger project.
Much time will be given to fundamental aspects of logic synthesis and VHDL-related design automation that are already commonly used in industry. Tools from industry, Mentor, Cypress, Summit, and Orcad, are presented and used in the projects. System-related subjects are discussed that are of personal interest to students. Students can propose their own group or individual projects. There will be at least three different projects related to VHDL logic synthesis to choose from.