Performance results are shown in a hierarchical display enabling designers to identify slow spots in their simulations. Armed with this information, design teams can make coding changes where they have the greatest impact, thereby reaping the benefits of faster simulation runs. Modelsim's new integrated code coverage feature enhances overall efficiency of the verification environment by measuring the percentage of a HDL model exercised by a testbench during simulation. Code coverage provides a graphical summary of executable lines hit. The results can be accumulated during a set of regression tests.
Users also can view the details of each source file.
The new Modelsim Elite simulator will include a language-neutral license enabling simulation of either VHDL or Verilog designs with one simulator and one license. Industry experts are predicting that single-language simulators will be replaced by simulators with single kernels within the next few years. Modelsim Elite version 5.3 will be available in Q2 1999. Existing customers will be notified of upgrade pricing. The process geometry shrink will improve transaction speed, enable more sophisticated management of larger on-chip memories, and strengthen data encryption features of smart card designs.