Verification is the number one bottleneck in chip design today.
As the industry leading verilog simulator, VCS is the backbone of Synopsys comprehensive HLV solution. We have seen phenomenol growth for VCS in the recent past, and it continues to be a high-growth champion product at Synopsys. You will learn to maximize the VCS performance for lightening speed RTL simulation and work with adjacent technologies such as VERA for testbench generation, and CoverMeter for sophisticated code coverage analysis. In addition you will work with other groups in Synopsys in integrating VCS in different flows. You will be able to maintain a steep learning curve and get acquainted with next generation verification tools that will be in demand tomorrow.