ASICs have reached densities of over 3M gates. Custom chip densities are reaching 20M transistors. For very large and complex designs, engineers need to significantly increase the amount of functional verification they employ to insure correctness before they incur the time and expense of a physical prototype of the chip. Static timing verifiers have provided a huge improvement in the effort required to get the timing correct.
Specialized emulators offer a big performance gain in functional verification.
However, there hasn't been a major breakthrough in the performance of commercial software simulators until now. That breakthrough is the arrival of commercially available cycle-based, logic simulators. Inter-phase timing is ignored. Cycle-based simulators only focus on the functionality of the design and therefore can highly optimize the calculations for that purpose. These internal simulators were historically based on an internal proprietary design language and were not available to other companies.