Grading is based on two homeworks and project. Volunteers can have one larger project. Much time will be given to fundamental aspects of logic synthesis and VHDL-related design automation that are already commonly used in industry. Tools from industry, Mentor, Cypress, Summit, and Orcad, are presented and used in the projects. System-related subjects are discussed that are of personal interest to students.
Students can propose their own group or individual projects.
There will be at least three different projects related to VHDL logic synthesis to choose from. The new course does not require any specific prerequisites. It can be taken as a part of Design Automation sequence. Most time will be spend to teach VHDL language on a sequence of carefully selected progressively more difficult examples, for both specification, simulation and synthesis. System-related subjects will be discussed that are of interest to students.