The main thrust of the Virtual Channel is to reduce the page-miss latency inherent in today's DRAMs. A conventional DRAM experiences a multiclock delay any time a new page of the memory is addressed. It would not be a major problem if most DRAM accesses were sequential. But in today's systems, an interleaved mix of traffic from L2 cache controllers, graphics controllers, PCI controllers and other potential bus masters forces DRAMs to hop about nearly at random through the memory space. Often, most cycles cause page misses, resulting in a dramatic drop in memory bandwidth.
Vendors try to hide the delay by dividing fast DRAMs into multiple banks.
This does nothing to reduce the precharge time, but increases the possibility that a given memory reference will be to a row that is already active in one of the banks. This technique is used in Concurrent Rambus and Mosys DRAMs. NEC takes a different approach. A memory master can read or write to the SRAM buffer, and copy it into or load it from the DRAM array. In more sophisticated uses, the mapping can be refined.