The industry is still trying to expand the idea of EDIF, a common netlist that would allow input to any simulator and any placement system. Once an acceptable netlist has been generated by whatever means, the designer needs to check or verify that the design rules have not been violated. When the circuit is certified as acceptable and buildable, the circuit must be simulated according to the design submission requirements of the chosen vendor. The simulation must be checked. The design must be documented.
Simulations involve control programs, stimulus generation, annotation delay files and descriptions.
AC test analysis requires additional documentation. Which simulator can be used, and whether any timing verifier or other tools are available, is limited to what the array vendor supports. The simulation output files must be formatted according to vendor rules to allow the generation of test vectors. These will be transferred to the placement software and to test-generation software. A submission may include dozens of files that must be tracked, controlled for revision level and managed to verify that the design submitted to the vendor is the one intended to be submitted.