They are due to the inability of conventional wire-load synthesis to effectively predict net delays, which dominate the overall delay. These problems are exacerbated when the two teams work at different locations or companies. The only way to work around these problems using conventional synthesis is through overly conservative wireload estimates, which result in designs with sub-optimal performance and area. With conventional approaches, crosstalk and IR drop issues are found after final placement and routing. Lucky design teams identify the problems and perform expensive manual fixes before tapeout.
Unlucky teams find their problems when the device fails on the tester.
Logic design teams use PKS physical synthesis to create an optimized netlist. The extraordinary capacity and performance of PKS enables teams to synthesize million-gate blocks, greatly reducing constraint specification and constraint maintenance time. During PKS synthesis, the tool makes millions of logical and physical tradeoffs as it incrementally optimizes the logic, placement, and routing to achieve the highest quality of results. This concurrent optimization inherently yields fewer signal integrity issues, because it properly sizes drivers based on actual physical information. However, teams starting with PKS-synthesized designs will rapidly achieve the best possible timing closure and quality of results.