Any change to the design information such as moving an edge on an input signal or changing a delay in a logic equation automatically triggers a re-simulation, providing instant feedback on the impact of changes on system functionality and performance. Worst case simulation enables designers to check for race conditions that can occur because of component timing tolerances. Delay uncertainty is the difference between the max time and the min time of a gate delay in a design. Uncertainty on a single delay that cascades down two different signal paths can be removed when computing relative times between signal transitions on those two paths as the delay will be the same for both paths. Summary SynaptiCAD's WaveFormer Pro v4.0 with Interactive HDL Simulation represents a new way to perform simulation and timing analysis.
Users can view and edit the generated code.
Models and test benches can be exported and used with external VHDL and Verilog simulators. 2001 CMP Media Inc. All rights reserved.