This is a tool which helps to fill the tool need in the domain of formal asynchronous circuit and system verification. This tool uses CCS as an input language to analyze asynchronous circuits and verify they satisfy the specification. The tool is coded using efficient model checking techniques, but does not used advanced data representations such as BDDs. Bisimulation and Trace equivalences are the foundational equivalences between specification and implementation. Analyze will also generate CWB compatible output of minimized agents in standard normal form.
Verification uses both bisimulation and trace formalisms.
Links for downloading the source and examples Common Lisp source for Analyze a verification tool for asynchronous circuits and systems based on bisimulation. This tool supports all the asynchronous hazard models, including Burst-Mode. Documentation for Analyze. Short demo presentation of Analyze. Analyze examples from the Post Office chip and other sources.