A circuit design usually employs a number of components. Processes are therefore combined in an SDL block type. An SDL block type consists of processes that represents a component. Connections between blocks are made via SDL gates. The approach has been embodied in a library of SDL packages that define block types for the components.
Tools allow library packages to be generated automatically using a macro processor.
Much of the library consists of variants on basic components. These variants are generated automatically, allowing the core library to be much smaller and more maintainable. A discrete event simulation has been developed for circuit timing analysis. Circuit Validation Circuits are validated partly through manual simulation and partly through scenarios expressed as MSCs. These scenarios are manually generated or are automatically produced from simulation runs.