Abstract Formal verification has long been promised as a means of reducing the amount of testing required to ensure correct VLSI devices. These models are called specifications.
Verification is a mathematical analysis showing that the behavior follows from the structure.
Formal verification of microprocessor designs has been quite successful. Indeed, several verified microprocessors have been presented in the literature, and one microprocessor where formal modeling has been applied is commercially available. These efforts were virtuoso performances largely academic exercises carried out by experts in logic and specification. This paper presents a methodology for microprocessor verification that significantly reduces the learning curve for performing verification. The methodology is formalized in the HOL theorem-proving system.