Circuit transformations can target the decrease of area or delay, possibly while satisfying bounds on delay or area. Typical example of such transformations is a partitioning of large circuit netlist for implementation into several FPGA devices. Performance evaluation is an important task, even when it is not coupled to timing optimization. Timing verification is usually a part of a complex circuit verification process which consists of design rule checking, functional and performance verification, validation of operating conditions, etc. The earliest and the most accurate method for performance evaluation is circuit simulation.
Timing analysis consists of extracting the delay information directly from a logic network.
The logic network is represented by a graph or hypergraph model and the timing behavior is approximated by simple delay models. An example of such abstraction is a delay model that was introduced in Chapter 2 and will be used extensively throughout this chapter. Using this kind of abstraction, the problem of finding the longest propagation path in a circuit is equivalent of finding the longest path in a corresponding graph. Thus, the principal advantage of timing analysis over simulation is that the former finds the longest propagation path without requiring input excitation. Since these methods do not consider logic behaviour, a long path identified in a graph representation may not be logically meaningful, i.e., there is no input vector to excite the long path.