The EDA industry is in a virtual alphabet soup of standards and standards bodies. A good deal of this confusion stems from the origin of the standards. Many of these efforts were initiated by EDA vendors seeking to gain a market advantage. Often, the adoption of a standard is influenced by its source and the support it receives. Both Verilog and VHDL were standards long before organizations were formed to promote them.
Standards work best when they are based on existing installed technologies.
In the early stages of technology development, chaos occurs when a number of solutions are tried and discarded, making the definition of a standard risky. The risk correlates to the number of possible winning approaches that lead warring entrepreneurial engineers to concede territory to exploit the core technology and not its supporting architecture. In short, it is too early to standardize. Current examples are formal verification and behavioral synthesis language. This stage is entered when innovation slows, so the number of possible choices and attendant risks are known.