Depending on the manufacturer, a macro or standard cell library may exist that can speed the design time if the cells and macros are suitable for the application. The internal macro interconnects would still run through all mask layers. Design time may be reduced at the cost of some flexibility, but prototype time would remain lengthy. The advantage of the macro library is to help the designer by providing common functions while lessening the experience level required for a successful design. The interconnect pattern, also called a netlist , is generated from the customer-designed schematic and restricted to the topmost mask layers.
Some arrays require three metal and two via layers.
Three-layer arrays may use two layers for global interconnect and the third for macro intraconnect, but there are no hard rules. The more layers, the more prototype debug time required. This may be compromised with the significant gain in power management possible with the third layer. Most manufacturers prefer that the released macros be used. For example, at least one CMOS array uses the AMD Am2909 sequencer as a macro.