The embedded DRAM architecture has the advantage of enabling wide data paths of 128 bit, and the memory subsystem runs at chip speed. Additionally, less buffering is required to process streaming data, and the memory sizes are not restricted to standard configurations. The Jazz processor from Improv Systems is a VLIW configurable data-path architecture designed for very high performance. Shallow two-stage pipelines in the CPUs limit the clock frequency of the chip, but wide parallelism enables the processor to execute 3 to 6 BOPS at only 100 MHz. The interesting part is that the CPUs are not connected by a databus.
Scheduling is done by the compiler ahead of time.
There is one global bus on the chip, the Qbus, passing task address and 16-bit datum. The presentations at the EPF certainly demonstrated that there is more interesting stuff to come in the world of embedded systems. While the PC processor market consolidates, the embedded processor market seems to proliferate, and the ever-growing diversity of embedded applications is a continuous challenge and also an opportunity for embedded processor companies to come up with new designs and solutions. Copyright of all documents and scripts belonging to this site by Thomas Pabst 1996 - 2001. Most of the information contained on this site is copyrighted material.