Chip makers such as AMD, Cyrix, and NexGen are further blurring the line between CISC and RISC by incorporating RISC-like features into their Pentium clones. The difference between RISC and CISC microprocessors is no longer one of instruction sets, but of chip architectures. These days, both RISC and CISC manufacturers are pulling out all the stops to get an edge on the competition. How It Works Pipelining is a technique used by RISC and CISC microprocessors to break the execution of individual instructions into stages and overlap the stages so several instructions can be processed in parallel. Pipelining allows more than one microprocessor instruction to be serviced at once.
Time moves from left to right in units of a clock cycle.
Follow the first instruction, I1, from left to right, and you can see that other operations enter the pipeline before I1 is finished. This allows the microprocessor to average 1 clock cycle for each instruction. Under ideal conditions, each stage requires 1 clock cycle. You can trace the path that a single instruction takes through the pipeline by following I1 from start to finish. During the first clock cycle, I1 is fetched.