Software pipelining, the mixing instructions from one iteration to another may be aiding this code to hide the latency of the level two cache misses. These routines are found on all high performance architectures. These routines are expected to be the building blocks for larger numeric intensive algorithms and computations. As such, we expect them to be highly tuned for each specific architecture obtain as close to peak performance as is achievable. Evaluate compiler efficiency by comparing performance of the reference BLAS versus the hand-tuned BLAS provided by the vendor.
Validate vendor claims about the numerical performance of their processor.
The benchmark can run in either single or double precision. This is important as many systems cannot sustain the additional memory bandwidth required by using double precision data. These numbers are not computed from hardware statistics, but rather from the absolute operation and memory reference count required by each algorithm. 2.3 Sample Results - Matrix Multiplication Matrix multiplication provides a lot of opportunity for cache reuse due to the fact that the number of computations is an order of magnitude larger than the number of unique memory references. By tiling the matrices appropriately, the working set of the problem can be reduced to the size of cache.