Forward jumps are not as simple, the distance is unknown at the time of the instruction generation. It is necessary to repeat the jump instruction selection in an iterative fashion until all jump instructions in a block are determined. We implemented a special datastructure mimicking the jumps to find the relevant instructions. Another performance critical aspect of code generation for CISC architectures is the choice of the optimal addressing mode for a given load and store operation. This is particularly true on the 680x0 processor with so many modes to choose from.
Several instruction sequences using different addressing modes are possible to access a variable.
The choice of the best scheme is influenced by the number of bytes for the sequence and the number of cycles for the instruction sequence. Combining as many operations as possible into a single instruction used to be the optimal strategy. In the times of burst transfers from memory to CPU and multistage instruction decode, this strategy is no longer adequate. For example the memory indirect addressing mode, used in MPW Oberon to access VAR parameters on lower lexical levels, is slower on the 68040 than a two instruction sequence. The 68030 performs better with the single instruction scheme.