Then the home, knowing which other processors shared the variable, would send invalidate messages to these processors in order to invalidate their copies of the variable, and grant the exclusive copy to the requesting processor. Since all memory operations are handled centrally, latency is increased for these operations. The following diagram is a multiprocessor with directories. It shows that for every memory block there is a directory entry. A is accessing variable x and processor B is accessing variable y.
Typical caches contain more than a single word per cache line.
Therefore if x and y reside on the same cache line, then the two processors will be sharing a single cache line though they are not actually sharing the same variable. A to x will cause processor B's copy of the shared cache line to be invalidated. And likewise a write by processor B to y will cause processor A's copy of the shared cache line to be invalidated. This side effect of using coherence protocols with multiple-word cache lines, which leads to unneeded invalidations, is called false sharing . It is up to the programmer to detect false sharing and to take steps to alleviate it.