Not surprisingly, this process is called prefetching. Once in a while the CPU will decode and execute some sort of branch operation. Jumps and calls flush the FIFO, erasing these unneeded entries. The BIU then starts fetching from the new execution address. Soon, however, the BIU will again fill the FIFO, keeping a bit ahead of the EU's needs.
Some instructions read or write data to the memory array.
In general, a deeper FIFO lets the BIU get further ahead of the Execution Unit, maximizing the memory channel bandwidth. It's hard to say just what the most efficient FIFO size is. The pipeline is similar to a prefetcher, in that it blindly and dumbly reads ahead, trying too fill a queue with sequential instructions that might be needed. Where with a prefetcher the queued instructions just hang around in a FIFO, the pipeline contains logic that starts to interpret each prefetched instruction. RISC processors depend on pipelines to meet their much vaunted one clock per instruction specification.