Adherence to industry standards and open architecture provides the maximum in hardware and software compatibility, while facilitating system customization and expansion. This commitment is evident in the MVME167. The VMEchip 2 and DRAM map decoders are disabled by a local bus reset. This area is user-programmable. The suggested use is shown in the table.
Size is approximate.
Cache inhibit depends on devices in area mapped. This area is not decoded. If these locations are accessed and the local bus timer is enabled, the cycle times out and is terminated by a TEA signal. Async Baud Rate, 38.4K bps max. Sync Baud Rate, 64K bps max.