The processor completes state changes that have occurred in instructions prior to the faulting instruction. The faulting and subsequent instructions have no effect on machine state. Faults are IVA-based interruptions. Traps are synchronous with respect to the instruction stream. The trapping instruction and all previous instructions are completed.
Subsequent instructions have no effect on machine state.
Traps are IVA-based interruptions. The following figure summarizes the above classification.