Power consuption is typically lower than for CPLDs. FPGA typically conatin many Flip-Flops and IO gates. Hold thier programming in non-volitile memory and so fire up ready to go. Unfortunatly, these types of memory do have a limited life so CPLDs can not be reprogrammed continuosly. Many CPLDs do have deterministic timing since the signals are routed between macrocells via interconnects.
Signals travel from pin to pin very quickly.
Wide decoders PAL-device integration Software to translate HDL description of circuits into JDEC files, program the JDEC files into the individual devices and the interconnection cable between the PC and the device via an adapter socket or ISP header costs thousands of dollars. You can get started for quite a bit less. It is crippled in that it is limited in the size device it can compile. Still, the devices it handles are plenty big to do many things, especially learn about the device capabilities. That package has a schematic entry capture tool.