Such scheduling hardware can yield good performance without relying on compile-time scheduling. The hardware can also schedule around unexpected run-time occurrences such as cache misses. As issue widths increase, however, the complexity of such scheduling hardware increases considerably and can have an impact on the cycle time of the processor. Scheduling hardware is removed from the processor pipeline altogether and placed on the path between the instruction cache and the next level of memory.
Scheduling is performed at cache miss time as instructions are received from memory.
Scheduled blocks of instructions are issued to an aggressively clocked in-order execution core. Details of a hardware scheduler that can perform speculation are outlined and shown to be feasible. Performance results from simulations are presented that highlight the effectiveness of an MPS design. All Rights Reserved. The full text of is available to members of the IEEE Computer Society who have an online subscription and an e-account .