It still takes too long to debug the RTL model, and the risk of missing bugs that will not be found until system integration remains high. By using formal model checking to check these details at the block level, users can save valuable time bringing up the RTL simulation model at the chip level. And since more bugs are found earlier in the process, where they are less expensive to repair, overall development cost and risk are reduced. The Design Insight Formal Model Checker comprises a set of capabilities for proving complex temporal properties that may involve hundreds of state bits and require analysis of many thousands of states. This new tool is most effectively used by advanced design groups who partner with Chrysalis to develop a new design methodology that creates and proves formal properties in parallel with the development of RTL models.
Users describe properties in terms of a design's signals.
The Formal Model Checker automatically extracts the required state bits and adaptively applies a wide range of advanced formal techniques to prove whether the circuit function obeys the properties. The Design Insight Formal Model Checker is readily incorporated into existing design environments because it requires no changes to users' Verilog and VHDL RTL source descriptions. The product uses Verilog and VHDL as its property description languages so designers can easily write properties that describe correct operation of their block-level design details. It also incorporates built-in functions to handle concepts such as liveness and fairness that are not readily expressed in RTL code. All Design Insight products are built on the same Chrysalis symbolic logic database that underlies the Design Verifyer formal equivalence checking software.