Idealised waveforms to show how the CDS circuit measures the difference between porch and pixel value at each tick of the CCD clock. First the number of frames to be acquired was specified. Then host memory was allocated using host memory allocation functions. Performanc e evaluation To assess the capability of the recording system to acquire high-speed sequences of frames, a LED digital counter was built and clocked by FVAL pulses, each FVAL pulse incrementing the counter by one digital unit. It follows that, in principle, the maximum amount of PC memory that could be reserved for acquisition was limited only by the available RAM, although in the present configuration only RAM sizes up to 128 MBytes were tested.
Solid lines are linear least-square fits to data.
Error bars are smaller than plot symbols and do not show. Extrapolation to zero input gives non-zero output because of residual offset, affecting the CCD signal prior to digitisation. Illumination was varied by changing the aperture of the diaphragm in front of the fibre optics and its intensity was measured with a photodiode placed on the illumination light path after the dichroic blade. As N Ph is the square root of the photoelectron number, the contribution to the overall noise from the electronics was of the order of 300 e - . In fact, N R decreased whereas N D increased when reducing the speed of acquisition, but N D was kept efficiently under control by cooling the sensor.