Designing with HDLs is an ongoing learning process. As you gain experience, your designs will be faster and consume less logic. Don t be afraid to try trial implementations to understand how a tool responds. Also look at other people s code for ideas. Investigate how your coding affects the final implementation.
Schematic viewers are helpful.
Without them, you must reconstruct the design s structure from a text-based netlist. Always include a default assignment in all IF and CASE statements, even if you re sure they cover all conditions. Without a default assignment, a synthesis tool can generate inferred latches. Watch for warnings from the software. It s generally better to code multiplexers using a CASE construct rather than a nested-IF construct.