Executing XCHG instruction. Cache Considerations Systems programmers must take care when updating shared data that may also be stored in on-chip registers and caches. A change to a descriptor that is shared among processors should be broadcast to all processors. A change to a descriptor will not be utilized by another processor if that processor already has a copy of the old version of the descriptor in a segment register. Page tables, which may be held in the page-table cache.
Systems designers can employ an interprocessor interrupt to handle the above cases.
When one processor changes data that may be cached by other processors, it can send an interrupt signal to all other processors that may be affected by the change. If the interrupt is serviced by an interrupt task, the task switch automatically flushes the segment registers. In multiprocessor systems that need a cacheability signal from the CPU, it is recommended that physical address pin A31 be used to indicate cacheability. Such a system can then possess up to 2 Gbytes of physical memory. The virtual address range available to the programmer is not affected by this convention.