The S4406Q can be tailored to individual system clocking requirements. It allows 32 configuration options over a range of output frequencies from 20- to 66MHz. Each output can drive 35pF or two to three typical input clock loads. All 12 outputs switch within 500ps of each other, with less than 500ps of jitter. Two or more can be used for systems requiring more than 12 outputs.
Sample parts are available now.
FPGA design tool Programmable logic device and field programmable gate array designers can use TotalDesigner, the full package with the latest version of CUPL, on the 7000 family of Xilinx erasable programmable logic devices. When programming Xilinx FPGA devices, the complete design can be done in CUPL, as all device features can be accessed and specified directly from the CUPL language. Existing CUPL users can upgrade to the TotalDesigner package. Expected shortly is version 4.6, which among other upgraded features will include VHDL support. The first two are HLPE and RCE, intended as the first products in a suite of RC extraction and analysis tools.