Mark Heinrich One of the biggest challenges facing modern computer architects is overcoming the memory wall .
Technology trends dictate that the gap between processor and memory performance is widening.
Even though good cache behavior mitigates this problem to some extent, memory latency remains a critical performance bottleneck in modern high-performance processors. Although current high-speed systems have improved memory bandwidth by using heavily pipelined clocked architectures, these techniques do not improve memory latency and they burden the memory controller designer with a number of complex timing constraints. The latter benefit is the key to transparent support for active memories.