These RPUs have small inter communication costs and the overall optimization problem resumes to the minimization of the critical path length. The algorithm uses the max flow min cut computation iteratively to find k partitions. Results comparing the latency of the solutions are neither presented nor examined. Symposium on FPGAs, Monterey, CA, USA, February 22-24, 1998. Specialized configurable architectures which are utilized for speeding up specific applications are replacing some ASICs.
Some applications also exploit optimization based on a specific input instance of the computation.
New algorithmic techniques are needed to schedule the computations. Existing algorithmic mapping techniques focus primarily on loops in general purpose programs. Partitioning sequential circuits on dynamically reconfigurable fpgas . In IEEE Transactions on Computers, June 1999. Partitioning sequential circuits on dynamically reconfigurable fpgas .