They crash themselves and their computers a lot. This makes labs frustrating. They waste a lot of time, it s hard to get through labs. Good programmers have fewer problems with Verilog. Some of these problems can change from generation to generation of the design software.
Students often do things like specifying delayless loops.
This causes system to have a slow response time due to infinite looping. It is easy to describe circuits that are impossible to build, and not realize it. Sally Thurman suggested that students could be encouraged to do better design prep work before lab, and better testing and debugging skills and use. Due to use of verilog, an object oriented design approach would likely be useful. For debugging, the following possibilities present themselves as potentially useful here.