Responsible for architectural development, scheduling and planning, and team resource allocation. Additional development to provide MPLS, DiffServ, Classification and Forwarding routing capability.
Team shares responsibility for processor architecture specification and design validation.
Interfacing with SQE, Marketing, Support and Customers. Provided support for existing software and firmware platforms. Led subsequent development effort of Cell Switching and DS0 switching. Active involvement in performance analysis and architectural enhancement. Developed release notes and supporting documentation.