As processing power of hardware accelerators increase and developers start moving over to higher resolution textures, bandwidth has the potential to become a limiting factor in performance. One solution is to move the memory onto the accelerator silicon. This allows hardware architects to use 512bit or even 1024bit data paths to access the embedded memory with relative ease. The second solution to the bandwidth problem is the one S3 has already implemented and 3dfx is planning for their future chipset. This solution is texture compression.
Texture compression is the process of removing redundant image information from the texture data.
The texture compression employed in FXT uses a lossy compression algorithm which generates textures with the same compression ratio every time. Since RAM prices fluctuate and don't go down as steadily as one would like, increasing onboard RAM can become very costly. Current boards have up to 32MB of RAM, but future products will likely wield anywhere from 64 to 128MB of texture storage power.