After 15 years and more than 1,400 successful translations, AMIS knows one thing for certain customers who plan their FPGA design around converting to an ASIC will save valuable time and money when their FPGA is converted. Use synchronous design. Asynchronous timing issues present the biggest conversion problems.
Synchronous design eliminates the problem altogether.
Synchronous means one external clock and one external reset to each and every sequential element. EDA tools such as static timing analyzers and test software have difficulty with latches. If possible, use a flip-flop instead. Spreading high-drive pins around the package will solve the problem. Develop a test bench.