The most common conversion problems typically involve circuits with internal timing problems, such as races and hazards. Often these circuits are developed with a very loose FPGA-design approach modify, program and test. It is not uncommon for designers to simply add gate delays until circuit operation is achieved. Subsequently, when the circuit is converted to an ASIC, the delays shift, the simulations fail and the fun begins. Given the size of today s complex circuits, it is essential to adopt a more reliable design approach.
Synchronous design is effective because it virtually eliminates timing issues.
This means a synchronous design can be easily ported from an FPGA to an ASIC, or between any two technologies, for that matter. The only issue remaining is performance. The truth is synchronous designs are very easy to create. Simply put, the definition is that all sequential elements in the design, such as flip-flops, registers and memories, are clocked by a single common, external clock signal. They re also all set or reset by a single, common, external reset sig-nal.