You can do this repeatedly to see the effect of a series of CPU reads and writes. The address is split into tag, index and position, and the result of the access is displayed. The affected cache line is shown in green.
Valid blocks are light gray, invalid ones are dark gray.
Note that this cache simulation ignores write misses and invalidates on write hits for a write-through cache. Other options will be added in a future version. Hence all blocks are written back whether they are dirty or not. This will be fixed in a future version.