Simulator ensures quick transition from design to fault simulation.
Capabilities such as distributed fault simulation, statistical methods, and fault list management create a highly productive test environment. To execute this model, the simulator uses an internal instance of the Verilog-XL Simulator to simulate a test vector. This vector is input using any method appropriate for the Verilog-XL Simulator, including Verilog RTL, PLI, a vector file, or others. The Verifault-XL Simulator executes its simulation by evaluating a good machine in parallel with a concurrent set of faulty machines. These faulty machines are created by injecting faults into the design.