The Sparc architects use the word trap to designate both. Sparc recognizes traps listed in Table 12.1 on page 297 of Paul. S bit of PSR is stored in the PS bit. CWP is decremented so that handler can use local registers of next window. ET set to 1.
Traps have highest priority.
Notice that PIL is only 4 bits long. An interrupt or trap cannot interrupt an ISR unless that ISR has reenabled ET . Priorities on Intel machines Intel machines have two interrupt levels maskable and nonmaskable . You should understand trap handling on the Sparc processor.