This page describes a delay-insensitive ram cell used for asynchronous logic. This cell is based on a standard 6-transistor static memory cell. The idea is to use three-state inverters instead of using normal inverters, and to write high values to the cell instead of low values.
Verification is possible because it is possible to read when the negated output goes low.
High drive capacity. Low sensitivity of Vcc. The cell acts dynamic when no Vcc is applyed. No transistors drives against each other during write operation. That means no spikes at Vcc to the cell.