This tiled structure provides both high performance and low energy consumption by allowing distributed parallel computations on local data.
Software can trade energy and performance by varying the number of tiles allocated to a task.
In addition, each tile has an unprecedented level of fine-grain software power control to enable deactivation of unneeded microarchitectural components. We expect that much of the compiler work will also be applicable to existing commercial architectures. To evaluate our approach, we are developing a fast and accurate energy-performance simulation framework that will enable us to simulate complete microprocessor designs running large scale applications while gathering detailed energy statistics. Complete energy-performance simulator for baseline architecture. Our analysis will be at a higher level than previous studies, concentrating on how compiler usage of the hardware affects energy dissipation.