Design of basic communication systems are required at a block diagram level. Week 10 Design and test of linear oscillator circuits. Basic feedback and gain networks are simulated and tested. State machine design, simulation and test using GAL architecture. Students utilize an industry standard PLD compiler tool.
Students interface different memory types to a basic microcomputer.
Designs must include worst case timing and drive analysis and PLD logic may be used as part of design. Design must consider worst case timing and drive specs. Students test interface by writing and executing a simple assembler program. Oral presentation and submission of final design projects. Copyright 1999 by the Department of Electrical Engineering and Computer Science at the University of Wisconsin-Milwaukee, all rights reserved.