Since there is an optional flip-flop for retiming, each LUT can be used for combinational or sequential logic. There are many tradeoffs between them. For instance, FPGAs do not use crossbar or mesh connection for interconnects due to area and delay constraints. The main feature of FPGA interconnection is the hierarchy of short, long and dedicated connections. There are also some special features such as corner turns and joining segments.
Vendors usually distribute different connections statistically.
XC3000 devices are the second generation FPGA family of Xilinx. The left corner figure gives a large view of possible connections of XC3000 devices. There are also a limited number of long vertical and horizontal lines. There are switch boxes to join those local segments and thus allow programmed interconnections between CLBs. The right-upper corner figure shows the legitimate switching matrix combinations for each pin.