Megacell configurable as a Target only, Master only, or both. FIFOs can be included into either the Target or Master or both.
Target includes both delayed transaction and posted write queues.
Common microprocessor type backend interface. Fully compliant with PCI Local Bus Revision 2.2. Available in RTL source or gate level netlist. Embedded scan for testability available with PCI core netlist. Enhanced Image Common Microprocessor Type Backend Interface Interface includes microprocessor read data, write data, and address buses.