For instance, programming a system with 1T-SRAM would be identical to programming a CPU with normal memory. We come upon several new approaches for intermediate models, where there is a fast main CPU, that can spawn off simple, memory-intensive ops to the memory. From a programmer's point of view, this can often be hidden in lower-level APIs. The memory would then block on all accesses to parts of memory where it had not yet finished processing. For a simple, but quite sub-optimal approach, one could also treat programs in OO blocks of data and operations that deal on that data, and having message passing return immediately, rather than having it wait.
Several architectures introduce unique sets of problems.
For instance, FPGAs require the programmer or compiler to configure the FPGA, and then add difficulties swapping. VRAM included a funky shift-register mechanism that allowed it to simultaneously send refresh data to the monitor, while handling normal memory transactions. This was a clearly superior approach. It died, as it turned out that it was not economically feasible because it required a very different manufacturing process from conventional memory. Few people write papers on failed projects, so it is difficult to answer why people don't manufacture some sort of technology.