Physical Compiler has now been adopted as a standard part of the Unisys ASIC design flow. Before adopting Physical Compiler, the conventional Unisys back-end flow required intensive designer intervention resulting in design schedule unpredictability. With Physical Compiler, we saved several weeks of manual iteration on a very complex design.
Tape outs are the true measure of success for an implementation tool.
This tape out builds upon the success that Synopsys' Physical Synthesis has demonstrated through more than 25 tape outs of networking, communications, computing, and graphics chips. Physical Synthesis brings key physical design considerations to the front-end, allowing RTL designers to rapidly achieve high quality of results. The overall design flow includes Chip Architect design planner, Physical Compiler unified synthesis and placement, and FlexRoute top-level router. Pricing and Availability Physical Compiler is available now. Support and maintenance options vary and are in addition to the product license.