Packets contain headers that are used by simple, extremely fast switches to perform routing. The switching hardware also provides flow control. Each computation node has a processor dedicated to handling messages with direct access to main memory. The processor on the Myrinet interface card shields the main processor from interruptions generated by the Myrinet, and the direct memory access hardware can transfer data directly into physical memory. If the operating system has set up virtual memory so that this physical memory maps into the address space of the application receiving a message, then there is no need to copy the message within main memory.
Message passing without a context switch into the kernel is the essence of user-level networking.
These techniques will become commonplace in the future because of recent standardization efforts led by Intel, Microsoft, and Compaq. In this application domain, both high bandwidth and low latency are critical for acceptable performance. VI Arch messaging is designed to operate asynchronously with the main computation to allow the off-loading of message processing onto a coprocessor. Furthermore, VI Arch messaging is connection-oriented, and it requires that the destination buffer for a message be allocated in advance. The buffer must also be locked into physical memory.