This is a hardware counter used by the cache which is initially set to the same address as that output by the processor. On the 1st memory read by the CPU, the ATC loads itself with the same address. When the CPU issues the next address, the ATC checks to see if it is within the range of the cache table. If not, the CPU is connected dircetly to RAM, then the ATC updates itself and clears the cache table entries. Performance is increased using cache memory, but factors affecting its performance are, program activity cache size Programs with jump statements impede cache use by continually flushing the cache entries.
Some processors support both instruction and data caches.
This overcomes the cache becoming flushed by a memory write. When using a data cache, you need to implement some method of handling writes to locations which also appear in cache. The write through method writes both to the data cache entry and system memory simultaneously. This prevents cache and system data getting out of step. It however, requires more complex hardware to implement.