At the end of an integration period the data in the accumulators is parallel-loaded into 1024 output registers.
New integration can begin immediately.
Only three, of the four possible, data words are valid. Data Cascading Stream A and Stream B are output, after an extra delay for synchronization, as A0OUT, A1OUT, B0OUT and B1OUT . These pins can be tied to the A and B inputs of another chip, to form cascades with multiples of 1024 lags. To avoid high-speed global control signal distribution, control signals are passed through the chip, with an extra delay for synchronization. This mechanism avoids problems associated with high-speed data bus distribution.