First was Dr. Martin Walker, now Marketing Director of Digital. Some of the processors have a clock rate of 440up to 620 MHz. He noticed a reconvergence of the SMPs and interconnected systems for scientific and commercial applications. One of the major issues of the Digital system is the Memory Channel Interconnect for SMPs.
Protocols are no longer necessary, and direct memory to memory transfer is possible.
With the Alpha instruction set architecture there is no compromise on speed. The next generation, the EV7 is in design stages and the EV8 is just in the first step of design. It designed for the needs of application performance. The processor follows the PA-RISC architecture. Thus all of the applications that run on H-P workstations can also run on a processor of the Exemplar.