Teaches language syntax relevant to a hardware designer. Numerous examples show how the language is used for hardware design and test. Concepts presented in each section are reinforced with exercises and labs. At the completion of the course the student will be ready for their first project in VHDL hardware design and test. Day 2 Standard Synthesis Packages Design Objects Design Units Design Hierarchy Subprograms Day 3 VHDL Design Flow Foundations of RTL Code RTL vs.
Questions are welcome.
Bring problematic code. Copyright 1999 SynthWorks Design Inc. All rights reserved.