All instructions have one, two or three source operands and are non-destructive in nature. The 128-bit wide vector operands consist of multiple, packed and scalar data elements. Loads and Stores. AltiVec loads and stores use indexed addressing with address operands coming from the general register file. All data operands are aligned to their natural size boundary and scalar data elements are transferred on their natural byte lanes.
Misaligned data is handled explicitly with the data manipulation instructions.
Four unique prefetch streams are provided, each described by a block size, stride and count. A deficiency of classical SIMD architectures is that the parallelism is lost when the organization of the data does not exactly match that of the machine. AltiVec solves this with a set of powerful data manipulation instructions. Permute creates a result vector consisting of any 16 bytes selected out of any two source vector registers and arranged in any arbitrary order as specified by a control vector located in a third source vector register. Besides its data reorganization capabilities, permute performs other useful functions such as table-lookups which are prevalent in DSP algorithms.