A resolved subtype is a type combined with a resolution function. A resolved signal can be assigned by multiple signal assignments. Depending on the value of each driver, the resolution function determines the effective value of the signal. A guarded signal is a resolved signal with drivers that can be disconnected. They can be applied on all types supported by the subset.
Simulation is performed in zero delay mode.
Then, stop the simulation. Assert statements are ignored by the logic synthesis tool. This is taken into account by the logic synthesis tool in the optimization process. When the value of an output is 'D' the logic synthesis tool may turn it into a '1' or a '0'. Here is the description of an adder with an accumulator register.