Ideal first VHDL state machine lab assignment, many different variations on train operation can be given as different assignments. A newer version of this model can be found on our book's CD-ROM and is described in more detail in chapter 7. Very simple design that contains just the basics of VGA video signal generation. Uses both RLE encoding and color dithering. Plug in mouse and monitor, power up UP1, and then download this file.
Mouse moves cursor and buttons change cursor color.
Additional documentation with source code can be found in our lab book. Construction details and sensor info can be found in the lab book. Powerpoint presentation on UP1bot Georgia Tech Student Design Projects Doug, Gauthier, and Mike's Pipelined DLX and Video Terminal Project Page Contains a VHDL UP 1 tutorial, and a 5 stage pipelined DLX RISC processor design. The processor has a video terminal with drivers for keyboard input and video character generation for output. Runs on a 10K70 - UP1.