The future of the technology is open-ended, beginning with the obvious promises of improved power and performance, but including more subtle advantages and reaching to new, as yet unimagined structures in silicon. While both designs reported gains in power consumption and speed over comparable bulk CMOS designs, both were relatively simple extensions of existing circuitry and methodology. Basically, circuits from existing CMOS CPUs were picked up, plopped down on an SOI process, and only modified if they broke. But an exciting future awaits in the next phase of SOI development. But that will be only the beginning of the evolution, according to the IBM engineers.
More advantages are to be gleaned by changing circuit designs as well as transistors.
In SOI, stacking is good, where in bulk CMOS it's a problem. As SOI opens up new possibilities, it also seems to remove old problems. What may be less obvious is that it also eliminates parasitic diodes and transistors that are the plague of bulk CMOS device modelers' lives. In this way, the move from bulk CMOS to SOI may have the same happy effect on device modeling, isolation and packing limitations that the move to copper has had on interconnect modeling. It just makes life simpler.