For Tcl examples, refer to the Tcl examples web site . Synthesis Altera subscriptions include the Exemplar Logic LeonardoSpectrum-Altera tool for VHDL or Verilog HDL synthesis. The timing-driven router algorithms in the Quartus II software intelligently prioritize which routing resources are used for a critical timing path in the design. The Quartus II software further improves fMAX results by supporting the latest device architectures such as in APEX II , APEX 20KC , and Mercury devices. Verification Static timing analysis is a method of analyzing, debugging, and validating a design's timing performance.
Timing analysis measures the delay of every path in the design and reports the design's performance.
Altera software subscriptions now include the Mentor Graphics ModelSim-Altera HDL simulator. ModelSim-Altera also gives Quartus II users full support for VHDL and Verilog HDL test benches to perform automated and fully repeatable testing of large and complicated designs. SignalTap logic analysis facilitates the verification process by integrating the functionality of a logic analyzer within the software. The Quartus II software inserts a logic analyzer megafunction that incorporates a logic analyzer's functionality, including trigger options, into the design. Data is captured and stored in the device's embedded RAM block and reported to the Quartus II waveform viewer via a download cable.