Raw chips will be able to achieve clock frequencies on the order of 10 to 15 gigahertz by 2010, compared with frequencies of about 500 megahertz for today's microprocessors. After the first signal value arrives at its destination, subsequent signal values will arrive at the end of every clock cycle, thereby increasing the signal throughput, or carrying capacity, of the wire. The compiler also attempts to place signal values in memory locations close to the function units that will process the data. This minimizes the number of cycles that the signal values spend traveling from one location to another. The next step comes from the realization that because the chip's wires are such a critical resource, using a wire to connect only two locations on a chip is wasteful.
Multiplexing is similar to merging the feeder roads from several cities into a superhighway.
Signals from the feeder connections arrive at one end of the wire segment, and a multiplexer constructed from logic gates ensures that only one signal is transmitted along the segment during a given clock cycle. The compiler programs the multiplexers to select the appropriate signals at the right times for each application. Just as a superhighway carries more traffic than a feeder road, a multiplexed wire carries many more signals than an ordinary wire. Finally, the compiler routes the signals along the optimal pathways by precisely scheduling the signals to meet the demands of the application. The faster data input will yield far better performance and energy efficiency than is currently possible.