The designs prove that all engineers are facing the same grand challenge. In contrast, Intel Corp. is forging a novel path toward explicit parallelism, relying on a new kind of cooperation between the hardware and the compiler in its IA-64 architecture. HP worked with Intel to define the IA-64 instruction set. To date, the fundamental tool for keeping the execution units humming has been to maintain a pool of ready instructions in the CPU and to dispatch as many as possible on the next clock. The problem, according to architects, is that conventional programs usually don't make enough instructions ready at any one time for the CPU to dispatch more than a couple in an average cycle.
Memory latency can be a more expensive problem.
Architects' first line of defense has been to build big, single-cycle L1 caches, in an attempt to minimize the number of L1 cache misses. But the hardware cost of this approach is growing. Taking a different approach, the IBM Power3 design team included only 32 kbytes of instruction and 64 kbytes of data cache, but made each cache 128-way set associative. Another way to reduce the miss rate is to cheat. Instruction sets in both Sun's Sparc V9 and IBM's Power3 include prefetch instructions that, in effect, tell the CPU to preload certain information into its L1 caches.