However, if there is more than one interrupt in a system, this practice often leads to problems down the line relating to having one ISR block out others for extended periods of time. The most critical problem with lengthy ISRs is causing the system to fail maximum latency requirements. The maximum latency requirement is often determined by the most frequently occurring interrupt. In other words, when one interrupt is being serviced, all interrupts are inhibited. Because of this arrangement, the minimum guaranteed latency cannot be shorter than the maximum execution duration of all ISRs.
Some processor architectures allow stacking ISRs.
Usually, this is implemented by allowing the ISR of an interrupt to disable only interrupts of equal or lower priority. As a result, higher priority interrupts can interrupt the ISR of a lower priority interrupt. Satellite technology also involves a large expense, both for the satellite itself and for the ground control facilities. The traditional answer is that an interpreter scans the source text as it executes the code, while a compiler scans the source once and generates machine code that the processor executes directly. However, the distinction becomes fuzzy if you look too closely at the details.