SpeedSim works within existing EDA tool environments on UNIX workstations. Allows for complex chip designs that require Multiple-Clock Domain support. Enhances performance through support of two logic states to verify correctness of Boolean logic. No timing analysis provided. Achieves fast compilation speeds and low memory usage on very large designs.
Users get the speed benefits of a two-state simulator without losing bus assertion checking.
Supports static detection and notification of Asynchronous feedback loops and correctly simulates Asynchronous feedback loops in-line with Synchronous logic. Ensures fast run-times with exceptionally low memory usage. Comes with the FLEXlm network license manager from Globetrotter Software. All licenses are floating across a site network. This can reduce greatly the number of workstations needed for regression testing.