But this results in a speed penalty, and makes in-circuit emulation difficult, Martin said. FPGA Stuffer partitions at the process level. That's one step down from the module level, since modules are collections of processes and instantiations of other modules. A key advantage of this approach, said Martin, is retention of RTL signal names. These are typically lost because synthesis changes the names.
Most people go through a correlation process, which is a major bottleneck.
It helps with analysis, but the user still partitions the netlist, either graphically or using text scripts. Synthesis first Input to FPGA Stuffer consists of RTL Verilog code, with VHDL support to follow later. The product then builds a database, decomposes the design and kicks of FPGA synthesis. The EDIF file can go into Xilinx placement and routing tools. FPGA Stuffer also spits out an EDIF file for board-level interconnect between the FPGAs.