This advanced level of power provides today s customers with areal density leadership at a reasonable cost. The new TI 'C27x DSP core utilizes a modified Harvard architecture that can be addressed as a single software stack for Von Neumann operations. It features two data read busses and an instruction read bus, with several enhancements aimed at improving code density and performance in interrupt-driven applications in the storage industry. The 'C27x provides this level of performance at no additional cost in hardware, opening the door for developers to take optimum advantage of the DSP s advances in integration and power. Furthermore, it opens the door for the design team to focus on creating product innovation and differentiation that will drive the future of storage product electronics.
More compact code executes faster, consumes less power and reduces memory cost.
A single instruction directs the processor to read data from memory, modify it and write it back to memory. This single, or atomic, instruction provides a distinct advantage over traditional load-store or RISC architectures because it generates less code, executes the code faster and protects the operation from being corrupted by interrupts. With the 'C27x devices, these logical or arithmetic operations can be performed on any memory location. In developing the 'C27x architecture, existing firmware code for all major drive manufacturers was closely examined. Virtually all of the most commonly used instructions were implemented as part of the 'C27x s final instruction set, allowing drive designers to work as they have with previous generations of less capable MCUs.