An internally generated high rate processing clock allows symbol processing at rates higher than the analog sampling rate. The technology offers a high level of integration of programmable logic and embedded memory. The prototype hardware used to test the digital IF PLD consists of a daughterboard containing an EP20K400E PLD with an adapter socket, which maps to the footprint of the ASIC package. A production radio signal processing module, with ASIC removed, serves as the host for this prototype board. The daughterboard also has two 14-bit DAC devices which enable monitoring of a complex signal.
Monitoring is done in both the frequency and time domain.
The digital IF PLD uses a high rate processing clock to drive hardware blocks at a sufficient rate to meet the sample throughput requirement. The Altera PLD, utilizing an on-chip PLL, internally generates a processing clock operating at 20 times the input sample rate. The system architecture uses a clock with enable topology, which distributes a high rate system clock to all control and storage circuits. Control logic and state machines generate enable signals for these circuits. An enable signal must be active for the clock to affect a circuit's output.