It has become clear that new multiprocessor computers are required to solve the problems ahead. The objectives of this research are to develop efficient parallel algorithms for VLSI CAD tasks that can utilize the computing power of a wide range of parallel platforms that are becoming available to the community, with the eventual goal of reducing the design turnaround time of complex chips of the future. In this research we are investigating parallel algorithms for placement, routing, layout verification, logic synthesis, test generation, and fault simulation, and behavioral simulation. The parallel algorithms are designed such that they are portable across a range of parallel machines, including multiprocessor workstations, shared memory multiprocessors, message passing multiprocessors, and networks of workstations. In this research we are investigating scalable, data partitioned parallel algorithms for placement, routing, layout verification, logic synthesis, test generation, and fault simulation, and behavioral simulation.
Work is ongoing on some of the above tools.
State assignment of finite-state machines. Test generation for sequential circuits based on a genetic algorithm. This work has been funded by the Advanced Research Projects Agency, by the National Science Foundation, and by the Semiconductor Research Corporation. We are working closely with several CAD companies such as Cadence, LSI Logic and Sierra Vista Corporation in transferring some of these parallel CAD tools to industry. Unfortunately, to extract all that computational power from these machines, users have to write efficient software for them, which is an extremely laborious process.