In a highly competitive market, the equation is shifted even more towards preservation of the lowest possible cost without sacrificing performance. If one applies Occam s Razor to analyze the needs in a commodity as opposed to a pure performance design, it is clear that separate SRAM cells serving each individual row of memory are a powerful albeit expensive feature. That means that there is no need for additional bit and data lines only a rearrangement. The major modification is to slightly offset the DRAM array in each chip s quadrant to make room for the embedded the central row cache in the die. Typical example of a 256 Mbit memory chip.
Output occurs through global data lines.
Instead of moving only the data from cells specified by the CAS along the bit lines into the secondary sense amps, the entire amount of data within an activated row is moved into the row cache. Consequently, a read request will call data merely from the fast SRAM cells. At the same time, the DRAM array goes back to idle state as soon as an auto-precharge all command has been executed. Replacing the secondary sense amps with an SRAM register reduces the risk of talk-back to the primary sense amps when forwarding the signal to the global data lines. Therefore, the signal can be stronger.