The initiation interval is the number of cycles that must elapse between instruction issue to the same unit. For pipelined units, this interval is 1. Therefore, FP pipelined units may have multiple outstanding operations, which are initiated every cycle. Result can be used after one intervening cycle. Note that the forth instruction after the add can use the result of an FP Add.
Structural hazards can occur for the divide unit.
The number of register writes that occur in one cycle can be greater than 1 . Several instructions can reach WB in a single cycle because of variable length instructions. This could cause a structural hazard if the CPU can only write one register per cycle. WAW hazards are now possible and must be detected. This also causes problems with exceptions .