Here we limit ourselves to the way an FPGA can be used for implementing a shogi program.
Pipelined designs are well structured and map well onto configurable devices.
Pipelined designs have reduced and predictable delays because they use mostly local interconnections. Hence , mapping loop computations onto pipelined configurations proves to be very effective on configurable hardware. We compare the effectiveness of our heuristics against a greedy heuristic based list scheduling. Our mapping techniques promise potential performance improvement on several classes of FPGAs. In Section 2, we describe some related research work which addresses similar issues.