Power, in Borkar's view, is a potentially more serious issue than better-known problems relating to interconnect parasitics or clocking. In Intel's experience, Borkar said, frequency has doubled with each chip generation every 30 months. Transistor density has doubled during the same period, and transistor count has doubled every 18 months. This is due not only to an increase in active power, but also leakage power, which will make the situation worse. One possible solution, he said, is to place more memory on-chip.
Memory is more power-efficient than logic.
But in general, Borkar said, designers will have to trade off some performance to reduce power. This might mean using static logic instead of the higher performance, but more power-hungry, domino logic. In a second presentation, Sani Nassif of IBM's Austin Research Lab called for better ways of handling process variations than design rules or worst-case corner simulations. He argued that variability and yield are inextricably linked to physical design. Complicated phenomena are abstracted into rules that are checked for compliance.