The designers previously used to draw the full layout of the module using layout editors. This was very time consuming and error prone because the design had to done right from the functional specification to the layout design. Nowadays the designers are using cell-based design methodologies, which is easier and has a fast turn around time. Here the cells are pre-laid out characterized, and put in the library. The designer manually translates his design from functional specification down to gate level, and uses a schematic editor to capture and simulate the gate-level design.
Physical design is done automatically by using placement and routing tools.
These are used to describe the structure or behavior of a digital system for simulation or for synthesis. This helps people without much knowledge of circuit design to design hardware in less time. HDL descriptions provide technology-independent documentation of the circuit. VHDL is recognized as a standard HDL by IEEE and is widely used these days. A design code written in VHDL is usually run through a VHDL simulator to verify the behavior of the modeled system.