Based upon such metrics, or upon occurrence of a particular event, the user can interrupt the simulation and redirect the testbench. Alternatively, the user can halt the simulation and call for a coverage report. Users can rely upon CoverMeter's query facilities to assure a given simulation session is contributing to coverage goals as expected and continues to warrant the simulator resources applied. CoverMeter Leads the Industry in Simulator Throughput . CoverMeter PLI calls have benefited from advances in instrumentation techniques, making CoverMeter substantially faster with less drag for all Verilog simulators.
Users appreciate speed increases as much, or even more, than functionality increases.
It's high throughput that makes routine use of code coverage really practical. VCS users can direct CoverMeter execution from within VCS command scripts, simplifying their use of code coverage with all VCS operations. Coverage Throughout the Design Flow CoverMeter is useful at all stages of the design verification process. Most users first test their designs for Statement Coverage, then move to Condition Coverage. Toggle Coverage completes the package, measuring activity in registers and nets.