In VOQ, each input buffer maintains a separate queue for each destination port. Switch scheduling is thereby optimized due to the maximum number of routing options. Another common switch throughput performance enhancement involves over-speeding the switch packet transport rate. Actual switch design may not be impacted much, except for the power increase caused by the higher clock frequencies. Complexity in a switch resides in the scheduling mechanism.
Schedulers receive packet destination port data via each input buffer.
From this input, they determine the highest possible traffic route through the switch for the next switch packet transport cycle. Switch configuration is commanded, and all input buffers are directed to send the specific packets that are destined for the selected output ports. Three more hurdles hinder switch scheduler design. Fairness doctrines must be incorporated to allow input ports equal access opportunities to the same output port. LEO traffic revenue models generally provide for different levels of service.