The circuit presented is a 5-stage partially pipelined ring that iteratively computes quotients. The ring is controlled asynchronously. By using enough stages, overhead for computing control signals is eliminated. This is a complete and very understandable design for a divider. The advantages of asynch are well highlighted.
Performance is impressive.
The claim of zero overhead is questionable, given that two-rail logic leads to more transistors and more wires. Some discussion of two-rail vs bundled is given, but I didn't follow much of it. It takes as granted issues that I'm still struggling with, and solves problems I either consider irrelevant or simply don't understand. The idea is quite simple. It's questionable how applicable it is, since it may not be easy always to predict when functional units finish early.