PKS benefits design teams employing an ASIC flow, where an ASIC vendor performs design finishing, or a COT flow, where design finishing is performed internally. Both tools use PKS concurrent optimization which simultaneously optimizes a design's logic, placement, and global routing. They also have common synthesis, placement, routing, and timing engines. Performance and design stages PKS integrates physical technology with synthesis to deliver a synthesis system with perfect timing correlation and superior quality of results. With PKS, designers are assured of having early and accurate timing information which enables a highly productive design flow free of timing closure iteration.
Productivity is improved through reduced partitioning and scripting.
High capacity and performance is requisite for each. High-level synthesis transforms PKS includes all synthesis transforms found in the BuildGates synthesis tool. PKS is capable of full restructuring, cloning, buffer insertion, re-mapping, and sizing operations. Incremental full chip static timing analysis PKS' integrated high performance incremental static timing analysis engine delivers the performance and capacity traditionally associated with standalone timing tools. PKS also supports placement-driven scan chain reordering which clears any scan congestion and finalizes the placement of the design.