Inc. All rights reserved. This paper discusses an approach using area interconnect to achieve high performance for an experimental multichip microprocessor. The described method is being used in the PUMA project at the University of Michigan to design a processor that has a clock speed goal of 1 GHz. The use of area array pads to provide high bandwidth interconnections between the chips, and low inductance power connection to the MCM is also essential. Three stages of MCM development for the project are described.
Results show a good agreement with the published data.
By contrast, this technique has efficient calculation and flexible handling of conductors having arbitrarily shaped topology. We have designed multichip modules using three alternative technologies for a variety of applications, and have used the results to study the impact of miniaturization and passive component integration on module size, distribution of net length and estimated cost. We find that the advanced, highly miniaturized technologies result not only in higher packaging density and shorter average net length, but in lower estimated module cost as well. Passive component integration can also lower module cost especially in mixed-signal and analog applications. The electrical properties of the new structure are deduced from the well-known coaxial and triplate transmission line models.