We have built a sophisticated model for power effects of register allocation changes since it can change the number of instructions issued as well as the program's memory traffic. This model is incorporated in the simulator and we are currently exploring its use at compile time to help guide the per-function register allocation process. Using global register allocation we have been evaluating the bounds on power savings from this method. We have also been exploring pure hardware and compiler-driven management of L1 caches. L1 and L2 caches to save power.
Preliminary results are very promising.
The first two mechanisms were targeting cache hit energy dissipation. It is accomplished by changing fetch size to affect the number of bytes read and transferred between L1 and L2 cache on a miss. This can be done purely in hardware or under compiler control. We are currently exploring methods for AOT annotation generation that can be incorporated in our architectural description language thus providing a systematic path from developing architectural smarts to their utilization in compiler algorithms. There are three major components that define the activities undertaken in this project.