The architecture has 8 registers, R 0 through R 7 . All instructions and registers are 16 bits wide and use two's complement arithmetic.
Memory is word addressable .
The program counter is separate from the general purpose registers. The register R 7 is treated as the link register. This register is read by the JOO instruction. Finally, for extra credit, a specification is provided for a performance counter register. Once the counter has reached this value it should not change.