This leads to a degradation in the correction performance compared to the continuous decoding where each and every bit has the observation length of 50. A code has also been prepared in VHDL language for this algorithm at VTT Electronics , Finland. Using Cadence program a layout of the SOVA chip has been generated. Tests have been conduted using the paralle port of personal computer. Since this is our first implementation, we have tried to keep the circuit as simple as possible.
Plans are on to make an efficient circuit for continious block oriented communication systems.
As the block code is variable, the decoder can be adapted to any system. This circuit allows to test different algorithms with different parameters. The core of the decoder is written in VHDL such that it can be used by other platforms. Please mail to us for further information. The following figure shows the development of the results.