D in Electrical Engineering required. Must be able to construct physical device models for use in circuit simulations, define modeling test patterns and extract typical device models for various foundry processes. Must be able to calculate worst-case models. Must be able to analyze quantitatively device mechanisms such as impact ionization and breakdowns and other parasitic device characteristics. Will also interact with process development engineers on issues relating to device behavior.
Position requires independence, priority setting, and support of user community.
Position reports to VP Engineering. MSEE and minimum of 5 years modeling experience required. Simulate the designs using HSpice and verify schematics using Verilog. Supervise the layout of the chip and debug the new designs in the lab. BSEE, MSEE preferred with emphasis in VLSI circuit design using semiconductor technology.