The maximum specified operating frequency and critical path performance are usually clearly defined. Balanced path design is essential in communications circuits and has its own restrictions and tracking requirements. Macros selected to allow speed to be achieved may increase power while macros chosen to allow balanced delays may increase cell utilization. Cell utilization can determine which array in a series is acceptable, and the larger arrays do cost more. Cell reduction techniques may affect final speed, power and cost.
Modular designs are an important reliability and testability issue.
Modularity may require additional macros for degating while testability may require additional macros for test point monitoring or circuits such as scan-path. Refinements to the circuit testability are what should be required at this point in the design cycle. DFT circuits are easier to develop test vectors for than non-DFT circuits and they require significantly less vectors. The size of the test vector set also has an effect on cost. It is more costly to develop a large set of vectors, more time consuming to fault-grade them and takes more tester time to test the die.