Depending on the wiring of these 3 pins, software in ROM configures the video hardware for one the supported display types. In a number of cases the design was optimized for high performance over low cost. However, this results in having to perform 3 separate memory accesses for each 24-bit pixel read from or written to the frame buffer. However, when frame buffer memory is placed directly on the processor bus, this approach results in a nearly 3X performance degradation. This was judged unacceptable for the Quadras.
Performance is improved still more by another frame buffer architectural feature.
Frame buffer memory in the Quadras is organized into 4 'banks' of 512 KBytes per bank. As mentioned earlier, Quadra VRAM can operate in fast page mode. In addition, each bank of VRAM operates in fast page mode independently of the other 3 banks. This causes the number of in-page 'hits' to increase, and thus improves the effective bandwidth into the frame buffer. This memory organization improves performance during certain commonly performed graphics operations such as vertical scrolling.