This circuit, which is described in VHDL, applies stimulus to your design description. The Data Source can be a FSM producing waveforms or stored waveframes. The observer is optional . Data Types VHDL contains many types of data structures. All VHDL objects have a type associated with them.
Processes are the basic unit of behavioural descriptions.
A process is considered a series of sequential statements which represents a single action during simulation. A process is executed until a wait statement or the end of the process is reached. All statements within a process are sequential, the execution time of a process can be thought of as zero. Figure 6 shows the general structure of a process. The sensitivity list is required if the process doesn't contain a wait-statement, otherwise the process would be permanently executed and hinder the execution of any other statements.