The output assumes the appropriate level within 200ns after the falling edge of the input. The response to a single high-going pulse. This is astonishing. Our observations at the output show that Part C is also in a static state during the pulse. This is hard to believe, so we have reinforced this finding through many separate types of observation, and all agree that the circuit is inactive during the pulse.
Power consumption returns to quiescent levels during the pulse.
Glitches sufficiently strong to circulate for tens of microseconds could be expected to trigger the glitch-catcher, but it detected no activity in any of the recurrent loops during an input pulse. The simulated circuit never reproduced the FPGA configuration's successful behaviour, but did corroborate that the transient as the circuit enters its static state at the beginning of an input pulse is just a few tens of nanoseconds, in agreement with our experimental measurements of internal FPGA signals, and according with the logic analysis. We then built the circuit out of separate CMOS multiplexer chips, mimicking the way that the gates are actually implemented by multiplexers on the FPGA, and also modelling the relative time-delays. We then went back to find the first circuit during the evolutionary run which responded at all to input frequency. Its behaviour is shown in Figure 4 .