For example, the SMV tool verifies symbolically the correctness of communicating reactive systems such as bus and cache protocols. The Symbolic Trajectory Evaluation methodology verifies the complex interactionsbetween the specification and actual transistor-level design of complex superscalar processors. Both techniques have been used on commercial processor designs. Thisvirtual hardware, coupled with new compiler technology, allows new trade-offs between complexity and speed for systems that need to be quickly deployed. Research venues include microarchitectural resource adaptation to application needs, novel architectural design paradigms for power aware systems and techniques for generating energy aware software.
Projects focus on both general purpose and embedded applications.
The Operation-Centric Hardware Description Project is developing a simpler and faster design framework for creation of computer hardware and other digital systems. A novel operation-centric abstraction for the hardware description enables the behavior of a system to be decomposed and described as a collection of atomic operations. At a high-level of representation this permits interpretation by the designer and allows a hardware compiler to exploit parallelism.