Today's superscalar processors are able to issue up to six instructions per cycle from a single sequential instruction stream. VLSI technology will soon allow future microprocessors to issue and execute eight or more instructions per cycle. A multithreaded processor is able to pursue multiple threads of control in parallel within the processor pipeline. The functional units are multiplexed between the thread contexts.
Most approaches store the thread contexts in different register sets on the processor chip.
Latencies are masked by switching to another thread. Sequences of instructions are dynamically extracted from sequential binaries and speculatively executed by different processing elements or in multiple thread slots within a single processor. In case of misspeculation, the results of the speculative thread and of subsequent threads are discarded. Threads start execution as soon as all operands are available. Such threads may be generated with the aim to decouple memory accesses from execute instructions.