Once at the correct output, packets are simply sent, in turn, every time slot. The input buffered switches in this paper use separate input queues that can send any waiting packet. A common way to build a large N 2 xN 2 switch is to use two stages of smaller NxN switches as in Figure 1a. While straight forward, this may not be optimal.
Packets buffer in two stages which, in general, doubles the delay.
In recent years, there has been an increased awareness of the impact queueing disciplines play in high performance packet switches. 711-715, June 1991. This leads to a proportional increase in cost, making it advantageous to keep the required speed advantage as low as possible. Kozaki, T., et al. 9, No. 8, Oct. 1991.