This is a concise description of the LANai3 CPU core. The registers, instructions, and instruction pipeline are described here. Pointers to successive words differ by 4, pointers to half-words differ by 2, and pointers to bytes differ by 1. All instructions are 1 word long. All word addresses must be word-aligned.
Memory storage is big-endian.
The meaning of instructions is tied to the pipeline, and, in the remainder of this document, the instructions are defined operationally, in terms of the pipeline. If this same register were a source in the Register-Immediate instruction, the source register contents for the RI instruction would be those after time 3, i.e., before the result of the memory read is placed into this register. If these two destinations are the same register, the computed value is written, and the loaded value is discarded. However, regardless of the number of wait-states that may be introduced, the processor state changes are guaranteed to follow the pipeline diagrams presented in this document. An unusual feature of the LANai 3.0 processor is that it is a dual-context machine.