In other words, we need data lines in addition to the row and column select lines. In most cases, the data lines are running in parallel to the row select lines. Each bi-directional black arrow represents a pair of bit lines projecting from the 1.SA either to the left or the right into the memory cell array. As a result of this architecture memory cells talk to sense amps on either flank, vice versa, it is the same situation since sense amps are talking to memory cells on either side. For a better distribution of power and heat, current solutions often use 2 hemi-rows as shown above to access the data from the memory cells sandwiched in between.
Red lines are the row seloct lines, column select lines are dark green and data lines are turquoise.
The secondary sense amps and global data lines are purple. There they are amplified again and sent via global data lines into the output buffers. All processes from the point of where the read command is issued until the data are output need to be completed within the time interval allocated for the CAS latency. This means, column decoding, sending the signal into the array, latching the data on the data lines, getting them back out to the secondary sense amps and finally moving them to the output pins, all are part of the CAS latency. All names and trademarks mentioned in this review are the exclusive property of the respective parent companies.