D.F. Wong, Shankar Krishnamoorthy, and P. Moceyunas. Delay Minimal Decomposition of Multiplexers in Technology Mapping International Workshop on Logic Synthesis, May 1995. Technology mapping requires the unmapped logic network to be represented in terms of base functions. Technology decomposition is the step that transforms arbitrary networks to this form. Typically such decomposition schemes ignore the fact that certain circuit elements can be mapped more efficiently by treating them separately during decomposition.
Multiplexers are in one such category of circuit elements.
They appear very naturally in circuits, in the form of datapath elements, and as a result of synthesis of CASE statements in HDL specifications of control logic. Mapping them using multiplexers in technology libraries has many advantages. In this paper, we give an algorithm for optimally decomposing multiplexers, so as to minimize the delay of the network. Experimental results indicate that the quality of the mapped circuits, measured in terms of area, delay, and routability, is greatly improved, when compared to a Huffman tree based AND-OR decomposition scheme. We address the technology mapping problem for lookup table FPGAs.