Hardware speedups in long integer multiplication . The interconnections are configured afresh whenever the equipment is started up, by a program downloaded to the chip. M Shand, P Bertin, and J Vuillemin. Hardware speedups in long integer multiplication . The dotted lines show how the digital stage is being expanded into higher frequencies.
Performance is the major advantage of FPGAs over conventional processors.
The major advantage of FPGAs over ASICs is programmability, which of course has a performance penalty. However , creating a new configuration on FPGAs means designing a new hardware architecture. M. Shand, P. Bertin, J. Vuillemin, Hardware Speedups in Long Integer Multiplication , Computer Architecture News, 1991. The translation from programs to circuits has been implemented within the existing Esterel compiler. We have run very successful experiments using the Xilinx TM based Perle0 programmable coprocessor developed at DEC Paris Research Laboratory by J. Vuillemin et al.