However, if capacitance is entered instead, only charging dissipation is calculated. Then, with an estimate for total power and knowledge of the package we can compute on-chip temperature rise. Most ASICs are spec'd for commercial operation at or below an 85 deg. A similar analysis can be applied to FPGAs, however, in this case power estimation is best calculated at the block, rather than gate, level. A good example is Xilinx's Virtex Power Estimator tool.
Power is estimated by module and category as well as overall.
For power-critical design, simulators are used with test vectors to get more precise estimates of toggle rates. There are also tools dedicated to computing power use, such as Synopsys PowerMill TM . Large currents flow for short periods of time and good design limits fanout and capacitance, keeping rise times short so that short-circuit current is minimized.