In addition, a further goal is the combination of threshold logic with bit-level systolic arrays, a locally interconnected circuit architecture operated in a pipelined fashion. In potentially larger scale circuits such as the 4-bit a block pipelined adder these three terminal LTG's are a fundamental component. For digital application both the layer structure and the device fabrication has to be optimised. Of great importance is the lateral size control of the device area. In this work anisotropic reactive ion etching will be used for accurate mesa definition.
Ohmic contacts are all non-alloyed.
This way access to all electrodes is assured without metal electrodes allowing a total freedom in designing various combinations of HFETs and RTDs for any circuit topology of multiple terminal threshold gates. Based on this technology the demonstrator circuits will be fabricated. The modifications induced by resonant tunnelling in double barriers, and by the digital application envisaged here, will allow for less tight tolerances to become acceptable. The tolerances required in practice will be analysed in order to set-up a full reverse engineering loop. In the next step both, the experimental and simulated device data are inserted in the circuit simulation giving advice which circuit design parameters have to be more or less fault tolerant .