If version 9.2 or greater is used you may now get errors in some of these design files.
Most problems seem to be connected with multiple output assignments in a process.
We have fixed the examples used in the lab manual but have not had time to fix all of the examples listed here. If you note the errors, you can fix the minor problems in the VHDL code in a few minutes. In most cases we have found, several if statements can be converted to a case statement to fix the problems. One such LPM error occurs in the memory LPM blocks in a few of the first edition book's designs. In version 10.0 and higher, it seems that the VHDL netlist reader no longer defaults to 1987 VHDL syntax.