It is a two-pass assembler, so program counter labels may be used by the programmer and they will be resolved by the assembler. This is only necessary if the designer wants to modify or add instructions to the instruction register. The example.tar package contains a sample design for memory, and a sample top-level design file. If new instructions are needed, the stack processor can be modified, but this requires detailed knowledge of the processor's internals. To function properly, the SP requires the system memory behave in a well-known way.
Memory is synchonous.
To access a particular memory location, the appropriate address is placed on the address lines. On the next rising clock edge, the address is latched in. The SP assumes that the data will be available on the next rising clock edge. Altera recommends that this memory be configured as synchronous. If both of these inputs are clocked on the rising edge, two clock cycles would be required to fetch a particular memory location.