SEUs are a major source of errors in electronics used in space applications. There is also a growing concern about SEUs at ground level for deep sub-micron technologies. Estimating the SEU error rate of individual units of a digital circuit is very important in designing a fault tolerant system and predicting its overall error rate. In this work, a new software method is developed that uses weighted test programs in conjunction with multiple linear regression for SEU characterization of digital circuits. We also show how errors in bistables can be distinguished from the errors in combinational logic by operating a sequential circuit at different clock frequencies.
Radiation hardening is a fault avoidance technique used for electronic components used in space.
However, these components lag behind today's commercial components in terms of performance. In this work, these two approaches are compared in an actual space experiment. We measured the rate and pattern dependency of SEUs in memories. We tested this scheme on the COTS board and showed that, in the absence of hardware EDAC, system reliability can be significantly improved by providing protection through software. We demonstrate that the reliability of COTS can be enhanced by using software techniques for detecting, correcting and recovering from errors without changing the hardware.