A number of cross sections are also shown. The simulations were done using rational Runge-Kutta integration. Last month I accompanied Mr Lloyd M. Thorndyke on a visit to Hitachi. At that time we were given an overview and explanation of Hitachi packaging technology, some of which is used in these new systems. Both of us were extremely impressed, especially Thorndyke, who has many years of experience in this field.
Packaging refers to multi-chip module construction, boards, cooling, etc.
One of the most interesting aspects of Hitachi's work was that the packaging technology looked to us like it was capable of being used cost effectively on products below their highest end machine. Reducing machine cycle time is a very direct way to increase performance, but doing this requires a substantial number of technological improvements. Machine cycle time is a direct function of the switching time delay or fanout delay per gate for logic or the access time for memory, times the number of circuits in the loop. Logic and memory improvements require semiconductor technology, such as developing faster circuit families, or circuits with larger fanout capability. Shortening signal paths, using lower dielectric constant materials, using pins and other conductors with lower inductance, and generally using lsi, modules, boards, and cables with better and more uniform electric characteristics are areas where improvements can be looked for.