Although register loading requires an additional lead-off cycle, it results in early access to the next address while supplying data from the present location. Delivering Data With No Delay When used with bus speeds of 66 Mhz or higher, the Sync Burst SRAM is the fastest burst SRAM available. A Long Standing Tradition Async RAM, the traditional cache RAM, has been in use since the 386 system with the first level 2 cache was introduced. Because this type of RAM is not fast enough to be accessed synchronously, the central processor must wait for it. The capabilities of Pipelined Burst, Synchronous and Asynchronous SRAM at selected external bus frequencies are presented in the table below.
Numbers represent typical memory accesses achieved in terms of number of wait states.
The most cost-effective SRAM technology shifts from async to sync burst to pipelined burst as bus speeds increase. There are currently fewer vendors with the SRAM technology needed for extremely rapid flow-through sync SRAMs. This situation has motivated designers to choose pipelined burst sync SRAMs for the 50 to 66 Mhz bus frequencies in order to increase the number of suppliers, hence the availability of product. Sync burst SRAMs achieve high-speed operation by including a minimal degree of logic that lets the memory cycle automatically through sequential locations. All signals are triggered on a clock edge.