The interconnect pattern, also called a netlist , is generated from the customer-designed schematic and restricted to the topmost mask layers. Some arrays require three metal and two via layers. Three-layer arrays may use two layers for global interconnect and the third for macro intraconnect, but there are no hard rules. The more layers, the more prototype debug time required. This may be compromised with the significant gain in power management possible with the third layer.
Most manufacturers prefer that the released macros be used.
For example, at least one CMOS array uses the AMD Am2909 sequencer as a macro. If the designer is experienced and familiar with the macro library, the resulting silicon usage may approach that required by the best full custom design. At the simplest end of the semi-custom spectrum are gate arrays, providing one level of interconnect to the user for specification with all other connections defined. Programmable devices are restrictive in the functionality provided. They are suitable and competitive when there is a match between a module and the current application.