The first five weeks of the quarter give the students a comprehensive view of the design and analysis of static CMOS digital integrated circuits. Meanwhile, in lecture, students learn to design digital integrated circuits using a variety of other MOS technologies, ranging from pseudo n-MOS to switch logic and a variety of dynamic logic families, including domino. Students have free access to the Sun Microsystems Laboratory computers upon which reside the Cadence, Avanti and Synopsys software programs. All of the lectures and the majority of the exams are based on math, science, and engineering knowledge. Students must learn how to analyze the propagation delay of CMOS gates starting from basic physics principles.
Mathematical formulations are commonplace throughout the course.
Various methods and styles of performing digital logic at the transistor level are studied. A significant component of designing and developing a real world application, and indeed the projects in this class, is to ensure that one's system performs to specification in the intended environment. In this class, students learn how to design, lay out and characterize a complete library of static CMOS cells. The students design their system, a finite state machine of their choice, starting with Verilog, including Verilog simulation. The project is a design competition in which students use the cell library they developed in addition to using the Synopsys Design Compiler for synthesis, the Silicon Ensemble placement and routing tool from Cadence, and the DRC and LVS verification tools from Cadence, as well as Avanti's Hspice.