M CORE was introduced in November 1997. These include analog cellular phones, digital phones, PDAs, portable GPS systems, automobile braking systems, automobile engine control, and automotive body electronics. The M CORE family roadmap originates with the M200 Integer Core, a general-purpose core that operates at a maximum clock frequency of 60 MHz. This helps achieve a high level of throughput and more compact code density, reducing overall memory requirements and lowering total system cost. For maximum efficiency, the M200 family's microRISC architecture uses a four-stage pipeline for instruction execution.
Most instructions can execute in a single clock cycle.
An alternate register file of 16 entries is provided to support low-overhead interrupt exception processing. Taking performance to the next level. Improving on the already efficient M200 family, the M300 family efficiently executes code in fewer clock cycles at lower frequencies. Compared to competitors running at much higher frequencies, the M300 family's ability to work at lower frequencies while accomplishing the same task in the same amount of time adds additional power savings to power conscious applications. The M300 family centers around the M310 Enhanced Core with Fast Math capabilities.