An experimental port to Windows is now available as well. Please see the configuration page for further details. Actually, the problem resided in the fact that we could not get out compiled code at the expected time. It should work correctly now. When compiling the JIT compiler, JIT compilation for FPU instructions and the Lazy Translation Cache Flush mechanism are enabled by default Removed support for spcflags hacks when compiling the JIT compiler.
Native registers can now hold more than one virtual register.
Avoids some pointless register moves, and thus gives a very slight speedup Low level instruction optimizer.