Minimize the relative delay between the high to low transitions on one polarity of the output and the corresponding low to high transition on the other. The absolute delay does not matter. Sketch the transistor layout and schematic for the following sample layout from an early '80s sram cell built onto the Intel 8085 processor. The technology is a single level metal depletion load nmos with poly gates and buried contacts between dif and poly. The left image has metal still in place, the right image has had the metal and overlaid oxide removed with dilute hydrofluoric acid.
Power comes in on diffusion, ground on metal.