None of them are designed for use in mixed-mode with analog simulators.
None use parallel processing effectively.
Why Verilog and not VHDL is dicussed below, and elsewhere . A language used to specify hardware. A language used to describe actual hardware. VHDL is quite good for the first of these but is not as good at the second because of it's simulation semantics and syntactic restrictions, and lack of primitive types. It's regularity, formality and ability to describe abstract data types allow easy specification of high-level concepts.