When behavioral descriptions and logic simulators replace schematics and breadboards, FPGA architectures become critical factors. The ASIC design style, although new to many FPGA and PLD designers, will emerge as the best way to achieve more efficient FPGA designs of substantially more than 10 kgates. Without it, FPGA designers will be unable to complete high-density designs on time, or to maintain or improve their competitive positions. Some of them are quite similar to architectures used in mask-programmed ASIC gate arrays, while others bear little resemblance. Design style refers to the methods of developing designs with high gate counts, from design concept through production of working prototypes.
Performance is a measure of how well the design meets target specifications.
Predictability establishes with fair accuracy, early in the design cycle, the number of gates that will implement the design, along with the fact that the design meets performance goals or by what margin it misses those goals. Design cost includes both the time and resources needed to complete the design cycle through working prototypes, and the cost per chipset to produce the design.