Adding a cancelling branch instruction adds flexibility to filling the branch delay slot. All instructions before the faulting instruction complete AND And instructions following the faulting instruction, including the faulting instruction, do not change the state of the machine. One way to maintain precise exceptions. Use a exception vector for each instruction to disable writes. On integer DLX, no updates occur before instruction commit.
Precise interrupts are easy.
On CISC, this may not be true because of early state changes and memory updates. Number of register writes that occur in one cycle can be greater than 1. RAW stalls more frequent. Cancel the WB phase of the earlier instruction. Ignore the problem, let them happen.