On the opposite end of the security vs visibility spectrum is vendor-supplied source code. For this model, you have the vendor's core as a Verilog or VHDL RTL model, allowing you to debug design problems using normal HDL simulation tools and techniques. With IP-Tiles, the most useful of these two models, the IP vendor partitions and maps a core to some number of FPGA devices of the type used within Mercury. Since the cores have partitioning fixed by the IP vendor, timing characteristics are consistent every time you run a simulation using an IP-Tile model. Alternately, IP-Flexiblox are binary library models supplied by the IP vendor.
Mercury treats the model as a big binary library cell.
However, Mercury partitions the model during model compilation. Not shown in Figure 6 is a fifth form of IP model, C-code that runs on a Mercury RISC microprocessor. Chip designers can use this type of model when the IP is not in a synthesizable hardware form. This offers flexibility in including very large models, behavioral RAM, and even analog models. Mercury's modular compilation simplifies multichip design verification.