The CY7C42x1 FIFOs have synchronous PAE and PAF flags at all times. When starting with an empty FIFO it essentially takes two read clocks to read the first word from the device. This update cycle occurs whether the read clock is enabled or not. In this case it takes two write cycles to write into a device which just became not full. This type of flag operation is necessary to ensure that the empty and full flags will be valid and useable for a minimum of 1 clock cycle.
Many applications require that multiple FIFOs are used in parallel to generate a wider data path.
Such applications should use external logic to generate composite empty and full flags. All other operations to the FIFOs will occur just as a single device. Such cascading does not slow overall FIFO operation, but does limit the usability of the PAE, PAF, and HF flags. Each device will generate flags which accurately represent the state of that device. However, any one individual flag can not be used to determine the overall state of the system.