The general knowledge is that cache interferences are highly irregular, in terms of occurrence and intensity. In this paper, the different types of cache interferences that can occur in numerical loop nests are identified. An analytical method is developed for detecting the occurrence of interferences and, more important, for computing the number of cache misses due to interferences. Simulations and experiments on real machines show that the model is generally accurate and that most interference phenomena are captured.
Experiments also show that cache interferences can be intense and frequent.
Certain parameters such as array base addresses or dimensions can have a strong impact on the occurrence of interferences. Applications of these modeling techniques are numerous and range from performance evaluation and prediction to enhancement of data locality optimizations techniques. The Digital Library is published by the Association for Computing Machinery.