Existing turbo codes can also be employed to suit a user's needs. All these codes are stored in the prototype and can be selected from the front panel or from a remote port. He notes that this can be reduced to three FPGAs and two memory components in a unit that is probably capable of performing better than the current prototype. However, turbo codes have their drawbacks in the form of a throughput delay that can be annoying in synchronous communications such as voice or videoconferencing. But turbo codes are more complex than the traditional solutions and consume more time, he says.
Performance is proportional to the size of the interleaver.
The bigger the interleaver between two codes, the better the performance generally is, Jacobsen maintains. But the throughput delay will also be longer because the code has to iterate several times through the interleaver. Because of this, there is a trade-off between how close to capacity one wishes to get and how much one can tolerate delay. One way around this is to transmit at a higher data rate of 1 to 2 megabits because the delay itself will only be a small fraction of the overall transmission time. For example, with a 64-kilohertz transmission and an interleaver with a memory of 8 kilobits, one pass through the interleaver will cause an eighth of a second delay, which is significant at low data rates.