This question was contributed by Weal Badawy. However there are only 48 op-code bits to describe all this information. The selection of registers R0, R4, R8 and R12 as scratch registers means that there is one scratch register available in each register bank ready for high speed parallel operations without the necessity of saving non-volatile registers onto the C stack. How fast these transistors operate depends basically on how fast these charge carriers can move around. This in turn depends on the mobility of these charge carriers.
Mobility is the ratio of the drift velocity to the strength of the electric field.
The electrons have a higher mobility than the holes and hence can move faster than the holes. Since electrons are the majority charge carriers in NPN transistors, these are generally faster than their PNP counterparts. This question was contributed by Naveen P N . The following circuit is designed to demonstrate the working of a NAND gate. There is a mistake in the circuit.