The new template was posted to the World Wide Web and provides a fast and easy way for modelers to generate a wide range of SRAM models. The approach reduces the time it takes to implement changes in an FPGA design. It also helps designers stay connected with the implementation issues and helps new synthesis users get over the learning curve. It involves resynthesizing only the blocks of the design that change rather than the whole design. Existing blocks of unmodified logic are reused through the netlist merge capabilities of many foundry tools.
Results show that the incremental approach helps speed up the total design cycle time.
The University of Cincinnati Systems engineering is the process of looking at many facets of an emerging design. A systems engineer is required to examine and reconcile many information sources when making high level design decisions. Although VHDL is an excellent digital system description language, it lacks flexibility to address all systems level issues. Digital system behavior and structure are effectively handled, but other facets are not. It adds functional requirement and performance constraint modeling to the VHDL-based design process.