The algorithms for automatic code generation presented in this paper use a very general description of the target machine. They can be applied to a large number of modern integrated digital signal processors. As an example, we present results of a compiler based on these algorithms generating code for the integrated digital signal processor DSP56000. While previous approaches have used a fixed granularity, i.e. the size of the partitioning objects was fixed, we present a partitioning approach that dynamically determines the partitioning granularity to adapt optimization steps to application properties and to intermediate optimization results. Experiments with simulated annealing optimization show a faster convergence and far better adaptability to cost function variations than in previous experiments with fixed granularity.
Many software compilers for embedded processors produce machine code of insufficient quality.
Since for most applications software must meet tight code speed and size constraints, embedded software is still largely developed in assembly language. In order to eliminate this bottleneck and to enable the use of high-level language compilers also for embedded software, new code generation and optimization techniques are required. This paper describes a novel code generation technique for embedded processors with irregular data path architectures, such as typically found in fixed-point DSPs. The proposed code generation technique maps data flow graph representation of a program into highly efficient machine code for a target processor modeled by instruction set behavior. High code quality is ensured by tight coupling of different code generation phases.