A comparison of wire bond and flip chip wiring rules will be made, along with a discussion of a proposed path to provide suitable card wiring rules, while remaining economically viable. These logic applications will be the drivers of this technology in the future, far surpassing the needs of the memory circuits that are driving small packages today. Both of these factors directly affect the circuit designer's noise budget. To meet these increasing signal connection demands, all levels of packaging are being required to support interconnection, which is driving smaller line widths, spaces, and vias. A similar graph for wire bond products is shown in Figure 2.
Full area array module sizes.
Practical limitations are imposed on the substrate by wiring rules and physical capabilities of tools, such as drills. Additionally, wiring is required under the die to support connection to the BGA in the center of the package. Flip chip applications impose tighter requirements on via and land size when compared with wire bond products, since wiring between C4 sites is limited to less than three lines per channel. Therefore signals must escape the C4 area with vias to be redistributed on multiple signal layers. Figure 6 defines the C4 via dimensions, and Figure 7 shows the theoretical maximum land size for vias in the C4 area.