This duo has performed a Herculean job, but has hit the proverbial wall. Consumers want more choices and options, beyond the cosmetics. Meanwhile, consumption in the handset's digital portion is dropping fast. Here, the handset designer must get higher computing performance without incurring greater power consumption.
Handset efficiency is governed by the battery power consumed and the performance a user demands.
A DSP chip's CPE is about 8 to12 percent. This means only 8 to12 percent of the chip's electronic functions perform useful work. The other 90 percent is required to either keep the rest operational, or for other functions used at later times. This is why ASICs are less expensive, consume less power and boast greater performance. But ASIC gains come at the expense of flexibility.