Normal delivery includes the edif netlist, VHDL, Verilog and schematic templates for instantiation into your design, and VHDL behavioral models. The transmit CORE converts transmit data to the scrambled NRZI format in 20 bit parallel format to be serialized by an AMCC S8401. The receive core accepts scrambled NRZI data from and AMCC S8501in 20 bit parallel format, descrambles the data, detects frame sync and aligns the received data to the 20 bit output.
More detail is available in the datasheet .
Call or email for more information and pricing. Call or email for more information. Intellectual Property Andraka consulting has developed an impressive collection of intellectual property for DSP applications, which although are not productized for stand-alone sale, can be drawn upon for a customers design.