Using formal verification methods, Formality determines functional equivalency by comparing different stages of a design without the need for simulation vectors, permitting designers to rapidly detect implementation errors. Finally, with Formality as an integral part of its verification tool suite, Synopsys provides the fastest and most comprehensive functional verification solution from design concept through implementation.
Formality is now an integral part of our formal analysis flow and overall verification strategy.
After extensive evaluation of formal verification tools, we chose Formality based on the performance and capacity of the latest Formality 2000 release. With Formality, we saved over two months on our verification cycle time and plan to use Formality to verify our next generation seven million-gate design. Kenichi Akiba, Senior Specialist for System Development of Real Vision Helping customers produce increasingly complex, feature-rich SLI ASICs while at the same time reducing overall time to market is one of the most critical mandates placed on our design teams. TAEC s formal verification process, first announced in 1998, has been key to achieving this time reduction and now the Synopsys latest Formality release gives us more options to provide the very best solutions. We comprehensively evaluated how Formality could enhance FlexStream s design verification methodology and concluded that supporting Formality is a priority for introducing formal verification capability into our FlexStream Design System now, and enabling formal verification for functional sign-off in the future.