So, counting the 2x2 tiles from an FEM with the ETC is the currently favored approach. Even if this decision were made, say to go with driving the 6-bit digital sum at the card edge, much remains to be decided before the ETC design can be specified. None of these is really satisfactory, and this remains a technical sore point for the ETC project. Now, about those details. The first prototype muID ROC is being assembled right now, so we should be able to get an answer about its response time soon.
Foolishness is usually an indicator that there is a better way to do things.
The scale of the ETC readout project is so small that not much extra engineering can be amortized when we only need to buy a dozen or so ROC boards and one or two crates. Alan points out that if we don't change the ROC it will be more engineering cost for the ETC, which may have to grow in layers or physical size and add more cost for assembly. There is no free lunch, certainly. So we should be getting detailed information on this possibility soon, ie within a month. Both these are possible.