Independent Behavioral-Level Modules Registers hold data. Similar to C with looping and flow control strcutures. Assignments of data via the use of operators. The design of modules is a less abstract representation. However, it is still very useful for larger designs, when descriptions at the gate-level would be tedious.
Modules contain a gate hierarchy.
Design of transistor devices is at yet a lower level. In NetList VeriLog - 'VeriWell' Simulate with VeriLog Layout Vs.