This is achievable despite the device being run at a very low speed of 33 MHz. Since we used the same memory chips as those used in the L2-caches of personal computers, the cost of the memories is low. The device can be used as a co-processor, next to a general purpose processor that handles all the other parts of IP forwarding or firewall functions. The 2-dimensional classification problem is of increasing importance in the evolving Internet architecture. An alternative approach that has been proposed is route aggregated flows along specific traffic engineered paths.
Rules can still have arbritrary overlaps and priority amongst rules is used to resolve conflicts.
For IP routers, we are interested in solutions that can scale to hundreds of thousands of entries. Also, as for all other operations, we are interested in only worst-case performance of the algorithms since we want to avoid queueing for header processing in order to provide service assurances. It is shown that for a number of possible prefix lengths of 32 and filter rules, the number of memory accesses is about 50 which makes it possible to process at a million packets per second with a less than a 100 Mhz clock speed. Specifically, there may be no need to restrict filtering to the edges or to very simple operations such as using only the TOS bits in the IP packet header.