Only signals are used as the connection ports for VHDL entities. Variables are declared within process blocks, procedures, and functions. A general rule of thumb is to use variables wherever possible. From a synthesis point of view, both variables and signals can turn into internal circuit nodes. Typical uses of generics are for controlling bus widths, feature inclusion, message generation, timing values.
Generics offer a method for parameterizing entity declarations and architectures.
One VHDL model will be written for the control and one for the datapath. A schematic will be used to tie these two blocks together. Later, a VHDL structural model will be used to connect the blocks. Mux for choosing between card value, plus 10 and minus 10. Adder for adding card with current score.