This device is an 8-bit serial shift register which shifts data in the direction of Q A toward Q H when clocked. These registers also feature gated clock inputs and complementary outputs from the eighth bit. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with the load input high enables the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is high.
Parallel loading is inhibited as long as the load input is high.
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