Floating-point intensive applications allow typically exploit much more parallelism that in integer intensive applications. When we expect in near future 1 GHz implementations, this is translated into 2 Gflops peak performance. This number is not impressive in comparison to Sony Emotion Engine with peak 6 Gflops at 300 MHz. Extending Alpha instruction set with support at least packed floating-point operations will allow at least close performance gap. However, by proper design of reorder-buffer scheduling mechanism is possible to get advantage of fused operation.
Modification is pretty straightforward.
Reorder-buffer receiving register numbers, for which will be result computed in next tick in arithmetic unit. At least latency can be improved. Another issue is throughput. Next is required 8-issue implementation. Requiring more and more FP performance will produce problems with issue-width with number of FP write ports.