Candidate should be a good communicator with teambuilding skills. The ideal candidate must have a BSEE or MSEE and 5 years of experience. Candidate should be experienced in VLSI ASIC design methodology using Verilog VCS and Synopsys design tools including Static Timing Analysis running on the UNIX platform. Candidate should posses a comprehensive understanding of automatic test vector generation as well as scan design methodologies. Candidate should be a good communicator and embrace teambuilding concepts.
Experience designing optical storage devices is a plus.
Inc. All rights reserved.