Sure enough, Janick quickly replied. My explicit statement was that I preferred Vera over VHDL and Verilog. I also prefer Specman over VHDL and Verilog. By my estimates, I'm over 5x more efficient writing testbenches in either language. Janick went on for six paragraphs.
Language features is but one element in the selection process.
In my personal experience, Vera and Specman both offer tremendous productivity gains over VHDL and Verilog for verification. Janick's run for cover may be moot. A few months ago, Tom Faison of Nortel accidentally foreshadowed this in an e-mail. Right now, there's no real meat to SystemC, and yet we have to be planning NOW for the next-generation verification methodology. So SystemC is a sword of Damocles which will chop off any residual interest in dedicated verification languages like Specman and Vera, dooming them all to orphan status, while itself remaining unrealized for the foreseeable future.