There are certainly areas that are more difficult to work around, particularly if an additional gate count penalty is unacceptable. Some libraries are not coupled to a single foundry, but this does not entirely alleviate the concern. Even generic libraries may have elements which are not available from certain participating foundries due to process constraints. It is important to include potential foundry limitations as part of the decision process. It is preferable to use methodologies which do not restrict the silicon foundry choices unnecessarily.
Memories Let's examine compiled and hard cells such as memories.
Memories themselves may seem easy to evaluate, but there are so many design variations which can accomplish the same results that this often becomes an extensive area of library research. Memories also represent a domain where more speed almost instantly requires more silicon area. Techniques such as interleaving and bank switching cause an instant gate impact. It is important to consider other bit widths and address lengths than those obviously indicated by the design. Sometimes, due to layout aspect ratios and speed, dividing the problem into smaller RAMs may yield significant benefits.