40, No. 6, December 1997. In this paper, we study the problem of scheduling parallel loops at compile-time for a heterogeneous network of workstations. We propose a simple yet comprehensive model for use in compiling for a network of processors, and develop compiler algorithms for generating optimal and near-optimal schedules of loops for load balancing, communication optimizations, network contention and memory heterogeneity.
Experiments show that a significant improvement of performance is achieved using our techniques.