One of obvious candidates is predicated instruction execution. Alpha supports only conditional move to reduce branch penalty. Still remain memory operations and subprogram calls, for which conditional move only is not adequate. However, increased number of instructions and memory resources is penalty. This instruction just adds tag into micro-operation stored into reorder buffer.
Next issue is branch prepare instruction.
Sometimes branch is hard predictable even by dynamic branch prediction. In that case, branch prepare instruction allow reduce branch penalty. Another issue is then memory latency. When load waits to resolve cache miss, all subsequent operations cannot retire, flooding reorder buffer. Even big Alpha's reorder buffer will be full in case of L2 cache miss.