Write hit Processor Write data in cache. Read miss Bus Request data from cache or memory. This causes processors with copies to invalidate them. These state transitions have no analog in a uniprocessor cache controller. Also, read misses on a split transaction bus are not atomic.
Nonatomic actions introduce the possibility that the protocol can deadlock .
See Appendix E for a fix. From the shared state, a write miss would require the action shown previously. All that is needed is an invalidate operation. Real protocols distinguish between shared and clean data in exactly one cache.