It also ensures timing analysis results are consistent with PrimeTime and Design Compiler. In delay calculations, Chip Architect supports interconnect load extraction using statistical wire load models, lumped RC and distributed RC networks. Designers can choose the extraction method based on accuracy and run-time tradeoffs. Today's design flow is a two-step process. First logic design is executed block by block.
Physical design is performed independently after logic design is completely finished.
As designs move to deep submicron processes, the effect of interconnects dominates delays and results in unpredictable timing convergence. This unpredictable timing convergence is caused by the physical effect of interconnects not seen during synthesis. Synopsys' Floorplan Manager has helped somewhat. However, large iteration loops between logical and physical design occur. The long and large iterations between logical and physical designs often ruin design schedules.