The Silicon Fabrication area is basically configured as a CMOS facility but one of the main attractions is the flexibility of the unit.
Processes can be varied and adapted to suit customers needs.
The resistivity of the epitaxial layer is 10-16 W .cm and it is 10 m m thick. There are two levels of metal and the option of a double polysilicon capacitor. The 5.0 m m CMOS process is the most commonly used process. It is a 15V analogue process with a well established performance record. As with all the processes the core process can be used by researchers and changed to suit particular needs.