National Semicondutor, 1993. Parallel Computation of Correlation. This circuit consumed nine cells and operates with an internal delay of 9.4 ns. A complete correlation circuit is created by physically tiling 256 of these conditional bit serial adders into a 16 Theta 16 array as suggested by Figure 2. Such improvements extend the technique to other systems where the technique would otherwise be unjustifiable.
Partial configuration is one technique that can significantly reduce reconfiguration time.
Due its slow speed, full configuration is limited to very slow adaptations on the order of milliseconds. A part of the chip can be reconfigured while another part is operating. CLAy was designed to support real time algorithm and logic sharing by using dynamic partial reconfiguration. The logic cell layout is similar to existing FPGA devices, with a flip flop and 5 input lookup tables. The first chip controls the configuration, processor execution and instruction paging.