This category takes into account time spent processing. Given the simple processing model in the simulator, this is only an approximation, but it should be roughly accurate. These categories give time spent waiting on an interface register to become ready to handle a read or write. The first write typically takes only a cycle, since the interface register is empty. Subsequent writes may take longer, if the interface register has not been cleared by the router.
Reads give the time spent blocking waiting for data to become available from the router.
This reflects generic phase-synchronization time. For all phase changes, this includes time spent providing the synchronization word, as well as time spent blocking to allow the change to reach the read stage of the pipeline. This does not include any later run-time tweaking, but just the baseline time to load a complete schedule with appropriate VFSM annotations. While some figures present raw cycle counts, others present results in units of wall-clock time, attempting to factor in the difference in cycle speeds between two equivalent implementations. While this ratio is admittedly purely theoretical, it seems likely to reflect the approximate difference in possible speeds likely with the two architectures.