In class we presented an architecture for the basic 16 bit RISC computer. We outlined the organization of the registers, the format of instruction, the list of instructions, the timing sequence for each instruction and the flow chart for operation. I will post the relevant notes. Memory is external to the processor chip. The bus width must be 24-bits wide.
Memory address is output in parallel from the processor chip.
AC, DR, TR, PC, AR, registers must allow load, clear, increment, decrement. Outlined the organization of the registers, the format of instruction, the list of instructions, the timing sequence for each instruction and the flow chart of operation for this new 24-bit computer. Design the sequence counter for this computer. List all design decisions made and show all hand calculations. Explain clearly how you obtained these specifications.