Many applications require a high-speed conversion from one bus width to another.
This is an ideal application for FIFO memories. The 8-bit data is stored in the four FIFOs sequentially. A Cypress SPLD, the PALC22V10D, determines the FIFO that's written to. The active- low reset signal brings all the outputs low while the FIFOs are reset. FIFO3 and FIFO4 are operated in the same way.