Last item, then we have the whole picture. The cache needs a way of distinguishing between an empty block frame and a full one. This access includes an address. The memory access is sent to main memory, which responds by providing the block corresponding to the address. Blocks are 4 bytes.
Memory is byte addressable.
There are 4 blocks in the cache. Assume that all accesses are to READ a single byte. Assume the cache is empty at the start of the example. Memory is small enough that we can make up a complete example. Assume little endian byte numbering.