You will observe the effects of control dependency, data dependency, and resource limitations on performance of pipelined computers.
Memory hierarchy is a key architecture approach to reducing memory latency.
As the speed gap between CPU and memory increases, effective design of memory hierarchy becomes essential to today's computers. Using the logic analyzer to measure and analyze system timing. Serial communication by programming the UART in the computer. Learn and exercise how microprocessor communicate with other modules. This lab will familerize you with the modern communication protocols and error control coding concepts.