Pads can have the same name as signal nets with no conflicts.
Recall that the logic block contains a 4-input LUT and a flip flop. The pinlist line lists the nets connected to this logic block. The nets connected to the four LUT inputs are listed first, followed by the net connected to the logic block output and then the net connected to the logic block clock pin. A logic block may not need signals connected to all of its LUT inputs or to its clock pin. Some signals in FPGAs are normally routed via dedicated, special-purpose networks, rather than the general routing resources.