Simulation Models TopProtect generates object code models from standard VHDL and Verilog files. Easy IP Distribution TopProtect's architecture greatly simplifies the distribution of models and maintenance of simulation libraries. Freely downloadable Topdown utilities generate the files needed to run a TopProtect model with any supported VHDL or Verilog simulator on any computer platform, eliminating the need to compile new models for every version of every simulator used by an IP vendor's customers. Flexible Visibility and Licensing Controls IP providers and end-user designers both get what they need. Event-driven simulators are too slow.
Hardware accelerators are too expensive.
Cycle-based simulators are too difficult, requiring the adoption of yet another tool and imposing restrictions on the designs they process. CyclopsPro isn't a separate new simulator to purchase, integrate, and learn. Instead, it generates simulation models that execute faster with your existing VHDL or Verilog simulator. These models use cycle-based techniques to provide functional accuracy with much improved simulation performance. Mean Easier Use CyclopsPro supports design complexities like asynchrony and it uses your existing test benches.