Once this is done, we should be able to characterize how the ATM NAPs will perform under various conditions. Today Bugs in buffering, clock, segmentation chips. As a result, even a fixed ADSU could perform less than adequately in N to 1 configuration. VBR model requires back pressure in the form of rate shaping Lack of rate shaping in the ADSU makes a large buffer in ATM switch very important. Delay on WAN link is very important to simulate.
Homogeneous hosts make test results easier to interpret.
There are more tests that can be run to better characterize ATM performance. Even ciscos break on windows above 500KB, i.e. the size of the card to card buffer pool in the cisco. Problem is not limited to ATM, ATM just doesn't look great right now because of the smaller buffer. We can guess that the congestion collapse will look much better. Predicting real world conditions are important to arrive at conclusions from test results.