The other extreme is adding so much syntax to a language that it becomes difficult to use. Some find Specman Elite to be too much language with an insufficient gain for the large learning investment required. For example, there's much hoopla about temporal expressions, but anyone can do similar things in Verilog. In many cases, the extra syntax is just something more to learn, but unnecessary. Second, evolution is the way of our species.
Evolution is a good way to preserve investments in ideas that are known to work.
Too many companies have spent much good time and money creating designs with Verilog and VHDL to want to rewrite them. Certainly, new designs might want to use new language features, but not if they won't interoperate smoothly with old code. Reuse was a buzzword of the recent past that continues to make sense. If we evolve our languages, reuse is more achievable. Simply, extend existing engines to understand new language features while preserving the old.