One of the main contributors to inefficiency in computers is the time it takes to transfer data from memory to a processor, and move the result of the processing back to memory. This transfer time can be several times greater than the actual processing time. Placing processors on a memory chip is an approach toward solving this problem.
Future chips having much greater capability are under development.
When functioning in the processing mode, a row address and command are presented to the PIM chip. Since there are 64 PEs in the PIM chip, each PE is associated with one column of memory containing 2,048 bits. All 64 PEs in the PIM chip execute the command simultaneously on data at the row address. U.S. Patent No. For the Abington Cross Benchmark, the image of a cross with noise is given as input.