Welcome to the seminar page of the VLSI design and test at Rutgers, The State University of New Jersey. The participants in this seminar series are people involved in VLSI circuit testing and verification research at Rutgers. The seminar series gives the participants an opportunity to present their research ideas. The seminars are organized on the Friday of every week in CoRE 601 . Lunch will be served around 12 noon.
Lunch is available for a fee.
People who wish to have their lunch are kindly requested to place their order in advance with Sanjay Mohan . 12th Nov, 1999. 5th Nov, 1999. 29th Oct, 1999. 22nd Oct, 1999.