In fact, Figure 6.32 is a shorthand representation of what really happens in the hardware. Another kind of pipeline hazard involves branches. Simplest approach is to stall the next instruction until the branch instruction is complete. Many times a conditional branch will decide against branching. If the branch is taken, the instructions that are being fetched and decoded must be discarded.
Execution continues at the branch target.
If branches are taken half the time, this optimization halves the cost of the control hazards. To discard the instructions, we merely change the original control values to 0s much as in the stall approach. For stalls, we just changed control to 0 in the ID stage and let them percolate right. In the branch case, to flush the instructions properly, we must also change the control values in the IF, ID, and EX stages when the branch reaches the MEM stage. Control determines whether to send a flush signal depending on the instruction opcode and the value of the branch condition being tested.