The new part will contains some architectural changes to enhance performance as well as new PLL features. A 105K-gate part is scheduled for 2Q99 delivery. The company is also working on a 0.25-micron version of the DL6000 family. DynaChip is concentrating on high-performance FPGA applications and has designed its devices with this goal in mind. Each of the nine logic cells in a block are internally connected using high-speed buffers.
Longer connections use active repeaters.
The active repeaters have allowed the design of circuits with fanouts of hundreds of loads. Altera has promised this feature for its Raphael family that is due out next year. GTL usage has been driven by Intel's use of the signal format for its 100MHz and 133MHz processor busses. DynaChip also claims that it is the only FPGA vendor that can implement 125MHz FIFOs and is the only vendor with two PLLs. The company has been able to build OC3 framers that operate at 155MHz.