During the fetch stage, a 32-byte aligned data is brought from the instruction cache unit. The next stage aligns an instruction packet of 16 bytes based on the header bits. The aligned instructions are then placed in an instruction buffer to feed the decode stage. The branch prediction information bits are looked at this stage to prepare for both static and dynamic predictions. The instruction decode and operand read from the register file occur in the next stage.
Instructions then enter the execution pipelines in the functional units.
All the other instructions have a deterministic delay. MAJC-5200 provides precise exception handling capabilities for most instructions. Majority of the instructions take a single cycle, with some taking two and four cycles. Within a functional unit, the results are bypassed to younger instructions as soon as available. The results of FU0 are forwarded to FU2 and FU3 with one cycle delay and are visible to FU1 in the next cycle.