Shrinking process technologies and increasing design sizes continually challenge design methodologies and EDA tools to develop at an ever-increasing rate. The advent of DSM processes is changing all of this, invalidating assumptions and approximations that existing design methodologies are based upon, and forcing design teams to re-tool.
Interconnect resistance increases, because of shrinking wire widths.
Vertical heights of interconnect layers increase, in an attempt to offset increasing interconnect resistance. The area component of interconnect capacitance no longer dominates. Interconnect capacitance dominates total gate loading. These changes directly affect the performance of a design and indirectly force a change in design methodology. Download a PDF version of this paper.