For that reason, optimizing V t is often left as the last step in the design of the device, where it can be altered without having to reevaluate the settings of more fundamental device parameters. A set of constraints for V t selection are described. The gate delay improves linearly with decreasing V t . V t selection is driven by the desired product speed, provided the other following boundary conditions are met. Asynchronous coupling into dynamic inputs and supply rail noise can erode precharge and signal margin.
Excessive leakage requires the use of keepers, adding back delay.
Keepers are half-latches that replace charge lost to noise and leakage but introduce a small amount of loop hysteresis. Noise-margin dependence on V t . Hence, a 100-mV decrease in V t increases I off by approximately one order of magnitude. Standby Power Subthreshold currents at use conditions are responsible for only a fraction of the active power in high-performance logic. In portable products, however, battery lifetime is a serious consideration.