This includes registers for memory configuration, internally cached PRCB data, breakpoint registers, and interrupt control. The processor ensures that accesses to the MMRs generate no external bus cycles. This high bandwidth bus provides burst transfer capability allowing up to four successive 32-bit data word transfers at a maximum rate of one word every clock cycle. In addition to the bus signals, the i960 Jx processor provides signals to allow external bus masters. When a fault is detected, the processors make an implicit call to a fault handling routine.
Information collected for each fault allows a program developer to quickly correct faulting code.
The processors also allow automatic recovery from most faults. To support system debug, the i960 architecture provides a mechanism for monitoring processor activities through a software tracing facility. The processors also provide four breakpoint registers that allow break decisions to be made based upon instruction or data addresses.