The downside has been the need to develop technology in load balancing and interprocess communications, in addition to IC placement and routing. Moreover, Parakh acknowledged, global optimization and routing have proved difficult to apply in a parallel fashion. As placement is developed, for example, routing models are refined. The accuracy of congestion analysis improves as the layout progresses, and timing estimation becomes accurate enough to address crosstalk. The final placement and routing thus converge in terms of timing, power and clocking, Parakh said.
Global optimization comes first, and then the placement moves toward greater and greater detail.
Parakh said that Monterey uses partitioning technology similar to the h-Metis algorithm, cited in many academic papers. As placement is being refined, routes are continually monitored and Dolphin is modeling timing and congestion. Any given net might start at a high level of abstraction and then work its way through placement and optimization. A statistical model is created for each net. As quadrisection proceeds, partitions are physically smaller and spaced farther apart, and parallel threads focus more on local improvements.