Taking a different approach, the IBM Power3 design team included only 32 kbytes of instruction and 64 kbytes of data cache, but made each cache 128-way set associative. Another way to reduce the miss rate is to cheat. Instruction sets in both Sun's Sparc V9 and IBM's Power3 include prefetch instructions that, in effect, tell the CPU to preload certain information into its L1 caches. Trying to overcome branches can lead to even more complexity. Instead of waiting for an instruction's turn to come up before considering it for the pool, the CPU can look all the way to the end of the block and see if there are any more instructions ready.
Further improvement depends on speculative execution.
In essence, the CPU guesses which way the branch will work out. The latest chips, such as the Power3, take the technique one step further, speculating down both possible paths of the branch. All of these techniques tend to improve the all-important average instructions per clock figure. But all of them can be defeated by careless programming or a sloppy compiler. Indeed, the conventional superscalar RISC engine is approaching the point where no one will be able to tell whether it is designed correctly.