Each memory cell consists of six transistors. The CY7C1382BV25 and CY7C1380BV25 SRAMs integrate 1,048,576x18 and 524,288x36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation.
Individual byte write allows individual byte to be written.
BWa controls DQa and DQPa. BWb controls DQb and DQPb. BWc controls DQc and DQPd. BWd controls DQd-DQd and DQPd. GW being LOW causes all bytes to be written.