Later in the course will consider advanced concepts, including caches and memory management, instruction prefetch queues, pipelines, and floating point arithmetic. Depending on time, the intent is to cover multiscalar architectures, branch prediction, translation lookaside buffers, and the like. The course will use Xess development boards with Xilinx XC4010XL FPGAs, using Synopsys VHDL and the Xilinx M1-series place and route tools. There will be weekly homework and lab assignments, two prelims, and a final project. Homework will prepare you for the lab assignments and may be considered part of the lab writeup, but will always be due at the beginning of your assigned lab period.
Graded homework is returned in Lab.
No late assignments will be accepted without prior approval. Late assignments will receive a ZERO grade. You may discuss homework with your partner, you are expected to write homework assignments together with your partner. You and your partner are expected to write homework assignments independently of other groups. No late assigments will be accepted without prior permission.