As a matter of fact, clock-delayed domino logic was heavily used in 1 GHz microprocessor announced by IBM earlier this year. After inverter I1 has fully developed output Q, the delay circuit produces a delayed clock output, which is provided to subsequent stages. By propagating a unique clock network parallel with the logic, CD domino eliminates the fundamental monotonic signal requirement imposed on standard dynamic domino. CD domino and other selected dynamic domino schemes arguably provide the fastest practical logic evaluation. They are also by far the most risky.
Dynamic logic is intrinsically unstable.
If not carefully assessed, charge leakage, input signal noise, missed timings, and application conditions can reduce the reliability of a design. Dynamic logic is feasible only in settings with appropriate interconnect technology. IBM led the industry with the introduction of copper wiring. Superior wiring capacitance, enabled by IBM copper research and development, encourages heavy use of dynamic circuitry. By choosing a hierarchical wiring strategy, IBM can provide wire sizes with relatively small aspect ratios that have both low coupling capacitance and reduced total capacitance.