The result will be available in the form of an integer and a rounded off fraction. A shift register is used for left shift. Subtraction is carried out using two's complement. The system has a two phase clock, for a synchronous design. Our goal was to implement an 8-bit ALU, supporting division, and including addition and subtraction.
Logic is provided to choose the required operation.
The outputs at the end of every state are available on the output pads for testability.