That is something that can be comprehended by logic designers. Yes they do. Global routing is thrown away. But the Physical Compiler timing reports correlated very well with post-layout detailed routing. I think that different development engines and teams working on two different software tools can contribute to lack of correlation.
Estimates are exactly that-estimates.
In high-speed design we rely a lot on clock skew. With this design, we were able to do scan chain reordering based on the placement, but we had to write some extra scripts to do that. That helped out quite a bit, because in the past we had a lot of problems with scan chains. But Physical Compiler has helped only with scan chain reordering. We would love to see more.