Europractice offers MPW runs, too, with much cheaper prices. First step is to find out possible tools. ASIC design companies use very expensive designing tools, but I can't afford those. If layout generation is done by hand from logical design, it's very probable that you make an error and you waste your money. This means, that if I use that kind of cell library, I can't share design via Internet.
Later chips contains actual processor core with additional units.