Second, technology mapping adapts the functions to the target technology. We developed an additional powerful approach to optimize netlists after the technology mapping step. In this approach, we analyze the circuit from a global view to find permissible substitutions of signals. Such substitutions incrementally change the netlist. They can be utilized to optimize area, delay and power consumption.
Experimental results show significant improvements.
In recent years power consumption of integrated circuits has become more and more important. Techniques to estimate power consumption are required not only to predict the total power consumption of a device but also to serve as a cost function during synthesis. We developed techniques to estimate the switching activity of internal signals, which is the crucial quantity for logic-level power estimation and optimization. Both pattern simulation and probabilistic computation are used to estimate power consumption rapidly and accurately. Estimation results are used during logic synthesis for functional decomposition and netlist optimization to minimize power consumption.