This chapter also introduces the recursive bipartitioning paradigm PROP , which combines concepts from logic synthesis with the recursive bipartitioning. While it can be shown that either replication or optimization can improve the quality of partitions, it is the combination of processes that consistently achieves the best results to date. Although the formulation and the implementation are general, we demonstrate the application of our method using circuits generated with a commercial tool and partitioned for implementation with specific library of Xilinx's FPGA devices. We conclude this chapter with an comprehensive report on the experimental work. The fifth chapter introduces basic concepts of performance optimization that target the minimization of critical delay in a circuit.
Experimental results demonstrate the efficiency of the proposed approach.
We conclude the thesis with the conclusions and directions for future work.