In most cases, a flip-flop will work just as well, with fewer potential problems. The problem with latches centers around the transparency issue. In the circuit shown in Figure 1, if Gate A and Gate B were to both go low, the circuit could become an oscillator even though this was not the intention of the designer. Latches pose a significant problem for EDA software tools. Static timing analyzers typically make incorrect assumptions about latch transparency, and either find a false timing path through the input data pin or miss a critical path altogether.
Latches tend to make circuits less testable.
Synthesis tools occasionally infer a latch in a design when one is not intended. Some FPGA architectures do not support latches. This means that synthesis tools must create combinational feedback loops when latches were unintentionally implied by the RTL code. Like latches, they cause testability problems. In many cases, combinational feedback loops can be replaced by flip-flops or latches, or completely eliminated by fully enumerating RTL conditionals.