The prototype DSSD for the outer layers and test structure will be fabricated to find the optimum width and provide test sample for ladder assembly and support structure. The result indicates that we can reduce the leak current by a factor of 2 by reducing the temperature from 25 deg to 15 deg. We should consider the possibility to cool the detector to less than 15 deg. This requires careful ladder design taking into account the shrinkage of the ladder and better support structure. Due to this improvement VA1 noise is no longer a dominant noise source after 100 kRad, The VA1 is still functioning after 650 kRad.
Further irradiation is planned until the chips die.
As for the choice of the feature size, 0.35um process is preferred to end the radiation hardness issue. Bias compensation scheme was also discussed. Several choices are presented. Normal FET based feedback scheme, passive n-well resister feedback scheme, internal RC scheme and external R internal C scheme. Internal C can be shielded to some extent.