When synthesized, the surprising thing was that even when I broke the long path in my re-design, their tool produced faster gates than mine with much less effort to synthesize. We did not have the option to break this up since our simulation environment didn't allow this at the time. We did most of the port to C-Level style ourselves in about a week. As good or better timing results with much less effort than a hand port. There are some limitations to what we can do with C-Level.
Hierarchy is a little bit cumbersome.
To get the simulations to work, no submodule can have both registered paths and purely combinatorial paths through it. The combinatorial paths must be broken out into a separate module. We were also impressed with the size. Simulation speed similar to what we have with our in-house tool. We have decided to continue to use our in-house simulation engine, since we have many features invested in it.