If stupid register allocation is in use, this dump file reflects the full results of such allocation. This pass attempts to combine groups of two or three instructions that are related by data flow into single instructions. It combines the RTL expressions for the instructions by substitution, simplifies the result using algebra, and then attempts to match the result against the machine description. This pass looks for instructions whose output will not be available by the time that it is used in subsequent instructions. It re-orders instructions within a basic block to try to separate the definition and use of items that otherwise would cause pipeline stalls.
Instruction scheduling is performed twice.
The first time is immediately after instruction combination and the second is immediately after reload. Register class preferencing. The RTL code is scanned to find out which register class is best for each pseudo register. This pass allocates hard registers to pseudo registers that are used only within one basic block. Because the basic block is linear, it can use fast and powerful techniques to do a very good job.