Each memory cell consists of four transistors and two high-valued resistors. SRAMs integrate 262,144x36 and 524,288x18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. However, the CE2 chip enable input is only available for the TA package version.
Individual byte write allows individual byte to be written.
BWa controls DQa. BWb controls DQb. BWc controls DQc. BWd controls DQd. GW being LOW causes all bytes to be written.