However, such scaling can increase the leakage current through a transistor, thereby increasing the leakage power. It can also be noted that in static CMOS circuits, the paths converging to any internal gate may have different propagation delays. The delay mismatch of different paths causes spurious transitions. Such transitions increase the power dissipation due to the switching component of current. In this report we present a novel algorithm to balance different paths of a design converging to logic gates using multiple threshold transistors such that both power dissipation due to spurious transitions and leakage current are minimized.
Leakage power is reduced due to the use of high threshold transistors in the non-critical paths.
The system configuration and parameters correspond to an industrial customer served by a large electric utility. Welder operation produces severe cyclic flicker which leads to customer complaints. Computer studies have been conducted to determine the effectiveness of the AVC on the reduction of observable flicker at neighboring loads. Different control strategies involving the AVC have been considered and compared with respect to flicker reduction. The measurement technique used in the FAC is shown to be accurate even in the presence of heavy system distortion.