Let's characterize the behavior of this PFET using another experiment shown in Figure 3. The current through the PFET changed from 43.39uA to 46.73uA when BIT changed. We can see that the PFET is barely on, and that for most values of VDS the device is in saturation. Since the left PFET is in saturation, even a small increase in current requires a large decrease in VDS across the PFET, and hence a large drop in the output voltage. This example illustrates the value of being able to quickly conduct circuit experiments using the JADE tools in the interactive learning environment.
Easy experimentation is a key to gaining a thorough understanding of what is really going on.