It is helpful to understand the hardware you are trying to describe. Draw the logic that will behave like the following VHDL code segments. One must be careful not to synthesize latches where none are intended. Notice the definition of the outputs X and Y for each of the cases in the VHDL process.
Extra logic is synthesized to implement the priorities implied by the if statement.
Assign Device Max7000 family. Examine the report files to see what happened.