It is getting very difficult to do synchronous design. The skew allowed is very small. Conventional clocking schemes don't work for high performance computing. 400-401, Feb. 1998. In CMOS, when voltage is reduced, gates slow down but the energy per computation is reduced.
Idea here is dynamically adjust the power supply voltage.
Lower the supply when less performance is needed. 425-435, Dec. 1997. 252-253, February 1994. 25-26, June 1995. It would factor these inputs to minimize the energy consumed.