All instructions take one cycle to execute, but a few combinations are illegal or operate in parallel. Unlike interlocked RISC chips, the DSP3210 doesn't hide this from you. These cases can be divided into restrictions and latencies. You'll want to see the manual for examples. Don't loose any sleep over this one, either.
Latencies Pipelined chips often feel as if they're suffering from a little lag.
You tell the chip to do something, and it doesn't always complete before the start of the next instruction. However, it is still accepting new instructions. When you write to memory, the data spends the next three instruction cycles arriving, and is ready for the fourth. There's probably a few dirty optimizations here. Accumulator as Multiplier Input.