With the advent of Intel's Multiprocessor PC specification, two-processor machines are becoming common. Originally designed for symmetric multiprocessing, these machines are easily subverted to our needs. A simple first step is to separate the IP input and forwarding code from the rest of the system and run it on the second processor. With this design, packet routing performance is not subject to slowdown or variation when routing protocols or other user applications execute. This alone gives a large improvement.
Further improvements are possible.
With separate, large Level 2 caches for each processor, and correct memory layout and cache control policy, it is possible to ensure that the forwarding processor's L2 cache is used solely for the forwarding code and a routing table cache. The design of the hardware interrupt controller in these machines allows the forwarding processor to handle network interface interrupts while the control processor handles all others. In rare cases it may be useful for the control processor to handle the initial interrupt at high priority, and have it present the packet to the forwarding processor in a simple, low-overhead way. We're currently implementing these ideas, and hope to have measured performance results shortly. A key aspect of these designs, particularly the multiprocessor versions, is that CPU instruction count does not appear to be the limiting performance bottleneck.