This translates to a coding gain of 0.6dB for the same rate. However, Hermitian codes were deemed to be too complex to implement until the emergence of a recent algorithmic breakthrough with made the complexity of Hermitian decoders comparable to that of RS codes. Thus, the same IC can be used for decoding RS codes as well. The IC prototype consumes 3.0W with a 50MHz clock. I and Q data streams.
Input data is interpolated in four stages each interpolating by a factor two.
A converter which is integrated on the same silicon chip. Process used in realization of the chip is a 0.35 um BiCMOS process. However, only CMOS transistors are used. Realizations of demanding applications particularly in the field of mobile communications often require processing performance which is far beyond what is delivered by DSPs today. The DSP is based on a scalable architecture which supports customization depending on the application needs.