The second course presents Verilog for synthesis of digital systems. We begin with presenting point-examples illustrating various constructs of Verilog and how they synthesize to hardware. We will then present a complete digital system which will be described and synthesized into simulatable library components. Using a commercial synthesis tool, an online demonstration shows steps that are involved in synthesizing with Verilog. For the use of simulation and synthesis tools on Northeastern University computers, students will be issued access codes, provided they register at least two week in advance.
Lecture slides provide a complete reference for the material that is presented.
In addition, Northeastern University web pages include Verilog code for all examples that are being presented plus a complete set of other examples covering all hardware description aspects. The 1999 McGraw-Hill book, Verilog Digital System Design , discusses topics covered in these courses in greater detail, and is recommended for the series. This series can benefit engineers in migrating from conventional design methodologies to using Verilog for design and implementation of complex digital systems, or beginner engineers who are familiar with digital system design techniques and need to use Verilog in their hardware design projects. This series is intended for engineers, scientists, and instructors who are already familiar with digital system design.