OpenRISC 1000 Description OpenRISC 1000 is an architecture of a family of open source, synthesizeable RISC microprocessor cores. It is a 32-bit load and store RISC architecture designed with emphasis on speed, compact instruction set and scalability. OpenRISC 1000 targets wide range of embedded environments. Performance features include fully 32-bit architecture, powerful virtual memory support, cache coherency, optional SMP and SMT support and optional static scheduling information.
Architecture defines several features for embedded environments.
OpenRISC 1000 architecture is a predecessor of more powerful and feature richful next generation OpenRISC architectures. Most implementations will be designed modular and vendor independent. They will be able to interface with other open source cores available from this web site. Implementations of the architecture vary in performance and complexness. Opencores.org encourages companies to design and market their own implementations of the OpenRISC 1000 architecture.