Combined, the new design and faster bus will tend to accelerate large programs and data sets that don't fit in the cache. This pin count reflects the fact that like its predecessors, the 7200 supports external data and instruction caches with separate 64-bit interfaces. By current standards, the 7200 is only a modestly superscalar design. You can pair any two from different groups or two from the integer group. Branches are considered to be special integer operations that may be paired with their predecessor but not their successor.
Branch instructions employ static branch prediction.
To keep the pipeline flowing as smoothly as possible, instructions with data dependencies and resource conflicts should not be paired. The 7200 uses hardware checking for dependencies, but to save time, it performs some of this work as the instructions are loaded from memory into the instruction cache. The predecode bits add about 10 percent to the SRAM overhead. These caches have to be built from the fastest SRAM and must be able to cycle at full processor speed, which means a 6-nanosecond access time at speeds of greater than 120 MHz. Full associativity requires a lot of lookup logic and is too expensive for all but the smallest of caches.