The nice thing about this concept is that it has a 'built-in' bus mastering technique. If the bus is 'occupied' by a chip that is sending a 0 then all other chips loose their comm's capability. More will be explained about this further on in the Faq. However the open collector technique has a drawback too. If you have a long bus this will have a serious effect on the speed you can obtain .
Long lines present a capacitive load onto the output .
Since the pull-up is passive you are facing an RC constant which will reflect onto the shapes of the signals. The higher this RC constant the slower you can go. At a certain point the chip will not be able to distinguisch clearly between a logic 1 and 0. What's more is that you can get reflections at high speed .This can be so bad that 'ghost signals' disturb your transmission and corrupt the data you transmit. And then even the Shmitt trigger at the input of the chip will not keep you out of trouble Therefore some strict electrical specs have been set forth.