Also, once the design is partitioned into a few manageable blocks, engineers can work concurrently on them, reducing the elapsed time for the completion of the design. EDA tools work much better at these gate counts when compared to gate counts of two to five million gates. For better timing assurance, it's recommended that a register bank be added at the interfaces. This buffer is connected directly to the top-level clock buffer. Gated clock-tree expansion could be done at this stage as well.
Logic synthesis is performed based on the block-level constraints extracted at the top level.
Since the gate count isn't known at this time, an automatic wire-load selection is assumed. Setup times need to be checked in pre-layout stage using the MAX library. Hold check will be performed during timing driven layout or after the layout stage using MIN library. After synthesis, scan insertion is performed. Once this is finished, delay estimation of the block netlist is initiated.