Detailed timing information is available only in timing mode. In state mode, the logic traces represent signals that get sampled once per UUT synchronous clock cycle. The Timing Analyzer In timing mode, a logic analyzer acts exactly like a 1-bit digital oscilloscope. Figure 2 illustrates how state and timing analyzers measure logic signals that exhibit pesky analog behavior. A rising edge on the asynchronous clock triggers sampling of the A, B, and C signals at the logic analyzer.
Logic analyzers can employ a two-clock approach to derive state and timing information.
A and B are high, and channel C, the exclusive-OR of A and B, is low. The timing analyzer does describe this period. In this example, the pulse on C is fortuitously high during a rising edge of the asynchronous clock, so it is properly sampled. To prevent this sort of glitch from escaping unnoticed, most timing analyzers include circuitry that continuously looks for logic transitions. If this circuitry detects at least one transition between successive sample points, but the sampling circuitry doesn't report a change of state, then the instrument reports a glitch, illustrated by the red icon beginning at 13.75 ns in Figure 2.