The logic used was chosen from commonly available FPGA hard macros. The instruction coding allows 128 different opcodes. The instructions necessary to do useful work were created first. Then, less useful instructions that didn't complicate the decode logic were added. Assigning opcodes was a balancing act between functionality and decoder complexity.
Execution is pipelined.
The decode logic is a stage in the pipeline so it has one cycle to settle. Jumps, external memory cycles, etc. The decoder pipe doesn't get cleared, so the instruction immediately following a jump or call gets executed just after the jump. There are some restrictions on the placement of some instructions in groups. For example, calls, jumps and some memory instructions must be the next to last instruction in a group.