Energy is conserved by grouping operations in the most energy efficient patterns based on their critical path delay or the time it takes to complete the operation. For example, Narayanan says, consider a circuit that includes three adders and a multiplier. Adders have a smaller critical path delay than multipliers. Grouping one of the fast adders with the slower multiplier allows the researchers to slow the adder down to the speed of the multiplier without slowing the overall process. To slow the adder down, the researchers supply it with a lower frequency and voltage which conserves energy.
Higher voltages make signals propagate down wires faster but require more energy.
The researchers have, so far, performed simulations of their approach for some benchmark circuits particularly useful for signal and image processing computer architectures. They found that, with a suitable choice of voltage levels, their approach produces an average energy saving of 53.5 percent versus the standard, static clocking scheme and single supply voltages. However, the authors note in their paper that their algorithm can be applied to any other combination of resource and time constraints. Certain procedures in such applications require only logic functions, while others require only additions and certain others multiplication or division. Currently the research team is investigating using multi-cycling and chaining in conjunction with their approach for further performance improvements.