On a contrary, partitions based on signal reconvergence have been shown to lead to much improved logic optimization results for large circuits. Although the formulation and the implementation are general, we demonstrated the application of our method using circuits generated with a commercial tool and partitioned for implementation with specific library of Xilinx's FPGA devices. All contributions have been justified through the comprehensive report on the experimental work. One of the most important objective in design process is an implementation of a digital circuit for optimal performance. We amended the proposed k-way partitioning algorithm with the concepts from performance optimization that target the minimization of critical delay in a circuit.
Experimental results demonstrate the efficiency of the proposed approach.