The DC Inhibit mode provides external control of the gating period. Norm Input pulse will be gated through to the output during a gate width interval following the leading edge of each Enable Input pulse. Pulse Inhibit Input pulses will be inhibited from passing through the output during a gate width interval following each Enable Input pulse. DC Inhibit Input pulses will be inhibited from passing through the output during intervals of pulses or dc levels through the rear-panel DC Inhibit connector. 12 V maximum.
Input is ac-coupled with a passive symmetric baseline restorer.
BLR can be bypassed for dc-coupling.