Each memory cell consists of six transistors. The CY7C1380B and CY7C1382A SRAMs integrate 524,288x36 and 1,048,576x18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. DQa,b,c,d and DQPa,b,c,d apply to CY7C1380 and DQa,b and DQPa,b apply to CY7C1382.
Individual byte write allows individual byte to be written.
BWa controls DQa and DQPa. BWb controls DQb and DQPb. BWc controls DQcand DQPd. BWd controls DQd-DQd and DQPd. GW being LOW causes all bytes to be written.