Each memory cell consists of four transistors and two high valued resistors.
Individual byte write allows individual byte to be written.
GW being LOW causes all bytes to be written. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. All inputs and outputs are TTL-compatible. The device is ideally suited for 486, Pentium , 680x0, and PowerPC systems and for systems that are benefited from a wide synchronous data bus. Cypress Semiconductor Corporation.