The huge effort needed to create functional test vectors can be avoided except for those parts of the design where simulation makes sense, and a thorough verification can be achieved in a much shorter time than using simulation. Unlike simulation, which only shows the presence of bugs, formal verification can prove their absence. When errors are found, formal verification tools can also generate counter examples to demonstrate the error conditions. This enables designers to complete verification tasks faster and with a much higher level of confidence. Formal verification has become an essential technology for solving today's verification problems.
Formal verification can be valuable throughout the design process.
In the design creation stage, formal verification tools can show whether a design satisfies certain desirable properties and can derive functional vectors to demonstrate the violation of such conditions. At some point, blocks from various designers must be gathered together and verified as a full-chip system. Formal verification is highly useful for this stage, since it does not require each designer to have detailed knowledge of all other blocks of the chip. Instead, each designer can focus upon verifying interface constraints that are specific to their own blocks. In addition, it is often necessary to tweak the logic to correct timing problems after layout.