They also had to effectively manage multiple clocks and timing domains to support the 100 Mbps Ethernet interface. The nice thing about Synopsys synthesis is that the designers can easily swap processes. Because they had built up a script methodology for running synthesis, they simply retargeted the design by changing the technology file and using the new 0.5-micron library. Putting the whole LinkSwitch 1000 system together and validating that not only the hardware, but also the software performed to specification was by far 3Com's greatest challenge. Since we used multiple chips within the system, there were various combinations depending on the scenario we wanted to check.
Ethernet can generate some very complex situations with the possibility for packet collisions.
To cover all scenarios, we performed simulation at the base module level, the module within the ASIC and the ASICs within the system. At the module and single chip levels, 3Com used Verilog-XL for simulation. To check the board and system-level functionality of the LinkSwitch 1000 design, 3Com assembled a comprehensive system simulation and prototyping environment. This environment was based around Synopsys software and hardware modeling tools, and some specialized test equipment for automatic data generation at random times. The latter automatic packet generators helped 3Com test the LinkSwitch 1000 for all possible network problem areas such as short packets, long packets, collisions etc., and was one of the reasons why the product shipped early.