An RTL circuit is generated following the scheduling and assignment phases. The RTL designs produced may not be optimized for area, and may not be completely testable at the gate level. The optimized RTL circuits are completely testable under full-scan at the gate level. In general, there may be multiple solutions to the scheduling, assignment and RTL generation tasks. Hence fast and accurate estimation tools are essential to evaluate the quality of different possible implementations.
Good techniques exist for area estimation.
In this dissertation, we develop efficient techniques for estimating the number of clock cycles required to execute a specification and the clock period of the implementation.