The buffer is organised as 2 times 32 bits. The FADC outputs are organised as shown in table . The external trigger follows the same rules as the analog trigger and could be generated from the slow control board by software or any external source. 4.2.1 External trigger connector 2 pins, 2.54 mm pitch, ribbon cable connector. Double buffering is implemented in order to minimize the dead time and be compatible with the reference design 3 .
Figure shows the timing diagram.
Timing diagram in the case of two buffers. In the shaded area the 2 buffers are full. This section makes some suggestions about implementing the buffering, for single buffer only. When the FIFO contains M samples, each new write into the fifo is immediatly followed by a read from the fifo. When a trigger has occurred, this mechanism is stopped and the FIFO is filled with the N-M remaining samples.