We propose the use of a graphical environment based on dataflow graphs to capture suitable algorithms. Furthermore, FPGA emulation or ASIC design can be started from the same dataflow graph which has already been validated, yielding improved confidence and efficiency of the design flow. A real-world design example shows the feasibility of this approach of handling the complexity and heterogeneity of many algorithms found in mechatronics applications. The reprogrammable system architecture allows prototyping of different topologies, communication types and protocols and will be supported by a powerful tool set for automatic system configuration. This paper presents a hardware based approach to Fault Emulation without a dedicated logic emulation system.
Logic is introduced for fault injection in a targeted circuit.
The logic emulator is expanded with additional hardware modules required for the Fault Emulation process. When tested on combinational circuits using a commercial emulator, speeds varying from a few kHz to several MHz were reached. The efficiency of this form of fault injection is illustrated by the experimental results presented here. An extension to the cyclo-static dataflow graph model is proposed. If this part of the application is to be synthesized from a specification to a software or a hardware realization both automatically and efficiently, a systematic approach is to be taken for that data routing.