This is called 'strobing the decode signals'. If you study the accompanying timing diagrams, note that the glitches for state 4 decode signal have dissappeared. Notice also, that the decoded state 4 signal is shorter in duration than it was before, and shorter than the decoded state 7 signal. 7.31 Draw the complete waveforms at the output of the decoding gates of a MOD-16 ripple counter, including any glitches or spikes that can occur due to the FF delays. Using the timing diagrams with the decoded states shown, we can list the state sequence along with the intermediate false states.
False states occur whenever more than one bit has to change.
The number of false states between any two normal states can be determined by subtracting 1 from the number of bits that must change to produce the new state. When advancing from an even state to an odd state, only the LSB will need to change, therefore there will be no false states in moving from even to odd.