Each memory cell consists of four transistors and two high-valued resistors. The CY7C1347D SRAM integrate 131,072 x 36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. Write cycles can be one to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written.
BWa controls DQa. BWb controls DQb. BWc controls DQc. BWd controls DQd. GW being LOW causes all bytes to be written.