A 64Mb DRAM would hold 335K such configurations. In practice, a perfect packing is difficult to achieve due to connectivity and dependency requirements such that configuration memories are required. Our is based on a DRAM cell design which is 600 per memory bit, making the memory cells 2 smaller than an SRAM implementation. Of course, there are many issues and details associated with multicontext computing devices. In this section, we will walk through a specific design example in order to make the previous discussion more concrete and in order to motivate additional issues.
Figure describes the basic conversion task.
Figure shows the LUT mapping both in equations and circuit topology. If we cared only about achieving the highest throughput, we would fully pipeline this implementation such that it took in a new character on each cycle and output its encoding three cycles later. Assuming this is the only limit to cycle time, the implementation could achieve 140 MHz operation. Notice that the only reason we had to have any more LUTs or LUT descriptions than strictly required by the task description was in order to perform signal retiming based on the dependency structure of the computation. If, instead, we cared about the latency, but did not need 140 MHz operation, we could use a multicontext device with 3 LUT descriptions per active element.