The second unit also contains a multiply and divide unit. If a second FXU instruction exists in the FXU instruction buffers, and its input operands are available, the issue logic sends it to the second unit. To minimize data dependencies, the upper portion of the second unit has a three-input adder. Since address generation uses the GPRs in the FXU, the FXU executes all storage reference instructions, including the address translation and D-cache directory search. Both execution units work together on multi-cycle load and store operations.
Dual units allow execution of two floating-point instructions per cycle.
Since loads do not overwrite the previous data in the architected register, functional units may execute a load before the completion of a logically previous arithmetic instruction, even if it loads an FPR which is a source operand for the arithmetic. This is a substantial benefit on short loops where register renaming can not be done in software. Moving the loads further ahead allows the effects of load-use delay to be minimized. To support the increased number of functional pipelines, the FPU supports 54 physical registers. Usually the FXU can only issue an instruction to the second functional unit if two instructions are ready for issue simultaneously.