This results in a bottleneck that can severely limit the processor execution engine. Increasing throughput requires increasing the frequency or width of the bus. Each is 8 bytes wide, thus doubling the available channels for data. For example, with the single bus in Socket 7 architecture, there is only one path for data to travel to and from the processor. The analogy is a one-way road in each direction.
Congestion results from limited access to the processor.
In contrast, D.I.B. architecture provides two paths to and from the processor. It is like a large freeway with two lanes in each direction. The dedicated bus for the L2 cache removes traffic from the crowded system bus. The pipelined system bus enables simultaneous parallel transactions accelerating the flow of information within the system and boosting overall performance. The new cartridge package and associated Slot 1 infrastructure provide headroom for future high-performance processors.