The structural description of the Am2901 follows a hierarchical approach. First, each functionnal block is described as a separate gate netlist. The next hierarchical level is the heart that interconnects these five blocks among each others. The final hierarchical level is the chip that connects the heart to the pads . The chip.c file uses the genlib language to describe these 7 hierarchical blocs.
Environment variables allow to set the formats.
The .vst extension corresponds to the structural VHDL . All netlist files created and used by genlib will now be structural VHDL . The 7 files alu.vst , accu.vst , ram.vst , muxe.vst , muxout.vst , heart.vst and chip.vst have been created. The various netlist files we have created represent the structural description that should be validated by simulation, using the same patterns as in step 1. Note the -b option does not appear any more, since we now have a structural model.