Requirements on low power, low voltages, and higher densities have led to the development of devices which use Fowler-Nordheim tunneling for both programming and erasing. Multilevel cells which allow storage of more than one bit of data per cell are also drawing a lot of attention. However, the clear trend is towards the use of single-voltage supply. For example, in the case of single-voltage NOR based flash devices from AMD, a positive bias is applied to the source, and a negative voltage is generated internally to be applied to the gate. Although at present, a majority of the flash memory devices are for 5V systems, new devices which operate at 2.7V are emerging, with 1.8V devices on the horizon.
Flash memories have unique quality and reliability testing issues.
Besides memory related issues such as data retention, cycling endurance, cell disturbs, and erase control, flash devices need to be tested for proper functioning of an embedded state machine. As a result, flash memories present a unique challenge to build both analog and digital testability on chip. In this paper, we will review the history of flash memory development, the physics behind the operation of flash memory, various technological approaches, testing issues, and the future anticipated developments for flash memories. A concurrent strategy in which placement and routing activity proceeds in parallel with circuit design and layout tasks is presented. In addition to improving the design cycle time, this strategy helps in providing an early estimate of the layout parasitics which can be used to improve the accuracy of the simulations.