Each memory cell consists of four transistors and two high-valued resistors. SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. Write cycles can be one to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written.
GW being LOW causes all bytes to be written. All inputs and outputs are TTL-compatible. The device is ideally suited for 486, Pentium , 680x0, and PowerPC systems and for systems that are benefited from a wide synchronous data bus. Cypress Semiconductor Corporation. All rights reserved.