When a system is partitioned into separate components, versus a single SOC, the components can be optimized for manufacturing cost as well as performance. The wafer fabrication process can be simplified, yields can be improved, and die size reduced. In addition to reducing die area by partitioning functions like memory, logic, and analog into separate die, changes to the interface circuitry can produce a more efficient die layout. Voltage reduction or simplification is also desirable. This not only reduces power but also simplifies IC design and manufacturing.
Full optimization occurs when the system interconnect and die are co-designed.
In some cases, this can eliminate the need to add expensive copper processing to the IC wafer. The bus standards that have been developed for PC boards are too restrictive, consume too much power, and retard bandwidth. The act of multiplexing always adds latency and is likely to increase power dissipation by causing extraneous bit transitions on wires. Multiplexed architectures force dissimilar bits to coexist on a physical wire, leading to a source of extra power consumption. The technique of doubling the number of pins to separate input and output paths to avoid bus turnaround and contention inefficiency are very rarely used off die, although this is a routine technique to improve performance on die.