Synopsys developed Formality to provide the performance, capacity, debugging and flexibility for successful SoC designs. Formality Provides Powerful, Graphical Diagnostic Analysis and Schematic Debugging Introduction Formality is a new equivalency-checking, formal verification tool that was designed to address the problems associated with verifying large SoC designs. When used together as part of a new verification methodology, these tools will reduce the amount of gate-level simulation runs, thus enabling designers to complete their design faster and with a higher level of confidence.
Formality offers unique benefits to designers.
Its superior performance and capacity allow multiple analysis runs in a single day, thereby completing verification faster and offering exhaustive verification coverage of the design. Formality's powerful debugging features enable designers to isolate and repair problems quickly and are easy to use and interpret. Formality is also the only commercially available formal verification tool that integrates verification and debugging within a single tool. Formality's tight integration with Design Compiler enables the designer to take advantage of Formality's superior feature integration and data handling techniques specific to the synthesis-based design flow. It has been designed for optimal performance through a flexible verification environment and multiple solver architecture.