As soon as the bitlines are properly precharged, the next cycle can begin. Please note that if the timing terms tasu and tah are not met, the possibility exists that data in the RAM will be corrupted. This possibility exists not only during a write cycle, but also during a read cycle. The following table shows available sizes. There is a tristated and a non-tristated version of each size.
All timing is relative to the rising edge of the clock.
Though this is published at Typical process parameters, the worst case speed can be estimated by scaling the typical cycle time by a factor that depends on voltage and temperature. Because all inputs are latched, the inputs must meet setup and hold times with respect to the rising edge of the clock. The WRT control input is active high for a write cycle, and is deasserted low during a read. The OEN input is asserted low to enable the Qi outputs to be driven onto their bus.