The extremely high instruction rate achieved by these processors place extraordinary demands on memory system design if maximum throughput is to be sustained and costs minimized. Static RAM offers a simple solution for high speed memory systems. However, high cost and low density make this an expensive and space consumptive choice.
Dynamic RAMs are an attractive alternative with higher density and low cost.
Their drawbacks are, slower access time and more complex control circuitry required to operate them. The access time problem is solved if DRAMs are used in page mode. The device manages one or two-way interleaved arrangements of DRAMs such that during burst access, data can be read, or written, at the rate of one word per system clock cycle. The full range of processor speeds is supported for a wide range of DRAM speeds, sizes and organizations. It reduces design complexity, space requirements and is fully derated for loading, temperature and voltage.