The method is inspired by the fact that power analysis performed on a technology mapped network gives more realistic estimates than at the technology-independent level. After the switching activity of each node in the circuit is determined, high power nodes are eliminated through redundancy addition and removal. To do so, the nodes are sorted according to their switching activity, they are considered one at a time, and learning is used to identify direct and indirect logic implications inside the network. The end result is a circuit with a decreased switching power.
Experimental results show the effectiveness of the proposed technique.