Instead, the whole operation is achieved in the form of hardwired logic. This greatly accelerates the execution of an instruction. For a RISC CPU the chip designers put the complexity in a complicated hardware multiplier. Due to the reduced number of machine instructions, there is now enough space on the chip for implementing such highly complex circuitries. The execution structure of an instruction is, as a result of the basic microprocessor working principles, the same for the majority of machine code instructions.
Every instruction is broken down into partial steps for execution in the stage pipeline.
The partial steps are executed within one single clock cycle i.e. instruction 'k' needs five clock cycles to complete but then at the pipeline output, an instruction result is available with each clock cycle. The result would be a four-stage pipeline. In practical terms, superpipelining will never give you more than a 2x improvement in performance. Another possibility for increasing the performance of a RISC microprocessor is the integration of many pipelines operating in parallel. With this method, the result is a superscalar.