One for each channel. This signal is asserted by the device to indicate the end of the DMA operation. In our case it should be tied to the FIFO Empty signal. DMA Data Transfer. This signal is asserted by the DMA controler.
Figure shows the sequence of signals in the case of fly-by burst high priority.
The basic design makes provision for a simplified digital trigger daughter board. Later on one will provide a Front-end board version with a more complete connection permitting the test of daughter board implementing the reference design digital trigger and buffering. In that case the buffering is not implemented on the Front-end board itself. The list of signals is shown in table . Figure 5 shows the geometry of the, optional, digital daughter board.