Many place and route systems can insert clock trees with balanced delays into a design to prevent excessive skew in large clock networks. After clock-tree insertion, the design contains nets and gates that were not present prior to layout, causing a problem for backannotation. Delay data, including these clock-tree nets, cannot be applied directly to the original design. We solve this problem by calculating the total delay across the clock tree, and use SDF port delays to apply this delay to the original design. Final processing Final processing includes layout design-rule checks to ensure that the design does not violate technology size and spacing limits.
LVS tests ensure that the logic extracted from the physical layout matches the original design.
After these final steps, the design is ready for manufacturing. What we learned The VHDL design system depends on EDA standard formats. Fortunately, EDA vendors are motivated to ensure that their tools operate with the products of other companies, so these differences are usually resolved in later releases after standards documents have stabilized. The models created by the Synopsys Library Compiler were satisfactory, but they needed manual modifications to meet our sign-off requirements. To have more control over the format of the models, we will develop software to create future versions of the library.