High Performance, Mixed-HDL Simulation Using the MX solution, design teams can mix design IP regardless of the source language, without changing their native simulation environment. Additionally, VHDL designers can take advantage of the VCS gate-level performance using VCS supported technology libraries. VCS is the primary simulator for our Verilog designs, so we found it extremely useful for our engineers to continue working in a familiar simulation environment while integrating VHDL IP into our latest design. Complete Functional Verification Solution Synopsys provides a complete line of functional verification solutions supporting Verilog, VHDL, and mixed-HDL, for complex SoC designs aimed at achieving the highest functional coverage in the shortest amount of time. Customers with both Scirocco and VCS licenses get the MX solution at no charge.
All solutions are available immediately.
It was not long ago that almost all ASIC designs were done in Verilog. Everyone is aware of the verification problem. Synopsys is announcing both an improved Verilog VCS simulator, Version 6.0, and a mixed-language capability. The claims for the new version of VCS is that execution times have been improved by a factor of up to two at the RTL level and by a factor of up to five for gate-level simulations. Scirocco is the company's VHDL simulator.