One way to derive the interface timing is to refer it to another existing spec. Contention and Cascading Contention occurs when both ports try to access the same address at the same time. In asynchronous devices, arbitration logic provided to the dual-port takes care of arbitration and therefore saves the system designer the need for external logic to solve the problem associated with bus contention. Another attractive feature is the presence of two chip enables with different polarities for each port. This provides the ability to easily expand the depth and the width of the RAM by cascading two or more devices to create deeper and wider interfaces at very high speeds without the need for any external logic.
All signals are synchronous and are asserted at the rising edge of the port clock.
Such an operation provides the ability to free the address bus. If no other task is required by the system, then power can be saved by disabling the address generation during burst mode. The burst operation allows the sequential access of the memory. The dual-port can be used as a FIFO by connecting all address lines to logic level 0. The counter has the capability of addressing the entire depth of the memory array and wraps around to location zero.