In a write-cycle, new data values are driven onto the bitlines during the evaluate state to rewrite the selected core. This is the self-timed feature. Because it happens in hardware, not on the trailing clock edge, the user does not have to hold the clock signal asserted until the proper time, nor waste time by providing useless margin past the proper time. Output data are latched, and the user samples them while the bitlines are pulled to their precharged high state. As soon as the bitlines are properly precharged, the next cycle can begin.
All timing is relative to the rising edge of the clock.
Though this is published at Typical process parameters, the worst case speed can be estimated by scaling the typical cycle time by a factor that depends on voltage and temperature. Because all inputs are latched, the inputs must meet setup and hold times with respect to the rising edge of the clock. The WRT control input is active high for a write cycle, and is deasserted low during a read. The OEN input is asserted low to enable the Qi outputs to be driven onto their bus.