This document describes how the DSP processes TDC edge data and defines the format of the hit words. Some preliminary results of processing times are also included. The DSP used is a Texas Instruments TMS320C32. Upon witnessing a L2A the DSP must poll TDC chips for valid wire data. The DSP can be programmed to have dedicated machine instructions for the purpose of reading the TDC chips in a loop.
Every channel is read until it is empty.
This method is straightforward, but since the CPU can only be used for one task at a time. It is possible for the DMA to perform TDC reads while the CPU is used to perform some other function such as constructing header word fragments. This method requires detailed management of DSP resources , such as internal DSP SRAM to avoid CPU-DMA conflicts. These leading or trailing edges are stored along with the time they passed out of the TDC digitizing buffer relative to a L1 Accept, up to a maximum time of 2047 nanoseconds. The DSP has the duty to construct hit words from a given channels edges.