The simple ideas will continue to be quickly promoted and accepted, with most of them leading to understated disappointments. I only hope for many simple, good ideas. Several will fail, but one or two will revolutionize the industry. I hope readers will get a better appreciation for the difficulty and the rewards in a functional verification task well done. The prevailing attitude in the industry is that design is fun, and verification is the necessary evil.
Every engineer wants to be a hardware designer when they grow up.
In too many Verilog or VHDL training classes or books, the topic of verification is quickly glanced over or simply ignored in favor of the all-important RTL coding and design. I also want my readers to realize that design verification requires a different skill set from hardware design. I do not wish to minimize the expertise of the hardware designer. The designer is an optimist who thinks in terms of clock cycles, finite-state machines, datapaths, and timing closure. A verification engineer is paranoid and thinks in terms of transactions, protocols, data abstractions, random operations, and failure modes.