This slide gives you more detailed interconnect layout of XC4000. Each CLB has two tri-state buffered long lines, possibly suitable for global buses. One common scheme for routing lines spanning multiple CLBs is to transpose them with each other, which makes sure that all CLB is identical. This feature might be also helpful to reduce the cross-couple noise. The model, in particular, is showing that we expect the larger device families to require more area per 4-LUT due to more required interconnection.
Longer communication pays more delay penalty on interconnection.
This is an abstract-level description of the flow of FPGA programming. One important issue is to adapt cost models to map properly to FPGAs, since the relative costs of logic functions are different than custom chips. For instance, since flip-flops are already built into each CLB, we should use pipelining as much as possible. Another example is that one-hot encoded FSMs is preferable to densely encoded FSM state bits due to the relative inexpense of FFs. We usually first pack logic into LUTs, and then try to build logic elements out of these LUTs and the surrounding resources.