The latest and greatest family of programmable logic from Altera is the Max 7000 family. A three-state output buffer in a PLD implies that the pin may be used for either input or output at different times. AHDL is an acronym for Advanced Heuristic Design Logic. To fully verify a combinational circuit's operation, every possible input combination must be applied during simulation. Metastability is a problem caused by excessive pulse width on a set or reset signal entering a latch.
Latches always change state on a clock edge.