The number of cycles is supposed to be less than the value at the knee of the curve separating the useful life region from the wearout region. In practice, the stated level should be significantly less than the actual value at the onset of wearout. During the useful life region, there will be a small, but constant failure rate. The issue facing manufacturers is to assure each device has been screened to eliminate infant mortality , has an endurance value greater than the stated level, and the failure rate in the useful life region meets industry standards. Initial defects determine the duration and failure rate in the infant mortality region.
Latent defects establish the failure rate in the useful life region.
Generated defects and uniform degradation determine the onset of the wearout region. Latent and generated defects are random events that are difficult to measure and predict, so that specific devices with different intrinsic endurance values are difficult to identify. The relative frequency of the four categories is technology dependent. For example the thin oxide approaches used by stacked gate and two transistor manufacturers are most susceptible to latent and generated defects, while the thick oxide approach is most susceptible to uniform degradation. Latent and generated defects are minimised by the use of thick oxides, in addition to normal wafer fabrication cleanliness and statistical process control.