Zhang's Research Research and Projects Synthesis algorithms to optimize circuits at gate level with gate resizing, supply voltage scaling, threshold voltage scaling and glitch reduction techniques. Formally proved complete library gate resizing problem is polynomial time solvable for the first time. Implemented a system to optimize power consumption of circuits on standard-cell library with cells of different sizes, and supply and threshold voltages.
Low power register allocation algorithm.
Developed a compiler in C to generate low power software. Designed a multi-cycle RISC processor. Developed RTL VHDL for control path, and synthesized by Autologic. Developed a Xilinx FPGA testboard for testing. Designed a transistor-level SRAM with four different sense amplifier Schemes.