It enables the architecture of the processor to be modified to closely match the architecture of the computation problem, offering the possibility of very high performance. However, fine-grained reconfigurability exacts a high price in area and performance. The RDPP falls between the DSPs and the CPLDs, with multiple, configurable processing elements connected by a configurable data path. The strategy is to carefully design the processing elements at the circuit and gate levels, yielding high-performance units. Control of the switching threshold is managed through dynamic back-bias techniques.
Latchup immunity is achieved through layout techniques.
Low-power design in conventional CMOS seeks to limit dynamic power dissipation by minimizing the amount of switching activity. This encourages vertical designs, with little parallelism and no wasted switching events. While dynamic power is significantly reduced, static power dissipation, due to leakage in parasitic source and drain diodes, is proportionally more significant. Static power dissipation is independent of the amount of switching activity, but is proportional to the source and drain area, and so increases with an increase in the number of transistors in the circuit. To maximize the power savings in the ULP technology, we avoid designs incorporating large numbers of idle transistors, such as memories.