There are situations, called hazards , that prevent the next instruction in the instruction stream from being executing during its designated clock cycle.
Hazards reduce the performance from the ideal speedup gained by pipelining.
They arise from resource conflicts when the hardware cannot support all possible combinations of instructions in simultaneous overlapped execution. They arise when an instruction depends on the result of a previous instruction in a way that is exposed by the overlapping of instructions in the pipeline. Hazards in pipelines can make it necessary to stall the pipeline. A cache miss . A cache miss stalls all the instructions on pipeline both before and after the instruction causing the miss.