Some of the new, larger FPGAs or PLDs offer some nice extra features. For instance, some of Altera s largest PLDs offer the ability to probe some signals during operation through the JTAG port, providing something like a virtual logic analyzer. Altera and Xilinx are offering digital delay loops to help synchronize clocks to external signals. The importance of global clocks is a worthwhile discussion topic during FPGA design. Global clocks should be considered for the multiple clock sources needed in many designs.
Global clocks allow logic such as synchronous counters to function without glitches.
Using cliques can help place the logic cells for the counter close enough together that they receive the clock virtually simultaneously. No hold time. With global clocks, usually, no data hold times are required. The particular chip select line coming from the 860 was de-asserted at approximately the same time as the address and data. Bringing the chip select from the 860 microprocessor to a global clock input of the FPGA solved the problem.