As the manager of ASIC development, Hoogenboom recognized that his decision on a formal-verification tool would be critical. Based on his past experience in ASIC design and the project's complexity, Hoogenboom made the decision to use a formal-verification tool early on in the design cycle. A formal-verification tool, he understood, would address the problems ASIC developers typically face in attempting to verify an extremely complex design within the constraints of the market window. ASIC designers in the networking industry are frequently unable to simulate extremely complex designs well enough to validate their functionality. Our hand-chosen subset of simulation vectors required eight CPUs running for two weeks, using a lot of market time to achieve partial functional verification.
Formal verification is the obvious solution.
In the end, Xylan selected Synopsys' Formality for a variety of reasons, not the least of which was Synopsys' expertise in ASIC development tools. The other Synopsys tools we have work very well and are very well supported. Hoogenboom evaluated two verification tools for two to three months before choosing Formality for its superior performance and capacity. In the end, Formality played a key role in the verification process, proving its value early on in the development cycle. Formality saved us months in delay to market as well as substantial sums of money.