You can try to introduce a schematic error by modifying the chip.c file, running genlib and asimut to see the errors. 3 Physical Design Building the heart, and routing the heart to the pads are quite different jobs. So we use different tools. 3.1 Routing the heart Scr is a standard cell placing and routing tool. Here again Alliance accepts several external file formats for the symbolic layout.
Environment variables allow to set the formats.
The hierarchical netlist will be flattenned before routing. The output layout will be heart.ap . The symbolic layout file heart.ap has been created. The extracted netlist file heart.al is created at this level. The next tool is the net-compare lvx that performs a netlist comparison between the input netlist heart.vst and the extracted netlist heart.al , after flattening to the gate level.