Each memory cell consists of six transistors. The CY7C1381BV25 and CY7C1383BV25 SRAMs integrate 524,288x36 and 1,048,576x18SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation.
Individual byte write allows individual byte to be written.
BWa controls DQ1 DQ8 and DQP1. BWb controls DQ9 DQ16 and DQP2. DQ17 DQ24and DQP3. BWd controls DQ25 DQ32 and DQP4. GW being LOW causes all bytes to be written.