The ADC08351 uses an unique architecture that achieves 7.2 Effective Bits with a 4.4 MHz input and 42 MHz clock frequency and 6.8 Effective Bits with a 21 MHz input and 42 MHz clock frequency. Output formatting is straight binary coding. To minimize system cost and power consumption, the ADC08351 requires minimal external components and includes input biasing to allow optional a.c. input signal coupling.
Many applications require no separate reference or driver components.
Total power consumption is reduced to less than 7 mW in the power-down mode. If you have trouble printing, see Printing Problems . If you have trouble printing, see Printing Problems . Quick Search Parametric Search System Diagrams Product Tree Home About Languages . Website Guide .