A revised specification is given below.
Bold typeface indicates new specs.
For your orientation, architecture diagrams for the XC4000 Family CLB and IOB Blocks are given in your Lecture Notes. You can also research the Xilinx Web site for more info on the XC4005E chips. In the schematics, represent the FPGA chip by a rectangular block with signal names assigned to the appropriate pins. Comment on your simulation results. Attach a hard copy of your .abl, and .cmd files, the simulation timing diagram with comments, and the Pad Report to your Project Report.