When a board observes a write to memory, it checks its own cache and, if it has a copy of the same line, it invalidates that copy. This design, often called snoopy coherency because each CPU reads its neighbors' mail, works well when all memory access uses a single bus. The cache coherency design of the Origin2000 is fundamentally different from that of its predecessor. In the Origin2000, there is no central bus. Memory access packets can flow within a node or between any two nodes.
Cache coherency is implemented using what is called a directory-based scheme.
These extra bits are called directory bits. The directory bits are managed as part of memory by the hub chip in the node that contains that memory. The directory bits are not accessible to user-level software. When a CPU accesses an unmodified cache line for reading, the node that contains the memory sends the requested cache line, and also sets the bit for the reading CPU's node to 1. When a CPU discards a cached line for any reason, the corresponding bit is set to 0.