The goal of simulation is to verify that the design you entered, via schematics or AHDL text, performs properly according to the problem specifications.
All devices operate with zero propagation delay and zero setup and hold times.
But Functional Simulation has advantages over a full Timing Simulation. It is faster to compile the design for Functional Simulation, so you can find errors faster. Every internal node is available for examination during the simulation, since no logic is reduced or modified, so it may be easier to find the cause of problems. No timing problems are shown, so there is less to worry about at this point, so you can more easily find basic logic problems. So there are good reasons to do a Functional Simulation, but you have to eventually do a Timing Simulation to find any timing-related problems before actually program ming a real PLD and plugging it into your circuit board.