The bus adapter provides a connection to an asynchronous bus that is constrained to matching the characteristics of the synchronous bus. Usually, in such architectures, the synchronous bus is a custom design that is found only on the CPU board itself, and possibly on memory expansion daughter cards, although systems have been designed in the past with such buses on custom backplanes to facilitate memory expansion. In many such applications, the synchronous control scheme is even further simplified by the fact that there are only two potential bus masters. The arbitration can be either central or distributed. The central arbiter can determine priorities and can force termination of a transaction if necessary.
Central arbitration is simpler and lower in cost for a uniprocessor system.
It does not work as well for a symmetric multiprocessor design unless the arbiter is independent of the CPUs. In the distributed scheme, every potential master carries some hardware for arbitration and all potential masters compete equally for the bus. The arbitration scheme is often based on some preassigned priorities for the devices, but these can be changed. Daisychaining is a hybrid of central and distributed arbitration. Devices request the bus by passing a signal to their neighbors who are closer to the central arbiter.