Both of these are sourced from the system controller. A processor reference to an undefined location will silently return undefined data on a read or silently accept data on a write. Writing to an undefined location may generate an undesired side effect. The Rev 1 board memory maps have been copied to the end of the document until the Rev 2 boards are functional and have replaced the Rev 1 boards.
All registers are in big endian order.
FFFF 4 MB L2 cache tag test range Only valid when the L2 cache tag test bit of the Control register is set. Cisco Systems Inc. All rights reserved. Important Notices and Privacy Statement .