Complex instructions and addressing modes mandate microcode or multicycle execution. In addition, they complicate the design of the processor hardware and the compilers. All other instructions operate on data in registers. A Load instruction moves data from system memory to registers, where the data can be rapidly processed and temporarily held for further access. At the appropriate time, a Store instruction returns the data to its place in system memory.
Conventional computers support instructions that process information directly in system memory.
Pipelining Modern processor design generally includes a multistage pipeline to increase the rate of instruction execution. Because each stage is responsible for an individual execution phase, such as instruction decoding or operand fetching, a pipelined processor is actually working on several instructions at once. Conventional processor pipelines are subject to various kinds of inefficiencies that slow execution or even temporarily stop it altogether. The predictability of the time required to perform operations in a RISC design allows pipelines to operate at maximum efficiency. In those instances when a memory reference cannot be avoided, the complier can rearrange instructions so that useful work not dependent on the referenced data can be performed while the processor is waiting for the data to be loaded into a register.