CPU recognizes that an interrupt has occurred as one step in its instruction cycle. CPU asserts an interrupt acknowlege on the bus.
Device puts a small integer called interrupt vector on the bus.
ISR determines specific device that caused interrupt. Service the device. Restore all saved registers. Since an interrupt could occur at any time it must be completely transparent to any program executing on the machine. Tanenbaum distinguishes interrupts which are asynchronous from traps which are synchronous and caused by program conditions such as divide by 0.