150mV. Vrst is usually operated in the 0.5V to 1.0V range. Biasgate is used to adjust the speed and dynamic range of the unit cell source follower. A trade off can be made between speed and dynamic range by adjusting Biasgate from 3.3V to 3.8V. Lower voltages increase the speed at the expense of dynamic range, while higher voltages increase the dynamic range at the expense of speed. A typical Biasgate voltage of 3.5V is used for initial characterization of the hybrid. The Source and Bus pins on the carrier are two simultaneous outputs available on the multiplexer.
Bus is connected to the gate of the output source follower.
Replacement of the Clear clock function with a Read clock function. Reduction of pixel pitch from 40 m m to 18.5 m m. This means that at any time while accessing a row, the entire row will be reset when ResetB clock is pulsed low. This also true for Fsync and Line inputs for the vertical register. The two remaining clock inputs are ResetB and Read .