For a detailed definition of the system behavior within each Sx state, see section 7.5.2. For a detailed definition of the transitions between each of the Sx states, see section 9.1. Control starts from the processor's reset vector after the wake-up event. CPU, cache, and chip set context are lost in this state. Hardware maintains memory context and restores some CPU and L2 configuration context.
Control starts from the processor's reset vector after the wake-up event.
In order to reduce power to a minimum, it is assumed that the hardware platform has powered off all devices. Platform context is maintained. Software uses a different state value to distinguish between the S5 state and the S4 state to allow for initial boot operations within the BIOS to distinguish whether or not the boot is going to wake from a saved memory image.