We illustrate these contributions by providing a VHDL precompiler that will isolate the synthesizable portion of the design from the nonsynthesizable portion of the design and a post compiler that connects the synthesized design to the nonsynthesizable design elements in a schematic of the completed design. Once the design is simulated, the synthesizable VHDL may be synthesized and implemented as an FPGA or ASIC, and then a postprocessing tool provides a netlist of the complete design with the nonsynthesized components. A flowchart showing how the compiler is implemented is shown below. The boxes in the flowchart show what is happening as Store, Action, Output, and Function. Store indicates when the compiler is actively storing information in the symbol table.
Action indicates what specific actions are being taken at that stage of the compiler.
Output indicates where the compiler is storing its output for that section of the code. Function describes the overall purpose of that section of the code.