At the end of the course, one should expect to have a strong grasp of Digital Verification techniques for use in the EDA and VLSI design fields or in research. Most courses 4000-level and above can be credited to all degree programs.
All courses are subject to advisor approval.
VLSI design verification is a primary contributor to the productivity gap between the integration available due to advances in semiconductor technology and the integration achievable in the face of real-life constraints. Design verification is time intensive, dollar intensive, unpredictable and a show-stopper. At the end of the course, one should expect to have a strong enough grasp of these techniques for use in the field or in research. The course will involve the use of CAD tools for Verilog simulation, equivalence checking and property checking. The student can expect one or more programming projects in the course.