There are no restrictions on how vector instructions can be intermixed with branch, integer or floating-point instructions and there is no context switching, overhead or penalty for doing so. The AltiVec instruction set is general in nature, but optimized for digital signal processing algorithms. Vector instructions are RISC style, which are relatively simple in nature. Every vector instruction is carefully designed to be fully pipelineable. All vector instructions are architecturally consistent with the existing PowerPC scalar instructions but operate on fixed-length vector operands rather than scalar operands.
All instructions have one, two or three source operands and are non-destructive in nature.
The 128-bit wide vector operands consist of multiple, packed and scalar data elements. Loads and Stores. AltiVec loads and stores use indexed addressing with address operands coming from the general register file. All data operands are aligned to their natural size boundary and scalar data elements are transferred on their natural byte lanes. Misaligned data is handled explicitly with the data manipulation instructions.