The code in Example 1 uses a common, efficient Verilog coding style to implement the state diagram shown in Figure 2. This coding style is sometimes referred to as a two-always block coding style with continuous assignment outputs. The first always block in this example is used to generate the sequential state register, the second always block is used to generate the combinational next state logic, and the continuous assignments are used to generate the combinational output logic. The code in Example 2 is used to synthesize the same basic logic as Example 1, but the generation of the outputs is accomplished by moving the output equations into the same always block that is used to generate the combinational next state logic. This is a commonly used two-always block coding style.
Combinational outputs can glitch between states.
Combinational outputs consume part of the overall clock cycle that would have been available to the block of logic that is driven by the FSM outputs. When module outputs are generated using combinational logic, there is less time for the receiving module to pass signals through inputs and additional combinational logic before they must be clocked. 3.0 Partitioning For Synthesis A popular and proven technique for partitioning a design for synthesis is to partition the design so that all outputs are registered and all combinational logic is on the input-side of a module as shown in Figure 3. A variation on the same synthesis technique is to partition the design so that all combinational logic is on the inputs or between registered stages within the module as shown in Figure 4. The reason this technique is important is not that it necessarily makes a design any better, but that it greatly simplifies the task of constraining a design for synthesis.