Each of these operations can be performed independently of the others, except is not good form to attempt to write different data to the same address. There is no internal address arbitration. The address lines are latched on the falling edges of the clocks.
All timing is relative to the falling edge of the clocks.
The Write control input and the Data inputs are NOT latched, nor does the return to its precharge mode until the clock rises. Though these are published at Typical process parameters, the worst case speed can be estimated by scaling the typical cycle time by a factor that depends on voltage and temperature. The WRT control input is active high for a write cycle, and is deasserted low during a read. With WRT deasserted low, a read-cycle is initiated by a falling clock edge. The data inputs can then be set to their new values, and the WRT input asserted high simultaneously, to write the new data directly to the RAM in the same cycle.