The high speed, low power RAM is available in both single and dual port versions. The dual port RAM uses an 8-T memory cell design. Decoding is simple combinational logic.
Bitline differential is kept small in read mode, eliminating precharge delay.
Column select passgates provide a cascode gain stage, followed by a differential voltage sense amp. A fast ATD circuit turns on wordlines and sense amps only as they are needed, saving power while allowing asynchronous operation. Minimum write cycle time is no longer than access time. The memory array columns may be multiplexed to allow for a more optimal aspect ratio. No change in the total memory bit count occurs.