Once the CPU fills the pipeline, it completes one instruction on each cycle . Note that this is true even if there are complex addressing modes to be computed, memory operands to fetch, or other operations which use cycles on a non-pipelined processor. All you need to do is add more stages to the pipeline, and you can still effectively process each instruction in one clock cycle. 3.3.12.2 Stalls in a Pipeline Unfortunately, the scenario presented in the previous section is a little too simplistic. Both problems may increase the average execution time of the instructions in the pipeline.
Bus contention occurs whenever an instruction needs to access some item in memory.
For example, if a mov mem, reg instruction needs to store data in memory and a mov reg, mem instruction is reading data from memory, contention for the address and data bus may develop since the CPU will be trying to simultaneously fetch data and write data in memory. One simplistic way to handle bus contention is through a pipeline stall . The CPU, when faced with contention for the bus, gives priority to the instruction furthest along in the pipeline. This example is but one case of bus contention. There are many others.