Dr. Kathryn Fisler CS Faculty Candidate Computer-aided verification uses logic and formal modeling to locate errors in chips and protocols. Verification research looks for techniques to bridge this gap. Significant advances are likely to arise from detecting and exploiting structural information about designs.
Designers express systems using a wide array of notations, including several forms of diagrams.
Little work has explored the structure of these diagrams and their potential role in verification. This talk considers timing diagrams, a common design notation, as a data structure for verification. This perspective unveils several interesting properties of timing diagrams that have positive implications for enhancing verification technology. Our results not only suggest new avenues for verification research, but encourage further studies of diagrammatic notations as formal notations for computational problems. The talk assumes no background with either timing diagrams or verification.