Questions on Specific Cores I noticed you have a number of different variations of the C16550 device. Signals rd2, wr2, xin and xout have been eliminated from the interface. Reset requires at least one clock cycle. MSR register is reset during the clock cycle following a MSR read. Our C16550AS version of the core has no additional differences.
ADSn signal is removed.
Address and chip selects are not latched, but must be valid during write or read cycles. C2901 Microprocessor I'm running the C2901 through Altera Maxplus2 or Quartus. The C2901 is asynchronous and has combinational feedback. We recommend that you perform post route simulation to determine the performance of the routing. The testbenches we delivered with the core are parameterizable and can be used to assist with this.