This made a lot of the newer buses a lot messier. The data bandwidth on the bus refers to the amount of memory that can be passed on the data lines over a fixed amount of time. To increase the data bandwidth you can decrease the bus cycle time or increase the data bus width. The problem with speeding the bus up is something known as bus skew. Data traveling on different lines will go at slightly different speeds so the faster you try to push the data through, the more you will see the effects of bus skew.
Backward compatibility is another problems with speeding up the bus.
A multiplexed bus sends address signals and data signals on the same line. While this reduces the bus width it results in a slower system. Has a line driven by a crystal oscillator. Signal consists of a square sine wave with a frequency between 5 and 100 MHz. All bus activities take an integral number of these cycles, called bus cycles.