With a clock speed of 100 MHz, it runs at three-times the PCI bus frequency. Write merging, write buffering and instruction prefetching provide optimizations to enhance performance onto the internal bus. The bridge supports both posted and delayed writes. Once transactions are posted, they are completed. In addition, the bridge supports streaming, thereby allowing data to enter the bridge from one PCI bus while data is simultaneously written to the other bus.
Data can flow straight through the bridge without becoming packetized.
Another noteworthy enhancement is that dual 128-byte read queues allow the processor to support two simultaneous upstream read requests. The addition of a second 64 byte delayed memory read queue supports parallel reads, allowing partitioning. For example, two SCSI controllers can be programmed for concurrent reads. More important, the bridge provides high-throughput data paths to the processor core and local memory. There is a single inbound write queue, expanded to 128 bytes, in each ATU allowing up to four simultaneous write transactions without fully draining the queue.