This achieves the highest level of performance from a given process technology, but requires much more design effort and offers much less flexibility in porting to other processes. Cores in the Jade family will be available in both optimized and synthesizable versions, making them process-portable. The cores include integrated instruction and data caches. Most instructions are executed in a single cycle. Power consumption is minimized via fully static design, selectable core and bus-interface operating frequency, and two power modes.
Cost is minimized by small die size.
The Jade 32-bit MIPS processor core family includes R3000 execution units with enhanced R4000 functionality. A fully static design reduces power consumption and minimizes process sensitivity. The Jade family of cores provides key advantages of the popular R3000 and R4000 architectures with a large number of development and debug tools that provide flexibility and ease of implementation. The MIPS architecture has achieved a leadership position as the number one high performance embedded RISC processor. It leads the market in volume of units shipped, diversity of high-profile applications utilizing the MIPS architecture, and number of implementations and configurations from the many MIPS processor licensees.