Several EDA software vendors have boasted recently about the number of tapeouts design teams have achieved while using their software tools. Tapeouts are not an end unto themselves, but, rather a milestone on the way to the goal of working silicon. They can claim design wins through partial placement-they typically don't handle detailed routing or other necessary elements such as clock or power. To be fair, tapeout appears to mean different things to different people. A recent column in this publication quoted three people, each with a slightly different definition of tapeout.
Complex chips go through a long and rigorous design cycle.
Tapeout is one of many important steps along the way, but so is mask set generation. I believe the endless talk about tapeouts is misleading. Believing that the number of tapeouts is proof of the superiority of a new EDA tool is ludicrous. Chip-design teams are measured on their ability to deliver working silicon on schedule. Whether a particular EDA tool has taped out two designs or 20 is irrelevant-it is the ability of the tool to enable the team to meet their goal that counts.