Moreover, over time, the set of computed tasks varies. We propose to use reconfigurable logic blocks to make the architecture adaptive to the applications' computing and memory bandwidth needs. Specifically, the following architecture components would be reconfigurable. Dynamically programmable FUs and effective management of data and configuration flow. FUs reconfigurable as queues embedded in the register address space.
Caches reconfigurable as multi-function FUs.
Our objective is to use these novel ideas, reconfigurable FUs, cache memory, RMB, to achieve balanced computing. A computation is balanced if the computing bandwidth matches the memory bandwidth. We propose to use reconfigurable function units and caches to offer fast dynamic reconfiguration of the computing and memory bandwidth. The RMB will be used to dynamically meet the variable bus traffic demands. We also propose to modify the compiler and operating system to support an application to utilize the new features.