It is faster to compile the design for Functional Simulation, so you can find errors faster. Every internal node is available for examination during the simulation, since no logic is reduced or modified, so it may be easier to find the cause of problems. No timing problems are shown, so there is less to worry about at this point, so you can more easily find basic logic problems. So there are good reasons to do a Functional Simulation, but you have to eventually do a Timing Simulation to find any timing-related problems before actually program ming a real PLD and plugging it into your circuit board. Timing Simulation Simulate the operation from a timing perspective, using actual worst-case component propagation delays.
All devices operate with real propagation delays and real setup and hold times.
This will indicate any timing problems that may exist, as well as re-verify your Boolean equations and state machine sequencing. But Timing Simulation is slower to compile, some internal nodes are NOT available because they have been simplified, and there are more possible problems, making it harder to find simple logic mistakes. So you usually want to do a Functional Simulation first, to find most of the errors quickly, followed by a Timing Simulation to find more sinister timing problems. Make sure the current project is set to the design you want to simulate. If this is a Timing Simulation, select the type of PLD device to be simulated.