The Peak Detector tracks the input signal and maintains the highest previous positive level until a negative going zero crossing occurs. The pulse that produced the peak and zero crossing is monitored elsewhere in the experiment logic. Note that S1 must be available since there is significant probability a large signal will occur during the 1 millisecond and the peak detecting diode would again conduct. Once the data measurement is made, or at the end of the two microsecond delay in the absence of a measurement request, the six microsecond one-shot fires closing S2 and discharging the peak storage capacitor. The actual circuit allows any of the five D input lines to initiate the delay and reset cycle, each line having its own threshold discriminator.
Circuitry is described in detail later herein.
Their outputs drive multiplexers to each of two redundant analog to digital converters. Any failure in the remaining electronics would kill the system if it were not redundant. Therefore, no attempt is made for precise timing between the event and data output. Timing signals are internally generated to be compatible with the data section. The function described could not be implemented with commercial components available at the time of design.