M.H. Salinas, A.E. Szymkowiak, K.L. Wright, Wm.A. Wulf, and J.H. Aylor Submitted for publication, February 1996. Streamed Computations S.A. McKee Ph.D. thesis, School of Engineering and Applied Science, University of Virginia, May 1995. It will soon be revised to include results for version 2 of the chip. These graphs illustrate the measured performance of our prototype SMC system on several benchmark kernels on vectors of 16 to 8192 elements. The vectors used in each experiment are of equal length, and share no DRAM pages in common.
All vectors are unit stride, unless otherwise indicated.
Performance is given as a percentage of the peak system bandwidth exploited for each benchmark. The black lines indicate the performance of our access ordering hardware. Looking at it from a different perspective, the SMC brings the average cycles per memory access very close to the minimum one cycle for long-vector computations. In contrast, the average number of cycles per access when using the cache is more than three. In contrast, each cache-line fill incurs a DRAM page miss for the first word in the line, regardless of whether or not it is on the same DRAM page as the previously loaded cache line.