The Virtex-E family has more elements that are capable of higher performance. Any design in Virtex can be easily reused in Virtex-E devices with recompilation. Initially there will be a slight price premium over the Virtex family. However, price projections show the Virtex-E family at lower price per logic cell by mid 2000. Xilinx expects the Virtex-E family to be the main design vehicle of choice starting in 2000.
Clock synchronization is critical in high performance applications.
In ultra high performance applications, clock skew and clock to output delays can easily be more than 50 percent of the critical path. With Virtex-E DLLs these values can be reduced to nearly zero effectively doubling possible system frequency. The Virtex-E DLL does not accumulate jitter because each clock edge in essence restarts the circuitry. Further, the Virtex-E DLL has been proven to operate at frequencies over 311 MHz while competing PLL solutions in programmable logic devices either had questionable success or are limited to frequencies below 100 MHz. Unlike the PLL solution, the Virtex-E DLL also does not require external inductors, capacitors, or separate ground and power plane when implemented in a system design.