This provides additional opportunities for hardware and software optimization based on resynthesis and optimization of Place Chart nets. Those conditions roughly correspond to the requirement of a delay-insensitive interface between the models. We are planning to explore this topic at a subsequent meeting. Testing of asynchronous circuits Testing of asynchronous circuits has been a long term project between the groups in Torino and Aizu. Recently also the Universitat Politecnica de Catalunya has decided to entered this area of research.
Asynchronous circuits operate correctly only under timing assumptions.
Hence testing those circuits for delay faults is crucial. In the current work we tackle the problem of partial scan testing, that requires test pattern generation on a sequential circuit. As the result of our work we have submitted a paper to the International Workshop on Logic Synthesis. An abstract of the paper follows. Hence testing those circuits for delay faults is crucial.