The next sample point position is chosen with this distance value apart from the current sample point. An additional delay originates from the calculation of the next sample point address. Both delays force that the next sample point can be calculated only after more than 10 clock cycles. The top of Figure 2.1 illustrates the problem. This example assumes a delay of three clock cycles.
Dark squares indicate that the respective hardware stage is used at a certain clock cycle.
As can be seen due to the dependency of operations 1 and 3 the pipeline is used only every third clock cycle. Instead of inserting no-operations into the pipeline, sample points of other rays are calculated. This approach corresponds to a method in processors that is called multithreading. Thus there is enough time to calculate the next sample point position of a ray before this result is required. Figure 2.2 shows the new architecture.