IBM's 405xx chips support both big endian and little endian views of memory storage for the data types supported. The table below shows how the basic data types are stored in memory in both big and little endian modes. The CPU expects all instructions fed into the pipeline to be in big endian format. Byte swapping in the data path to or from memory provides for support of little endian data storage. The instruction interface also has byte steering logic to support instruction fetch from little endian memory.
All memory is viewed as big endian by default.
A memory region may be programmed as little endian via a memory attribute. Instruction Fetch considerations Instructions in memory can be in big or little endian format. In the I-cache, they are always stored in big endian format. The 405 CPU s internal instruction bus interface performs the byte swapping necessary when instructions are stored in little endian memory. Even though it is possible for PowerPC instructions to be stored in little endian memory space, there are no apparent advantages to doing so.