With the introduction of PrimeTime-SI, Synopsys is poised to establish the standard for signal integrity analysis within the design implementation flow. Looking forward, we expect that signal integrity analysis will drive the top-down implementation flow to proactively prevent and repair signal integrity problems. Crosstalk or capacitive coupling between lines can impact signal timing and, in some cases, actually cause logic errors. This is the same problem that impacted circuit-board design as trace widths and spacings were reduced. In addition, the capacitance between lines becomes an increasingly important part of the interconnect delay as the feature size drops below 0.18 micron.
Crosstalk is but one of several signal integrity effects.
Others include IR drops on the power rails, antenna effects, substrate-induced coupling, driver switching noise, and switching induced AC on the power supply lines. It is estimated that one in five chips fail because of signal integrity problems. Synopsys plans to cover some of these other signal integrity issues in future release of PrimeTime-IT . The company's milestone presentation shows an integration of the new tool with its physical synthesis products in an effort to achieve signal integrity closure in 0.15-micron designs. PrimeTime's integration into logical and physical design flows enables quick debugging of complex timing problems and speeds timing closure.