The implementation is optimized for lowest power consumption, especially in embedded systems. With the MIPS16 instruction set a compressed code can be generated. It also interfaces the CPU to the internal I-bus of the device. The ATM cell processor is based on a firmware preprogrammed 32-bit RISC controller. Full duplex operation is supported on both data rates.
Address filtering for unicast, multicast and broadcast is supported.
MIB counters for network management and a loopback function in the MII interface are also available. The ports communicate with the main CPU via individual DMA channels. Ethernet MAC-2 pins are shared with the TS interface. USB Interface An USB version 1.1 controller is integrated. It supports USB class functions compliant with the communication class definitions.