Functions, procedures and processes are the main elements. There is no regard to the structural realisation of the design. An explicit clock is used. RTL design contains exact timing possibility, operations are scheduled to occur at certain times. Within the logic level the characteristics of a system are described by logical links and their timing properties.
All signals are discrete signals.
Sometimes also packages are used and testbenches must be written to test models. An entity declaration in VHDL is a statement that defines the external specification of a circuit or sub-circuit. The actual operation of the circuit, however, is not included in the entity declaration. The entity declaration includes the name of the entity and a set of generic and port declarations. O. A port may correspond to a pin on a IC, an edge connector on a board, etc.