A message is sent to every CPU whose directory bit in that cache line is 1, telling the CPU to discard its copy because it is no longer valid. And the modifying CPU is noted in the directory as exclusive owner of that line. Any further requests for that cache line are rerouted to the owning CPU so it can supply the latest version. Eventually the owning CPU updates memory and dis- cards its cache line, and the status returns to the original situation. The purpose of the cache is to give the CPU extremely fast access to often-used data.
Cache access becomes a performance bottleneck only when cache lines are invalidated frequently.
Each invalidation causes overhead at each CPU that receives it. When any CPU next needs that data, the cache line has to be fetched again from main memory. When one CPU updates a line often, the CPUs that only read the line do so at memory speed, not cache speed. When a memory location is frequently updated by more than one CPU, the updating CPUs end up taking turns as exclusive owner of the cache line. This slows access to the line even further.