MIPS instruction sets are used frequently in the present routers and switches and people are familiar with it. For our first core, we built an 8-way multithreaded processor. Up to 8 threads can execute simultaneously. Each thread can issue up to four instructions in a clock cycle, for a total of 32 eligible instructions. From those 32, up to eight are issued.
Clustering simplifies the design with little impact on performance.
The design also includes a packet management unit that takes care of storing packets into memory and loading the pieces of the packets that require processing back into the processor. Get 'em while they're hot One indicator of the interest in network processors is the number of start-ups that have been bought up by larger communications companies. Last year Vitesse Semiconductor bought Sitera, the developer of the Prisma processor, and Broadcom agreed to acquire SiByte, a leading provider of highly integrated processors for the network market. The platform also includes software and development tools from third parties. They can mix and match their components.