Many tests remain to be conceived and written to exercise the DSP along with its peripherals inside the context of the design. Also, lower level tests to functionally verify the RTL and gate-level versions of the ASICs need to be developed. The engineer would be responsible for conceiving, writing and debugging verification tests, gate-level simulations, and continue to evolve the DV environment. Experience with DSP subsystems is highly desirable, but not necessary. Compensation is commensurate with experience.
Company offers excellent benefits.
However, most assignments will be in the above mentioned metropolitan areas. Company will sponsor.