However, numerous issues still exist in the design of very high-speed switches. Link speeds are now approaching, and exceeding, memory bandwidths complicating buffer designs. The trend of growth in link speeds exceeding increases in memory bandwidth is expected to continue. This includes traffic classes with guaranteed throughput and bounded delay requirements. Input buffered architectures are being used to deal with memory bandwidth bottlenecks.
Challenges remain in packet classification.
Multistage switching fabrics are being revisited. Network processors are opening new opportunities for supporting high-level capabilities including traffic management. In addition, standardization efforts for switch fabric interfaces are ongoing. Overall, this is an exciting time for switch developers and researchers. Tutorial and survey papers are also solicited.