Differences can also be output to a text file.
Configurable settings Compare wizard for fast set up and run Superior Debugging with Waveform Compare ModelSim, the world s most popular HDL simulator, is the simulator of choice for both ASIC and FPGA design. Its advanced debugging feature, Waveform Compare, further increases design verification throughput with a complete debugging environment for VHDL, Verilog, and mixed-language environments. The ModelSim Waveform Compare feature analyzes the results of two simulations to quickly identify design errors. Waveform Compare is completely configurable. Any number of signals or regions can be compared either continuously or relative to a signal edge.