Must control access to bus, to avoid chaos. Processor initiates and controls all bus usage. Scheme must allow some devices to have higher bus priority . Must also ensure fairness - guarantee that every device that wants to use the bus eventually gets it. High priority device that wants bus access simply intercepts the bus grant signal.
Advantage is simplicity.
Disadvantage is that it cannot assure fairness. A centralized arbiter decides and notifies selected device that it is bus master. Disadvantage is that central arbiter may become bottleneck. Used by PCI, standard backplane bus. Requires more lines for request signals.