These new test languages make it easier than ever to generate huge test suites. While more tests can be written faster, the simulation time needed to execute tests grows proportionally to the generated test suite size. This means that major breakthroughs in simulation performance are required to efficiently design the next generation of ICs. Software simulators offer convenient use models, relatively low cost and sophisticated debugging capabilities, but they are running out of steam for present and future generations of chip designs. Performance and capacity characteristics for large designs are their weakness because they depend upon the configuration of the workstation on which they are being run.
Capacity is limited by virtual memory size.
A Patented New Approach Design engineers frustrated with current verification solutions founded Tharas Systems. Software solutions run out of steam on large designs, no matter how generously a workstation was configured. The Tharas Systems founders saw this as an opportunity, and set out create a technology that would yield the blend of performance, capacity, ease of use, and cost that is needed for this and the coming generations of chip designs. The key problem that it has solved is that of integrating the interconnect and communication between a large number of specialized processors. Previous attempts have used bus architectures that suffer from resource conflict and algorithmically intractable scheduling problems.