Deliverables might include assertions to be verified, which might be derived from embedded checkers, and a definition of legal application interface input behavior, which might be derived from the application interface protocol monitor. In such a case, these deliverables might include stimulus test programs or a hardware abstraction layer library, which can be very useful in verifying the correct operation of the VC in the SOC as well as the interface to the rest of the system. The verification elements delivered along with the VC enable various forms of verification reuse by allowing the VC integrator to leverage the stand-alone VC functional verification effort. Indeed, experienced VC integrators often argue that design reuse isn't effective without companion verification reuse. In recognition of this importance, the VSIA Verification DWG is hard at work on the reference and deliverables documents described above.
Additional members are always welcome.
The more good ideas-the better the final result. Tom Anderson and Robin Bhagat are co-chairs of the VSIA Verification Development Working Group. Inc. Robin Bhagat is vice president, SOC technology at Palmchip Corp. Comments on our editorial are welcome. 2001 CMP Media Inc. All rights reserved.