Gate Width 50 nsec to 1500 nsec. In operation with wide gates, ADC conversion gain depends on pulse position in ADC gate time. Fast Clear May be executed any time. Requires 3 usec to settle. Test Feature Exercised by 2280 System Processor.
All channels have a test pulse applied.
Three output buffers on rear panel allow option for additional current summing. Special Options 15-bit operation and variable gain. Sensitivity should be selected to give a full scale of 1000 pC or less. 4 per module.