A Verilog cycle-based simulator. The first alternative Verilog simulator. The good old standard that started it all. A coverage-driven vector generator for RTL code. Historically popular for boards.
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A mention of a tool or EDA vendor on this page does not constitute an endorsement. Model-Checking Techniques and Tools. Basic rules to ensure high fault-coverage, simple scan insertion, and simple automatic test pattern generation. Real-life FPGA design, from specification to finished product. Goes beyond the language syntax.