The Verilog commands and the associated ModelSim Tcl commands and easy viewing of Verilog VCD files in our Waveform window are in the 5.5 release. The new compressed format is 10X smaller than non-compressed mode, and incurs no performance impact to compress. ModelSim 5.4, released in 2000, was the initial release of our global optimization Verilog technology. The new global view of the entire design enables a much broader scope of optimization. Differences between the test and reference signals are highlighted in red markers in the Wave window.
Differences can also be output to a text file.
Leveraging algorithms from the Verilog RTL global optimizations and many new cell algorithms, ModelSim 5.5 provides 2 4X faster Verilog gate-level performance over our 5.4 release. These ASIC library cell optimizations also yield an average 2X smaller memory footprint. Additional SDF annotation optimizations reduce annotation time by 2 5X and SDF memory footprint reduction of 4X versus version 5.4. This ensures access to ModelSim for any size design.