Architectural options for increasing the performance of these systems are to increase the clock frequency, to introduce concurrency through pipelined instruction and data paths, and to speed up memory access wtih multilevel cache. The RDPP takes a different approach, based on a synchronous pipeline model. In this model, multiple processing elements are connected in a network, and data and control information flow between them. Execution agility is achieved, not through conditional branching of execution, but though conditional switching of data paths. The example in Figure 2 below has three processing elements, separated by clocked registers.
Data flows from left to right.
PE2 and PE3 receive the same input data, but perform different computations on it. A conditional switch, indicated by the question mark, decides which one of the two is passed on downstream. Thus, this network makes decisions through conditional switching of data paths instead of conditional branching. The RDPP architecture, shown in Figure 3, consists of an array of configurable processing elements linked to each other, and to input and output buffers, through a flexible switching network. The evolution of a computation in the RDPP consists of setting up a pipeline, executing it until completion, then setting up a different pipeline with the same components, executing it, etc.