Any ensuing design changes from new information would thus cause time-consuming reiteration of the synthesis and place and route. The size and aspect ratio of blocks of logic determine the ASIC vendor library's estimated wireload models, which in turn depend on estimated capacitance per fanout. The actual interconnect characteristics of the block under design may thus differ from the wireload model used by the synthesis tool. Current procedures call for multiple repetitions of the synthesis and placement and routing until the physical design meets the timing specs. Such a process, however, is itself unstable because a potential fix for one timing violation can result in a violation in another path.
Designs can end up highly congested and impossible to route.
The solution to the timing convergence issue is to estimate the interconnect characteristics of the block under design and feed that information to the synthesis tool as early as possible in the design flow. Specifically, using floorplanning tools early on and setting up a dataflow between the floorplanning and synthesis tools can significantly reduce the number of necessary iterations. A timing-driven approach Several currently available methodologies improve the chances of timing convergence for large designs. Today's floorplanning tools generally require a gate-level netlist to estimate the size of the block, though initial versions of some recent tools work at the RT level. In either case the floorplanning tool can assign the pin locations, plan the location of megacells and memories, and determine the size and aspect ratio of groups of logic.