Coverage statistics now can be gathered for designs containing both Verilog and VHDL source. Previously, designs were limited to one language. Support for variable or signal coverage. Coverage statistics can now be gathered on individual signals, bits or ranges of signals, and concatenated signals. HDLScore lets designers know if the signal went through all permutations.
Designers can determine if a signal achieved all possible states in a functional simulation.
Supports Complete Process HDLScore supports the complete design verification process from behavioral to gate-level. With this tool, engineers have full control over when and where coverage statistics are gathered. Coverage can be selectively turned on and off at any time. The tool provides an accurate measure of the quality of the simulation tests applied to a design through fast, thorough code coverage analysis for the entire design. Inc. These unions form the foundation of Innoveda's comprehensive electronic product solutions for system level design, design capture, board design and electromechanical design.