It executes instructions out of order, and it does so more deftly than any other processor. HP's PA-8000 can handle 56. To make this possible, Digital implemented a clever register scheme. Like most RISC chips, the Alpha has an architectural set of 32 integer registers and 32 FP registers, all 64 bits wide. To enlarge the CPU's capacity for reordering instructions, the 21264 has 48 extra integer registers and 40 extra FP registers.
Any register can hold temporary values for pending instructions.
When an instruction is ready to retire, the CPU renames the register holding the temporary result so it represents one of the 32 integer or 32 FP registers that comprise the architecture definition. But the 21264 adds a unique twist. It has a duplicate set of 80 integer registers that are copies of the first 80 registers. In other words, there are really 160 integer registers on the chip. Consider that at 1 GHz, the cycle time will be only 1 nanosecond.