The two tools examined do generate eight faults from redundant logic. However, in the fault-coverage report, these eight faults are discounted by tool A and thus the fault coverage for Circuit 1 is measured at 100 percent. A defect in redundant logic may affect the design's expected behavior. The testability issue is hidden when 100 percent fault coverage is reported. If we know that there is an issue in testability because of redundant logic, then an additional DFT scheme should be considered, such as adding observable points.
All tools exclude tied faults in fault-coverage calculation in one way or the other.
Tied logic, just like any other logic, can go wrong in manufacturing. Excluding tied faults in fault-coverage calculation doesn't reflect silicon defect of tied logic and can yield false information about testability within a design. Additionally, fault coverage is calculated with a formula. Today, there aren't any two tools that use the same formula. Table 6 shows fault-coverage calculation formulas from three different tools.