Observations Note that pipeline scheduling increases the number of registers used. Compiler algorithms that perform this optimization can do so easily for code in basic blocks .
Basic blocks are code sequences with no branches.
If one instruction executes, they all do. Method is simple and effective for DLX with a latency for loads of 1 cycle. As latencies become longer, more aggressive strategies are needed. More on this later. Forwarding always works for R-R instructions, but only sometimes for loads.