Gated enable inputs are provided for controlling the entry of data into the flip-flops. Gate output control inputs are also provided. When both are low, the normal logic states of the four outputs are available for driving the loads or bus lines. The outputs are disabled independently from the level of the clock by a high logic level at either output control input. The outputs then present a high impedance and neither load nor drive the bus line.
Detailed operation is given in the function table.
To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output control circuitry is designed so that the average output disable times are shorter than the average output enable times. If you have trouble printing, see Printing Problems . Quick Search Parametric Search System Diagrams Product Tree Home About Languages . Website Guide .