The processor inter-connection network can be imagined using this picture as the wires that hold the PEs in place. Part of each PE is a Router chip that has 8 connections. 6 of the connections go to the next PE, to and from, in each of the X, Y and Z dimensions. The edge connections loop over to join with the PEs on the far side in each dimension passing through the aligned PEs in the partial plain if required. Each of the router connections can be downed to isolate faults within the machine.
Data can pass by a PE through the router chip with no cpu intervention.
The application PEs have been sub divided using labels in this system to perform different types of user work. Some of the high memory PEs have been used as OS pes and the rest reserved for high memory commands. Although the application pool has been subdivided all processors and PE share the same single system image. It does not matter where in the machine an application runs as it sees and has equal access to all operating system services provided by the single system image. This second picture also shows how cpu faults are handled.