Use ideal nets for any signals which will be distributed and repowered at the global level. Makefiles and lots of DC licenses facilitate the rapid parallelized creation of the gate-level netlist. Partition the gate-level netlist. The IBM physical guys prefer a flat netlist because of data management issues, but logic design like me prefer not to risk having 50K cell sub-designs spammed across the face of the die. My preferred floorplan tool is dry marker in a room filled with white boards.
Blue marker works best.
Front-end process the floorplan netlist using the vendor's toolset. Insert ideal clock trees, insert scan chains, etc. Static timing analysis allows rapid feedback of placement-based optimizations. Hierarchical netlist enables parallel work. I choose personally not to use PrimeTime because I sign off on timing closure with IBM's EinsTimer static timing analysis tool anyway.