We modelled 2 versions of the on chip cache structure. The modeling results have shown that the 2nd version gives better results on our code. It should be noted, if the technology allows, we will increase the size of L1 cache leaving the delay time of 2 clocks.
All simulators are consistent.
The most precise and consequently the slowest is Verilog RTL model. It operates with the speed of several wide instructions a second, that is why it can be used only for small engineering tests. The fastest is ISET simulator. It runs with the speed of 2 mln. In our architecture everything is implemeted such that, if multiprocessing has been taken into account specifically in OS, then it can be ensured.