All modules are custom designed to fit together for a compact layout with minimum interconnection delays. Figure 1 shows a typical layout of modules and buses for a comprehensive design using most module types. The block diagram in Figure 1 illustrates the architecture of the CD2450. This is an example system showing many of the possible configurations of the modules on-chip with possible external circuits. In this example the data precision is 16 bits with data buses are sized accordingly.
Address buses support the maximum address spaces.
The left-hand portion of the Figure is the irreducible internal core processor. Arrayed along the internal D bus are the Multiplier, ALU, Shifter, the eight Address Pointers, and the eight Data and Status Registers including the Program Counter. There is a corresponding some increase in the clock cycle from 20 ns as the precision is increased above 16 bits. Note the Accumulator Bus A, and Product Bus PT are 2N- bits precision. Pointers may be indexed and loop in arbitrarily sized buffers.