With an optimized Direct Compile architecture, ModelSim uniquely offers design and library portability with machine-independent object code. Direct Compile delivers up to 10X faster compile times than any other HDL simulator and simulation speeds that rank with the fastest in the industry. Designers can add company, project, or user-specific menus and buttons to ModelSim to create the most efficient simulation and debugging environment possible. Enabled by Single Kernel Simulation, a common intuitive interface is used to develop and debug in either language. One kernel executes VHDL and Verilog events in one event queue.
Designers can debug the design at any level, regardless of the language.
The same simulation controls, TCL-based scripting language, design browser, waveform viewer, and other debugging windows are available for both languages. The performance analyzer can help uncover inefficient code as well as more elusive performance sinks, such as non-accelerated library cells, unnecessary signals on sensitivity lists, unnecessary testbench code, and architectural bottlenecks. It works with both VHDL and Verilog, at the behavioral, RTL and gate levels. Designers can examine performance analyzer results then make modeling changes to dramatically decrease simulation run times. The coverage report indicates which lines of HDL code have been executed and which have not.