The technological advances needed to verify modern systems will likely arise from detecting and exploiting structural information about designs. Studying the notations in which designers express systems may reveal useful structural information for verification.
Designers use a wide array of notations, including several forms of diagrams.
Little work has explored the structure of these diagrams and their potential role in verification. This talk considers timing diagrams, a common design notation, as a data structure for verification. This perspective unveils several interesting properties of timing diagrams that have positive implications for enhancing verification technology. Our results suggest new avenues for verification research and encourage further studies of diagrammatic notations as formal notations for computational problems.