K x 18 synchronous-pipelined cache SRAM, respectively. They are designed to support zero wait state secondary cache with minimal glue logic.
All synchronous inputs pass through input registers controlled by the rising edge of the clock.
All data outputs pass through output registers controlled by the rising edge of the clock. The burst sequence is selected through the MODE pin. Address advancement through the burst sequence is controlled by the ADV input. Cypress Semiconductor Corporation. All rights reserved.