Both Verilog and VHDL were standards long before organizations were formed to promote them. Standards work best when they are based on existing installed technologies. In the early stages of technology development, chaos occurs when a number of solutions are tried and discarded, making the definition of a standard risky. The risk correlates to the number of possible winning approaches that lead warring entrepreneurial engineers to concede territory to exploit the core technology and not its supporting architecture. In short, it is too early to standardize.
Current examples are formal verification and behavioral synthesis language.
This stage is entered when innovation slows, so the number of possible choices and attendant risks are known. Synopsys was the only one that directly parsed Verilog, making it a drop-in solution for hundreds of Verilog users. Synopsys was destined to take the checkered flag even though its competitors may have had superior algorithms. Silc and SCS violated a marketplace rule by betting on the superiority of their algorithms without regard to a decision already made by the market. This is the same scenario for a submicron delay calculation solution.