For each chip design, HP carefully studies the available technologies and possible implementations, and then makes the right design trade-offs to achieve the desired cost and performance goals. With the arrival of a mature 0.5 micron technology, it became feasible to design a sufficiently large on-chip cache to provide balanced overall performance for systems in this price class. The 64 Kbyte Instruction and Data caches are each two-way set associative and virtually indexed. The Data cache uses a copyback store policy. Single and double word stores to the cache have been optimized to take a single cycle, eliminating any hangs to the pipeline on a D-cache hit.
All loads execute in a single cycle as well.
A two entry store queue is used to pipeline the stores into the D-cache. 3 on the instruction side, and two on the data side. Yields are kept high by using cache redundancy, which allows us to correct many of the processing defects which could occur in these blocks. There are several interesting features of this on-chip cache subsystem shown in the figure. Copy-in buffers separate each cache array from the memory controller.