3 on the instruction side, and two on the data side. Yields are kept high by using cache redundancy, which allows us to correct many of the processing defects which could occur in these blocks. There are several interesting features of this on-chip cache subsystem shown in the figure. Copy-in buffers separate each cache array from the memory controller. These buffers are filled as data becomes available from the memory controller, critical doubleword first.
Data can bypass from the copy-in buffers to the main instruction or data buses without penalty.
Once the copy-in buffer is filled, a burst mode transfer occurs, filling the cache array with a full eight word cache line in a single cycle. In the idle time between cache misses the copy in buffers are used as prefetch buffers. During prefetching, the I-cache buffer acts as a third way of associatively. Data cache prefetching is based upon compiler hints. With today's real world applications, we are seeing the need to perform well with larger code and dataset sizes.