In general, the less accurate the tester, the harder it is to tell whether the part tested can really run at speed. Until now, testers for most memory applications have been accurate enough to let you make credible judgements about device speed. The more mature the process gets, the tighter the distribution becomes. You then use the guardband to establish the edge-strobe placement. This graph plots yield improvement against tester accuracy at different DPM levels.
Actual yield approaches ideal yield as tester accuracy improves.
From the beginning of the design process, you as a test engineer must be in the loop, working closely with your peers in design, process, and product engineering. Information on device design, validation, and characterization must flow among all team members from the first day. All members must understand the effects of design and layout on accuracy as well as on the appearance of defect mechanisms. The test-head interface should provide tightly controlled impedances to DUT pins, with contact points minimized to reduce lumped and distributed capacitance. As production ramps up, you'll need a tester that maintains the requisite accuracies and speeds when a handler is docked to the test head.