As Digital ASIC Verification Engineer will be responsible for conversion of HDL code to ASICs. This will include scan insertion and ATPG, test bench development, verification, synthesis, and supervision of place and route. The successful candidate shall possess a BSEE and 2 years applicable experience along with familiarity with Verilog code and Verilog simulators such as NC Verilog, and synthesis tools such as Synopsys Design Compiler. Additional pluses would include prior experience with scan insertion and ATPG tools and place and route tools. Familiarity with coding signal processing algorithms or communications systems theory is also a plus.
Company offers excellent compensation, benefits, stock options and relocation package.
New sponsorship not available at this time. Please state job number when applying. . As Sr. ASIC Design Engineer, you will be responsible for ASIC architecture and implementation in high performance semiconductors plus perform synthesis, testing, timing analysis and FPGA for SOCs. You will also be responsible for system specification and architecture SOCs. A keen understanding of the use of UNIX, Linux, and Windows as part of design task, development of design methodology and task automation using Perl and TCL scripting languages and in-depth knowledge of ASIC development and tools required.