In many situations, only selection of the interconnect design parameters might not be enough to meet the design constrains in terms of global delay or transient time in on-chip signal nets. To meet the design requirements, designers should optimize their interconnect parameters. At early design stage, designers would like to estimate the driver size depending on the estimated interconnect load. Also they want to know delay or transient time for circuit which will be designed by them.
Designer have difficult time to optimize interconnect parameters for circuit performances.
InterCal can resuce time-consuming works and be used to select most possible interconnect path for signal nets or to generates delay estimation for given layout. All rights reserved. Terms of Use . Privacy Policy .