There will be one exam during the quarter covering the lecture and the lab material. A Xilinx FPGA will be used for each project, and some labs will require the use of additional discrete parts. All work must be finished by the Friday before finals. No Incompletes will be given. No non-working projects will be accepted.
Deductions are cumulative.
You may not turn in the report until you demonstrate a working project. Labs must be completed, even for 0 points to finish the course. Labs will be handed back as soon as possible after the deadline. All handouts will be available in lab after being distributed in class.