The input data is a byte, but the output CRC is 16 bits. This PLD is designed to let us multiplex the CRC onto the bus as two individual bytes. The input bits come from the same data bus. Typically these inputs are connected as input port selects. Your interface circuit must assert clock when preset is also low.
Clock is high-edge triggered.
Then transfer data one byte at a time. The PLD will compute a new value for the CRC and load it in the a0-a15 registers when clock goes high. After a block is transferred, the CRC can then be read by the computer. This is a pretty complex series of equations. One way is to compare the CRC to known good values after specific data is transferred.