The CY7C1327B is a 3.3V, 256K by 18 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic.
All synchronous inputs pass through input registers controlled by the rising edge of the clock.
All data outputs pass through output registers controlled by the rising edge of the clock. The burst sequence is selected through the MODE pin. Cypress Semiconductor Corporation. All rights reserved.