This statement could not be further from the truth. CynApps provides a library of macros that makes the language look very much like Verilog. Designers, familiar with Verilog, can learn to use the tool quickly.
Designers can have the best of two worlds.
The problem with remarks like the one above is that they strictly focus on the design effort. Today's ASIC design projects are bottlenecked by verification. The problem with Superlog is that it's a new language. Most designers know C today. No new langauge to learn.