Using the same design database eliminates the need to translate netlists or manage new libraries. This consistency and usability ensures accurate timing results from synthesis through final verification. Timing Verification Challenges Throughput of analysis with STA was very important to meet their schedule. Figure three illustrates an example of the script used in case analysis techniques. Sometimes a designer needs to restrict the paths and transitions considered in static timing for certain ports or pins.
Case analysis allows the user to analyze timing under certain conditions.
For instance, the user can set constant 1 or 0 values on specific pins or ports to analyze scan timing. By taking advantage of case analysis techniques in STA, it only took us a couple of hours. Achieving Timing Closure with PrimeTime PrimeTime was the main timing analyzer at the block and chip level. Timing closure was achieved in two layout runs. At the Design Compiler level, they synthesized the blocks with constraints coming from Design Budgeting.