My area is verification engineering. The increasing complexity of the chip makes it hard and verification is taking too much time. When you find a bug it's difficult to find where the bug is. A lot of times it's something that happened earlier in the process. So far all the one pass solutions I've seen are getting better but are not there yet.
Capacity is the biggest shortfall.
I like what Magma has done, they look good. We're not trying to pull more of the design process that we normally do at the back end up into the front end, but we are looking seriously at reducing or taking away dynamic regressions on the back end altogether, and going to a strictly formal verification and static timing signoff flow. You jump around from one machine to do synthesis to another machine to do simulation. We're continually looking for ways to bring things earlier into the phase so we don't take as much time. Iterative flows on the back end are what take time.