The goal of the ADK is to provide a complete design kit for use in teaching, research and even commercial use. It will support design entry in schematic, VHDL, Verilog or any combination of these. A synthesis library for Leonardo Spectrum will be provided for HDL synthesis, and digital models for the cells will be available in HDL and QuickPart forms. To make all this possible, a few rules must be followed in the physical cell design to assure that the cells are good . Power and ground rails will line up and there will be no DRC errors no matter what the order of cells in the layout.
Cells have uniform rules for placement and types of ports .
A port is an input or output of a cell. The significance of a port is that during routing, only ports may have wires between them. Cells should have relatively low delay. Transistor sizing and wiring capacitance. The former has been designed at the schematic level so during layout only the routing is of primary concern.