All inputs and outputs may be compatible with either TTL or CMOS logic levels and are fully protected from electrostatic discharge and latch-up. Extensive library support and other proprietary tools are available on most commercial platforms. These ratings define stress parameters under which useful product performance may be impaired. All CMOS circuits are susceptible to damage from stress voltages even when inputs are properly protected internally. TTL interface requires TTL operating voltages.
Capacitance is indicated for typical interface conditions.
Worst case will depend upon circuit configuration and package being used. Actual internal logic delays depend on a number of factors, including process parameters, supply voltage, temperature, fanout, and interconnect. The values shown are very conservative representations of circuit performance actually experienced across a broad range of applications. All rights reserved. Do not duplicate or redistribute in any form without prior consent.