Hui Zhang, of the Berkeley Wireless Research Center at the University of California at Berkeley, presented a paper on Maia, an ARM-based reconfigurable processor for wireless baseband applications. With 1-volt operation and the use of proprietary architectures in the reconfigurable portion of the die, the emphasis was on power efficiency. In his presentation on the Maia processor, Zhang, a member of a UCB team of coauthors led by professor Jan Rabaey, said the custom implementation of an ARM-8 core operates with multiple ALU and MAC and memory resources.
Allocation of resources is done automatically by a scheduler during the compilation process.
Aside from the ARM core, some 21 so-called satellite processing resources are embedded in the device. They provide building blocks for a reconfigurable datapath that can be altered to configure the hardware architecture to different dataflow requirements for executing data-intensive loops. The ARM-8 processor core supports the control and the reconfiguration while the repetitive and data intensive loops are mapped to the array of satellite resources by configuring their parameters and through interconnection. Built in a 0.25-micron CMOS technology by STMicroelectronics, the 1.2 million transistor design uses several techniques to keep power consumption low both in the FPGA and, particularly, in the reconfigurable interconnection network. Zhang said it was 70 times more energy efficient than equivalent commercial solutions.