The design is partitioned to determine the portions of the source code that are RTL versus behavioral code. The portion that is purely behavioral and non-synthesizable will be left untouched and simulated on the software platform. The IKOS RTL Compiler is easily integrated into the design process flow. The automatic compilation allows the designer to go straight to the NSIM hardware accelerator and run very fast RTL descriptions without going through a synthesis step. This problem is avoided by mapping directly to hardware accelerator primitives and maintaining both signal name integrity and design hierarchy.
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