In the most basic makefile, your goal is to define a target, tell make what, if anything, that target is dependent on, and how to build the target. The two required parts in the most basic makefile are a target line , which tells make what your target is and what it is dependent on, and a command line , which tells make how to reach the goal of your target. The first step is to define the target. A target line begins with the target wish you wish to build, followed by a space, a colon, another space, and a list of dependencies, or prerequisites, necessary to reach this target. The dependencies in the list are each separated by a space.
Dependencies can be either filenames, or other targets.
The command line immediately follows the target line. A command line consists of a tab followed by whatever shell command is needed to reach the target. This could be a call to a C compiler, or an instruction to remove files. The previous example showed the most basic makefile that one would want to use, for what is probably a fairly basic program. The problem with this is that you are not really taking advantage of what a makefile can do - you're still compiling every source file if just one of them is modified.