The simulation accurately modeled the interaction between the analog and digital blocks and allowed verification of circuit connectivity and signal path integrity. The models, through their dramatically increased design speeds, also permitted whole-chip simulation and verification against chip design specifications as well as architectural exploration of the digital and analog sections. This occurred at the functional level before transistor-level implementation. We typically modeled the digital portions at the behavioral level and the analog portions at the transistor level. But learning to write behavioral models is a one-time effort, and we feel the advantages for the CSP1088 chip demonstrate the value of learning this new technique.
Behavioral models offer tremendous potential reusability.
They can be used with minor variations to seed new designs, allowing the designer to evaluate them before implementation. The results were compared against the functional simulation results, verifying that the analog transistor-level implementation matched the functional design. Behavioral analog simulation was 150 times faster than transistor-level circuit simulation. With speed improvements of this nature, one month becomes an unacceptable delay. It is also impractical to check all the operational modes of the design in a circuit simulator.