The secret to maintaining signal integrity is applying a combination of better design tools and better design techniques. Also, at that size, ground bounce increases because of faster signal rise times and package parasitics. In any silicon design, resistance is caused by the interaction of the current-carrying electrons with the atoms and crystalline grains in the metal. Foundries are addressing that problem by changing the metallization, incorporating new metals that minimize resistance. Another factor affecting signal integrity in chip design is capacitance.
Capacitance is the result of the closeness of structures with independent voltages.
As silicon foundries move to five and six layers of metal, capacitance calculations become more complex. For example, for the metal cross section shown in Figure 3, a piece of metal on layer 4 may be completely shielded from the substrate by intervening wiring. Thus it's no longer sufficient to calculate capacitances to the substrate. Instead, capacitances are dominated by internodal effects, so the calculations have to be adjusted accordingly. None of those can be overlooked in calculating the capacitance on that electrical net.