ALL instructions are 16 bits in length. Shift immediates are restricted to 2 bits. All PC-Relative addresses are sign extended.
All addresses are word aligned.
PC is incremented by 2 after each instruction. SEQ Rd Rs1 Rs2 Set register Rd to 1 if the values in Rs1 and Rs2 are equal, else set to 0. ADD Rd Rs1 Rs2 Add registers Rs1 and Rs2 and store the result in Rd. SUB Rd Rs1 Rs2 Compute Rs1 - Rs2 and store the result in Rd. AND Rd Rs1 Rs2 Store in register Rd the bitwise AND of Rs1 and Rs2.