The robustness of functional, asynchronous interfaces removes the problems of clock skew and simplifies link arbitration and transfer synchronization. Each PE in the multiprocessor contains a local crystal and a clock generator that runs at its own clock speed. Processor speeds for communication between PEs are irrelevant due to the asynchronous interface. One PE in the HP prototype running at an internal clock speed of 16 MHz communicates perfectly well with another running at 64 MHz via the Post Office chips. The low power nature of asynchronous architectures was one further advantage demonstrated in the Post Office.
Asynchronous circuits contain fine grain, dynamic power management due to the handshake protocols.
Each idle Mayfly PE requires 30 amperes of current at 5 volts. By way of contrast, the Post Office, which is the only asynchronous part in the system, uses only 2 milliamps when idle. The complexity, low latency requirements, and inherent parallelism of the Post Office made the current asynchronous design styles impractical. Some MIC techniques overly restricted the arrival time of signals. My solution for implementing low latency state machines designed for parallel process forking and synchronization was to invent the burst-mode hazard model.