FPU pipeline is a hairy, ugly beast. Fault management often difficult because information is hidden from OS, such as address that caused fault. OS must interpret faulting instruction to deduce it. TLB management done by OS typically. TLB's without process ID tags must be purged on context switch, including context switches within kernel.
Architecture can impact user-level threads, most crucially on thread context switches.
Also, current window pointer is privileged, so pay kernel trap on every thread context switch. Assume procedure calls more frequent than context switches. Less true for parallel systems today that make heavy use of threads. Kernel-level threads cause decreased TLB effectiveness because of thread context switches in different address spaces. Atomic lock instructions are missing in some RISC IS, requiring either kernel trap or expensive synchronization algorithm.