Improving the performance of address translation Caching principles Very commonly used performance improvement principle. Keep recently accessed stuff around, so we can quickly access copy. More things in cache, larger hit ratio but more access time for hit. Translation Lookaside Buffers Caching can be applied to address translation. Recall that to resolve one virtual address, we needed 2-3 memory accesses.
Access times are small.
Can have hash collisions, so choice of hash function critical. To reduce collisions, can have set associative TLBs. Algorithms to replace, for the set associative case, later. Whenever MMU incurs cache miss, we trap to OS, so OS can fill in the translation. Demand Paged Virtual Memory So far, we have assumed that the result of a translation is always in physical memory.