The Source window provides a textual display of the design, while the Hierarchy window displays the design structure and all relationships between design blocks. The VStation-5M package includes the IKOS RTL compiler, condensing verification turnaround time with fast compiles at 50,000 gates per minute. The RTL compiler enables a direct mapping of the design written in RTL onto the FPGAs in the VStation without a separate time-consuming synthesis step. By passing synthesis allows the RTL compiler to maintain signal name integrity and design hierarchies. VStation's advanced RTL debugging capabilities include source code debug with active line and breakpointing, graphical path browser and waveform viewer all dynamically linked to maximize debug productivity.
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