From a competitive standpoint, each of the three new Warp packages offer much more flexibility and functionality at a lower cost than any other tool available. The Architecture Explorer and Timing Analyzer are new for Release 6.0, and were specifically engineered to allow designers to use Delta39K CPLDs more easily than FPGAs, even at high densities. The Architecture Explorer provides design implementation analysis through graphical representation. Designers can zoom in to the macrocell level and view the equations for every signal. The Timing Analyzer allows designers to evaluate critical performance parameters by quickly reviewing the timing parameters for different signals.
Designers then have the option to create specific sheets with user-defined timing parameters.
Designers can cross-probe between the Architecture Explorer and Timing Analyzer, using the architechture explorer to present a graphical view of paths highlighted in the Timing Analyzer. Using these tools, the numerical timing delays can be arranged and filtered in a variety of methods to explore asynchronous or synchronous paths within the design. Warp Professional and Enterprise products also provide additional, high-end Aldec tools, such as a graphical HDL block editor, automatic text HDL to graphical design translation, HDL source code debugging, and full behavioral and timing simulation with testbench support. Cypress's Warp R6.0 can be used as a standalone CPLD development system or seamlessly integrated with third-party EDA environments. Cypress CPLD devices are supported by third-party synthesis tools from Aldec, Cadence, Exemplar Logic, Innoveda, Mentor Graphics, Synopsys, Synplicity, and more.