Even that for many multimedia related tasks require more processor cycles that Pentium-III, faster clock in many cases compensates penalty. But because seems, that frequency disparity between Alpha and next generation x86 architecture will be narrower, it is more likely that additional multimedia acceleration will be required, to keep pace with rest of architectures. It should not negatively affect frequency, however. Packed multiply is one of urgent candidate for inclusion in instruction set. It is multi-cycle operation, which does not create critical path.
Different question is saturated arithmetic.
Micro-architecture From architecture point of view, can be applied many of techniques described for x86 architecture. For unleashing more parallelism, it is needed to reduce length of dependency chains and broke long instruction dependency chains. Immediate operand merging described for x86 architecture is very important. Using stack caching in registers as described in article about x86 can unleash more parallelism across subprogram call boundaries, by reducing store-load from critical path. Because instruction set architecture is lacking support for efficient Boolean expression trees high reduction, doing this type of transformation on the fly by hardware will be costly, but more that welcomed.