Model Sim simulator uses compiled HDL libraries. You must first compile all needed files into libraries for the top level netlist. The Altera ModelSim flow for each language is slightly different and is described below. Each language flow will be described with command line and User Interface examples. Links to the source files are listed below.
Batch mode is the typical method when running regression tests.
Interactive Command line mode is very similar to batch mode in the fact that the UI is not displayed, the only interface is a command line console. The UI can accept both command line, and menu input. The following commands can be used in any mode. In the above example the synthesizable RTL counter.vhd is VHDL, but could just as easly been Verilog. The RTL netlist will be input to your synthesis tools.