Solidify complements your existing synthesis design flow. No modifications in your HDL are needed to use Solidify. Either VHDL or Verilog can be used with Solidify. The coverage option to Solidify provides design coverage analysis to assure that all portions of a block have been verified for some behavior. If some portion of a block does not have a property covering its logic then Solidify reports it as uncovered and should be attended to by the designer.
Advanced algorithms eliminate false coverage problems seen in traditional code coverage tools.
Solidify's coverage analysis has no impact on verification times since it is a separate step. Incremental coverage analysis is supported so the designer saves time and effort since only those unverified portions of the circuit are analyzed. Say, there are 10 engineers in the company. They would probably get a factor of 2-3 speedup. The user can run Solidify on NT but ask it to send its compilation jobs to UNIX where the DC executable resides.