We will make use of the WDF software included in the DSPLab of Mentor Graphics to design these filters and optimize the coefficients. This greatly simplifies the multiplication operation that is the most area and power consuming operation in the filter. The QMF block uses crude instruction set architecture like mechanism. A control unit executes hardwired command subroutines for the filter calculations. The clocks necessary to synchronize and execute these routine are also generated from the master clock by this control unit.
All calculations use the same hardware components.
Each instruction takes one clock cycle to execute. The QMF bank is the most important block for both design and implementation. Fig.4 Shows the details of the filter bank in the analysis mode configuration. The figure also shows the number of bits used on the signal lines as well as the corresponding sampling rates. The four outputs are fed into four coding blocks which code the signals bits down to desired number of bits.