256K by 36 and 512K by 18 Synchronous-Pipelined Burst SRAMs, respectively.
All synchronous inputs pass through input registers controlled by the rising edge of the clock.
All data outputs pass through output registers controlled by the rising edge of the clock. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. Cypress Semiconductor Corporation. All rights reserved.