It also makes it harder to restart instructions. Allowing addressing modes with multiple memory accesses also complicates pipelining. Even if it's not in the pipeline, it could be in the instruction cache. IF First half of instruction fetch. PC selection occurs.
Cache access is initiated.
IS Second half of instruction fetch. This allows the cache access to take two cycles. RF Decode and register fetch, hazard checking, I-cache hit detection. The third cycle involves checking a tag check to determine if the cache access was a hit. WB Write back result for loads and R-R operations.