DOI: 10.57760/sciencedb.space.02189
title: A Novel Architecture for Addressing the Throughput Bottleneck in Spaceborne Solid-State Recorder for Electromagnetic Spectrum Sensors
title: A Novel Architecture for Addressing the Throughput Bottleneck in Spaceborne Solid-State Recorder for Electromagnetic Spectrum Sensors

description: The data acquisition rate of electromagnetic spectrum sensors is exceedingly high. However, the throughput of current high-speed spaceborne solid-state recorders (S-SSR) remains relatively low, making it difficult for the data to be fully stored. To address this issue, a novel architecture for a high-speed S-SSR is introduced in this study. The throughput of the S-SSR is primarily limited by three factors: the performance of the error-checking algorithm, the inability of a single FPGA to support the parallel expansion of too many Flash chips due to its limited effective I/O pins, and the efficiency of FLASH control. In the proposed architecture, a 10-stage pipelined RS(252,256) code is implemented. Data are distributed and stored in different memory regions controlled by separate FPGAs. Interleaved storage, multi-plane, and cache operation FLASH control module are also employed to resolve these bottlenecks. To further increase the throughput of the S-SSR, the system clock distribution has been optimized. In addition, interleaved encoding technology has been applied to improve radiation resistance and ensure data integrity. The performance of the system was evaluated on the Xilinx XC7K325T platform. The results confirm that the architecture is capable of handling high data rates and effectively correcting errors. The system can achieve a throughput of 46.8948 Gbps, making it suitable for future deployment in space exploration missions.
description: The data acquisition rate of electromagnetic spectrum sensors is exceedingly high. However, the throughput of current high-speed spaceborne solid-state recorders (S-SSR) remains relatively low, making it difficult for the data to be fully stored. To address this issue, a novel architecture for a high-speed S-SSR is introduced in this study. The throughput of the S-SSR is primarily limited by three factors: the performance of the error-checking algorithm, the inability of a single FPGA to support the parallel expansion of too many Flash chips due to its limited effective I/O pins, and the efficiency of FLASH control. In the proposed architecture, a 10-stage pipelined RS(252,256) code is implemented. Data are distributed and stored in different memory regions controlled by separate FPGAs. Interleaved storage, multi-plane, and cache operation FLASH control module are also employed to resolve these bottlenecks. To further increase the throughput of the S-SSR, the system clock distribution has been optimized. In addition, interleaved encoding technology has been applied to improve radiation resistance and ensure data integrity. The performance of the system was evaluated on the Xilinx XC7K325T platform. The results confirm that the architecture is capable of handling high data rates and effectively correcting errors. The system can achieve a throughput of 46.8948 Gbps, making it suitable for future deployment in space exploration missions.