DOI: 10.5281/zenodo.18305997
title: PCIe-Resident Artificial Intelligence (Public Architecture Draft)

description: PCIe-Resident Artificial Intelligence (Public Architecture Draft)

Persistent Execution Substrates for Offline-Capable and Governable AI Systems

Author: Mark Anthony BrewerDate: January 2026Status: Public Architecture Draft (Defensive Publication)

 



 

Abstract

Most contemporary AI systems assume a transient execution model in which models are loaded into volatile memory, executed within session-bound contexts, and continuously dependent on centralized infrastructure. This paper introduces PCIe-resident artificial intelligence as an alternative execution topology, in which model weights persist on high-bandwidth non-volatile storage (e.g., PCIe 5.0 NVMe), while CPUs and GPUs act as transient execution environments rather than owners of model state.

At current PCIe bandwidths, the traditional boundary between storage and memory becomes operationally porous. This enables AI systems that exhibit deterministic startup behavior, reduced data-movement overhead, offline-first operation, and hardware-anchored continuity. This paper presents the architectural rationale, performance characteristics, and governance implications of PCIe-resident AI, without proposing new hardware primitives or physical control systems.

 



 

1. Motivation: Limits of Transient AI Execution

Large-scale AI systems have achieved remarkable performance by centralizing compute and abstracting execution. However, this design introduces structural limitations in environments that require:





offline or degraded-network operation




predictable startup and response behavior




clear data custody and jurisdiction




inspectable execution lineage



These constraints are not edge cases; they define entire classes of real-world deployment where cloud-centric AI performs poorly or cannot operate at all.

 



 

2. The Cost of Data Movement

In modern systems, the dominant energy and latency cost of AI inference is often data movement, not arithmetic.

In a typical pipeline:





model weights are read from storage,




copied into system memory,




transferred across interconnects,




and finally staged into accelerator memory.



Each transfer consumes orders of magnitude more energy than the computation itself. As model sizes grow, this overhead becomes a first-order constraint.

 



 

3. PCIe as a Threshold Technology

PCIe 5.0 NVMe devices deliver sustained throughput sufficient to support fine-grained, memory-mapped access patterns. At this threshold:





full model preloading becomes optional,




cold-start latency is dramatically reduced,




non-volatile storage can serve as a persistent execution substrate.



This does not eliminate CPUs or GPUs; it reorders their role in the hierarchy.

 



 

4. Architecture: Persistent Model Substrates

In a PCIe-resident architecture:





model weights persist on non-volatile storage,




system RAM functions primarily as cache and scratch space,




accelerators are optional performance enhancers, not prerequisites,




the model’s identity and state continuity are anchored to hardware presence.



Execution adapts to locality rather than copying entire models into volatile memory.

 



 

5. Offline-First Operation

Because model state is local by default, PCIe-resident AI operates naturally in offline or intermittently connected environments.

Offline operation is not a degraded mode; it is the baseline.Network access, when available, becomes an optional augmentation rather than a dependency.

This characteristic is essential for deployments where connectivity cannot be assumed.

 



 

6. Governance and Auditability

When AI execution is physically local:





data custody is explicit,




jurisdiction is unambiguous,




shutdown is enforceable by disconnection,




audit does not require third-party cooperation.



Governance shifts from policy overlays to architectural properties.

 



 

7. Performance Characteristics

PCIe-resident AI does not aim to outperform high-end accelerators in peak throughput. Instead, it offers:





near-elimination of cold-start latency,




reduced memory pressure,




improved energy efficiency for batch-1 inference,




graceful degradation across heterogeneous hardware.



These characteristics favor reliability and predictability over raw scale.

 



 

8. Relationship to Centralized AI

PCIe-resident AI is not a replacement for centralized systems. The two are complementary:





centralized AI excels at large-scale training and aggregation,




resident AI excels at local reasoning, continuity, and reliability.



Together, they form a layered ecosystem rather than a competitive dichotomy.

 



 

9. Scope and Limitations

This paper intentionally limits itself to information-space architecture.

It does not address:





physical actuation,




real-time control systems,




robotics or vehicles,




enforcement hardware, or




military or surveillance applications.



These domains require separate governance frameworks and are outside the scope of this publication.

 



 

10. Conclusion

PCIe-resident artificial intelligence represents a reordering of the AI execution stack rather than an incremental optimization. By anchoring model state to high-bandwidth non-volatile storage, it enables AI systems that are offline-capable, auditable, and locally governable by design.

As AI continues to move from abstract services into real-world infrastructure, architectures that prioritize locality, continuity, and explicit boundaries will be essential. PCIe-resident AI offers one such path.

 



 

End of Public-Safe Draft