DOI: 10.25549/usctheses-c127-654132
title: Techniques for design and synthesis of approximate digital circuits for error-tolerant applications

description: As VLSI technology node scales to nano-scale, dramatic improvements in most attributes of circuits, especially delay and yield, provided by scaling are beginning to decrease. One of the main reasons for this trend is the increase in non-idealities, such as increasing defect rates and increasing variations due to the manufacturing process. The concept of error tolerance has been proposed earlier to mitigate the effect of the non-idealities. Main concept of error tolerance is that for a wide variety of applications including audio, video, graphics, and wireless communications, defective chips that produce erroneous values at its outputs can be acceptable, provided the errors are of certain types and their severities are within application-specified thresholds. Previous research on error tolerance focused on identifying such defective but acceptable chips during post-fabrication testing to improve yield. ❧ This Ph.D. dissertation proposes, a new approach to exploit error tolerance based on the following observation: If certain deviations from the nominal output values are acceptable, then we can exploit this flexibility during circuit design or synthesis to reduce circuit's area, delay, and power and as a consequence to increase yield. In this thesis, we introduce approximate design technique for several different scenarios of original implementation of the circuit as well as different cost metrics to be improved. Original circuit and error tolerance threshold is assumed to be given for developing approximate design methodology. In the application level analysis, we show the existence of error tolerance in the application level with the defined error tolerance metrics as well as the relationship between error tolerance metric and traditional quality metric of information. Then, we introduce approximate circuit design methodology for error tolerance applications in gate level implementation of original circuit. Two different techniques have been proposed that is to simplify circuit using forward and backward removal by injecting stuck-at faults and substitute sub-function of the circuit with another sub-function in the circuit. Approximate design methodology for Boolean function (typically in the form of a truth table) level also has been explored. Main idea is to expand original cubes by complementing minterms in original function. The expansion of original cubes can be considered as area decrease in circuit implemented by the function. To select good candidate minterms in the circuit, we deterministically prune the candidate minterms that cannot reduce area when complemented. Finally, we explore the case when the objective is to improve parametric yield of the circuit in gate level implementation of generic combinational circuit. To improve parametric yield, we not only focus on reducing critical delay but reducing number of critical and near-critical paths. Critical delay and number of critical and near-critical path reduction reduces probability of the circuit to have delay greater than required delay. Experiment results show us significant amount of improvement in area, delay, and yield with approximate design that is produced by our new design methodology.