DOI: 10.5281/zenodo.18494460
title: UTH FPGA Telemetry Dataset for ML Inference Experiments on AMD/Xilinx ZCU102 MPSoC Development Board

description: 📌 Overview

This dataset contains telemetry traces from repeated machine learning inference experiments executed on a Xilinx ZCU102 FPGA platform.Each experiment corresponds to a specific DPU bitstream configuration (DPU size and number of DPU compute units), a model variant (including pruning variants), and a system workload mode applied on the ARM CPU.

The dataset is intended to support research on:



FPGA-based ML inference performance,

DPU scaling and configuration trade-offs,

interaction between FPGA accelerators and ARM CPU workloads,

power, memory bandwidth, and system-level telemetry analysis.


Each experiment produces a time-series telemetry trace recorded during a batch inference run.

📂 Dataset Structure

The dataset is organized into two main components:





experiments.csv — index fileOne row per experiment run, describing its configuration.




data/<experiment_id>.csv — telemetry traceTime-series telemetry recorded during the corresponding experiment.



🗂️ experiments.csv — Index File

experiments.csv is the entry point to the dataset.Each row describes one complete experiment run on the FPGA.

Format

Experiment ID,DPU CU#,DPU Size,Model,Workload Mode

Index Columns




Column
Description




Experiment ID
Unique identifier for the experiment run. Used to locate the trace at data/<experiment_id>.csv.


DPU CU#
Number of DPU compute units (parallel inference threads).


DPU Size
DPU configuration size. The dataset includes 8 sizes and 26 total configurations when combined with CU counts.


Model
Model executed during the experiment. Pruning variants are encoded in the name (e.g., resnet18-25 for 25% pruning).


Workload Mode
Background workload on the ARM CPU: None, C-H (compute-bound), or M-H (memory-bound).




🧪 Experiments Overview




Aspect
Description




Hardware platform
Xilinx ZCU102 MPSoC Development Board


DPU configurations
26 total (8 DPU sizes × multiple CU counts)


Models
12 models with pruning variants (-25, -50, or none)


Run duration
From seconds up to ~10 minutes


Execution mode
Batch inference




Each row in experiments.csv corresponds to one full experiment run on the development board.

📈 Telemetry Traces — data/<experiment_id>.csv

Each telemetry file contains a time series of system and inference measurements recorded during the experiment.

Time Columns




Column
Description




timestamp
Unix timestamp (seconds, fractional) when the telemetry row was recorded.


timestamp_human
Human-readable timestamp of the same moment.




These represent the actual time at which telemetry was sampled.

Per-Thread Performance Columns (*_K)

Many columns are indexed by K, representing per-DPU compute unit (per inference thread) measurements.K ranges from 1 to DPU CU#.




Column Pattern
Description




preprocessing_time_K
Preprocessing latency for inference thread K.


inference_time_K
Inference latency for thread K.


postprocessing_time_K
Postprocessing latency for thread K.


job_id_K
Identifier of the inference job executed on thread K.


fps_K
Frames-per-second observed for thread K.




Memory Bandwidth Telemetry (ZCU102 Ports)




Column
Description




S0_read … S4_read
Read bandwidth for memory ports 0–4.


S0_write … S4_write
Write bandwidth for memory ports 0–4.




Power Telemetry




Column
Description




arm_power
Instantaneous power consumption of the ARM CPU subsystem.


fpga_power
Instantaneous power consumption of the FPGA fabric.




CPU Utilization (ARM Cortex-A53)




Column
Description




cpu_0, cpu_1, cpu_2, cpu_3
Utilization of the four ARM Cortex-A53 cores.




Memory Metrics




Column
Description




memory_available
Available system memory at sampling time.


memory_total
Total system memory.


swap_free
Free swap space.




Experiment Linkage




Column
Description




experiment_id
Experiment identifier matching the filename and the index in experiments.csv.




🚀 How to Use the Dataset



Select an experiment from experiments.csv based on:



DPU configuration (DPU Size, DPU CU#)

model variant (Model)

workload mode (Workload Mode)



Open the corresponding telemetry trace:



data/<experiment_id>.csv



Analyze:



inference latency breakdown (pre / infer / post),

per-thread throughput (fps_K),

memory bandwidth usage (S*_read, S*_write),

CPU utilization and power behavior under different workloads.




🎯 Intended Use

This dataset is intended for:



FPGA performance analysis,

ML inference benchmarking,

system-level telemetry studies,

research on accelerator–CPU interaction.


It represents a controlled experimental environment, not a production deployment.

🤝 Acknowledgements & Funding

This work is part of the MLSysOps project and is funded by the European Union’s Horizon Europe research and innovation programme under grant agreement No. 101092912.

More information: https://mlsysops.eu/