DOI: 10.5061/dryad.wpzgmsbws
title: Low-voltage short-channel MoS2 memtransistors with high gate-tunability

description: Neuromorphic hardware promises to revolutionize information technology
 with brain-inspired parallel processing, in-memory computing, and
 energy-efficient implementation of artificial intelligence and machine
 learning. In particular, two-dimensional (2D) memtransistors enable
 gate-tunable non-volatile memory, bio-realistic synaptic phenomena, and
 atomically thin scaling. However, previously reported 2D memtransistors
 have not achieved low operating voltages without compromising
 gate-tunability. Here, we overcome this limitation by demonstrating
 MoS2 memtransistors with short channel
 lengths &lt; 400 nm, low operating
 voltages &lt; 1 V, and high field-effect switching
 ratios &gt; 104 while concurrently achieving strong
 memristive responses. This functionality is realized by fabricating
 back-gated memtransistors using highly polycrystalline monolayer
 MoS2 channels on high-κ Al2O3 dielectric layers. Finite-element
 simulations confirm enhanced electrostatic modulation near the channel
 contacts, which reduces operating voltages without compromising memristive
 or field-effect switching. Overall, this work demonstrates a pathway for
 reducing the size and power consumption of 2D memtransistors as is
 required for ultrahigh-density integration.
description: <strong>CVD MoS<sub>2</sub> Sample
 Preparation</strong> Continuous polycrystalline
 films of monolayer MoS<sub>2</sub> were synthesized  by
 chemical vapor deposition (CVD) using sulfur powder (Millipore-Sigma,
 99.98%) and molybdenum trioxide powder (MoO3, 99.98% trace metal,
 Sigma-Aldrich) following previously a reported method [20]. Growth
 substrates were c-plane sapphire substrates cleaned by ultra-sonication
 with acetone and isopropyl alcohol.
 <strong>Fabrication of MoS<sub>2</sub>
 Memtransistors</strong>
 MoS<sub>2</sub> films were transferred to
 pre-patterned gate electrodes on Si substrates through a wet transfer
 process [20]. Memtransistor devices were patterned by an electron beam
 lithography (Raith Voyager 100) process using a PMMA mask followed by
 metal evaporation (Denton Vacuum Explorer 14) and lift-off in acetone. Dry
 etching (Samco RIE-10NR) was used to descum and etch
 MoS<sub>2</sub> to define the channel regions [18]. ALD of
 Al<sub>2</sub>O<sub>3</sub> gate dielectric was
 deposited at 100°C using trimethylaluminum precursor (Cambridge Nanotech
 ALD S100). <strong>Material
 Characterization</strong> CVD films were
 screened for coverage and monolayer growth quality using optical
 microscopy, Raman spectroscopy, and photoluminescence spectroscopy (XploRA
 PLUS). Raman and photoluminescence measurements used a 532 nm laser with
 1800 gr/mm under 100X objective. Lateral force microscopy (LFM)
 measurements were performed under contact mode atomic force microscopy
 (Asylum Cypher AFM) characterize the film quality and quantify grain size
 distribution. Soft and thin LFM tips (NanoAndMore PPP-LFMR) were used of
 dimension 48 µm × 225 µm, ≈ 0.2 N/m force constant, and ≈ 23 kHz resonant
 frequency. Grain statistics were calculated by measuring flake lateral
 size using Gwyddion and plotted in Origin.
 <strong>Electrical Measurements</strong>
 Electrical measurements were conducted in a vacuum probe station
 (pressure ≈ 5 x 10<sup>-5 </sup>Torr) at room-temperature
 using LakeShore CRX 4K probe station. Voltage sweep, endurance, retention,
 and pulse tests were measured using a Keithley 4200A-SCS Parametere
 Analyser and homebuilt LabVIEW programs.
 <strong>COMSOL Finite-Element
 Simulations</strong> A finite-element method is
 employed to quantify the relationship between charge distribution and
 potential by solving the Poisson equation, ∇²Φ = -ρ/ε, which calculates
 the potential at various points within the device. Φ signifies the
 potential, ρ represents the charge density, and ε is the dielectric
 constant. In contrast to other software packages, COMSOL Multiphysics®
 software streamlines the modelling workflow by automatically computing the
 Schottky barrier height after defining the work function and metal
 contact-related boundary conditions specified in Table S1 of the
 Supporting Information document. The Schottky barrier height
 Φ<sub>𝐵</sub><sub>, </sub>is calculated as
 Φ<sub>𝐵</sub> = Φ<sub>M</sub> −𝜒, where
 Φ<sub>𝑀</sub> is the metal contact work function (Au) and 𝜒 is
 electron affinity (MoS<sub>2</sub>). Subsequent calculations
 assumed the device adheres to a drift-diffusion model without quantum
 effects to allow model classical charge carrier transport under the
 contacts and inside the channel.
description: # Low-voltage short-channel MoS2 memtransistors with high gate-tunability
 [https://doi.org/10.5061/dryad.wpzgmsbws](https://doi.org/10.5061/dryad.wpzgmsbws) Data were visualized and organized via Microsoft Excel and OriginLab software. Open-access, unformatted text files are attached here for Dryad compatibility. Dataset was collected via Raman/photoluminescence and custom electrical characterization methods, in addition to finite-element modelling via COMSOL. The dataset describes the following, separated by text file name: * Raman: chemical fingerprint of underlying MoS2 film, confirming polycrystalline, monolayer character * Flake_distribution: provides distribution of randomly selected flakes in MoS2 film in units of um * Output_IV_curves: electrical output curves (varying drain voltage Vd) at various gate voltages Vg; na = not applicable * Endurance_curves: repeating cycles of electrical output curves at set gate voltage Vg * Endurance_curves_by_cycle: repeating cycles of electrical output curves at set gate voltage Vg separated by cycle * Retention_by_cycle: memory behavior once programmed with write and read voltages Vd at low and high states of resistance * Vary_gate_pulse_Vg: gating effect of pulsing drain bias Vd for set number of write pulses * Number_of_pulses: pulse number dependency achieves varying levels of resistance states and ON/OFF ratios; na = not applicable * Band_diagram: COMSOL simulations of device performance under electrical bias; na = not applicable * Number_of_carriers_dependence: COMSOL simulations of device performance of free carrier dependence under electrical bias; na = not applicable * Potential_v_dependence: COMSOL simulations of device performance of potential dependence under electrical bias; na = not applicable * Electric_field_Ex_dependence: COMSOL simulations of device performance of electrical field under electrical bias * Photoluminescence: optical behavior of underlying MoS2 confirming good monolayer, optoelectronic performance * Device_variation_in_log_ONOFF: variation among fabricated devices in ONOFF metric * Current_voltage_transfer_curve: electrical output curves (varying gate voltage Vg) for Vd biases