Predictive Electro and Thermal Quantum Transport in Nanoscale Devices
Creators: name: Chu, Yuanchen
Publisher: name: Purdue University Graduate School
Year: 2019
Subjects: Electrical engineering not elsewhere classified

description: Modern semiconductor devices have reached the sub-20nm regime. Before long, it will be practically impossible to further scale down the size of Si-based MOSFETs due to short channel effects. Novel device geometries (e.g. tri-gate and gate-all-around), device concepts (e.g. TFET and NCFET) and channel materials (e.g. III-Vs and TMDs) have been proposed to achieve lower power dissipation and faster speed, allowing for higher transistor density on a chip. In the past decade, quantum transport methods (e.g. NEGF) have become the standard approaches for modeling such nanoscale devices.<br>In state-of-the-art quantum transport models, the dielectric constant is typically set to the material's constant, neglecting the spatial variation of the screening effects in the nanodevice structure. When applied to TFETs, hybrid states that enable band-to-band tunneling are subject to interpolation that yields model dependent charge contributions. In this work, it is exemplified that the use of different charge interpretation models brings large variability when applied to ultra-thin body transistor performance predictions. To solve these modeling challenges, an electron-only band structure model is extended to atomistic quantum transport. Performance predictions of MOSFETs and TFETs confirm the generality of the new model and its independence of additional screening models.<br>Secondly, as devices become smaller, their thermal resistances increase because of the reduced area under the device and thinner silicon layer in the horizontal direction. Thus, despite lower power per device, self-heating effects in digital circuits are actually increasing which compromise both the performance and the reliability of the device. Therefore, for future electronics, an increasingly important role of energy dissipation necessitates electro-thermal co-design. As a first step, seeking to include anharmonicity in phonon related NEGF, the NEGF method with Büttiker probe scattering self-energies is proposed and its accuracy is assessed by comparing its predictions for the thermal boundary resistance with molecular dynamics (MD) simulations. For simplicity, the interface of Si/heavy-Si is considered. With Büttiker probe scattering parameters tuned against MD in homogeneous Si, the NEGF-predicted thermal boundary resistance quantitatively agrees with MD for wide mass ratios, proving that the proposed method provides an efficient and reliable way to include anharmonicity in phonon related NEGF. An algorithm to couple the electron and phonon transport in the NEGF formalism via Büttiker probes is also proposed.<br>Thirdly, NEGF with self-consistent Born approximation is introduced for modeling band tail and bandgap narrowing driven by LO phonons and charged impurities in III-V semiconductors. Extracted scattering rates are benchmarked against Fermi’s golden rule. Urbach tail and band gap narrowing calculated in bulk III-V materials agree well with experimental results for a range of temperature and doping concentration. Predictions are made for band-tail and bandgap narrowing in confined structures. <br>Next, the performance of 5nm gate length GaN nMOS nanowire field effect transistor (GaN-NW-nFET) of various geometrical shapes is investigated, around the limits of cross-sectional scalability, using atomistic quantum transport simulations. Benchmarking results with simulated Si-NW-nFET reveal large enhancement in GaN drive current in both Low Standby Power (LP) and High Performance (HP) applications. Further performance enhancement is observed with the use of non-square geometries that are akin to GaN's wurtzite crystal structure. Particularly, it is found that triangular cross-section GaN-NW-nFETs exhibit the smallest subthreshold swing, excellent drive current and superior energy-delay product compared to simulated Si-NW-nFET.<br>Furthermore, quantum transport simulation is applied to design of complementary van der Waal TFETs based on the monolayer p-WTe<sub>2</sub>/n-ZrS<sub>2</sub> vertical heterojunction. Non-idealities such as electron-phonon and electron-electron interactions are included via a phenomenological scattering model. Through band structure engineering and design of the electrostatics, both n- and p-type TFETs are realized with the same device configuration.Transfer and output characteristics, suitable for VLSI applications, are observed. 3D views of energy resolved local density of states (LDOS) illustrate device operating principles and identify three different tunneling paths in the device. It is found that in order to improve the electron collection at drain (source) of the n-type (p-type) TFET, efforts are needed to seek alternative material combinations with similar values of LDOS in the conduction and the valence band of the n- and the p-type materials, respectively. Circuit level simulation of the designed n- and the p-type TFETs is performed on a 25-stage ring oscillator which demonstrates the promise of the proposed designs for low-power digital VLSI applications.<br>Lastly, a finite element Landau-Khalatnikov equation solver is implemented in NEMO5, as a preparation to enable NCFET modeling.