title: Ð ÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ñ Ð¼Ð¾Ð´ÑÐ»Ñ ÐºÐ¾Ð³ÐµÑÐµÐ½ÑÐ½Ð¾Ð³Ð¾ ÑÐ»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÑÐ¸Ð³Ð½Ð°Ð»Ð¾Ð² Ð² FPGA
title: Ð²ÑÐ¿ÑÑÐºÐ½Ð°Ñ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð±Ð°ÐºÐ°Ð»Ð°Ð²ÑÐ°
titleType: Subtitle
title: Implementation of the coherent signal addition module in FPGA
Creators: name: Ð¦Ð¸ÑÐ°Ð¸ÑÐ²Ð¸Ð»Ð¸, Ð ÑÑÐ»Ð°Ð½
Publisher: name: Ð¡Ð°Ð½ÐºÑ-ÐÐµÑÐµÑÐ±ÑÑÐ³ÑÐºÐ¸Ð¹ Ð¿Ð¾Ð»Ð¸ÑÐµÑÐ½Ð¸ÑÐµÑÐºÐ¸Ð¹ ÑÐ½Ð¸Ð²ÐµÑÑÐ¸ÑÐµÑ ÐÐµÑÑÐ° ÐÐµÐ»Ð¸ÐºÐ¾Ð³Ð¾
Year: 2020
Subjects: Ð¿Ð»Ð¸Ñ
ÑÐ°Ð·Ð½ÐµÑÐµÐ½Ð½ÑÐ¹ Ð¿ÑÐ¸ÐµÐ¼
Ð°Ð´Ð°Ð¿ÑÐ¸Ð²Ð½ÑÐ¹ ÑÐ¸Ð»ÑÑÑ
Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼ LMS
ÐºÐ¾Ð³ÐµÑÐµÐ½ÑÐ½Ð¾Ðµ ÑÐ»Ð¾Ð¶ÐµÐ½Ð¸Ðµ
ÑÑÐ°Ð½ÑÐ¿Ð¾Ð½Ð¸ÑÐ¾Ð²Ð°Ð½Ð½Ð°Ñ Ð°ÑÑ Ð¸ÑÐµÐºÑÑÑÐ°
fpga
diversity receive
adaptive filter
LMS algorithm
coherent addition
transposed architecture

description: ÐÐ°Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð¿Ð¾ÑÐ²ÑÑÐµÐ½Ð° ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ð¸ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð° Ð°Ð´Ð°Ð¿ÑÐ¸Ð²Ð½Ð¾Ð¹ Ð¾Ð±ÑÐ°Ð±Ð¾ÑÐºÐ¸ ÑÐ¸Ð³Ð½Ð°Ð»Ð¾Ð² Ð¿ÑÐ¸Ð¼ÐµÐ½Ð¸ÑÐµÐ»ÑÐ½Ð¾ Ðº ÑÐ¸ÑÑÐµÐ¼Ð°Ð¼ ÑÐ°Ð·Ð½ÐµÑÐµÐ½Ð½Ð¾Ð³Ð¾ Ð¿ÑÐ¸ÐµÐ¼Ð° Ð´Ð»Ñ ÐºÐ¾Ð³ÐµÑÐµÐ½ÑÐ½Ð¾Ð³Ð¾ ÑÐ»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÑÐ¸Ð³Ð½Ð°Ð»Ð¾Ð². ÐÑÐ½Ð¾Ð²Ð½Ð°Ñ Ð¸Ð´ÐµÑ â ÑÐ²ÐµÐ»Ð¸ÑÐ¸ÑÑ Ð¾ÑÐ½Ð¾ÑÐµÐ½Ð¸Ðµ ÑÐ¸Ð³Ð½Ð°Ð»-ÑÑÐ¼ Ð² ÑÐ¸ÑÑÐµÐ¼Ðµ ÑÐ´Ð²Ð¾ÐµÐ½Ð½Ð¾Ð³Ð¾ Ð¿ÑÐ¸ÐµÐ¼Ð°. ÐÐ°Ð´Ð°ÑÐ¸, ÐºÐ¾ÑÐ¾ÑÑÐµ ÑÐµÑÐ°Ð»Ð¸ÑÑ Ð² Ð¿ÑÐ¾ÑÐµÑÑÐµ Ð¸ÑÑÐ»ÐµÐ´Ð¾Ð²Ð°Ð½Ð¸Ñ:
1. Ð Ð°Ð·ÑÐ°Ð±Ð¾ÑÐºÐ° Ð°ÑÑÐ¸ÑÐµÐºÑÑÑÑ Ð¼Ð¾Ð´ÑÐ»Ñ ÐºÐ¾Ð³ÐµÑÐµÐ½ÑÐ½Ð¾Ð³Ð¾ ÑÐ»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÑÐ¸Ð³Ð½Ð°Ð»Ð¾Ð² Ð½Ð° Ð¾ÑÐ½Ð¾Ð²Ðµ Ð°Ð´Ð°Ð¿ÑÐ¸Ð²Ð½Ð¾Ð³Ð¾ ÑÐ¸Ð»ÑÑÑÐ°;
2. ÐÐ½Ð°Ð»Ð¸Ð· ÑÑÑÐµÐºÑÐ¸Ð²Ð½Ð¾ÑÑÐ¸ Ð¼Ð¾Ð´ÑÐ»Ñ ÐºÐ¾Ð³ÐµÑÐµÐ½ÑÐ½Ð¾Ð³Ð¾ ÑÐ»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÑÐ¸Ð³Ð½Ð°Ð»Ð¾Ð²;
3. Ð ÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ñ Ð¼Ð¾Ð´ÑÐ»Ñ ÐºÐ¾Ð³ÐµÑÐµÐ½ÑÐ½Ð¾Ð³Ð¾ ÑÐ»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÑÐ¸Ð³Ð½Ð°Ð»Ð¾Ð² Ð² FPGA.
Ð ÑÐ¾Ð´Ðµ ÑÐ°Ð±Ð¾ÑÑ Ð² ÑÑÐµÐ´Ðµ Simulink Ð±ÑÐ»Ð° ÑÐ¾Ð·Ð´Ð°Ð½Ð° Ð¼Ð¾Ð´ÐµÐ»Ñ ÑÑÑÑÐ¾Ð¹ÑÑÐ²Ð° Ð½Ð° Ð¾ÑÐ½Ð¾Ð²Ðµ Ð°Ð´Ð°Ð¿ÑÐ¸Ð²Ð½Ð¾Ð³Ð¾ ÑÐ¸Ð»ÑÑÑÐ°. ÐÑÑÐ¸ÑÐµÐºÑÑÑÐ° ÑÐ¸Ð»ÑÑÑÐ° â ÑÑÐ°Ð½ÑÐ¿Ð¾Ð½Ð¸ÑÐ¾Ð²Ð°Ð½Ð½Ð°Ñ ÑÐ²ÐµÑÐ½ÑÑÐ°Ñ, Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼ Ð°Ð´Ð°Ð¿ÑÐ°ÑÐ¸Ð¸ â LMS. ÐÑÐ¾Ð²ÐµÐ´ÐµÐ½Ð¾ Ð¸Ð¼Ð¸ÑÐ°ÑÐ¸Ð¾Ð½Ð½Ð¾Ðµ Ð¼Ð¾Ð´ÐµÐ»Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ðµ Ð´Ð»Ñ ÑÐ°Ð·Ð»Ð¸ÑÐ½ÑÑ Ð¿Ð°ÑÐ°Ð¼ÐµÑÑÐ¾Ð² Ð¿ÑÐ¸Ð½Ð¸Ð¼Ð°ÐµÐ¼ÑÑ ÑÐ¸Ð³Ð½Ð°Ð»Ð¾Ð², ÑÐµÐ°Ð»Ð¸Ð·Ð¾Ð²Ð°Ð½ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼ ÑÐ°Ð±Ð¾ÑÑ Ð¼Ð¾Ð´ÐµÐ»Ð¸ Ð½Ð° VHDL, Ð¸ Ð¿ÑÐ¾Ð²ÐµÐ´ÐµÐ½Ð° ÐºÐ¾ÑÐ¸Ð¼ÑÐ»ÑÑÐ¸Ñ ÑÑÑÑÐ¾Ð¹ÑÑÐ²Ð° Ñ Ð¿Ð¾Ð¼Ð¾ÑÑÑ ModelSim.
description: This work is devoted to the implementation of adaptive signal processing algorithm as applied to diversity receive systems for coherent signal addition. The main idea is to increase signal-to-noise ratio in a dual reception system. Tasks that were solved in the research process:
1. Development of the architecture of the module for coherent signal addition based on an adaptive filter;
2. Analysis of the efficiency of the coherent signal addition module;
3. Implementation of the coherent signal addition module in FPGA.
In the course of the work in Simulink environment, a device model based on an adaptive filter was created. The filter architecture is transposed folded, the adaptation algorithm is LMS. Simulation for various parameters of the received signals was carried out, the algorithm of the model on VHDL was implemented, and the device was cosimulated using ModelSim.