title: Ð Ð°Ð·ÑÐ°Ð±Ð¾ÑÐºÐ° Ð¸ Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ðµ soft-Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ° Ð´Ð»Ñ Ð¼Ð¾Ð´ÑÐ»Ñ ÑÐ¿ÑÐ°Ð²Ð»ÐµÐ½Ð¸Ñ
title: Ð²ÑÐ¿ÑÑÐºÐ½Ð°Ñ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð±Ð°ÐºÐ°Ð»Ð°Ð²ÑÐ°
titleType: Subtitle
title: Development and programming of a soft-processor for the control module
Creators: name: ÐÑÑÐµÐ½ÐºÐ¾, ÐÐ°Ð»ÐµÑÐ¸Ñ
Publisher: name: Ð¡Ð°Ð½ÐºÑ-ÐÐµÑÐµÑÐ±ÑÑÐ³ÑÐºÐ¸Ð¹ Ð¿Ð¾Ð»Ð¸ÑÐµÑÐ½Ð¸ÑÐµÑÐºÐ¸Ð¹ ÑÐ½Ð¸Ð²ÐµÑÑÐ¸ÑÐµÑ ÐÐµÑÑÐ° ÐÐµÐ»Ð¸ÐºÐ¾Ð³Ð¾
Year: 2022
Subjects: soft-Ð¿ÑÐ¾ÑÐµÑÑÐ¾Ñ
ÐÐÐÐ¡
MSP430
SPr430
IAR Embedded Workbench
soft-processor
FPGA

description: Ð¢ÐµÐ¼Ð° Ð²ÑÐ¿ÑÑÐºÐ½Ð¾Ð¹ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð¾Ð¹ ÑÐ°Ð±Ð¾ÑÑ: Â«Ð Ð°Ð·ÑÐ°Ð±Ð¾ÑÐºÐ° Ð¸ Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ðµ soft-Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ° Ð´Ð»Ñ Ð¼Ð¾Ð´ÑÐ»Ñ ÑÐ¿ÑÐ°Ð²Ð»ÐµÐ½Ð¸ÑÂ».ÐÐ°Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð¿Ð¾ÑÐ²ÑÑÐµÐ½Ð° ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐºÐµ soft-Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ°, ÑÐ°Ð·Ð¼ÐµÑÐ°ÐµÐ¼Ð¾Ð³Ð¾ Ð½Ð° ÐÐÐÐ¡, Ð´Ð»Ñ Ð·Ð°Ð¼ÐµÐ½Ñ ÑÑÑÐ°ÑÐµÐ²ÑÐ¸Ñ Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ½ÑÑ ÑÐ¸Ð¿Ð¾Ð² Ð¸ ÑÐ¼ÐµÐ½ÑÑÐµÐ½Ð¸Ñ Ð½Ð¾Ð¼ÐµÐ½ÐºÐ»Ð°ÑÑÑÑ ÑÐ»ÐµÐºÑÑÐ¾Ð½Ð½ÑÑ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½ÑÐ¾Ð² Ð² Ð¼Ð¾Ð´ÑÐ»Ðµ ÑÐ¿ÑÐ°Ð²Ð»ÐµÐ½Ð¸Ñ ÐÐ-1000Ð.Soft-Ð¿ÑÐ¾ÑÐµÑÑÐ¾Ñ Ñ ÑÐ°Ð±Ð¾ÑÐ¸Ð¼ Ð½Ð°Ð·Ð²Ð°Ð½Ð¸ÐµÐ¼ SPr430 ÑÐ¾Ð·Ð´Ð°Ð½ Ð½Ð° Ð¾ÑÐ½Ð¾Ð²Ðµ Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ° ÑÐ¸ÑÐ¼Ñ TI ÑÐµÐ¼ÐµÐ¹ÑÑÐ²Ð° MSP430ÑÑ, Ð¸Ð¼ÐµÑÑÐµÐ³Ð¾ Ð±Ð»Ð¸Ð·ÐºÐ¸Ðµ ÑÐ°ÑÐ°ÐºÑÐµÑÐ¸ÑÑÐ¸ÐºÐ¸ Ðº Ð·Ð°Ð¼ÐµÐ½ÑÐµÐ¼Ð¾Ð¼Ñ Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÑ ADSP-2185N.Ð ÐºÐ°ÑÐµÑÑÐ²Ðµ ÑÑÐµÐ´Ñ ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐºÐ¸ Ð¸ Ð¾ÑÐ»Ð°Ð´ÐºÐ¸ Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼ Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ° Ð¿ÑÐµÐ´Ð»Ð¾Ð¶ÐµÐ½Ð° ÑÑÐµÐ´Ð° IAR Embedded Workbench, ÐºÐ¾ÑÐ¾ÑÐ°Ñ Ð¿Ð¾Ð·Ð²Ð¾Ð»ÑÐµÑ ÑÐ¾Ð·Ð´Ð°Ð²Ð°ÑÑ Ð¸ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ð¸ÑÐ¾Ð²Ð°ÑÑ Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ñ, Ð° ÑÐ°ÐºÐ¶Ðµ Ð²ÑÐ¿Ð¾Ð»Ð½ÑÑÑ Ð¸Ñ ÑÐ¸Ð¼ÑÐ»ÑÑÐ¸Ñ.Ð Ð°Ð·ÑÐ°Ð±Ð¾ÑÐ°Ð½Ð° ÑÐ°Ð±Ð¾ÑÐ°Ñ Ð²ÐµÑÑÐ¸Ñ Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ° Ñ ÑÑÐµÑÐµÐ½Ð½ÑÐ¼ Ð½Ð°Ð±Ð¾ÑÐ¾Ð¼ ÐºÐ¾Ð¼Ð°Ð½Ð´ Ð¸ ÑÐµÐ¶Ð¸Ð¼Ð¾Ð² Ð°Ð´ÑÐµÑÐ°ÑÐ¸Ð¸ Ð² ÑÑÐµÐ´Ðµ Quartus Ð´Ð»Ñ ÐÐÐÐ¡ ÑÐ¸ÑÐ¼Ñ INTEL. ÐÐ»Ñ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ð¸ Ð¸ÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°Ð»ÑÑ ÑÐ·ÑÐº SystemVerilog. Ð¢ÐµÑÑÐ¸ÑÐ¾Ð²Ð°Ð½Ð¸Ðµ Ð²ÑÐ¿Ð¾Ð»Ð½ÑÐ»Ð¾ÑÑ Ð½Ð° ÑÑÐ¾Ð²Ð½Ðµ ÐºÐ¾Ð´Ð¾Ð² ÐºÐ¾Ð¼Ð°Ð½Ð´ Ð¸ Ñ Ð¿Ð¾Ð¼Ð¾ÑÑÑ Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼ Ð½Ð° ÑÐ·ÑÐºÐµ Ð°ÑÑÐµÐ¼Ð±Ð»ÐµÑ.ÐÑÐµÐ´Ð»Ð¾Ð¶ÐµÐ½Ñ ÑÐ¿Ð¾ÑÐ¾Ð±Ñ Ð²Ð·Ð°Ð¸Ð¼Ð¾Ð´ÐµÐ¹ÑÑÐ²Ð¸Ñ Ð¼ÐµÐ¶Ð´Ñ ÑÑÐµÐ´Ð¾Ð¹ ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐºÐ¸ Ð¸ soft-Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ¾Ð¼.ÐÑÐ°ÐºÑÐ¸ÑÐµÑÐºÐ¸Ðµ ÑÐµÐ·ÑÐ»ÑÑÐ°ÑÑ ÑÐ°Ð±Ð¾ÑÑ Ð¼Ð¾Ð³ÑÑ Ð±ÑÑÑ Ð¸Ð½ÑÐµÑÐµÑÐ½Ñ ÑÐ¸ÑÐ¼Ð°Ð¼, ÐºÐ¾ÑÐ¾ÑÑÐµ ÑÑÑÐµÐ¼ÑÑÑÑ Ðº ÑÐ¼ÐµÐ½ÑÑÐµÐ½Ð¸Ñ Ð½Ð¾Ð¼ÐµÐ½ÐºÐ»Ð°ÑÑÑÑ Ð¸ ÑÐ¸Ð¿Ð¾Ð² Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ¾Ð² Ð¸ ÐºÐ¾Ð½ÑÑÐ¾Ð»Ð»ÐµÑÐ¾Ð² Ð² Ð¸Ñ Ð¸Ð·Ð´ÐµÐ»Ð¸ÑÑ, Ñ Ð²Ð¾Ð·Ð¼Ð¾Ð¶Ð½Ð¾ÑÑÑÑ ÑÐµÑÐµÐ½Ð¸Ñ Ð·Ð°Ð´Ð°Ñ Ð¸Ð¼Ð¿Ð¾ÑÑÐ¾Ð·Ð°Ð¼ÐµÑÐµÐ½Ð¸Ñ.
description: The subject of the graduate qualification work is Â«Development and programming of a soft-processor for the control moduleÂ».This work is devoted to the development of a soft-processor located on the FPGA to replace outdated processor chips and reduce the range of electronic components in the ÐÐ-1000Ð control module.The soft-processor with the working name SPr430 is based on the MSP430xx family processor from TI, which has similar characteristics to the replaced ADSP-2185N processor.As an environment for developing and debugging processor programs, the IAR Embedded Workbench environment is proposed, which allows you to create and compile programs, as well as perform their simulation.A working version of the processor with a reduced set of instructions and addressing modes in the Quartus environment for INTEL FPGAs has been developed. For implementation, the SystemVerilog language was used. Testing was performed at the level of instruction codes and using assembly language programs.Methods of interaction between the development environment and the soft-processor are proposed.The practical results of the work may be of interest to companies that seek to reduce the range and types of processors and controllers in their products, with the possibility of solving import substitution problems.