title: Statistical Analysis and Predictive Modelling of Random Telegraph Noise in Nanometre Devices for Low Power Applications
Creators: name: Tok, KH
Publisher: name: Liverpool John Moores University
Year: 2024

description: As the Internet of Things is becoming the new normal in electronics, one of the core issues is low power consumption. The direct solution is to reduce the operation voltage towards the threshold voltage of Metal Oxide Silicon Field Effect Transistors (MOSFETs); however, this reduces noise toleration. The focus of this research is Random Telegraph Noise (RTN), which is one of the dominant noises in MOSFETs. It is well known that the impacts of RTN are inversely proportional to the size of the transistors. As the size of the transistor goes down, the impact of RTN increases and this affects the performance of circuits, such as causing jitters. RTN is a stochastic and step-like fluctuation of drain or gate current of a device under given voltages. It occurs when an electron/hole is captured or emitted from or into a trap in the oxide layer. RTN has received attention widely, but understanding of it is incomplete, and its modelling remains a challenge. At present, there is no trustworthy RTN model of acceptable accuracy for circuit designers to use to optimize the performance of their circuits. One of the key weaknesses of early models is that they were developed based on test data gained from a short time window and their ability to predict future long-term RTN was not verified. The aim of this work is to develop a statistical model that can be used to predict the long-term impact of RTN on the device. 
To develop RTN models, early works followed a bottom-up approach by extracting the properties of individual traps, including RTN amplitude per trap, capture and emission times. This requires selecting devices where the fluctuation can be clearly separated into the contributions of individual traps. In reality, however, there are many devices where such separation cannot be achieved. Excluding these devices when developing RTN models makes it questionable whether the data used for developing the model represents the statistical properties of real devices. Also, this is time consuming and does not provide direct information for circuit designers to evaluate their circuit stability. The needed direct information includes shifts in threshold voltage, ΔVth, and in drain current, ΔI_D/I_D. An open question is: what is the probability that RTN can cause ΔVth in mV or ΔI_D/I_D in % to go beyond a certain level? A top-down modelling approach is proposed and used in this work. This approach does not select devices and extracts the cumulative distribution function (CDF) of RTN by measuring the impacts of all traps and integrating data from multiple devices into one dataset. This new approach will be referred to hereafter as the integral approach. RTN has been widely characterized under a fixed voltage (DC); for example, in this project, Vg=0.5V and 0.9V have been applied as the gate voltage. The integral approach removes the burden of determining capture and emission time constants of individual traps by introducing the concept of ‘Effectively Charged Traps’ (ECT). A time-dependent number of ECTs is introduced to replace the time constant distribution and the kinetics of ECT against time are extracted, which can be extrapolated to predict the long-term RTN. The predictive ability of the integral approach is verified.
Rather than DC RTN, the majority of commercial circuits operate under AC conditions. It has been reported that AC RTN behaves differently from DC RTN. Early work has been carried out for AC RTN on characterizing the single trap properties, such as time constants and amplitude under different frequencies. In this work, the integral approach has been applied to analyse and model AC RTN. It is shown that the model developed by the integral approach can also be used to predict future RTN. The relationship is assessed between capture, emission time constants of a single trap and the number of ECTs against frequency. A 6T SRAM circuit in read operation requires transistors to operate in either a linear or a saturation region. Early works have worked on saturation measurement but knowledge in the area is limited: no CDF information has been provided. To optimize circuit performance, RTN under saturation conditions must be measured, analysed, and modelled. Furthermore, both driving current and threshold voltage shift are needed in real circuit operation. Without them, the simulation of RTN for real circuit operation cannot be completed. RTN measurement under saturation is carried out and analysed by using the integral approach. ΔVth and ΔI_D/I_D have been found to follow different statistical distributions. In summary, to optimize circuit performance and yield against RTN, designers need to know the probability of the RTN-induced ΔVth and ΔI_D/I_D reaching a certain level within a specific time window. This work tackles this challenge by developing an integral approach to extract an RTN model which can not only model short-term RTN, but also predict future RTN. It is hoped that the new model can eventually be embedded into an industrial standard simulator for circuit optimization.