Reconfigurable nanowires for thermo-electric applications
Creators: name: Hamid, Ali
Publisher: name: Imperial College London
Year: 2020

description: Nano-structuration of bulk into nanowires and nanosheets has led to massive changes in device behaviour and to opportunities for designing novel devices that exploit these changes. The combination of these two consequences of nanoscale devices in integrated circuits will lead to further enhancements in their performance in the future. In this project, different novel device structures have been designed and their performance investigated using Sentaurus Technology Computer Aided Design (TCAD) software. Sentaurus TCAD is a commercial software package that is used in the semiconductor industry to predict the behaviour of nanoscale devices. Its transport models have been tuned and calibrated over at least the last decade to give realistic performance parameters of novel device structures. One current trend in semiconductor device technology that we have embraced in this work is the replacement of n+/p (p+/n) junctions as contacts to the external world by metal/semiconductor Schottky contacts. This resolves the k_BT/q limitation of diffusive processes leading to better device performance parameters. In this work, doping has been avoided in order to maximise the mobility of the carriers and minimise the challenges with doping control in nanostructures. Carrier modulation techniques have been implemented to control the thermal and electrical conductivities of the novel devices designed in this work. This project focused on two areas of research. One is the solution of the traditional a-symmetric current-voltage characteristics of the p- and n-FET in CMOS. A novel reconfigurable double gate nanowire structure with oxide bridges that controls the symmetry of operation of the p- and n-FET in CMOS was designed. Not only can the approach be integrated in CMOS technology, it is also relatively tolerant to small geometrical deviations. The challenge in this design lies in the oxide bridge perpendicular to the gate length direction. Nano-structuration of Si also leads to a reduction of the thermal conductivity. Although this is a problem for nanowire and nanosheet FETs due to increased self-heating, it also leads to opportunities offered for on-chip thermo-electric power generation, TEG (or thermoelectric cooling (TEC)) and temperature sensors. We propose a carrier modulation technique based on the work function difference between the gate metal and the intrinsic NW - a technique similar to a nanoFET process and thus compatible with CMOS technology - that shows an increase in the TEG’s performance. Another application where thermo-electrics can be used is in on-chip temperature sensing. Currently on-chip temperature sensors suffer from high power consumption and high real estate on the chip. We use a gated reconfigurable Si nanowire FET as temperature sensor that in principle works on the same supply rail as the circuits and is sufficiently small to be placed close to where hotspots will occur. The gate voltage that needs to be applied to keep the current constant as a function of temperature difference is a measure of heating. Due to the weak electrical conductivity of the nanowire, an efficient temperature difference can be maintained between the hotspot and the surrounding thermal mass minimising the need for re-callibration.