title: ÐÐ¿Ð¿Ð°ÑÐ°ÑÐ½Ð°Ñ Ð°ÑÑ Ð¸ÑÐµÐºÑÑÑÐ° Ð±Ð»Ð¾ÐºÐ° Ð¿Ð¾Ð¼ÐµÑ Ð¾ÑÑÑÐ¾Ð¹ÑÐ¸Ð²Ð¾Ð³Ð¾ ÐºÐ¾Ð´Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ ÑÑÐ°Ð½Ð´Ð°ÑÑÐ¾Ð² DVB-S2/S2X Ð¸ ÐµÐµ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ñ Ð² FPGA
title: Ð²ÑÐ¿ÑÑÐºÐ½Ð°Ñ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð¼Ð°Ð³Ð¸ÑÑÑÐ°
titleType: Subtitle
title: Hardware architecture of the error-correcting coding block of DVB-S2/S2X standards and its implementation in FPGA
Creators: name: ÐÐ°Ð·Ð°ÑÐµÐ½ÐºÐ¾, ÐÐ»ÐµÐºÑÐµÐ¹
Publisher: name: Ð¡Ð°Ð½ÐºÑ-ÐÐµÑÐµÑÐ±ÑÑÐ³ÑÐºÐ¸Ð¹ Ð¿Ð¾Ð»Ð¸ÑÐµÑÐ½Ð¸ÑÐµÑÐºÐ¸Ð¹ ÑÐ½Ð¸Ð²ÐµÑÑÐ¸ÑÐµÑ ÐÐµÑÑÐ° ÐÐµÐ»Ð¸ÐºÐ¾Ð³Ð¾
Year: 2022
Subjects: ÐÐ¾Ð´Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ðµ Ð¿Ð¾Ð¼ÐµÑ Ð¾ÑÑÑÐ¾Ð¹ÑÐ¸Ð²Ð¾Ðµ

description: Ð¢ÐµÐ¼Ð° Ð²ÑÐ¿ÑÑÐºÐ½Ð¾Ð¹ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð¾Ð¹ ÑÐ°Ð±Ð¾ÑÑ: Â«ÐÐ¿Ð¿Ð°ÑÐ°ÑÐ½Ð°Ñ Ð°ÑÑÐ¸ÑÐµÐºÑÑÑÐ° Ð±Ð»Ð¾ÐºÐ° Ð¿Ð¾Ð¼ÐµÑÐ¾ÑÑÑÐ¾Ð¹ÑÐ¸Ð²Ð¾Ð³Ð¾ ÐºÐ¾Ð´Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ ÑÑÐ°Ð½Ð´Ð°ÑÑÐ¾Ð² DVB-S2/S2X Ð¸ ÐµÐµ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ñ Ð² FPGAÂ». ÐÐ°Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð¿Ð¾ÑÐ²ÑÑÐµÐ½Ð° ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐºÐµ Ð¸ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ð¸ Ð°Ð¿Ð¿Ð°ÑÐ°ÑÐ½Ð¾Ð¹ Ð°ÑÑÐ¸ÑÐµÐºÑÑÑÑ Ð±Ð»Ð¾ÐºÐ° Ð¿Ð¾Ð¼ÐµÑÐ¾ÑÑÑÐ¾Ð¹ÑÐ¸Ð²Ð¾Ð³Ð¾ ÐºÐ¾Ð´Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ ÑÑÐ°Ð½Ð´Ð°ÑÑÐ¾Ð² DVB-S2/S2X Ð´Ð»Ñ Ð¿ÑÐ¸Ð¼ÐµÐ½ÐµÐ½Ð¸Ñ Ð² ÑÐ¸ÑÑÐµÐ¼Ðµ Ð¼Ð¾Ð½Ð¸ÑÐ¾ÑÐ¸Ð½Ð³Ð° ÑÐ¿ÑÑÐ½Ð¸ÐºÐ¾Ð²ÑÑ ÑÐ¸Ð³Ð½Ð°Ð»Ð¾Ð² ÑÐ¸Ð¿Ð° âÐ½ÐµÑÑÑÐ°Ñ-Ð²-Ð½ÐµÑÑÑÐµÐ¹â. Ð ÑÐ¾Ð´Ðµ ÑÐ°Ð±Ð¾ÑÑ Ð±ÑÐ»Ð¸ ÑÐµÐ°Ð»Ð¸Ð·Ð¾Ð²Ð°Ð½Ñ ÐºÐ¾Ð´ÐµÑ BCH, ÐºÐ¾Ð´ÐµÑ LDPC, Ð¿ÐµÑÐµÐ¼ÐµÐ¶Ð¸ÑÐµÐ»Ñ Ð¸ Ð¼Ð¾Ð´ÑÐ»ÑÑÐ¾Ñ.ÐÐ»Ñ Ð¼Ð½Ð¾Ð³Ð¾ÐºÐ°Ð½Ð°Ð»ÑÐ½ÑÑ ÑÐ¸ÑÑÐµÐ¼ Ð¼Ð¾Ð½Ð¸ÑÐ¾ÑÐ¸Ð½Ð³Ð° ÑÐ¿ÑÑÐ½Ð¸ÐºÐ¾Ð²ÑÑ ÑÐ¸Ð³Ð½Ð°Ð»Ð¾Ð², Ð¸ÑÐ¿Ð¾Ð»ÑÐ·ÑÑÑÐ¸Ñ ÑÐ¸Ð¿ ÑÐ¸Ð³Ð½Ð°Ð»Ð° âÐ½ÐµÑÑÑÐ°Ñ-Ð²-Ð½ÐµÑÑÑÐµÐ¹â, ÐºÑÐ°Ð¹Ð½Ðµ Ð²Ð°Ð¶ÐµÐ½ Ð±Ð»Ð¾Ðº Ð¿Ð¾Ð¼ÐµÑÐ¾ÑÑÑÐ¾Ð¹ÑÐ¸Ð²Ð¾Ð³Ð¾ ÐºÐ¾Ð´Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ, Ð¸ÑÐ¿Ð¾Ð»ÑÐ·ÑÑÑÐ¸Ð¹ Ð¼Ð°Ð»Ð¾Ðµ ÐºÐ¾Ð»Ð¸ÑÐµÑÑÐ²Ð¾ Ð»Ð¾Ð³Ð¸ÑÐµÑÐºÐ¸Ñ ÑÐµÑÑÑÑÐ¾Ð² ÐÐÐÐ¡, Ð° ÑÐ°ÐºÐ¶Ðµ Ð¾Ð±Ð»Ð°Ð´Ð°ÑÑÐ¸Ð¹ Ð²ÑÑÐ¾ÐºÐ¾Ð¹ Ð¿ÑÐ¾Ð¸Ð·Ð²Ð¾Ð´Ð¸ÑÐµÐ»ÑÐ½Ð¾ÑÑÑÑ Ð´Ð»Ñ Ð¿Ð¾ÑÐ¾ÐºÐ¾Ð²Ð¾Ð¹ Ð¾Ð±ÑÐ°Ð±Ð¾ÑÐºÐ¸ Ð´Ð°Ð½Ð½ÑÑ. ÐÑÐµÐ´Ð»Ð°Ð³Ð°ÐµÐ¼Ð¾Ðµ ÑÑÑÑÐ¾Ð¹ÑÑÐ²Ð¾ Ð¾Ð±Ð»Ð°Ð´Ð°ÐµÑ Ð¿ÑÐ¾Ð¸Ð·Ð²Ð¾Ð´Ð¸ÑÐµÐ»ÑÐ½Ð¾ÑÑÑÑ Ð´Ð¾ 1,65 ÐÐ±Ð¸Ñ/ÑÐµÐº, Ð¿ÑÐ¸ ÑÐ°Ð±Ð¾ÑÐµÐ¹ ÑÐ°ÐºÑÐ¾Ð²Ð¾Ð¹ ÑÐ°ÑÑÐ¾ÑÐµ 352 ÐÐÑ Ð¸ ÑÐ¸ÑÐ»Ðµ Ð¸ÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°Ð½Ð½ÑÑ ÑÐµÑÑÑÑÐ¾Ð²: 15155 LUT, 8361 FF Ð¸ 75 BRAM. ÐÑÐ¸ ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐºÐµ Ð°ÑÑÐ¸ÑÐµÐºÑÑÑÑ Ð±ÑÐ»Ð° ÑÐ¾Ð·Ð´Ð°Ð½Ð° Ð¿Ð¾Ð´ÑÐ¾Ð±Ð½Ð°Ñ Ð¼Ð¾Ð´ÐµÐ»Ñ Ð² ÑÑÐµÐ´Ðµ Matlab, ÐºÐ¾ÑÐ¾ÑÐ°Ñ Ð²Ð¼ÐµÑÑÐµ Ñ ÑÐµÑÑÐ±ÐµÐ½ÑÐµÐ¼ ÑÐ¾ÑÑÐ°Ð²Ð»ÑÐ»Ð° ÑÐµÑÑÐ¾Ð²Ð¾Ðµ Ð¾ÐºÑÑÐ¶ÐµÐ½Ð¸Ðµ ÑÐµÐ°Ð»Ð¸Ð·Ð¾Ð²Ð°Ð½Ð½Ð¾Ð³Ð¾ Ð±Ð»Ð¾ÐºÐ° Ð¿Ð¾Ð¼ÐµÑÐ¾ÑÑÑÐ¾Ð¹ÑÐ¸Ð²Ð¾Ð³Ð¾ ÐºÐ¾Ð´Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ Ð¸ Ð¿Ð¾Ð·Ð²Ð¾Ð»ÑÐ»Ð° Ð½Ð° ÐºÐ°Ð¶Ð´Ð¾Ð¼ ÑÑÐ°Ð¿Ðµ ÐºÐ¾Ð´Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ ÑÐ²ÐµÑÑÑÑ Ð¾Ð¶Ð¸Ð´Ð°ÐµÐ¼ÑÐµ Ð´Ð°Ð½Ð½ÑÐµ Ñ Ð¿Ð¾Ð»ÑÑÐµÐ½Ð½ÑÐ¼Ð¸ Ð¸Ð· ÑÐ¸Ð¼ÑÐ»ÑÑÐ¸Ð¸ Ð² ÑÑÐµÐ´Ðµ ModelSim. Ð Ð°Ð·ÑÐ°Ð±Ð¾ÑÐ°Ð½Ð½Ð¾Ðµ ÑÑÑÑÐ¾Ð¹ÑÑÐ²Ð¾ Ð¿Ð¾Ð´Ð´ÐµÑÐ¶Ð¸Ð²Ð°ÐµÑ Ð¾Ð±Ð° ÑÑÐ°Ð½Ð´Ð°ÑÑÐ° DVB-S2 Ð¸ DVB-S2X, ÑÐ²Ð»ÑÐµÑÑÑ ÐºÐ¾Ð¼Ð¿Ð°ÐºÑÐ½ÑÐ¼ Ð¸ Ð¿ÑÐ¾Ð¸Ð·Ð²Ð¾Ð´Ð¸ÑÐµÐ»ÑÐ½ÑÐ¼. ÐÐ»Ð°Ð³Ð¾Ð´Ð°ÑÑ Ð´Ð°Ð½Ð½ÑÐ¼ ÐºÐ°ÑÐµÑÑÐ²Ð°Ð¼ Ð¾Ð½Ð¾ Ð¼Ð¾Ð¶ÐµÑ Ð½Ð°Ð¹ÑÐ¸ ÑÐ²Ð¾Ðµ Ð¿ÑÐ¸Ð¼ÐµÐ½ÐµÐ½Ð¸Ðµ Ð²Ð¾ Ð¼Ð½Ð¾Ð³Ð¸Ñ ÑÐ¸ÑÑÐµÐ¼Ð°Ñ ÑÐ¿ÑÑÐ½Ð¸ÐºÐ¾Ð²Ð¾Ð¹ ÑÐ²ÑÐ·Ð¸, Ð³Ð´Ðµ ÐºÑÐ°Ð¹Ð½Ðµ Ð²Ð°Ð¶ÐµÐ½ Ð±Ð°Ð»Ð°Ð½Ñ Ð¿ÑÐ¾Ð¸Ð·Ð²Ð¾Ð´Ð¸ÑÐµÐ»ÑÐ½Ð¾ÑÑÐ¸ Ð¸ ÐºÐ¾Ð¼Ð¿Ð°ÐºÑÐ½Ð¾ÑÑÐ¸. Ð ÑÐ°ÑÑÐ½Ð¾ÑÑÐ¸, ÑÐ°ÐºÐ¾Ð¹ ÑÐ¸ÑÑÐµÐ¼Ð¾Ð¹ Ð¸ ÑÐ²Ð»ÑÐµÑÑÑ Ð¼Ð½Ð¾Ð³Ð¾ÐºÐ°Ð½Ð°Ð»ÑÐ½Ð°Ñ ÑÐ¸ÑÑÐµÐ¼Ð° Ð¼Ð¾Ð½Ð¸ÑÐ¾ÑÐ¸Ð½Ð³Ð° ÑÐ¿ÑÑÐ½Ð¸ÐºÐ¾Ð²ÑÑ ÑÐ¸Ð³Ð½Ð°Ð»Ð¾Ð².
description: The subject of the graduate qualification work is: "Hardware architecture of the DVB-S2/S2X error-correcting coding block and its implementation in FPGA". The given work is devoted to the development and implementation of the hardware architecture of the DVB-S2/S2X error-correcting coding unit for use in a carrier-in-carrier satellite signal monitoring system. During the work, a BCH encoder, an LDPC encoder, an interleaver and a modulator were implemented. For multi-channel satellite signal monitoring systems using the carrier-in-carrier signal type, an error-correcting encoding block, using a small amount of FPGA logic resources, and also having high performance for streaming data processing, is extremely important. The proposed device has a performance of up to 1.65 Gb / s, with an operating clock frequency of 352 MHz and the number of resources used: 15155 LUT, 8361 FF and 75 BRAM.When developing the architecture, a detailed model was created in the Matlab environment, which, together with the testbench, constituted the test environment of the implemented block of error-correcting encoding and allowed to compare the expected data with those obtained from the simulation in the ModelSim environment at each stage of encoding. The developed device supports both DVB-S2 and DVB-S2X standards, is compact and efficient. Thanks to these qualities, it can find its application in many satellite communication systems, where the balance of performance and compactness is extremely important. In particular, such a system is a multi-channel monitoring system for satellite signals.