High-performance oversampling A/D converter design techniques in scaled CMOS technologies
Creators: name: Li, Shaolan
Publisher: name: The University of Texas at Austin
Year: 2018
Subjects: Analog-to-digital converters (ADC)
Oversampling ADC
Delta-Sigma ADC
Successive approximation register (SAR) ADC
Noise-shaping SAR ADC
Voltage-controlled-oscillator (VCO)
VCO-based ADC
Dynamic amplifier
Mixed-signal integrated circuit

description: Oversampling analog-to-digital converters (ADCs) are specialists in digitizing real-word signals in high resolution. They have been crucial building blocks in many modern electronic systems, and are expected to have a growing significance in the booming era of Internet-of-Things (IoT). However, many classic oversample ADC techniques are power-hungry and scaling-unfriendly, making them deficient for many emerging applications. To address this challenge, this thesis explores solution from two directions: voltage-controlled-oscillator (VCO)-based ADC and hybrid ADC. The first work presents a VCO-based ADC featuring a novel phase- extended-quantizer (PEQ). Compared to prior VCO-based ADCs, the proposed phase extension technique enabled this work to achieve 1-bit higher resolution with very little power and circuit overhead. On top of resolution boosting, A tri-level resistor digital-to-analog converter (DAC) is also introduced as complementary to the new quantizer, enabling high DR while creating a dynamic power saving mechanism for the proposed design. Fabricated in 130 nm CMOS, the prototype ADC achieved peak Schreier Figure-of-Merits (FoM) of 174.3 dB, marking 2.5x improvement over prior arts. The second project extends the achievement of the first and develops techniques to push the performance frontier of high-order VCO-based ADC. Existing high-order VCO-based ADCs still rely on OTA-based active loop filter, which deemphasizes the merits of the VCO-based quantizer. To address their limitation, a hybrid "passive + VCO" architecture is proposed, where we made the front-end loop filter fully passive and zero-power, and used the VCO to support the entire loop gain. This technique innovatively utilizes the parasitic effect of the VCO, hence also obviates the need for parasitic cancellation. A prototype fabricated in 40 nm CMOS measured 19 fJ/conversion Walden FoM, achieving 5x improvement over existing high-order VCO-based ADC. Finally, this thesis also presents the design of a noise-shaping SAR (NS-SAR) ADC. Unlike prior works that all rely on the cascaded integrator feed-forward (CIFF) structure, this work distinctively employs the error-feedback (EF) structure. It is the first in its kind to achieves second-order NTF with complex zero optimization, using all low-power scaling-friendly building blocks such as passive finite-impulse-response (FIR) filter and dynamic amplifier (D-Amp). A background calibration scheme is also developed to improve robustness over process-voltage-temperature (PVT) variation. The prototype chip fabricated in 40nm CMOS measured the state-of-the-art performance of 178 dB Schreier FoM. This works demonstrated a NS-SAR solution that combines optimized NTF, power efficiency and PVT robustness