Design and Implementation of Complexity Reduced Digital Signal Processors for Low Power Biomedical Applications
Creators: name: Eminaga, Yaprak
Publisher: name: University of Westminster
Year: 2019

description: Wearable health monitoring systems can provide remote care with supervised, inde-pendent living which are capable of signal sensing, acquisition, local processing and transmission. A generic biopotential signal (such as Electrocardiogram (ECG), and Electroencephalogram (EEG)) processing platform consists of four main functional components. The signals acquired by the electrodes are ampliﬁed and preconditioned by the (1) Analog-Front-End (AFE) which are then digitized via the (2) Analog-to-Digital Converter (ADC) for further processing. The local digital signal processing is usually handled by a custom designed (3) Digital Signal Processor (DSP) which is responsible for either anyone or combination of signal processing algorithms such as noise detection, noise/artefact removal, feature extraction, classiﬁcation and compres-sion. The digitally processed data is then transmitted via the (4) transmitter which is renown as the most power hungry block in the complete platform. All the afore-mentioned components of the wearable systems are required to be designed and ﬁtted into an integrated system where the area and the power requirements are stringent. Therefore, hardware complexity and power dissipation of each functional component are crucial aspects while designing and implementing a wearable monitoring platform. The work undertaken focuses on reducing the hardware complexity of a biosignal DSP and presents low hardware complexity solutions that can be employed in the aforemen-tioned wearable platforms. A typical state-of-the-art system utilizes Sigma Delta (Σ∆) ADCs incorporating a Σ∆ modulator and a decimation ﬁlter whereas the state-of-the-art decimation ﬁlters employ linear phase Finite-Impulse-Response (FIR) ﬁlters with high orders that in-crease the hardware complexity [1–5]. In this thesis, the novel use of minimum phase Inﬁnite-Impulse-Response (IIR) decimators is proposed where the hardware complexity is massively reduced compared to the conventional FIR decimators. In addition, the non-linear phase eﬀects of these ﬁlters are also investigated since phase non-linearity may distort the time domain representation of the signal being ﬁltered which is un-desirable eﬀect for biopotential signals especially when the ﬁducial characteristics carry diagnostic importance. In the case of ECG monitoring systems the eﬀect of the IIR ﬁlter phase non-linearity is minimal which does not aﬀect the diagnostic accuracy of the signals. The work undertaken also proposes two methods for reducing the hardware complexity of the popular biosignal processing tool, Discrete Wavelet Transform (DWT). General purpose multipliers are known to be hardware and power hungry in terms of the number of addition operations or their underlying building blocks like full adders or half adders required. Higher number of adders leads to an increase in the power consumption which is directly proportional to the clock frequency, supply voltage, switching activity and the resources utilized. A typical Field-Programmable-Gate-Array’s (FPGA) resources are Look-up Tables (LUTs) whereas a custom Digital Signal Processor’s (DSP) are gate-level cells of standard cell libraries that are used to build adders [6]. One of the proposed methods is the replacement of the hardware and power hungry general pur-pose multipliers and the coeﬃcient memories with reconﬁgurable multiplier blocks that are composed of simple shift-add networks and multiplexers. This method substantially reduces the resource utilization as well as the power consumption of the system. The second proposed method is the design and implementation of the DWT ﬁlter banks using IIR ﬁlters which employ less number of arithmetic operations compared to the state-of-the-art FIR wavelets. This reduces the hardware complexity of the analysis ﬁlter bank of the DWT and can be employed in applications where the reconstruction is not required. However, the synthesis ﬁlter bank for the IIR wavelet transform has a higher computational complexity compared to the conventional FIR wavelet synthesis ﬁlter banks since re-indexing of the ﬁltered data sequence is required that can only be achieved via the use of extra registers. Therefore, this led to the proposal of a novel design which replaces the complex IIR based synthesis ﬁlter banks with FIR ﬁl-ters which are the approximations of the associated IIR ﬁlters. Finally, a comparative study is presented where the hybrid IIR/FIR and FIR/FIR wavelet ﬁlter banks are de-ployed in a typical noise reduction scenario using the wavelet thresholding techniques. It is concluded that the proposed hybrid IIR/FIR wavelet ﬁlter banks provide better denoising performance, reduced computational complexity and power consumption in comparison to their IIR/IIR and FIR/FIR counterparts.