title: A Highly Reconfigurable RF-DPLL Phase Modulator for Digital-Intensive Transmitter Architectures in Cellular RFICs
title: Ein hochgradig rekonfigurierbarer RF-DPLL-Phasenmodulator für digital-intensive Sender-Architekturen in integrierten Hochfrequenz-Schaltkreisen für Mobilfunkanwendungen
Creators: name: Buckel, Tobias
Publisher: name: Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU)
Year: 2024
Subjects: subject: RF-DPLL, Polar Transmitter, Quadrature Transmitter, Phase Modulator, LTE, Hybrid Polar-I/Q Transmitter
subject: DDC Classification::5 Naturwissenschaften::53 Physik::537 Elektrizität und Elektronik

description: With the rapid development of cellular mobile communication towards the 4th generation (4G) and emerging 5th generation (5G), multi-band/multi-standard cellular radio frequency (RF) integrated circuits (ICs) operating in the UHF and lower SHF regions have experienced significant changes in several decisive properties like data rates, power consumption, and integration level in order to enable low-cost mobile platforms and mobile devices for the mass market. As a result of the ever-increasing demand for higher data rates and subscribers, channel access and modulation schemes with improved spectral efficiency, increased transmit (TX) and receive (RX) bandwidths as well as new frequency bands have been introduced. Due to the transition from bipolar complementary metal-oxide-semiconductor (CMOS) to ultra-deep submicron CMOS technology in line with a highly reconfigurable RF transceiver architecture and circuit design, more and more functionality of the wireless modem platform has been integrated into a single RFIC with the benefit of reduced area, bill of materials, and power consumption. As one of the big drawbacks arising with shrinking CMOS process structures, the analog performance of the transistor circuits degrades, leading to a trade-off between performance, power consumption and functional integration level. Therefore, digital-intensive transceivers have been developed, replacing functionality formerly realized within analog circuitry by digital circuits or supporting essential analog circuitry by additional digital signal processing to counter impairments in the analog parts caused by process, voltage and temperature effects. In this context, RF digital phase-locked loops (DPLLs), RF digital-to-analog converters (DACs) and digital power amplifiers (DPAs) enabling the implementation of digital-intensive polar and quadrature TX architectures have been developed. The digital polar TX consists of an amplitude and phase modulation path. The phase modulation of the RF carrier can be directly realized by a two-point modulation of the RF-DPLL, which recombines with the digital amplitude signal inside the RF-DAC. A major challenge in the polar TX is given by the arbitrary wideband nature of the phase and amplitude modulation signals as a result of the inherently non-linear coordinate transformation. As a consequence, the sampling rate of the digital front-end responsible for the Cartesian to polar coordinate transformation has to be very high compared to the Nyquist rate of the band-limited complex I/Q modulation signal. In terms of the RF-DPLL phase modulator, this results in a significantly increased frequency tuning range. This complicates the digital controlled oscillator (DCO) design and exhibits an increased sensitivity to effects like DCO nonlinearity, gain, and delay matching of the two-point modulation. The support of narrowband and wideband modulation schemes over a wide frequency range with power-optimized operation modes further complicates the phase modulator design. The thesis focuses on the system design of the RF-DPLL phase modulator. Several enhancements over existing implementations are shown to be necessary with respect to the support of single-carrier frequency division multiple access (SC-FDMA) as utilized channel access and modulation scheme in 4G LTE-A uplink transmission. It is shown that a DCO digital predistortion (DPD) is inevitable for higher LTE-A channel bandwidths in order to achieve a sufficiently low TX in-band distortion. An efficient implementation of the DPD is realized by a piece-wise linear predistortion based on a small set of DCO frequency measurements executed during RF-DPLL power-up. The two-point modulation requires precise delay matching and DCO gain normalization. Since the DCO gain is subject to PVT effects as well as the operating point, it can change over time, which requires accurate tracking. A DCO gain estimation (DGE) based upon a stochastic gradient minimization approach with model-reference adaptive control is shown. Due to the flexible spectral allocation found in LTE-A uplink, the DGE has to handle signals with a very low persistent excitation level, resulting in insufficient estimator performance, as well as signals with a very high excitation level and stringent requirements on the residual DGE error. A highly reconfigurable modulation path supporting a wide range of sampling frequencies has been implemented to also cover 2G and 3G legacy standards at optimized power consumption. Measurement results of the polar transmitter as part of a commercial RF transceiver implemented in 28 nm CMOS are shown to fulfill the stringent in-band and out-of-band requirements of 4G LTE-A uplink transmission with an aggregated channel bandwidth of 40 MHz for contiguous intra-band carrier aggregation. The second part of the thesis shows a novel digital-intensive hybrid polar-I/Q TX architecture that combines constrained phase with quadrature modulation, enabling a fluent transition from an exclusive polar to quadrature operation. In order to utilize the RF-DPLL as a phase modulator in the polar TX for transmission bandwidths beyond 20 MHz, the main challenges will be to cope with the limited DCO fine-tuning range for frequency modulation as well as the number of required DCO cores to cover the fragmented frequency spectrum. By incorporating constrained phase modulation, the quadrature RF-DAC can be operated with less back-off at a higher average output power and drain efficiency comparable to the digital-polar TX. In addition, a decoupling of the DFE sampling rate and RF-DPLL frequency modulation range is achieved. This results in a significant relaxation of the DCO tuning range requirement and reduces the number of required DCO cores. Therefore, the design effort is further shifted from analog to digital domain in order to better exploit the benefits of CMOS technology scaling.