title: Investigation into Detection of Counterfeit Integrated Circuits in Nano-scale CMOS Designs Using Aging Degradation
Creators: name: Alnuayri, Turki
Publisher: name: University of Liverpool Repository
Year: 2027

description: Electronic system designs and integrated circuits are exposed to counterfeiting due to the involvement of untrustworthy parties in the semiconductor supply chain. The semiconductor supply chain is spread across the globe to reduce cost and time to market and increase productivity. Recently, counterfeiting of integrated circuits (ICs) has threatened the security and reliability of all domain systems that utilise ICs, including computational platforms for various sectors such as banking, healthcare, military and aerospace. It is important to develop safeguards against IC counterfeiting in order to reduce the risks that can cause critical system failure in safety-critical applications, as such vulnerable devices may lead to financial loss and even compromise human lives. This research focuses on the most critical aspect of counterfeit ICs, including recycled and remarked ICs. It aims to develop a technique to distinguish between new and used digital ICs that have been used for a short period based on an aging sensor mechanism, including bias temperature instability (BTI) and hot carrier injection (HCI). Aging sensors have been studied based on path-delay fingerprinting and ring oscillators frequency degradation; their resolution requires further development to detect short usage accurately. This research discusses the novel works to provide techniques to detect ICs during short usage, contributing to IC counterfeiting countermeasures. The common problems in aging sensors that may bias detection results, including process, voltage, and temperature variations (PVTs), are considered. Cadence simulation tools are utilised based on the 22-nm CMOS technology provided by GlobalFoundries (GF) to achieve the thesis’s goals.

The first contribution of this thesis proposes a novel differential aging sensor to measure the discharge time (τdv) increase that depends on the sub-threshold leakage current degradation due to aging with two on chip designs. The first design incorporates two ring oscillators (ROs) copies: reference and stress RO (RRO and SRO). The second design only consists of one RO and a non-volatile memory (NVM) designed to reduce area overhead. The simulation results show that discharge time is a better aging indicator than frequency even with PVT variations for short usage (12 hours or more). The discharge times reached 48.75% and 55.93% after 15 days of usage and 160.93% and 310.17% after three years of usage for 13- and 51-stage ROs, respectively. In contrast, the frequency degradation of the 13-RO reached 19.71% after 15 days of usage and 42.12% after three years of usage, while it reached 11.63% after 15 days of usage and 45.44% after three years of usage with the 51-RO.

The second contribution of this thesis collects aging degradation induced by BTI and HCI, observing frequency and discharge time affected by changes in drain current and sub-threshold leakage current over time. It utilises a simple transfer function over the modelling results (Cadence simulations) to develop a Machine Learning (ML) model for real-time on-chip aging evaluation that can be used to estimate the IC’s age under any operating conditions (supply voltage and temperature). The support vector regression (SVR) algorithm is adapted for this application using a training process that involves operating temperature, discharge time, frequency, and aging time. The proposed model is also trained and tested to account for inter-die and intra-die process variation for frequency and discharge time.