Layout automation for custom integrated circuits
Creators: name: Chen, Hao (Ph. D. In Electrical And Computer Engineering)
name: 0000-0001-5830-3643
Publisher: name: The University of Texas at Austin
Year: 2023
Subjects: Physical design
Custom circuit layout

description: In the past few decades, there has been extensive research on automating the layout of custom integrated circuits (ICs), including analog and mixed-signal (AMS) designs and sensitive digital circuits (e.g., high-speed serializers and deserializers). However, in contrast to their digital counterparts, automated layout tools for custom circuits have not yet been widely embraced in contemporary industrial circuit design procedures. This shortcoming stems from the difficulty and sensitive nature of the custom circuit design problem itself. Parasitic matching, layout-dependent effects (LDE), and signal integrity are crucial design factors that can significantly impact the ultimate post-layout performance. Stacking together, these intricate constraints prevent automated tools from producing solutions of comparable quality to manual designs handcrafted by experienced experts. Nonetheless, as application-specific designs receive more attention to enable accelerated, energy-efficient computing for artificial intelligence (AI) workloads, recent research has demonstrated a growing interest in custom layout automation, as it continues to be one of the primary bottlenecks in the custom circuit design flow. Due to their superior balance of solution quality and execution efficiency, existing custom layout tools make extensive use of optimization-based techniques. This dissertation discusses the three major challenges for an optimization-based layout system to automatically implement layouts for custom circuits, namely: (1) automated layout constraint extraction, which generates specialized geometrical requirements to realize specific layout structures for improved performance; (2) constraint-aware custom placement, which determines the physical locations of transistors and devices while satisfying specified constraints; and (3) constraint-aware custom routing, which completes the interconnections while considering performance-driven constraints and design rules for manufacturing. For automated constraint extraction, we propose a novel graph-learning-based framework for universal symmetry constraint annotation. Leveraging unsupervised inductive learning on graph neural networks (GNNs), the proposed framework learns a strategy to extract the information of matching patterns in circuit netlists, which can then be applied to a wide variety of circuit classes. In addition, we propose a constraint-aware custom placement engine targeting advanced fin field-effect transistor (FinFET) designs. Using satisfiability modulo theory (SMT) formulations, the proposed custom placer has extensive constraint-solving capabilities and the flexibility to add new constraint support for future needs. Finally, we propose a robust custom router capable of optimizing wire connections while incorporating geometrical and electrical constraints and industrial design rules for sign-off quality layouts. To realize complex wiring structures, we also proposed a reinforcement learning (RL)-based rip-up and re-route method as an extension to our router. Extensive experiments demonstrate the efficacy of the proposed methods for constructing a comprehensive end-to-end optimization-based custom layout automation system. The proposed techniques are now integral components of MAGICAL, an open-source analog and mixed-signal layout software, and AutoCRAFT, the custom layout implementation tool for advanced FinFET technology.