VP8-01 Exploring the energy efficiency of MRAM-based Computing-in-Memory for DNN training
Creators: Shuai Zhou、Yanfeng Jiang
Publisher: name: IEEE
Year: 2025

As Deep Neural Networks (DNNs) are widely used in various AI applications, there is an increasing demand for energy efficiency and computational speed. Computing-in-Memory (CIM), as a potential solution, can significantly reduce the energy consumption and latency associated with data transmission by performing computation in memory. In this paper, the application of spintronics-based in-store computing methods in training DNNs is explored. Firstly, the fundamentals of spintronic devices and their potential application in nonvolatile storage are introduced. Subsequently, an architecture for in-store computation using spintronic devices is proposed, as shown in Fig. 1. This architecture is capable of efficiently performing computational tasks of neural networks at the storage level. The architecture can be used to accelerate the DNN training process and reduce the energy consumption for training by utilizing the parallel computing power and low energy consumption characteristics of spintronic devices. Based on the designed architecture, the effectiveness and the performance of the proposed in-store computation scheme are verified based on NeuroSim simulation platform. By conducting the standard DNN training task, it shows that the spintronic device-based in-store computation method is able to significantly reduce the energy consumption compared to SRAM- and PCM-based training with the same accuracy, as shown in Fig. 2. Finally, the challenges and future research directions for in-store computational methods based on spintronic devices are discussed. These challenges include aspects of device fabrication and consistency, architecture scalability, and algorithm optimization. In conclusion, the potential and advantages of in-store computing methods based on spintronic devices in training deep neural networks are demonstrated by the theoretical analysis and the experimental validation. This research provides valuable reference and guidance for future efficient AI hardware design and development.References: Doevenspeck J, Garello K, Verhoef B, et al. "SOT-MRAM based analog in-memory computing for DNN inference." IEEE Symposium on VLSI Technology. IEEE, 2020. Yu Pan,Peng Ouyang,Yinglin Zhao. et al."A multilevel cell STT-MRAM-based computing inmemory accelerator for binary convolutional neural network." IEEE Transactions on Magnetics, vol. 54, no. 11, pp. 1-5, 2018. Q. Dong, Mahmut E. Sinangil, Burak Erbagci. et al., "A 351TOPS/W and 372.4 GOPS compute-in-memory SRAM macro in 7nm FinFET CMOS for machine-learning applications." IEEE International Solid-State Circuits Conference (ISSCC), 2020. Peng X, Huang S, Luo Y, et al. "DNN+ NeuroSim: An end-to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies." IEEE international electron devices meeting (IEDM), 2019.
As Deep Neural Networks (DNNs) are widely used in various AI applications, there is an increasing demand for energy efficiency and computational speed. Computing-in-Memory (CIM), as a potential solution, can significantly reduce the energy consumption and latency associated with data transmission by performing computation in memory. In this paper, the application of spintronics-based in-store computing methods in training DNNs is explored. Firstly, the fundamentals of spintronic devices and their potential application in nonvolatile storage are introduced. Subsequently, an architecture for in-store computation using spintronic devices is proposed, as shown in Fig. 1. This architecture is capable of efficiently performing computational tasks of neural networks at the storage level. The architecture can be used to accelerate the DNN training process and reduce the energy consumption for training by utilizing the parallel computing power and low energy consumption characteristics of spintronic devices. Based on the designed architecture, the effectiveness and the performance of the proposed in-store computation scheme are verified based on NeuroSim simulation platform. By conducting the standard DNN training task, it shows that the spintronic device-based in-store computation method is able to significantly reduce the energy consumption compared to SRAM- and PCM-based training with the same accuracy, as shown in Fig. 2. Finally, the challenges and future research directions for in-store computational methods based on spintronic devices are discussed. These challenges include aspects of device fabrication and consistency, architecture scalability, and algorithm optimization. In conclusion, the potential and advantages of in-store computing methods based on spintronic devices in training deep neural networks are demonstrated by the theoretical analysis and the experimental validation. This research provides valuable reference and guidance for future efficient AI hardware design and development.References: Doevenspeck J, Garello K, Verhoef B, et al. "SOT-MRAM based analog in-memory computing for DNN inference." IEEE Symposium on VLSI Technology. IEEE, 2020. Yu Pan,Peng Ouyang,Yinglin Zhao. et al."A multilevel cell STT-MRAM-based computing inmemory accelerator for binary convolutional neural network." IEEE Transactions on Magnetics, vol. 54, no. 11, pp. 1-5, 2018. Q. Dong, Mahmut E. Sinangil, Burak Erbagci. et al., "A 351TOPS/W and 372.4 GOPS compute-in-memory SRAM macro in 7nm FinFET CMOS for machine-learning applications." IEEE International Solid-State Circuits Conference (ISSCC), 2020. Peng X, Huang S, Luo Y, et al. "DNN+ NeuroSim: An end-to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies." IEEE international electron devices meeting (IEDM), 2019.