title: Ð Ð°Ð·ÑÐ°Ð±Ð¾ÑÐºÐ° Ð±Ð»Ð¾ÐºÐ¾Ð² Ð´Ð»Ñ Ð¿Ð¾Ð´ÑÐ¸ÑÑÐµÐ¼Ñ ÑÐµÑÐ½Ð¾ ÑÐ²ÑÐ·Ð°Ð½Ð½Ð¾Ð¹ Ð¿Ð°Ð¼ÑÑÐ¸ Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ½Ð¾Ð³Ð¾ ÐºÐ¾Ð¼Ð¿Ð»ÐµÐºÑÐ°
title: Ð²ÑÐ¿ÑÑÐºÐ½Ð°Ñ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð±Ð°ÐºÐ°Ð»Ð°Ð²ÑÐ°
titleType: Subtitle
title: Development of blocks for the tightly coupled memory subsystem of a processor complex
Creators: name: ÐÐ½ÑÑÑÐ¸ÐµÐ½ÐºÐ¾, ÐÐ¸ÐºÐ¾Ð»Ð°Ð¹
Publisher: name: Ð¡Ð°Ð½ÐºÑ-ÐÐµÑÐµÑÐ±ÑÑÐ³ÑÐºÐ¸Ð¹ Ð¿Ð¾Ð»Ð¸ÑÐµÑÐ½Ð¸ÑÐµÑÐºÐ¸Ð¹ ÑÐ½Ð¸Ð²ÐµÑÑÐ¸ÑÐµÑ ÐÐµÑÑÐ° ÐÐµÐ»Ð¸ÐºÐ¾Ð³Ð¾
Year: 2024
Subjects: ÑÐµÑÐ½Ð¾ ÑÐ²ÑÐ·Ð°Ð½Ð½Ð°Ñ Ð¿Ð°Ð¼ÑÑÑ
ÐºÐ¾Ð½ÑÑÐ¾Ð»Ñ ÑÐµÐ»Ð¾ÑÑÐ½Ð¾ÑÑÐ¸
ÑÐ¿ÑÐ°Ð²Ð»ÐµÐ½Ð¸Ðµ Ð´Ð¾Ð¼ÐµÐ½Ð°Ð¼Ð¸ Ð¿Ð¸ÑÐ°Ð½Ð¸Ñ
tightly coupled memory
power management
error detection and correction
ECC

description: Ð¦ÐµÐ»ÑÑ ÑÐ°Ð±Ð¾ÑÑ ÑÐ²Ð»ÑÐµÑÑÑ ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐºÐ° Ð±Ð»Ð¾ÐºÐ¾Ð² Ð½Ð° ÑÐ·ÑÐºÐµ SystemVerilog, ÑÐµÐ°Ð»Ð¸Ð·ÑÑÑÐ¸Ñ Ð¼ÐµÑÐ°Ð½Ð¸Ð·Ð¼Ñ ÐºÐ¾Ð½ÑÑÐ¾Ð»Ñ ÑÐµÐ»Ð¾ÑÑÐ½Ð¾ÑÑÐ¸ Ð¸ ÑÐ¿ÑÐ°Ð²Ð»ÐµÐ½Ð¸Ñ ÑÐ½ÐµÑÐ³Ð¾Ð¿Ð¾ÑÑÐµÐ±Ð»ÐµÐ½Ð¸ÐµÐ¼ Ð² Ð°ÑÐ±Ð¸ÑÑÐµ ÑÐµÑÐ½Ð¾ ÑÐ²ÑÐ·Ð°Ð½Ð½Ð¾Ð¹ Ð¿Ð°Ð¼ÑÑÐ¸ Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ½Ð¾Ð³Ð¾ ÐºÐ¾Ð¼Ð¿Ð»ÐµÐºÑÐ°. Ð ÑÐ°Ð¼ÐºÐ°Ñ ÑÐ°Ð±Ð¾ÑÑ Ð½Ð°Ð´ Ð²Ð½ÐµÐ´ÑÐµÐ½Ð¸ÐµÐ¼ Ð¼ÐµÑÐ°Ð½Ð¸Ð·Ð¼Ð° ÐºÐ¾Ð½ÑÑÐ¾Ð»Ñ ÑÐµÐ»Ð¾ÑÑÐ½Ð¾ÑÑÐ¸ Ð±ÑÐ» ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐ°Ð½ ÐºÐ¾Ð½ÑÑÐ¾Ð»Ð»ÐµÑ ECÐ¡. Ð Ð°Ð·ÑÐ°Ð±Ð¾ÑÐºÐ° Ð´Ð°Ð½Ð½Ð¾Ð³Ð¾ Ð±Ð»Ð¾ÐºÐ° Ð±ÑÐ»Ð° Ð¾ÑÐ»Ð¾Ð¶Ð½ÐµÐ½Ð° ÑÐ°ÑÐ°ÐºÑÐµÑÐ¾Ð¼ Ð¸Ð·Ð¼ÐµÐ½ÐµÐ½Ð¸Ð¹, Ð²Ð½Ð¾ÑÐ¸Ð¼ÑÑ Ð² Ð¸Ð½ÑÐµÑÑÐµÐ¹Ñ Ð±Ð»Ð¾ÐºÐ¾Ð² ÑÐµÑÐ½Ð¾ ÑÐ²ÑÐ·Ð°Ð½Ð½Ð¾Ð¹ Ð¿Ð°Ð¼ÑÑÐ¸. Ð¢Ð°ÐºÐ¶Ðµ Ð±ÑÐ»Ð¸ ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐ°Ð½Ñ Ð±Ð»Ð¾ÐºÐ¸, Ð¿Ð¾Ð·Ð²Ð¾Ð»ÑÑÑÐ¸Ðµ ÑÐ¾ ÑÑÐ¾ÑÐ¾Ð½Ñ Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ð½Ð¾Ð³Ð¾ Ð¾Ð±ÐµÑÐ¿ÐµÑÐµÐ½Ð¸Ñ Ð¿ÑÑÐµÐ¼ Ð¾Ð±ÑÐ°ÑÐµÐ½Ð¸Ñ Ðº ÑÐµÐ³Ð¸ÑÑÑÐ°Ð¼, Ð¾ÑÐ¾Ð±ÑÐ°Ð¶ÐµÐ½Ð½ÑÐ¼ Ð² Ð¿Ð°Ð¼ÑÑÑ, Ð²Ð½Ð¾ÑÐ¸ÑÑ Ð¾ÑÐ»Ð°Ð´Ð¾ÑÐ½ÑÐµ ECC Ð¾ÑÐ¸Ð±ÐºÐ¸ Ð¸ Ð¾ÑÑÐ»ÐµÐ¶Ð¸Ð²Ð°ÑÑ Ð¾Ð±ÑÐµÐµ ÐºÐ¾Ð»Ð¸ÑÐµÑÑÐ²Ð¾ Ð¸ÑÐ¿ÑÐ°Ð²Ð»ÐµÐ½Ð½ÑÑ Ð¾Ð´Ð¸Ð½Ð¾ÑÐ½ÑÑ ECC Ð¾ÑÐ¸Ð±Ð¾Ðº. ÐÐ»Ñ Ð¿Ð¾Ð´Ð´ÐµÑÐ¶ÐºÐ¸ ÑÐ¿ÑÐ°Ð²Ð»ÐµÐ½Ð¸Ñ Ð´Ð¾Ð¼ÐµÐ½Ð°Ð¼Ð¸ Ð¿Ð¸ÑÐ°Ð½Ð¸Ñ Ð±ÑÐ» ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐ°Ð½ Ð±Ð»Ð¾Ðº, ÑÐ¾Ð³Ð»Ð°ÑÑÑÑÐ¸Ð¹ ÑÐ¾ÑÑÐ¾ÑÐ½Ð¸Ðµ Ð´Ð¾Ð¼ÐµÐ½Ð° Ð¿Ð¸ÑÐ°Ð½Ð¸Ñ Ñ Ð±Ð»Ð¾ÐºÐ¾Ð¼ ÑÐ¿ÑÐ°Ð²Ð»ÐµÐ½Ð¸Ñ ÑÐ½ÐµÑÐ³Ð¾Ð¿Ð¾ÑÑÐµÐ±Ð»ÐµÐ½Ð¸Ñ Ð¿Ð¾ ÑÐ¾Ð¾ÑÐ²ÐµÑÑÑÐ²ÑÑÑÐµÐ¼Ñ Ð¸Ð½ÑÐµÑÑÐµÐ¹ÑÑ. Ð¢Ð°ÐºÐ¶Ðµ Ð±ÑÐ»Ð° Ð¿ÑÐ¾ÑÐ°Ð±Ð¾ÑÐ°Ð½Ð° ÑÑÐµÐ¼Ð° ÑÐ°ÐºÑÐ¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ Ð´Ð¾Ð¼ÐµÐ½Ð¾Ð² Ð¿Ð¸ÑÐ°Ð½Ð¸Ñ. ÐÐ»Ñ ÑÑÐ½ÐºÑÐ¸Ð¾Ð½Ð°Ð»ÑÐ½Ð¾Ð¹ Ð²ÐµÑÐ¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¸ Ð²Ð½ÐµÐ´ÑÐµÐ½Ð½ÑÑ Ð¼ÐµÑÐ°Ð½Ð¸Ð·Ð¼Ð¾Ð² Ð±ÑÐ»Ð¸ ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐ°Ð½Ñ ÑÐµÑÑÑ Ð½Ð° ÑÐ·ÑÐºÐµ SystemVerilog, Ð² ÐºÐ¾ÑÐ¾ÑÑÑ Ð±ÑÐ»Ð° ÑÐµÐ°Ð»Ð¸Ð·Ð¾Ð²Ð°Ð½Ð° Ð¿ÑÐ¾Ð²ÐµÑÐºÐ° ÑÐ¸Ð¿Ð¾Ð²ÑÑ Ð¸ ÐºÑÐ°Ð¹Ð½Ð¸Ñ ÑÐ»ÑÑÐ°ÐµÐ², Ð²Ð¾Ð·Ð½Ð¸ÐºÐ°ÑÑÐ¸Ñ Ð¿ÑÐ¸ ÑÑÐ½ÐºÑÐ¸Ð¾Ð½Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ð¸ ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐ°Ð½Ð½Ð¾Ð³Ð¾ Ð½Ð°Ð±Ð¾ÑÐ° Ð±Ð»Ð¾ÐºÐ¾Ð². Ð ÐºÐ¾Ð½ÑÐµ ÑÐ°Ð±Ð¾ÑÑ Ð±ÑÐ» Ð¿ÑÐ¾Ð¸Ð·Ð²ÐµÐ´ÐµÐ½ Ð°Ð½Ð°Ð»Ð¸Ð· Ð²Ð»Ð¸ÑÐ½Ð¸Ñ Ð²Ð½ÐµÐ´ÑÑÐ½Ð½ÑÑ Ð¼ÐµÑÐ°Ð½Ð¸Ð·Ð¼Ð¾Ð² Ð½Ð° ÑÐµÐ·ÑÐ»ÑÑÐ°ÑÑ ÑÐ¸Ð½ÑÐµÐ·Ð° Ð°ÑÐ±Ð¸ÑÑÐ° Ð¸ Ð½Ð° Ð¿ÑÐ¾Ð¸Ð·Ð²Ð¾Ð´Ð¸ÑÐµÐ»ÑÐ½Ð¾ÑÑÑ Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ½Ð¾Ð³Ð¾ ÐºÐ¾Ð¼Ð¿Ð»ÐµÐºÑÐ°.
description: The aim of the work is to develop blocks in the SystemVerilog language that implement error detection and correction and power management mechanisms in the arbiter of the tightly coupled memory (TCM) of the processor complex. As part of the work on implementing the error detection and correction mechanism, an ECC controller was developed. The development of this block was complicated by the nature of the changes made to the TCM interface. Additional blocks were also developed to allow software, through access to memory-mapped registers, to inject debug ECC errors and monitor the total number of corrected single ECC errors. To support power domain management, a block was developed to coordinate the power domain state with the power management block through the appropriate interface. A power domain clocking scheme was also developed. For the functional verification of the implemented mechanisms, tests were developed in SystemVerilog, which included checking typical and corner cases arising from the functioning of the developed set of blocks. At the end of the work, the impact of the implemented mechanisms on synthesis results and the performance of the processor complex was analyzed.