title: Ð ÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ñ Ð¿ÐµÑÐµÐ¼ÐµÐ¶Ð¸ÑÐµÐ»Ñ ÑÑÐ°Ð½Ð´Ð°ÑÑÐ° DVB-S2X Ð² FPGA
title: Ð²ÑÐ¿ÑÑÐºÐ½Ð°Ñ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð±Ð°ÐºÐ°Ð»Ð°Ð²ÑÐ°
titleType: Subtitle
title: Implementation of the interleaver of standard DVB-S2X in FPGA
Creators: name: Ð§ÑÐ¿ÑÐ¸Ð½Ð°, Ð Ð¾Ð¼Ð°Ð½
Publisher: name: Ð¡Ð°Ð½ÐºÑ-ÐÐµÑÐµÑÐ±ÑÑÐ³ÑÐºÐ¸Ð¹ Ð¿Ð¾Ð»Ð¸ÑÐµÑÐ½Ð¸ÑÐµÑÐºÐ¸Ð¹ ÑÐ½Ð¸Ð²ÐµÑÑÐ¸ÑÐµÑ ÐÐµÑÑÐ° ÐÐµÐ»Ð¸ÐºÐ¾Ð³Ð¾
Year: 2020
Subjects: DVB-S2X
Ð¿Ð¾Ð¼ÐµÑ Ð¾ÑÑÑÐ¾Ð¹ÑÐ¸Ð²Ð¾Ðµ ÐºÐ¾Ð´Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ðµ
ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ñ
Ð¿ÐµÑÐµÑÑÐ°Ð½Ð¾Ð²ÐºÐ°
forward error-correction
implementation
permutation

description: Ð¢ÐµÐ¼Ð° Ð²ÑÐ¿ÑÑÐºÐ½Ð¾Ð¹ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð¾Ð¹ ÑÐ°Ð±Ð¾ÑÑ: Â«Ð ÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ñ Ð¿ÐµÑÐµÐ¼ÐµÐ¶Ð¸ÑÐµÐ»Ñ ÑÑÐ°Ð½-Ð´Ð°ÑÑÐ° DVB-S2X Ð² FPGAÂ». Ð Ð´Ð°Ð½Ð½Ð¾Ð¹ ÑÐ°Ð±Ð¾ÑÐµ ÑÐ°ÑÑÐ¼Ð¾ÑÑÐµÐ½ Ð±Ð»Ð¾Ðº-Ð¿ÐµÑÐµÐ¼ÐµÐ¶Ð¸ÑÐµÐ»Ñ ÑÑÐ°Ð½Ð´Ð°ÑÑÐ° DVB-S2X. ÐÐ·ÑÑÐµÐ½Ð° Ð¾Ð±ÑÐ°Ñ ÑÑÐµÐ¼Ð° Ð¼Ð¾Ð´ÐµÐ¼Ð° Ð¸ÑÑÐ»ÐµÐ´ÑÐµÐ¼Ð¾Ð³Ð¾ ÑÑÐ°Ð½Ð´Ð°ÑÑÐ°, Ð° ÑÐ°ÐºÐ¶Ðµ Ð¼Ð¾Ð´ÑÐ»Ñ Ð¿Ð¾Ð¼ÐµÑÐ¾ÑÑÑÐ¾Ð¹ÑÐ¸Ð²Ð¾Ð³Ð¾ ÐºÐ¾Ð´Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ Ð² ÐµÑ ÑÐ¾ÑÑÐ°Ð²Ðµ. ÐÑÐµÐ´Ð»Ð¾Ð¶ÐµÐ½ Ð¼ÐµÑÐ¾Ð´ Ð½Ð° Ð¾ÑÐ½Ð¾Ð²Ðµ Ð»Ð¸Ð½ÐµÐ¹Ð½Ð¾Ð³Ð¾ ÐºÐ¾Ð½Ð³ÑÑÑÐ½ÑÐ½Ð¾Ð³Ð¾ Ð³ÐµÐ½ÐµÑÐ°ÑÐ¾ÑÐ°, ÐºÐ¾ÑÐ¾ÑÑÐ¹ Ð²Ð·ÑÑ Ð·Ð° Ð¾ÑÐ½Ð¾Ð²Ñ Ð¿ÑÐ¸ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ð¸ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð° Ð² FPGA. ÐÑÐµÐ½ÐµÐ½Ñ ÑÐ°Ð·Ð»Ð¸ÑÐ½ÑÐµ ÐºÐ¾Ð½ÑÐ¸Ð³ÑÑÐ°ÑÐ¸Ð¸ Ð¿ÐµÑÐµÐ¼ÐµÐ¶Ð¸ÑÐµÐ»Ñ. Ð Ð°ÑÑÐ¼Ð¾ÑÑÐµÐ½Ñ ÑÐ¶Ðµ ÑÑÑÐµÑÑÐ²ÑÑÑÐ¸Ðµ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ð¸ Ð±Ð»Ð¾ÐºÐ° Ð¿ÐµÑÐµÐ¼ÐµÐ¶Ð¸ÑÐµÐ»Ñ Ð¸ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ñ Ð¸Ñ ÑÐ°Ð±Ð¾ÑÑ. ÐÑÐ»Ð° ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐ°Ð½Ð° Ð°ÑÑÐ¸ÑÐµÐºÑÑÑÐ° Ð±Ð»Ð¾ÑÐ½Ð¾Ð³Ð¾ Ð¿ÐµÑÐµÐ¼ÐµÐ¶Ð¸ÑÐµÐ»Ñ ÑÐ¿ÑÐ°Ð²Ð»ÑÐµÐ¼Ð¾Ð³Ð¾ Ð¼Ð¾Ð´ÐºÐ¾Ð´Ð¾Ð¼, Ñ Ð¿Ð¾Ð¼Ð¾ÑÑÑ ÐºÐ¾ÑÐ¾ÑÐ¾Ð³Ð¾ Ð·Ð°Ð´Ð°ÑÑÑÑ Ð¿Ð°ÑÐ°Ð¼ÐµÑÑÑ Ð¿ÐµÑÐµÐ¼ÐµÐ¶Ð¸ÑÐµÐ»Ñ, ÑÐ°Ð±Ð¾ÑÐ°ÑÑÐµÐ³Ð¾ Ð¿Ð¾ Ð¿ÑÐ¸Ð½-ÑÐ¸Ð¿Ñ Ð´Ð²Ð¾Ð¹Ð½Ð¾Ð¹ Ð¿Ð°Ð¼ÑÑÐ¸, Ð² ÐºÐ¾ÑÐ¾ÑÐ¾Ð¼ ÑÑÑÑÐ°Ð½ÐµÐ½Ð° Ð¿ÑÐ¾Ð±Ð»ÐµÐ¼Ð° ÐºÐ¾Ð¼Ð¿Ð»ÐµÐºÑÐ½Ð¾Ð³Ð¾ ÐºÐ¾Ð½ÐµÑÐ½Ð¾Ð³Ð¾ Ð°Ð²ÑÐ¾Ð¼Ð°ÑÐ° Ð¿ÑÑÐµÐ¼ ÑÐ°Ð·Ð´ÐµÐ»ÐµÐ½Ð¸Ñ Ð¾Ð¿ÐµÑÐ°ÑÐ¸Ð¸ Ð¿ÐµÑÐµÐ¼ÐµÐ¶ÐµÐ½Ð¸Ñ Ð² Ð´Ð²Ð° ÑÑÐ°Ð¿Ð°: Ð¼Ð°ÑÑÐ¸ÑÐ½Ð¾Ð³Ð¾ Ð¿ÐµÑÐµÐ¼ÐµÐ¶ÐµÐ½Ð¸Ñ Ð¸ Ð±Ð»Ð¾ÐºÐ° Ð¿ÐµÑÐµÑÑÐ°Ð½Ð¾Ð²ÐºÐ¸. Ð£Ð´Ð°Ð»Ð¾ÑÑ ÑÑÐ¿ÐµÑÐ½Ð¾ Ð¿ÑÐ¾Ð¸Ð·Ð²ÐµÑÑÐ¸ ÑÐ°Ð·Ð²Ð¾Ð´ÐºÑ Ð¿ÑÐ¾ÐµÐºÑÐ° Ð´Ð»Ñ Ð°ÑÑÐ¸ÑÐµÐºÑÑÑÑ, Ð¿ÑÐµÐ´Ð»Ð¾Ð¶ÐµÐ½Ð½Ð¾Ð¹ Ð² Ð´Ð°Ð½Ð½Ð¾Ð¹ Ð±Ð°ÐºÐ°Ð»Ð°Ð²ÑÑÐºÐ¾Ð¹ ÑÐ°Ð±Ð¾ÑÐµ.
description: The subject of the graduate qualification work is "Implementation of the interleaver of standard DVB-S2X in FPGA." In this paper, a block interleaver of the DVB-S2X standard is considered. The general modem circuit of the standard under study, as well as FEC module in its composition, are studied. A method based on a linear congruent generator is pro-posed, which is taken as the basis for the implementation of the algorithm in FPGA. Different interleaver configurations are evaluated. Existing implementations of the interleaver block and their operation algorithms are considered. The architecture of a block interleaver controlled by a modcode was developed, with the help of which parameters of an interleaver working on the principle of double memory are set, in which the problem of a complex state machine is eliminated by separating the inter-leaving operation in two stages: matrix interleaving and a permutation unit. It was possible to successfully lay out the project for the architecture proposed in this bachelor's work.