title: Ð Ð°Ð·ÑÐ°Ð±Ð¾ÑÐºÐ° Ð¿ÑÐ¾ÑÐ¾ÑÐ¸Ð¿Ð¾Ð² Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ð¸ÑÑÐµÐ¼Ð¾Ð³Ð¾ Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ° Ð¾Ð±ÑÐ°Ð±Ð¾ÑÐºÐ¸ ÑÐ¸Ð³Ð½Ð°Ð»Ð¾Ð² Ð½Ð° ÐÐÐÐ¡
title: Ð²ÑÐ¿ÑÑÐºÐ½Ð°Ñ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð±Ð°ÐºÐ°Ð»Ð°Ð²ÑÐ°
titleType: Subtitle
title: Development of prototypes of a programmable signal processor on an FPGA
Creators: name: ÐÐ°Ð³Ð¾Ð¼ÐµÐ´Ð¾Ð², Ð¢Ð¸Ð¼ÑÑ
Publisher: name: Ð¡Ð°Ð½ÐºÑ-ÐÐµÑÐµÑÐ±ÑÑÐ³ÑÐºÐ¸Ð¹ Ð¿Ð¾Ð»Ð¸ÑÐµÑÐ½Ð¸ÑÐµÑÐºÐ¸Ð¹ ÑÐ½Ð¸Ð²ÐµÑÑÐ¸ÑÐµÑ ÐÐµÑÑÐ° ÐÐµÐ»Ð¸ÐºÐ¾Ð³Ð¾
Year: 2024
Subjects: DSP
Ð¿ÑÐ¾ÑÐµÑÑÐ¾Ñ ÑÐ¸ÑÑÐ¾Ð²Ð¾Ð¹ Ð¾Ð±ÑÐ°Ð±Ð¾ÑÐºÐ¸ ÑÐ¸Ð³Ð½Ð°Ð»Ð¾Ð²
PSP
Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ð¸ÑÑÐµÐ¼ÑÐ¹ Ð¿ÑÐ¾ÑÐµÑÑÐ¾Ñ ÑÐ¸Ð³Ð½Ð°Ð»Ð¾Ð²
ÐÐÐÐ¡
soft-Ð¿ÑÐ¾ÑÐµÑÑÐ¾Ñ
ÐºÐ¾Ð½Ð²ÐµÐ¹ÐµÑ
Quartus
ModelSim
SystemVerilog
Java
digital signal processor
programmable signal processor
FPGA
soft-processor
pipeline

description: ÐÐ°Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð¿Ð¾ÑÐ²ÑÑÐµÐ½Ð° Ð¿ÑÐ¾ÐµÐºÑÐ¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ Ð¿ÑÐ¾ÑÐ¾ÑÐ¸Ð¿Ð¾Ð² Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ° ÑÐ¸ÑÑÐ¾Ð²Ð¾Ð¹ Ð¾Ð±ÑÐ°Ð±Ð¾ÑÐºÐ¸ ÑÐ¸Ð³Ð½Ð°Ð»Ð¾Ð² Ð½Ð° ÐÐÐÐ¡ Ñ Ð¸ÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°Ð½Ð¸ÐµÐ¼ ÑÐ·ÑÐºÐ° Ð¾Ð¿Ð¸ÑÐ°Ð½Ð¸Ñ SystemVerilog. ÐÐ°Ð´Ð°ÑÐ¸, ÐºÐ¾ÑÐ¾ÑÑÐµ ÑÐµÑÐ°Ð»Ð¸ÑÑ Ð² ÑÐ¾Ð´Ðµ ÑÐ°Ð±Ð¾ÑÑ: 1. ÐÑÑÐ»ÐµÐ´Ð¾Ð²Ð°Ð½Ð¸Ðµ ÑÑÑÐµÑÑÐ²ÑÑÑÐ¸Ñ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð¾Ð² Ð¸ Ð¼ÐµÑÐ¾Ð´Ð¾Ð² Ð¾Ð±ÑÐ°Ð±Ð¾ÑÐºÐ¸ ÑÐ¸Ð³Ð½Ð°Ð»Ð¾Ð². 2. Ð Ð°Ð·ÑÐ°Ð±Ð¾ÑÐºÐ° Ð¸ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ñ ÑÑÑÑÐºÑÑÑÑ ÐºÐ¾Ð½Ð²ÐµÐ¹ÐµÑÐ° Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ°. 3. ÐÑÐ¾ÐµÐºÑÐ¸ÑÐ¾Ð²Ð°Ð½Ð¸Ðµ Ð¾ÑÐ½Ð¾Ð²Ð½ÑÑ Ð±Ð»Ð¾ÐºÐ¾Ð² Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ°: ÐºÐ¾Ð½Ð²ÐµÐ¹ÐµÑ, Ð¿Ð°Ð¼ÑÑÑ Ð´Ð°Ð½Ð½ÑÑ, ÑÐµÐ³Ð¸ÑÑÑÐ¾Ð²Ð°Ñ Ð¿Ð°Ð¼ÑÑÑ, ÑÐ¿ÑÐ°Ð²Ð»ÑÑÑÐµÐµ ÑÑÑÑÐ¾Ð¹ÑÑÐ²Ð¾. 4. Ð¢ÐµÑÑÐ¸ÑÐ¾Ð²Ð°Ð½Ð¸Ðµ Ð¸ Ð¾ÑÐ»Ð°Ð´ÐºÐ° ÑÐµÐ°Ð»Ð¸Ð·Ð¾Ð²Ð°Ð½Ð½ÑÑ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð¾Ð². 5. Ð Ð°Ð·ÑÐ°Ð±Ð¾ÑÐºÐ° Ð°Ð²ÑÐ¾Ð¼Ð°ÑÐ¸Ð·Ð°ÑÐ¸Ð¸ Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ°. 6. ÐÑÐµÐ½ÐºÐ° ÑÐµÑÑÑÑÐ¾Ð² Ð¸ Ð±ÑÑÑÑÐ¾Ð´ÐµÐ¹ÑÑÐ²Ð¸Ñ Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ°. Ð Ð¿ÑÐ¾ÑÐµÑÑÐµ Ð¿ÑÐ¾ÐµÐºÑÐ¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ Ð¾Ð¿ÑÐµÐ´ÐµÐ»ÐµÐ½Ñ: ÑÑÐµÐ±Ð¾Ð²Ð°Ð½Ð¸Ñ Ðº ÐºÐ°Ð¶Ð´Ð¾Ð¹ ÑÐ°Ð·Ðµ ÐºÐ¾Ð½Ð²ÐµÐ¹ÐµÑÐ°, ÑÐ°Ð±Ð¾ÑÐ° ÑÐµÐ³Ð¸ÑÑÑÐ¾Ð² Ð°Ð´ÑÐµÑÐ°ÑÐ¸Ð¸, ÑÐ¾ÑÐ¼Ð°ÑÑ ÐºÐ¾Ð¼Ð°Ð½Ð´. Ð¡Ð±Ð°Ð»Ð°Ð½ÑÐ¸ÑÐ¾Ð²Ð°Ð½Ñ Ð¿Ð¾ Ð²ÑÐµÐ¼ÐµÐ½Ð¸ Ð²ÑÐ¿Ð¾Ð»Ð½ÐµÐ½Ð¸Ñ ÑÐ°Ð·Ñ ÐºÐ¾Ð½Ð²ÐµÐ¹ÐµÑÐ°. Ð ÑÐ°Ð±Ð¾ÑÐµ Ð¿ÑÐµÐ´ÑÑÐ°Ð²Ð»ÐµÐ½Ñ Ð¾Ð¿Ð¸ÑÐ°Ð½Ð¸Ñ Ð¿ÑÐ¾ÑÐ¾ÑÐ¸Ð¿Ð¾Ð² Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ° Ð¿Ð¾ Ð¿Ð°ÑÐ°Ð¼ÐµÑÑÐ°Ð¼, ÐºÐ¾ÑÐ¾ÑÑÐµ Ð²ÐºÐ»ÑÑÐ°ÑÑ Ð² ÑÐµÐ±Ñ ÑÐ°Ð·ÑÑÐ´Ð½Ð¾ÑÑÑ Ð¸ Ð¾Ð±ÑÐµÐ¼ Ð¿Ð°Ð¼ÑÑÐ¸, Ð¿Ð¾ÐºÐ°Ð·ÑÐ²Ð°ÑÑÐ¸Ðµ, ÑÑÐ¾ Ð¸Ñ ÑÐ°ÑÐ°ÐºÑÐµÑÐ¸ÑÑÐ¸ÐºÐ¸ ÑÐ¾Ð¿Ð¾ÑÑÐ°Ð²Ð¸Ð¼Ñ Ñ ÑÑÑÐµÑÑÐ²ÑÑÑÐ¸Ð¼Ð¸ ÑÐµÑÐµÐ½Ð¸ÑÐ¼Ð¸. ÐÑÐµÐ´Ð»Ð¾Ð¶ÐµÐ½Ð½ÑÐ¹ Ð²Ð°ÑÐ¸Ð°Ð½Ñ Ð°Ð²ÑÐ¾Ð¼Ð°ÑÐ¸Ð·Ð°ÑÐ¸Ð¸ Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ ÑÐµÐ°Ð»Ð¸Ð·Ð¾Ð²Ð°Ð½ Ð² Ð²Ð¸Ð´Ðµ Ð²ÐµÑÑÐ¸Ð¸, Ð²ÐºÐ»ÑÑÐ°ÑÑÐ¸Ð¹ Ð¸Ð½ÑÐµÑÑÐµÐ¹Ñ Ð¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°ÑÐµÐ»Ñ, Ð·Ð°Ð´Ð°Ð½Ð¸Ðµ Ð¿Ð°ÑÐ°Ð¼ÐµÑÑÐ¾Ð² Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð¾Ð² Ð¸ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ñ Ð³ÐµÐ½ÐµÑÐ°ÑÐ¸Ð¸ Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ð½Ð¾Ð³Ð¾ ÐºÐ¾Ð´Ð°.
description: This work is devoted to the design of prototypes of a digital signal processor on an FPGA using the SystemVerilog description language. Problems that were solved during the work: 1. Research of existing algorithms and methods of signal processing. 2. Design and implementation of the processor pipeline structure. 3. Design of processor blocks. 4. Testing and debugging of implemented algorithms. 5. Development of automation of processor programming. 6. Evaluation of processor resources and speed. During the design process, the requirements for each phase of the pipeline, the operation of addressing registers, and command formats were determined. The pipeline phases are balanced in terms of execution time. The paper presents descriptions of processor prototypes based on parameters that include the bit depth and memory size of data and programs, which show that their characteristics are comparable to existing solutions. The proposed option for programming automation is implemented in the form of a version that includes a user interface and setting algorithm parameters and program code generation algorithms.