D7.4: Best Practices Guides for New and Emerging Architectures
Creators: name: Weinberg, Volker
name: Lührs, Sebastian
name: Rijks, Wim
name: Saastad, Ole W.
name: Sloan, Terence
name: Sloan-Murphy, Dominic
name: Van Leeuwen, Caspar
Publisher: name: Zenodo
Year: 2019
Subjects: Deliverable
HPC
Research infrastructure
Best practice guide
Parallel I/O
ARM64
AMD EPYC
Deep learning

description: The Work Package 7 ‘Application Enabling and Support’ provides applications enabling services for HPC applications codes that are important for European academic and/or industrial researchers to ensure that these applications can effectively exploit current and future PRACE systems. Applications are selected for enabling via the PRACE Preparatory Access (PA) or the SHAPE programme. In addition to this enabling work on existing systems, the Work Package progresses the technical work needed to ensure that key applications are able to use future PRACE and EuroHPC (Pre-) Exascale systems, and investigates the tools and techniques needed to exploit such Exascale systems. Contribution to the development of numerical libraries for heterogeneous/hybrid architectures, and adoption of such libraries in community codes is a new goal in PRACE-5IP. Beyond directly working on improving applications and libraries, one of the main objectives of the Work Package is to support European HPC research communities through the provision of Best Practice Guides, benchmarks, and technical results in White Papers.<br> The successful series of Best Practice Guides has been already initiated in PRACE-1IP and has been continuously extended since then: PRACE-1IP provided four Best Practice Guides for PRACE Tier-0 systems (JUGENE, Curie, Cray XE and IBM Power) that cover programming techniques, compilers, tools and libraries. PRACE-2IP added a generic guide about the x86 architecture and a Best Practice Guide for the SuperMUC system, together with a series of seven Best Practice Mini-Guides for other architectures which are important at Tier-1 to allow European researchers to make efficient use of these systems. PRACE-3IP supplemented these with Best Practice Guides about Intel Xeon Phi, Blue Gene/Q and IBM Power 775 and provided updates of the Curie and the Cray XE guide, which was renamed into Cray XE/XC. PRACE-4IP Task 7.3.B added new guides about Knights Landing and Haswell/Broadwell and provided updates of the Intel® Xeon Phi™ and the GPGPU Best Practice Guides. Finally, PRACE-5IP Task 7.3B added six new Best Practice Guides about the processors AMD EPYC and ARM64, Deep Learning in HPC, HPC for Data Science on the Cray Urika, Modern Interconnects and Parallel I/O.<br> Topics for these Best Practice Guides include: a short description of the processor architecture, optimal porting of applications (e.g., choice of numerical libraries and compiler options); architecture specific optimisation and scaling techniques; optimal system environment (e.g., tuneable system parameters, job placement and optimised system libraries); debugging tools, performance analysis tools and programming environment.<br> This report describes the process which led to the Best Practice Guides and the structure of the guides. For the Best Practice Guides itself we refer to the online versions on the PRACE RI web site.