title: Ð¢ÐµÑ Ð½Ð¾Ð»Ð¾Ð³Ð¸Ñ ÑÐ¿Ð°ÐºÐ¾Ð²ÐºÐ¸ Ð±Ð¸ÑÐ¾Ð²ÑÑ Ð¿Ð¾Ð»ÐµÐ¹ Ð² Ð²ÑÑÐ¾ÐºÐ¾ÑÑÐ¾Ð²Ð½ÐµÐ²Ð¾Ð¼ ÑÐ¸Ð½ÑÐµÐ·Ðµ Ð°Ð¿Ð¿Ð°ÑÐ°ÑÐ½Ð¾Ð³Ð¾ ÑÑÐºÐ¾ÑÐ¸ÑÐµÐ»Ñ
title: Ð²ÑÐ¿ÑÑÐºÐ½Ð°Ñ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð±Ð°ÐºÐ°Ð»Ð°Ð²ÑÐ°
titleType: Subtitle
title: Bit field packing technology in high-level synthesis of hardware accelerator
Creators: name: ÐÐ°Ð»ÑÑÐµÐ½ÐºÐ¾, ÐÐ¸ÑÐ°Ð¸Ð»
Publisher: name: Ð¡Ð°Ð½ÐºÑ-ÐÐµÑÐµÑÐ±ÑÑÐ³ÑÐºÐ¸Ð¹ Ð¿Ð¾Ð»Ð¸ÑÐµÑÐ½Ð¸ÑÐµÑÐºÐ¸Ð¹ ÑÐ½Ð¸Ð²ÐµÑÑÐ¸ÑÐµÑ ÐÐµÑÑÐ° ÐÐµÐ»Ð¸ÐºÐ¾Ð³Ð¾
Year: 2022
Subjects: Ð²ÑÑÐ¾ÐºÐ¾ÑÑÐ¾Ð²Ð½ÐµÐ²ÑÐ¹ ÑÐ¸ÑÑÐ¾Ð²Ð¾Ð¹ ÑÐ¸Ð½ÑÐµÐ·
ÑÐ·ÑÐº Ð¾Ð¿Ð¸ÑÐ°Ð½Ð¸Ñ Ð°Ð¿Ð¿Ð°ÑÐ°ÑÑÑÑ
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Ð²ÑÐ´ÐµÐ»ÐµÐ½Ð¸Ðµ Ð¸ Ð¿ÑÐ¸Ð²ÑÐ·ÐºÐ° ÑÐµÐ³Ð¸ÑÑÑÐ¾Ð²
high-level synthesis
hardware description language
fpga
compiler
register allocation and binding

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description: The development of digital circuitsontheregister transferlevel can be performed automatically basedona behavioral description in a high-level programming language. At the same time, there is a problem of the efficiency of using the hardware resources of the target computing platform, in particular the register memory of programmable logic devices. The aim of the work is to develop an algorithm for minimizing the number of registers used in the process of high-level digital synthesis of a hardware function accelerator. The result of the work is the implementation of register allocation optimization technology within the existing high-level synthesis system.The results of the work can be used in the development and verification of ICS at the register transfer level with their further implementation in programmable logic devices.