<b>Probabilistic Computing Through Integrated Spintronic Nanodevices</b>
Creators: name: Daniel, John Arnesh Divakaruni
Publisher: name: Purdue University Graduate School
Year: 2025
Subjects: classificationCode: 401804
subject: Nanoelectronics
classificationCode: 401805
subject: Nanofabrication, growth and self assembly
classificationCode: 401807
subject: Nanomaterials
classificationCode: 401810
subject: Nanoscale characterisation
classificationCode: 401899
subject: Nanotechnology not elsewhere classified
classificationCode: 510404
subject: Electronic and magnetic properties of condensed matter; superconductivity
classificationCode: 510499
subject: Condensed matter physics not elsewhere classified

description: Probabilistic computing is a novel computing scheme that offers a more efficient approach than conventional complimentary metal-oxide-semiconductor (CMOS)-based logic in a variety of applications ranging from Bayesian inference to combinatorial optimization, and invertible Boolean logic. These applications, which have found use in the rapidly growing fields of machine learning and artificial intelligence, are traditionally computationally-intensive and so make the push for novel computing schemes that are intrinsically low-power and scalable all the more urgent.The probabilistic bit (or p-bit, the base unit of probabilistic computing) is a naturally fluctuating entity that requires <i>tunable </i>stochasticity; low-barrier nanomagnets, in which the magnetic moment fluctuates randomly and continuously due to the presence of thermal energy, are a natural vehicle for providing the core functionality required. This dissertation describes the work done in mining the rich field of spintronics to produce devices that can act as natural hardware accelerators for probabilistic computing algorithms.First, experiments exploring Fe<sub>3</sub>O<sub>4</sub> nanoparticles as naturally stochastic systems are presented. Using NV center measurements on an array of such nanoparticles, it is shown that they fluctuate intrinsically at GHz frequencies at room temperature; these fluctuations could be harnessed to act as a stochastic noise source, and would, in principle, enable fast computation.The focus then shifts to the development of a platform that allows for easier <i>electrical</i> readout: the low-barrier magnetic tunnel junction (MTJ). We show the work done in the development and characterization of these devices, how they respond to non-ideal environments, such as elevated temperatures and exposure to high-energy electromagnetic radiation, how their intrinsic stochasticity might be tuned with electrical currents and external magnetic fields, and then how these might be integrated with a simple transistor circuit to produce a compact low-energy implementation of a p-bit.Next, by integrating our stochastic MTJs with 2D-MoS<sub>2</sub><sup> </sup>field-effect transistors (FETs), the first <i>on-chip </i>realization of a key p-bit building block, displaying voltage-controllable stochasticity, is demonstrated. This is followed by another key demonstration through the fabrication of stochastic MTJs directly on top of an integrated circuit platform, where the transistor circuitry is provided by 180nm-node CMOS technology.In addition, supported by circuit simulations, this work provides a careful device-level analysis of the three transistor-one magnetic tunnel junction (3T-1MTJ) p-bit design, evaluating how the characteristics of each component can influence the overall p-bit’s output. In particular, we show that – against common wisdom – a large tunnel magnetoresistance (TMR) is not the best choice for p-bits; bimodal telegraphic fluctuations are highly undesirable and are a sign of a slow device; and an ideal inverter with a large gain is unsuitable for p-bit applications due to the higher likelihood of unwanted plateaus in the resulting p-bit’s output.This analysis is extended to consider the impact of such non-ideal p-bits when used to construct probabilistic circuits, with the focus on the emulation of the Boolean logic AND gate through a three p-bit correlated system. It is found that a probabilistic circuit made with ideal p-bits can accurately emulate the function of an AND gate, while the non-ideal p-circuits suffer from an increased error rate in emulating the AND gate’s truth table.The understanding gained at the individual device level, in what makes a good or bad MTJ, to how the different components of the 3T-1MTJ p-bit can affect its output, and subsequently how non-ideal p-bits can impact circuit performance, can be important for the future realization of scaled on-chip p-bit networks.