The synthesis of silicon and germanium nanowires for energy storage and single nanowire devices
Creators: name: Storan, Dylan
Publisher: name: University of Limerick
Year: 2023
Subjects: subject: Chemical sciences
subject: FOS: Chemical sciences

description: The work presented in this thesis describes the bottom-up synthesis of Si and Ge nanowires for use as both anode materials for Li-ion batteries, and as channels in field effect transistors. The results are arranged as research articles with introductory summaries at the beginning of each chapter. For use as an anode material, Si boasts a superior capacity compared to graphite, which is the current anode material used in state-of-the-art batteries. Si is a Li-alloying material, which allows for the improved capacity compared to the intercalation-based graphite. However, the formation of Li-rich Si alloys results in huge volume expansion and contraction (~300%) during the charge and discharge processes leading to material pulverization. Fortunately, Si in NW form is better able to accommodate the large volume expansion and contraction and its associated negative effects. While Si NWs show promise as next generation Li-ion battery anodes, Si NW synthesis protocols are expensive and are limited by the low Si content achievable per anode. These low active mass loadings lead to low areal capacities, hindering the application of Si NWs in commercial Li-ion batteries. Chapter 3 of this thesis describes the synthesis of Si NWs directly on a high surface area. flexible carbon cloth current collector. The study demonstrates that the high surface area of the carbon cloth allows for more nucleation sites for Si NW growth and higher mass loadings. This results in significantly higher areal capacities compared to Si NWs grown on planar stainless steel substrates. The Si NWs grown on carbon cloth exhibited high areal capacities of &gt;2 mAh/cm2 and a capacity retention of 80% after 200 cycles. Si and Ge are traditionally more associated with transistor-based applications. This is due to the fact that Si and Ge are semiconductors with conductivities between that of a metal and an insulator. The conductivity of a semiconductor can be tuned by adding trace amounts of impurities. This is known as doping. Furthermore, these doped semiconductors are used in metal-oxide-semiconductor field-effect-transistors (MOSFETs). In this configuration, the conductivity of the semiconductor can be modulated by the presence of a voltage applied to the gate terminal. Current transistors are fabricated by top-down lithographic technologies. However, as we approach lithographic resolution limits, alternate fabrication methods must be considered. Bottom-up NW synthetic protocols are not hindered by such resolution limits. Bottom-up synthesis techniques are hindered however by non-conormal doping protocols, as well as seed metal contamination of the NW. In Chapter 4, the concept of selectively choosing the metal seed catalyst to simultaneously synthesize and dope Ge NWs is explored. In and Bi catalysts (P-type and N-type, respectively), are chosen with the aim of taking advantage of seed metal incorporation to dope Ge NWs. We demonstrate through complimentary elemental and electronic analysis that In and Bi seeded Ge NWs are doped with metal seed catalyst atoms. Furthermore, Bi seeded Ge NWs were so heavily doped that they could not be gated, while In seeded Ge NWs exhibited switch-like ehaviour in MOSFET configuration. Chapter 5 describes the exploration of selectively doping Si NWs using an In seed catalyst. It was revealed that In seeded Si NWs were degenerately doped with In and could not be gated. However, SnIn alloy seeded Si NWs exhibited a 60% reduction in In dopant density as determined by electron dispersive X-ray spectroscopy (EDS). Subsequent MOSFET devices fabricated from SnIn alloy seeded Si NWs could be gated, with increased resistances observed at high gate voltages This chapter showcases control over seed catalyst mediated doping of Si NWs. Chapter 6 explores the concept of doping of Si and Ge NWs by selectively choosing a dopant growth substrate (Al) for NW growth. While EDS analysis revealed only background levels of Al present in the NW bodies, single NW device fabrication revealed significantly reduced resistivities of Si and Ge NWs grown on Al foil, compared to intrinsic NWs. The reduced resistivities of NWs grown on Al foil provides evidence for Al incorporation from the substrate through the NW during growth. This study opens the door for substrate mediated doping of Si and Ge NWs. It must be emphasized that the doping protocols explored in this thesis are not yet competitive with current-day semiconductor protocols. However, a significant gap in the influence of seed and substrate incorporation on NW electrical characteristics remains. Chapters 4, 5 and 6 of this thesis aim to bridge some of this gap. <br>