Design and Test of Imaging and Particle Detection Microelectronic System for Frontier Research Applications
Creators: name: RICEPUTI, Elisa
Publisher: name: Universit� degli studi di Bergamo
Year: 2018

description: Over the last decades, the use of CMOS integrated circuits has largely diffused in many different fields and, in particular, in the readout of radiation detectors. Among the advantages of an integrated CMOS technology, high integration density, capability of handling large data rates, small form factor and last but not least, high radiation resistance are crucial to meet the demanding specifications of modern physics experiments using high granularity detectors.
In a well studied realization of an analog readout channel for a radiation detector, three foundamentals steps are needed:
- 1 - characterization of the CMOS nanoscale technology that will be adopted to design the analog channel;
- 2 - desing and simulation of the circuit;
- 3 - characterization and validation of the final chip.
Nanoscale CMOS technology are provided with detailed models capable of perfectly describing the behavior of the transistors for digital applications. Models describing transistors characteristics for analog applications can be not so accurate as far as noise and radiation effects are concerned. In particular noise characteristics, and above all flicker noise, are stongly dependent on the technology, thus an in-depth characterization is needed. Moreover, normally, there are no information regarding the radiation hardness of the technology, thus a detailed analysis at the expected radiation doseis needed depending on the scope of the electronic readout.
Once these peculiar aspects of the chosen technology are defined and analyzed, it is possible to move forward to the second step: design and simulate the circuit meeting the specifications required from the application.
Last but not least, there is the characterization and the validation of the final chip. This step has the goal of verifying the correct functioning of the system. Such phase could also highlight some problems of the designed circuits that ideal simulation did not point out, so that the designers will be able to cope such with defects in the following production steps.
Usually, chip development is not carried out only by one work group, but with a collaboration of different Universities and Institutions. In this thesis, all these steps were taken into account for three different projects: RD53, GAPS and DSSC. All these 3 projects require the design and test of custom integrated circuit for the readout of silicon pixel or strip detectors, with avdanced analog signal processing features providing a low noise performance. Additional requirements such as radiation hardness may depending on the application, as discussed in the following chapters.
In particular, the first part of the work provides an extensive analysis of total dose effects in devices belonging to a commercial 65 nm and 110 nm CMOS process, in the context of designing rad-hard analog integrated circuits for front-end applications in future colliders. This activity has been carried out in the framework of the RD53 collaboration. The aim of this project is to design the next generation of hybrid pixel readout chips for the silicon vertex inner tracker of the ATLAS and CMS detectors of the Lrge Hadron collider (LHC) at CERN facility.
The second part of the work concerns the design of the analog reading channel of a novel cosmic antideuteron detector. This work is carried out for the GAPS project that has the aim to realize a novel approach for indirect dark matter searches. NASA approved GAPS's proposal in September 2016. GAPS experiments is the result of the collaboration of different Universities and Institutes, e.g. MIT, UCLA, INFN and others. The balloon launch is expected by the end of year 2020 from the McMurdo station in Antarctica.
The third part of the work regards the characterization of silicon pixel detectors for DSSC project at European XFEL. The last part of this thesis presents the characterization of the readout ASIC functionality and the backside current of the first and second prototype of the bare modules of such project.