title: ÐÐ½Ð°Ð»Ð¾Ð³Ð¾-ÑÐ¸ÑÑÐ¾Ð²Ð¾Ð¹ Ð¿ÑÐµÐ¾Ð±ÑÐ°Ð·Ð¾Ð²Ð°ÑÐµÐ»Ñ Ð¿Ð¾ÑÐ»ÐµÐ´Ð¾Ð²Ð°ÑÐµÐ»ÑÐ½Ð¾Ð³Ð¾ Ð¿ÑÐ¸Ð±Ð»Ð¸Ð¶ÐµÐ½Ð¸Ñ Ñ ÑÐ¼ÐµÐ½ÑÑÐµÐ½Ð½ÑÐ¼ ÐºÐ¾Ð»Ð¸ÑÐµÑÑÐ²Ð¾Ð¼ ÑÐ»ÐµÐ¼ÐµÐ½ÑÐ¾Ð² Ð² Ð¼Ð°ÑÑÐ¸ÑÐµ ÐºÐ¾Ð½Ð´ÐµÐ½ÑÐ°ÑÐ¾ÑÐ¾Ð²
title: Ð²ÑÐ¿ÑÑÐºÐ½Ð°Ñ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð±Ð°ÐºÐ°Ð»Ð°Ð²ÑÐ°
titleType: Subtitle
title: A SAR ADC with a reduced number of elements in the capacitor network
Creators: name: Ð¦ÑÑÐ¸Ð½Ð¾Ð²Ð°, ÐÐ»ÑÐ°Ð½Ð°
Publisher: name: Ð¡Ð°Ð½ÐºÑ-ÐÐµÑÐµÑÐ±ÑÑÐ³ÑÐºÐ¸Ð¹ Ð¿Ð¾Ð»Ð¸ÑÐµÑÐ½Ð¸ÑÐµÑÐºÐ¸Ð¹ ÑÐ½Ð¸Ð²ÐµÑÑÐ¸ÑÐµÑ ÐÐµÑÑÐ° ÐÐµÐ»Ð¸ÐºÐ¾Ð³Ð¾
Year: 2021
Subjects: Ð°Ð½Ð°Ð»Ð¾Ð³Ð¾-ÑÐ¸ÑÑÐ¾Ð²Ð¾Ð¹ Ð¿ÑÐµÐ¾Ð±ÑÐ°Ð·Ð¾Ð²Ð°ÑÐµÐ»Ñ (ÐÐ¦Ð)
ÑÐ¸ÑÑÐ¾-Ð°Ð½Ð°Ð»Ð¾Ð³Ð¾Ð²ÑÐ¹ Ð¿ÑÐµÐ¾Ð±ÑÐ°Ð·Ð¾Ð²Ð°ÑÐµÐ»Ñ (Ð¦ÐÐ)
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successive approximation register analog-to-digital converter (SAR ADC)
digital-to-analog converter (DAC)
comparator
circuit on switchable capacitors
logic circuits
DNL
INL

description: Ð¦ÐµÐ»ÑÑ Ð´Ð°Ð½Ð½Ð¾Ð¹ ÑÐ°Ð±Ð¾ÑÑ ÑÐ²Ð»ÑÐµÑÑÑ ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐºÐ° ÐÐ¦Ð Ð¿Ð¾ÑÐ»ÐµÐ´Ð¾Ð²Ð°ÑÐµÐ»ÑÐ½Ð¾Ð³Ð¾ Ð¿ÑÐ¸Ð±Ð»Ð¸Ð¶ÐµÐ½Ð¸Ñ Ñ ÑÐ¼ÐµÐ½ÑÑÐµÐ½Ð½ÑÐ¼ ÐºÐ¾Ð»Ð¸ÑÐµÑÑÐ²Ð¾Ð¼ ÑÐ»ÐµÐ¼ÐµÐ½ÑÐ¾Ð² Ð² Ð¼Ð°ÑÑÐ¸ÑÐµ ÐºÐ¾Ð½Ð´ÐµÐ½ÑÐ°ÑÐ¾ÑÐ¾Ð² Ð¦ÐÐ. Ð Ð°Ð·ÑÐ°Ð±Ð¾ÑÐ°Ð½ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼ Ð¿ÐµÑÐµÐºÐ»ÑÑÐµÐ½Ð¸Ð¹ ÑÐ»ÐµÐ¼ÐµÐ½ÑÐ¾Ð² Ð¼Ð°ÑÑÐ¸ÑÑ Ð¦ÐÐ, Ð¿Ð¾Ð·Ð²Ð¾Ð»ÑÑÑÐ¸Ð¹ Ð¸ÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°ÑÑ Ð¼ÐµÐ½ÑÑÐµÐµ ÐºÐ¾Ð»Ð¸ÑÐµÑÑÐ²Ð¾ ÐºÐ¾Ð½Ð´ÐµÐ½ÑÐ°ÑÐ¾ÑÐ¾Ð². ÐÐ°Ð½Ð½ÑÐ¹ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼ ÑÐµÐ°Ð»Ð¸Ð·Ð¾Ð²Ð°Ð½ Ð² ÑÑÐµÐ´Ðµ Matlab. Ð¡Ð¾Ð·Ð´Ð°Ð½Ð° Ð¼Ð¾Ð´ÐµÐ»Ñ ÐÐ¦Ð Ð¿Ð¾ÑÐ»ÐµÐ´Ð¾Ð²Ð°ÑÐµÐ»ÑÐ½Ð¾Ð³Ð¾ Ð¿ÑÐ¸Ð±Ð»Ð¸Ð¶ÐµÐ½Ð¸Ñ Ð² ÑÑÐµÐ´Ðµ Matlab Simulink Ð´Ð»Ñ Ð¿ÑÐ¾Ð²ÐµÑÐºÐ¸ ÑÐ°Ð±Ð¾ÑÐ¾ÑÐ¿Ð¾ÑÐ¾Ð±Ð½Ð¾ÑÑÐ¸ Ð¿ÑÐµÐ´Ð»Ð¾Ð¶ÐµÐ½Ð½Ð¾Ð³Ð¾ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð°. Ð ÑÐµÐ·ÑÐ»ÑÑÐ°ÑÐµ Ð²ÑÐ¿Ð¾Ð»Ð½ÐµÐ½Ð½Ð¾Ð¹ ÑÐ°Ð±Ð¾ÑÑ Ð´Ð»Ñ Ð´ÐµÑÑÑÐ¸ÑÐ°Ð·ÑÑÐ´Ð½Ð¾Ð³Ð¾ ÐÐ¦Ð ÑÐ´Ð°Ð»Ð¾ÑÑ ÑÐ¼ÐµÐ½ÑÑÐ¸ÑÑ ÐºÐ¾Ð»Ð¸ÑÐµÑÑÐ²Ð¾ ÑÐ»ÐµÐ¼ÐµÐ½ÑÐ¾Ð² Ð¼Ð°ÑÑÐ¸ÑÑ ÐºÐ¾Ð½Ð´ÐµÐ½ÑÐ°ÑÐ¾ÑÐ¾Ð² Ð¦ÐÐ Ð² 2,5 ÑÐ°Ð·Ð° Ð¿Ð¾ ÑÑÐ°Ð²Ð½ÐµÐ½Ð¸Ñ Ñ ÑÑÑÐµÑÑÐ²ÑÑÑÐ¸Ð¼Ð¸ Ð¿Ð¾Ð´Ð¾Ð±Ð½ÑÐ¼Ð¸ ÑÐµÑÐµÐ½Ð¸ÑÐ¼Ð¸. ÐÐ¾ ÑÐµÐ·ÑÐ»ÑÑÐ°ÑÐ°Ð¼ ÑÐ°Ð±Ð¾ÑÑ Ð´ÐµÑÑÑÐ¸ÑÐ°Ð·ÑÑÐ´Ð½Ð¾Ð¹ Ð¼Ð¾Ð´ÐµÐ»Ð¸ Ð±ÑÐ»Ð¸ Ð¿Ð¾ÑÑÑÐ¾ÐµÐ½Ñ ÑÐ°ÑÐ°ÐºÑÐµÑÐ¸ÑÑÐ¸ÐºÐ° Ð¿ÑÐµÐ¾Ð±ÑÐ°Ð·Ð¾Ð²Ð°Ð½Ð¸Ñ, Ð¸Ð½ÑÐµÐ³ÑÐ°Ð»ÑÐ½Ð°Ñ Ð¸ Ð´Ð¸ÑÑÐµÑÐµÐ½ÑÐ¸Ð°Ð»ÑÐ½Ð°Ñ Ð½ÐµÐ»Ð¸Ð½ÐµÐ¹Ð½Ð¾ÑÑÐ¸.
description: The object of this work is to develop a SAR ADC with a reduced number of elements in the DAC capacitor network. An algorithm for switching the elements of the DAC network is developed, which allows using a smaller number of capacitors. This algorithm is implemented in the Matlab environment. The efficiency of the proposed algorithm is confirmed by the created model of the SAR ADC in the Matlab Simulink environment. As a result of the work performed for a ten-bit ADC, it was possible to reduce the number of elements of the DAC capacitor network by 2.5 times compared to existing similar solutions. Based on the results of the ten-bit model, transfer curve, INL and DNL were plotted.