D9.3.4: Final Report on Prototype Evaluation
Creators: name: Johnsson, Lennart
name: Netzer, Gilbert
Publisher: name: Zenodo
Year: 2013
Subjects: Deliverable
HPC
Research infrastructure

description: This report supplements deliverable D9.3.3 and covers future technology prototype<br> efforts from March 2013. Three prototype efforts not reported on in D9.3.3 are fully reported<br> here: the ARM based NVidia Tegra3 with NVidia Kepler GPU acceleration prototype at BSC;<br> the energy recovery prototype using immersive cooling techniques at PSNC; and the results<br> from the Advanced Multi-level Fault Tolerant prototype. Additional results are provided for<br> the x86+GPU prototype at CaSToRC, the DSP prototype at SNIC/KTH, and the energy<br> recovery prototype at LRZ.<br> The DSP results show that for the benchmarks that were well optimised the observed energy<br> efficiency for the DSP was in line with the nominal energy efficiency that can be derived<br> from specifications. Thus, the energy efficiency is comparable to that of GPUs and better than<br> that of x86 CPUs. Furthermore, the DSP does not require a host processor. In fact, the 40 nm<br> DSP used is, for the optimised benchmarks, more energy efficient than correspondingly<br> optimised codes for the 22 nm Intel Ivy Bridge. ARM Coretx-A9 CPUs are not energy<br> efficient for HPC workloads, but nodes using powerful and energy efficient acceleration, such<br> as the NVidia Kepler, can form part of a viable HPC node. Due to late delivery of the relevant<br> prototype only preliminary results are available at this time.<br> The shared memory prototype is based on standard x86 servers and a node add-in card for<br> cache coherency. This prototype clearly demonstrated that, though a very large shared<br> memory address space is supported, it is a NUMA architecture and paying proper attention to<br> the memory architecture is necessary for good performance.<br> One of the lessons learnt in the project is that delivering energy efficiency advantages for<br> architectures different from x86 architectures requires well-optimised codes also for the non-<br> x86 architectures, i.e. for significant energy efficiency gains at the application level resource<br> use needs to be at a level comparable to that for x86 architectures. High resource utilization<br> requires detailed understanding of the alternative architectures as well as developing or<br> inventing new programming methodologies and techniques in a less-rich software ecosystem<br> than that available for x86 architectures today. It also became apparent that quality energy<br> efficiency assessment adds significant complexity to benchmarking, in that instrumentation<br> and measurement technologies as well a good understanding of applications and system<br> behaviours are all necessary.<br> For the energy recovery approach assessed by the LRZ prototype it was demonstrated that a<br> 20% energy recovery could be achieved even for the partially hot-water liquid cooled system<br> Valuable insights were also gained into how the approach used can be improved for increased<br> energy recovery. The immersive cooling prototype at PSNC exposed some of the many<br> engineering issues in integrating new cooling technologies in a data centre setting.<br> The Advanced Multi-level Fault Tolerant approach to checkpoint/restart was demonstrated to<br> have good scalability and sufficiently low overhead to allow for frequent checkpointing even<br> at a large scale.