VP23-05 Research and Design of Hierarchical Cache with Mixed SOT- and STT-MRAM in Multi-core CPU Environments
Creators: Yulei Dai and Yanfeng Jiang
Publisher: name: IEEE
Year: 2025

In modern CPU system, the number of computational cores is increased, which can effectively enhance the computing capability. However, the performance gained from on-chip caches in single-core versus multi-core scenarios is not always linearly increased. Substituting static random-access memory (SRAM) with magnetic random-access memory (MRAM) in computational systems can improve cache performance since MRAM shows the merits of low power, non-volatile and high density, etc.. In this paper, based on the Reduced Instruction Set Computer-Five (RISC-V) instruction set framework, a novel simulation strategy is employed to evaluate the performance of a multi-core hybrid cache system (L1, L2, and L3 caches). By comparing the performance of Spin-Transfer Torque MRAM (STT-MRAM), Spin-Orbit Torque MRAM (SOT-MRAM), and SRAM in a multi-core environment, an octa-core CPU system with a three-tier cache structure is proposed, in which SOT-MRAM and STT-MRAM are used to replace L2 and L3 caches, respectively. Additionally, the cache coherence protocol of the optimized architecture is tailored for magnetic memory components in an eight-core CPU system. Simulation results demonstrate that this hybrid cache system achieves 54.96% leakage power savings and 22.53% overall power savings compared to SRAM. The evaluation of the hybrid cache system aligns closely with real-world requirements and exhibits scalability.References: [1]Saha, Rajesh, Yogendra Pratap Pundir, and Pankaj Kumar Pal. "Comparative analysis of STT and SOT based MRAMs for last level caches." Journal of Magnetism and Magnetic Materials 551 (2022): 169161. [2]F. Hameed and J. Castrillon, “A novel hybrid DRAM/STT-RAM last-level-cache architecture for performance, energy, and endurance enhancement,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 27, no. 10, pp. 2375–2386, Oct. 2019. [3]E. Cheshmikhani, H. Farbeh and H. Asadi, "A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches," in IEEE Transactions on Reliability, vol. 69, no. 2, pp. 594-610, June 2020, doi: 10.1109/TR.2019.2923258. [4]Gao, L., Wang, R., Xu, Y. et al. SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU–GPU heterogeneous architectures. J Supercomput 74, 3388–3414 (2018).
In modern CPU system, the number of computational cores is increased, which can effectively enhance the computing capability. However, the performance gained from on-chip caches in single-core versus multi-core scenarios is not always linearly increased. Substituting static random-access memory (SRAM) with magnetic random-access memory (MRAM) in computational systems can improve cache performance since MRAM shows the merits of low power, non-volatile and high density, etc.. In this paper, based on the Reduced Instruction Set Computer-Five (RISC-V) instruction set framework, a novel simulation strategy is employed to evaluate the performance of a multi-core hybrid cache system (L1, L2, and L3 caches). By comparing the performance of Spin-Transfer Torque MRAM (STT-MRAM), Spin-Orbit Torque MRAM (SOT-MRAM), and SRAM in a multi-core environment, an octa-core CPU system with a three-tier cache structure is proposed, in which SOT-MRAM and STT-MRAM are used to replace L2 and L3 caches, respectively. Additionally, the cache coherence protocol of the optimized architecture is tailored for magnetic memory components in an eight-core CPU system. Simulation results demonstrate that this hybrid cache system achieves 54.96% leakage power savings and 22.53% overall power savings compared to SRAM. The evaluation of the hybrid cache system aligns closely with real-world requirements and exhibits scalability.References: [1]Saha, Rajesh, Yogendra Pratap Pundir, and Pankaj Kumar Pal. "Comparative analysis of STT and SOT based MRAMs for last level caches." Journal of Magnetism and Magnetic Materials 551 (2022): 169161. [2]F. Hameed and J. Castrillon, “A novel hybrid DRAM/STT-RAM last-level-cache architecture for performance, energy, and endurance enhancement,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 27, no. 10, pp. 2375–2386, Oct. 2019. [3]E. Cheshmikhani, H. Farbeh and H. Asadi, "A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches," in IEEE Transactions on Reliability, vol. 69, no. 2, pp. 594-610, June 2020, doi: 10.1109/TR.2019.2923258. [4]Gao, L., Wang, R., Xu, Y. et al. SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU–GPU heterogeneous architectures. J Supercomput 74, 3388–3414 (2018).