title: Ð ÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ñ ÐºÐ¾Ð´ÐµÑÐ° LDPC ÐºÐ¾Ð´Ð° ÑÑÐ°Ð½Ð´Ð°ÑÑÐ¾Ð² DVB-S2/S2X Ð² FPGA
title: Ð²ÑÐ¿ÑÑÐºÐ½Ð°Ñ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð±Ð°ÐºÐ°Ð»Ð°Ð²ÑÐ°
titleType: Subtitle
title: Implementation of DVB-S2/S2X LDPC encoder in FPGA
Creators: name: ÐÐ°Ð·Ð°ÑÐµÐ½ÐºÐ¾, ÐÐ»ÐµÐºÑÐµÐ¹
Publisher: name: Ð¡Ð°Ð½ÐºÑ-ÐÐµÑÐµÑÐ±ÑÑÐ³ÑÐºÐ¸Ð¹ Ð¿Ð¾Ð»Ð¸ÑÐµÑÐ½Ð¸ÑÐµÑÐºÐ¸Ð¹ ÑÐ½Ð¸Ð²ÐµÑÑÐ¸ÑÐµÑ ÐÐµÑÑÐ° ÐÐµÐ»Ð¸ÐºÐ¾Ð³Ð¾
Year: 2020
Subjects: ÐÐ¾Ð´ÐµÑ
LDPC
DVB-S2
DVB-S2X
FEC
FPGA
ÐÐÐÐ¡
ASIC
ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ñ
Encoder
implementation

description: ÐÐ°Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð¿Ð¾ÑÐ²ÑÑÐµÐ½Ð° ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐºÐµ ÑÐ½Ð¸Ð²ÐµÑÑÐ°Ð»ÑÐ½Ð¾Ð³Ð¾ ÐºÐ¾Ð´ÐµÑÐ° LDPCÑÑÐ°Ð½Ð´Ð°ÑÑÐ¾Ð² DVB-S2/S2X. Ð ÐµÐ°Ð»Ð¸Ð·Ð¾Ð²Ð°Ð½Ð½ÑÐ¹ ÐºÐ¾Ð´ÐµÑ Ð¿Ð¾Ð´Ð´ÐµÑÐ¶Ð¸Ð²Ð°ÐµÑ Ð²ÑÐµ ÑÐºÐ¾ÑÐ¾ÑÑÐ¸ LDPCÐºÐ¾Ð´Ð°, Ð¾Ð¿ÑÐµÐ´ÐµÐ»ÐµÐ½Ð½ÑÐµ Ð² Ð´Ð°Ð½Ð½ÑÑ ÑÑÐ°Ð½Ð´Ð°ÑÑÐ°Ñ. Ð ÑÐ¾Ð´Ðµ Ð²ÑÐ¿Ð¾Ð»Ð½ÐµÐ½Ð¸Ñ Ð²ÑÐ¿ÑÑÐºÐ½Ð¾Ð¹ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð¾Ð¹ ÑÐ°Ð±Ð¾ÑÑ Ð±ÑÐ»Ð° ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐ°Ð½Ð° Ð°ÑÑÐ¸ÑÐµÐºÑÑÑÐ° Ð²ÑÑÐµÑÐ¿Ð¾Ð¼ÑÐ½ÑÑÐ¾Ð³Ð¾ ÐºÐ¾Ð´ÐµÑÐ°, Ð¿Ð¾ÑÐ»Ðµ ÑÐµÐ³Ð¾ Ð¾Ð½Ð° Ð±ÑÐ»Ð° ÑÐµÐ°Ð»Ð¸Ð·Ð¾Ð²Ð°Ð½Ð° Ð² ÐÐÐÐ¡ ÑÐµÐ¼ÐµÐ¹ÑÑÐ²Ð° XilinxKintexUltrascale. ÐÐ°Ð½Ð½ÑÐ¹ ÐºÐ¾Ð´ÐµÑ Ð±ÑÐ» Ð¿ÑÐ¾Ð²ÐµÑÐµÐ½ Ð² ÑÐ°Ð·Ð»Ð¸ÑÐ½ÑÑ ÑÐµÐ¶Ð¸Ð¼Ð°Ñ ÑÐ°Ð±Ð¾ÑÑ, ÑÐ°ÐºÐ¸Ñ ÐºÐ°Ðº: Ð¾Ð±ÑÐ°Ð±Ð¾ÑÐºÐ° Ð¾Ð´Ð½Ð¾Ð³Ð¾ Ð¿Ð°ÐºÐµÑÐ° Ð´Ð°Ð½Ð½ÑÑ, Ð¿Ð¾ Ð¾ÑÐ´ÐµÐ»ÑÐ½Ð¾ÑÑÐ¸,Ð´Ð»Ñ ÐºÐ°Ð¶Ð´Ð¾Ð¹ ÑÐºÐ¾ÑÐ¾ÑÑÐ¸ ÐºÐ¾Ð´Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ, Ð¾Ð±ÑÐ°Ð±Ð¾ÑÐºÐ° Ð¼Ð½Ð¾Ð¶ÐµÑÑÐ²Ð° Ð¿Ð°ÐºÐµÑÐ¾Ð² Ð´Ð°Ð½Ð½ÑÑ Ð² ÑÐ¾Ð´Ðµ Ð¿Ð¾ÑÐ¾ÐºÐ¾Ð²Ð¾Ð¹ Ð¿ÐµÑÐµÐ´Ð°ÑÐ¸Ð¿ÑÐ¸ Ð¼Ð½Ð¾Ð¶ÐµÑÑÐ²Ðµ ÑÐ°Ð·Ð»Ð¸ÑÐ½ÑÑ ÐºÐ¾Ð¼Ð±Ð¸Ð½Ð°ÑÐ¸Ð¹ ÑÐºÐ¾ÑÐ¾ÑÑÐµÐ¹ ÐºÐ¾Ð´Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ. ÐÐ»Ñ ÑÐ¾Ð·Ð´Ð°Ð½Ð¸Ñ Ð¸Ð½ÑÐ¾ÑÐ¼Ð°ÑÐ¸Ð¾Ð½Ð½ÑÑ Ð¿Ð¾ÑÐ»ÐµÐ´Ð¾Ð²Ð°ÑÐµÐ»ÑÐ½Ð¾ÑÑÐµÐ¹, Ð¿Ð¾Ð´Ð°Ð²Ð°ÐµÐ¼ÑÑ Ð½Ð° Ð²ÑÐ¾Ð´ ÐºÐ¾Ð´ÐµÑÐ°, Ð° ÑÐ°ÐºÐ¶Ðµ Ð´Ð»Ñ Ð¿ÑÐ¾Ð²ÐµÑÐºÐ¸ Ð´Ð¾ÑÑÐ¾Ð²ÐµÑÐ½Ð¾ÑÑÐ¸ Ð´Ð°Ð½Ð½ÑÑ Ð½Ð° Ð²ÑÑÐ¾Ð´Ðµ ÐºÐ¾Ð´ÐµÑÐ° Ð±ÑÐ»Ð¸ ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐ°Ð½Ñ ÑÐºÑÐ¸Ð¿ÑÑ Ð² Matlab.Ð ÑÐµÐ·ÑÐ»ÑÑÐ°ÑÐµ, Ð²ÑÐµ Ð´Ð°Ð½Ð½ÑÐµ, Ð¿Ð¾Ð»ÑÑÐµÐ½Ð½ÑÐµ Ñ Ð²ÑÑÐ¾Ð´Ð° ÐºÐ¾Ð´ÐµÑÐ°,Ð¾ÐºÐ°Ð·Ð°Ð»Ð¸ÑÑ Ð´Ð¾ÑÑÐ¾Ð²ÐµÑÐ½ÑÐ¼Ð¸. ÐÑÐ¾Ð¼ÐµÑÑÐ¾Ð³Ð¾,Ð±ÑÐ»Ð° Ð¿ÑÐ¾Ð²ÐµÐ´ÐµÐ½Ð° ÑÐ°Ð·Ð²Ð¾Ð´ÐºÐ° Ð¿ÑÐ¾ÐµÐºÑÐ°Ð² ÐÐÐÐ¡. Ð ÑÐ¾Ð´Ðµ Ð²ÑÐ¿Ð¾Ð»Ð½ÐµÐ½Ð¸Ñ Ð´Ð°Ð½Ð½Ð¾Ð¹ Ð·Ð°Ð´Ð°ÑÐ¸ Ð±ÑÐ»Ð¸ Ð¸ÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°Ð½Ñ ÑÐ°Ð·Ð»Ð¸ÑÐ½ÑÐµ ÑÑÑÐ°ÑÐµÐ³Ð¸Ð¸ ÑÐ°Ð·Ð²Ð¾Ð´ÐºÐ¸ Ð² ÑÑÐµÐ´Ðµ Vivado.ÐÐ»Ð¾ÐºÐ¸ LDPCÐºÐ¾Ð´ÐµÑÐ° Ð±ÑÐ»Ð¸ Ð¾Ð¿ÑÐ¸Ð¼Ð¸Ð·Ð¸ÑÐ¾Ð²Ð°Ð½Ñ Ð´Ð»Ñ Ð¿Ð¾Ð»ÑÑÐµÐ½Ð¸Ñ Ð½Ð°Ð¸Ð±Ð¾Ð»ÐµÐµ Ð²ÑÑÐ¾ÐºÐ¾Ð¹ ÑÐ°ÐºÑÐ¾Ð²Ð¾Ð¹ ÑÐ°ÑÑÐ¾ÑÑ.ÐÑÐµÐ·ÑÐ»ÑÑÐ°ÑÐµÐ¿ÑÐ¾Ð²ÐµÐ´ÐµÐ½Ð½Ð¾Ð¹ ÑÐ°Ð±Ð¾ÑÑ Ð±ÑÐ»Ð¸ Ð¿Ð¾Ð»ÑÑÐµÐ½Ñ Ð´Ð°Ð½Ð½ÑÐµ Ð¾ ÑÐ°Ð±Ð¾ÑÐµÐ¹ ÑÐ°ÐºÑÐ¾Ð²Ð¾Ð¹ ÑÐ°ÑÑÐ¾ÑÐµ Ð¸ Ð¾ ÐºÐ¾Ð»Ð¸ÑÐµÑÑÐ²Ðµ Ð·Ð°Ð´ÐµÐ¹ÑÑÐ²Ð¾Ð²Ð°Ð½Ð½ÑÑ ÑÐµÑÑÑÑÐ¾Ð².Ð ÑÐ°Ð¼ÐºÐ°Ñ Ð´Ð°Ð½Ð½Ð¾Ð¹ ÑÐ°Ð±Ð¾ÑÑ Ð±ÑÐ» Ð¿ÑÐ¾Ð¸Ð·Ð²ÐµÐ´ÐµÐ½ Ð¿Ð¾Ð¸ÑÐº Ð¸ Ð°Ð½Ð°Ð»Ð¸Ð· ÑÑÑÐµÑÑÐ²ÑÑÑÐ¸Ñ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ð¹ ÐºÐ¾Ð´ÐµÑÐ° LDPCÑÑÐ°Ð½Ð´Ð°ÑÑÐ¾Ð² DVB-S2/S2X, Ð¿Ð¾ÑÐ»Ðµ ÑÐµÐ³Ð¾ Ð±ÑÐ»Ð¾ Ð¿ÑÐ¾Ð²ÐµÐ´ÐµÐ½Ð¾ Ð¸Ñ ÑÑÐ°Ð²Ð½ÐµÐ½Ð¸Ðµ Ñ Ð¿ÑÐµÐ´Ð»Ð¾Ð¶ÐµÐ½Ð½Ð¾Ð¹ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸ÐµÐ¹. ÐÐ°Ð´Ð°Ð½Ð¸Ðµ Ð½Ð° Ð²ÑÐ¿ÑÑÐºÐ½ÑÑ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½ÑÑ ÑÐ°Ð±Ð¾ÑÑ Ð²ÑÐ¿Ð¾Ð»Ð½ÐµÐ½Ð¾ Ð² Ð¿Ð¾Ð»Ð½Ð¾Ð¼ Ð¾Ð±ÑÐµÐ¼Ðµ.
description: This work is devoted to the development of a universal LDPC encoder ofDVB-S2/S2Xstandards. The implemented encoder supports all the LDPC code rates defined in these standards.During the final qualifying work, the architecture of the aforementioned coder was developed, after which it was implemented in the FPGA of the Xilinx Kintex Ultrascale family. This encoder has been tested in various operating modes, such as: processing one data packet, separately, for each coding rate, processing multiple data packets during streaming with many different combinations of coding rates. To create information sequences supplied to the encoder input, as well as to verify the reliability of the data at the encoder output, scripts were developed in Matlab. As a result, all data obtained from the output of the encoder turned out to be reliable.In addition, the project was implementedin the FPGA. In the course of this task, various implementationstrategies in the Vivado were used. The LDPC encoder blocks have been optimized for the highest clock rate. As a result of the work, the information about operating clock frequency and thenumber of resources used wasobtained.Within the framework of this work, a search and analysis of existing implementations of the LDPC encoder of the DVB-S2/S2X standards was performed, after which they were compared with the proposed implementation.The task for the final qualification work is completed in full.