title: Ð ÐµÑÐµÐ½Ð¸Ðµ Ð·Ð°Ð´Ð°ÑÐ¸ Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ð½Ð¾-Ð°Ð¿Ð¿Ð°ÑÐ°ÑÐ½Ð¾Ð¹ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ð¸ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð¾Ð² ÑÐ¿ÑÐ°Ð²Ð»ÐµÐ½Ð¸Ñ ÑÐ¾Ð±Ð¾ÑÐ¾Ð¼
title: Solving the problem of software and hardware implementation of a robot control algorithms
Creators: name: ÐÐ¼Ð¾ÑÐ¾Ð², ÐÐ»Ð°Ð´Ð¸Ð¼Ð¸Ñ
name: ÐÐµÑÑÐ¾Ð², ÐÐ»ÐµÐºÑÐ°Ð½Ð´Ñ
name: Ð¢ÑÑÐºÐµÐ²Ð¸Ñ, ÐÐ½ÑÐ¾Ð½
name: "Ð¡Ð¸ÑÑÐµÐ¼Ð½ÑÐ¹ Ð°Ð½Ð°Ð»Ð¸Ð· Ð² Ð¿ÑÐ¾ÐµÐºÑÐ¸ÑÐ¾Ð²Ð°Ð½Ð¸Ð¸ Ð¸ ÑÐ¿ÑÐ°Ð²Ð»ÐµÐ½Ð¸Ð¸", Ð¼ÐµÐ¶Ð´ÑÐ½Ð°ÑÐ¾Ð´Ð½Ð°Ñ Ð½Ð°ÑÑÐ½Ð°Ñ Ð¸ ÑÑÐµÐ±Ð½Ð¾-Ð¿ÑÐ°ÐºÑÐ¸ÑÐµÑÐºÐ°Ñ ÐºÐ¾Ð½ÑÐµÑÐµÐ½ÑÐ¸Ñ (25; 2021; Ð¡Ð°Ð½ÐºÑ-ÐÐµÑÐµÑÐ±ÑÑÐ³)
Publisher: name: ÐÐÐÐÐ¢ÐÐ¥-ÐÐ ÐÐ¡Ð¡
Year: 2021
Subjects: Ð¡Ð¸ÑÑÐµÐ¼Ð½ÑÐ¹ Ð°Ð½Ð°Ð»Ð¸Ð·
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description: Ð Ð´Ð°Ð½Ð½Ð¾Ð¹ ÑÑÐ°ÑÑÐµ Ð¿ÑÐµÐ´Ð»Ð°Ð³Ð°ÐµÑÑÑ ÑÐµÑÐµÐ½Ð¸Ðµ Ð¿ÑÐ¾Ð±Ð»ÐµÐ¼Ñ Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ð½Ð¾Ð¹ Ð¸ Ð°Ð¿Ð¿Ð°ÑÐ°ÑÐ½Ð¾Ð¹ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ð¸ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð¾Ð² ÑÐ¿ÑÐ°Ð²Ð»ÐµÐ½Ð¸Ñ ÑÐ¾Ð±Ð¾ÑÐ¾Ð¼. Ð ÐºÐ°ÑÐµÑÑÐ²Ðµ Ð¿ÑÐ¸Ð¼ÐµÑÐ° ÑÐ°ÑÑÐ¼Ð°ÑÑÐ¸Ð²Ð°ÑÑÑÑ ÑÐ°Ð·Ð»Ð¸ÑÐ½ÑÐµ Ð¼ÐµÑÐ¾Ð´Ñ Ð°Ð¿Ð¿Ð°ÑÐ°ÑÐ½Ð¾Ð¹ Ð¸ Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ð½Ð¾Ð¹ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ð¸ Ð¾Ð´Ð½Ð¸Ñ Ð¸ ÑÐµÑ Ð¶Ðµ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð¾Ð², Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð°Ð¼Ð¸ ÐºÐ¾ÑÐ¾ÑÑÑ ÑÐ²Ð»ÑÑÑÑÑ ÐºÐ¾Ð½ÑÑÐ¾Ð»Ð»ÐµÑ Ð»Ð¸ÑÑÐ° Ð¸ ÑÐ¾ÑÑÐ¸ÑÐ¾Ð²ÐºÐ° Ð¿ÑÐ·ÑÑÑÐºÐ¾Ð². ÐÑÐµÐ´Ð»Ð¾Ð¶ÐµÐ½Ñ ÑÐ·ÑÐºÐ¸ Ð¸Ñ Ð¾Ð¿Ð¸ÑÐ°Ð½Ð¸Ñ: Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ð½Ð°Ñ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ñ Ð²ÑÐ¿Ð¾Ð»Ð½ÐµÐ½Ð° Ð½Ð° ÑÐ·ÑÐºÐµ Ð²ÑÑÐ¾ÐºÐ¾Ð³Ð¾ ÑÑÐ¾Ð²Ð½Ñ SystemC Ð¸ Ð½Ð° ÑÐ±Ð¾ÑÐºÐµ 32-ÑÐ°Ð·ÑÑÐ´Ð½Ð¾Ð³Ð¾ ÑÐ¸ÑÑÐ¾Ð²Ð¾Ð³Ð¾ Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ° (DP32), Ð°Ð¿Ð¿Ð°ÑÐ°ÑÐ½Ð°Ñ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ñ Ð²ÑÐ¿Ð¾Ð»Ð½ÐµÐ½Ð° Ð½Ð° ÑÐ·ÑÐºÐ°Ñ Ð¾Ð¿Ð¸ÑÐ°Ð½Ð¸Ñ ÑÐ¸ÑÑÐ¾Ð²Ð¾Ð³Ð¾ Ð¾Ð±Ð¾ÑÑÐ´Ð¾Ð²Ð°Ð½Ð¸Ñ VHDL Ð¸ Verilog HDL. ÐÐ°Ð¶Ð´Ð°Ñ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ñ Ð¿Ð¾Ð´ÑÐ°Ð·ÑÐ¼ÐµÐ²Ð°ÐµÑ Ð½Ð°Ð¿Ð¸ÑÐ°Ð½Ð¸Ðµ ÑÐµÑÑÐ¾Ð²Ð¾Ð³Ð¾ ÑÑÐµÐ½Ð°ÑÐ¸Ñ (TestBench). Ð¢ÐµÑÑÐ¸ÑÐ¾Ð²Ð°Ð½Ð¸Ðµ Ð´Ð»Ñ SystemC, Ð° ÑÐ°ÐºÐ¶Ðµ Ð²ÐµÑÑÐ¸Ð¹ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð¾Ð² VHDL Ð¸ Verilog HDL Ð¿ÑÐ¾Ð²Ð¾Ð´Ð¸Ð»Ð¾ÑÑ Ñ Ð¸ÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°Ð½Ð¸ÐµÐ¼ Ð¼Ð¾Ð´ÐµÐ»Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ, Ð² ÑÐ¾ Ð²ÑÐµÐ¼Ñ ÐºÐ°Ðº Ð´Ð»Ñ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð° Ð² Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ½Ð¾Ð¹ ÑÐ±Ð¾ÑÐºÐµ DP32 Ð¸ÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°Ð»Ð¾ÑÑ ÑÐ¾Ð²Ð¼ÐµÑÑÐ½Ð¾Ðµ Ð¼Ð¾Ð´ÐµÐ»Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ðµ. Ð Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ð½Ð¾Ð¹ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ð¸ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð¾Ð² ÑÐµÑÑÐ¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ Ð¸ÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°Ð»Ð°ÑÑ ÑÑÐµÐ´Ð° Aldec Active CAD Ñ VHDL-Ð¼Ð¾Ð´ÐµÐ»ÑÐ¼Ð¸ Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ°, Ð¿Ð°Ð¼ÑÑÐ¸ Ð¸ Ð³ÐµÐ½ÐµÑÐ°ÑÐ¾ÑÐ° ÑÐ°ÐºÑÐ¾Ð²ÑÑ Ð¸Ð¼Ð¿ÑÐ»ÑÑÐ¾Ð², Ð° ÑÐ°ÐºÐ¶Ðµ ÑÑÐµÐ´Ð° Microsoft Visual Studio ÑÐ¾ ÑÑÐµÐ´ÑÑÐ²Ð¾Ð¼ Ð¿ÑÐ¾ÑÐ¼Ð¾ÑÑÐ° Ð²ÑÐµÐ¼ÐµÐ½Ð½ÑÑ Ð´Ð¸Ð°Ð³ÑÐ°Ð¼Ð¼ GTKWave. Ð Ð°Ð¿Ð¿Ð°ÑÐ°ÑÐ½Ð¾Ð¹ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ð¸ Ð´Ð»Ñ ÑÐµÑÑÐ¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ Ð¸ Ð¾ÑÐµÐ½ÐºÐ¸ ÑÐ¸Ð½ÑÐµÐ·Ð¸ÑÑÐµÐ¼Ð¾ÑÑÐ¸ Ð¸ÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°Ð»Ð°ÑÑ CAD-ÑÐ¸ÑÑÐµÐ¼Ð° Quartus II, Ð° ÑÐ°ÐºÐ¶Ðµ Ð¿ÐµÑÐµÐ²Ð¾Ð´ÑÐ¸Ðº âsc2vâ Ñ ÑÐ·ÑÐºÐ° System C Ð½Ð° ÑÐ·ÑÐº Verilog HDL. Ð¤ÑÐ°Ð³Ð¼ÐµÐ½ÑÑ ÑÐµÐ·ÑÐ»ÑÑÐ°ÑÐ¾Ð² Ð¼Ð¾Ð´ÐµÐ»Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ, ÑÐ¾Ð²Ð¼ÐµÑÑÐ½Ð¾Ð³Ð¾ Ð¼Ð¾Ð´ÐµÐ»Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ Ð¸ ÑÐµÑÑÐ¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ Ð½Ð° ÑÐ¸Ð½ÑÐµÐ·Ð¸ÑÑÐµÐ¼Ð¾ÑÑÑ Ð¿ÑÐµÐ´ÑÑÐ°Ð²Ð»ÐµÐ½Ñ Ð² Ð²Ð¸Ð´Ðµ Ð¾ÑÑÐµÑÐ° Ð¾ ÑÐ°Ð·Ð¼ÐµÑÐµÐ½Ð¸Ð¸ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð° Ð² Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ð¸ÑÑÐµÐ¼Ð¾Ð¹ Ð»Ð¾Ð³Ð¸ÑÐµÑÐºÐ¾Ð¹ Ð¸Ð½ÑÐµÐ³ÑÐ°Ð»ÑÐ½Ð¾Ð¹ ÑÑ ÐµÐ¼Ðµ (ÐÐÐÐ¡), ÑÑ ÐµÐ¼Ñ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð° Ð² ÐÐÐÐ¡ Ð½Ð° ÑÑÐ¾Ð²Ð½Ðµ Ð¿ÐµÑÐµÐ´Ð°ÑÐ¸ ÑÐµÐ³Ð¸ÑÑÑÐ¾Ð² (RTL) Ð¸ ÑÐµÑ Ð½Ð¾Ð»Ð¾Ð³Ð¸ÑÐµÑÐºÐ¾Ð¹ ÑÑ ÐµÐ¼Ñ Ð¸Ð· Ð»Ð¾Ð³Ð¸ÑÐµÑÐºÐ¸Ñ ÑÑÐµÐµÐº ÑÑÐ¾Ð¹ ÐÐÐÐ¡.
description: In the following article a solution to the problem of software and hardware implementations of robot control algorithms is proposed. Various methods of hardware and software implementations of the same algorithms are reviewed by way of example, the algorithms being the elevator controller and the bubble sorting. The languages of their description are proposed: the software implementation was carried out in the high-level SystemC language and in assembly of the 32-bit Digital Processor (DP32), the hardware implementation was carried out in the VHDL and Verilog HDL digital equipment description languages. Each implementation implies writing a test script (TestBench). Testing for the SystemC as well the VHDL and Verilog HDL algorithm versions was carried out using simulation, while for the algorithm in DP32 processor assembly a cosimulation was used. In the software implementation of the test algorithms, we used the Aldec Active CAD environment with VHDL models of the processor, memory and clock pulse generator, and the Microsoft Visual Studio environment with the GTKWave timing diagram viewer. In the hardware implementation, for tests and synthesizability estimation the Quartus II CAD system was used, as well as the âsc2vâ translator from the System C language to the Verilog HDL language. Fragments of the results of simulation, co-simulation and testing for synthesizability are presented in the form of a report on the placement of the algorithm in a programmable logic integrated circuit (FPGA), an algorithm diagram in an FPGA at the register transfer level (RTL) and a technological scheme from logical cells of this FPGA.