title: Statistical charge-based modeling of 1/f noise in standard and high-voltage MOS transistors
title: Στατιστικό μοντέλο θορύβου 1/f σε standard και high-voltage MOS τρανζίστορ

Creators: name: Μαυρεδακης Νικολαος
Publisher: name: Technical University of Crete
Year: 2016

description: Nowadays, analog and RFIC applications are exclusively been designed by CMOS
technology because of many advantages such as the high level of integration, the low cost and low consumption that it offers. The achievement of integration on a single chip (SoC) both for analog and digital systems triggered a great boost in the domination of CMOS especially with the downscaling of MOSFET dimensions. Apart from conventional CMOS, HV-MOS process is also widely used in specific applications such as automotive industry, scientific and medical applications and consumer electronics. The latter kind of power applications created the need of the usage of power devices such as HV-MOSFETs and nowadays in circuit design, high-voltage parts are integrated together with low-voltage modules. Nevertheless, the performance of both CMOS and HV-MOS design can be limited by low frequency noise (LFN) which becomes really significant in state of the art technologies because it is inversely proportional to channel area. Despite the fact that is dominant for lower frequencies below the corner frequency, it can prove to be a significant hurdle even for high-frequency (RF) applications due to its up conversion in phase noise in VCO design for example. Furthermore, in advanced ultradeep nano-scaled transistors, corner frequencies of several MHz can be noticed and thus analog designers can not ignore LFN. As far as HV-MOSFETs are concerned, circuits such as oscillators, analog baseband and bandgap reference can be limited by LFN. In general, it affects any kind of MOS device but it can also be used as an effective way to evaluate the quality and reliability of a MOS transistor. LFN is distinguished into two kinds; random telegraph signal (RTS) noise and flicker or 1/f noise. RTS noise is created by the generation-recombination process or trapping/detrapping mechanism at the silicon oxide interface. Each such trap can create an RTS in time domain or a Lorentzian-like spectrum in frequency domain. RTS noise prevails in smaller area transistors where the traps are only few. In larger devices, on the other hand, the number of traps is quite large and the superposition of Lorentzian spectra can lead to 1/f behavior and thus it creates 1/f noise. This connection of RTS with 1/f noise is fully described by carrier number fluctuation effect which constitutes one of the main 1/f noise generators in MOS devices. Two other phenomena create 1/f noise and these are mobility fluctuation and series resistance effects. It is experimentally shown that each of these effects is dominant under different operating conditions. Mean value and variability of LFN are both area- and bias-dependent. Variability increases as device dimensions shrink bearing similarity with the behavior of mean value noise. The same trend can be observed in the bias-dependence of 1/f noise variability. Carrier number fluctuation effect has been proven to increase normalized flicker noise WL  SID=ID^2 at 1Hz, in moderate and strong inversion and the same is confirmed for its variability while mobility fluctuation effect is considered responsible for the increase of normalized 1/f noise in weak inversion and its variability also increases there. This bias-dependence of flicker noise variability is of great concern especially since the downscaling of advanced nanotechnologies has led to circuit operation in moderate or even in weak inversion. Flicker noise in HV MOSFETs is expected to be generated by the same causes as in conventional MOSFETs since the same operating principles rule both kind of these MOS devices due to the existence of the oxide interface. Thus, it is experimentally shown that in the LV or channel part of the HV-MOSFET, carrier number fluctuation, mobility fluctuation and series resistance effects are the main contributors to 1/f noise. This was already known and the main question was if any similar effect is observed in drift region. Our analysis showed that the extension of gate oxide in the surface of drift region, causes a similar carrier number fluctuation effect which can give rise to 1/f noise. This noise becomes significant under linear region and strong inversion regime of long channel transistors since only under these conditions it reaches a similar level as the noise generated in the channel. Because of the significant impact of LFN in advanced analog and RF circuit design, the usage of correct, physics-based, compact models both for mean value and statistical behavior of LFN has become essential for noise simulation. Within the context of this Thesis, a charge-based compact model both for the mean-value and the variability of 1/f noise was implemented, validated at an experimental 180 nm CMOS process with measurements in our lab and appended in the charge-based EKV3 compact MOSFET model. The mean value model was also tested at an 90nm CMOS process provided by the industry while the variability model was also tested at an 140 nm CMOS process. The analytical, charge-based approach for 1/f noise statistics is directly related to the physical effects that generate 1/f noise in MOS devices and this is something proposed for the first time. A similar charge-based 1/f noise compact model is proposed for the first time for HV-MOSFETs after exploring and locating new noise sources that arise from the drift region of the device. An expression for the variability of 1/f noise arising from the channel of HV-MOSFETs is also proposed but is not validated since sufficient statistical data were not available. The mean value model was validated with data from an 350 nm HV-MOS process provided by ams AG. Measurements were performed by us in a new 1/f noise measurement set-up specialized for HV-MOSFETs and provided by AdMOS. Characterization of 1/f noise data in all the above cases confirms the existing theory while the developed 1/f noise models both for CMOS and HV-MOS technologies give qualitively good results over a wide range of area and operating conditions