A Low-Cost Cell-Level Differential Power Processing CMOS IC with Wire Bond Inductors and Soft-Switching Controller for Single Junction Photovoltaic Cells
Creators: Amoorezaei, Afshin
Publisher: name: University of Alberta Library
Year: 2023

<p>Recent developments of distributed generation systems and reduced cost of solar panels have enabled Photovoltaic systems to become one of the most promising and invested renewable energy sources over the last decades. Due to the low output voltage of a single PV cell, a series connection of 60 or 72 PV cells is usually employed within PV panels to increase the voltage level. The series and parallel combinations of PV panels are then utilized to further increase the DC voltage and meet the power requirements of the PV system. However, partial shading or any characteristic mismatch can lead to different maximum power point currents for the PVs. Since the PVs in a series connection share the same current, this issue limits the overall string current to the lowest MPP current, drastically deteriorating the power yield and system efficiency. The current mismatch affects the operation of PV systems at different granularity levels, from individual cells to string level.</p>

<p>The main objective of this research is to design a low-cost small form-factor cell-level differential power processing IC to maximize the power yield of series-connected single junction PV cells under partial shading and mismatch conditions. First, a 3-MHz dual-phase bidirectional buck-boost DPP converter with off-chip passive components is proposed to force the PV cells to operate near their maximum power point for different mismatch levels. The proposed circuit maintains high system efficiency using a low-power low-area analog controller to achieve voltage equalization. The proposed DPP IC eliminates the need for power-hungry blocks such as ADCs, DACs, OP-Amps, saw-tooth generator, and regulators. The voltage of adjacent PV cells is utilized to drive the high-side switches through bootstrap supplies, eliminating the requirement for voltage regulators. The performance of the proposed IC, fabricated in a 130 nm CMOS process, is validated through simulation and experimental results. The converter is capable of handling mismatch currents up to 4 A, while the control circuitry consumes less than 40 mW and a system efficiency above 95% is achieved.</p>

<p>In the second design, to improve the performance and reduce the form-factor of the DPP IC, the switching frequency is increased to enable the use of packaging wire bonds for implementing inductors. A dual-phase Cuk converter topology was selected for implementing the DPP, as it allows the utilization of the parasitic inductors of the wire bonds as part of the passive components in the topology. The converters are interleaved to reduce input/output current ripples and minimize the size of filter components. To mitigate switching losses at higher frequencies, a closed-loop soft switching controller is proposed, which achieves zero voltage switching by operating in triangular conduction mode regardless of the mismatch current and process variations. To eliminate the need for extra connections from adjacent PV cells, a modified low voltage bootstrap circuit is proposed to generate the gate signal for the high-side switches. The simulation and experimental results validate the performance of the circuit, achieving a system efficiency of over 93% for mismatch currents up to 3 A.  </p>