title: ÐÑÑÐ»ÐµÐ´Ð¾Ð²Ð°Ð½Ð¸Ðµ ÑÑÑÐµÐºÑÐ¸Ð²Ð½Ð¾ÑÑÐ¸ ÑÑÐµÐ´ÑÑÐ² Ð²ÑÑÐ¾ÐºÐ¾ÑÑÐ¾Ð²Ð½ÐµÐ²Ð¾Ð³Ð¾ ÑÐ¸Ð½ÑÐµÐ·Ð° Ð´Ð»Ñ Ð°Ð¿Ð¿Ð°ÑÐ°ÑÐ½Ð¾Ð¹ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ð¸ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð¾Ð² ÑÐ¾ÑÑÐ¸ÑÐ¾Ð²ÐºÐ¸
title: Ð²ÑÐ¿ÑÑÐºÐ½Ð°Ñ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð¼Ð°Ð³Ð¸ÑÑÑÐ°
titleType: Subtitle
title: Research of the effectiveness of high level synthesis tools for hardware implementation of sorting algorithms
Creators: name: ÐÐµÑÐµÐ´Ð¸Ð½, ÐÐµÐ½Ð¸Ñ
Publisher: name: Ð¡Ð°Ð½ÐºÑ-ÐÐµÑÐµÑÐ±ÑÑÐ³ÑÐºÐ¸Ð¹ Ð¿Ð¾Ð»Ð¸ÑÐµÑÐ½Ð¸ÑÐµÑÐºÐ¸Ð¹ ÑÐ½Ð¸Ð²ÐµÑÑÐ¸ÑÐµÑ ÐÐµÑÑÐ° ÐÐµÐ»Ð¸ÐºÐ¾Ð³Ð¾
Year: 2020
Subjects: Ð°Ð¿Ð¿Ð°ÑÐ°ÑÐ½Ð¾Ðµ ÑÑÐºÐ¾ÑÐµÐ½Ð¸Ðµ
Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ñ ÑÐ¾ÑÑÐ¸ÑÐ¾Ð²ÐºÐ¸
Ð²ÑÑÐ¾ÐºÐ¾ÑÑÐ¾Ð²Ð½ÐµÐ²ÑÐ¹ ÑÐ¸Ð½ÑÐµÐ·
ÑÐµÐºÐ¾Ð½ÑÐ¸Ð³ÑÑÐ¸ÑÑÐµÐ¼ÑÐµ Ð°Ð¿Ð¿Ð°ÑÐ°ÑÐ½ÑÐµ ÑÑÐºÐ¾ÑÐ¸ÑÐµÐ»Ð¸
FPGA
hardware acceleration
sorting algorithms
high-level synthesis
reconfigurable hardware accelerator

description: Ð¢ÐµÐ¼Ð° Ð²ÑÐ¿ÑÑÐºÐ½Ð¾Ð¹ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð¾Ð¹ ÑÐ°Ð±Ð¾ÑÑ: "ÐÑÑÐ»ÐµÐ´Ð¾Ð²Ð°Ð½Ð¸Ðµ ÑÑÑÐµÐºÑÐ¸Ð²Ð½Ð¾ÑÑÐ¸ ÑÑÐµÐ´ÑÑÐ² Ð²ÑÑÐ¾ÐºÐ¾ÑÑÐ¾Ð²Ð½ÐµÐ²Ð¾Ð³Ð¾ ÑÐ¸Ð½ÑÐµÐ·Ð° Ð´Ð»Ñ Ð°Ð¿Ð¿Ð°ÑÐ°ÑÐ½Ð¾Ð¹ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ð¸ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð¾Ð² ÑÐ¾ÑÑÐ¸ÑÐ¾Ð²ÐºÐ¸".

ÐÐ°Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð¿Ð¾ÑÐ²ÑÑÐµÐ½Ð° Ð¸ÑÑÐ»ÐµÐ´Ð¾Ð²Ð°Ð½Ð¸Ñ ÑÑÑÐµÐºÑÐ¸Ð²Ð½Ð¾ÑÑÐ¸ Ð°Ð¿Ð¿Ð°ÑÐ°ÑÐ½Ð¾Ð¹ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ð¸ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð¾Ð² ÑÐ¾ÑÑÐ¸ÑÐ¾Ð²ÐºÐ¸, ÑÐ¾Ð·Ð´Ð°Ð½Ð½ÑÑ Ñ Ð¸ÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°Ð½Ð¸ÐµÐ¼ Ð¸Ð½ÑÑÑÑÐ¼ÐµÐ½ÑÐ¾Ð² Ð²ÑÑÐ¾ÐºÐ¾ÑÑÐ¾Ð²Ð½ÐµÐ²Ð¾Ð³Ð¾ ÑÐ¸Ð½ÑÐµÐ·Ð°, Ð¿Ð°ÐºÐµÑÐ° Vivado HLS Ð¸ FPGA, ÑÐµÐ»ÑÑ ÐºÐ¾ÑÐ¾ÑÐ¾Ð³Ð¾ ÑÐ²Ð»ÑÑÑÑÑ: Ð¾ÑÐµÐ½ÐºÐ° ÑÑÑÐµÐºÑÐ¸Ð²Ð½Ð¾ÑÑÐ¸ Ð¿ÑÐ¸Ð¼ÐµÐ½ÐµÐ½Ð¸Ñ Ð¸Ð½ÑÑÑÑÐ¼ÐµÐ½ÑÐ¾Ð² Ð²ÑÑÐ¾ÐºÐ¾ÑÑÐ¾Ð²Ð½ÐµÐ²Ð¾Ð³Ð¾ ÑÐ¸Ð½ÑÐµÐ·Ð° Ð´Ð»Ñ Ð°Ð¿Ð¿Ð°ÑÐ°ÑÐ½Ð¾Ð³Ð¾ ÑÑÐºÐ¾ÑÐµÐ½Ð¸Ñ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð¾Ð² ÑÐ¾ÑÑÐ¸ÑÐ¾Ð²ÐºÐ¸, Ð° ÑÐ°ÐºÐ¶Ðµ Ð¿Ð¾Ð¸ÑÐº Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð¾Ð² ÑÐ¾ÑÑÐ¸ÑÐ¾Ð²ÐºÐ¸, Ð´Ð»Ñ ÐºÐ¾ÑÐ¾ÑÑÑ Ð¿Ð°ÐºÐµÑ Vivado HLS Ð¿Ð¾Ð·Ð²Ð¾Ð»ÑÐµÑ ÑÐ¾Ð·Ð´Ð°ÑÑ Ð°Ð¿Ð¿Ð°ÑÐ°ÑÐ½ÑÑ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ñ, Ð¸Ð¼ÐµÑÑÑÑ Ð±Ð¾Ð»ÑÑÐµÐµ, Ð¿Ð¾ ÑÑÐ°Ð²Ð½ÐµÐ½Ð¸Ñ Ñ Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ð½Ð¾Ð¹ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸ÐµÐ¹, Ð±ÑÑÑÑÐ¾Ð´ÐµÐ¹ÑÑÐ²Ð¸Ðµ.

Ð ÑÐ¾Ð´Ðµ Ð¸ÑÑÐ»ÐµÐ´Ð¾Ð²Ð°Ð½Ð¸Ñ Ð±ÑÐ»Ð¾ Ð¿ÑÐ¾Ð²ÐµÐ´ÐµÐ½Ð¾ Ð¸Ð¼Ð¸ÑÐ°ÑÐ¸Ð¾Ð½Ð½Ð¾Ðµ Ð¼Ð¾Ð´ÐµÐ»Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ðµ Ð¸ ÑÑÐ°Ð²Ð½Ð¸ÑÐµÐ»ÑÐ½ÑÐ¹ Ð°Ð½Ð°Ð»Ð¸Ð· ÑÐ¸ÑÐ¾ÐºÐ¾Ð³Ð¾ ÑÐ¿ÐµÐºÑÑÐ° Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð¾Ð² ÑÐ¾ÑÑÐ¸ÑÐ¾Ð²ÐºÐ¸, ÑÐµÐ°Ð»Ð¸Ð·Ð¾Ð²Ð°Ð½Ð½ÑÑ Ð½Ð° ÑÐ½Ð¸Ð²ÐµÑÑÐ°Ð»ÑÐ½Ð¾Ð¼ Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐµ Ð¸ Ð½Ð° FPGA Xilinx. ÐÐ¾Ð»ÑÑÐµÐ½Ð½ÑÐµ Ð² ÑÐ¾Ð´Ðµ ÑÐ°Ð±Ð¾ÑÑ ÑÐµÐ·ÑÐ»ÑÑÐ°ÑÑ Ð¸ÑÑÐ»ÐµÐ´Ð¾Ð²Ð°Ð½Ð¸Ð¹ Ð¿Ð¾ÐºÐ°Ð·Ð°Ð»Ð¸, ÑÑÐ¾ Ð°Ð¿Ð¿Ð°ÑÐ°ÑÐ½ÑÐµ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ð¸ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð¾Ð² ÑÐ¾ÑÑÐ¸ÑÐ¾Ð²ÐºÐ¸, ÑÐ¸Ð½ÑÐµÐ·Ð¸ÑÐ¾Ð²Ð°Ð½Ð½ÑÐµ Ñ Ð¿Ð¾Ð¼Ð¾ÑÑÑ Ð¿Ð°ÐºÐµÑÐ° Xininx HLS, Ð½Ðµ Ð²ÑÐµÐ³Ð´Ð° Ð¾Ð±ÐµÑÐ¿ÐµÑÐ¸Ð²Ð°ÑÑ Ð±Ð¾Ð»ÐµÐµ Ð²ÑÑÐ¾ÐºÑÑ Ð¿ÑÐ¾Ð¸Ð·Ð²Ð¾Ð´Ð¸ÑÐµÐ»ÑÐ½Ð¾ÑÑÑ Ð¿Ð¾ ÑÑÐ°Ð²Ð½ÐµÐ½Ð¸Ñ Ñ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸ÑÐ¼Ð¸ ÑÐµÑ Ð¶Ðµ Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð¾Ð² Ð½Ð° ÑÐ½Ð¸Ð²ÐµÑÑÐ°Ð»ÑÐ½Ð¾Ð¼ Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐµ, Ð¸ Ð·Ð°Ð²Ð¸ÑÑÑ Ð¾Ñ Ð²Ð½ÑÑÑÐµÐ½Ð½Ð¸Ñ ÑÐ²Ð¾Ð¹ÑÑÐ² Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð°, ÑÐ°ÐºÐ¸Ñ ÐºÐ°Ðº Ð²Ð¾Ð·Ð¼Ð¾Ð¶Ð½Ð¾ÑÑÐ¸ Ð¸Ñ ÑÐ°ÑÐ¿Ð°ÑÐ°Ð»Ð»ÐµÐ»Ð¸Ð²Ð°Ð½Ð¸Ñ Ð¸ ÐºÐ¾Ð½Ð²ÐµÐ¹ÐµÑÐ¸Ð·Ð°ÑÐ¸Ð¸.
description: The subject of the graduate qualification work is "Research of the effectiveness of high-level synthesis tools for the hardware implementation of sorting algorithms."

This work is devoted to the research of the efficiency of hardware implementation of sorting algorithms created using high-level synthesis tools, the Vivado HLS package and FPGA. The purpose of the research is to evaluate effectiveness of the use of high-level synthesis tools for hardware acceleration of sorting algorithms, as well as the search for sorting algorithms for which the Vivado HLS package allows you to create a hardware implementation that has greater speed compared to the software implementation

 There are simulation modeling and comparative analysis of a wide range of sorting algorithms implemented on a universal processor and on Xilinx FPGA were carried out. The research results showed that the hardware implementations of the sorting algorithms synthesized using the Xininx HLS package do not always provide higher performance than implementations of the same algorithms on a universal processor and depend on the internal properties of the algorithm, such as the possibility of parallelization and pipelining.