title: Ð Ð°Ð·ÑÐ°Ð±Ð¾ÑÐºÐ° Ð¼Ð¸ÐºÑÐ¾Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ½Ð¾Ð³Ð¾ ÑÐ´ÑÐ° Ð°ÑÑ Ð¸ÑÐµÐºÑÑÑÑ RISC-V Ð½Ð° ÑÐ·ÑÐºÐµ SystemVerilog Ð´Ð»Ñ Ð²ÑÑÑÐ°Ð¸Ð²Ð°ÐµÐ¼ÑÑ ÑÐ¸ÑÑÐµÐ¼
title: Ð²ÑÐ¿ÑÑÐºÐ½Ð°Ñ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð±Ð°ÐºÐ°Ð»Ð°Ð²ÑÐ°
titleType: Subtitle
title: Development of a RISC-V architecture microprocessor core for embedded systems on SystemVerilog language
Creators: name: ÐÐ½ÑÑÐ¾Ð¿Ð¾Ð², ÐÐ»Ð°Ð´Ð¸ÑÐ»Ð°Ð²
Publisher: name: Ð¡Ð°Ð½ÐºÑ-ÐÐµÑÐµÑÐ±ÑÑÐ³ÑÐºÐ¸Ð¹ Ð¿Ð¾Ð»Ð¸ÑÐµÑÐ½Ð¸ÑÐµÑÐºÐ¸Ð¹ ÑÐ½Ð¸Ð²ÐµÑÑÐ¸ÑÐµÑ ÐÐµÑÑÐ° ÐÐµÐ»Ð¸ÐºÐ¾Ð³Ð¾
Year: 2023
Subjects: Ð¼Ð¸ÐºÑÐ¾Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ½Ð¾Ðµ ÑÐ´ÑÐ¾
SystemVerilog HDL
RISC
RISC-V
Ð°ÑÑ Ð¸ÑÐµÐºÑÑÑÐ°
Ð¼Ð¸ÐºÑÐ¾Ð°ÑÑ Ð¸ÑÐµÐºÑÑÑÐ°
Ð¸Ð½ÑÐµÐ³ÑÐ°Ð»ÑÐ½Ð°Ñ ÑÑ ÐµÐ¼Ð°
ÑÐ·ÑÐº Ð¾Ð¿Ð¸ÑÐ°Ð½Ð¸Ñ Ð°Ð¿Ð¿Ð°ÑÐ°ÑÐ½Ð¾Ð³Ð¾ ÑÑÐ¾Ð²Ð½Ñ
ÑÑÐ°ÑÐ¸ÑÐµÑÐºÐ¸Ð¹ Ð²ÑÐµÐ¼ÐµÐ½Ð½Ð¾Ð¹ Ð°Ð½Ð°Ð»Ð¸Ð·
Ð¿ÑÐµÐ´ÑÐºÐ°Ð·Ð°ÑÐµÐ»Ñ Ð²ÐµÑÐ²Ð»ÐµÐ½Ð¸Ð¹
microcessor core
architecture
microarchitecture
integral circuit
hardware description language
static timing analysis
branch predictor

description: Ð ÑÐ¾Ð´Ðµ Ð´Ð°Ð½Ð½Ð¾Ð¹ ÑÐ°Ð±Ð¾ÑÑ Ð±ÑÐ» ÑÐ°ÑÑÐ¼Ð¾ÑÑÐµÐ½ Ð¿ÑÑÑ ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐºÐ¸ ÑÐ¸ÑÑÐ¾Ð²Ð¾Ð¹ ÐÐ¡, Ð¾ÑÐ¾Ð±Ð¾Ðµ Ð²Ð½Ð¸Ð¼Ð°Ð½Ð¸Ðµ ÑÐ´ÐµÐ»ÐµÐ½Ð¾ Ð»Ð¾Ð³Ð¸ÑÐµÑÐºÐ¾Ð¼Ñ ÑÐ¸Ð½ÑÐµÐ·Ñ Ð¸ ÑÑÐ°ÑÐ¸ÑÐµÑÐºÐ¾Ð¼Ñ Ð²ÑÐµÐ¼ÐµÐ½Ð½Ð¾Ð¼Ñ Ð°Ð½Ð°Ð»Ð¸Ð·Ñ, Ð¿ÑÐ¸ ÑÑÐ¾Ð¼ Ð¿ÑÐ¸Ð¼ÐµÐ½ÑÐ»Ð¸ÑÑ Ð¼ÐµÑÐ¾Ð´Ñ Ð¿Ð¾Ð¸ÑÐºÐ° Ð¸ Ð°Ð½Ð°Ð»Ð¸Ð·Ð° Ð¸Ð½ÑÐ¾ÑÐ¼Ð°ÑÐ¸Ð¸ Ð¸Ð· ÑÐ°Ð·Ð»Ð¸ÑÐ½ÑÑ Ð¸ÑÑÐ¾ÑÐ½Ð¸ÐºÐ¾Ð². ÐÑÐ»Ð¸ ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐ°Ð½Ñ Ð¸ ÑÐ¸Ð½ÑÐµÐ·Ð¸ÑÐ¾Ð²Ð°Ð½Ñ Ð½Ð° ÐÐÐÐ¡ ÑÑÐ¸ ÑÐ¸Ð¿Ð° Ð¼Ð¸ÐºÑÐ¾Ð°ÑÑÐ¸ÑÐµÐºÑÑÑ Ð¼Ð¸ÐºÑÐ¾Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ½Ð¾Ð³Ð¾ ÑÐ´ÑÐ° Ð°ÑÑÐ¸ÑÐµÐºÑÑÑÑ RISC-V: Ð¾Ð´Ð½Ð¾ÑÐ°ÐºÑÐ½Ð°Ñ, Ð¼Ð½Ð¾Ð³Ð¾ÑÐ°ÐºÑÐ½Ð°Ñ Ð¸ ÐºÐ¾Ð½Ð²ÐµÐ¹ÐµÑÐ½Ð°Ñ, Ð¿ÑÐ¸ ÑÑÐ¾Ð¼ Ð¸ÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°Ð»Ð¸ÑÑ ÑÑÐµÐ´ÑÑÐ²Ð° Ð°Ð²ÑÐ¾Ð¼Ð°ÑÐ¸Ð·Ð¸ÑÐ¾Ð²Ð°Ð½Ð½Ð¾Ð¹ ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐºÐ¸ ÑÐ¸ÑÑÐ¾Ð²ÑÑ ÑÑÐµÐ¼ Ð½Ð° ÐÐÐÐ¡. Ð ÑÐ¾Ð´Ðµ ÑÑÐ°Ð²Ð½ÐµÐ½Ð¸Ñ Ð´Ð°Ð½Ð½ÑÑ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ð¹ Ð±ÑÐ»Ð¾ Ð¿ÑÐ¸Ð½ÑÑÐ¾ ÑÐµÑÐµÐ½Ð¸Ðµ Ð¸ÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°ÑÑ Ð² Ð´Ð°Ð»ÑÐ½ÐµÐ¹ÑÐµÐ¹ ÑÐ°Ð±Ð¾ÑÐµ ÐºÐ¾Ð½Ð²ÐµÐ¹ÐµÑÐ½Ð¾Ðµ Ð¼Ð¸ÐºÑÐ¾Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ½Ð¾Ðµ ÑÐ´ÑÐ¾. ÐÑÐ¸Ð²ÐµÐ´ÐµÐ½Ð¾ ÑÑÐ°Ð²Ð½ÐµÐ½Ð¸Ðµ ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐ°Ð½Ð½Ð¾Ð³Ð¾ ÐºÐ¾Ð½Ð²ÐµÐ¹ÐµÑÐ½Ð¾Ð³Ð¾ Ð¼Ð¸ÐºÑÐ¾Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ½Ð¾Ð³Ð¾ ÑÐ´ÑÐ° Ñ Ð´ÑÑÐ³Ð¸Ð¼Ð¸ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸ÑÐ¼Ð¸. ÐÑÐµÐ´Ð»Ð¾Ð¶ÐµÐ½Ñ Ð¸ ÑÐµÐ°Ð»Ð¸Ð·Ð¾Ð²Ð°Ð½Ñ Ð²Ð°ÑÐ¸Ð°Ð½ÑÑ ÑÐ»ÑÑÑÐµÐ½Ð¸Ñ ÑÐ°ÑÐ°ÐºÑÐµÑÐ¸ÑÑÐ¸Ðº ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐ°Ð½Ð½Ð¾Ð³Ð¾ Ð¼Ð¸ÐºÑÐ¾Ð¿ÑÐ¾ÑÐµÑÑÐ¾ÑÐ½Ð¾Ð³Ð¾ ÑÐ´ÑÐ°, ÐºÐ¾ÑÐ¾ÑÑÐµ Ð¿Ð¾Ð·Ð²Ð¾Ð»Ð¸Ð»Ð¸ ÑÐ¾ÐºÑÐ°ÑÐ¸ÑÑ ÑÐ°Ð·ÑÑÐ² Ñ Ð´ÑÑÐ³Ð¸Ð¼Ð¸ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸ÑÐ¼Ð¸ Ð² ÑÐ°ÑÑÐ¾ÑÐµ ÑÐ°ÐºÑÐ¾Ð²Ð¾Ð³Ð¾ ÑÐ¸Ð³Ð½Ð°Ð»Ð° Ð½Ð° 47% Ð¸ Ð²Ð¾ Ð²ÑÐµÐ¼ÐµÐ½Ð¸ Ð²ÑÐ¿Ð¾Ð»Ð½ÐµÐ½Ð¸Ñ ÑÐµÑÑÐ¾Ð²Ð¾Ð¹ Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ñ Ð½Ð° 52,5%.
description: In this work, the development path of a digital IC has been reviewed, focusing on logic synthesis and static timing analysis at that time we used several methods to search and analyze information from different sources. Three types of RISC-V architecture microprocessor core microarchitectures were developed and synthesized on FPGA: single-cycle, multi-cycle and pipeline at that time we used tools for computer-aided design of digital circuits on FPGAs. As a result of a comparison of these implementations it was decided to use pipeline microprocessor core in the further work. The developed pipeline microprocessor core is compared with other implementations. Variants of improvement of characteristics of the developed microprocessor core which have allowed to reduce a gap with other realizations in frequency of a clock signal on 47 % and in test program execution time on 52,5 % are offered and realized.