title: ÐÐ¾Ð¼Ð¿Ð°ÑÐ°ÑÐ¾ÑÑ Ð´Ð»Ñ ÐÐ¦Ð Ð¿Ð¾ÑÐ»ÐµÐ´Ð¾Ð²Ð°ÑÐµÐ»ÑÐ½Ð¾Ð³Ð¾ Ð¿ÑÐ¸Ð±Ð»Ð¸Ð¶ÐµÐ½Ð¸Ñ
title: Ð²ÑÐ¿ÑÑÐºÐ½Ð°Ñ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð±Ð°ÐºÐ°Ð»Ð°Ð²ÑÐ°
titleType: Subtitle
title: Comparators used in successive approximation register (SAR) based ADCs
Creators: name: Ð¡Ð¸ÑÐºÐ°ÐµÐ²Ð°, ÐÐ°ÑÐ¸Ñ
Publisher: name: Ð¡Ð°Ð½ÐºÑ-ÐÐµÑÐµÑÐ±ÑÑÐ³ÑÐºÐ¸Ð¹ Ð¿Ð¾Ð»Ð¸ÑÐµÑÐ½Ð¸ÑÐµÑÐºÐ¸Ð¹ ÑÐ½Ð¸Ð²ÐµÑÑÐ¸ÑÐµÑ ÐÐµÑÑÐ° ÐÐµÐ»Ð¸ÐºÐ¾Ð³Ð¾
Year: 2023
Subjects: ÐºÐ¾Ð¼Ð¿Ð°ÑÐ°ÑÐ¾Ñ
Ð°Ð½Ð°Ð»Ð¾Ð³Ð¾-ÑÐ¸ÑÑÐ¾Ð²Ð¾Ð¹ Ð¿ÑÐµÐ¾Ð±ÑÐ°Ð·Ð¾Ð²Ð°ÑÐµÐ»Ñ
Ð±Ð¸ÑÑÐ°Ð±Ð¸Ð»ÑÐ½Ð°Ñ ÑÑÐµÐ¹ÐºÐ°
Ð°ÑÑ Ð¸ÑÐµÐºÑÑÑÐ°
Ð¿ÑÐµÐ´ÑÑÐ¸Ð»Ð¸ÑÐµÐ»Ñ
ÑÐµÐ¿Ð»Ð¾Ð²Ð¾Ð¹ ÑÑÐ¼
ÑÑÐ¼ ÐºÐ²Ð°Ð½ÑÐ¾Ð²Ð°Ð½Ð¸Ñ
ÐÐÐÐ-ÑÑÑÑÐ¾Ð¹ÑÑÐ²Ð¾
Ð»Ð¸Ð½ÐµÐ¹Ð½Ð°Ñ ÑÑ ÐµÐ¼Ð°
Ð´Ð¸ÑÐ¿ÐµÑÑÐ¸Ñ
comparator
analog-to-digital converter
latch
architecture
preamplifier
thermal noise
quantization noise
CMOS device
linear circuit
variance

description: Ð¦ÐµÐ»Ñ ÑÐ°Ð±Ð¾ÑÑ â Ð¾ÑÐµÐ½Ð¸ÑÑ Ð²Ð»Ð¸ÑÐ½Ð¸Ðµ ÑÑÐ¼Ð¾Ð² ÐºÐ¾Ð¼Ð¿Ð°ÑÐ°ÑÐ¾ÑÐ° Ð½Ð° ÑÐ°Ð±Ð¾ÑÑ Ð°Ð½Ð°Ð»Ð¾Ð³Ð¾- ÑÐ¸ÑÑÐ¾Ð²Ð¾Ð³Ð¾ Ð¿ÑÐµÐ¾Ð±ÑÐ°Ð·Ð¾Ð²Ð°ÑÐµÐ»Ñ. ÐÐ¿Ð¸ÑÐ°ÑÑ Ð¼ÐµÑÐ¾Ð´Ð¸ÐºÑ Ð¼Ð¾Ð´ÐµÐ»Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ Ð°Ð½Ð°Ð»Ð¸Ð·Ð° Ð»Ð¸Ð½ÐµÐ¹Ð½Ð¾Ð¹ ÑÐµÐ¿Ð¸ Ð²Ð¾ Ð²ÑÐµÐ¼ÐµÐ½Ð½Ð¾Ð¹ Ð¾Ð±Ð»Ð°ÑÑÐ¸ Ð¿Ð¾ ÑÐ°ÑÑÐ¸ ÑÑÐ¼Ð¾Ð², Ð° ÑÐ°ÐºÐ¶Ðµ Ð¿ÑÐ¾Ð¼Ð¾Ð´ÐµÐ»Ð¸ÑÐ¾Ð²Ð°ÑÑ Ð¸ ÑÑÐ°Ð²Ð½Ð¸ÑÑ ÐºÐ¾Ð¼Ð¿Ð°ÑÐ°ÑÐ¾ÑÑ, Ð½Ð°Ð¸Ð±Ð¾Ð»ÐµÐµ Ð¿Ð¾Ð´ÑÐ¾Ð´ÑÑÐ¸Ðµ Ð´Ð»Ñ Ð¸ÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°Ð½Ð¸Ñ Ð² ÐÐ¦Ð ÐÐ. Ð ÑÐ¾Ð´Ðµ Ð¿Ð¾Ð´Ð³Ð¾ÑÐ¾Ð²ÐºÐ¸ ÐÐÐ  Ð¸ÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°Ð½Ñ Ð¾ÑÐºÑÑÑÑÐµ Ð¾Ð±ÑÐ°Ð·Ð¾Ð²Ð°ÑÐµÐ»ÑÐ½ÑÐµ ÑÐµÑÑÑÑÑ Ð¸ Ð´Ð¾ÑÑÑÐ¿Ð½ÑÐµ Ð±Ð°Ð·Ñ Ð´Ð°Ð½Ð½ÑÑ, Ð¸ÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°Ð½Ñ ÑÑÐµÐ´ÑÑÐ²Ð° Ð°Ð²ÑÐ¾Ð¼Ð°ÑÐ¸Ð·Ð¸ÑÐ¾Ð²Ð°Ð½Ð½Ð¾Ð¹ ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐºÐ¸ Ð¸Ð½ÑÐµÐ³ÑÐ°Ð»ÑÐ½ÑÑ ÑÑÐµÐ¼ (Ð¡ÐÐÐ  Cadence Virtuoso), Ð¿ÑÐ¸Ð¼ÐµÐ½ÐµÐ½Ñ ÑÐ¸ÑÐ»ÐµÐ½Ð½ÑÐµ Ð¼ÐµÑÐ¾Ð´Ñ Ð´Ð»Ñ ÑÐµÑÐµÐ½Ð¸Ñ Ð·Ð°Ð´Ð°Ñ Ð½Ð° Ð¾ÑÐ½Ð¾Ð²Ðµ Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ð½Ð¾Ð³Ð¾ Ð¾Ð±ÐµÑÐ¿ÐµÑÐµÐ½Ð¸Ñ Cadence Virtuoso Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐ°Ð½Ð½ÑÑ Ð¸Ð½ÑÐµÐ³ÑÐ°Ð»ÑÐ½ÑÑ ÑÑÐµÐ¼. Ð ÑÐµÐ·ÑÐ»ÑÑÐ°ÑÐµ ÑÐ°Ð±Ð¾ÑÑ ÑÐ°ÑÑÐ¼Ð¾ÑÑÐµÐ½Ñ Ð¾ÑÐ½Ð¾Ð²Ð½ÑÐµ ÑÐ°ÑÐ°ÐºÑÐµÑÐ¸ÑÑÐ¸ÐºÐ¸ ÐºÐ¾Ð¼Ð¿Ð°ÑÐ°ÑÐ¾ÑÐ¾Ð², Ð¿ÑÐ¾Ð²ÐµÐ´ÐµÐ½ Ð¾Ð±Ð·Ð¾Ñ ÑÐ°Ð·Ð»Ð¸ÑÐ½ÑÑ Ð²Ð°ÑÐ¸Ð°Ð½ÑÐ¾Ð² Ð°ÑÑÐ¸ÑÐµÐºÑÑÑ ÑÐ½ÐµÑÐ³Ð¾ÑÑÑÐµÐºÑÐ¸Ð²Ð½ÑÑ ÐºÐ¾Ð¼Ð¿Ð°ÑÐ°ÑÐ¾ÑÐ¾Ð² Ð¸ ÑÑÐ°Ð²Ð½ÐµÐ½Ð¸Ðµ Ð¸Ñ Ð¿Ð°ÑÐ°Ð¼ÐµÑÑÐ¾Ð², ÑÐ´ÐµÐ»Ð°Ð½Ñ Ð²ÑÐ²Ð¾Ð´Ñ Ð¾ ÑÐµÐ»ÐµÑÐ¾Ð¾Ð±ÑÐ°Ð·Ð½Ð¾ÑÑÐ¸ Ð¿ÑÐ¸Ð¼ÐµÐ½ÐµÐ½Ð¸Ñ ÑÐ°ÐºÐ¸Ñ ÐºÐ¾Ð¼Ð¿Ð°ÑÐ°ÑÐ¾ÑÐ¾Ð² Ð² ÐÐ¦Ð ÐÐ. Ð Ð°ÑÑÐ¼Ð¾ÑÑÐµÐ½Ñ Ð²Ð¸Ð´Ñ ÑÑÐ¼Ð¾Ð² Ð² ÐÐ¦Ð ÐÐ, Ð¿ÑÐ¸Ð²ÐµÐ´ÐµÐ½Ð° ÑÑÐ¼Ð¾Ð²Ð°Ñ Ð¼Ð¾Ð´ÐµÐ»Ñ ÐºÐ¾Ð¼Ð¿Ð°ÑÐ°ÑÐ¾ÑÐ° Ð¸ Ð¾ÑÐµÐ½ÐµÐ½Ñ ÐµÐ³Ð¾ ÑÑÐ¼Ñ, Ð¿ÑÐ¸Ð²ÐµÐ´ÐµÐ½Ð½ÑÐµ ÐºÐ¾ Ð²ÑÐ¾Ð´Ñ. ÐÑÐ¾Ð¼Ð¾Ð´ÐµÐ»Ð¸ÑÐ¾Ð²Ð°Ð½Ñ Ð¸ ÑÑÐ°Ð²Ð½ÐµÐ½Ñ Ð°ÑÑÐ¸ÑÐµÐºÑÑÑÑ Ð´Ð¸Ð½Ð°Ð¼Ð¸ÑÐµÑÐºÐ¸Ñ ÐºÐ¾Ð¼Ð¿Ð°ÑÐ°ÑÐ¾ÑÐ¾Ð² Ð´Ð»Ñ ÐÐ¦Ð ÐÐ.
description: The aim is to evaluate the effect of comparator noise on the operation of the analog-to-digital converter. Describe the methodology for modeling the analysis of a linear circuit in the time domain. Simulate and compare the most and least suitable for ADC comparators. During the preparation of the thesis, open educational resources and accessible databases were used, automated integrated circuit development tools (Cadence Virtuoso CAD) were used, numerical methods were applied to solve problems based on Cadence Virtuoso software for modeling the developed integrated circuits. As a result of the study, the main characteristics of comparators are considered, a review of various architectures of energy-efficient comparators and a comparison of their parameters is carried out, conclusions are drawn about the feasibility of using such comparators in a SAR ADC. The types of noise in a SAR ADC are considered, a noise model of the comparator is given, and its noise brought to the input is estimated. The architectures of dynamic comparators for successive approximation register based ADCs are modeled and compared.