title: Ð ÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ñ ÑÐ¸Ð½ÑÐµÐ·Ð°ÑÐ¾ÑÐ° ÑÐ¸Ð³Ð½Ð°Ð»Ð¾Ð² Ð½Ð° ÑÐ·ÑÐºÐµ SystemVerilog
title: Ð²ÑÐ¿ÑÑÐºÐ½Ð°Ñ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð±Ð°ÐºÐ°Ð»Ð°Ð²ÑÐ°
titleType: Subtitle
title: Implementation of the architecture of a direct digital synthesizer of sygnals on FPGA as part of the Kintex UltraScale family of SoC
Creators: name: ÐÐ¾ÑÐºÐ¾Ð², Ð¡ÐµÐ¼ÐµÐ½
Publisher: name: Ð¡Ð°Ð½ÐºÑ-ÐÐµÑÐµÑÐ±ÑÑÐ³ÑÐºÐ¸Ð¹ Ð¿Ð¾Ð»Ð¸ÑÐµÑÐ½Ð¸ÑÐµÑÐºÐ¸Ð¹ ÑÐ½Ð¸Ð²ÐµÑÑÐ¸ÑÐµÑ ÐÐµÑÑÐ° ÐÐµÐ»Ð¸ÐºÐ¾Ð³Ð¾
Year: 2024
Subjects: ÐÐÐÐ¡
ÑÐ¸ÑÑÐ¾Ð²Ð¾Ð¹ Ð²ÑÑÐ¸ÑÐ»Ð¸ÑÐµÐ»ÑÐ½ÑÐ¹ ÑÐ¸Ð½ÑÐµÐ·Ð°ÑÐ¾Ñ
ÑÐ°Ð·Ð¾Ð²ÑÐ¹ Ð°ÐºÐºÑÐ¼ÑÐ»ÑÑÐ¾Ñ
Ð¿ÑÐµÐ¾Ð±ÑÐ°Ð·Ð¾Ð²Ð°Ð½Ð¸Ðµ ÑÐ°Ð·Ñ Ð² Ð°Ð¼Ð¿Ð»Ð¸ÑÑÐ´Ñ
ÑÑÐµÑÐµÐ½Ð¸Ðµ ÑÐ°Ð·Ñ
ÐÐÐ¡Ð¡
Ð»Ð¸Ð½ÐµÐ¹Ð½Ð°Ñ Ð¸Ð½ÑÐµÑÐ¿Ð¾Ð»ÑÑÐ¸Ñ
SNR
SFDR
LUT
DSP
FF
BRAM
FPGA
direct digital synthesizer
phase battery
phase to amplitude conversion
linear interpolation

description: ÐÐ±ÑÐµÐºÑ Ð¸ÑÑÐ»ÐµÐ´Ð¾Ð²Ð°Ð½Ð¸Ñ â ÑÐ¸ÑÑÐ¾Ð²Ð¾Ð¹ Ð²ÑÑÐ¸ÑÐ»Ð¸ÑÐµÐ»ÑÐ½ÑÐ¹ ÑÐ¸Ð½ÑÐµÐ·Ð°ÑÐ¾Ñ Ð½Ð° ÐÐÐÐ¡ Ð² ÑÐ¾ÑÑÐ°Ð²Ðµ Ð¡Ð½Ð ÑÐµÐ¼ÐµÐ¹ÑÑÐ²Ð° Kintex Ultrascale. Ð¦ÐµÐ»Ñ ÑÐ°Ð±Ð¾ÑÑ â ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ñ Ð°ÑÑÐ¸ÑÐµÐºÑÑÑÑ ÑÐ¸ÑÑÐ¾Ð²Ð¾Ð³Ð¾ Ð²ÑÑÐ¸ÑÐ»Ð¸ÑÐµÐ»ÑÐ½Ð¾Ð³Ð¾ ÑÐ¸Ð½ÑÐµÐ·Ð°ÑÐ¾ÑÐ°, Ð¾Ð±ÐµÑÐ¿ÐµÑÐ¸Ð²Ð°ÑÑÐµÐ³Ð¾ Ð³ÐµÐ½ÐµÑÐ¸ÑÐ¾Ð²Ð°Ð½Ð¸Ðµ ÑÐ¸Ð½ÑÑÐ¾Ð¸Ð´Ð°Ð»ÑÐ½Ð¾Ð³Ð¾ ÑÐ¸Ð³Ð½Ð°Ð»Ð° Ñ Ð²ÐµÐ»Ð¸ÑÐ¸Ð½Ð°Ð¼Ð¸ SNR, SFDR Ð½Ðµ Ð¼ÐµÐ½ÐµÐµ 98 Ð´Ð, Ð¾Ð±ÐµÑÐ¿ÐµÑÐ¸Ð²Ð°ÑÑÐµÐ³Ð¾ Ð»Ð¸Ð½ÐµÐ¹Ð½Ð¾-ÑÐ°ÑÑÐ¾ÑÐ½ÑÑ Ð¼Ð¾Ð´ÑÐ»ÑÑÐ¸Ñ, ÑÐ°Ð·Ð¾ÐºÐ¾Ð´Ð¾Ð²ÑÑ Ð¼Ð°Ð½Ð¸Ð¿ÑÐ»ÑÑÐ¸Ñ, ÑÐ°Ð±Ð¾ÑÑ Ð² Ð¸Ð¼Ð¿ÑÐ»ÑÑÐ½Ð¾Ð¼ ÑÐµÐ¶Ð¸Ð¼Ðµ. Ð ÑÐ¾Ð´Ðµ Ð¸ÑÑÐ»ÐµÐ´Ð¾Ð²Ð°Ð½Ð¸Ñ Ð² ÑÑÐµÐ´Ðµ MATLAB Ð¿ÑÐ¾Ð²ÐµÐ´ÐµÐ½Ð¾ Ð¼Ð¾Ð´ÐµÐ»Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ðµ ÑÐ°Ð±Ð¾ÑÑ Ð¦ÐÐ¡ Ñ Ð´Ð²ÑÐ¼Ñ ÑÐ°Ð·Ð»Ð¸ÑÐ½ÑÐ¼Ð¸ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸ÑÐ¼Ð¸ Ð°ÑÑÐ¸ÑÐµÐºÑÑÑÑ, Ð´Ð»Ñ ÐºÐ°Ð¶Ð´Ð¾Ð¹ Ð¸Ð· ÐºÐ¾ÑÐ¾ÑÑÑ Ð¿Ð¾Ð»ÑÑÐµÐ½Ñ Ð·Ð°Ð²Ð¸ÑÐ¸Ð¼Ð¾ÑÑÐ¸ ÑÐ°ÐºÐ¸Ñ ÑÑÐ¼Ð¾Ð²ÑÑ Ð¿Ð°ÑÐ°Ð¼ÐµÑÑÐ¾Ð² Ð³ÐµÐ½ÐµÑÐ¸ÑÑÐµÐ¼Ð¾Ð¹ ÑÐ¸Ð½ÑÑÐ¾Ð¸Ð´Ñ ÐºÐ°Ðº SFDR Ð¸ SNR Ð¾Ñ ÑÐ°Ð·ÑÑÐ´Ð½Ð¾ÑÑÐ¸ ÑÐ¾ÑÑÐ°Ð½ÐµÐ½Ð½ÑÑ Ð² Ð¿Ð°Ð¼ÑÑÐ¸ Ð¾ÑÑÑÐµÑÐ¾Ð² ÑÐ¸Ð³Ð½Ð°Ð»Ð°. ÐÑÐ¾Ð²ÐµÐ´ÐµÐ½Ð¾ ÑÑÐ°Ð²Ð½ÐµÐ½Ð¸Ðµ Ð´Ð²ÑÑ Ð°ÑÑÐ¸ÑÐµÐºÑÑÑ Ð¦ÐÐ¡ Ð¿Ð¾ ÐºÑÐ¸ÑÐµÑÐ¸Ñ ÑÐ¾Ð¾ÑÐ²ÐµÑÑÑÐ²Ð¸Ñ Ð·Ð°Ð´Ð°Ð½Ð½ÑÐ¼ Ð·Ð½Ð°ÑÐµÐ½Ð¸ÑÐ¼ SFDR, SNR, Ð° ÑÐ°ÐºÐ¶Ðµ Ð¿Ð¾ ÐºÑÐ¸ÑÐµÑÐ¸Ñ Ð·Ð°ÑÑÐ°ÑÐµÐ½Ð½ÑÑ ÑÐµÑÑÑÑÐ¾Ð². ÐÐ· Ð´Ð²ÑÑ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ð¹ Ð°ÑÑÐ¸ÑÐµÐºÑÑÑ ÑÐ¸Ð½ÑÐµÐ·Ð°ÑÐ¾ÑÐ° Ð±ÑÐ»Ð° Ð¾Ð¿ÑÐµÐ´ÐµÐ»ÐµÐ½Ð° ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ñ, ÑÐ´Ð¾Ð²Ð»ÐµÑÐ²Ð¾ÑÑÑÑÐ°Ñ Ð·Ð°Ð´Ð°Ð½Ð½ÑÐ¼ Ð·Ð½Ð°ÑÐµÐ½Ð¸ÑÐ¼ SFDR, SNR Ð¸ Ð·Ð°ÑÑÐ°ÑÐ¸Ð²Ð°ÑÑÐ°Ñ Ð¿ÑÐ¸ ÑÑÐ¾Ð¼ Ð¼ÐµÐ½ÑÑÐµÐµ ÐºÐ¾Ð»Ð¸ÑÐµÑÑÐ²Ð¾ ÑÐµÑÑÑÑÐ¾Ð². ÐÐ°Ð½Ð½Ð°Ñ Ð°ÑÑÐ¸ÑÐµÐºÑÑÑÐ° Ð¦ÐÐ¡ Ð±ÑÐ»Ð° ÑÐµÐ°Ð»Ð¸Ð·Ð¾Ð²Ð°Ð½Ð° Ð½Ð° ÑÐ·ÑÐºÐµ SystemVerilog. ÐÑÐ¾Ð²ÐµÐ´ÐµÐ½Ð¾ Ð¼Ð¾Ð´ÐµÐ»Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ðµ ÑÐµÐ°Ð»Ð¸Ð·Ð¾Ð²Ð°Ð½Ð½Ð¾Ð¹ Ð°ÑÑÐ¸ÑÐµÐºÑÑÑÑ Ð² ÑÑÐµÐ´Ðµ Vivado, Ð¾Ð¿ÑÐµÐ´ÐµÐ»ÐµÐ½Ñ Ð·Ð°ÑÑÐ°ÑÐµÐ½Ð½ÑÐµ ÑÐµÑÑÑÑÑ. Ð ÐµÐ°Ð»Ð¸Ð·Ð¾Ð²Ð°Ð½Ð½Ð°Ñ Ð¦ÐÐ¡ Ð¾Ð±ÐµÑÐ¿ÐµÑÐ¸Ð²Ð°ÐµÑ Ð³ÐµÐ½ÐµÑÐ¸ÑÐ¾Ð²Ð°Ð½Ð¸Ðµ ÑÐ¸Ð½ÑÑÐ¾Ð¸Ð´Ñ, ÐÐ§Ð-ÑÐ¸Ð³Ð½Ð°Ð»Ð¾Ð², Ð¤ÐÐ-ÑÐ¸Ð³Ð½Ð°Ð»Ð¾Ð², ÑÐ°Ð±Ð¾ÑÑ Ð² Ð¸Ð¼Ð¿ÑÐ»ÑÑÐ½Ð¾Ð¼ ÑÐµÐ¶Ð¸Ð¼Ðµ. Ð ÐµÐ°Ð»Ð¸Ð·Ð¾Ð²Ð°Ð½Ð½Ð°Ñ Ð°ÑÑÐ¸ÑÐµÐºÑÑÑÐ° Ð¿Ð¾Ð·Ð²Ð¾Ð»ÑÐµÑ ÑÐ¸Ð½ÑÐµÐ·Ð¸ÑÐ¾Ð²Ð°ÑÑ ÑÐ¸Ð½ÑÑÐ¾Ð¸Ð´Ð°Ð»ÑÐ½ÑÐµ ÑÐ¸Ð³Ð½Ð°Ð»Ñ Ñ Ð½Ð¸Ð·ÐºÐ¸Ð¼ ÑÑÐ¾Ð²Ð½ÐµÐ¼ ÑÑÐ¼Ð¾Ð² Ð² ÑÐ¿ÐµÐºÑÑÐµ Ð³ÐµÐ½ÐµÑÐ¸ÑÑÐµÐ¼Ð¾Ð³Ð¾ ÑÐ¸Ð³Ð½Ð°Ð»Ð°, Ð½Ð° ÐµÐµ Ð¾ÑÐ½Ð¾Ð²Ðµ Ð¼Ð¾Ð¶ÐµÑ Ð±ÑÑÑ ÑÐ¾Ð·Ð´Ð°Ð½Ð° ÑÐ¸ÑÑÐµÐ¼Ð° Ð³ÐµÐ½ÐµÑÐ¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ Ð·Ð¾Ð½Ð´Ð¸ÑÑÑÑÐ¸Ñ Ð¸Ð¼Ð¿ÑÐ»ÑÑÐ¾Ð².
description: The object of research is a direct digital synthesizer based on FPGA as part of the Kintex Ultrascale family of SoC. The purpose of the work is to implement the architecture of a direct digital synthesizer that provides the generation of a sinusoidal signal with SNR, SFDR values of at least 98 dB, providing linear frequency modulation, phase-code manipulation, and operation in pulse mode. In the course of the study, in the MATLAB environment, a simulation of the operation of a DDS with two different architecture implementations was carried out, for each of which the dependences of such noise parameters of the generated sine wave as SFDR and SNR on the bit depth of the signal samples stored in memory were obtained. A comparison of two DDS architectures was carried out according to the criterion of compliance with the specified values of SFDR, SNR, as well as according to the criterion of resources spent. Of the two implementations of synthesizer architectures, an implementation was determined that satisfies the specified values of SFDR, SNR and at the same time consumes fewer resources. This DDS architecture was implemented in the SystemVerilog language. The simulation of the implemented architecture in the Vivado environment was carried out, and the resources spent were determined. The implemented DDS provides the generation of sinusoids, LFM signals, PSK signals, and operation in pulse mode. The implemented architecture allows synthesizing sinusoidal signals with a low noise level in the spectrum of the generated signal, based on it.