title: ÐÐ²ÑÐ¾Ð¼Ð°ÑÐ¸Ð·Ð°ÑÐ¸Ñ Ð¿ÑÐ¾ÐµÐºÑÐ¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ Ð´Ð¸ÑÐºÑÐµÑÐ½ÑÑ ÑÑÑÑÐ¾Ð¹ÑÑÐ². ÐÑÐ¾ÐµÐºÑÐ¸ÑÐ¾Ð²Ð°Ð½Ð¸Ðµ Ð² ÑÑÐµÐ´Ðµ QUARTUS PRIME. ÐÐ°Ð±Ð¾ÑÐ°ÑÐ¾ÑÐ½ÑÐ¹ Ð¿ÑÐ°ÐºÑÐ¸ÐºÑÐ¼
title: ÑÑÐµÐ±Ð½Ð¾Ðµ Ð¿Ð¾ÑÐ¾Ð±Ð¸Ðµ
titleType: Subtitle
Creators: name: ÐÐ½ÑÐ¾Ð½Ð¾Ð², ÐÐ»ÐµÐºÑÐ°Ð½Ð´Ñ
name: ÐÐ°Ð¼ÑÑÐ¾Ð²Ð°, ÐÐ»ÑÐ³Ð°
name: Ð¤ÐµÐ´Ð¾ÑÐ¾Ð², ÐÐ»ÐµÐºÑÐ°Ð½Ð´Ñ
name: Ð¤Ð¸Ð»Ð¸Ð¿Ð¿Ð¾Ð², ÐÐ»ÐµÐºÑÐµÐ¹
Publisher: name: ÐÐ·Ð´-Ð²Ð¾ ÐÐ¾Ð»Ð¸ÑÐµÑÐ½. ÑÐ½-ÑÐ°
Year: 2018
Subjects: ÐÑÑÐ¸ÑÐ»Ð¸ÑÐµÐ»ÑÐ½ÑÐµ Ð¼Ð°ÑÐ¸Ð½Ñ ÑÐ»ÐµÐºÑÑÐ¾Ð½Ð½ÑÐµ
Ð¢ÐµÑ Ð½Ð¸ÑÐµÑÐºÐ¸Ðµ ÑÐ¸ÑÑÐµÐ¼Ñ
ÐÐ¾Ð³Ð¸ÑÐµÑÐºÐ¸Ðµ ÑÑ ÐµÐ¼Ñ

description: ÐÐ°Ð±Ð¾ÑÐ°ÑÐ¾ÑÐ½ÑÐ¹ Ð¿ÑÐ°ÐºÑÐ¸ÐºÑÐ¼ Ð¿ÑÐµÐ´Ð½Ð°Ð·Ð½Ð°ÑÐµÐ½ Ð´Ð»Ñ Ð·Ð½Ð°ÐºÐ¾Ð¼ÑÑÐ²Ð° Ñ Ð¾ÑÐ½Ð¾Ð²Ð°Ð¼Ð¸ Ð¿ÑÐ¾ÐµÐºÑÐ¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ Ð²
ÑÑÐµÐ´Ðµ Quartus Prime, Ð¸ÑÐ¿Ð¾Ð»ÑÐ·ÑÐµÐ¼Ð¾Ð¹ Ð´Ð»Ñ ÑÐ¾Ð·Ð´Ð°Ð½Ð¸Ñ ÑÐ¸ÑÑÐ¾Ð²ÑÑ ÑÑÑÑÐ¾Ð¹ÑÑÐ² Ð½Ð° Ð±Ð°Ð·Ðµ Ð¡ÐÐÐ¡ Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ð¸ÑÑÐµÐ¼Ð¾Ð¹ Ð»Ð¾Ð³Ð¸ÐºÐ¸ (Ð¡ÐÐÐ¡ ÐÐ) ÐºÐ¾Ð¼Ð¿Ð°Ð½Ð¸Ð¸ Intel (Altera). ÐÐ°ÑÐ°Ð»ÑÐ½ÑÐµ Ð»Ð°Ð±Ð¾ÑÐ°ÑÐ¾ÑÐ½ÑÐµ ÑÐ°Ð±Ð¾ÑÑ
Ð¿Ð¾ÑÐ²ÑÑÐµÐ½Ñ Ð²Ð¾Ð¿ÑÐ¾ÑÐ°Ð¼ ÑÐ¾Ð·Ð´Ð°Ð½Ð¸Ñ Ð¸ Ð½Ð°ÑÑÑÐ¾Ð¹ÐºÐ¸ Ð¿ÑÐ¾ÐµÐºÑÐ¾Ð², Ð¸ÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°Ð½Ð¸Ñ ÐºÐ°ÑÐ°Ð»Ð¾Ð³Ð° IP-Ð±Ð»Ð¾ÐºÐ¾Ð², Ð°
ÑÐ°ÐºÐ¶Ðµ Ð°Ð½Ð°Ð»Ð¸Ð·Ð° ÑÐµÐ·ÑÐ»ÑÑÐ°ÑÐ¾Ð² ÐºÐ¾Ð¼Ð¿Ð¸Ð»ÑÑÐ¸Ð¸ Ð¿ÑÐ¾ÐµÐºÑÐ¾Ð². Ð£ÑÐ»Ð¾Ð¶Ð½ÐµÐ½Ð½ÑÐµ Ð»Ð°Ð±Ð¾ÑÐ°ÑÐ¾ÑÐ½ÑÐµ ÑÐ°Ð±Ð¾ÑÑ Ð¾ÑÐ²Ð°ÑÑÐ²Ð°ÑÑ Ð²Ð¾Ð¿ÑÐ¾ÑÑ, ÑÐ²ÑÐ·Ð°Ð½Ð½ÑÐµ Ñ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸ÐµÐ¹ ÑÑÑÑÐ¾Ð¹ÑÑÐ² Ð² Ð¡ÐÐÐ¡ ÐÐ: ÑÐ¾Ð·Ð´Ð°Ð½Ð¸Ðµ Ð¸ÐµÑÐ°ÑÑÐ¸ÑÐµÑÐºÐ¸Ñ
Ð¾Ð¿Ð¸ÑÐ°Ð½Ð¸Ð¹ ÑÑÑÑÐ¾Ð¹ÑÑÐ² Ñ Ð¸ÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°Ð½Ð¸ÐµÐ¼ ÑÑÐµÐ¼Ð½Ð¾Ð³Ð¾ Ð²Ð²Ð¾Ð´Ð°, ÑÐ·ÑÐºÐ¾Ð² Ð¾Ð¿Ð¸ÑÐ°Ð½Ð¸Ñ Ð°Ð¿Ð¿Ð°ÑÐ°ÑÑÑÑ Ð¸ IP-
Ð±Ð»Ð¾ÐºÐ¾Ð², Ð¼Ð¾Ð´ÐµÐ»Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ðµ ÑÐ°Ð±Ð¾ÑÑ ÑÑÑÑÐ¾Ð¹ÑÑÐ², ÐºÐ¾Ð½ÑÐ¸Ð³ÑÑÐ°ÑÐ¸Ñ Ð¡ÐÐÐ¡ ÐÐ ÑÐµÐ¼ÐµÐ¹ÑÑÐ²Ð° Cyclone V Ð¸
Ð¾ÑÐ»Ð°Ð´ÐºÐ° ÑÐ°Ð±Ð¾ÑÑ ÑÑÑÑÐ¾Ð¹ÑÑÐ² Ð½Ð° Ð¿Ð»Ð°ÑÐµ DE1-SoC. Ð Ð·Ð°ÐºÐ»ÑÑÐ¸ÑÐµÐ»ÑÐ½Ð¾Ð¼ Ð¿ÑÐ¾ÐµÐºÑÐµ Ð´Ð»Ñ Ð·Ð°ÐºÑÐµÐ¿Ð»ÐµÐ½Ð¸Ñ
Ð¿Ð¾Ð»ÑÑÐµÐ½Ð½ÑÑ ÑÐ¼ÐµÐ½Ð¸Ð¹ Ð¸ Ð½Ð°Ð²ÑÐºÐ¾Ð² ÑÑÐ°Ð²Ð¸ÑÑÑ Ð·Ð°Ð´Ð°ÑÐ° ÑÐ¾Ð·Ð´Ð°Ð½Ð¸Ñ ÑÑÐ½ÐºÑÐ¸Ð¾Ð½Ð°Ð»ÑÐ½Ð¾-ÑÐ»Ð¾Ð¶Ð½Ð¾Ð³Ð¾ ÑÑÑÑÐ¾Ð¹ÑÑÐ²Ð°. ÐÑÐ¿Ð¾Ð»Ð½ÐµÐ½Ð¸Ðµ Ð²ÑÐµÑ Ð»Ð°Ð±Ð¾ÑÐ°ÑÐ¾ÑÐ½ÑÑ ÑÐ°Ð±Ð¾Ñ ÑÐ°ÑÑÑÐ¸ÑÐ°Ð½Ð¾ Ð½Ð° Ð¸ÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°Ð½Ð¸Ðµ Quartus Prime
Standard (Ð¸Ð»Ð¸ Lite) Edition Ð²ÐµÑÑÐ¸Ð¸ 15.1.
ÐÐ»Ñ ÑÑÑÐ´ÐµÐ½ÑÐ¾Ð², Ð¾Ð±ÑÑÐ°ÑÑÐ¸ÑÑÑ Ð¿Ð¾ Ð½Ð°Ð¿ÑÐ°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¿Ð¾Ð´Ð³Ð¾ÑÐ¾Ð²ÐºÐ¸ 09.03.01 Â«ÐÐ½ÑÐ¾ÑÐ¼Ð°ÑÐ¸ÐºÐ° Ð¸ Ð²ÑÑÐ¸ÑÐ»Ð¸ÑÐµÐ»ÑÐ½Ð°Ñ ÑÐµÑÐ½Ð¸ÐºÐ°Â», Ð° ÑÐ°ÐºÐ¶Ðµ ÑÑÑÐ´ÐµÐ½ÑÐ¾Ð² Ð´ÑÑÐ³Ð¸Ñ ÑÐ¿ÐµÑÐ¸Ð°Ð»ÑÐ½Ð¾ÑÑÐµÐ¹, Ð¸Ð·ÑÑÐ°ÑÑÐ¸Ñ Ð´Ð¸ÑÑÐ¸Ð¿Ð»Ð¸Ð½Ñ
Â«ÐÐ²ÑÐ¾Ð¼Ð°ÑÐ¸Ð·Ð°ÑÐ¸Ñ Ð¿ÑÐ¾ÐµÐºÑÐ¸ÑÐ¾Ð²Ð°Ð½Ð¸Ñ Ð´Ð¸ÑÐºÑÐµÑÐ½ÑÑ ÑÑÑÑÐ¾Ð¹ÑÑÐ²Â» Ð½Ð° Ð°Ð½Ð³Ð»Ð¸Ð¹ÑÐºÐ¾Ð¼ ÑÐ·ÑÐºÐµ.
description: The objective for the Digital Electronic Design Automation course is to teach the fundamentals of computer-aided design flow for digital circuits using Intel FPGA technologies and Quartus Prime software. Basic Exercises introduce the concepts of project, IP Catalog, and compilation flow. Intermediate Exercises focus on the details of FPGA-based implementation, including hierarchical design entry using schematic and HDL descriptions, as well as IP-cores, design simulation flow, Cyclone V FPGA configuration, and debug using DEl-SoC development board. The Final Project presents a complex problem, which highlights the know-how of digital circuit design. All the exercises require Quartus Prime Standard (or Lite) Edition v 15.1. This exercise manual targets students, who study the Digital Electronic Design Automation course (in English) in a Computers and Information Science program.