Single rail ternary null convention logic architecture for digital signal processing applications
Creators: name: ANDRAWES, Sameh
Publisher: name: RMIT University
Year: 2024
Subjects: classificationCode: 400908
subject: Microelectronics

description: Synchronous design techniques have been used for decades to design and implement digital systems mainly due to their simplicity and the ready availability of sophisticated tools. While these techniques offer many advantages there are also some disadvantages. Issues such as clock skew and the need for high power clock drivers to generate the required global clock may result in large area and high dynamic power consumption. In contrast, asynchronous techniques eliminate the need for a global clock along with its associated drivers and offer a promising path to overcome many of the problems with synchronous design.

While there are many different techniques and architectures that can be used to create asynchronous digital systems, Null Convention Logic is considered one of the more effective methods due to its straightforward 'structural' approach to design, being based on a predefined library of majority logic (threshold) gates. Just as for any other asynchronous digital design technique, Null Convention Logic eliminates the need for a high frequency global clock, replacing it with localised handshaking signals. This may lead to lower power consumption in some circumstances and the gate library approach does not require the sort of complicated timing analysis required by other methodologies, including synchronous. A Null Convention Logic design can therefore be 'correct by construction', with its overall performance adjusting automatically to suit changes in operating conditions due to process variability, supply voltage and/or temperature.

On the other hand, there are various drawbacks. Null Convention Logic relies on multi-rail signals, where each individual logic bit can be represented by a dual or quad-rail, two or four wires respectively. While multi-rail logic in NCL may simplify path logic in some cases, it invariably results in greater area and also supports the generation of illegal states. For instance, in both dual-rail and quad-rail systems, the rails must be mutually exclusive, such that they can never be asserted simultaneously. This type of illegal state may occur within high speed, low power system on chip (SOC) implementations due to system noise or delays caused by variable interconnection lengths or unbalanced fanouts.

This research proposes and analyses the concept of using single-rail, ternary logic to represent the three levels required to define Null Convention Logic i.e., Data-One, Null and Data-Zero. The architecture is implemented using two different CMOS technology processes and voltage level mappings to demonstrate that is largely technology independent. Two different versions are presented in this work: register-controlled and register-less ternary. The more conventional register controlled ternary NCL system relies on the use of the ternary delay insensitive registers to control the flow of the data in the pipeline. The 'register-free' implementation eliminates the additional pipeline registers, which helps to reduce both the total design area as well as its power consumption. Both designs propagate data only and do not need to propagate Null thereby enhancing the performance of the design by eliminating the Null cycle propagation.

A representative example of a Short Word Length Digital Finite Impulse Response Low Pass Filter is used to demonstrate that the Single-Rail Ternary Logic approach can be used to design and implement a sophisticated NCL system. The system was designed and implemented at the CMOS transistor level and the three alternative architectures, dual-rail Binary Logic NCL, register-controlled Single-Rail Ternary Logic NCL and register-less Single-Rail Ternary Logic NCL, were compared in terms of total design area, power consumption and design performance. The register-less ternary NCL example system exhibited an approximately 30% reduction in both area and propagation delay, at the cost of a significant increase in power compared to dual rail binary NCL. The register-less ternary system has reduced both power consumption and design area by almost 2.5% and 8% respectively compared to the register-controlled ternary version. These comparisons indicate that both register-controlled and register-less Single-Rail Ternary Logic NCL can reduce the design area, as each signal is represented by only one wire, and at the same time can enhance system performance. However, as the conventional dual-rail Binary Logic NCL still exhibits much lower overall power consumption, the main advantage of the two proposed Single-Rail Ternary Logic NCL architectures are their slightly higher performance and the elimination of illegal state that can otherwise occur. They also offer a means to save area where this is a key design parameter.