title: ÐÐ¿ÑÐ¸Ð¼Ð¸Ð·Ð°ÑÐ¸Ñ Ð²Ð½ÑÑÑÐ¸-ÐºÑÐ¸ÑÑÐ°Ð»ÑÐ½ÑÑ ÐÐ¡ Ð Ð Ð¿ÑÐ¸ Ð¸Ð¼Ð¿Ð»ÐµÐ¼ÐµÐ½ÑÐ°ÑÐ¸Ð¸ Ð² ÐÐÐÐ¡
title: Ð²ÑÐ¿ÑÑÐºÐ½Ð°Ñ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð±Ð°ÐºÐ°Ð»Ð°Ð²ÑÐ°
titleType: Subtitle
title: Optimization of on-chip RTOS when implemented in FPGA
Creators: name: ÐÐ¸Ð»ÑÐ´ÐµÐµÐ², Ð ÑÑÑÐ°Ð¼
Publisher: name: Ð¡Ð°Ð½ÐºÑ-ÐÐµÑÐµÑÐ±ÑÑÐ³ÑÐºÐ¸Ð¹ Ð¿Ð¾Ð»Ð¸ÑÐµÑÐ½Ð¸ÑÐµÑÐºÐ¸Ð¹ ÑÐ½Ð¸Ð²ÐµÑÑÐ¸ÑÐµÑ ÐÐµÑÑÐ° ÐÐµÐ»Ð¸ÐºÐ¾Ð³Ð¾
Year: 2023
Subjects: Ð°Ð¿Ð¿Ð°ÑÐ°ÑÐ½Ð°Ñ Ð¾Ð¿ÑÐ¸Ð¼Ð¸Ð·Ð°ÑÐ¸Ñ
ÐÐÐÐ¡
ÐÐ¡Ð Ð
ÑÐ¸ÑÑÐµÐ¼Ð½ÑÐ¹ ÑÐ¸Ðº
VHDL
C
C++
hardware optimization
FPGA
RTOS
system tick

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description: The graduate qualification work is devoted to the development of optimization of real-time operating system at its implementation in the hardware, fully implemented on the programmable logic integrated circuit. A study of various RTOS operating systems to identify common components and parts that can be implemented on the FPGA logic elements was conducted. Based on this, variants of hardware optimizations that can be applied to different systems were proposed, weaknesses were explained, the architecture and possible modifications for different use cases were demonstrated. An optimization was developed in the form of a hardware scheduler in VHDL language in Quartus Prime Standard Edition environment with the command system, and the code of the real-time operating system kernel was modified to interact with it. To simplify the testing process, a program was written in C++ that generates test code for multiple tasks depending on different parameters. The results were analyzed and showed that the time to reschedule and process the tasks decreased and became constant. The developed optimization can be applied to different RTOS by modifying their kernel code.