40th VI-HPS Tuning Workshop
Creators: name: Dr. Volker Weinberg
Publisher: name: Zenodo
Year: 2021
Subjects: HPC
Tuning Workshop
MPI profiling
automated trace analysis
Scalasca
Training Material

description: Goals This workshop organised by VI-HPS and LRZ as a PRACE training event will: give an overview of the VI-HPS programming tools suite explain the functionality of individual tools, and how to use them effectively offer hands-on experience and expert assistance using the tools On completion participants should be familiar with common performance analysis and diagnosis techniques and how they can be employed in practice (on a range of HPC systems). Those who prepared their own application test cases will have been coached in the tuning of their measurement and analysis, and provided optimization suggestions. Programme Overview Presentations and hands-on sessions are planned on the following topics: Setting up, welcome and introduction mpiP lightweight MPI profiling TAU performance system MAQAO performance analysis &amp; optimisation Score-P instrumentation and measurement Scalasca automated trace analysis Paraver/Extrae/Dimemas trace analysis and performance prediction Extra-P automated performance modeling [k]cachegrind cache utilisation analysis ... and potentially others to be added A brief overview of the capabilities of these and associated tools is provided in the VI-HPS Tools Guide. The workshop will be held in English and run from 09:00 to not later than 18:00 each day, with breaks. Participants are encouraged to prepare their own MPI, OpenMP and hybrid MPI+OpenMP parallel application codes for analysis. Programme in Detail (provisional) - all times given as CEST (UTC+2) <strong>Day 1</strong>: <strong><em>Monday 14 June</em></strong> 09:00 <strong>Welcome </strong>[Volker Weinberg] <strong>Introduction to Zoom</strong> <strong>The IvyMUC system</strong> <strong>Introduction to VI-HPS &amp; overview of tools </strong>[Valensi] <strong>Introduction to parallel performance engineering</strong> <strong>Building and running NPB/BT-MZ on IvyMUC </strong>[Knobloch] 10:30 <em><em>(break)</em></em> 11:00 <strong>Preparation of participants' own codes on IvyMUC</strong> 12:30 <em>(lunch)</em> 14:00 <strong>kCachegrind cache utilisation analysis</strong> [Josef Weidendorfer, LRZ] 15:30 <em>(break)</em> 16:00 <strong>Hands-on coaching</strong> to apply kCachegrind to analyze participants' own code(s). 17:30 Review of day and schedule for remainder of workshop 18:00 <em>(adjourn)</em> <strong>Day 2</strong>: <strong><em>Tuesday 15 June</em></strong> 09:00 <strong>MAQAO performance analysis tools</strong> [Jäsper Ibnamar &amp; Emmanuel Oseret, UVSQ] <strong>MAQAO hands-on exercises</strong> (MAQAO quick reference) 10:30 <em><em>(break)</em></em> 11:00 <strong>BSC performance tools</strong> [Judit Giménez &amp; Lau Mercadal, BSC] <strong>Tools installation</strong> <strong>BSC tools hands-on exercises</strong> 12:30 <em>(lunch)</em> 14:00 <strong>Hands-on coaching</strong> to apply MAQAO to analyze participants' own code(s). 15:30 <em><em>(break)</em></em> 16:00 <strong>Hands-on coaching</strong> to apply Paraver to analyze participants' own code(s). 17:30 Schedule for remainder of workshop 18:00 <em>(adjourn)</em> <strong>Day 3</strong>: <strong><em>Wednesday 16 June</em></strong> 09:00 <strong>Score-P instrumentation &amp; measurement toolset</strong> [Brian Wylie, Michael Knobloch &amp; Radita Liem, JSC] <strong>Score-P analysis scoring &amp; measurement filtering</strong> <strong>Score-P hands-on exercises</strong> <strong>CUBE profile explorer hands-on exercises</strong> 10:30 <em><em>(break)</em></em> 11:00 <strong>Score-P specialized instrumentation and measurement</strong> [Brian Wylie, Michael Knobloch &amp; Radita Liem, JSC] <strong>Score-P hands-on exercises</strong> 12:30 <em>(lunch)</em> 14:00 <strong>Hands-on coaching</strong> to apply Score-P/CUBE to analyze participants' own code(s). 15:30 <em><em>(break)</em></em> 16:00 <strong>TAU performance system</strong> [Sameer Shende, UOregon] <strong>TAU hands-on exercises</strong> 17:30 Review of day and schedule for remainder of workshop 18:00 <em>(adjourn)</em> <strong>Day 4</strong>: <strong><em>Thursday 17 June</em></strong> 09:00 <strong>Scalasca automated trace analysis</strong> [Brian Wylie, JSC] <strong>Scalasca hands-on exercises</strong> 10:30 <em><em>(break)</em></em> 11:00 <strong>Extra-P automated performance modeling</strong> [Marcus Ritter, TUDarmstadt] <strong>Extra-P hands-on exercises</strong> 12:30 <em>(lunch)</em> 14:00 <strong>Hands-on coaching</strong> to apply Scalasca to analyze participants' own code(s). 15:30 <em><em>(break)</em></em> 16:00 <strong>Hands-on coaching</strong> to apply TAU to analyze participants' own code(s). 17:30 Review of day and schedule for remainder of workshop 18:00 <em>(adjourn)</em> <strong>Day 5</strong>: <strong><em>Friday 18 June</em></strong> 09:00 <strong>mpiP lightweight MPI profiling</strong> [Martin Schulz, TUM/LRZ] <strong>mpiP hands-on exercises</strong> 10:30 <strong>Review of the workshop</strong><em> </em>[Cédric Valensi, UVSQ] 10:45 <em><em>(break)</em></em> 11:00 <strong>Hands-on coaching</strong> to apply tools to analyze participants' own code(s). 12:30 <em>(lunch)</em> 14:00 <strong>Hands-on coaching</strong> to apply tools to analyze participants' own code(s). 16:00 <em>(adjourn)</em> <pre> </pre> Hardware and Software Platforms <strong>IvyMUC</strong> 8-way Ivy Bridge-based Linux Cluster FDR14 Infiniband interconnect 31 nodes, 16 cores per node 64 GB DDR Memory per node Operating System: SUSE Linux Enterprise Server (SLES) 12 SP5 Compilers: Intel icc, icpc, ifort 19.0 Intel MPI The local HPC system <em>IvyMUC</em> is the primary platform for the workshop and will be used for the hands-on exercises. Course accounts will be provided during the workshop to participants without existing accounts. Other systems where up-to-date versions of the tools are installed can also be used when preferred, though support may be limited and participants are expected to already possess user accounts on non-local systems. Regardless of whichever external systems they intend to use, participants should be familiar with the relevant procedures for compiling and running their parallel applications (via batch queues where appropriate).
description: https://doku.lrz.de/display/PUBLIC/VI-HPS+Tuning+Workshop+2021