title: ÐÐ¿Ð¿Ð°ÑÐ°ÑÐ½ÑÐµ Ð°ÑÑ Ð¸ÑÐµÐºÑÑÑÑ Ð°Ð»Ð³ÐµÐ±ÑÐ°Ð¸ÑÐµÑÐºÐ¸Ñ Ð´ÐµÐºÐ¾Ð´ÐµÑÐ¾Ð² Ð´Ð»Ð¸Ð½Ð½ÑÑ ÐÐ§Ð¥-ÐºÐ¾Ð´Ð¾Ð² ÑÑÐ°Ð½Ð´Ð°ÑÑÐ° DVBS2
title: Ð²ÑÐ¿ÑÑÐºÐ½Ð°Ñ ÐºÐ²Ð°Ð»Ð¸ÑÐ¸ÐºÐ°ÑÐ¸Ð¾Ð½Ð½Ð°Ñ ÑÐ°Ð±Ð¾ÑÐ° Ð±Ð°ÐºÐ°Ð»Ð°Ð²ÑÐ°
titleType: Subtitle
title: Hardware architectures of algebraic decoders of long BCH codes for DVB-S2 standard
Creators: name: ÐÐ¸Ð»Ð¾Ð², ÐÐ½Ð´ÑÐµÐ¹
Publisher: name: Ð¡Ð°Ð½ÐºÑ-ÐÐµÑÐµÑÐ±ÑÑÐ³ÑÐºÐ¸Ð¹ Ð¿Ð¾Ð»Ð¸ÑÐµÑÐ½Ð¸ÑÐµÑÐºÐ¸Ð¹ ÑÐ½Ð¸Ð²ÐµÑÑÐ¸ÑÐµÑ ÐÐµÑÑÐ° ÐÐµÐ»Ð¸ÐºÐ¾Ð³Ð¾
Year: 2023
Subjects: ÐÐ§Ð¥ ÐºÐ¾Ð´
DVB-S2
Ð´ÐµÐºÐ¾Ð´Ð¸ÑÐ¾Ð²Ð°Ð½Ð¸Ðµ
Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼ ÐÐµÑÐ»ÐµÐºÐµÐ¼Ð¿Ð°-ÐÐµÑÑÐ¸
Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼ ÐÐ²ÐºÐ»Ð¸Ð´Ð°
Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼ ÐÐ¸ÑÐµÑÑÐ¾Ð½Ð°
Ð¼Ð½Ð¾Ð³Ð¾ÑÐ»ÐµÐ½ Ð»Ð¾ÐºÐ°ÑÐ¾ÑÐ¾Ð² Ð¾ÑÐ¸Ð±Ð¾Ðº
ÐºÐ»ÑÑÐµÐ²Ð¾Ðµ ÑÑÐ°Ð²Ð½ÐµÐ½Ð¸Ðµ
Ð¿Ð¾Ð»Ðµ ÐÐ°Ð»ÑÐ°
FPGA
Matlab
BCH
Berlekamp-Massey algorithm
Euclidean algorithm
Peterson-Gorenstein-Ziepler algorithm
Galois field
key equation solver

description: ÐÐ±ÑÐµÐºÑ Ð¸ÑÑÐ»ÐµÐ´Ð¾Ð²Ð°Ð½Ð¸Ñ â Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼ Ð²ÑÑÐ¸ÑÐ»ÐµÐ½Ð¸Ñ ÐºÐ¾ÑÑÑÐ¸ÑÐ¸ÐµÐ½ÑÐ¾Ð² Ð¼Ð½Ð¾Ð³Ð¾ÑÐ»ÐµÐ½Ð° Ð»Ð¾ÐºÐ°ÑÐ¾ÑÐ¾Ð² Ð¾ÑÐ¸Ð±Ð¾Ðº ÐÐ§Ð¥ ÐºÐ¾Ð´Ð¾Ð² ÑÑÐ°Ð½Ð´Ð°ÑÑÐ° DVB-S2. Ð¦ÐµÐ»Ñ ÑÐ°Ð±Ð¾ÑÑ â ÑÐ½Ð¸Ð¶ÐµÐ½Ð¸Ðµ ÐºÐ¾Ð»Ð¸ÑÐµÑÑÐ²Ð° Ð°Ð¿Ð¿Ð°ÑÐ°ÑÐ½ÑÑ ÑÐµÑÑÑÑÐ¾Ð² Ð¿ÑÐ¸ ÑÐµÐ°Ð»Ð¸Ð·Ð°ÑÐ¸Ð¸ Ð² FPGA Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð° Ð²ÑÑÐ¸ÑÐ»ÐµÐ½Ð¸Ñ ÐºÐ¾ÑÑÑÐ¸ÑÐ¸ÐµÐ½ÑÐ¾Ð² Ð¼Ð½Ð¾Ð³Ð¾ÑÐ»ÐµÐ½Ð° Ð»Ð¾ÐºÐ°ÑÐ¾ÑÐ¾Ð² Ð¾ÑÐ¸Ð±Ð¾Ðº Ð² Ð´ÐµÐºÐ¾Ð´ÐµÑÐµ ÐÐ§Ð¥ ÐºÐ¾Ð´Ð¾Ð². Ð ÑÐµÐ·ÑÐ»ÑÑÐ°ÑÐµ Ð¸ÑÑÐ»ÐµÐ´Ð¾Ð²Ð°Ð½Ð¸Ñ ÑÐµÐ°Ð»Ð¸Ð·Ð¾Ð²Ð°Ð½ Ð¼Ð¾Ð´ÑÐ»Ñ, Ð²ÑÑÐ¸ÑÐ»ÑÑÑÐ¸Ð¹ ÐºÐ¾ÑÑÑÐ¸ÑÐ¸ÐµÐ½ÑÑ Ð¼Ð½Ð¾Ð³Ð¾ÑÐ»ÐµÐ½Ð° Ð»Ð¾ÐºÐ°ÑÐ¾ÑÐ¾Ð² Ð¾ÑÐ¸Ð±Ð¾Ðº Ð¿Ð¾ Ð¿ÑÐ¸Ð½ÑÑÐ¾Ð¼Ñ Ð¼Ð½Ð¾Ð³Ð¾ÑÐ»ÐµÐ½Ñ ÑÐ¸Ð½Ð´ÑÐ¾Ð¼Ð¾Ð². Ð ÑÐ¾Ð´Ðµ ÑÐ°Ð±Ð¾ÑÑ ÑÐ¾Ð·Ð´Ð°Ð½Ð° Ð¼Ð¾Ð´ÐµÐ»Ñ Ð´ÐµÐºÐ¾Ð´ÐµÑÐ° ÐÐ§Ð¥ ÐºÐ¾Ð´Ð¾Ð² Ð² ÑÑÐµÐ´Ðµ Matlab, ÐºÐ¾ÑÐ¾ÑÐ°Ñ Ð¿ÑÐµÐ´ÑÑÐ°Ð²Ð»ÑÐµÑ ÑÐ¾Ð±Ð¾Ð¹ ÑÐµÑÑÐ¾Ð²Ð¾Ðµ Ð¾ÐºÑÑÐ¶ÐµÐ½Ð¸Ðµ ÑÐµÐ°Ð»Ð¸Ð·Ð¾Ð²Ð°Ð½Ð½Ð¾Ð³Ð¾ Ð¼Ð¾Ð´ÑÐ»Ñ. ÐÑÐµÐ´Ð»Ð¾Ð¶ÐµÐ½Ð° ÑÐ²ÑÑÐ½ÑÑÐ°Ñ Ð°ÑÑÐ¸ÑÐµÐºÑÑÑÐ° Ð°Ð»Ð³Ð¾ÑÐ¸ÑÐ¼Ð° Ð²ÑÑÐ¸ÑÐ»ÐµÐ½Ð¸Ñ ÐºÐ¾ÑÑÑÐ¸ÑÐ¸ÐµÐ½ÑÐ¾Ð² Ð¼Ð½Ð¾Ð³Ð¾ÑÐ»ÐµÐ½Ð° Ð»Ð¾ÐºÐ°ÑÐ¾ÑÐ¾Ð² Ð¾ÑÐ¸Ð±Ð¾Ðº. ÐÐ°Ð½Ð½ÑÐ¹ Ð¼Ð¾Ð´ÑÐ»Ñ Ð¼Ð¾Ð¶Ð½Ð¾ Ð¸ÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°ÑÑ Ð² Ð´ÐµÐºÐ¾Ð´ÐµÑÐµ ÐÐ§Ð¥ ÐºÐ¾Ð´Ð¾Ð² ÑÑÐ°Ð½Ð´Ð°ÑÑÐ° DVB-S2. ÐÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°Ð»Ð¸ÑÑ Ð¾ÑÐºÑÑÑÑÐµ Ð¾Ð±ÑÐ°Ð·Ð¾Ð²Ð°ÑÐµÐ»ÑÐ½ÑÐµ ÑÐµÑÑÑÑÑ Ð¸ Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ñ Ð¿Ð¾Ð¸ÑÐºÐ° Ð¸ Ð°Ð½Ð°Ð»Ð¸Ð·Ð° Ð¸Ð½ÑÐ¾ÑÐ¼Ð°ÑÐ¸Ð¸. ÐÑÐ¿Ð¾Ð»ÑÐ·Ð¾Ð²Ð°Ð»Ð¸ÑÑ ÑÑÐµÐ´ÑÑÐ²Ð° Ð°Ð²ÑÐ¾Ð¼Ð°ÑÐ¸Ð·Ð°ÑÐ¸Ð¸ (Ð°Ð²ÑÐ¾Ð¼Ð°ÑÐ¸Ð·Ð¸ÑÐ¾Ð²Ð°Ð½Ð½Ð¾Ð¹) ÑÐ°Ð·ÑÐ°Ð±Ð¾ÑÐºÐ¸ Matlab, Vivado. ÐÑÐ¸Ð¼ÐµÐ½ÐµÐ½Ð¾ (Ð¿ÑÐ¾ÑÐµÑÑÐ¸ÑÐ¾Ð²Ð°Ð½Ð¾) Ð¿ÑÐ¾Ð³ÑÐ°Ð¼Ð¼Ð½Ð¾Ðµ Ð¾Ð±ÐµÑÐ¿ÐµÑÐµÐ½Ð¸Ðµ Matlab.
description: The subject of the graduate qualification work is algorithm for calculating the coefficients of the polynomial of error locators of BCH codes of the DVB-S2 standard. The purpose of the work is to reduce the amount of hardware resources when implementing in the FPGA an algorithm for calculating the error locator polynomial coefficients in a BCH code decoder. As a result of the study, a module was implemented that calculates the error locator polynomial coefficients from the received syndrome polynomial. In the course of the work, a model of a BCH code decoder was created in the Matlab environment, which is a test environment for the implemented module. A collapsed architecture of the algorithm for calculating the coefficients of the error locator polynomial is proposed. This module can be used in a BCH decoder for DVB-S2 codes. Open educational resources and programs for searching and analyzing information were used. We used automation tools for (automated) development of Matlab, Vivado. Applied (tested) Matlab software.