Implementation of CNN and CNN specific learning algorithms on FPGA
Creators: name: Köse, Erdem
Publisher: name: figshare
Year: 2021
Subjects: subject: 170205 Neurocognitive Patterns and Neural Networks
subject: FOS: Psychology
subject: Artificial Intelligence and Image Processing
subject: FOS: Computer and information sciences

description: Humankind has been working for the survival and prosperity since the existence. Almost all of these works are based on engineering and experience. While civilizations are evolving, curiosity is increasing and needs are changing, the calculations and designs was started to become more complex. Humankind's calculation capacity had been very limited until invention of transistor and then computer. When the information age came, the problem complexity has been started to increase even faster. One of these problems is parallel computing which forces current computers seriously. One of the models to solve this problem is artificial neural networks. It's possible that implementing nervous system of living beings on electronic circuits with artificial neural networks. Even nervous systems of living beings are working at low frequencies, they have highly parallel processing capabilities. Nervous systems' the biggest advantage on general purposed processors is processing multiple inputs and giving multiple outputs in a very short time. With artificial neural networks, nervous systems of living being can be used to solve different kind of problems and that expands the range of problems that can be solved. Artificial neural network or connectionist system is a nervous system based computational model used in various research disciplines. Artificial neural networks are based on a large collection of artificial neurons, which behaves like biological brain's axons. A single neural unit is connected to some of others and links can improve or prevent activation state of neighboring neural units. Each individual neural unit computes output using summation of inputs' multiplication with other units' weights. Limiting or thresholding function can be placed on each connection and on the unit itself to prevent datum exceeding the limit before propagating to other neural units. In spite of being manually programmed, these systems can be self-learning and trained. Thus, systems using this model outclasses competitors in areas where the solution or feature detection is difficult. In 1988 Chua and Yang purposed a new and special neural network model called cellular neural networks. Cellular neural networks are based on artificial neural networks and cellular automata. It can be used in image processing, wave generation, cryptology and sound processing. Cellular neural networks' first implementation is Cellular Neural Network Universal Machine is based on analogue and logic hybrid structure; processing is based on analogue, control is based on digital circuitries.Because of analogue implementation's disadvantages like flexibility and prototyping, discrete time cellular neural network model was designed by Harrer and Nossek and this became the start of the digital era for cellular neural networks. Until today many digital implementations of cellular neural network emulation has implemented. These implementations have some disadvantages and advantages to each other, so new solutions are being investigated. Multi core processors or graphics processors are used in doing parallel processes; but their mobility is lacking. Even so; processors like IBM Cell, NVidia Cuda and Intel Xeon can be used in modelling and simulation of cellular neural network applications. More application specific and mobile processors like digital signal processors and microcontrollers have limited capabilities. Because of all of these problems, Field Programmable Gate Arrays have been used in implementation of cellular neural network emulation processors; but there is no such cellular neural network emulation processor has learning capabilities. There are a few learning methods to learn cellular neural network templates. The mostly known examples are genetic algorithm, backpropagation like algorithm and manual template design. Backpropagation like learning method is a runtime learning method which based on error between desired and current value. In this work a cellular neural networks emulation processor which can do template learning with backpropagation was implemented. Processor has built on two units which are control unit and calculation unit. Processor works on 100 MHz frequency with 41.5 cantigrade degree heat and total 1 W power consumption. Processor is designed on Digilent Atlys, which has Spartan 6, development board using VHDL. Control unit includes Microblaze microprocessor which have communication units, pseudo-random number generator and configuration registers unit. Microblaze microprocessor controls random access memory, ethernet, UART, flash memory. Pseudo-random number generator is for using in learning methods. Microblaze microprocessor unit controls cellular neural network emulation processor via configuration registers unit. Calculation unit includes arithtmetic unit, caches and finite state machine. Finite state machine controls arithmetic unit, cache read-write and iteration control to get maximum parallelised and pipelined processing structure to have fast cellular neural network emulation processor. Finite state machine is cellular neural network emulation processor's control unit. Because of calculation unit is designed parametrically, calculation unit can be implemented in different FPGAs with different configuration settings. Configurable properties are; template size, cache size, and bit width. The configuration parameters in our design are; 3$\times$3 templates, 128$\times$128 cache and 16 bit data lane. These settings are the maximum settings for Digilent Atlys development board. Cellular neural network emulation processor can do a 3$\times$3 state pixel process in 5 clock pulse with reading from cache, writing to cache and reading a template. Total calculation time depends on image size, software algorithm, DDR2 RAM, Microblace microprocessor and communication connection. Level 1 cache designed as first in first out memory, by this reading from level 2 block RAM cache becomes faster. The purpose of the level 2 block RAM ise decrease the speed disadvantage of reading from DDR2 RAM. Ethernet connection is for fast image transfer between host and client, the client is our FPGA implementation. UART connection is for error debugging and slow image transfer. Processor successfully runs on Digilent Atlys development board. Xilinx Spartan 6 XC6SLX45-3CSG324C FPGA, 128 MB 600 MHz DDR2 RAM and 1 Mbit UART connection on Digilent Atlys development board are being used and 16 MByte QSPI flash memory, 100 Mbits ethernet connection can be used in further works. With all of these functions, various cellular neural network and template learning algorithms can be implemented on cellular neural network emulation processor. Backpropagation template learning, random initialized template learning and multi template cellular neural network applications are successfully implemented on Microblaze microprocessor with C language. GPIOs are used for communication between Microblaze microprocessor and cellular neural network emulation processor core. The results are competitive with Intel Core i7 4790 MATLAB simulation results, even for 100 MHz frequency restrict. Processors' performance without learning is head to head with Intel Core i7 4790 MATLAB simulation with 84/1 power consumption gain and mobility advantages.