Study of silicon-on-insulator multiple-gate MOS structures including band-gap engineering and self heating effects
Creators: name: Braccioli, Marco <1979>
Publisher: name: Alma Mater Studiorum - Università di Bologna
Year: 2009
Subjects: ING-INF/01 Elettronica

description: The progresses of electron devices integration have proceeded for more than 40 years following the well–known Moore’s law, which states that the transistors density on chip doubles every 24 months. This trend has been possible due to the downsizing of the MOSFET dimensions (scaling); however, new issues and new challenges are arising, and the conventional ”bulk” architecture is becoming inadequate in order to face them.
In order to overcome the limitations related to conventional structures, the researchers
community is preparing different solutions, that need to be assessed.
Possible solutions currently under scrutiny are represented by:
• devices incorporating materials with properties different from those of silicon, for
the channel and the source/drain regions;
• new architectures as Silicon–On–Insulator (SOI) transistors: the body thickness of Ultra-Thin-Body SOI devices is a new design parameter, and it permits
to keep under control Short–Channel–Effects without adopting high
doping level in the channel.
Among the solutions proposed in order to overcome the difficulties related to scaling,
we can highlight heterojunctions at the channel edge, obtained by adopting for the
source/drain regions materials with band–gap different from that of the channel material.
This solution allows to increase the injection velocity of the particles travelling
from the source into the channel, and therefore increase the performance of the transistor
in terms of provided drain current.
The first part of this thesis work addresses the use of heterojunctions in SOI transistors:
chapter 3 outlines the basics of the heterojunctions theory and the adoption of such
approach in older technologies as the heterojunction–bipolar–transistors; moreover the
modifications introduced in the Monte Carlo code in order to simulate conduction band
discontinuities are described, and the simulations performed on unidimensional simplified
structures in order to validate them as well.
Chapter 4 presents the results obtained from the Monte Carlo simulations performed
on double–gate SOI transistors featuring conduction band offsets between the source
and drain regions and the channel. In particular, attention has been focused on the drain
current and to internal quantities as inversion charge, potential energy and carrier velocities.
Both graded and abrupt discontinuities have been considered.
The scaling of devices dimensions and the adoption of innovative architectures have
consequences on the power dissipation as well. In SOI technologies the channel is thermally
insulated from the underlying substrate by a SiO2 buried–oxide layer; this SiO2
layer features a thermal conductivity that is two orders of magnitude lower than the
silicon one, and it impedes the dissipation of the heat generated in the active region.
Moreover, the thermal conductivity of thin semiconductor films is much lower than
that of silicon bulk, due to phonon confinement and boundary scattering. All these aspects
cause severe self–heating effects, that detrimentally impact the carrier mobility
and therefore the saturation drive current for high–performance transistors; as a consequence,
thermal device design is becoming a fundamental part of integrated circuit
engineering.
The second part of this thesis discusses the problem of self–heating in SOI transistors.
Chapter 5 describes the causes of heat generation and dissipation in SOI devices, and
it provides a brief overview on the methods that have been proposed in order to model
these phenomena. In order to understand how this problem impacts the performance of
different SOI architectures, three–dimensional electro–thermal simulations have been
applied to the analysis of SHE in planar single and double–gate SOI transistors as well
as FinFET, featuring the same isothermal electrical characteristics.
In chapter 6 the same simulation approach is extensively employed to study the impact
of SHE on the performance of a FinFET representative of the high–performance
transistor of the 45 nm technology node. Its effects on the ON–current, the maximum
temperatures reached inside the device and the thermal resistance associated to the device
itself, as well as the dependence of SHE on the main geometrical parameters have
been analyzed. Furthermore, the consequences on self–heating of technological solutions
such as raised S/D extensions regions or reduction of fin height are explored as
well.
Finally, conclusions are drawn in chapter 7.