A Test Chip Design for Automatic Insertion of Logic Circuit Demographics
Creators: name: Zeye Liu
Publisher: name: Carnegie Mellon University
Year: 2020
Subjects: subject: 90699 Electrical and Electronic Engineering not elsewhere classified
subject: FOS: Electrical engineering, electronic engineering, information engineering
subject: FOS: Electrical engineering, electronic engineering, information engineering

description: The continued scaling of integrated circuits (ICs) introduces complex interactions between layout features, which can lead to manufacturability issues that reduce yield. In recent years, foundries have increased capital expenditures and time to inspect and review equipment for process control and yield improvement. One strategy is the use of test structures to identify sources of yield loss early in the development of a new manufacturing process. However, the aggressive scaling of feature dimensions, the integration of new materials, and the increase in structural complexity in modern technologies has challenged the capabilities of conventional test structures. To help address these challenges, a new logic test chip, called the Carnegie Mellon Logic Characterization Vehicle (CM-LCV), has been developed. It is based on the insight that the manufacturing process is sensitive only to the physical features of a design (i.e., its physical layout), and not the logic functionality the layout implements. This provides the freedom to select a logical functionality and structure that maximizes testability and diagnosability, and a layout implementation that has physical features that will be manufactured in the actual product designs. To be specific, the CM-LCV utilizes a two-dimensional array of functional unit blocks (FUBs) that each implement an innovative functionality. Composability within this FUB array is demonstrated for fault coverage, logical and physical design features, and fault distinguishability. Particularly, three design methodologies that leverage composability to adapt the FUB array to incorporate three layout demographics automatically are presented. The three layout demographics represent the physical features of the actual production design, including 1) layout geometries within the each individual standard cell, 2) the layout geometries of the standard-cell neighborhoods, and 3) layout geometries that connect the standard cells. Experiments demonstrate that these design methodologies are capable of incorporating the physical features, while achieving the enhanced testability and diagnosability. In conjunction with the design methodology of inserting logic circuit demographics into the CM-LCV, methods for improving the design efficiency are also presented. Particularly, two random forest classifiers are deployed to predict 1) whether a synthesis configuration will result in a unique FUB implementation, and 2) whether a unique FUB implementation has an acceptable level of testability, so that unnecessary synthesis and testability analysis can be avoided. In addition, an on-line learning strategy is developed to mitigate the cost of obtaining training data. Various design experiments demonstrate that the ML-aided flow speeds up design by 11x with negligible performance degradation. A new FUB array architecture is also presented for the CM-LCV. The new FUB array architecture extends the two-dimensional FUB array to three dimension for enhancing the diagnosability for multiple defects. Techniques to create minimal sets of test patterns that exhaustively exercise each FUB within the three-dimensional FUB array are developed. Meanwhile, A hierarchical FUB array diagnosis methodology is described for the CM-LCV that leverages the properties of the three dimensional FUB array to improve performance for multiple defects. Experiments demonstrate that this new FUB array architecture and corresponding diagnosis methodology is capable of perfect accuracy in 100% of simulations with single and double injected faults, and up to 92% perfect accuracy when three faulty FUBs within the array, an improvement on the state-of-the-art commercial diagnosis. The contributions of this dissertation can thus be summarized as the description of the design, test, and diagnosis of a new logic test chip for use in yield learning. This CM-LCV can be adapted to meet a wide range of test chip requirements, can be efficiently and rigorously tested, and exhibits properties that can be used to improve diagnosis outcomes.