Register Organization in RISC CPU

21 Jun, 2021
RISC processors :They are processors that use a small instruction set and simple addressing mode so that their instructions can be executed much faster within the CPU with less referring to the memory. This type of processor is classified as a reduced instruction set computer( RISC).
For detailed understanding of the RISC processor and its characteristics, please refer thisSome other characteristics of the RISC processor are –
They contain a large number of registers.
They use overlapped register windows to speed up procedure call and return.
They have an efficient instruction pipeline.
They have compiler support for efficient translation of high level language programs into machine language programs.
RISC instructions :
A typical RISC processor instruction set mainly includes the LOAD and STORE instructions that are used for communicating between memory and CPU.
All other instructions are executed within the registers of the CPU without referring to the memory.
A program of a RISC CPU contains LOAD and STORE instructions that have one memory and one CPU register address and computational instructions(ADD, SUB MUL  etc.) have three addresses and all three are referring to processor registers.
For example :A program that evaluates X = (A*B) + (C*D), here A,B,C,D are memory locations that contain four numbers and X is a memory location that contains the result of that expression.
Instruction 
comment 
LOAD R1, A
LOAD R2, B
LOAD R3, C
LOAD R4, D
MUL R1, R1, R2
MUL R3, R3 , R4
ADD R1, R1, R3 
STORE X, R1 
; Processor register R1 is loaded with content of the memory location A.
; Processor register R2 is loaded with content of the memory location B.
; Processor register R3 is loaded with content of the memory location C.
; Processor register R4 is loaded with content of the memory location D.
; Multiplication of the contents of the R1 and R2 register and the result is stored in the R1 register (i.e. A*B is performed).
; Multiplication of the contents of the R3 and R4 register and the result is stored in the R1 register (i.e. C*D is performed).
; Addition of contents of register R1 and R3 and the result is stored in the R1 register(i.e. (A*B) + (C*D)).
; Content of R1 register is stored in memory location X. 
Register organization in RISC CPU :
The characteristics of some RISC CPUs is to use an overlapped register window that provides passing of parameters to called procedure and stores the result to the calling procedure.
For each procedure call, the new register window is assigned from register file used by the new procedure.
Each procedure call activates the new register window by increment a pointer and the return statement decrements the pointer which causes the activation of the previous window.
Windows of adjacent procedures have overlapping registers that are shared to provide passing of parameters and storage of results.
Overlapped register window of RISC CPU
In this organization, the RISC CPU contains 74 registers. Registers R0 to R9 are global registers that contain parameters which are common to all procedures.
The remaining registers(R10 to R73) are divided into four windows to contain procedures A, B, C and D.
Each window contains 10 local registers and two sets of 6 registers common to consecutive windows. Local registers contain local variables and common overlapped registers help to pass parameters between adjacent procedures without actual movement of data.
One of the register window is activated at a time. The high registers of the calling procedure overlap the low registers of the called procedures, therefore parameters are passed from calling to called procedure easily.
For example: 
Procedure C  called procedure D. Therefore, registers R58 to R63 are common to both procedures C and D. Therefore, procedure C stores parameters for procedure D in these registers. Procedure D uses registers R64 to R73 to store the local variables.
When procedure B returns after performing its computation, then the result from registers(R26 to R31) is transferred back to window A.
Registers R10 to R15 are common to procedures A and D also the four windows have a circular organization.
As R0 to R9(i.e. 10 registers) is available all procedures. Therefore, a procedure contains 32 registers while procedure it is active(which includes 10 global ,10 local, 6 low overlapping registers and 6 high overlapping registers) .
The organization of register windows has the relationship as
Number of global registers = g
Number of local registers present in each window = l
Number of registers common to two adjacent windows = c
Number of windows  = w
Then the number of registers available for each window is calculated by 
Window size = l+2c+g
The total number of registers required in the processor is
Register file = (l + c)w+ g
For example :
In the above figure we have g= 10, l= 10, c= 6, w= 4, then
the window size = 10+2×6+4 = 36 and register file size = (10+6)×4 + 10 = 74
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