Introduction of General Register based CPU Organization - GeeksforGeeks

24 Feb, 2022
When we are using multiple general-purpose registers, instead of a single accumulator register, in the CPU Organization then this type of organization is known as General register-based CPU Organization. In this type of organization, the computer uses two or three address fields in their instruction format. Each address field may specify a general register or a memory word. If many CPU registers are available for heavily used variables and intermediate results, we can avoid memory references much of the time, thus vastly increasing program execution speed, and reducing program size. 
For example: 
MULT R1, R2, R3 
This is an instruction of an arithmetic multiplication written in assembly language. It uses three address fields R1, R2, and R3. The meaning of this instruction is:
R1 <-- R2 * R3 
This instruction also can be written using only two address fields as: 
MULT R1, R2 
In this instruction, the destination register is the same as one of the source registers. This means the operation 
R1 <-- R1 * R2 
The use of a large number of registers results in a short program with limited instructions. 
Some examples of General register-based CPU Organizations are IBM 360 and PDP- 11. 
The advantages of General register-based CPU organization – 
The efficiency of the CPU increases as large number of registers are used in this organization.
Less memory space is used to store the program since the instructions are written in a compact way.
The disadvantages of General register based CPU organization – 
Care should be taken to avoid unnecessary usage of registers. Thus, compilers need to be more intelligent in this aspect.
Since a large number of registers are used, thus extra cost is required in this organization.
General register CPU organization of two types:
Register-memory reference architecture (CPU with less register) – In this organization Source 1 is always required in the register, source 2 can be present either in the register or in memory. Here two address instruction formats are compatible instruction formats.Register-register reference architecture (CPU with more register) – In this organization, ALU operations are performed only on registered data. So operands are required in the register. After manipulation, the result is also placed in a register. Here three address instruction formats are the compatible instruction format.
Register-memory reference architecture (CPU with less register) – In this organization Source 1 is always required in the register, source 2 can be present either in the register or in memory. Here two address instruction formats are compatible instruction formats.
Register-register reference architecture (CPU with more register) – In this organization, ALU operations are performed only on registered data. So operands are required in the register. After manipulation, the result is also placed in a register. Here three address instruction formats are the compatible instruction format.
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