GATE | GATE-CS-2015 (Set 1) | Question 47 - GeeksforGeeks

29 Sep, 2021
A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flipflop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.(A) 0110110...(B) 0100100...(C) 011101110...(D) 011001100...Answer: (A)Explanation: 
Initially Q output of D – FF  = 1
Initially Q output of JK – FF  = 0
Now with the help of present state and next state table we can see what is happening in circuit.
Toggle: J = K = 1
Hold : J = K = 0
We see from table Q output of D-FF is going to next state input of JK-FF and the bits sequence produced is like 110110.....
Including initial condition (0) we get output as 0110110110....
Hence answer is (A) part.
Another Explanation:
Here, it is given that JK flip flop will toggle when J = K = 1 and it will retain the output if J = K = 0.Also, the output of the D flip flop would remain the same as the input.
So, we have
Initial output : D = 1
JK = 0
After clock 1 : D = 0 (D gets 0 as input 
from initial output of JK, so output = 0)
JK = 1 (J = K = 1 from initial output of D, so output would be toggled from 0 to 1)
After clock 2 : D = 1 (D gets 1 as input 
from previous output of JK, so output = 1)
JK = 1 (J = K = 0 from previous output of D, so output would be retained to 1)
After clock 3 : D = 1 (D gets 1 as input
from previous output of JK, so output = 1)
JK = 0 (J = K = 1 from previous output of D, so output would be toggled from 1 to 0)
After clock 4 : D = 0 (D gets 0 as input
from previous output of JK, so output = 0)
JK = 1 (J = K = 1 from previous output of D, so output would be toggled from 0 to 1)
After clock 5 : D = 1 (D gets 1 as input
from previous output of JK, so output = 1)
JK = 1 (J = K = 0 from previous output of D, so output would be retained to 1)
Thus, the bit sequence generated at the Q output of the JK flip flop will be 0110110...
 YouTubeGeeksforGeeks GATE Computer Science16.4K subscribersSequential Circuits : Latches and Flip Flops : GATE PYQs with Rishabh SetiyaWatch laterShareCopy linkInfoShoppingTap to unmuteIf playback doesn't begin shortly, try restarting your device.You're signed outVideos you watch may be added to the TV's watch history and influence TV recommendations. To avoid this, cancel and sign in to YouTube on your computer.CancelConfirmMore videosMore videosSwitch cameraShareInclude playlistAn error occurred while retrieving sharing information. Please try again later.Watch on0:000:008:00 / 30:16•Live•<div class="player-unavailable"><h1 class="message">An error occurred.</h1><div class="submessage"><a href="https://www.youtube.com/watch?v=ngYeqE_gFV0" target="_blank">Try watching this video on www.youtube.com</a>, or enable JavaScript if it is disabled in your browser.</div></div>Quiz of this Question
GATE-CS-2015 (Set 1)
GATE-GATE-CS-2015 (Set 1)
GATE
Writing code in comment?
Please use ide.geeksforgeeks.org,
generate link and share the link here.
GATE | Gate IT 2007 | Question 25
GATE | GATE-CS-2001 | Question 39
GATE | GATE-CS-2000 | Question 41
GATE | GATE-CS-2005 | Question 6
GATE | GATE MOCK 2017 | Question 21
GATE | GATE MOCK 2017 | Question 24
GATE | GATE-CS-2006 | Question 47
GATE | Gate IT 2008 | Question 43
GATE | GATE-CS-2009 | Question 38
GATE | GATE-CS-2003 | Question 90