Architecture of 8086 - GeeksforGeeks

16 Jul, 2021
A Microprocessor is an Integrated Circuit with all the functions of a CPU however, it cannot be used stand alone since unlike a microcontroller it has no memory or peripherals. 
8086 does not have a RAM or ROM inside it. However, it has internal registers for storing intermediate and final results and interfaces with memory located outside it through the System Bus. 
In case of 8086, it is a 16-bit Integer processor in a 40 pin, Dual Inline Packaged IC. 
The size of the internal registers(present within the chip) indicate how much information the processor can operate on at a time (in this case 16-bit registers) and how it moves data around internally within the chip, sometimes also referred to as the internal data bus. 
8086 provides the programmer with 14 internal registers, each 16 bits or 2 Bytes wide. 
Memory segmentation: 
To increase execution speed and fetching speed, 8086 segments the memory. 
It’s 20 bit address bus can address 1MB of memory, it segments it into 16 64kB segments. 
8086 works only with four 64KB segments within the whole 1MB memory.
The internal architecture of Intel 8086 is divided into 2 units: The Bus Interface Unit (BIU), and The Execution Unit (EU). These are explained as following below.  
It provides the interface of 8086 to external memory and I/O devices via the System Bus. It performs various machine cycles such as memory read, I/O read etc. to transfer data between memory and I/O devices. 
BIU performs the following functions- 
It generates the 20 bit physical address for memory access.
It fetches instructions from the memory.
It transfers data to and from the memory and I/O.
Maintains the 6 byte prefetch instruction queue(supports pipelining).
BIU mainly contains the 4 Segment registers, the Instruction Pointer, a prefetch queue and an Address Generation Circuit. 
Instruction Pointer (IP): 
It is a 16 bit register. It holds offset of the next instructions in the Code Segment.
IP is incremented after every instruction byte is fetched.
IP gets a new value whenever a branch instruction occurs.
CS is multiplied by 10H to give the 20 bit physical address of the Code Segment.
Address of the next instruction is calculated as CS x 10H + IP.
Example: 
CS = 4321H IP = 1000H 
then CS x 10H = 43210H + offset =  44210H  
This is the address of the instruction. 
Code Segment register: CS holds the base address for the Code Segment. All programs are stored in the Code Segment and accessed via the IP. 
Data Segment register: DS holds the base address for the Data Segment. 
Stack Segment register: SS holds the base address for the Stack Segment. 
Extra Segment register: ES holds the base address for the Extra Segment. 
Address Generation Circuit: 
The BIU has a Physical Address Generation Circuit.
It generates the 20 bit physical address using Segment and Offset addresses using the formula:  
Physical Address 
= Segment Address x 10H + Offset Address
6 Byte Pre-fetch Queue: 
It is a 6 byte queue (FIFO).
Fetching the next instruction (by BIU from CS) while executing the current instruction is called pipelining.
Gets flushed whenever a branch instruction occurs. 
The main components of the EU are General purpose registers, the ALU, Special purpose registers, Instruction Register and Instruction Decoder and the Flag/Status Register. 
Fetches instructions from the Queue in BIU, decodes and executes arithmetic and logic operations using the ALU.Sends control signals for internal data transfer operations within the microprocessor.Sends request signals to the BIU to access the external module.It operates with respect to T-states (clock cycles) and not machine cycles.
Fetches instructions from the Queue in BIU, decodes and executes arithmetic and logic operations using the ALU.
Sends control signals for internal data transfer operations within the microprocessor.
Sends request signals to the BIU to access the external module.
It operates with respect to T-states (clock cycles) and not machine cycles.
8086 has four 16 bit general purpose registers AX, BX, CX and DX. Store intermediate values during execution. Each of these have two 8 bit parts (higher and lower). 
AX register: It holds operands and results during multiplication and division operations. Also an accumulator during String operations.  
BX register: It holds the memory address (offset address) in indirect addressing modes.  
CX register: It holds count for instructions like loop, rotate, shift and string operations.  
DX register: It is used with AX to hold 32 bit values during multiplication and division.  
Arithmetic Logic Unit (16 bit): Performs 8 and 16 bit arithmetic and logic operations. 
Special purpose registers (16-bit): 
Stack Pointer: Points to Stack top. Stack is in Stack Segment, used during instructions like PUSH, POP, CALL, RET etc.
Base Pointer: BP can hold offset address of any location in the stack segment. It is used to access random locations of the stack.
Source Index: It holds offset address in Data Segment during string operations.
Destination Index: It holds offset address in Extra Segment during string operations.
Instruction Register and Instruction Decoder: The EU fetches an opcode from the queue into the instruction register. The instruction decoder decodes it and sends the information to the control circuit for execution. 
Flag/Status register (16 bits): It has 9 flags that help change or recognize the state of the microprocessor. 
6 Status flags:  
carry flag(CF)parity flag(PF)auxiliary carry flag(AF)zero flag(Z)sign flag(S)overflow flag (O)
carry flag(CF)
parity flag(PF)
auxiliary carry flag(AF)
zero flag(Z)
sign flag(S)
overflow flag (O)
Status flags are updated after every arithmetic and logic operation. 
3 Control flags: 
trap flag(TF)interrupt flag(IF)direction flag(DF)
trap flag(TF)
interrupt flag(IF)
direction flag(DF)
These flags can be set or reset using control instructions like CLC, STC, CLD, STD, CLI, STI, etc. 
The Control flags are used to control certain operations. 
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