Repository: llvm/llvm-project
Pull request #135248: [RISCV] Fix assertion failure when using -fstack-clash-protection
Author: login: ilovepi
Labels: name: backend:RISC-V
Created: 2025-04-10T20:12:42Z | Merged: 2025-04-18T16:12:52Z

We can't assume MBBI is still pointing at MBB if we've already expanded
a probe. We need to re-query the MBB from MBBI. Fixes #135206

Co-authored-by: Craig Topper <craig.topper@sifive.com>

Linked issue #135206: [RISC-V] Infinite loop when compiling w/ -fstack-clash-protection on RISC-V
When compiling some Fuchsia code for RISC-V, we found that enabling -fstack-clash-protection started causing our builders to time out. When investigating locally, I found that the build would not complete, even after more than a full day. Typically these files compile on the order of seconds, so there seems to be something wrong in the RISC-V implementation of stack clash protection. Note: we don't see these issues on x86_64 or Aarch64.

I'm uploading a reproducer, but I haven't had a chance to reduce it yet.

[clang-crashreports.zip](https://github.com/user-attachments/files/19688491/clang-crashreports.zip)
Linked issue comments: user: login: llvmbot
created_at: 2025-04-10T16:36:10Z
body: 
@llvm/issue-subscribers-backend-risc-v

Author: Paul Kirth (ilovepi)

<details>
When compiling some Fuchsia code for RISC-V, we found that enabling -fstack-clash-protection started causing our builders to time out. When investigating locally, I found that the build would not complete, even after more than a full day. Typically these files compile on the order of seconds, so there seems to be something wrong in the RISC-V implementation of stack clash protection. Note: we don't see these issues on x86_64 or Aarch64.

I'm uploading a reproducer, but this I haven't had a chance to reduce it yet.

[clang-crashreports.zip](https://github.com/user-attachments/files/19688491/clang-crashreports.zip)
</details>

author_association: MEMBER
user: login: llvmbot
created_at: 2025-04-10T16:36:12Z
body: 
@llvm/issue-subscribers-bug

Author: Paul Kirth (ilovepi)

<details>
When compiling some Fuchsia code for RISC-V, we found that enabling -fstack-clash-protection started causing our builders to time out. When investigating locally, I found that the build would not complete, even after more than a full day. Typically these files compile on the order of seconds, so there seems to be something wrong in the RISC-V implementation of stack clash protection. Note: we don't see these issues on x86_64 or Aarch64.

I'm uploading a reproducer, but this I haven't had a chance to reduce it yet.

[clang-crashreports.zip](https://github.com/user-attachments/files/19688491/clang-crashreports.zip)
</details>

author_association: MEMBER
user: login: topperc
created_at: 2025-04-10T16:41:33Z
body: cc: @rzinsly 
author_association: COLLABORATOR
user: login: topperc
created_at: 2025-04-10T17:11:48Z
body: Assertions build gives this error

```
clang++: llvm/include/llvm/CodeGen/MachineBasicBlock.h:1045: iterator llvm::MachineBasicBlock::insert(iterator, MachineInstr *): Assertion `(I == end() || I->getParent() == this) && "iterator points outside of basic block"' failed.
```

with this stack trace

```
-lto-objects -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -x c++ sysmem_tests-1a6d89.cpp -mllvm -opt-bisect-limit=-1
1.      <eof> parser at end of file
2.      Code generation
3.      Running pass 'Function Pass Manager' on module 'sysmem_tests-1a6d89.cpp'.
4.      Running pass 'Prologue/Epilogue Insertion & Frame Finalization' on function '@_ZN12_GLOBAL__N_121AttachTokenSucceedsV1EbbN3fit13function_implILm16ELb0EFvRN14fuchsia_sysmem4wire27BufferCollectionConstraintsEENSt3__29allocatorISt4byteEEEESB_SB_NS1_ILm16ELb0EFvRNS3_21BufferCollectionInfo2EESA_EEj'
 #0 0x000055c5984332f8 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (./bin/clang+++0x3c842f8)
 #1 0x000055c598430e4e llvm::sys::RunSignalHandlers() (./bin/clang+++0x3c81e4e)
 #2 0x000055c5984339a6 SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
 #3 0x00007f83913e6cf0 __restore_rt (/lib64/libpthread.so.0+0x12cf0)
 #4 0x00007f838fe66acf raise (/lib64/libc.so.6+0x4eacf)
 #5 0x00007f838fe39ea5 abort (/lib64/libc.so.6+0x21ea5)
 #6 0x00007f838fe39d79 _nl_load_domain.cold.0 (/lib64/libc.so.6+0x21d79)
 #7 0x00007f838fe5f426 (/lib64/libc.so.6+0x47426)
 #8 0x000055c595ab8e62 (./bin/clang+++0x1309e62)
 #9 0x000055c596be5c4b llvm::RISCVInstrInfo::movImm(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::DebugLoc const&, llvm::Register, unsigned long, llvm::MachineInstr::MIFlag, bool, bool) const (./bin/clang+++0x2436c4b)
#10 0x000055c596ca3f5d llvm::RISCVFrameLowering::inlineStackProbe(llvm::MachineFunction&, llvm::MachineBasicBlock&) const (./bin/clang+++0x24f4f5d)
#11 0x000055c597a38b84 (anonymous namespace)::PEI::runOnMachineFunction(llvm::MachineFunction&) PrologEpilogInserter.cpp:0:0
#12 0x000055c5978dc88b llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (./bin/clang+++0x312d88b)
#13 0x000055c597e31e15 llvm::FPPassManager::runOnFunction(llvm::Function&) (./bin/clang+++0x3682e15)
#14 0x000055c597e39b52 llvm::FPPassManager::runOnModule(llvm::Module&) (./bin/clang+++0x368ab52)
#15 0x000055c597e32661 llvm::legacy::PassManagerImpl::run(llvm::Module&) (./bin/clang+++0x3683661)
#16 0x000055c59865b7c0 clang::emitBackendOutput(clang::CompilerInstance&, clang::CodeGenOptions&, llvm::StringRef, llvm::Module*, clang::BackendAction, llvm::IntrusiveRefCntPtr<llvm::vfs::FileSystem>, std::unique_ptr<llvm::raw_pwrite_stream, std::default_delete<llvm::raw_pwrite_stream>>, clang::BackendConsumer*) (./bin/clang+++0x3eac7c0)
#17 0x000055c598c61160 clang::BackendConsumer::HandleTranslationUnit(clang::ASTContext&) (./bin/clang+++0x44b2160)
#18 0x000055c59a314b79 clang::ParseAST(clang::Sema&, bool, bool) (./bin/clang+++0x5b65b79)
#19 0x000055c598f0a126 clang::FrontendAction::Execute() (./bin/clang+++0x475b126)
#20 0x000055c598e7e39d clang::CompilerInstance::ExecuteAction(clang::FrontendAction&) (./bin/clang+++0x46cf39d)
#21 0x000055c598ff1d0f clang::ExecuteCompilerInvocation(clang::CompilerInstance*) (./bin/clang+++0x4842d0f)
#22 0x000055c595a78a74 cc1_main(llvm::ArrayRef<char const*>, char const*, void*) (./bin/clang+++0x12c9a74)
#23 0x000055c595a752f5 ExecuteCC1Tool(llvm::SmallVectorImpl<char const*>&, llvm::ToolContext const&) driver.cpp:0:0
#24 0x000055c595a73f65 clang_main(int, char**, llvm::ToolContext const&) (./bin/clang+++0x12c4f65)
#25 0x000055c595a84197 main (./bin/clang+++0x12d5197)
#26 0x00007f838fe52d85 __libc_start_main (/lib64/libc.so.6+0x3ad85)
#27 0x000055c595a72a8e _start (./bin/clang+++0x12c3a8e)
```

author_association: COLLABORATOR
user: login: topperc
created_at: 2025-04-10T17:33:46Z
body: Proposed fix. We can't assume MBBI is still pointing at MBB if we've already expanded a probe. We need to re-query the MBB from MBBI.

```
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index c7b2b781422d..a83119957d95 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -2270,11 +2270,13 @@ TargetStackID::Value RISCVFrameLowering::getStackIDForScalableVectors() const {
 }
 
 // Synthesize the probe loop.
-static void emitStackProbeInline(MachineFunction &MF, MachineBasicBlock &MBB,
-                                 MachineBasicBlock::iterator MBBI, DebugLoc DL,
+static void emitStackProbeInline(MachineBasicBlock::iterator MBBI, DebugLoc DL,
                                  Register TargetReg, bool IsRVV) {
   assert(TargetReg != RISCV::X2 && "New top of stack cannot already be in SP");
 
+  MachineBasicBlock &MBB = *MBBI->getParent();
+  MachineFunction &MF = *MBB.getParent();
+
   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
   const RISCVInstrInfo *TII = Subtarget.getInstrInfo();
   bool IsRV64 = Subtarget.is64Bit();
@@ -2363,7 +2365,7 @@ void RISCVFrameLowering::inlineStackProbe(MachineFunction &MF,
       MachineBasicBlock::iterator MBBI = MI->getIterator();
       DebugLoc DL = MBB.findDebugLoc(MBBI);
       Register TargetReg = MI->getOperand(1).getReg();
-      emitStackProbeInline(MF, MBB, MBBI, DL, TargetReg,
+      emitStackProbeInline(MBBI, DL, TargetReg,
                            (MI->getOpcode() == RISCV::PROBED_STACKALLOC_RVV));
       MBBI->eraseFromParent();
     }
```
author_association: COLLABORATOR
user: login: ilovepi
created_at: 2025-04-10T18:19:36Z
body: @topperc That does fix the assertion, and I'm not seeing an infinite loop when compiling some other files too. Thanks.
author_association: CONTRIBUTOR
user: login: topperc
created_at: 2025-05-02T20:15:49Z
body: Looks like this needs to be backported to llvm-20.
author_association: COLLABORATOR
user: login: topperc
created_at: 2025-05-02T20:23:05Z
body: /cherry-pick b3d2dc321c5c78b7204696afe07fe6ef3375acfd
author_association: COLLABORATOR
user: login: topperc
created_at: 2025-05-05T17:10:00Z
body: /cherry-pick https://github.com/llvm/llvm-project/commit/b3d2dc321c5c78b7204696afe07fe6ef3375acfd
author_association: COLLABORATOR
user: login: tstellar
created_at: 2025-05-10T15:34:43Z
body: /cherry-pick b3d2dc321c5c78b7204696afe07fe6ef3375acfd
author_association: COLLABORATOR
user: login: llvmbot
created_at: 2025-05-10T15:40:45Z
body: /pull-request llvm/llvm-project#139388
author_association: MEMBER

Diff:
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index c7b2b781422d1..a83119957d95e 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -2270,11 +2270,13 @@ TargetStackID::Value RISCVFrameLowering::getStackIDForScalableVectors() const {
 }
 
 // Synthesize the probe loop.
-static void emitStackProbeInline(MachineFunction &MF, MachineBasicBlock &MBB,
-                                 MachineBasicBlock::iterator MBBI, DebugLoc DL,
+static void emitStackProbeInline(MachineBasicBlock::iterator MBBI, DebugLoc DL,
                                  Register TargetReg, bool IsRVV) {
   assert(TargetReg != RISCV::X2 && "New top of stack cannot already be in SP");
 
+  MachineBasicBlock &MBB = *MBBI->getParent();
+  MachineFunction &MF = *MBB.getParent();
+
   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
   const RISCVInstrInfo *TII = Subtarget.getInstrInfo();
   bool IsRV64 = Subtarget.is64Bit();
@@ -2363,7 +2365,7 @@ void RISCVFrameLowering::inlineStackProbe(MachineFunction &MF,
       MachineBasicBlock::iterator MBBI = MI->getIterator();
       DebugLoc DL = MBB.findDebugLoc(MBBI);
       Register TargetReg = MI->getOperand(1).getReg();
-      emitStackProbeInline(MF, MBB, MBBI, DL, TargetReg,
+      emitStackProbeInline(MBBI, DL, TargetReg,
                            (MI->getOpcode() == RISCV::PROBED_STACKALLOC_RVV));
       MBBI->eraseFromParent();
     }
diff --git a/llvm/test/CodeGen/RISCV/pr135206.ll b/llvm/test/CodeGen/RISCV/pr135206.ll
new file mode 100644
index 0000000000000..196e78d8ed8b9
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr135206.ll
@@ -0,0 +1,84 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple riscv64 < %s -o - | FileCheck %s
+
+%"buff" = type { [4096 x i64] }
+
+declare void @llvm.memset.p0.i64(ptr, i8, i64, i1)
+declare void @bar()
+
+define i1 @foo() nounwind "probe-stack"="inline-asm" "target-features"="+v" {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -2032
+; CHECK-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s1, 2008(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s2, 2000(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s3, 1992(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    lui a0, 7
+; CHECK-NEXT:    sub t1, sp, a0
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    bne sp, t1, .LBB0_1
+; CHECK-NEXT:  # %bb.2:
+; CHECK-NEXT:    addi sp, sp, -2048
+; CHECK-NEXT:    addi sp, sp, -96
+; CHECK-NEXT:    csrr t1, vlenb
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_3: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    sub t1, t1, t2
+; CHECK-NEXT:    bge t1, t2, .LBB0_3
+; CHECK-NEXT:  # %bb.4:
+; CHECK-NEXT:    sub sp, sp, t1
+; CHECK-NEXT:    li a0, 86
+; CHECK-NEXT:    addi s0, sp, 48
+; CHECK-NEXT:    addi s1, sp, 32
+; CHECK-NEXT:    addi s2, sp, 16
+; CHECK-NEXT:    lui a1, 353637
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    lui a0, 8
+; CHECK-NEXT:    addiw a0, a0, 32
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT:    addiw a0, a1, 1622
+; CHECK-NEXT:    vse8.v v8, (s0)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    vse8.v v8, (s2)
+; CHECK-NEXT:    slli a1, a0, 32
+; CHECK-NEXT:    add s3, a0, a1
+; CHECK-NEXT:    sd s3, 64(sp)
+; CHECK-NEXT:    call bar
+; CHECK-NEXT:    lui a0, 8
+; CHECK-NEXT:    addiw a0, a0, 32
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vse8.v v8, (s0)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    vse8.v v8, (s2)
+; CHECK-NEXT:    sd s3, 64(sp)
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    lui a1, 8
+; CHECK-NEXT:    addiw a1, a1, -1952
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s1, 2008(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s2, 2000(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s3, 1992(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 2032
+; CHECK-NEXT:    ret
+  %1 = alloca %"buff", align 8
+  call void @llvm.memset.p0.i64(ptr %1, i8 86, i64 56, i1 false)
+  call void @bar()
+  call void @llvm.memset.p0.i64(ptr %1, i8 86, i64 56, i1 false)
+  ret i1 false
+}
+


Reviews:
user: login: topperc
body: LGTM
state: APPROVED
author_association: COLLABORATOR
submitted_at: 2025-04-10T20:24:02Z
user: login: jrtc27
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-04-10T20:25:27Z
user: login: ilovepi
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-04-10T20:56:50Z
user: login: ilovepi
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-04-10T20:57:15Z
user: login: ilovepi
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-04-10T21:23:34Z
user: login: ilovepi
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-04-10T21:24:01Z
user: login: ilovepi
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-04-10T21:26:53Z
user: login: jrtc27
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-04-10T21:29:39Z
user: login: jrtc27
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-04-10T21:29:58Z
user: login: jrtc27
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-04-10T21:30:15Z
user: login: ilovepi
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-04-10T21:36:08Z
user: login: ilovepi
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-04-10T21:43:52Z
user: login: ilovepi
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-04-10T21:49:45Z
user: login: wangpc-pp
state: APPROVED
author_association: CONTRIBUTOR
submitted_at: 2025-04-11T03:12:26Z
user: login: ilovepi
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-04-11T19:28:29Z
user: login: preames
body: LGTM
state: APPROVED
author_association: COLLABORATOR
submitted_at: 2025-04-17T13:43:26Z

Review comments:
diff_hunk: @@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+
+; RUN: llc < %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-fuchsia"
path: llvm/test/CodeGen/RISCV/pr135206.ll
user: login: jrtc27
body: ```suggestion
; RUN: llc -mtriple=riscv64-unknown-fuchsia < %s | FileCheck %s
```
created_at: 2025-04-10T20:22:35Z
author_association: COLLABORATOR
diff_hunk: @@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+
+; RUN: llc < %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-fuchsia"
+
+%"struct.fuchsia_sysmem::wire::BufferCollectionConstraints" = type { %"struct.fuchsia_sysmem::wire::BufferUsage", i32, i32, i32, i32, i32, i8, %"struct.fuchsia_sysmem::wire::BufferMemoryConstraints", i32, [4 x i8], %"struct.fidl::Array.94" }
+%"struct.fuchsia_sysmem::wire::BufferUsage" = type { i32, i32, i32, i32, i32 }
+%"struct.fuchsia_sysmem::wire::BufferMemoryConstraints" = type { i32, i32, i8, i8, i8, i8, i8, i32, %"struct.fidl::Array" }
+%"struct.fidl::Array" = type { [32 x i64] }
+%"struct.fidl::Array.94" = type { [32 x %"struct.fuchsia_sysmem::wire::ImageFormatConstraints"] }
+%"struct.fuchsia_sysmem::wire::ImageFormatConstraints" = type <{ %"struct.fuchsia_sysmem::wire::PixelFormat", i32, %"struct.fidl::Array.95", i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i8] }>
+%"struct.fuchsia_sysmem::wire::PixelFormat" = type { i32, i8, %"struct.fuchsia_sysmem::wire::FormatModifier" }
+%"struct.fuchsia_sysmem::wire::FormatModifier" = type { i64 }
+%"struct.fidl::Array.95" = type { [32 x %"struct.fuchsia_sysmem::wire::ColorSpace"] }
+%"struct.fuchsia_sysmem::wire::ColorSpace" = type { i32 }
+
+; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
path: llvm/test/CodeGen/RISCV/pr135206.ll
user: login: jrtc27
body: ```suggestion
```
created_at: 2025-04-10T20:23:03Z
author_association: COLLABORATOR
diff_hunk: @@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+
+; RUN: llc < %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-fuchsia"
+
+%"struct.fuchsia_sysmem::wire::BufferCollectionConstraints" = type { %"struct.fuchsia_sysmem::wire::BufferUsage", i32, i32, i32, i32, i32, i8, %"struct.fuchsia_sysmem::wire::BufferMemoryConstraints", i32, [4 x i8], %"struct.fidl::Array.94" }
+%"struct.fuchsia_sysmem::wire::BufferUsage" = type { i32, i32, i32, i32, i32 }
+%"struct.fuchsia_sysmem::wire::BufferMemoryConstraints" = type { i32, i32, i8, i8, i8, i8, i8, i32, %"struct.fidl::Array" }
+%"struct.fidl::Array" = type { [32 x i64] }
+%"struct.fidl::Array.94" = type { [32 x %"struct.fuchsia_sysmem::wire::ImageFormatConstraints"] }
+%"struct.fuchsia_sysmem::wire::ImageFormatConstraints" = type <{ %"struct.fuchsia_sysmem::wire::PixelFormat", i32, %"struct.fidl::Array.95", i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i8] }>
+%"struct.fuchsia_sysmem::wire::PixelFormat" = type { i32, i8, %"struct.fuchsia_sysmem::wire::FormatModifier" }
+%"struct.fuchsia_sysmem::wire::FormatModifier" = type { i64 }
+%"struct.fidl::Array.95" = type { [32 x %"struct.fuchsia_sysmem::wire::ColorSpace"] }
+%"struct.fuchsia_sysmem::wire::ColorSpace" = type { i32 }
+
+; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
+declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #0
path: llvm/test/CodeGen/RISCV/pr135206.ll
user: login: jrtc27
body: Can we drop the attributes that aren't needed (both on the arguments and in #<n>)?
created_at: 2025-04-10T20:23:26Z
author_association: COLLABORATOR
diff_hunk: @@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+
+; RUN: llc < %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-fuchsia"
+
+%"struct.fuchsia_sysmem::wire::BufferCollectionConstraints" = type { %"struct.fuchsia_sysmem::wire::BufferUsage", i32, i32, i32, i32, i32, i8, %"struct.fuchsia_sysmem::wire::BufferMemoryConstraints", i32, [4 x i8], %"struct.fidl::Array.94" }
+%"struct.fuchsia_sysmem::wire::BufferUsage" = type { i32, i32, i32, i32, i32 }
+%"struct.fuchsia_sysmem::wire::BufferMemoryConstraints" = type { i32, i32, i8, i8, i8, i8, i8, i32, %"struct.fidl::Array" }
+%"struct.fidl::Array" = type { [32 x i64] }
+%"struct.fidl::Array.94" = type { [32 x %"struct.fuchsia_sysmem::wire::ImageFormatConstraints"] }
+%"struct.fuchsia_sysmem::wire::ImageFormatConstraints" = type <{ %"struct.fuchsia_sysmem::wire::PixelFormat", i32, %"struct.fidl::Array.95", i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i8] }>
+%"struct.fuchsia_sysmem::wire::PixelFormat" = type { i32, i8, %"struct.fuchsia_sysmem::wire::FormatModifier" }
+%"struct.fuchsia_sysmem::wire::FormatModifier" = type { i64 }
+%"struct.fidl::Array.95" = type { [32 x %"struct.fuchsia_sysmem::wire::ColorSpace"] }
+%"struct.fuchsia_sysmem::wire::ColorSpace" = type { i32 }
+
+; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
+declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #0
+
+define fastcc i1 @_ZN12_GLOBAL__N_121AttachTokenSucceedsV1EbbN3fit13function_implILm16ELb0EFvRN14fuchsia_sysmem4wire27BufferCollectionConstraintsEENSt3__29allocatorISt4byteEEEESB_SB_NS1_ILm16ELb0EFvRNS3_21BufferCollectionInfo2EESA_EEj() #1 {
path: llvm/test/CodeGen/RISCV/pr135206.ll
user: login: jrtc27
body: ```suggestion
define fastcc i1 @foo() nounwind #1 {
```
(plus same comment re #<n>)

Also, is the fastcc important for reproducing?
created_at: 2025-04-10T20:24:00Z
author_association: COLLABORATOR
diff_hunk: @@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+
+; RUN: llc < %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-fuchsia"
+
+%"struct.fuchsia_sysmem::wire::BufferCollectionConstraints" = type { %"struct.fuchsia_sysmem::wire::BufferUsage", i32, i32, i32, i32, i32, i8, %"struct.fuchsia_sysmem::wire::BufferMemoryConstraints", i32, [4 x i8], %"struct.fidl::Array.94" }
+%"struct.fuchsia_sysmem::wire::BufferUsage" = type { i32, i32, i32, i32, i32 }
+%"struct.fuchsia_sysmem::wire::BufferMemoryConstraints" = type { i32, i32, i8, i8, i8, i8, i8, i32, %"struct.fidl::Array" }
+%"struct.fidl::Array" = type { [32 x i64] }
+%"struct.fidl::Array.94" = type { [32 x %"struct.fuchsia_sysmem::wire::ImageFormatConstraints"] }
+%"struct.fuchsia_sysmem::wire::ImageFormatConstraints" = type <{ %"struct.fuchsia_sysmem::wire::PixelFormat", i32, %"struct.fidl::Array.95", i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i8] }>
+%"struct.fuchsia_sysmem::wire::PixelFormat" = type { i32, i8, %"struct.fuchsia_sysmem::wire::FormatModifier" }
+%"struct.fuchsia_sysmem::wire::FormatModifier" = type { i64 }
+%"struct.fidl::Array.95" = type { [32 x %"struct.fuchsia_sysmem::wire::ColorSpace"] }
+%"struct.fuchsia_sysmem::wire::ColorSpace" = type { i32 }
+
+; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
+declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #0
+
+define fastcc i1 @_ZN12_GLOBAL__N_121AttachTokenSucceedsV1EbbN3fit13function_implILm16ELb0EFvRN14fuchsia_sysmem4wire27BufferCollectionConstraintsEENSt3__29allocatorISt4byteEEEESB_SB_NS1_ILm16ELb0EFvRNS3_21BufferCollectionInfo2EESA_EEj() #1 {
+; CHECK-LABEL: _ZN12_GLOBAL__N_121AttachTokenSucceedsV1EbbN3fit13function_implILm16ELb0EFvRN14fuchsia_sysmem4wire27BufferCollectionConstraintsEENSt3__29allocatorISt4byteEEEESB_SB_NS1_ILm16ELb0EFvRNS3_21BufferCollectionInfo2EESA_EEj:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s1, 2008(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s2, 2000(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s3, 1992(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -8
+; CHECK-NEXT:    .cfi_offset s0, -16
+; CHECK-NEXT:    .cfi_offset s1, -24
+; CHECK-NEXT:    .cfi_offset s2, -32
+; CHECK-NEXT:    .cfi_offset s3, -40
+; CHECK-NEXT:    lui a0, 5
+; CHECK-NEXT:    sub t1, sp, a0
+; CHECK-NEXT:    .cfi_def_cfa t1, 20480
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    bne sp, t1, .LBB0_1
+; CHECK-NEXT:  # %bb.2:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    addi sp, sp, -848
+; CHECK-NEXT:    .cfi_def_cfa_offset 21328
+; CHECK-NEXT:    csrr t1, vlenb
+; CHECK-NEXT:    .cfi_def_cfa t1, -8
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_3: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    sub t1, t1, t2
+; CHECK-NEXT:    bge t1, t2, .LBB0_3
+; CHECK-NEXT:  # %bb.4:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    sub sp, sp, t1
+; CHECK-NEXT:    .cfi_escape 0x0f, 0x0f, 0x72, 0x00, 0x11, 0xc0, 0xb6, 0x01, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 23360 + 1 * vlenb
+; CHECK-NEXT:    li s0, 0
+; CHECK-NEXT:    li a0, 170
+; CHECK-NEXT:    li s1, 32
+; CHECK-NEXT:    lui a1, %hi(.LCPI0_0)
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    lui a0, 6
+; CHECK-NEXT:    addiw a0, a0, -1264
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT:    ld s2, %lo(.LCPI0_0)(a1)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    li s3, 16
+; CHECK-NEXT:    vse8.v v8, (s3)
+; CHECK-NEXT:    vse8.v v8, (zero)
+; CHECK-NEXT:    sd s2, 48(zero)
+; CHECK-NEXT:    jalr s0
+; CHECK-NEXT:    lui a0, 6
+; CHECK-NEXT:    addiw a0, a0, -1264
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vse8.v v8, (zero)
+; CHECK-NEXT:    vse8.v v8, (s3)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    sd s2, 48(zero)
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa sp, 2032
+; CHECK-NEXT:    lui a1, 5
+; CHECK-NEXT:    addiw a1, a1, 848
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s1, 2008(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s2, 2000(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s3, 1992(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    .cfi_restore ra
+; CHECK-NEXT:    .cfi_restore s0
+; CHECK-NEXT:    .cfi_restore s1
+; CHECK-NEXT:    .cfi_restore s2
+; CHECK-NEXT:    .cfi_restore s3
+; CHECK-NEXT:    addi sp, sp, 2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 0
+; CHECK-NEXT:    ret
+  %1 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  %2 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  %3 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  call void @llvm.memset.p0.i64(ptr null, i8 -86, i64 56, i1 false)
+  %4 = call ptr null()
path: llvm/test/CodeGen/RISCV/pr135206.ll
user: login: jrtc27
body: Putting this kind of UB in the test seems like a bad idea, use a dummy external function instead, say?
created_at: 2025-04-10T20:24:33Z
author_association: COLLABORATOR
diff_hunk: @@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+
+; RUN: llc < %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-fuchsia"
+
+%"struct.fuchsia_sysmem::wire::BufferCollectionConstraints" = type { %"struct.fuchsia_sysmem::wire::BufferUsage", i32, i32, i32, i32, i32, i8, %"struct.fuchsia_sysmem::wire::BufferMemoryConstraints", i32, [4 x i8], %"struct.fidl::Array.94" }
+%"struct.fuchsia_sysmem::wire::BufferUsage" = type { i32, i32, i32, i32, i32 }
+%"struct.fuchsia_sysmem::wire::BufferMemoryConstraints" = type { i32, i32, i8, i8, i8, i8, i8, i32, %"struct.fidl::Array" }
+%"struct.fidl::Array" = type { [32 x i64] }
+%"struct.fidl::Array.94" = type { [32 x %"struct.fuchsia_sysmem::wire::ImageFormatConstraints"] }
+%"struct.fuchsia_sysmem::wire::ImageFormatConstraints" = type <{ %"struct.fuchsia_sysmem::wire::PixelFormat", i32, %"struct.fidl::Array.95", i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i8] }>
+%"struct.fuchsia_sysmem::wire::PixelFormat" = type { i32, i8, %"struct.fuchsia_sysmem::wire::FormatModifier" }
+%"struct.fuchsia_sysmem::wire::FormatModifier" = type { i64 }
+%"struct.fidl::Array.95" = type { [32 x %"struct.fuchsia_sysmem::wire::ColorSpace"] }
+%"struct.fuchsia_sysmem::wire::ColorSpace" = type { i32 }
+
+; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
+declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #0
+
+define fastcc i1 @_ZN12_GLOBAL__N_121AttachTokenSucceedsV1EbbN3fit13function_implILm16ELb0EFvRN14fuchsia_sysmem4wire27BufferCollectionConstraintsEENSt3__29allocatorISt4byteEEEESB_SB_NS1_ILm16ELb0EFvRNS3_21BufferCollectionInfo2EESA_EEj() #1 {
+; CHECK-LABEL: _ZN12_GLOBAL__N_121AttachTokenSucceedsV1EbbN3fit13function_implILm16ELb0EFvRN14fuchsia_sysmem4wire27BufferCollectionConstraintsEENSt3__29allocatorISt4byteEEEESB_SB_NS1_ILm16ELb0EFvRNS3_21BufferCollectionInfo2EESA_EEj:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s1, 2008(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s2, 2000(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s3, 1992(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -8
+; CHECK-NEXT:    .cfi_offset s0, -16
+; CHECK-NEXT:    .cfi_offset s1, -24
+; CHECK-NEXT:    .cfi_offset s2, -32
+; CHECK-NEXT:    .cfi_offset s3, -40
+; CHECK-NEXT:    lui a0, 5
+; CHECK-NEXT:    sub t1, sp, a0
+; CHECK-NEXT:    .cfi_def_cfa t1, 20480
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    bne sp, t1, .LBB0_1
+; CHECK-NEXT:  # %bb.2:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    addi sp, sp, -848
+; CHECK-NEXT:    .cfi_def_cfa_offset 21328
+; CHECK-NEXT:    csrr t1, vlenb
+; CHECK-NEXT:    .cfi_def_cfa t1, -8
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_3: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    sub t1, t1, t2
+; CHECK-NEXT:    bge t1, t2, .LBB0_3
+; CHECK-NEXT:  # %bb.4:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    sub sp, sp, t1
+; CHECK-NEXT:    .cfi_escape 0x0f, 0x0f, 0x72, 0x00, 0x11, 0xc0, 0xb6, 0x01, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 23360 + 1 * vlenb
+; CHECK-NEXT:    li s0, 0
+; CHECK-NEXT:    li a0, 170
+; CHECK-NEXT:    li s1, 32
+; CHECK-NEXT:    lui a1, %hi(.LCPI0_0)
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    lui a0, 6
+; CHECK-NEXT:    addiw a0, a0, -1264
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT:    ld s2, %lo(.LCPI0_0)(a1)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    li s3, 16
+; CHECK-NEXT:    vse8.v v8, (s3)
+; CHECK-NEXT:    vse8.v v8, (zero)
+; CHECK-NEXT:    sd s2, 48(zero)
+; CHECK-NEXT:    jalr s0
+; CHECK-NEXT:    lui a0, 6
+; CHECK-NEXT:    addiw a0, a0, -1264
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vse8.v v8, (zero)
+; CHECK-NEXT:    vse8.v v8, (s3)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    sd s2, 48(zero)
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa sp, 2032
+; CHECK-NEXT:    lui a1, 5
+; CHECK-NEXT:    addiw a1, a1, 848
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s1, 2008(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s2, 2000(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s3, 1992(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    .cfi_restore ra
+; CHECK-NEXT:    .cfi_restore s0
+; CHECK-NEXT:    .cfi_restore s1
+; CHECK-NEXT:    .cfi_restore s2
+; CHECK-NEXT:    .cfi_restore s3
+; CHECK-NEXT:    addi sp, sp, 2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 0
+; CHECK-NEXT:    ret
+  %1 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  %2 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  %3 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  call void @llvm.memset.p0.i64(ptr null, i8 -86, i64 56, i1 false)
+  %4 = call ptr null()
+  call void @llvm.memset.p0.i64(ptr null, i8 -86, i64 56, i1 false)
+  ret i1 false
+}
+
+attributes #0 = { nocallback nofree nounwind willreturn memory(argmem: write) }
+attributes #1 = { "probe-stack"="inline-asm" "target-features"="+v" }
path: llvm/test/CodeGen/RISCV/pr135206.ll
user: login: jrtc27
body: Is V important for the reproducer?
created_at: 2025-04-10T20:25:14Z
author_association: COLLABORATOR
diff_hunk: @@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+
+; RUN: llc < %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-fuchsia"
+
+%"struct.fuchsia_sysmem::wire::BufferCollectionConstraints" = type { %"struct.fuchsia_sysmem::wire::BufferUsage", i32, i32, i32, i32, i32, i8, %"struct.fuchsia_sysmem::wire::BufferMemoryConstraints", i32, [4 x i8], %"struct.fidl::Array.94" }
+%"struct.fuchsia_sysmem::wire::BufferUsage" = type { i32, i32, i32, i32, i32 }
+%"struct.fuchsia_sysmem::wire::BufferMemoryConstraints" = type { i32, i32, i8, i8, i8, i8, i8, i32, %"struct.fidl::Array" }
+%"struct.fidl::Array" = type { [32 x i64] }
+%"struct.fidl::Array.94" = type { [32 x %"struct.fuchsia_sysmem::wire::ImageFormatConstraints"] }
+%"struct.fuchsia_sysmem::wire::ImageFormatConstraints" = type <{ %"struct.fuchsia_sysmem::wire::PixelFormat", i32, %"struct.fidl::Array.95", i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i8] }>
+%"struct.fuchsia_sysmem::wire::PixelFormat" = type { i32, i8, %"struct.fuchsia_sysmem::wire::FormatModifier" }
+%"struct.fuchsia_sysmem::wire::FormatModifier" = type { i64 }
+%"struct.fidl::Array.95" = type { [32 x %"struct.fuchsia_sysmem::wire::ColorSpace"] }
+%"struct.fuchsia_sysmem::wire::ColorSpace" = type { i32 }
+
+; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
+declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #0
+
+define fastcc i1 @_ZN12_GLOBAL__N_121AttachTokenSucceedsV1EbbN3fit13function_implILm16ELb0EFvRN14fuchsia_sysmem4wire27BufferCollectionConstraintsEENSt3__29allocatorISt4byteEEEESB_SB_NS1_ILm16ELb0EFvRNS3_21BufferCollectionInfo2EESA_EEj() #1 {
+; CHECK-LABEL: _ZN12_GLOBAL__N_121AttachTokenSucceedsV1EbbN3fit13function_implILm16ELb0EFvRN14fuchsia_sysmem4wire27BufferCollectionConstraintsEENSt3__29allocatorISt4byteEEEESB_SB_NS1_ILm16ELb0EFvRNS3_21BufferCollectionInfo2EESA_EEj:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s1, 2008(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s2, 2000(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s3, 1992(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -8
+; CHECK-NEXT:    .cfi_offset s0, -16
+; CHECK-NEXT:    .cfi_offset s1, -24
+; CHECK-NEXT:    .cfi_offset s2, -32
+; CHECK-NEXT:    .cfi_offset s3, -40
+; CHECK-NEXT:    lui a0, 5
+; CHECK-NEXT:    sub t1, sp, a0
+; CHECK-NEXT:    .cfi_def_cfa t1, 20480
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    bne sp, t1, .LBB0_1
+; CHECK-NEXT:  # %bb.2:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    addi sp, sp, -848
+; CHECK-NEXT:    .cfi_def_cfa_offset 21328
+; CHECK-NEXT:    csrr t1, vlenb
+; CHECK-NEXT:    .cfi_def_cfa t1, -8
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_3: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    sub t1, t1, t2
+; CHECK-NEXT:    bge t1, t2, .LBB0_3
+; CHECK-NEXT:  # %bb.4:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    sub sp, sp, t1
+; CHECK-NEXT:    .cfi_escape 0x0f, 0x0f, 0x72, 0x00, 0x11, 0xc0, 0xb6, 0x01, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 23360 + 1 * vlenb
+; CHECK-NEXT:    li s0, 0
+; CHECK-NEXT:    li a0, 170
+; CHECK-NEXT:    li s1, 32
+; CHECK-NEXT:    lui a1, %hi(.LCPI0_0)
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    lui a0, 6
+; CHECK-NEXT:    addiw a0, a0, -1264
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT:    ld s2, %lo(.LCPI0_0)(a1)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    li s3, 16
+; CHECK-NEXT:    vse8.v v8, (s3)
+; CHECK-NEXT:    vse8.v v8, (zero)
+; CHECK-NEXT:    sd s2, 48(zero)
+; CHECK-NEXT:    jalr s0
+; CHECK-NEXT:    lui a0, 6
+; CHECK-NEXT:    addiw a0, a0, -1264
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vse8.v v8, (zero)
+; CHECK-NEXT:    vse8.v v8, (s3)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    sd s2, 48(zero)
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa sp, 2032
+; CHECK-NEXT:    lui a1, 5
+; CHECK-NEXT:    addiw a1, a1, 848
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s1, 2008(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s2, 2000(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s3, 1992(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    .cfi_restore ra
+; CHECK-NEXT:    .cfi_restore s0
+; CHECK-NEXT:    .cfi_restore s1
+; CHECK-NEXT:    .cfi_restore s2
+; CHECK-NEXT:    .cfi_restore s3
+; CHECK-NEXT:    addi sp, sp, 2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 0
+; CHECK-NEXT:    ret
+  %1 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  %2 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  %3 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  call void @llvm.memset.p0.i64(ptr null, i8 -86, i64 56, i1 false)
+  %4 = call ptr null()
path: llvm/test/CodeGen/RISCV/pr135206.ll
user: login: ilovepi
body: probably a good idea. This is just what came out of `llvm-reduce` from our reproducer. I'll take a pass at minimizing this further.
created_at: 2025-04-10T20:56:50Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+
+; RUN: llc < %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-fuchsia"
+
+%"struct.fuchsia_sysmem::wire::BufferCollectionConstraints" = type { %"struct.fuchsia_sysmem::wire::BufferUsage", i32, i32, i32, i32, i32, i8, %"struct.fuchsia_sysmem::wire::BufferMemoryConstraints", i32, [4 x i8], %"struct.fidl::Array.94" }
+%"struct.fuchsia_sysmem::wire::BufferUsage" = type { i32, i32, i32, i32, i32 }
+%"struct.fuchsia_sysmem::wire::BufferMemoryConstraints" = type { i32, i32, i8, i8, i8, i8, i8, i32, %"struct.fidl::Array" }
+%"struct.fidl::Array" = type { [32 x i64] }
+%"struct.fidl::Array.94" = type { [32 x %"struct.fuchsia_sysmem::wire::ImageFormatConstraints"] }
+%"struct.fuchsia_sysmem::wire::ImageFormatConstraints" = type <{ %"struct.fuchsia_sysmem::wire::PixelFormat", i32, %"struct.fidl::Array.95", i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i8] }>
+%"struct.fuchsia_sysmem::wire::PixelFormat" = type { i32, i8, %"struct.fuchsia_sysmem::wire::FormatModifier" }
+%"struct.fuchsia_sysmem::wire::FormatModifier" = type { i64 }
+%"struct.fidl::Array.95" = type { [32 x %"struct.fuchsia_sysmem::wire::ColorSpace"] }
+%"struct.fuchsia_sysmem::wire::ColorSpace" = type { i32 }
+
+; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
+declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #0
+
+define fastcc i1 @_ZN12_GLOBAL__N_121AttachTokenSucceedsV1EbbN3fit13function_implILm16ELb0EFvRN14fuchsia_sysmem4wire27BufferCollectionConstraintsEENSt3__29allocatorISt4byteEEEESB_SB_NS1_ILm16ELb0EFvRNS3_21BufferCollectionInfo2EESA_EEj() #1 {
+; CHECK-LABEL: _ZN12_GLOBAL__N_121AttachTokenSucceedsV1EbbN3fit13function_implILm16ELb0EFvRN14fuchsia_sysmem4wire27BufferCollectionConstraintsEENSt3__29allocatorISt4byteEEEESB_SB_NS1_ILm16ELb0EFvRNS3_21BufferCollectionInfo2EESA_EEj:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s1, 2008(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s2, 2000(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s3, 1992(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -8
+; CHECK-NEXT:    .cfi_offset s0, -16
+; CHECK-NEXT:    .cfi_offset s1, -24
+; CHECK-NEXT:    .cfi_offset s2, -32
+; CHECK-NEXT:    .cfi_offset s3, -40
+; CHECK-NEXT:    lui a0, 5
+; CHECK-NEXT:    sub t1, sp, a0
+; CHECK-NEXT:    .cfi_def_cfa t1, 20480
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    bne sp, t1, .LBB0_1
+; CHECK-NEXT:  # %bb.2:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    addi sp, sp, -848
+; CHECK-NEXT:    .cfi_def_cfa_offset 21328
+; CHECK-NEXT:    csrr t1, vlenb
+; CHECK-NEXT:    .cfi_def_cfa t1, -8
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_3: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    sub t1, t1, t2
+; CHECK-NEXT:    bge t1, t2, .LBB0_3
+; CHECK-NEXT:  # %bb.4:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    sub sp, sp, t1
+; CHECK-NEXT:    .cfi_escape 0x0f, 0x0f, 0x72, 0x00, 0x11, 0xc0, 0xb6, 0x01, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 23360 + 1 * vlenb
+; CHECK-NEXT:    li s0, 0
+; CHECK-NEXT:    li a0, 170
+; CHECK-NEXT:    li s1, 32
+; CHECK-NEXT:    lui a1, %hi(.LCPI0_0)
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    lui a0, 6
+; CHECK-NEXT:    addiw a0, a0, -1264
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT:    ld s2, %lo(.LCPI0_0)(a1)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    li s3, 16
+; CHECK-NEXT:    vse8.v v8, (s3)
+; CHECK-NEXT:    vse8.v v8, (zero)
+; CHECK-NEXT:    sd s2, 48(zero)
+; CHECK-NEXT:    jalr s0
+; CHECK-NEXT:    lui a0, 6
+; CHECK-NEXT:    addiw a0, a0, -1264
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vse8.v v8, (zero)
+; CHECK-NEXT:    vse8.v v8, (s3)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    sd s2, 48(zero)
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa sp, 2032
+; CHECK-NEXT:    lui a1, 5
+; CHECK-NEXT:    addiw a1, a1, 848
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s1, 2008(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s2, 2000(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s3, 1992(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    .cfi_restore ra
+; CHECK-NEXT:    .cfi_restore s0
+; CHECK-NEXT:    .cfi_restore s1
+; CHECK-NEXT:    .cfi_restore s2
+; CHECK-NEXT:    .cfi_restore s3
+; CHECK-NEXT:    addi sp, sp, 2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 0
+; CHECK-NEXT:    ret
+  %1 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  %2 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  %3 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  call void @llvm.memset.p0.i64(ptr null, i8 -86, i64 56, i1 false)
+  %4 = call ptr null()
+  call void @llvm.memset.p0.i64(ptr null, i8 -86, i64 56, i1 false)
+  ret i1 false
+}
+
+attributes #0 = { nocallback nofree nounwind willreturn memory(argmem: write) }
+attributes #1 = { "probe-stack"="inline-asm" "target-features"="+v" }
path: llvm/test/CodeGen/RISCV/pr135206.ll
user: login: ilovepi
body: not sure. Let me see if it still works w/o it.
created_at: 2025-04-10T20:57:15Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+
+; RUN: llc < %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-fuchsia"
+
+%"struct.fuchsia_sysmem::wire::BufferCollectionConstraints" = type { %"struct.fuchsia_sysmem::wire::BufferUsage", i32, i32, i32, i32, i32, i8, %"struct.fuchsia_sysmem::wire::BufferMemoryConstraints", i32, [4 x i8], %"struct.fidl::Array.94" }
+%"struct.fuchsia_sysmem::wire::BufferUsage" = type { i32, i32, i32, i32, i32 }
+%"struct.fuchsia_sysmem::wire::BufferMemoryConstraints" = type { i32, i32, i8, i8, i8, i8, i8, i32, %"struct.fidl::Array" }
+%"struct.fidl::Array" = type { [32 x i64] }
+%"struct.fidl::Array.94" = type { [32 x %"struct.fuchsia_sysmem::wire::ImageFormatConstraints"] }
+%"struct.fuchsia_sysmem::wire::ImageFormatConstraints" = type <{ %"struct.fuchsia_sysmem::wire::PixelFormat", i32, %"struct.fidl::Array.95", i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i8] }>
+%"struct.fuchsia_sysmem::wire::PixelFormat" = type { i32, i8, %"struct.fuchsia_sysmem::wire::FormatModifier" }
+%"struct.fuchsia_sysmem::wire::FormatModifier" = type { i64 }
+%"struct.fidl::Array.95" = type { [32 x %"struct.fuchsia_sysmem::wire::ColorSpace"] }
+%"struct.fuchsia_sysmem::wire::ColorSpace" = type { i32 }
+
+; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
+declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #0
+
+define fastcc i1 @_ZN12_GLOBAL__N_121AttachTokenSucceedsV1EbbN3fit13function_implILm16ELb0EFvRN14fuchsia_sysmem4wire27BufferCollectionConstraintsEENSt3__29allocatorISt4byteEEEESB_SB_NS1_ILm16ELb0EFvRNS3_21BufferCollectionInfo2EESA_EEj() #1 {
path: llvm/test/CodeGen/RISCV/pr135206.ll
user: login: ilovepi
body: Done. `fastcc` did not seem to be required.
created_at: 2025-04-10T21:23:34Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+
+; RUN: llc < %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-fuchsia"
+
+%"struct.fuchsia_sysmem::wire::BufferCollectionConstraints" = type { %"struct.fuchsia_sysmem::wire::BufferUsage", i32, i32, i32, i32, i32, i8, %"struct.fuchsia_sysmem::wire::BufferMemoryConstraints", i32, [4 x i8], %"struct.fidl::Array.94" }
+%"struct.fuchsia_sysmem::wire::BufferUsage" = type { i32, i32, i32, i32, i32 }
+%"struct.fuchsia_sysmem::wire::BufferMemoryConstraints" = type { i32, i32, i8, i8, i8, i8, i8, i32, %"struct.fidl::Array" }
+%"struct.fidl::Array" = type { [32 x i64] }
+%"struct.fidl::Array.94" = type { [32 x %"struct.fuchsia_sysmem::wire::ImageFormatConstraints"] }
+%"struct.fuchsia_sysmem::wire::ImageFormatConstraints" = type <{ %"struct.fuchsia_sysmem::wire::PixelFormat", i32, %"struct.fidl::Array.95", i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i8] }>
+%"struct.fuchsia_sysmem::wire::PixelFormat" = type { i32, i8, %"struct.fuchsia_sysmem::wire::FormatModifier" }
+%"struct.fuchsia_sysmem::wire::FormatModifier" = type { i64 }
+%"struct.fidl::Array.95" = type { [32 x %"struct.fuchsia_sysmem::wire::ColorSpace"] }
+%"struct.fuchsia_sysmem::wire::ColorSpace" = type { i32 }
+
+; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
+declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #0
+
+define fastcc i1 @_ZN12_GLOBAL__N_121AttachTokenSucceedsV1EbbN3fit13function_implILm16ELb0EFvRN14fuchsia_sysmem4wire27BufferCollectionConstraintsEENSt3__29allocatorISt4byteEEEESB_SB_NS1_ILm16ELb0EFvRNS3_21BufferCollectionInfo2EESA_EEj() #1 {
+; CHECK-LABEL: _ZN12_GLOBAL__N_121AttachTokenSucceedsV1EbbN3fit13function_implILm16ELb0EFvRN14fuchsia_sysmem4wire27BufferCollectionConstraintsEENSt3__29allocatorISt4byteEEEESB_SB_NS1_ILm16ELb0EFvRNS3_21BufferCollectionInfo2EESA_EEj:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s1, 2008(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s2, 2000(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s3, 1992(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -8
+; CHECK-NEXT:    .cfi_offset s0, -16
+; CHECK-NEXT:    .cfi_offset s1, -24
+; CHECK-NEXT:    .cfi_offset s2, -32
+; CHECK-NEXT:    .cfi_offset s3, -40
+; CHECK-NEXT:    lui a0, 5
+; CHECK-NEXT:    sub t1, sp, a0
+; CHECK-NEXT:    .cfi_def_cfa t1, 20480
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    bne sp, t1, .LBB0_1
+; CHECK-NEXT:  # %bb.2:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    addi sp, sp, -848
+; CHECK-NEXT:    .cfi_def_cfa_offset 21328
+; CHECK-NEXT:    csrr t1, vlenb
+; CHECK-NEXT:    .cfi_def_cfa t1, -8
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_3: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    sub t1, t1, t2
+; CHECK-NEXT:    bge t1, t2, .LBB0_3
+; CHECK-NEXT:  # %bb.4:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    sub sp, sp, t1
+; CHECK-NEXT:    .cfi_escape 0x0f, 0x0f, 0x72, 0x00, 0x11, 0xc0, 0xb6, 0x01, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 23360 + 1 * vlenb
+; CHECK-NEXT:    li s0, 0
+; CHECK-NEXT:    li a0, 170
+; CHECK-NEXT:    li s1, 32
+; CHECK-NEXT:    lui a1, %hi(.LCPI0_0)
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    lui a0, 6
+; CHECK-NEXT:    addiw a0, a0, -1264
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT:    ld s2, %lo(.LCPI0_0)(a1)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    li s3, 16
+; CHECK-NEXT:    vse8.v v8, (s3)
+; CHECK-NEXT:    vse8.v v8, (zero)
+; CHECK-NEXT:    sd s2, 48(zero)
+; CHECK-NEXT:    jalr s0
+; CHECK-NEXT:    lui a0, 6
+; CHECK-NEXT:    addiw a0, a0, -1264
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vse8.v v8, (zero)
+; CHECK-NEXT:    vse8.v v8, (s3)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    sd s2, 48(zero)
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa sp, 2032
+; CHECK-NEXT:    lui a1, 5
+; CHECK-NEXT:    addiw a1, a1, 848
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s1, 2008(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s2, 2000(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s3, 1992(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    .cfi_restore ra
+; CHECK-NEXT:    .cfi_restore s0
+; CHECK-NEXT:    .cfi_restore s1
+; CHECK-NEXT:    .cfi_restore s2
+; CHECK-NEXT:    .cfi_restore s3
+; CHECK-NEXT:    addi sp, sp, 2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 0
+; CHECK-NEXT:    ret
+  %1 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  %2 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  %3 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  call void @llvm.memset.p0.i64(ptr null, i8 -86, i64 56, i1 false)
+  %4 = call ptr null()
path: llvm/test/CodeGen/RISCV/pr135206.ll
user: login: ilovepi
body: Done
created_at: 2025-04-10T21:24:01Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+
+; RUN: llc < %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-fuchsia"
+
+%"struct.fuchsia_sysmem::wire::BufferCollectionConstraints" = type { %"struct.fuchsia_sysmem::wire::BufferUsage", i32, i32, i32, i32, i32, i8, %"struct.fuchsia_sysmem::wire::BufferMemoryConstraints", i32, [4 x i8], %"struct.fidl::Array.94" }
+%"struct.fuchsia_sysmem::wire::BufferUsage" = type { i32, i32, i32, i32, i32 }
+%"struct.fuchsia_sysmem::wire::BufferMemoryConstraints" = type { i32, i32, i8, i8, i8, i8, i8, i32, %"struct.fidl::Array" }
+%"struct.fidl::Array" = type { [32 x i64] }
+%"struct.fidl::Array.94" = type { [32 x %"struct.fuchsia_sysmem::wire::ImageFormatConstraints"] }
+%"struct.fuchsia_sysmem::wire::ImageFormatConstraints" = type <{ %"struct.fuchsia_sysmem::wire::PixelFormat", i32, %"struct.fidl::Array.95", i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i8] }>
+%"struct.fuchsia_sysmem::wire::PixelFormat" = type { i32, i8, %"struct.fuchsia_sysmem::wire::FormatModifier" }
+%"struct.fuchsia_sysmem::wire::FormatModifier" = type { i64 }
+%"struct.fidl::Array.95" = type { [32 x %"struct.fuchsia_sysmem::wire::ColorSpace"] }
+%"struct.fuchsia_sysmem::wire::ColorSpace" = type { i32 }
+
+; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
+declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #0
+
+define fastcc i1 @_ZN12_GLOBAL__N_121AttachTokenSucceedsV1EbbN3fit13function_implILm16ELb0EFvRN14fuchsia_sysmem4wire27BufferCollectionConstraintsEENSt3__29allocatorISt4byteEEEESB_SB_NS1_ILm16ELb0EFvRNS3_21BufferCollectionInfo2EESA_EEj() #1 {
+; CHECK-LABEL: _ZN12_GLOBAL__N_121AttachTokenSucceedsV1EbbN3fit13function_implILm16ELb0EFvRN14fuchsia_sysmem4wire27BufferCollectionConstraintsEENSt3__29allocatorISt4byteEEEESB_SB_NS1_ILm16ELb0EFvRNS3_21BufferCollectionInfo2EESA_EEj:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s1, 2008(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s2, 2000(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s3, 1992(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -8
+; CHECK-NEXT:    .cfi_offset s0, -16
+; CHECK-NEXT:    .cfi_offset s1, -24
+; CHECK-NEXT:    .cfi_offset s2, -32
+; CHECK-NEXT:    .cfi_offset s3, -40
+; CHECK-NEXT:    lui a0, 5
+; CHECK-NEXT:    sub t1, sp, a0
+; CHECK-NEXT:    .cfi_def_cfa t1, 20480
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    bne sp, t1, .LBB0_1
+; CHECK-NEXT:  # %bb.2:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    addi sp, sp, -848
+; CHECK-NEXT:    .cfi_def_cfa_offset 21328
+; CHECK-NEXT:    csrr t1, vlenb
+; CHECK-NEXT:    .cfi_def_cfa t1, -8
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_3: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    sub t1, t1, t2
+; CHECK-NEXT:    bge t1, t2, .LBB0_3
+; CHECK-NEXT:  # %bb.4:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    sub sp, sp, t1
+; CHECK-NEXT:    .cfi_escape 0x0f, 0x0f, 0x72, 0x00, 0x11, 0xc0, 0xb6, 0x01, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 23360 + 1 * vlenb
+; CHECK-NEXT:    li s0, 0
+; CHECK-NEXT:    li a0, 170
+; CHECK-NEXT:    li s1, 32
+; CHECK-NEXT:    lui a1, %hi(.LCPI0_0)
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    lui a0, 6
+; CHECK-NEXT:    addiw a0, a0, -1264
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT:    ld s2, %lo(.LCPI0_0)(a1)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    li s3, 16
+; CHECK-NEXT:    vse8.v v8, (s3)
+; CHECK-NEXT:    vse8.v v8, (zero)
+; CHECK-NEXT:    sd s2, 48(zero)
+; CHECK-NEXT:    jalr s0
+; CHECK-NEXT:    lui a0, 6
+; CHECK-NEXT:    addiw a0, a0, -1264
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vse8.v v8, (zero)
+; CHECK-NEXT:    vse8.v v8, (s3)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    sd s2, 48(zero)
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa sp, 2032
+; CHECK-NEXT:    lui a1, 5
+; CHECK-NEXT:    addiw a1, a1, 848
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s1, 2008(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s2, 2000(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s3, 1992(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    .cfi_restore ra
+; CHECK-NEXT:    .cfi_restore s0
+; CHECK-NEXT:    .cfi_restore s1
+; CHECK-NEXT:    .cfi_restore s2
+; CHECK-NEXT:    .cfi_restore s3
+; CHECK-NEXT:    addi sp, sp, 2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 0
+; CHECK-NEXT:    ret
+  %1 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  %2 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  %3 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  call void @llvm.memset.p0.i64(ptr null, i8 -86, i64 56, i1 false)
+  %4 = call ptr null()
+  call void @llvm.memset.p0.i64(ptr null, i8 -86, i64 56, i1 false)
+  ret i1 false
+}
+
+attributes #0 = { nocallback nofree nounwind willreturn memory(argmem: write) }
+attributes #1 = { "probe-stack"="inline-asm" "target-features"="+v" }
path: llvm/test/CodeGen/RISCV/pr135206.ll
user: login: ilovepi
body: Yeah, `+v` did seem to be required. Looking at the fix again, that makes sense due to the `(MI->getOpcode() == RISCV::PROBED_STACKALLOC_RVV)` bits. I'm guessing that if only one of the stack probes gets used, it wouldn't foul up the iterator.
created_at: 2025-04-10T21:26:53Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,105 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple riscv64 < %s -o - | FileCheck %s
+
+%"buff" = type { [4096 x i64] }
+
+declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg)
+declare ptr @bar()
+
+define i1 @foo() #0 {
path: llvm/test/CodeGen/RISCV/pr135206.ll
user: login: jrtc27
body: nounwind?
created_at: 2025-04-10T21:29:39Z
author_association: COLLABORATOR
diff_hunk: @@ -0,0 +1,105 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple riscv64 < %s -o - | FileCheck %s
+
+%"buff" = type { [4096 x i64] }
+
+declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg)
+declare ptr @bar()
+
+define i1 @foo() #0 {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s1, 2008(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s2, 2000(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s3, 1992(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -8
+; CHECK-NEXT:    .cfi_offset s0, -16
+; CHECK-NEXT:    .cfi_offset s1, -24
+; CHECK-NEXT:    .cfi_offset s2, -32
+; CHECK-NEXT:    .cfi_offset s3, -40
+; CHECK-NEXT:    lui a0, 7
+; CHECK-NEXT:    sub t1, sp, a0
+; CHECK-NEXT:    .cfi_def_cfa t1, 28672
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    bne sp, t1, .LBB0_1
+; CHECK-NEXT:  # %bb.2:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    addi sp, sp, -2048
+; CHECK-NEXT:    addi sp, sp, -96
+; CHECK-NEXT:    .cfi_def_cfa_offset 30816
+; CHECK-NEXT:    csrr t1, vlenb
+; CHECK-NEXT:    .cfi_def_cfa t1, -8
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_3: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    sub t1, t1, t2
+; CHECK-NEXT:    bge t1, t2, .LBB0_3
+; CHECK-NEXT:  # %bb.4:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    sub sp, sp, t1
+; CHECK-NEXT:    .cfi_escape 0x0f, 0x0f, 0x72, 0x00, 0x11, 0xd0, 0x80, 0x02, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32848 + 1 * vlenb
+; CHECK-NEXT:    li a0, 86
+; CHECK-NEXT:    addi s0, sp, 48
+; CHECK-NEXT:    addi s1, sp, 32
+; CHECK-NEXT:    addi s2, sp, 16
+; CHECK-NEXT:    lui a1, 353637
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    lui a0, 8
+; CHECK-NEXT:    addiw a0, a0, 32
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT:    addiw a0, a1, 1622
+; CHECK-NEXT:    vse8.v v8, (s0)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    vse8.v v8, (s2)
+; CHECK-NEXT:    slli a1, a0, 32
+; CHECK-NEXT:    add s3, a0, a1
+; CHECK-NEXT:    sd s3, 64(sp)
+; CHECK-NEXT:    call bar
+; CHECK-NEXT:    lui a0, 8
+; CHECK-NEXT:    addiw a0, a0, 32
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vse8.v v8, (s2)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    vse8.v v8, (s0)
+; CHECK-NEXT:    sd s3, 64(sp)
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa sp, 2032
+; CHECK-NEXT:    lui a1, 8
+; CHECK-NEXT:    addiw a1, a1, -1952
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s1, 2008(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s2, 2000(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s3, 1992(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    .cfi_restore ra
+; CHECK-NEXT:    .cfi_restore s0
+; CHECK-NEXT:    .cfi_restore s1
+; CHECK-NEXT:    .cfi_restore s2
+; CHECK-NEXT:    .cfi_restore s3
+; CHECK-NEXT:    addi sp, sp, 2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 0
+; CHECK-NEXT:    ret
+  %1 = alloca %"buff", align 8
+  call void @llvm.memset.p0.i64(ptr %1, i8 86, i64 56, i1 false)
+  %4 = call ptr @bar()
+  call void @llvm.memset.p0.i64(ptr %1, i8 86, i64 56, i1 false)
+  ret i1 false
+}
+
+attributes #0 = { "probe-stack"="inline-asm" "target-features"="+v" }
path: llvm/test/CodeGen/RISCV/pr135206.ll
user: login: jrtc27
body: Perhaps inline this for clarity?
created_at: 2025-04-10T21:29:57Z
author_association: COLLABORATOR
diff_hunk: @@ -0,0 +1,105 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple riscv64 < %s -o - | FileCheck %s
+
+%"buff" = type { [4096 x i64] }
+
+declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg)
+declare ptr @bar()
+
+define i1 @foo() #0 {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s1, 2008(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s2, 2000(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s3, 1992(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -8
+; CHECK-NEXT:    .cfi_offset s0, -16
+; CHECK-NEXT:    .cfi_offset s1, -24
+; CHECK-NEXT:    .cfi_offset s2, -32
+; CHECK-NEXT:    .cfi_offset s3, -40
+; CHECK-NEXT:    lui a0, 7
+; CHECK-NEXT:    sub t1, sp, a0
+; CHECK-NEXT:    .cfi_def_cfa t1, 28672
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    bne sp, t1, .LBB0_1
+; CHECK-NEXT:  # %bb.2:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    addi sp, sp, -2048
+; CHECK-NEXT:    addi sp, sp, -96
+; CHECK-NEXT:    .cfi_def_cfa_offset 30816
+; CHECK-NEXT:    csrr t1, vlenb
+; CHECK-NEXT:    .cfi_def_cfa t1, -8
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_3: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    sub t1, t1, t2
+; CHECK-NEXT:    bge t1, t2, .LBB0_3
+; CHECK-NEXT:  # %bb.4:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    sub sp, sp, t1
+; CHECK-NEXT:    .cfi_escape 0x0f, 0x0f, 0x72, 0x00, 0x11, 0xd0, 0x80, 0x02, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32848 + 1 * vlenb
+; CHECK-NEXT:    li a0, 86
+; CHECK-NEXT:    addi s0, sp, 48
+; CHECK-NEXT:    addi s1, sp, 32
+; CHECK-NEXT:    addi s2, sp, 16
+; CHECK-NEXT:    lui a1, 353637
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    lui a0, 8
+; CHECK-NEXT:    addiw a0, a0, 32
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT:    addiw a0, a1, 1622
+; CHECK-NEXT:    vse8.v v8, (s0)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    vse8.v v8, (s2)
+; CHECK-NEXT:    slli a1, a0, 32
+; CHECK-NEXT:    add s3, a0, a1
+; CHECK-NEXT:    sd s3, 64(sp)
+; CHECK-NEXT:    call bar
+; CHECK-NEXT:    lui a0, 8
+; CHECK-NEXT:    addiw a0, a0, 32
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vse8.v v8, (s2)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    vse8.v v8, (s0)
+; CHECK-NEXT:    sd s3, 64(sp)
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa sp, 2032
+; CHECK-NEXT:    lui a1, 8
+; CHECK-NEXT:    addiw a1, a1, -1952
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s1, 2008(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s2, 2000(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s3, 1992(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    .cfi_restore ra
+; CHECK-NEXT:    .cfi_restore s0
+; CHECK-NEXT:    .cfi_restore s1
+; CHECK-NEXT:    .cfi_restore s2
+; CHECK-NEXT:    .cfi_restore s3
+; CHECK-NEXT:    addi sp, sp, 2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 0
+; CHECK-NEXT:    ret
+  %1 = alloca %"buff", align 8
+  call void @llvm.memset.p0.i64(ptr %1, i8 86, i64 56, i1 false)
+  %4 = call ptr @bar()
path: llvm/test/CodeGen/RISCV/pr135206.ll
user: login: jrtc27
body: Does this actually need to return a value, or can it be `call void @bar()`?
created_at: 2025-04-10T21:30:15Z
author_association: COLLABORATOR
diff_hunk: @@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+
+; RUN: llc < %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-fuchsia"
+
+%"struct.fuchsia_sysmem::wire::BufferCollectionConstraints" = type { %"struct.fuchsia_sysmem::wire::BufferUsage", i32, i32, i32, i32, i32, i8, %"struct.fuchsia_sysmem::wire::BufferMemoryConstraints", i32, [4 x i8], %"struct.fidl::Array.94" }
+%"struct.fuchsia_sysmem::wire::BufferUsage" = type { i32, i32, i32, i32, i32 }
+%"struct.fuchsia_sysmem::wire::BufferMemoryConstraints" = type { i32, i32, i8, i8, i8, i8, i8, i32, %"struct.fidl::Array" }
+%"struct.fidl::Array" = type { [32 x i64] }
+%"struct.fidl::Array.94" = type { [32 x %"struct.fuchsia_sysmem::wire::ImageFormatConstraints"] }
+%"struct.fuchsia_sysmem::wire::ImageFormatConstraints" = type <{ %"struct.fuchsia_sysmem::wire::PixelFormat", i32, %"struct.fidl::Array.95", i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i8] }>
+%"struct.fuchsia_sysmem::wire::PixelFormat" = type { i32, i8, %"struct.fuchsia_sysmem::wire::FormatModifier" }
+%"struct.fuchsia_sysmem::wire::FormatModifier" = type { i64 }
+%"struct.fidl::Array.95" = type { [32 x %"struct.fuchsia_sysmem::wire::ColorSpace"] }
+%"struct.fuchsia_sysmem::wire::ColorSpace" = type { i32 }
+
+; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
+declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #0
path: llvm/test/CodeGen/RISCV/pr135206.ll
user: login: ilovepi
body: tried using a small extern function, but I think this needs to be llvm.memset, and the number of args are fixed. I was able to drop the attrs though.
created_at: 2025-04-10T21:36:08Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,105 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple riscv64 < %s -o - | FileCheck %s
+
+%"buff" = type { [4096 x i64] }
+
+declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg)
+declare ptr @bar()
+
+define i1 @foo() #0 {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s1, 2008(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s2, 2000(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s3, 1992(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -8
+; CHECK-NEXT:    .cfi_offset s0, -16
+; CHECK-NEXT:    .cfi_offset s1, -24
+; CHECK-NEXT:    .cfi_offset s2, -32
+; CHECK-NEXT:    .cfi_offset s3, -40
+; CHECK-NEXT:    lui a0, 7
+; CHECK-NEXT:    sub t1, sp, a0
+; CHECK-NEXT:    .cfi_def_cfa t1, 28672
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    bne sp, t1, .LBB0_1
+; CHECK-NEXT:  # %bb.2:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    addi sp, sp, -2048
+; CHECK-NEXT:    addi sp, sp, -96
+; CHECK-NEXT:    .cfi_def_cfa_offset 30816
+; CHECK-NEXT:    csrr t1, vlenb
+; CHECK-NEXT:    .cfi_def_cfa t1, -8
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_3: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    sub t1, t1, t2
+; CHECK-NEXT:    bge t1, t2, .LBB0_3
+; CHECK-NEXT:  # %bb.4:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    sub sp, sp, t1
+; CHECK-NEXT:    .cfi_escape 0x0f, 0x0f, 0x72, 0x00, 0x11, 0xd0, 0x80, 0x02, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32848 + 1 * vlenb
+; CHECK-NEXT:    li a0, 86
+; CHECK-NEXT:    addi s0, sp, 48
+; CHECK-NEXT:    addi s1, sp, 32
+; CHECK-NEXT:    addi s2, sp, 16
+; CHECK-NEXT:    lui a1, 353637
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    lui a0, 8
+; CHECK-NEXT:    addiw a0, a0, 32
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT:    addiw a0, a1, 1622
+; CHECK-NEXT:    vse8.v v8, (s0)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    vse8.v v8, (s2)
+; CHECK-NEXT:    slli a1, a0, 32
+; CHECK-NEXT:    add s3, a0, a1
+; CHECK-NEXT:    sd s3, 64(sp)
+; CHECK-NEXT:    call bar
+; CHECK-NEXT:    lui a0, 8
+; CHECK-NEXT:    addiw a0, a0, 32
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vse8.v v8, (s2)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    vse8.v v8, (s0)
+; CHECK-NEXT:    sd s3, 64(sp)
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa sp, 2032
+; CHECK-NEXT:    lui a1, 8
+; CHECK-NEXT:    addiw a1, a1, -1952
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s1, 2008(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s2, 2000(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s3, 1992(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    .cfi_restore ra
+; CHECK-NEXT:    .cfi_restore s0
+; CHECK-NEXT:    .cfi_restore s1
+; CHECK-NEXT:    .cfi_restore s2
+; CHECK-NEXT:    .cfi_restore s3
+; CHECK-NEXT:    addi sp, sp, 2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 0
+; CHECK-NEXT:    ret
+  %1 = alloca %"buff", align 8
+  call void @llvm.memset.p0.i64(ptr %1, i8 86, i64 56, i1 false)
+  %4 = call ptr @bar()
path: llvm/test/CodeGen/RISCV/pr135206.ll
user: login: ilovepi
body: oh, yeah it can be void. Good catch!
created_at: 2025-04-10T21:43:52Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,105 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple riscv64 < %s -o - | FileCheck %s
+
+%"buff" = type { [4096 x i64] }
+
+declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg)
+declare ptr @bar()
+
+define i1 @foo() #0 {
path: llvm/test/CodeGen/RISCV/pr135206.ll
user: login: ilovepi
body: Done.
created_at: 2025-04-10T21:49:45Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,105 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple riscv64 < %s -o - | FileCheck %s
+
+%"buff" = type { [4096 x i64] }
+
+declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg)
+declare ptr @bar()
+
+define i1 @foo() #0 {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s1, 2008(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s2, 2000(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s3, 1992(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -8
+; CHECK-NEXT:    .cfi_offset s0, -16
+; CHECK-NEXT:    .cfi_offset s1, -24
+; CHECK-NEXT:    .cfi_offset s2, -32
+; CHECK-NEXT:    .cfi_offset s3, -40
+; CHECK-NEXT:    lui a0, 7
+; CHECK-NEXT:    sub t1, sp, a0
+; CHECK-NEXT:    .cfi_def_cfa t1, 28672
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    bne sp, t1, .LBB0_1
+; CHECK-NEXT:  # %bb.2:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    addi sp, sp, -2048
+; CHECK-NEXT:    addi sp, sp, -96
+; CHECK-NEXT:    .cfi_def_cfa_offset 30816
+; CHECK-NEXT:    csrr t1, vlenb
+; CHECK-NEXT:    .cfi_def_cfa t1, -8
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_3: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    sub t1, t1, t2
+; CHECK-NEXT:    bge t1, t2, .LBB0_3
+; CHECK-NEXT:  # %bb.4:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    sub sp, sp, t1
+; CHECK-NEXT:    .cfi_escape 0x0f, 0x0f, 0x72, 0x00, 0x11, 0xd0, 0x80, 0x02, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32848 + 1 * vlenb
+; CHECK-NEXT:    li a0, 86
+; CHECK-NEXT:    addi s0, sp, 48
+; CHECK-NEXT:    addi s1, sp, 32
+; CHECK-NEXT:    addi s2, sp, 16
+; CHECK-NEXT:    lui a1, 353637
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    lui a0, 8
+; CHECK-NEXT:    addiw a0, a0, 32
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT:    addiw a0, a1, 1622
+; CHECK-NEXT:    vse8.v v8, (s0)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    vse8.v v8, (s2)
+; CHECK-NEXT:    slli a1, a0, 32
+; CHECK-NEXT:    add s3, a0, a1
+; CHECK-NEXT:    sd s3, 64(sp)
+; CHECK-NEXT:    call bar
+; CHECK-NEXT:    lui a0, 8
+; CHECK-NEXT:    addiw a0, a0, 32
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vse8.v v8, (s2)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    vse8.v v8, (s0)
+; CHECK-NEXT:    sd s3, 64(sp)
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa sp, 2032
+; CHECK-NEXT:    lui a1, 8
+; CHECK-NEXT:    addiw a1, a1, -1952
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s1, 2008(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s2, 2000(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s3, 1992(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    .cfi_restore ra
+; CHECK-NEXT:    .cfi_restore s0
+; CHECK-NEXT:    .cfi_restore s1
+; CHECK-NEXT:    .cfi_restore s2
+; CHECK-NEXT:    .cfi_restore s3
+; CHECK-NEXT:    addi sp, sp, 2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 0
+; CHECK-NEXT:    ret
+  %1 = alloca %"buff", align 8
+  call void @llvm.memset.p0.i64(ptr %1, i8 86, i64 56, i1 false)
+  %4 = call ptr @bar()
+  call void @llvm.memset.p0.i64(ptr %1, i8 86, i64 56, i1 false)
+  ret i1 false
+}
+
+attributes #0 = { "probe-stack"="inline-asm" "target-features"="+v" }
path: llvm/test/CodeGen/RISCV/pr135206.ll
user: login: ilovepi
body: Done.
created_at: 2025-04-11T19:28:29Z
author_association: CONTRIBUTOR

PR comments:
user: login: ilovepi
created_at: 2025-04-10T20:12:57Z
body: * **#135248** <a href="https://app.graphite.dev/github/pr/llvm/llvm-project/135248?utm_source=stack-comment-icon" target="_blank"><img src="https://static.graphite.dev/graphite-32x32-black.png" alt="Graphite" width="10px" height="10px"/></a> 👈 <a href="https://app.graphite.dev/github/pr/llvm/llvm-project/135248?utm_source=stack-comment-view-in-graphite" target="_blank">(View in Graphite)</a>
* `main`


<h2></h2>

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<!-- Current dependencies on/for this PR: -->
author_association: CONTRIBUTOR
user: login: llvmbot
created_at: 2025-04-10T20:16:43Z
body: 
<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Paul Kirth (ilovepi)

<details>
<summary>Changes</summary>

We can't assume MBBI is still pointing at MBB if we've already expanded
a probe. We need to re-query the MBB from MBBI. Fixes #<!-- -->135206

Co-authored-by: Craig Topper &lt;craig.topper@<!-- -->sifive.com&gt;

---
Full diff: https://github.com/llvm/llvm-project/pull/135248.diff


2 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVFrameLowering.cpp (+5-3) 
- (added) llvm/test/CodeGen/RISCV/pr135206.ll (+118) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index c7b2b781422d1..a83119957d95e 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -2270,11 +2270,13 @@ TargetStackID::Value RISCVFrameLowering::getStackIDForScalableVectors() const {
 }
 
 // Synthesize the probe loop.
-static void emitStackProbeInline(MachineFunction &MF, MachineBasicBlock &MBB,
-                                 MachineBasicBlock::iterator MBBI, DebugLoc DL,
+static void emitStackProbeInline(MachineBasicBlock::iterator MBBI, DebugLoc DL,
                                  Register TargetReg, bool IsRVV) {
   assert(TargetReg != RISCV::X2 && "New top of stack cannot already be in SP");
 
+  MachineBasicBlock &MBB = *MBBI->getParent();
+  MachineFunction &MF = *MBB.getParent();
+
   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
   const RISCVInstrInfo *TII = Subtarget.getInstrInfo();
   bool IsRV64 = Subtarget.is64Bit();
@@ -2363,7 +2365,7 @@ void RISCVFrameLowering::inlineStackProbe(MachineFunction &MF,
       MachineBasicBlock::iterator MBBI = MI->getIterator();
       DebugLoc DL = MBB.findDebugLoc(MBBI);
       Register TargetReg = MI->getOperand(1).getReg();
-      emitStackProbeInline(MF, MBB, MBBI, DL, TargetReg,
+      emitStackProbeInline(MBBI, DL, TargetReg,
                            (MI->getOpcode() == RISCV::PROBED_STACKALLOC_RVV));
       MBBI->eraseFromParent();
     }
diff --git a/llvm/test/CodeGen/RISCV/pr135206.ll b/llvm/test/CodeGen/RISCV/pr135206.ll
new file mode 100644
index 0000000000000..c7988cbc685fa
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr135206.ll
@@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+
+; RUN: llc < %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-fuchsia"
+
+%"struct.fuchsia_sysmem::wire::BufferCollectionConstraints" = type { %"struct.fuchsia_sysmem::wire::BufferUsage", i32, i32, i32, i32, i32, i8, %"struct.fuchsia_sysmem::wire::BufferMemoryConstraints", i32, [4 x i8], %"struct.fidl::Array.94" }
+%"struct.fuchsia_sysmem::wire::BufferUsage" = type { i32, i32, i32, i32, i32 }
+%"struct.fuchsia_sysmem::wire::BufferMemoryConstraints" = type { i32, i32, i8, i8, i8, i8, i8, i32, %"struct.fidl::Array" }
+%"struct.fidl::Array" = type { [32 x i64] }
+%"struct.fidl::Array.94" = type { [32 x %"struct.fuchsia_sysmem::wire::ImageFormatConstraints"] }
+%"struct.fuchsia_sysmem::wire::ImageFormatConstraints" = type <{ %"struct.fuchsia_sysmem::wire::PixelFormat", i32, %"struct.fidl::Array.95", i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i8] }>
+%"struct.fuchsia_sysmem::wire::PixelFormat" = type { i32, i8, %"struct.fuchsia_sysmem::wire::FormatModifier" }
+%"struct.fuchsia_sysmem::wire::FormatModifier" = type { i64 }
+%"struct.fidl::Array.95" = type { [32 x %"struct.fuchsia_sysmem::wire::ColorSpace"] }
+%"struct.fuchsia_sysmem::wire::ColorSpace" = type { i32 }
+
+; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
+declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #0
+
+define fastcc i1 @_ZN12_GLOBAL__N_121AttachTokenSucceedsV1EbbN3fit13function_implILm16ELb0EFvRN14fuchsia_sysmem4wire27BufferCollectionConstraintsEENSt3__29allocatorISt4byteEEEESB_SB_NS1_ILm16ELb0EFvRNS3_21BufferCollectionInfo2EESA_EEj() #1 {
+; CHECK-LABEL: _ZN12_GLOBAL__N_121AttachTokenSucceedsV1EbbN3fit13function_implILm16ELb0EFvRN14fuchsia_sysmem4wire27BufferCollectionConstraintsEENSt3__29allocatorISt4byteEEEESB_SB_NS1_ILm16ELb0EFvRNS3_21BufferCollectionInfo2EESA_EEj:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s1, 2008(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s2, 2000(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s3, 1992(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -8
+; CHECK-NEXT:    .cfi_offset s0, -16
+; CHECK-NEXT:    .cfi_offset s1, -24
+; CHECK-NEXT:    .cfi_offset s2, -32
+; CHECK-NEXT:    .cfi_offset s3, -40
+; CHECK-NEXT:    lui a0, 5
+; CHECK-NEXT:    sub t1, sp, a0
+; CHECK-NEXT:    .cfi_def_cfa t1, 20480
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    bne sp, t1, .LBB0_1
+; CHECK-NEXT:  # %bb.2:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    addi sp, sp, -848
+; CHECK-NEXT:    .cfi_def_cfa_offset 21328
+; CHECK-NEXT:    csrr t1, vlenb
+; CHECK-NEXT:    .cfi_def_cfa t1, -8
+; CHECK-NEXT:    lui t2, 1
+; CHECK-NEXT:  .LBB0_3: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sub sp, sp, t2
+; CHECK-NEXT:    sd zero, 0(sp)
+; CHECK-NEXT:    sub t1, t1, t2
+; CHECK-NEXT:    bge t1, t2, .LBB0_3
+; CHECK-NEXT:  # %bb.4:
+; CHECK-NEXT:    .cfi_def_cfa_register sp
+; CHECK-NEXT:    sub sp, sp, t1
+; CHECK-NEXT:    .cfi_escape 0x0f, 0x0f, 0x72, 0x00, 0x11, 0xc0, 0xb6, 0x01, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 23360 + 1 * vlenb
+; CHECK-NEXT:    li s0, 0
+; CHECK-NEXT:    li a0, 170
+; CHECK-NEXT:    li s1, 32
+; CHECK-NEXT:    lui a1, %hi(.LCPI0_0)
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    lui a0, 6
+; CHECK-NEXT:    addiw a0, a0, -1264
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT:    ld s2, %lo(.LCPI0_0)(a1)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    li s3, 16
+; CHECK-NEXT:    vse8.v v8, (s3)
+; CHECK-NEXT:    vse8.v v8, (zero)
+; CHECK-NEXT:    sd s2, 48(zero)
+; CHECK-NEXT:    jalr s0
+; CHECK-NEXT:    lui a0, 6
+; CHECK-NEXT:    addiw a0, a0, -1264
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vse8.v v8, (zero)
+; CHECK-NEXT:    vse8.v v8, (s3)
+; CHECK-NEXT:    vse8.v v8, (s1)
+; CHECK-NEXT:    sd s2, 48(zero)
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    csrr a1, vlenb
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa sp, 2032
+; CHECK-NEXT:    lui a1, 5
+; CHECK-NEXT:    addiw a1, a1, 848
+; CHECK-NEXT:    add sp, sp, a1
+; CHECK-NEXT:    .cfi_def_cfa_offset 2032
+; CHECK-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s1, 2008(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s2, 2000(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s3, 1992(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    .cfi_restore ra
+; CHECK-NEXT:    .cfi_restore s0
+; CHECK-NEXT:    .cfi_restore s1
+; CHECK-NEXT:    .cfi_restore s2
+; CHECK-NEXT:    .cfi_restore s3
+; CHECK-NEXT:    addi sp, sp, 2032
+; CHECK-NEXT:    .cfi_def_cfa_offset 0
+; CHECK-NEXT:    ret
+  %1 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  %2 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  %3 = alloca %"struct.fuchsia_sysmem::wire::BufferCollectionConstraints", align 8
+  call void @llvm.memset.p0.i64(ptr null, i8 -86, i64 56, i1 false)
+  %4 = call ptr null()
+  call void @llvm.memset.p0.i64(ptr null, i8 -86, i64 56, i1 false)
+  ret i1 false
+}
+
+attributes #0 = { nocallback nofree nounwind willreturn memory(argmem: write) }
+attributes #1 = { "probe-stack"="inline-asm" "target-features"="+v" }

``````````

</details>

author_association: MEMBER
user: login: ilovepi
created_at: 2025-04-10T20:18:11Z
body: @topperc this is basically your proposed patch w/ a reduced test case. 
.
author_association: CONTRIBUTOR
user: login: ilovepi
created_at: 2025-04-11T16:11:13Z
body: @jrtc27 I think I've addressed your comments. Anything else I should change in the test?
author_association: CONTRIBUTOR
user: login: ilovepi
created_at: 2025-04-16T20:45:53Z
body: I plan to merge this tomorrow if there isn't any more feedback.
author_association: CONTRIBUTOR
user: login: ilovepi
created_at: 2025-04-18T16:10:59Z
body: ### Merge activity

* **Apr 18, 12:10 PM EDT**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/135248).
* **Apr 18, 12:12 PM EDT**: A user merged this pull request with [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/135248).

author_association: CONTRIBUTOR