Repository: llvm/llvm-project
Pull request #123193: [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2
Author: login: liliumShade
Labels: name: clang
description: Clang issues not falling into any other category
name: backend:RISC-V
name: clang:driver
description: 'clang' and 'clang++' user-facing binaries. Not 'clang-cl'
Created: 2025-01-16T12:32:18Z | Merged: 2025-04-21T02:06:44Z

XiangShan-KunMingHu is the third generation of Open-source high-performance RISC-V processor developed by Beijing Institute of Open Source Chip (BOSC) , and its latest version is V2R2.

The KunMingHu manual is now available at https://github.com/OpenXiangShan/XiangShan-User-Guide/releases.
It will be updated on the official XiangShan documentation site: https://docs.xiangshan.cc/zh-cn/latest

You can find the corresponding ISA extension from the XiangShan Github repository: https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/Parameters.scala

If you want to track the latest performance data of KunMingHu, please check XiangShan Biweekly: https://docs.xiangshan.cc/zh-cn/latest/blog

This PR adds the processor definition for KunMingHu V2R2, developed by the XSCC team https://github.com/orgs/OpenXiangShan/teams/xscc.

The scheduling model for XiangShan-KunMingHu V2R2 will be submitted in a subsequent PR.


Diff:
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index e97b6940662d9..c2314efd34aa6 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,78 @@
 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
 // MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-kunminghu | FileCheck -check-prefix=MCPU-XIANGSHAN-KUNMINGHU %s
+// MCPU-XIANGSHAN-KUNMINGHU: "-nostdsysteminc" "-target-cpu" "xiangshan-kunminghu"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+m"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+a"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+f"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+d"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+c"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+b"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+v"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+h"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zic64b" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbom" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbop" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicboz" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccamoa" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccif" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicclsm" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccrse" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicntr" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicond" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicsr" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zihintntl" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zacas" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zawrs" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zfa" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zfh" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zca" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zcb" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zcmop" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zba" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbb" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbc"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkb" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkc" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkx" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbs"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zkn" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zks" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvbb" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64d" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64f" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64x" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvfh"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvkb"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvkt"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvl128b"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sha"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shcounterenw"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shgatpa"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shtvala"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shvsatpa"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shvstvala"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shvstvecd"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smcsrind"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smdbltrp"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smmpm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smnpm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smrnmi"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smstateen"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sscofpmf"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sscsrind"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssdbltrp"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssnpm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sspm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssstateen"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssstrict"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sstc"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssu64xl"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+supm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+svnapot"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-abi" "lp64d"
+
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-x60 | FileCheck -check-prefix=MCPU-SPACEMIT-X60 %s
 // MCPU-SPACEMIT-X60: "-nostdsysteminc" "-target-cpu" "spacemit-x60"
 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+m"
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index 6e4323958957a..199916f70c14f 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -45,6 +45,7 @@
 // RISCV64-SAME: {{^}}, syntacore-scr7
 // RISCV64-SAME: {{^}}, tt-ascalon-d8
 // RISCV64-SAME: {{^}}, veyron-v1
+// RISCV64-SAME: {{^}}, xiangshan-kunminghu
 // RISCV64-SAME: {{^}}, xiangshan-nanhu
 // RISCV64-SAME: {{$}}
 
@@ -95,6 +96,7 @@
 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr7
 // TUNE-RISCV64-SAME: {{^}}, tt-ascalon-d8
 // TUNE-RISCV64-SAME: {{^}}, veyron-v1
+// TUNE-RISCV64-SAME: {{^}}, xiangshan-kunminghu
 // TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
 // TUNE-RISCV64-SAME: {{^}}, generic
 // TUNE-RISCV64-SAME: {{^}}, generic-ooo
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 48c4663d63410..cc4fd38944ff6 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -167,6 +167,7 @@ Changes to the RISC-V Backend
 * Adds assembler support for ``.option exact``, which disables automatic compression,
   and branch and linker relaxation. This can be disabled with ``.option noexact``,
   which is also the default.
+* `-mcpu=xiangshan-kunminghu` was added.
 
 Changes to the WebAssembly Backend
 ----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index ece12c48b1cd9..4b288a9cfcb49 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -558,6 +558,33 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
 
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+                                              NoSchedModel,
+                                              !listconcat(RVA23S64Features,
+                                              [FeatureStdExtZacas,
+                                               FeatureStdExtZbc,
+                                               FeatureStdExtZfh,
+                                               FeatureStdExtZkn,
+                                               FeatureStdExtZks,
+                                               FeatureStdExtZvfh,
+                                               FeatureStdExtSmaia,
+                                               FeatureStdExtSmcsrind,
+                                               FeatureStdExtSmdbltrp,
+                                               FeatureStdExtSmmpm,
+                                               FeatureStdExtSmnpm,
+                                               FeatureStdExtSmrnmi,
+                                               FeatureStdExtSmstateen,
+                                               FeatureStdExtSsaia,
+                                               FeatureStdExtSscsrind,
+                                               FeatureStdExtSsdbltrp,
+                                               FeatureStdExtSspm,
+                                               FeatureStdExtSsstrict,
+                                               FeatureStdExtZvl128b]),
+                                              [TuneNoDefaultUnroll,
+                                               TuneZExtHFusion,
+                                               TuneZExtWFusion,
+                                               TuneShiftedZExtWFusion]>;
+
 def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
                                        NoSchedModel,
                                        !listconcat(RVA22S64Features,


Reviews:
user: login: wangpc-pp
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-01-16T15:13:01Z
user: login: tangshenglin
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-01-17T03:54:30Z
user: login: wangpc-pp
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-01-17T08:35:10Z
user: login: tclin914
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-04-16T05:18:29Z
user: login: liliumShade
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-04-16T07:36:36Z
user: login: Tang-Haojin
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-04-17T02:25:26Z
user: login: wangpc-pp
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-04-17T07:31:24Z
user: login: liliumShade
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-04-17T08:59:06Z
user: login: wangpc-pp
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-04-17T12:43:05Z
user: login: wangpc-pp
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-04-17T12:48:46Z
user: login: wangpc-pp
body: LGTM! Thanks for the insistence!
state: APPROVED
author_association: CONTRIBUTOR
submitted_at: 2025-04-18T10:31:22Z
user: login: mshockwave
state: APPROVED
author_association: MEMBER
submitted_at: 2025-04-18T16:25:28Z

Review comments:
diff_hunk: @@ -553,6 +553,37 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
 
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+                                          NoSchedModel,
+                                          !listconcat(!listremove(RVA23S64Features,
+                                                      [FeatureStdExtZiccamoa,
path: llvm/lib/Target/RISCV/RISCVProcessors.td
user: login: wangpc-pp
body: Any plan to make KMH RVA23-compatible?
created_at: 2025-01-16T15:12:54Z
author_association: CONTRIBUTOR
diff_hunk: @@ -553,6 +553,37 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
 
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+                                          NoSchedModel,
+                                          !listconcat(!listremove(RVA23S64Features,
+                                                      [FeatureStdExtZiccamoa,
path: llvm/lib/Target/RISCV/RISCVProcessors.td
user: login: tangshenglin
body: V2R2 is a validated and stable release. Full support for RVA23 is also in the pipeline, with updates expected to be completed by 2025. The timeline will be dynamically adjusted based on progress. Once finalized, the XSCC team will synchronize updates accordingly.
created_at: 2025-01-17T03:54:30Z
author_association: CONTRIBUTOR
diff_hunk: @@ -553,6 +553,37 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
 
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+                                          NoSchedModel,
+                                          !listconcat(!listremove(RVA23S64Features,
+                                                      [FeatureStdExtZiccamoa,
path: llvm/lib/Target/RISCV/RISCVProcessors.td
user: login: wangpc-pp
body: Then I think we should wait for the freeze of features. I don't think we will accept an intermediate version.
created_at: 2025-01-17T08:35:10Z
author_association: CONTRIBUTOR
diff_hunk: @@ -558,6 +558,34 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
 
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+                                          NoSchedModel,
path: llvm/lib/Target/RISCV/RISCVProcessors.td
user: login: tclin914
body: indentation alignment
created_at: 2025-04-16T05:18:28Z
author_association: CONTRIBUTOR
diff_hunk: @@ -558,6 +558,34 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
 
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+                                          NoSchedModel,
path: llvm/lib/Target/RISCV/RISCVProcessors.td
user: login: liliumShade
body: Done! 
created_at: 2025-04-16T07:36:35Z
author_association: CONTRIBUTOR
diff_hunk: @@ -553,6 +553,37 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
 
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+                                          NoSchedModel,
+                                          !listconcat(!listremove(RVA23S64Features,
+                                                      [FeatureStdExtZiccamoa,
path: llvm/lib/Target/RISCV/RISCVProcessors.td
user: login: Tang-Haojin
body: > Then I think we should wait for the freeze of features. I don't think we will accept an intermediate version.

Hi @wangpc-pp, the KunMingHu-V2R2 version of the ISA strings has been frozen, and support for the "ziccamoa", "zihintntl", and "zawrs" extensions has also been updated. Please check https://github.com/OpenXiangShan/XiangShan/pull/4219 (This PR has only updated the isa string, and the support of these three extensions had been done before this PR).
created_at: 2025-04-17T02:25:26Z
author_association: CONTRIBUTOR
diff_hunk: @@ -126,6 +126,7 @@ Changes to the PowerPC Backend
 Changes to the RISC-V Backend
 -----------------------------
 
+
path: llvm/docs/ReleaseNotes.md
user: login: wangpc-pp
body: Remove this extra blank line.
created_at: 2025-04-17T07:28:24Z
author_association: CONTRIBUTOR
diff_hunk: @@ -558,6 +558,34 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
 
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+                                              NoSchedModel,
+                                              !listconcat(RVA23S64Features,
+                                              [FeatureStdExtZicsr,
path: llvm/lib/Target/RISCV/RISCVProcessors.td
user: login: wangpc-pp
body: Zicsr is in `RVA23S64Features` already.
created_at: 2025-04-17T07:29:56Z
author_association: CONTRIBUTOR
diff_hunk: @@ -558,6 +558,34 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
 
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+                                              NoSchedModel,
+                                              !listconcat(RVA23S64Features,
+                                              [FeatureStdExtZicsr,
path: llvm/lib/Target/RISCV/RISCVProcessors.td
user: login: liliumShade
body: You are right, but I didn't find FeatureStdExtZicsr in RISCVProfiles.td. So, just to confirm, there won't be any problem if it is removed, right? 😮
created_at: 2025-04-17T08:59:06Z
author_association: CONTRIBUTOR
diff_hunk: @@ -558,6 +558,34 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
 
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+                                              NoSchedModel,
+                                              !listconcat(RVA23S64Features,
+                                              [FeatureStdExtZicsr,
path: llvm/lib/Target/RISCV/RISCVProcessors.td
user: login: wangpc-pp
body: Yes you can remove it because the F/D extensions imply `Zicsr`. I can add it explicitly to the RISCVProfiles.td to avoid future misleadings.
created_at: 2025-04-17T12:43:04Z
author_association: CONTRIBUTOR
diff_hunk: @@ -558,6 +558,34 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
 
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+                                              NoSchedModel,
+                                              !listconcat(RVA23S64Features,
+                                              [FeatureStdExtZicsr,
path: llvm/lib/Target/RISCV/RISCVProcessors.td
user: login: wangpc-pp
body: https://github.com/llvm/llvm-project/pull/136134
created_at: 2025-04-17T12:48:46Z
author_association: CONTRIBUTOR

PR comments:
user: login: github-actions[bot]
created_at: 2025-01-16T12:32:36Z
body: <!--LLVM NEW CONTRIBUTOR COMMENT-->

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author_association: NONE
user: login: llvmbot
created_at: 2025-01-16T12:33:08Z
body: 
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clang
@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-clang-driver

Author: Chyaka (liliumShade)

<details>
<summary>Changes</summary>

XiangShan-KunMingHu is the third generation of Open-source high-performance RISC-V processor developed by Beijing Institute of Open Source Chip (BOSC) , and its latest version is V2R2.

The KunMingHu manual is now available at https://github.com/OpenXiangShan/XiangShan-User-Guide/releases.
It will be updated on the official XiangShan documentation site: https://docs.xiangshan.cc/zh-cn/latest

You can find the corresponding ISA extension from the XiangShan Github repository: https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/Parameters.scala

If you want to track the latest performance data of KunMingHu, please check XiangShan Biweekly: https://docs.xiangshan.cc/zh-cn/latest/blog

This PR adds the processor definition for KunMingHu V2R2, developed by the XSCC team https://github.com/orgs/OpenXiangShan/teams/xscc.

The scheduling model for XiangShan-KunMingHu V2R2 will be submitted in a subsequent PR.

---
Full diff: https://github.com/llvm/llvm-project/pull/123193.diff


4 Files Affected:

- (modified) clang/test/Driver/riscv-cpus.c (+47) 
- (modified) clang/test/Misc/target-invalid-cpu-note/riscv.c (+2) 
- (modified) llvm/docs/ReleaseNotes.md (+1) 
- (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+31) 


``````````diff
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index e97b6940662d9f..b9b27eec61c6f3 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,53 @@
 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
 // MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-kunminghu | FileCheck -check-prefix=MCPU-XIANGSHAN-KUNMINGHU %s
+// MCPU-XIANGSHAN-KUNMINGHU: "-nostdsysteminc" "-target-cpu" "xiangshan-kunminghu"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+m"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+a"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+f"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+d"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+c"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+b"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+v"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zic64b" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbom" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbop" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicboz" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccif" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicclsm" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccrse" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicntr" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicond" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicsr" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zacas" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zfh" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zba" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbb" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbc"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkb" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkc" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkx" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbs"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zkn" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zks" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvfh"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvl128b"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smcsrind"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smdbltrp"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smmpm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smnpm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smrnmi"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smstateen"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sscsrind"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssdbltrp"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sspm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssstrict"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "-zawrs" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "-ziccamoa" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "-zihintntl" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-abi" "lp64d"
+
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-x60 | FileCheck -check-prefix=MCPU-SPACEMIT-X60 %s
 // MCPU-SPACEMIT-X60: "-nostdsysteminc" "-target-cpu" "spacemit-x60"
 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+m"
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index fb54dcb5b3a93a..e9ed7ff4764775 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -45,6 +45,7 @@
 // RISCV64-SAME: {{^}}, syntacore-scr7
 // RISCV64-SAME: {{^}}, tt-ascalon-d8
 // RISCV64-SAME: {{^}}, veyron-v1
+// RISCV64-SAME: {{^}}, xiangshan-kunminghu
 // RISCV64-SAME: {{^}}, xiangshan-nanhu
 // RISCV64-SAME: {{$}}
 
@@ -94,6 +95,7 @@
 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr7
 // TUNE-RISCV64-SAME: {{^}}, tt-ascalon-d8
 // TUNE-RISCV64-SAME: {{^}}, veyron-v1
+// TUNE-RISCV64-SAME: {{^}}, xiangshan-kunminghu
 // TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
 // TUNE-RISCV64-SAME: {{^}}, generic
 // TUNE-RISCV64-SAME: {{^}}, rocket
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 8f88b824f965aa..4a191bfbe594c7 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -199,6 +199,7 @@ Changes to the RISC-V Backend
 * `-mcpu=tt-ascalon-d8` was added.
 * `-mcpu=mips-p8700` was added.
 * `-mcpu=sifive-p550` was added.
+* `-mcpu=xiangshan-kunminghu` was added.
 * The `Zacas` extension is no longer marked as experimental.
 * Added Smdbltrp, Ssdbltrp extensions to -march.
 * The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6dfed7ddeb9f63..2a434f30722804 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -553,6 +553,37 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
 
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+                                          NoSchedModel,
+                                          !listconcat(!listremove(RVA23S64Features,
+                                                      [FeatureStdExtZiccamoa,
+                                                      FeatureStdExtZihintntl,
+                                                      FeatureStdExtZawrs]),
+                                            [FeatureStdExtZicsr,
+                                            FeatureStdExtZacas,
+                                            FeatureStdExtZbc,
+                                            FeatureStdExtZfh,
+                                            FeatureStdExtZkn,
+                                            FeatureStdExtZks,
+                                            FeatureStdExtZvfh,
+                                            FeatureStdExtSmaia,
+                                            FeatureStdExtSmcsrind,
+                                            FeatureStdExtSmdbltrp,
+                                            FeatureStdExtSmmpm,
+                                            FeatureStdExtSmnpm,
+                                            FeatureStdExtSmrnmi,
+                                            FeatureStdExtSmstateen,
+                                            FeatureStdExtSsaia,
+                                            FeatureStdExtSscsrind,
+                                            FeatureStdExtSsdbltrp,
+                                            FeatureStdExtSspm,
+                                            FeatureStdExtSsstrict,
+                                            FeatureStdExtZvl128b]),
+                                           [TuneNoDefaultUnroll,
+                                            TuneZExtHFusion,
+                                            TuneZExtWFusion,
+                                            TuneShiftedZExtWFusion]>;
+
 def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
                                        NoSchedModel,
                                        !listconcat(RVA22S64Features,

``````````

</details>

author_association: MEMBER
user: login: cyyself
created_at: 2025-04-08T08:19:34Z
body: I think some feature is missing in `clang/test/Driver/riscv-cpus.c`, such as "Zvbb".
author_association: CONTRIBUTOR
user: login: liliumShade
created_at: 2025-04-16T04:36:56Z
body: > I think some feature is missing in `clang/test/Driver/riscv-cpus.c`, such as "Zvbb".

 Thanks for the review! We've added the Zvbb test case and extended validation for XIANGSHAN-KUNMINGHU CPU's target features (including privileged/custom extensions)
author_association: CONTRIBUTOR
user: login: wangpc-pp
created_at: 2025-04-18T03:13:03Z
body: LGTM in general, but I have a question here: can you clarify the naming strategy? The name used in `-mcpu` is `xiangshan-kunminghu`, which corresponds to the `V2R2` version now apparently. Then, will there be `V2R3`/`V3R2`/...? If so, what should we use in `-mcpu`?
author_association: CONTRIBUTOR
user: login: liliumShade
created_at: 2025-04-18T10:04:53Z
body: > LGTM in general, but I have a question here: can you clarify the naming strategy? The name used in `-mcpu` is `xiangshan-kunminghu`, which corresponds to the `V2R2` version now apparently. Then, will there be `V2R3`/`V3R2`/...? If so, what should we use in `-mcpu`?
  
Thank you for raising this! To clarify: V2R2 is the current frozen version of kunminghu, the subsequent development in the plan will not affect the ISA string and pipeline.

If significant changes ever arise in a future major version (e.g., a hypothetical V3), we will introduce a new -mcpu name to reflect that divergence. 
author_association: CONTRIBUTOR
user: login: github-actions[bot]
created_at: 2025-04-21T02:07:06Z
body: <!--LLVM BUILDBOT INFORMATION COMMENT-->

@liliumShade Congratulations on having your first Pull Request (PR) merged into the LLVM Project!

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author_association: NONE