Repository: Xilinx/llvm-aie
Pull request #376: [AIE2P] Regbankselect Fixup! 
Author: login: abnikant
Created: 2025-02-28T14:51:39Z | Merged: 2025-03-04T10:23:07Z

1) Fix the compilation error when using -regbankselect-greedy, also fixup the opsize for vetor in store and G_CONCAT_VECTORS.
2) Support missing G_UNMERGE_VALUES in AlternativeMappings. 


Diff:
diff --git a/llvm/lib/Target/AIE/AIEBaseRegisterBankInfo.cpp b/llvm/lib/Target/AIE/AIEBaseRegisterBankInfo.cpp
index aed26a0bceb4..b24123c116a0 100644
--- a/llvm/lib/Target/AIE/AIEBaseRegisterBankInfo.cpp
+++ b/llvm/lib/Target/AIE/AIEBaseRegisterBankInfo.cpp
@@ -298,6 +298,8 @@ AIEBaseRegisterBankInfo::getAccPartialMappingIdx(const LLT &Ty) const {
 AIEBaseRegisterBankInfo::PartialMappingIdx
 AIEBaseRegisterBankInfo::getVecPartialMappingIdx(const LLT &Ty) const {
   switch (Ty.getSizeInBits()) {
+  case 128:
+    return PMI_VREG128;
   case 256:
     return PMI_VREG256;
   case 512:
diff --git a/llvm/lib/Target/AIE/aie2p/AIE2PRegisterBankInfo.cpp b/llvm/lib/Target/AIE/aie2p/AIE2PRegisterBankInfo.cpp
index 5cbe61278f8b..9c793c32e430 100644
--- a/llvm/lib/Target/AIE/aie2p/AIE2PRegisterBankInfo.cpp
+++ b/llvm/lib/Target/AIE/aie2p/AIE2PRegisterBankInfo.cpp
@@ -283,10 +283,7 @@ AIE2PRegisterBankInfo::getInstrAlternativeMappings(
     // Set all operand sizes to 20 by default.
     SmallVector<PartialMappingIdx, 4> OpRegBankIdx(NumOperands, PMI_MOD);
     SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
-    SmallVector<unsigned, 4> OpSize(NumOperands, 20);
 
-    // Operand[0]- vector operand.
-    OpSize[0] = DstSize;
     for (unsigned I = 1; I < FirstSrcIdx; ++I)
       OpRegBankIdx[I] = (I == 1) ? PMI_PTR : PMI_MOD;
 
@@ -304,7 +301,8 @@ AIE2PRegisterBankInfo::getInstrAlternativeMappings(
           LLT Ty = MRI.getType(MI.getOperand(Idx).getReg());
           if (!Ty.isValid())
             continue;
-          OpdsMapping[Idx] = getValueMapping(OpRegBankIdx[Idx], OpSize[Idx]);
+          OpdsMapping[Idx] =
+              getValueMapping(OpRegBankIdx[Idx], (Idx == 0) ? DstSize : 20);
         }
       }
       const InstructionMapping &InsnMapping = getInstructionMapping(
@@ -345,7 +343,6 @@ AIE2PRegisterBankInfo::getInstrAlternativeMappings(
     // Set all operand sizes to 20 by default.
     SmallVector<PartialMappingIdx, 4> OpRegBankIdx(NumOperands, PMI_MOD);
     SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
-    SmallVector<unsigned, 4> OpSize(NumOperands, 20);
 
     // Initialize first few indices based on VRegOpIdx
     for (unsigned I = 0; I < VecRegOpIdx; ++I) {
@@ -365,7 +362,8 @@ AIE2PRegisterBankInfo::getInstrAlternativeMappings(
           LLT Ty = MRI.getType(MI.getOperand(Idx).getReg());
           if (!Ty.isValid())
             continue;
-          OpdsMapping[Idx] = getValueMapping(OpRegBankIdx[Idx], OpSize[Idx]);
+          OpdsMapping[Idx] = getValueMapping(
+              OpRegBankIdx[Idx], (Idx == VecRegOpIdx) ? VecRegSize : 20);
         }
       }
       const InstructionMapping &InsnMapping = getInstructionMapping(
@@ -374,10 +372,61 @@ AIE2PRegisterBankInfo::getInstrAlternativeMappings(
     }
     return AltMappings;
   }
+  case TargetOpcode::G_UNMERGE_VALUES: {
+    const unsigned NumOperands = MI.getNumOperands();
+    assert(NumOperands == 3 &&
+           "Unsupported number of operands for G_UNMERGE_VALUES\n");
+    const Register SrcReg = MI.getOperand(NumOperands - 1).getReg();
+    const LLT SrcTy = MRI.getType(SrcReg);
+    unsigned SrcSize = getSizeInBits(SrcReg, MRI, TRI);
+    // Only the accumulator is of 2048-bit size, with the possible mapping
+    // restricted to accumulator register banks. For a 512-bit vector,
+    // the only possible mapping is to a vector register bank.
+    if (SrcSize <= 512 || SrcSize == 2048)
+      break;
+    const LLT HalfSrcTy = SrcTy.divide(2);
+    const unsigned HalfSrcTySize = HalfSrcTy.getSizeInBits();
+    InstructionMappings AltMappings;
+    const InstructionMapping &VRegMapping = getInstructionMapping(
+        /*ID*/ 1, /*Cost*/ 1,
+        getOperandsMapping(
+            {getValueMapping(getVecPartialMappingIdx(HalfSrcTy), HalfSrcTySize),
+             getValueMapping(getVecPartialMappingIdx(HalfSrcTy), HalfSrcTySize),
+             getValueMapping(getVecPartialMappingIdx(SrcTy), SrcSize)}),
+        /*NumOperands*/ 3);
+    const InstructionMapping &AccRegMapping = getInstructionMapping(
+        /*ID*/ 2, /*Cost*/ 1,
+        getOperandsMapping(
+            {getValueMapping(getAccPartialMappingIdx(HalfSrcTy), HalfSrcTySize),
+             getValueMapping(getAccPartialMappingIdx(HalfSrcTy), HalfSrcTySize),
+             getValueMapping(getAccPartialMappingIdx(SrcTy), SrcSize)}),
+        /*NumOperands*/ 3);
+    const InstructionMapping &FifoRegMapping = getInstructionMapping(
+        /*ID*/ 3, /*Cost*/ 1,
+        getOperandsMapping(
+            {getValueMapping(getFifoPartialMappingIdx(HalfSrcTy),
+                             HalfSrcTySize),
+             getValueMapping(getFifoPartialMappingIdx(HalfSrcTy),
+                             HalfSrcTySize),
+             getValueMapping(getFifoPartialMappingIdx(SrcTy), SrcSize)}),
+        /*NumOperands*/ 3);
+
+    AltMappings.push_back(&VRegMapping);
+    AltMappings.push_back(&AccRegMapping);
+    AltMappings.push_back(&FifoRegMapping);
+    return AltMappings;
+  }
   case TargetOpcode::G_CONCAT_VECTORS: {
     Register DstReg = MI.getOperand(0).getReg();
-    const LLT Ty = MRI.getType(DstReg);
-    unsigned Size = getSizeInBits(DstReg, MRI, TRI);
+    const LLT DstTy = MRI.getType(DstReg);
+    const LLT HalfDstTy = DstTy.divide(2);
+    unsigned DstSize = getSizeInBits(DstReg, MRI, TRI);
+    const unsigned HalfDstTySize = HalfDstTy.getSizeInBits();
+    // Only the accumulator is of 2048-bit size, with the possible mapping
+    // restricted to accumulator register banks. For a 512-bit vector,
+    // the only possible mapping is to a vector register bank.
+    if (DstSize <= 512 || DstSize == 2048)
+      break;
 
     // If the instruction has any implicit-defs or uses,
     // do not mess with it.
@@ -386,20 +435,33 @@ AIE2PRegisterBankInfo::getInstrAlternativeMappings(
     InstructionMappings AltMappings;
     const InstructionMapping &VRegMapping = getInstructionMapping(
         /*ID*/ 1, /*Cost*/ 1,
-        getOperandsMapping({getValueMapping(getPartialMappingIdx(Ty), Size),
-                            getValueMapping(getPartialMappingIdx(Ty), Size),
-                            getValueMapping(getPartialMappingIdx(Ty), Size)}),
+        getOperandsMapping(
+            {getValueMapping(getVecPartialMappingIdx(DstTy), DstSize),
+             getValueMapping(getVecPartialMappingIdx(HalfDstTy), HalfDstTySize),
+             getValueMapping(getVecPartialMappingIdx(HalfDstTy),
+                             HalfDstTySize)}),
         /*NumOperands*/ 3);
     const InstructionMapping &AccRegMapping = getInstructionMapping(
         /*ID*/ 2, /*Cost*/ 1,
         getOperandsMapping(
-            {getValueMapping(getAccPartialMappingIdx(Ty), Size),
-             getValueMapping(getAccPartialMappingIdx(Ty), Size),
-             getValueMapping(getAccPartialMappingIdx(Ty), Size)}),
+            {getValueMapping(getAccPartialMappingIdx(DstTy), DstSize),
+             getValueMapping(getAccPartialMappingIdx(HalfDstTy), HalfDstTySize),
+             getValueMapping(getAccPartialMappingIdx(HalfDstTy),
+                             HalfDstTySize)}),
+        /*NumOperands*/ 3);
+    const InstructionMapping &FifoRegMapping = getInstructionMapping(
+        /*ID*/ 3, /*Cost*/ 1,
+        getOperandsMapping(
+            {getValueMapping(getFifoPartialMappingIdx(DstTy), DstSize),
+             getValueMapping(getFifoPartialMappingIdx(HalfDstTy),
+                             HalfDstTySize),
+             getValueMapping(getFifoPartialMappingIdx(HalfDstTy),
+                             HalfDstTySize)}),
         /*NumOperands*/ 3);
 
     AltMappings.push_back(&VRegMapping);
     AltMappings.push_back(&AccRegMapping);
+    AltMappings.push_back(&FifoRegMapping);
     return AltMappings;
   }
   case TargetOpcode::G_BITCAST: {
@@ -408,7 +470,7 @@ AIE2PRegisterBankInfo::getInstrAlternativeMappings(
     // Only the accumulator is of 2048-bit size, with the possible mapping
     // restricted to accumulator register banks. For a 256-bit vector,
     // the only possible mapping is to a vector register bank.
-    if (Size == 256 || Size == 2048)
+    if (Size <= 256 || Size == 2048)
       break;
 
     // If the instruction has any implicit-defs or uses,
@@ -420,8 +482,10 @@ AIE2PRegisterBankInfo::getInstrAlternativeMappings(
     const InstructionMapping &VRegMapping = getInstructionMapping(
         /*ID*/ 1, /*Cost*/ 1,
         getOperandsMapping(
-            {getValueMapping(getPartialMappingIdx(MRI.getType(DstReg)), Size),
-             getValueMapping(getPartialMappingIdx(MRI.getType(DstReg)), Size)}),
+            {getValueMapping(getVecPartialMappingIdx(MRI.getType(DstReg)),
+                             Size),
+             getValueMapping(getVecPartialMappingIdx(MRI.getType(DstReg)),
+                             Size)}),
         /*NumOperands*/ 2);
     const InstructionMapping &AccRegMapping = getInstructionMapping(
         /*ID*/ 2, /*Cost*/ 1,
@@ -434,7 +498,8 @@ AIE2PRegisterBankInfo::getInstrAlternativeMappings(
     const InstructionMapping &AccToVRegMapping = getInstructionMapping(
         /*ID*/ 2, /*Cost*/ 2,
         getOperandsMapping(
-            {getValueMapping(getPartialMappingIdx(MRI.getType(DstReg)), Size),
+            {getValueMapping(getVecPartialMappingIdx(MRI.getType(DstReg)),
+                             Size),
              getValueMapping(getAccPartialMappingIdx(MRI.getType(DstReg)),
                              Size)}),
         /*NumOperands*/ 2);
@@ -443,7 +508,8 @@ AIE2PRegisterBankInfo::getInstrAlternativeMappings(
         getOperandsMapping(
             {getValueMapping(getAccPartialMappingIdx(MRI.getType(DstReg)),
                              Size),
-             getValueMapping(getPartialMappingIdx(MRI.getType(DstReg)), Size)}),
+             getValueMapping(getVecPartialMappingIdx(MRI.getType(DstReg)),
+                             Size)}),
         /*NumOperands*/ 2);
 
     AltMappings.push_back(&VRegMapping);
@@ -463,8 +529,8 @@ AIE2PRegisterBankInfo::getInstrAlternativeMappings(
     InstructionMappings AltMappings;
     const InstructionMapping &VRegMapping = getInstructionMapping(
         /*ID*/ 1, /*Cost*/ 1,
-        getOperandsMapping(
-            {getValueMapping(getPartialMappingIdx(MRI.getType(DstReg)), Size)}),
+        getOperandsMapping({getValueMapping(
+            getVecPartialMappingIdx(MRI.getType(DstReg)), Size)}),
         /*NumOperands*/ 1);
     const InstructionMapping &AccRegMapping = getInstructionMapping(
         /*ID*/ 2, /*Cost*/ 1,
@@ -971,17 +1037,19 @@ AIE2PRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     Register SrcReg = MI.getOperand(1).getReg();
     LLT DstType = MRI.getType(DstReg);
     LLT SrcType = MRI.getType(SrcReg);
+    if (SrcType.getSizeInBits() <= 64)
+      return AIEBaseRegisterBankInfo::getInstrMapping(MI);
     // Check if we already know the register bank.
     auto *RB = getRegBank(SrcReg, MRI, TRI);
     auto PreferredRegBank = getPreferredRegBankForVectorTy(MRI, TRI, DstReg);
     if (PreferredRegBank && &AIE2P::AccRegBank == *PreferredRegBank)
       OpRegBankIdx[0] = getAccPartialMappingIdx(DstType);
     else
-      OpRegBankIdx[0] = getPartialMappingIdx(DstType);
+      OpRegBankIdx[0] = getVecPartialMappingIdx(DstType);
     if (RB == &AIE2P::AccRegBank)
       OpRegBankIdx[1] = getAccPartialMappingIdx(SrcType);
     else
-      OpRegBankIdx[1] = getPartialMappingIdx(SrcType);
+      OpRegBankIdx[1] = getVecPartialMappingIdx(SrcType);
 
     return AIEBaseRegisterBankInfo::getInstrMappingFinal(MI, Cost, OpSize,
                                                          OpRegBankIdx);
diff --git a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-256bit.mir b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-256bit.mir
index 0497debf0509..0f34f779c0b1 100644
--- a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-256bit.mir
+++ b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-256bit.mir
@@ -4,9 +4,10 @@
 # See https://llvm.org/LICENSE.txt for license information.
 # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 #
-# (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
+# (c) Copyright 2025 Advanced Micro Devices, Inc. or its affiliates
 # RUN: llc -mtriple aie2p -run-pass=regbankselect -regbankselect-fast %s -verify-machineinstrs -o - | FileCheck %s
 # RUN: llc -mtriple aie2p -run-pass=regbankselect -regbankselect-greedy %s -verify-machineinstrs -o - | FileCheck %s
+
 ---
 name:            test_vector_256
 legalized:       true
@@ -26,3 +27,37 @@ body:             |
     %3:_(<8 x s32>) = G_LOAD %1(p0) :: (dereferenceable load (<8 x s32>))
     PseudoRET implicit $lr
 ...
+
+---
+name:            test_bitcast_256bits
+legalized:       true
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: test_bitcast_256bits
+    ; CHECK: [[DEF:%[0-9]+]]:vregbank(<4 x s64>) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:vregbank(<8 x s32>) = G_BITCAST [[DEF]](<4 x s64>)
+    ; CHECK-NEXT: $wl0 = COPY [[BITCAST]](<8 x s32>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $wl0
+    %1:_(<4 x s64>) = G_IMPLICIT_DEF
+    %0:_(<8 x s32>) = G_BITCAST %1(<4 x s64>)
+    $wl0 = COPY %0(<8 x s32>)
+    PseudoRET implicit $lr, implicit $wl0
+...
+
+---
+name:            test_concat_128bits
+legalized:       true
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: test_concat_128bits
+    ; CHECK: [[DEF:%[0-9]+]]:vregbank(<4 x s32>) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vregbank(<4 x s32>) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vregbank(<8 x s32>) = G_CONCAT_VECTORS [[DEF]](<4 x s32>), [[DEF1]](<4 x s32>)
+    ; CHECK-NEXT: $wl0 = COPY [[CONCAT_VECTORS]](<8 x s32>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $wl0
+    %1:_(<4 x s32>) = G_IMPLICIT_DEF
+    %2:_(<4 x s32>) = G_IMPLICIT_DEF
+    %0:_(<8 x s32>) = G_CONCAT_VECTORS %1(<4 x s32>), %2(<4 x s32>)
+    $wl0 = COPY %0(<8 x s32>)
+    PseudoRET implicit $lr, implicit $wl0
+...
diff --git a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-64bit.mir b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-64bit.mir
new file mode 100644
index 000000000000..c9650705bbf7
--- /dev/null
+++ b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-64bit.mir
@@ -0,0 +1,51 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+#
+# This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+#
+# (c) Copyright 2025 Advanced Micro Devices, Inc. or its affiliates
+# RUN: llc -mtriple aie2p -run-pass=regbankselect -regbankselect-fast %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple aie2p -run-pass=regbankselect -regbankselect-greedy %s -verify-machineinstrs -o - | FileCheck %s
+
+---
+name:            test_bitcast_2xs32_4xs16
+legalized:       true
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: test_bitcast_2xs32_4xs16
+    ; CHECK: [[DEF:%[0-9]+]]:gprregbank(<2 x s32>) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:gprregbank(<4 x s16>) = G_BITCAST [[DEF]](<2 x s32>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[BITCAST]](<4 x s16>)
+    %1:_(<2 x s32>) = G_IMPLICIT_DEF
+    %0:_(<4 x s16>) = G_BITCAST %1(<2 x s32>)
+    PseudoRET implicit $lr, implicit %0
+...
+
+---
+name:            test_bitcast_2xs32_s64
+legalized:       true
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: test_bitcast_2xs32_s64
+    ; CHECK: [[DEF:%[0-9]+]]:gprregbank(<2 x s32>) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:gprregbank(s64) = G_BITCAST [[DEF]](<2 x s32>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[BITCAST]](s64)
+    %1:_(<2 x s32>) = G_IMPLICIT_DEF
+    %0:_(s64) = G_BITCAST %1(<2 x s32>)
+    PseudoRET implicit $lr, implicit %0
+...
+
+---
+name:            test_bitcast_s64_2xs32
+legalized:       true
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: test_bitcast_s64_2xs32
+    ; CHECK: [[COPY:%[0-9]+]]:gprregbank(s64) = COPY $l0
+    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:gprregbank(<2 x s32>) = G_BITCAST [[COPY]](s64)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[BITCAST]](<2 x s32>)
+    %1:_(s64) = COPY $l0
+    %0:_(<2 x s32>) = G_BITCAST %1(s64)
+    PseudoRET implicit $lr, implicit %0
+...
diff --git a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-phi.mir b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-phi.mir
index 887a5d36d2f8..dbe012bbf59d 100644
--- a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-phi.mir
+++ b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-phi.mir
@@ -373,12 +373,12 @@ body:             |
   ; CHECK-NEXT:   [[PHI1:%[0-9]+]]:ptrregbank(p0) = G_PHI [[COPY]](p0), %bb.0, %8(p0), %bb.1
   ; CHECK-NEXT:   [[PHI2:%[0-9]+]]:gprregbank(s32) = G_PHI [[C]](s32), %bb.0, %10(s32), %bb.1
   ; CHECK-NEXT:   [[PHI3:%[0-9]+]]:fiforegbank(<16 x s64>) = G_PHI [[DEF]](<16 x s64>), %bb.0, %12(<16 x s64>), %bb.1
-  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:accregbank(<16 x s64>) = COPY [[PHI3]](<16 x s64>)
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vregbank(<16 x s64>) = COPY [[PHI3]](<16 x s64>)
   ; CHECK-NEXT:   [[BITCAST:%[0-9]+]]:vregbank(<32 x s32>) = G_BITCAST [[COPY1]](<16 x s64>)
   ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:fiforegbank(<32 x s32>) = COPY [[BITCAST]](<32 x s32>)
   ; CHECK-NEXT:   [[INT:%[0-9]+]]:ptrregbank(p0), [[INT1:%[0-9]+]]:fiforegbank(<32 x s32>), [[INT2:%[0-9]+]]:gprregbank(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aie2p.fifo.ld.fill), [[PHI1]](p0), [[COPY2]](<32 x s32>), [[PHI2]](s32)
   ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:vregbank(<32 x s32>) = COPY [[INT1]](<32 x s32>)
-  ; CHECK-NEXT:   [[BITCAST1:%[0-9]+]]:accregbank(<16 x s64>) = G_BITCAST [[COPY3]](<32 x s32>)
+  ; CHECK-NEXT:   [[BITCAST1:%[0-9]+]]:vregbank(<16 x s64>) = G_BITCAST [[COPY3]](<32 x s32>)
   ; CHECK-NEXT:   [[ADD:%[0-9]+]]:gprregbank(s32) = G_ADD [[PHI]], [[C1]]
   ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:gprregbank(s32) = G_ICMP intpred(eq), [[ADD]](s32), [[C]]
   ; CHECK-NEXT:   G_BRCOND [[ICMP]](s32), %bb.1
diff --git a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-unmerge-values.mir b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-unmerge-values.mir
index e33fcff8e85d..a9108290a9be 100644
--- a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-unmerge-values.mir
+++ b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-unmerge-values.mir
@@ -4,7 +4,7 @@
 # See https://llvm.org/LICENSE.txt for license information.
 # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 #
-# (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
+# (c) Copyright 2025 Advanced Micro Devices, Inc. or its affiliates
 # RUN: llc -mtriple aie2p -run-pass=regbankselect -regbankselect-fast %s -verify-machineinstrs -o - | FileCheck %s
 # RUN: llc -mtriple aie2p -run-pass=regbankselect -regbankselect-greedy %s -verify-machineinstrs -o - | FileCheck %s
 ---
@@ -145,3 +145,17 @@ body:             |
     %1:_(<4 x s64>), %2:_(<4 x s64>) = G_UNMERGE_VALUES %0(<8 x s64>)
     PseudoRET implicit $lr, implicit %2
 ...
+
+---
+name:            test_unmerge_v8s32
+legalized: true
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: test_unmerge_v8s32
+    ; CHECK: [[COPY:%[0-9]+]]:vregbank(<8 x s32>) = COPY $wl0
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:vregbank(<4 x s32>), [[UV1:%[0-9]+]]:vregbank(<4 x s32>) = G_UNMERGE_VALUES [[COPY]](<8 x s32>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[UV1]](<4 x s32>)
+    %0:_(<8 x s32>) = COPY $wl0
+    %1:_(<4 x s32>), %2:_(<4 x s32>) = G_UNMERGE_VALUES %0(<8 x s32>)
+    PseudoRET implicit $lr, implicit %2
+...


Reviews:
user: login: niwinanto
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-03-03T12:53:51Z
user: login: niwinanto
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-03-03T12:54:13Z
user: login: niwinanto
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-03-03T12:59:38Z
user: login: niwinanto
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-03-03T13:01:54Z
user: login: niwinanto
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-03-03T13:06:00Z
user: login: niwinanto
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-03-03T13:24:36Z
user: login: abnikant
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-03-04T05:57:52Z
user: login: abnikant
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-03-04T05:58:13Z
user: login: abnikant
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-03-04T05:59:16Z
user: login: niwinanto
body: LGTM!
state: APPROVED
author_association: COLLABORATOR
submitted_at: 2025-03-04T08:39:55Z
user: login: khallouh
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-03-04T09:15:24Z
user: login: khallouh
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-03-04T09:40:17Z
user: login: khallouh
state: APPROVED
author_association: COLLABORATOR
submitted_at: 2025-03-04T09:42:38Z

Review comments:
diff_hunk: @@ -346,6 +346,8 @@ AIE2PRegisterBankInfo::getInstrAlternativeMappings(
     SmallVector<PartialMappingIdx, 4> OpRegBankIdx(NumOperands, PMI_MOD);
     SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
     SmallVector<unsigned, 4> OpSize(NumOperands, 20);
+    // Operand[VecRegOpIdx]- vector operand.
+    OpSize[VecRegOpIdx] = VecRegSize;
path: llvm/lib/Target/AIE/aie2p/AIE2PRegisterBankInfo.cpp
user: login: niwinanto
body: Are we setting the vector size for `LOAD*` variants? DO you know why the unit tests where not complaining about this?
created_at: 2025-03-03T12:53:51Z
author_association: COLLABORATOR
diff_hunk: @@ -346,6 +346,8 @@ AIE2PRegisterBankInfo::getInstrAlternativeMappings(
     SmallVector<PartialMappingIdx, 4> OpRegBankIdx(NumOperands, PMI_MOD);
     SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
     SmallVector<unsigned, 4> OpSize(NumOperands, 20);
+    // Operand[VecRegOpIdx]- vector operand.
+    OpSize[VecRegOpIdx] = VecRegSize;
path: llvm/lib/Target/AIE/aie2p/AIE2PRegisterBankInfo.cpp
user: login: niwinanto
body: May be you could  `VecRegOpIdx ==idx ? VecRegSize: 20` at the uses, no need to create a vector.
created_at: 2025-03-03T12:54:12Z
author_association: COLLABORATOR
diff_hunk: @@ -373,12 +373,12 @@ body:             |
   ; CHECK-NEXT:   [[PHI1:%[0-9]+]]:ptrregbank(p0) = G_PHI [[COPY]](p0), %bb.0, %8(p0), %bb.1
   ; CHECK-NEXT:   [[PHI2:%[0-9]+]]:gprregbank(s32) = G_PHI [[C]](s32), %bb.0, %10(s32), %bb.1
   ; CHECK-NEXT:   [[PHI3:%[0-9]+]]:fiforegbank(<16 x s64>) = G_PHI [[DEF]](<16 x s64>), %bb.0, %12(<16 x s64>), %bb.1
-  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:accregbank(<16 x s64>) = COPY [[PHI3]](<16 x s64>)
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vregbank(<16 x s64>) = COPY [[PHI3]](<16 x s64>)
path: llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-phi.mir
user: login: niwinanto
body: Nice! we were selecting this wrong.
created_at: 2025-03-03T12:59:37Z
author_association: COLLABORATOR
diff_hunk: @@ -374,6 +374,51 @@ AIE2PRegisterBankInfo::getInstrAlternativeMappings(
     }
     return AltMappings;
   }
+  case TargetOpcode::G_UNMERGE_VALUES: {
+    const Register SrcReg = MI.getOperand(2).getReg();
+    const LLT SrcTy = MRI.getType(SrcReg);
+    unsigned SrcSize = getSizeInBits(SrcReg, MRI, TRI);
+    const LLT HalfSrcTy = SrcTy.divide(2);
+    const unsigned HalfSrcTySize = HalfSrcTy.getSizeInBits();
+    // Only the accumulator is of 2048-bit size, with the possible mapping
+    // restricted to accumulator register banks. For a 512-bit vector,
+    // the only possible mapping is to a vector register bank.
+    if (SrcSize <= 512 || SrcSize == 2048)
+      break;
+    // If the instruction has any implicit-defs or uses,
+    // do not mess with it.
+    if (MI.getNumOperands() != 3)
path: llvm/lib/Target/AIE/aie2p/AIE2PRegisterBankInfo.cpp
user: login: niwinanto
body: Probably you can assert here.
created_at: 2025-03-03T13:01:54Z
author_association: COLLABORATOR
diff_hunk: @@ -374,6 +374,51 @@ AIE2PRegisterBankInfo::getInstrAlternativeMappings(
     }
     return AltMappings;
   }
+  case TargetOpcode::G_UNMERGE_VALUES: {
+    const Register SrcReg = MI.getOperand(2).getReg();
+    const LLT SrcTy = MRI.getType(SrcReg);
+    unsigned SrcSize = getSizeInBits(SrcReg, MRI, TRI);
+    const LLT HalfSrcTy = SrcTy.divide(2);
+    const unsigned HalfSrcTySize = HalfSrcTy.getSizeInBits();
+    // Only the accumulator is of 2048-bit size, with the possible mapping
+    // restricted to accumulator register banks. For a 512-bit vector,
+    // the only possible mapping is to a vector register bank.
+    if (SrcSize <= 512 || SrcSize == 2048)
path: llvm/lib/Target/AIE/aie2p/AIE2PRegisterBankInfo.cpp
user: login: niwinanto
body: Move these lines down. If the size check fail, we can break without executing them.
```
    const LLT HalfSrcTy = SrcTy.divide(2);
    const unsigned HalfSrcTySize = HalfSrcTy.getSizeInBits();
```
created_at: 2025-03-03T13:06:00Z
author_association: COLLABORATOR
diff_hunk: @@ -374,6 +374,51 @@ AIE2PRegisterBankInfo::getInstrAlternativeMappings(
     }
     return AltMappings;
   }
+  case TargetOpcode::G_UNMERGE_VALUES: {
+    const Register SrcReg = MI.getOperand(2).getReg();
path: llvm/lib/Target/AIE/aie2p/AIE2PRegisterBankInfo.cpp
user: login: niwinanto
body: Super nit: You could use `MI.getNumOperands() - 1` instead hardcoding `3`, `G_UNMERGE_VALUES` can have more than 3 operands and 3 may not be a source operand. 
created_at: 2025-03-03T13:24:36Z
author_association: COLLABORATOR
diff_hunk: @@ -346,6 +346,8 @@ AIE2PRegisterBankInfo::getInstrAlternativeMappings(
     SmallVector<PartialMappingIdx, 4> OpRegBankIdx(NumOperands, PMI_MOD);
     SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
     SmallVector<unsigned, 4> OpSize(NumOperands, 20);
+    // Operand[VecRegOpIdx]- vector operand.
+    OpSize[VecRegOpIdx] = VecRegSize;
path: llvm/lib/Target/AIE/aie2p/AIE2PRegisterBankInfo.cpp
user: login: abnikant
body: yes, since we allow BaseIdxOffset as valid for size <= [RBIdx size]
created_at: 2025-03-04T05:57:52Z
author_association: COLLABORATOR
diff_hunk: @@ -374,6 +374,51 @@ AIE2PRegisterBankInfo::getInstrAlternativeMappings(
     }
     return AltMappings;
   }
+  case TargetOpcode::G_UNMERGE_VALUES: {
+    const Register SrcReg = MI.getOperand(2).getReg();
+    const LLT SrcTy = MRI.getType(SrcReg);
+    unsigned SrcSize = getSizeInBits(SrcReg, MRI, TRI);
+    const LLT HalfSrcTy = SrcTy.divide(2);
+    const unsigned HalfSrcTySize = HalfSrcTy.getSizeInBits();
+    // Only the accumulator is of 2048-bit size, with the possible mapping
+    // restricted to accumulator register banks. For a 512-bit vector,
+    // the only possible mapping is to a vector register bank.
+    if (SrcSize <= 512 || SrcSize == 2048)
path: llvm/lib/Target/AIE/aie2p/AIE2PRegisterBankInfo.cpp
user: login: abnikant
body: done
created_at: 2025-03-04T05:58:13Z
author_association: COLLABORATOR
diff_hunk: @@ -374,6 +374,51 @@ AIE2PRegisterBankInfo::getInstrAlternativeMappings(
     }
     return AltMappings;
   }
+  case TargetOpcode::G_UNMERGE_VALUES: {
+    const Register SrcReg = MI.getOperand(2).getReg();
path: llvm/lib/Target/AIE/aie2p/AIE2PRegisterBankInfo.cpp
user: login: abnikant
body: yes but not in RegisterBankSelect. We expect only 3 operands at this point. However I made this change, but still assert on 3 operands. 
created_at: 2025-03-04T05:59:16Z
author_association: COLLABORATOR
diff_hunk: @@ -145,3 +145,17 @@ body:             |
     %1:_(<4 x s64>), %2:_(<4 x s64>) = G_UNMERGE_VALUES %0(<8 x s64>)
     PseudoRET implicit $lr, implicit %2
 ...
+
+---
+name:            test_unmerge_v8s32
+legalized: true
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: test_unmerge_v8s32
+    ; CHECK: [[COPY:%[0-9]+]]:vregbank(<8 x s32>) = COPY $wl0
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:vregbank(<4 x s32>), [[UV1:%[0-9]+]]:vregbank(<4 x s32>) = G_UNMERGE_VALUES [[COPY]](<8 x s32>)
path: llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-unmerge-values.mir
user: login: khallouh
body: This is not using alternative mapping for because of the source size equal to 512. Could you add a test where it is used for other sizes where we can observe the difference between greedy and fast?
created_at: 2025-03-04T09:15:24Z
author_association: COLLABORATOR
diff_hunk: @@ -145,3 +145,17 @@ body:             |
     %1:_(<4 x s64>), %2:_(<4 x s64>) = G_UNMERGE_VALUES %0(<8 x s64>)
     PseudoRET implicit $lr, implicit %2
 ...
+
+---
+name:            test_unmerge_v8s32
+legalized: true
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: test_unmerge_v8s32
+    ; CHECK: [[COPY:%[0-9]+]]:vregbank(<8 x s32>) = COPY $wl0
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:vregbank(<4 x s32>), [[UV1:%[0-9]+]]:vregbank(<4 x s32>) = G_UNMERGE_VALUES [[COPY]](<8 x s32>)
path: llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-unmerge-values.mir
user: login: khallouh
body: Maybe there is no case where Greedy would be better because the Copies have the same cost. If so, you can ignore the above comment.
created_at: 2025-03-04T09:40:17Z
author_association: COLLABORATOR

PR comments:
user: login: khallouh
created_at: 2025-03-03T14:56:53Z
body: Last I checked we had only very minor improvements in a couple of QoR tests. Did you check how it looks like now? 
Also, there was a significant degradation in `Cumsum_AIE2_bfloat16` with greedy (128%), did you have a chance to look at it?
author_association: COLLABORATOR
user: login: abnikant
created_at: 2025-03-04T05:59:54Z
body: > Last I checked we had only very minor improvements in a couple of QoR tests. Did you check how it looks like now? Also, there was a significant degradation in `Cumsum_AIE2_bfloat16` with greedy (128%), did you have a chance to look at it?

This PR addresses compilation issues, but I will check the QoR. 
author_association: COLLABORATOR