Repository: deepin-community/kernel
Pull request #752: Base_ctrl: phytium: Add driver for base controller
Author: login: xuyan213
Labels: name: approved
Created: 2025-04-27T08:51:31Z | Merged: 2025-05-08T05:13:44Z

This driver provides interface functions for reading and writing base controller address.

## Summary by Sourcery

Add a new ACPI platform driver for the Phytium base controller.

New Features:
- Introduce the `phytium_base_ctrl` driver to manage the Phytium base controller.
- Export functions to allow other kernel modules to read/write base controller registers and retrieve its IRQ number.
- Add ACPI device ID matching for the Phytium base controller (`PHYT0007`).

Build:
- Add a Kconfig option (`CONFIG_PHYTIUM_BASE_CTRL`) to enable the driver.
- Update the ACPI Makefile to include the new driver file.


Diff:
diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
index cee82b473dc50..73e08daf0247e 100644
--- a/drivers/acpi/Kconfig
+++ b/drivers/acpi/Kconfig
@@ -45,6 +45,14 @@ if ACPI
 config ACPI_LEGACY_TABLES_LOOKUP
 	bool
 
+config PHYTIUM_BASE_CTRL
+	bool "Phytium base ctrl driver"
+	depends on ARCH_PHYTIUM || COMPILE_TEST
+	default y
+	help
+	  This driver provides interface functions for reading and
+	  writing phytium base controller device address.
+
 config ARCH_MIGHT_HAVE_ACPI_PDC
 	bool
 
diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
index eaa09bf52f176..e483aa370c2ef 100644
--- a/drivers/acpi/Makefile
+++ b/drivers/acpi/Makefile
@@ -42,6 +42,7 @@ acpi-y				+= resource.o
 acpi-y				+= acpi_processor.o
 acpi-y				+= processor_core.o
 acpi-$(CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC) += processor_pdc.o
+acpi-$(CONFIG_PHYTIUM_BASE_CTRL)	+= phytium_base_ctrl.o
 acpi-y				+= ec.o
 acpi-$(CONFIG_ACPI_DOCK)	+= dock.o
 acpi-$(CONFIG_PCI)		+= pci_root.o pci_link.o pci_irq.o
diff --git a/drivers/acpi/phytium_base_ctrl.c b/drivers/acpi/phytium_base_ctrl.c
new file mode 100644
index 0000000000000..5ebfd0794a452
--- /dev/null
+++ b/drivers/acpi/phytium_base_ctrl.c
@@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * base_ctrl driver for Phytium.
+ *
+ * Copyright (C) 2021-2024, Phytium Technology Co., Ltd.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/spinlock.h>
+#include <linux/acpi.h>
+
+#include "phytium_base_ctrl.h"
+
+#define BASE_CTRL_DRIVER_VERSION "1.1.0"
+
+static struct phytium_base_ctrl *boot_base_ctrl;
+
+int phytium_base_ctrl_irq(void)
+{
+	if (!boot_base_ctrl)
+		return -ENODEV;
+
+	return boot_base_ctrl->irq;
+}
+EXPORT_SYMBOL(phytium_base_ctrl_irq);
+
+int base_ctrl_read_int_status(void)
+{
+	unsigned long flags;
+	u16 value;
+
+	if (!boot_base_ctrl)
+		return 0;
+
+	spin_lock_irqsave(&boot_base_ctrl->lock, flags);
+	value = readw(boot_base_ctrl->base + boot_base_ctrl->int_status_reg);
+	spin_unlock_irqrestore(&boot_base_ctrl->lock, flags);
+
+	return value;
+}
+EXPORT_SYMBOL(base_ctrl_read_int_status);
+
+void base_ctrl_write_int_clear(int val)
+{
+	unsigned long flags;
+
+	if (!boot_base_ctrl)
+		return;
+
+	spin_lock_irqsave(&boot_base_ctrl->lock, flags);
+	writew(val, boot_base_ctrl->base + boot_base_ctrl->int_clear_reg);
+	spin_unlock_irqrestore(&boot_base_ctrl->lock, flags);
+}
+EXPORT_SYMBOL(base_ctrl_write_int_clear);
+
+bool phytium_check_cpu(void)
+{
+#ifdef CONFIG_ARCH_PHYTIUM
+	if (read_cpuid_implementor() == ARM_CPU_IMP_PHYTIUM)
+		return true;
+#endif
+	return false;
+}
+EXPORT_SYMBOL(phytium_check_cpu);
+
+u8 base_ctrl_readb(unsigned long offset)
+{
+	unsigned long flags;
+	u8 value;
+
+	if (!boot_base_ctrl)
+		return 1;
+
+	spin_lock_irqsave(&boot_base_ctrl->lock, flags);
+	value = readb(boot_base_ctrl->base + offset);
+	spin_unlock_irqrestore(&boot_base_ctrl->lock, flags);
+	return value;
+}
+EXPORT_SYMBOL(base_ctrl_readb);
+
+u32 base_ctrl_readl(unsigned long offset)
+{
+	unsigned long flags;
+	u32 value;
+
+	if (!boot_base_ctrl)
+		return 1;
+
+	spin_lock_irqsave(&boot_base_ctrl->lock, flags);
+	value = readl(boot_base_ctrl->base + offset);
+	spin_unlock_irqrestore(&boot_base_ctrl->lock, flags);
+
+	return value;
+}
+EXPORT_SYMBOL(base_ctrl_readl);
+
+int base_ctrl_writeb(unsigned long offset, u8 value)
+{
+	unsigned long flags;
+
+	if (!boot_base_ctrl)
+		return 0;
+
+	spin_lock_irqsave(&boot_base_ctrl->lock, flags);
+	writeb(value, boot_base_ctrl->base + offset);
+	spin_unlock_irqrestore(&boot_base_ctrl->lock, flags);
+
+	return 0;
+}
+EXPORT_SYMBOL(base_ctrl_writeb);
+
+int base_ctrl_writel(unsigned long offset, u32 value)
+{
+	unsigned long flags;
+
+	if (!boot_base_ctrl)
+		return 0;
+
+	spin_lock_irqsave(&boot_base_ctrl->lock, flags);
+	writel(value, boot_base_ctrl->base + offset);
+	spin_unlock_irqrestore(&boot_base_ctrl->lock, flags);
+
+	return 0;
+}
+EXPORT_SYMBOL(base_ctrl_writel);
+
+static int phytium_base_ctrl_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct phytium_base_ctrl *base_ctrl;
+	int error = -1;
+
+	base_ctrl = devm_kzalloc(dev, sizeof(*base_ctrl), GFP_KERNEL);
+	if (!base_ctrl)
+		return -ENOMEM;
+
+	base_ctrl->dev = &pdev->dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENOENT;
+
+	base_ctrl->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(base_ctrl->base)) {
+		dev_err(&pdev->dev, "region map failed\n");
+		return PTR_ERR(base_ctrl->base);
+	}
+
+	base_ctrl->irq = platform_get_irq(pdev, 0);
+	if (base_ctrl->irq < 0) {
+		dev_err(&pdev->dev, "no irq resource?\n");
+		return base_ctrl->irq;
+	}
+
+	error = device_property_read_u32(&pdev->dev, "int_state",
+			&base_ctrl->int_status_reg);
+	if (error)
+		base_ctrl->int_status_reg = base_ctrl_INT_STATE;
+
+	error = device_property_read_u32(&pdev->dev, "clr_int",
+				&base_ctrl->int_clear_reg);
+	if (error)
+		base_ctrl->int_clear_reg = base_ctrl_CLR_INT;
+
+	spin_lock_init(&base_ctrl->lock);
+	boot_base_ctrl = base_ctrl;
+	platform_set_drvdata(pdev, base_ctrl);
+
+	return 0;
+}
+
+static const struct acpi_device_id base_ctrl_acpi_match[] = {
+	{ "PHYT0007", 0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(acpi, base_ctrl_acpi_match);
+
+static struct platform_driver phytium_base_ctrl_driver = {
+	.probe		= phytium_base_ctrl_probe,
+	.driver	= {
+		.name	= "phytium_base_ctrl",
+		.acpi_match_table = ACPI_PTR(base_ctrl_acpi_match),
+	},
+};
+
+module_platform_driver(phytium_base_ctrl_driver);
+
+static int __init phytium_base_ctrl_init(void)
+{
+	platform_driver_register(&phytium_base_ctrl_driver);
+	return 0;
+}
+
+static void __exit phytium_base_ctrl_exit(void)
+{
+	platform_driver_unregister(&phytium_base_ctrl_driver);
+}
+
+early_initcall(phytium_base_ctrl_init);
+MODULE_AUTHOR("Li Yuze <liyuze@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium base_ctrl driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(BASE_CTRL_DRIVER_VERSION);
diff --git a/drivers/acpi/phytium_base_ctrl.h b/drivers/acpi/phytium_base_ctrl.h
new file mode 100644
index 0000000000000..017f21e5ac6af
--- /dev/null
+++ b/drivers/acpi/phytium_base_ctrl.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * acpi/phytium_base_ctrl.h
+ *
+ * Copyright (C) 2021-2024, Phytium Technology Co., Ltd.
+ */
+
+#define	base_ctrl_INT_STATE	0x7FFFFC4
+#define	base_ctrl_CLR_INT	0x7FFFFC0
+
+struct phytium_base_ctrl {
+	struct device *dev;
+	void __iomem *base;
+	int irq;
+	spinlock_t lock;
+	u32 int_status_reg;
+	u32 int_clear_reg;
+};
+
+int phytium_base_ctrl_irq(void);
+u8 base_ctrl_readb(unsigned long offset);
+u32 base_ctrl_readl(unsigned long offset);
+bool phytium_check_cpu(void);
+int base_ctrl_writeb(unsigned long offset, u8 value);
+int base_ctrl_writel(unsigned long offset, u32 value);
+int base_ctrl_read_int_status(void);
+void base_ctrl_write_int_clear(int val);


Reviews:
user: login: sourcery-ai[bot]
body: Hey @xuyan213 - I've reviewed your changes - here's some feedback:

**Overall Comments**:
- Consider if using a global variable (`boot_base_ctrl`) is necessary, or if device state could be managed more conventionally.
- Exported function names are inconsistent (e.g., `phytium_base_ctrl_irq` vs `base_ctrl_readb`); consider using a consistent prefix.
- The `phytium_check_cpu` function seems unrelated to the base controller; consider relocating it to a more appropriate module or architecture-specific code.

<details>
<summary>Here's what I looked at during the review</summary>

- 🟢 **General issues**: all looks good
- 🟢 **Security**: all looks good
- 🟢 **Testing**: all looks good
- 🟡 **Complexity**: 1 issue found
- 🟢 **Documentation**: all looks good
</details>

***

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state: COMMENTED
author_association: NONE
submitted_at: 2025-04-27T08:53:53Z
user: login: Avenger-285714
state: COMMENTED
author_association: MEMBER
submitted_at: 2025-05-07T13:59:36Z
user: login: opsiff
body: /approve
state: APPROVED
author_association: MEMBER
submitted_at: 2025-05-08T05:11:38Z
user: login: opsiff
state: COMMENTED
author_association: MEMBER
submitted_at: 2025-05-08T05:13:28Z

Review comments:
diff_hunk: @@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * base_ctrl driver for Phytium.
+ *
+ * Copyright (C) 2021-2024, Phytium Technology Co., Ltd.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/spinlock.h>
+#include <linux/acpi.h>
+
+#include "phytium_base_ctrl.h"
+
+#define BASE_CTRL_DRIVER_VERSION "1.1.0"
+
+static struct phytium_base_ctrl *boot_base_ctrl;
+
+int phytium_base_ctrl_irq(void)
+{
+	if (!boot_base_ctrl)
+		return -ENODEV;
+
+	return boot_base_ctrl->irq;
+}
+EXPORT_SYMBOL(phytium_base_ctrl_irq);
+
+int base_ctrl_read_int_status(void)
+{
+	unsigned long flags;
+	u16 value;
+
+	if (!boot_base_ctrl)
+		return 0;
+
+	spin_lock_irqsave(&boot_base_ctrl->lock, flags);
+	value = readw(boot_base_ctrl->base + boot_base_ctrl->int_status_reg);
+	spin_unlock_irqrestore(&boot_base_ctrl->lock, flags);
+
+	return value;
+}
+EXPORT_SYMBOL(base_ctrl_read_int_status);
+
+void base_ctrl_write_int_clear(int val)
+{
+	unsigned long flags;
+
+	if (!boot_base_ctrl)
+		return;
+
+	spin_lock_irqsave(&boot_base_ctrl->lock, flags);
+	writew(val, boot_base_ctrl->base + boot_base_ctrl->int_clear_reg);
+	spin_unlock_irqrestore(&boot_base_ctrl->lock, flags);
+}
+EXPORT_SYMBOL(base_ctrl_write_int_clear);
+
+bool phytium_check_cpu(void)
+{
+#ifdef CONFIG_ARCH_PHYTIUM
+	if (read_cpuid_implementor() == ARM_CPU_IMP_PHYTIUM)
+		return true;
+#endif
+	return false;
+}
+EXPORT_SYMBOL(phytium_check_cpu);
+
+u8 base_ctrl_readb(unsigned long offset)
path: drivers/acpi/phytium_base_ctrl.c
user: login: sourcery-ai[bot]
body: **issue (complexity):** Consider using macros to encapsulate the locking and read/write operations to reduce code duplication and improve maintainability.

You can reduce duplication by abstracting the repeated locking/read/write pattern into inline functions or macros. This avoids having nearly identical lock‐acquire and release sequences in every function while keeping all functionality intact.

For example, you could define read and write macros like this:

```c
#define BASE_CTRL_READ_OP(type, def_val, op)             \
	do {                                               \
		unsigned long flags;                         \
		type ret;                                    \
		if (!boot_base_ctrl)                         \
			return (def_val);                        \
		spin_lock_irqsave(&boot_base_ctrl->lock, flags); \
		ret = (op);                                  \
		spin_unlock_irqrestore(&boot_base_ctrl->lock, flags); \
		return ret;                                  \
	} while (0)

#define BASE_CTRL_WRITE_OP(default_ret, op)              \
	do {                                               \
		unsigned long flags;                         \
		if (!boot_base_ctrl)                         \
			return (default_ret);                    \
		spin_lock_irqsave(&boot_base_ctrl->lock, flags); \
		op;                                          \
		spin_unlock_irqrestore(&boot_base_ctrl->lock, flags); \
		return 0;                                    \
	} while (0)
```

Then you can simplify your functions:

```c
u8 base_ctrl_readb(unsigned long offset)
{
    BASE_CTRL_READ_OP(u8, 1, readb(boot_base_ctrl->base + offset));
}

u32 base_ctrl_readl(unsigned long offset)
{
    BASE_CTRL_READ_OP(u32, 1, readl(boot_base_ctrl->base + offset));
}

int base_ctrl_writeb(unsigned long offset, u8 value)
{
    BASE_CTRL_WRITE_OP(0, writeb(value, boot_base_ctrl->base + offset));
}

int base_ctrl_writel(unsigned long offset, u32 value)
{
    BASE_CTRL_WRITE_OP(0, writel(value, boot_base_ctrl->base + offset));
}
```

This refactoring removes code duplication while preserving functionality and improves maintainability for future changes.
created_at: 2025-04-27T08:53:53Z
author_association: NONE
diff_hunk: @@ -45,6 +45,13 @@ if ACPI
 config ACPI_LEGACY_TABLES_LOOKUP
 	bool
 
+config PHYTIUM_BASE_CTRL
+	bool "Phytium base ctrl driver"
path: drivers/acpi/Kconfig
user: login: Avenger-285714
body: 建议让其依赖ARCH_PHYTIUM || COMPILE_TEST
created_at: 2025-05-07T13:57:47Z
author_association: MEMBER
diff_hunk: @@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * base_ctrl driver for Phytium.
+ *
+ * Copyright (C) 2021-2024, Phytium Technology Co., Ltd.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/spinlock.h>
+#include <linux/acpi.h>
+
+#include "phytium_base_ctrl.h"
+
+#define BASE_CTRL_DRIVER_VERSION "1.1.0"
+
+static struct phytium_base_ctrl *boot_base_ctrl;
+
+int phytium_base_ctrl_irq(void)
+{
+	if (!boot_base_ctrl)
+		return -ENODEV;
+
+	return boot_base_ctrl->irq;
+}
+EXPORT_SYMBOL(phytium_base_ctrl_irq);
+
+int base_ctrl_read_int_status(void)
+{
+	unsigned long flags;
+	u16 value;
+
+	if (!boot_base_ctrl)
+		return 0;
+
+	spin_lock_irqsave(&boot_base_ctrl->lock, flags);
+	value = readw(boot_base_ctrl->base + boot_base_ctrl->int_status_reg);
+	spin_unlock_irqrestore(&boot_base_ctrl->lock, flags);
+
+	return value;
+}
+EXPORT_SYMBOL(base_ctrl_read_int_status);
+
+void base_ctrl_write_int_clear(int val)
+{
+	unsigned long flags;
+
+	if (!boot_base_ctrl)
+		return;
+
+	spin_lock_irqsave(&boot_base_ctrl->lock, flags);
+	writew(val, boot_base_ctrl->base + boot_base_ctrl->int_clear_reg);
+	spin_unlock_irqrestore(&boot_base_ctrl->lock, flags);
+}
+EXPORT_SYMBOL(base_ctrl_write_int_clear);
+
+bool phytium_check_cpu(void)
+{
+#ifdef CONFIG_ARCH_PHYTIUM
+	if (read_cpuid_implementor() == ARM_CPU_IMP_PHYTIUM)
+		return true;
+#endif
+	return false;
+}
+EXPORT_SYMBOL(phytium_check_cpu);
+
+u8 base_ctrl_readb(unsigned long offset)
+{
+	unsigned long flags;
+	u8 value;
+
+	if (!boot_base_ctrl)
+		return 1;
path: drivers/acpi/phytium_base_ctrl.c
user: login: opsiff
body: 几个 return 1的地方在使用的时候要注意到是!boot_base_ctrl
created_at: 2025-05-08T05:13:28Z
author_association: MEMBER

PR comments:
user: login: sourcery-ai[bot]
created_at: 2025-04-27T08:51:35Z
body: <!-- Generated by sourcery-ai[bot]: start review_guide -->

## Reviewer's Guide by Sourcery

This pull request adds a new driver for the Phytium base controller. The driver provides functions to interact with the base controller hardware, including reading and writing registers and managing interrupts. It is implemented as a platform driver and can be configured via Kconfig.

_No diagrams generated as the changes look simple and do not need a visual representation._

### File-Level Changes

| Change | Details | Files |
| ------ | ------- | ----- |
| Add the source code for the Phytium base controller driver. | <ul><li>Define the structure for the base controller device data.</li><li>Implement the probe function to initialize the device, map memory, and get IRQ.</li><li>Implement functions for reading and writing byte and word registers.</li><li>Implement functions for reading and clearing interrupt status.</li><li>Implement a function to check if the CPU is Phytium.</li><li>Define the ACPI device match table.</li><li>Register the driver as a platform driver.</li><li>Define register offset constants and declare driver functions in the header file.</li></ul> | `drivers/acpi/phytium_base_ctrl.c`<br/>`drivers/acpi/phytium_base_ctrl.h` |
| Update build system and configuration to include the new driver. | <ul><li>Add a Kconfig option to enable the Phytium base controller driver.</li><li>Modify the Makefile to compile the driver based on the Kconfig option.</li></ul> | `drivers/acpi/Makefile`<br/>`drivers/acpi/Kconfig` |

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author_association: NONE
user: login: deepin-ci-robot
created_at: 2025-05-08T02:16:49Z
body: ### deepin pr auto review
代码审查意见：

1. 在`phytium_base_ctrl.c`文件中，`base_ctrl_readb`和`base_ctrl_readl`函数返回值为1，这可能不是预期的行为。建议检查这些函数的返回值是否应该返回读取的数据。

2. `base_ctrl_writeb`和`base_ctrl_writel`函数的返回值总是0，这可能不足以表示操作是否成功。建议根据操作结果返回适当的错误码。

3. `phytium_base_ctrl_probe`函数中，`error`变量在成功时没有更新，这可能导致在错误处理时出现问题。建议在成功时将`error`设置为0。

4. `phytium_base_ctrl_probe`函数中，`base_ctrl->irq`的值没有进行错误检查。如果`platform_get_irq`返回负值，应该立即返回错误码。

5. `phytium_base_ctrl_probe`函数中，`device_property_read_u32`函数的错误处理不够完善。如果读取属性失败，应该记录错误并返回适当的错误码。

6. `phytium_base_ctrl.c`文件中的`EXPORT_SYMBOL`宏用于导出函数，但是没有对应的导入函数声明。建议在相应的头文件中添加对应的函数声明。

7. `phytium_base_ctrl.c`文件中的`phytium_check_cpu`函数使用了`CONFIG_ARCH_PHYTIUM`配置选项，但是没有在`Kconfig`文件中定义这个选项。建议在`Kconfig`文件中添加相应的配置选项。

8. `phytium_base_ctrl.c`文件中的`phytium_base_ctrl_init`和`phytium_base_ctrl_exit`函数使用了`early_initcall`宏，但是没有在`Makefile`文件中添加相应的编译规则。建议在`Makefile`文件中添加相应的编译规则。

9. `phytium_base_ctrl.c`文件中的`phytium_base_ctrl_init`和`phytium_base_ctrl_exit`函数使用了`early_initcall`宏，但是没有在`Kconfig`文件中添加相应的配置选项。建议在`Kconfig`文件中添加相应的配置选项。

10. `phytium_base_ctrl.c`文件中的`phytium_base_ctrl_init`和`phytium_base_ctrl_exit`函数使用了`early_initcall`宏，但是没有在`Kconfig`文件中添加相应的配置选项。建议在`Kconfig`文件中添加相应的配置选项。

以上是针对代码审查意见的详细说明，希望能够对您有所帮助。
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