Repository: opencompl/lean-mlir
Pull request #1257: feat: add simp_riscv tactic
Author: login: salinhkuhn
Created: 2025-05-22T10:20:47Z | Merged: 2025-05-22T12:37:34Z

This PR adds a simplifying tactic for RiscV semantic definitions.


Diff:
diff --git a/SSA/Projects/RISCV64/Semantics.lean b/SSA/Projects/RISCV64/Semantics.lean
index 0ac7dd803a..7fc55e40e1 100644
--- a/SSA/Projects/RISCV64/Semantics.lean
+++ b/SSA/Projects/RISCV64/Semantics.lean
@@ -1,5 +1,6 @@
 import SSA.Core.MLIRSyntax.EDSL
 import SSA.Projects.InstCombine.ForLean
+import SSA.Projects.RISCV64.Tactic.SimpRiscVAttr
 set_option maxHeartbeats 1000000000000000000
 
 open BitVec
@@ -21,19 +22,24 @@ open BitVec
 
 namespace RV64Semantics
 
+@[simp_riscv]
 def ADDIW_pure64 (imm : BitVec 12) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.signExtend 64 (BitVec.setWidth 32 (BitVec.add (BitVec.signExtend 64 imm) rs1_val))
 
 -- loads immediate into upper 20 bits and then fills the rest up with 0 and returns it as the result
+@[simp_riscv]
 def UTYPE_pure64_lui (imm : BitVec 20) : BitVec 64 :=
   BitVec.signExtend 64 (imm ++ (0x000 : (BitVec 12)))
 
+@[simp_riscv]
 def UTYPE_pure64_AUIPC (imm : BitVec 20) (pc : BitVec 64) : BitVec 64 :=
   BitVec.add (BitVec.signExtend 64 (BitVec.append imm (0x000 : BitVec 12))) pc
 
+@[simp_riscv]
 def SHIFTIWOP_pure64_RISCV_SLLIW (shamt : BitVec 5) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.signExtend 64 (BitVec.shiftLeft (BitVec.extractLsb' 0 32 rs1_val) (shamt).toNat)
 
+@[simp_riscv]
 def SHIFTIWOP_pure64_RISCV_SLLIW_bv (shamt : BitVec 5) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.signExtend 64 ((BitVec.extractLsb' 0 32 rs1_val)  <<< shamt)
 
@@ -42,9 +48,11 @@ theorem SHIFTIWOP_pure64_RISCV_SLLIW_eq_SHIFTIWOP_pure64_RISCV_SLLIW_bv (shamt :
   unfold SHIFTIWOP_pure64_RISCV_SLLIW SHIFTIWOP_pure64_RISCV_SLLIW_bv
   rfl
 
+@[simp_riscv]
 def SHIFTIWOP_pure64_RISCV_SRLIW (shamt : BitVec 5) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.signExtend 64 (BitVec.ushiftRight (BitVec.extractLsb' 0 32 rs1_val) (shamt).toNat)
 
+@[simp_riscv]
 def SHIFTIWOP_pure64_RISCV_SRLIW_bv (shamt : BitVec 5) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.signExtend 64 ((BitVec.extractLsb' 0 32 rs1_val) >>> shamt)
 
@@ -53,6 +61,7 @@ theorem  SHIFTIWOP_pure64_RISCV_SRLIW_eq_SHIFTIWOP_pure64_RISCV_SRLIW_bv (shamt
   unfold SHIFTIWOP_pure64_RISCV_SRLIW SHIFTIWOP_pure64_RISCV_SRLIW_bv
   rfl
 
+@[simp_riscv]
 def SHIFTIWOP_pure64_RISCV_SRAIW (shamt : BitVec 5) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.signExtend 64
     (BitVec.setWidth 32
@@ -61,6 +70,7 @@ def SHIFTIWOP_pure64_RISCV_SRAIW (shamt : BitVec 5) (rs1_val : BitVec 64) : BitV
         shamt.toNat
         (BitVec.signExtend (32 + shamt.toNat) (BitVec.extractLsb 31 0 rs1_val))))
 
+@[simp_riscv]
 def SHIFTIWOP_pure64_RISCV_SRAIW_bv (shamt : BitVec 5) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.signExtend 64 (BitVec.sshiftRight' (BitVec.extractLsb 31 0 rs1_val) shamt)
 
@@ -70,9 +80,11 @@ theorem SHIFTIWOP_pure64_RISCV_SRAIW_eq_SHIFTIWOP_pure64_RISCV_SRAIW_bv (shamt :
   rw [← sshiftRight_eq_setWidth_extractLsb_signExtend]
   rfl
 
+@[simp_riscv]
 def SHIFTIOP_pure64_RISCV_SLLI (shamt : BitVec 6) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.shiftLeft rs1_val shamt.toNat
 
+@[simp_riscv]
 def  SHIFTIOP_pure64_RISCV_SLLI_bv (shamt : BitVec 6) (rs1_val : BitVec 64) : BitVec 64 :=
   rs1_val <<< shamt
 
@@ -81,9 +93,11 @@ theorem SHIFTIOP_pure64_RISCV_SLLI_eq_SHIFTIOP_pure64_RISCV_SLLI_bv :
   unfold SHIFTIOP_pure64_RISCV_SLLI SHIFTIOP_pure64_RISCV_SLLI_bv
   simp only [BitVec.shiftLeft_eq, BitVec.shiftLeft_eq']
 
+@[simp_riscv]
 def SHIFTIOP_pure64_RISCV_SRLI (shamt : BitVec 6) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.ushiftRight rs1_val shamt.toNat
 
+@[simp_riscv]
 def SHIFTIOP_pure64_RISCV_SRLI_bv (shamt : BitVec 6) (rs1_val : BitVec 64) : BitVec 64 :=
     rs1_val >>> shamt
 
@@ -92,11 +106,13 @@ theorem SHIFTIOP_pure64_RISCV_SRLI_eq_SHIFTIOP_pure64_RISCV_SRLI_bv (shamt : Bit
   unfold SHIFTIOP_pure64_RISCV_SRLI SHIFTIOP_pure64_RISCV_SRLI_bv
   simp
 
+@[simp_riscv]
 def SHIFTIOP_pure64_RISCV_SRAI (shamt : BitVec 6) (rs1_val : BitVec 64): BitVec 64 :=
   let value := rs1_val ;
   let shift := shamt.toNat;
   BitVec.setWidth 64 (BitVec.extractLsb (63 + shift) shift (BitVec.signExtend (64 + shift) value))
 
+@[simp_riscv]
 def SHIFTIOP_pure64_RISCV_SRAI_bv (shamt : BitVec 6) (rs1_val : BitVec 64): BitVec 64 :=
   BitVec.sshiftRight' rs1_val  shamt
 
@@ -108,22 +124,26 @@ theorem SHIFTIOP_pure64_RISCV_SRAI_eq_SHIFTIOP_pure64_RISCV_SRAI_bv
   simp only [BitVec.sshiftRight_eq']
   rw [sshiftRight_eq_setWidth_extractLsb_signExtend]
 
+@[simp_riscv]
 def RTYPEW_pure64_RISCV_ADDW (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   let rs1_val32 := BitVec.extractLsb' 0 32 rs1_val;
   let rs2_val32 := BitVec.extractLsb' 0 32 rs2_val;
   BitVec.signExtend 64 (BitVec.add rs1_val32 rs2_val32)
 
+@[simp_riscv]
 def RTYPEW_pure64_RISCV_SUBW (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   let rs1_val32 := BitVec.extractLsb' 0 32 rs1_val;
   let rs2_val32 := BitVec.extractLsb' 0 32 rs2_val;
   BitVec.signExtend 64 (BitVec.sub rs1_val32 rs2_val32)
 
+@[simp_riscv]
 def RTYPEW_pure64_RISCV_SLLW (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   let rs1_val32 := BitVec.extractLsb' 0 32 rs1_val;
   let rs2_val32 := BitVec.extractLsb' 0 32 rs2_val;
   let shamt := BitVec.extractLsb' 0 5 rs2_val32;
   BitVec.signExtend 64 (BitVec.shiftLeft rs1_val32 shamt.toNat)
 
+@[simp_riscv]
 def RTYPEW_pure64_RISCV_SLLW_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   let rs1_val32 := BitVec.extractLsb' 0 32 rs1_val;
   let rs2_val32 := BitVec.extractLsb' 0 32 rs2_val;
@@ -138,12 +158,14 @@ theorem RTYPEW_pure64_RISCV_SLLW_eq_RTYPEW_pure64_RISCV_SLLW_bv
   simp only [extractLsb'_eq_setWidth, Nat.reduceLeDiff, BitVec.setWidth_setWidth_of_le,
     BitVec.toNat_setWidth, Nat.reducePow, BitVec.shiftLeft_eq, BitVec.shiftLeft_eq']
 
+@[simp_riscv]
 def RTYPEW_pure64_RISCV_SRLW (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   let rs1_val32 := BitVec.extractLsb' 0 32 rs1_val;
   let rs2_val32 := BitVec.extractLsb' 0 32 rs2_val;
   let shamt := BitVec.extractLsb' 0 5 rs2_val32;
   BitVec.signExtend 64 (BitVec.ushiftRight rs1_val32 shamt.toNat)
 
+@[simp_riscv]
 def RTYPEW_pure64_RISCV_SRLW_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   let rs1_val32 := BitVec.extractLsb' 0 32 rs1_val;
   let rs2_val32 := BitVec.extractLsb' 0 32 rs2_val;
@@ -157,6 +179,7 @@ theorem RTYPEW_pure64_RISCV_SLLW_eq_RTYPEW_pure64_RISCV_SRLW_bv
   unfold RTYPEW_pure64_RISCV_SRLW RTYPEW_pure64_RISCV_SRLW_bv
   simp
 
+@[simp_riscv]
 def RTYPEW_pure64_RISCV_SRAW (rs2_val : BitVec 64) (rs1_val : BitVec 64) :=
   BitVec.signExtend 64
         (BitVec.setWidth 32
@@ -166,6 +189,7 @@ def RTYPEW_pure64_RISCV_SRAW (rs2_val : BitVec 64) (rs1_val : BitVec 64) :=
                       (BitVec.signExtend (32 + rs2_val.toNat % 4294967296 % 32)
                           (BitVec.extractLsb 31 0 rs1_val))))
 
+@[simp_riscv]
 def RTYPEW_pure64_RISCV_SRAW_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) :=
   BitVec.signExtend 64
   (BitVec.sshiftRight' (BitVec.extractLsb 31 0 rs1_val) (BitVec.extractLsb 4 0 rs2_val))
@@ -178,30 +202,38 @@ theorem RTYPEW_pure64_RISCV_SRAW_eq_RTYPEW_pure64_RISCV_SRAW_bv
   rw [← sshiftRight_eq_setWidth_extractLsb_signExtend]
   simp
 
+@[simp_riscv]
 def RTYPE_pure64_RISCV_ADD (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.add rs1_val rs2_val
 
+@[simp_riscv]
 def RTYPE_pure64_RISCV_SLT (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   let b := BitVec.slt rs1_val rs2_val;
   BitVec.setWidth 64 (BitVec.ofBool b)
 
+@[simp_riscv]
 def RTYPE_pure64_RISCV_SLTU (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   let b := BitVec.ult rs1_val rs2_val;
   BitVec.setWidth 64 (BitVec.ofBool b)
 
+@[simp_riscv]
 def RTYPE_pure64_RISCV_AND (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.and rs2_val rs1_val
 
+@[simp_riscv]
 def RTYPE_pure64_RISCV_OR (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.or rs2_val rs1_val
 
+@[simp_riscv]
 def RTYPE_pure64_RISCV_XOR (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.xor rs2_val rs1_val
 
+@[simp_riscv]
 def RTYPE_pure64_RISCV_SLL (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   let shamt := (BitVec.extractLsb 5 0 rs2_val).toNat;
   BitVec.shiftLeft rs1_val shamt
 
+@[simp_riscv]
 def RTYPE_pure64_RISCV_SLL_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   let shamt := (BitVec.extractLsb 5 0 rs2_val);
   rs1_val <<< shamt
@@ -213,10 +245,12 @@ theorem RTYPE_pure64_RISCV_SLL_eq_RTYPE_pure64_RISCV_SLL_bv
   unfold RTYPE_pure64_RISCV_SLL  RTYPE_pure64_RISCV_SLL_bv
   simp
 
+@[simp_riscv]
 def RTYPE_pure64_RISCV_SRL (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   let shamt := (BitVec.extractLsb 5 0 rs2_val).toNat;
   BitVec.ushiftRight rs1_val shamt
 
+@[simp_riscv]
 def RTYPE_pure64_RISCV_SRL_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   let shamt := BitVec.extractLsb 5 0 rs2_val
   rs1_val >>> shamt
@@ -229,9 +263,11 @@ theorem RTYPE_pure64_RISCV_SRL_eq_RTYPE_pure64_RISCV_SRL_bv
   unfold RTYPE_pure64_RISCV_SRL RTYPE_pure64_RISCV_SRL_bv
   simp
 
+@[simp_riscv]
 def RTYPE_pure64_RISCV_SUB (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.sub rs1_val rs2_val
 
+@[simp_riscv]
 def RTYPE_pure64_RISCV_SRA (rs2_val : BitVec 64) (rs1_val : BitVec 64) :=
   BitVec.setWidth 64
     (BitVec.extractLsb
@@ -240,6 +276,7 @@ def RTYPE_pure64_RISCV_SRA (rs2_val : BitVec 64) (rs1_val : BitVec 64) :=
         (BitVec.signExtend
          (64 + (BitVec.extractLsb 5 0 rs2_val).toNat) rs1_val))
 
+@[simp_riscv]
 def RTYPE_pure64_RISCV_SRA_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.sshiftRight' rs1_val (BitVec.extractLsb 5 0 rs2_val)
 
@@ -252,6 +289,7 @@ theorem RTYPE_pure64_RISCV_SRA_eqRTYPE_pure64_RISCV_SRA_bv
 
 /- wip : working on removing toNats and toInts in this definiton, therefore waiting for a
  bit vec lemma to be upstreamed. -/
+ @[simp_riscv]
 def REMW_pure64_unsigned (rs2_val : BitVec 64) (rs1_val : BitVec 64): BitVec 64 :=
   BitVec.signExtend 64
     (BitVec.extractLsb' 0 32
@@ -259,6 +297,7 @@ def REMW_pure64_unsigned (rs2_val : BitVec 64) (rs1_val : BitVec 64): BitVec 64
         (if ((BitVec.extractLsb 31 0 rs2_val).toNat : Int) = 0 then ↑(BitVec.extractLsb 31 0 rs1_val).toNat
         else ((BitVec.extractLsb 31 0 rs1_val).toNat : Int).tmod ↑(BitVec.extractLsb 31 0 rs2_val).toNat)))
 
+@[simp_riscv]
 def REMW_pure64_unsigned_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.signExtend 64
     ((BitVec.extractLsb 31 0 rs1_val).umod (BitVec.extractLsb 31 0 rs2_val))
@@ -301,13 +340,14 @@ theorem REMW_pure64_unsigned_eq_REMW_pure64_unsigned_bv (rs2_val : BitVec 64) (r
         Nat.shiftRight_zero, Nat.sub_zero, Nat.reduceAdd, Int.natCast_emod, Nat.cast_ofNat]
       rfl
 
+@[simp_riscv]
 def REMW_pure64_signed (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
     BitVec.signExtend 64
       (BitVec.extractLsb' 0 32
         (BitVec.ofInt (33)
           (if (BitVec.extractLsb 31 0 rs2_val).toInt = 0 then (BitVec.extractLsb 31 0 rs1_val).toInt
           else (BitVec.extractLsb 31 0 rs1_val).toInt.tmod (BitVec.extractLsb 31 0 rs2_val).toInt)))
-
+@[simp_riscv]
 def REMW_pure64_signed_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
     BitVec.signExtend 64
     ((BitVec.extractLsb 31 0 rs1_val).srem (BitVec.extractLsb 31 0 rs2_val))
@@ -328,10 +368,12 @@ theorem REMW_pure64_signed_eq_REMW_pure64_signed (rs2_val : BitVec 64) (rs1_val
   case e_x.isFalse hf =>
     rw [← BitVec.toInt_srem, BitVec.ofInt_toInt]
 
+@[simp_riscv]
 def REM_pure64_unsigned (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.extractLsb' 0 64
     (BitVec.ofInt 65 (if (rs2_val.toNat: Int) = 0 then (rs1_val.toNat: Int)  else (rs1_val.toNat :Int).tmod (rs2_val.toNat : Int)))
 
+@[simp_riscv]
 def REM_pure64_unsigned_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   if rs2_val = 0 then rs1_val else ((rs1_val).umod (rs2_val))
 
@@ -357,10 +399,12 @@ theorem  REM_pure64_unsigned_eq_REM_pure64_unsigned_bv (rs2_val : BitVec 64) (rs
         simp only [BitVec.toInt_ofInt, Nat.reducePow, BitVec.toInt_umod]
         rfl
 
+@[simp_riscv]
 def REM_pure64_signed (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.extractLsb' 0 64
   (BitVec.ofInt 65 (if rs2_val.toInt = 0 then rs1_val.toInt else rs1_val.toInt.tmod rs2_val.toInt))
 
+@[simp_riscv]
 def REM_pure64_signed_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   rs1_val.srem rs2_val
 
@@ -377,12 +421,14 @@ theorem REM_pure64_signed_eq_REM_pure64_signed_bv (rs2_val : BitVec 64) (rs1_val
   case isFalse hf =>
     rw [← BitVec.toInt_srem, BitVec.ofInt_toInt]
 
+@[simp_riscv]
 def MULW_pure64 (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.signExtend 64
     (BitVec.extractLsb 31 0
       (BitVec.extractLsb' 0 64
         (BitVec.ofInt 65 ((BitVec.extractLsb 31 0 rs1_val).toInt * (BitVec.extractLsb 31 0 rs2_val).toInt))))
 
+@[simp_riscv]
 def MULW_pure64_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.signExtend 64
     (((BitVec.extractLsb 31 0 rs1_val) * (BitVec.extractLsb 31 0 rs2_val)))
@@ -401,9 +447,11 @@ theorem MULW_pure64_eq_MULW_pure64_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64
  the suffix indicates how the flags are assumed to be set.
 { high := _, signed_rs1:= _, signed_rs2 := _  }
 -/
+@[simp_riscv]
 def MUL_pure64_fff (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.extractLsb 63 0 (BitVec.extractLsb' 0 128 (BitVec.ofInt 129 (rs1_val.toNat * rs2_val.toNat)))
 
+@[simp_riscv]
 def MUL_pure64_fff_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=  rs2_val * rs1_val
 
 theorem MUL_pure64_fff_eq_MUL_pure64_fff_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) :
@@ -423,17 +471,21 @@ theorem MUL_pure64_fff_eq_MUL_pure64_fff_bv (rs2_val : BitVec 64) (rs1_val : Bit
   simp at this
   omega
 
-def  MUL_pure64_fft (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
+@[simp_riscv]
+def MUL_pure64_fft (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.extractLsb 63 0
     (BitVec.extractLsb' 0 128
       (BitVec.ofInt 129 (Int.ofNat (Int.mul (Int.ofNat rs1_val.toNat)  (rs2_val.toInt)).toNat)))
 
+@[simp_riscv]
 def MUL_pure64_ftf (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.extractLsb 63 0 (BitVec.extractLsb' 0 128 (BitVec.ofInt 129 (rs1_val.toInt * rs2_val.toNat)))
 
+@[simp_riscv]
 def MUL_pure64_tff (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.extractLsb 127 64 (BitVec.extractLsb' 0 128 (BitVec.ofInt 129 (rs1_val.toNat * rs2_val.toNat)))
 
+@[simp_riscv]
 def MUL_pure64_tff_bv  (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
    BitVec.extractLsb 127 64 (BitVec.extractLsb' 0 128 ((BitVec.zeroExtend 128 rs1_val)  * (BitVec.zeroExtend 128 rs2_val)))
 
@@ -466,9 +518,11 @@ theorem MUL_pure64_tff_eq_MUL_pure64_tff_bv (rs2_val : BitVec 64) (rs1_val : Bit
   have := @Nat.mul_lt_mul'' _ _ _ _ aa bb
   omega
 
+@[simp_riscv]
 def MUL_pure64_ttf (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.extractLsb 127 64 (BitVec.extractLsb' 0 128 (BitVec.ofInt 129 (rs1_val.toInt * rs2_val.toNat)))
 
+@[simp_riscv]
 def MUL_pure64_ttf_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.extractLsb 127 64 (((BitVec.signExtend 129 rs1_val ) * (BitVec.zeroExtend 129 rs2_val )))
 
@@ -491,12 +545,15 @@ theorem MUL_pure64_ttf_eq_MUL_pure64_ttf_bv (rs2_val : BitVec 64) (rs1_val : Bit
   simp only [BitVec.ofInt_natCast, BitVec.ofNat_toNat]
   rw [extractLsb_setWidth_of_lt (hi := 127) (lo := 64) (v := 128) (x := BitVec.signExtend 129 rs1_val * BitVec.setWidth 129 rs2_val) (by omega) (by omega)]
 
+@[simp_riscv]
 def MUL_pure64_ftt (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   rs2_val * rs1_val
 
+@[simp_riscv]
 def MUL_pure64_ttt (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.extractLsb 127 64 (BitVec.extractLsb' 0 128 (BitVec.ofInt 129 (rs1_val.toInt * rs2_val.toInt)))
 
+@[simp_riscv]
 def MUL_pure64_ttt_bv  (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.extractLsb 127 64 ((BitVec.signExtend 129 rs1_val) * (BitVec.signExtend 129 rs2_val))
 
@@ -519,6 +576,7 @@ theorem MUL_pure64_ttt_eq_MUL_pure64_ttt_bv (rs2_val : BitVec 64) (rs1_val : Bit
   be added in the future. These specific operations were skipped for now, as they
   are not required for the current project (instruction selection).
 -/
+@[simp_riscv]
 def DIVW_pure64_signed (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.signExtend 64
     (BitVec.extractLsb' 0 32
@@ -532,6 +590,7 @@ def DIVW_pure64_signed (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :
           if (BitVec.extractLsb 31 0 rs2_val).toInt = 0 then -1
           else (BitVec.extractLsb 31 0 rs1_val).toInt.tdiv (BitVec.extractLsb 31 0 rs2_val).toInt)))
 
+@[simp_riscv]
 def DIVW_pure64_unsigned (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.signExtend 64
     (BitVec.extractLsb' 0 32
@@ -540,6 +599,7 @@ def DIVW_pure64_unsigned (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64
         else ((rs1_val.toNat : Int) % 4294967296).tdiv
           ((rs2_val.toNat : Int) % 4294967296))))
 
+@[simp_riscv]
 def DIV_pure64_signed (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.extractLsb' 0 64
     (BitVec.ofInt 65
@@ -547,6 +607,7 @@ def DIV_pure64_signed (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
          -(2^63)
       else if rs2_val.toInt = 0 then -1 else rs1_val.toInt.tdiv rs2_val.toInt))
 
+@[simp_riscv]
 def DIV_pure64_signed_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   if rs2_val = 0#64 then
     -1#64
@@ -587,11 +648,13 @@ theorem DIV_pure64_signed_eq_DIV_pure64_signed_bv (rs2_val : BitVec 64) (rs1_val
           case isFalse iF =>
           rfl
 
+@[simp_riscv]
 def DIV_pure64_unsigned (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.extractLsb' 0 64
     (BitVec.ofInt 65
     (if ((rs2_val.toNat):Int) = 0 then -1 else (rs1_val.toNat : Int).tdiv (rs2_val.toNat: Int)))
 
+@[simp_riscv]
 def DIV_pure64_unsigned_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   if rs2_val = 0#64 then -1 else rs1_val.udiv rs2_val
 
@@ -622,41 +685,51 @@ theorem DIV_pure64_unsigned_eq_DIV_pure64_unsigned_bv (rs2_val : BitVec 64) (rs1
         rw [BitVec.toInt_eq_toNat_bmod]
         simp
 
+@[simp_riscv]
 def ITYPE_pure64_RISCV_ADDI (imm : BitVec 12) (rs1_val : BitVec 64) : BitVec 64 :=
   let immext : BitVec 64 := (BitVec.signExtend 64 imm) ;
   BitVec.add rs1_val immext
 
+@[simp_riscv]
 def ITYPE_pure64_RISCV_SLTI (imm : BitVec 12) (rs1_val : BitVec 64) : BitVec 64 :=
   let immext : BitVec 64 := (BitVec.signExtend 64 imm);
   let b := BitVec.slt rs1_val immext;
   BitVec.zeroExtend 64 (BitVec.ofBool b)
 
+@[simp_riscv]
 def ITYPE_pure64_RISCV_SLTIU (imm : BitVec 12) (rs1_val : BitVec 64) : BitVec 64 :=
   let immext : BitVec 64 := (BitVec.signExtend 64 imm);
   let b := BitVec.ult rs1_val immext;
   BitVec.setWidth 64 (BitVec.ofBool b)
 
+@[simp_riscv]
 def ITYPE_pure64_RISCV_ANDI (imm : BitVec 12) (rs1_val : BitVec 64) : BitVec 64 :=
   let immext : BitVec 64 := (BitVec.signExtend 64 imm);
   BitVec.and rs1_val immext
 
+@[simp_riscv]
 def ITYPE_pure64_RISCV_ORI (imm : BitVec 12) (rs1_val : BitVec 64) : BitVec 64 :=
   let immext : BitVec 64 := (BitVec.signExtend 64 imm) ;
   BitVec.or rs1_val immext
 
+@[simp_riscv]
 def ITYPE_pure64_RISCV_XORI (imm : BitVec 12) (rs1_val : BitVec 64) : BitVec 64 :=
   let immext : BitVec 64 := (BitVec.signExtend 64 imm) ;
   BitVec.xor rs1_val immext
 
+@[simp_riscv]
 def ZICOND_RTYPE_pure64_RISCV_CZERO_EQZ (rs2_val : BitVec 64) (rs1_val : BitVec 64) :=
   if rs2_val = BitVec.zero 64 then BitVec.zero 64 else rs1_val
 
+@[simp_riscv]
 def ZICOND_RTYPE_pure64_RISCV_RISCV_CZERO_NEZ (rs2_val : BitVec 64) (rs1_val : BitVec 64) :=
   if rs2_val = BitVec.zero 64 then rs1_val else BitVec.zero 64
 
+@[simp_riscv]
 def ZBS_RTYPE_pure64_RISCV_BCLR (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.and rs1_val (BitVec.not ((BitVec.zeroExtend 64 1#1) <<< (BitVec.extractLsb 5 0 rs2_val)))
 
+@[simp_riscv]
 def ZBS_RTYPE_pure64_RISCV_BCLR_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) :=
   BitVec.and rs1_val (BitVec.not ((BitVec.zeroExtend 64 1#1) <<< (BitVec.extractLsb 5 0 rs2_val)))
 
@@ -665,15 +738,19 @@ theorem ZBS_RTYPE_pure64_RISCV_BCLR_eq_ZBS_RTYPE_pure64_RISCV_BCLR_bv (rs2_val :
   unfold ZBS_RTYPE_pure64_RISCV_BCLR ZBS_RTYPE_pure64_RISCV_BCLR_bv
   bv_normalize
 
+@[simp_riscv]
 def ZBB_EXTOP_pure64_RISCV_SEXTB (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.signExtend 64 (BitVec.extractLsb 7 0 rs1_val)
 
+@[simp_riscv]
 def ZBB_EXTOP_pure64_RISCV_SEXTH (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.signExtend 64 (BitVec.extractLsb 15 0 rs1_val)
 
+@[simp_riscv]
 def ZBB_EXTOP_pure64_RISCV_ZEXTH (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.zeroExtend 64 (BitVec.extractLsb 15 0 rs1_val)
 
+@[simp_riscv]
 def ZBS_RTYPE_pure64_RISCV_BEXT (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.setWidth 64
     (match
@@ -682,6 +759,7 @@ def ZBS_RTYPE_pure64_RISCV_BEXT (rs2_val : BitVec 64) (rs1_val : BitVec 64) : Bi
     | true => 1#1
     | false => 0#1)
 
+@[simp_riscv]
 def ZBS_RTYPE_pure64_RISCV_BEXT_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) :=
   BitVec.setWidth 64
     (match
@@ -695,11 +773,13 @@ theorem ZBS_RTYPE_pure64_RISCV_BEXT_eq_ZBS_RTYPE_pure64_RISCV_BEXT_bv (rs2_val :
   unfold ZBS_RTYPE_pure64_RISCV_BEXT  ZBS_RTYPE_pure64_RISCV_BEXT_bv
   simp
 
+@[simp_riscv]
  def ZBS_RTYPE_pure64_BINV (rs2_val : BitVec 64) (rs1_val : BitVec 64) :=
   BitVec.xor rs1_val
     (BitVec.shiftLeft
       (BitVec.zeroExtend 64 1#1) (BitVec.extractLsb 5 0 rs2_val).toNat)
 
+@[simp_riscv]
  def ZBS_RTYPE_pure64_BINV_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) :=
   BitVec.xor rs1_val ((BitVec.zeroExtend 64 1#1) <<< (BitVec.extractLsb 5 0 rs2_val))
 
@@ -708,10 +788,12 @@ theorem ZBS_RTYPE_pure64_BINV_eq_ZBS_RTYPE_pure64_BINV_bv (rs2_val : BitVec 64)
   unfold ZBS_RTYPE_pure64_BINV ZBS_RTYPE_pure64_BINV_bv
   bv_decide
 
+@[simp_riscv]
 def ZBS_RTYPE_pure64_RISCV_BSET (rs2_val : BitVec 64) (rs1_val : BitVec 64) :=
   BitVec.or rs1_val (BitVec.shiftLeft
     (BitVec.zeroExtend 64 1#1) (BitVec.extractLsb 5 0 rs2_val).toNat)
 
+@[simp_riscv]
 def ZBS_RTYPE_pure64_RISCV_BSET_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) :=
   BitVec.or rs1_val ((BitVec.zeroExtend 64 1#1) <<< (BitVec.extractLsb 5 0 rs2_val))
 
@@ -720,9 +802,11 @@ theorem ZBS_RTYPE_pure64_RISCV_BSET_eq_ZBS_RTYPE_pure64_RISCV_BSET_bv (rs2_val :
   unfold ZBS_RTYPE_pure64_RISCV_BSET ZBS_RTYPE_pure64_RISCV_BSET_bv
   simp
 
+@[simp_riscv]
 def ZBS_IOP_pure64_RISCV_BCLRI (shamt : BitVec 6) (rs1_val : BitVec 64) : BitVec 64 :=
     BitVec.and rs1_val (BitVec.not ((BitVec.setWidth 64 1#1) <<< shamt))
 
+@[simp_riscv]
 def ZBS_IOP_pure64_RISCV_BCLRI_bv (shamt : BitVec 6) (rs1_val : BitVec 64) :=
   BitVec.and rs1_val (BitVec.not ((BitVec.setWidth 64 1#1) <<< shamt))
 
@@ -731,12 +815,14 @@ theorem ZBS_IOP_pure64_RISCV_BCLRI_eq_ZBS_IOP_pure64_RISCV_BCLRI_bv (shamt : Bit
   unfold ZBS_IOP_pure64_RISCV_BCLRI ZBS_IOP_pure64_RISCV_BCLRI_bv
   simp
 
+@[simp_riscv]
 def ZBS_IOP_pure64_RISCV_BEXTI (shamt : BitVec 6) (rs1_val : BitVec 64) :=
   BitVec.setWidth 64
       (match (BitVec.and rs1_val (BitVec.shiftLeft (BitVec.setWidth 64 1#1) shamt.toNat)) != 0#64 with
       | true => 1#1
       | false => 0#1)
 
+@[simp_riscv]
 def ZBS_IOP_pure64_RISCV_BEXTI_bv (shamt : BitVec 6) (rs1_val : BitVec 64) :=
   BitVec.setWidth 64
       (match (BitVec.and rs1_val ( (BitVec.setWidth 64 1#1) <<< shamt)) != 0#64 with
@@ -748,9 +834,11 @@ theorem ZBS_IOP_pure64_RISCV_BEXTI_eq_ZBS_IOP_pure64_RISCV_BEXTI_bv (shamt : Bit
   unfold ZBS_IOP_pure64_RISCV_BEXTI  ZBS_IOP_pure64_RISCV_BEXTI_bv
   simp
 
+@[simp_riscv]
 def ZBS_IOP_pure64_RISCV_BINVI (shamt : BitVec 6) (rs1_val : BitVec 64) :=
   BitVec.xor rs1_val  (BitVec.shiftLeft (BitVec.zeroExtend 64 1#1) shamt.toNat)
 
+@[simp_riscv]
 def ZBS_IOP_pure64_RISCV_BINVI_bv (shamt : BitVec 6) (rs1_val : BitVec 64) :=
   BitVec.xor rs1_val  ((BitVec.zeroExtend 64 1#1) <<< shamt)
 
@@ -759,9 +847,11 @@ theorem ZBS_IOP_pure64_RISCV_BINVI_eq_ZBS_IOP_pure64_RISCV_BINVI_bv (shamt : Bit
   unfold ZBS_IOP_pure64_RISCV_BINVI ZBS_IOP_pure64_RISCV_BINVI_bv
   rfl
 
+@[simp_riscv]
 def ZBS_IOP_pure64_RISCV_BSETI (shamt : BitVec 6) (rs1_val : BitVec 64) :=
   BitVec.or rs1_val (BitVec.shiftLeft (BitVec.zeroExtend 64 1#1) shamt.toNat)
 
+@[simp_riscv]
 def ZBS_IOP_pure64_RISCV_BSETI_bv (shamt : BitVec 6) (rs1_val : BitVec 64) :=
   BitVec.or rs1_val ((BitVec.zeroExtend 64 1#1) <<< shamt)
 
@@ -774,6 +864,7 @@ theorem ZBS_IOP_pure64_RISCV_BSETI_eq_ZBS_IOP_pure64_RISCV_BSETI_bv (shamt : Bit
 bit vector operation semantics. This is because it is not yet clear how such a translation
 into the bit vector domain without toNat and toInts would look like. Additionally there are
 not crucial for our current project. -/
+@[simp_riscv]
 def ZBB_RTYPEW_pure64_RISCV_RORW (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.signExtend (64)
       (BitVec.or (BitVec.ushiftRight (BitVec.setWidth 32 rs1_val) (rs2_val.toNat % 32))
@@ -782,6 +873,7 @@ def ZBB_RTYPEW_pure64_RISCV_RORW (rs2_val : BitVec 64) (rs1_val : BitVec 64) : B
               32 % 2 ^ (5 + 1)) %
             2 ^ 5)))
 
+@[simp_riscv]
 def ZBB_RTYPEW_pure64_RISCV_ROLW (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.signExtend 64
     (BitVec.or (BitVec.shiftLeft (BitVec.setWidth 32 rs1_val) (BitVec.extractLsb 4 0 rs2_val).toNat)
@@ -790,10 +882,12 @@ def ZBB_RTYPEW_pure64_RISCV_ROLW (rs2_val : BitVec 64) (rs1_val : BitVec 64) : B
             (BitVec.ofInt 6 32)))
           (BitVec.extractLsb 4 0 rs2_val)))).toNat))
 
- def ZBB_RTYPE_pure64_RISCV_ROL (rs2_val : BitVec 64) (rs1_val : BitVec 64) :=
+@[simp_riscv]
+  def ZBB_RTYPE_pure64_RISCV_ROL (rs2_val : BitVec 64) (rs1_val : BitVec 64) :=
   BitVec.or (BitVec.shiftLeft rs1_val (BitVec.extractLsb 5 0 rs2_val).toNat)
     (BitVec.ushiftRight rs1_val (BitVec.extractLsb' 0 6 (BitVec.ofInt 7 64) - BitVec.extractLsb 5 0 rs2_val).toNat)
 
+@[simp_riscv]
  def ZBB_RTYPE_pure64_RISCV_ROL_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) :=
   BitVec.or (BitVec.shiftLeft rs1_val (BitVec.extractLsb 5 0 rs2_val).toNat)
     (rs1_val >>> (BitVec.extractLsb' 0 6 (64#7) - BitVec.extractLsb 5 0 rs2_val))
@@ -803,10 +897,12 @@ theorem ZBB_RTYPE_pure64_RISCV_ROL_eq_ZBB_RTYPE_pure64_RISCV_ROL_bv (rs2_val : B
   unfold ZBB_RTYPE_pure64_RISCV_ROL ZBB_RTYPE_pure64_RISCV_ROL_bv
   simp
 
- def ZBB_RTYPE_pure64_RISCV_ROR (rs2_val : BitVec 64) (rs1_val : BitVec 64) :=
+@[simp_riscv]
+def ZBB_RTYPE_pure64_RISCV_ROR (rs2_val : BitVec 64) (rs1_val : BitVec 64) :=
   BitVec.or (BitVec.ushiftRight rs1_val (BitVec.extractLsb 5 0 rs2_val).toNat)
     (BitVec.shiftLeft rs1_val ((BitVec.extractLsb' 0 6 (BitVec.ofInt 7 64) - BitVec.extractLsb 5 0 rs2_val)).toNat)
 
+@[simp_riscv]
  def ZBB_RTYPE_pure64_RISCV_ROR_bv (rs2_val : BitVec 64) (rs1_val : BitVec 64) :=
   BitVec.or ( rs1_val >>> (BitVec.extractLsb 5 0 rs2_val))
     (rs1_val <<< ((BitVec.extractLsb' 0 6 (BitVec.ofInt 7 64) - BitVec.extractLsb 5 0 rs2_val)))
@@ -816,24 +912,31 @@ theorem ZBB_RTYPE_pure64_RISCV_ROR_eq_ZBB_RTYPE_pure64_RISCV_ROR_bv (rs2_val : B
   unfold ZBB_RTYPE_pure64_RISCV_ROR  ZBB_RTYPE_pure64_RISCV_ROR_bv
   simp
 
+@[simp_riscv]
  def ZBA_RTYPEUW_pure64_RISCV_ADDUW (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.zeroExtend 64 (BitVec.extractLsb 31 0 rs1_val) <<< 0#2 + rs2_val
 
+@[simp_riscv]
 def ZBA_RTYPEUW_pure64_RISCV_SH1ADDUW (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.add (BitVec.zeroExtend 64 (BitVec.extractLsb 31 0 rs1_val) <<< 1#2)  rs2_val
 
+@[simp_riscv]
 def ZBA_RTYPEUW_pure64_RISCV_SH2ADDUW (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.add (BitVec.zeroExtend 64 (BitVec.extractLsb 31 0 rs1_val) <<< 2#2) rs2_val
 
+@[simp_riscv]
 def  ZBA_RTYPEUW_pure64_RISCV_SH3ADDUW (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.add (BitVec.zeroExtend 64 (BitVec.extractLsb 31 0 rs1_val) <<< 3#2)  rs2_val
 
+@[simp_riscv]
 def ZBA_RTYPE_pure64_RISCV_SH1ADD (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.add (rs1_val <<< 1#2) rs2_val
 
+@[simp_riscv]
 def ZBA_RTYPE_pure64_RISCV_SH2ADD (rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.add (rs1_val <<< 2#2) rs2_val
 
+@[simp_riscv]
 def ZBA_RTYPE_pure64_RISCV_SH3ADD(rs2_val : BitVec 64) (rs1_val : BitVec 64) : BitVec 64 :=
   BitVec.add (rs1_val <<< 3#2) rs2_val
 
diff --git a/SSA/Projects/RISCV64/Tactic/SimpRiscV.lean b/SSA/Projects/RISCV64/Tactic/SimpRiscV.lean
new file mode 100644
index 0000000000..52dfeebb14
--- /dev/null
+++ b/SSA/Projects/RISCV64/Tactic/SimpRiscV.lean
@@ -0,0 +1,25 @@
+import SSA.Projects.RISCV64.Tactic.SimpRiscVAttr
+import SSA.Projects.InstCombine.ForLean
+import SSA.Projects.InstCombine.LLVM.EDSL
+import Lean.Meta.Tactic.Simp.SimpTheorems
+import Lean.Meta.Tactic.Simp.RegisterCommand
+import Lean.LabelAttribute
+
+
+open Lean
+open Lean.Elab.Tactic
+
+/-!
+This file defines the `simp_riscv` tactic, which unfolds and simplifies the RISC-V semantic definitions.
+It also defines the `simp_riscv` attribute, used to tag semantic definition functions so that
+they are automatically simplified when `simp_riscv` is invoked.
+
+The purpose of this tactic is to reduce proof size when reasoning about instruction lowerings.
+-/
+syntax "simp_riscv" : tactic
+macro "simp_riscv" : tactic =>
+  `(tactic|(
+      simp (config := {failIfUnchanged := false}) only [
+          simp_riscv
+        ]
+    ))
diff --git a/SSA/Projects/RISCV64/Tactic/SimpRiscVAttr.lean b/SSA/Projects/RISCV64/Tactic/SimpRiscVAttr.lean
new file mode 100644
index 0000000000..79c91d0317
--- /dev/null
+++ b/SSA/Projects/RISCV64/Tactic/SimpRiscVAttr.lean
@@ -0,0 +1,6 @@
+/-
+Released under Apache 2.0 license as described in the file LICENSE.
+-/
+import Lean
+
+register_simp_attr simp_riscv


Reviews:
user: login: tobiasgrosser
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-05-22T10:25:06Z
user: login: tobiasgrosser
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-05-22T10:25:32Z
user: login: salinhkuhn
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-05-22T10:51:03Z
user: login: alexkeizer
body: LGTM
state: APPROVED
author_association: COLLABORATOR
submitted_at: 2025-05-22T12:15:21Z
user: login: salinhkuhn
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-05-22T12:25:56Z

Review comments:
diff_hunk: @@ -0,0 +1,35 @@
+import SSA.Projects.LLVMRiscV.SimpRiscVAttr
+import SSA.Projects.InstCombine.ForLean
+import SSA.Projects.InstCombine.LLVM.EDSL
+import Lean.Meta.Tactic.Simp.SimpTheorems
+import Lean.Meta.Tactic.Simp.RegisterCommand
+import Lean.LabelAttribute
+import SSA.Projects.LLVMRiscV.LLVMAndRiscv
+
+open Lean
+open Lean.Elab.Tactic
+open RV64Semantics
+open LLVMRiscV
+
+/-!
+This file defines the `simp_riscv` tactic, which unfolds and simplifies the RISC-V semantic definitions.
+It also defines the `simp_riscv` attribute, used to tag semantic definition functions so that
+they are automatically simplified when `simp_riscv` is invoked.
+
+The purpose of this tactic is to reduce proof size when reasoning about instruction lowerings.
+-/
+
+attribute [simp_riscv]
+ ADDIW_pure64 UTYPE_pure64_lui UTYPE_pure64_AUIPC RTYPE_pure64_RISCV_ADD castriscvToLLVM
+ castLLVMToriscv RTYPE_pure64_RISCV_SRA_bv RTYPE_pure64_RISCV_SUB RTYPE_pure64_RISCV_AND
+ MUL_pure64_ftt RTYPE_pure64_RISCV_OR REM_pure64_signed_bv DIV_pure64_signed_bv
+ RTYPE_pure64_RISCV_SLL_bv RTYPE_pure64_RISCV_SRL_bv RTYPE_pure64_RISCV_SUB
+ DIV_pure64_unsigned_bv REM_pure64_unsigned_bv RTYPE_pure64_RISCV_XOR DIV_pure64_signed_bv
path: SSA/Projects/LLVMRiscV/SimpRiscV.lean
user: login: tobiasgrosser
body: Would it make sense to tag the relevant theorems directly?
created_at: 2025-05-22T10:25:06Z
author_association: COLLABORATOR
diff_hunk: @@ -0,0 +1,35 @@
+import SSA.Projects.LLVMRiscV.SimpRiscVAttr
+import SSA.Projects.InstCombine.ForLean
+import SSA.Projects.InstCombine.LLVM.EDSL
+import Lean.Meta.Tactic.Simp.SimpTheorems
+import Lean.Meta.Tactic.Simp.RegisterCommand
+import Lean.LabelAttribute
+import SSA.Projects.LLVMRiscV.LLVMAndRiscv
+
+open Lean
+open Lean.Elab.Tactic
+open RV64Semantics
+open LLVMRiscV
path: SSA/Projects/LLVMRiscV/SimpRiscV.lean
user: login: tobiasgrosser
body: Is this the minimal set of includes / open statements?
created_at: 2025-05-22T10:25:32Z
author_association: COLLABORATOR
diff_hunk: @@ -0,0 +1,35 @@
+import SSA.Projects.LLVMRiscV.SimpRiscVAttr
+import SSA.Projects.InstCombine.ForLean
+import SSA.Projects.InstCombine.LLVM.EDSL
+import Lean.Meta.Tactic.Simp.SimpTheorems
+import Lean.Meta.Tactic.Simp.RegisterCommand
+import Lean.LabelAttribute
+import SSA.Projects.LLVMRiscV.LLVMAndRiscv
+
+open Lean
+open Lean.Elab.Tactic
+open RV64Semantics
+open LLVMRiscV
+
+/-!
+This file defines the `simp_riscv` tactic, which unfolds and simplifies the RISC-V semantic definitions.
+It also defines the `simp_riscv` attribute, used to tag semantic definition functions so that
+they are automatically simplified when `simp_riscv` is invoked.
+
+The purpose of this tactic is to reduce proof size when reasoning about instruction lowerings.
+-/
+
+attribute [simp_riscv]
+ ADDIW_pure64 UTYPE_pure64_lui UTYPE_pure64_AUIPC RTYPE_pure64_RISCV_ADD castriscvToLLVM
+ castLLVMToriscv RTYPE_pure64_RISCV_SRA_bv RTYPE_pure64_RISCV_SUB RTYPE_pure64_RISCV_AND
+ MUL_pure64_ftt RTYPE_pure64_RISCV_OR REM_pure64_signed_bv DIV_pure64_signed_bv
+ RTYPE_pure64_RISCV_SLL_bv RTYPE_pure64_RISCV_SRL_bv RTYPE_pure64_RISCV_SUB
+ DIV_pure64_unsigned_bv REM_pure64_unsigned_bv RTYPE_pure64_RISCV_XOR DIV_pure64_signed_bv
path: SSA/Projects/LLVMRiscV/SimpRiscV.lean
user: login: salinhkuhn
body: Yes, I can also do it like that and move it entirely to the RiscV dialect folder.
created_at: 2025-05-22T10:51:03Z
author_association: CONTRIBUTOR
diff_hunk: @@ -20,20 +21,24 @@ open BitVec
 -/
 
 namespace RV64Semantics
-
+@[simp_riscv]
path: SSA/Projects/RISCV64/Semantics.lean
user: login: alexkeizer
body: Nit: you might wanna keep that whitespace
created_at: 2025-05-22T12:14:38Z
author_association: COLLABORATOR
diff_hunk: @@ -20,20 +21,24 @@ open BitVec
 -/
 
 namespace RV64Semantics
-
+@[simp_riscv]
path: SSA/Projects/RISCV64/Semantics.lean
user: login: salinhkuhn
body: yes
created_at: 2025-05-22T12:25:56Z
author_association: CONTRIBUTOR

PR comments:
user: login: github-actions[bot]
created_at: 2025-05-22T10:21:52Z
body: Alive Statistics: 90 / 93 (3 failed)
author_association: CONTRIBUTOR
user: login: github-actions[bot]
created_at: 2025-05-22T10:29:21Z
body: bitwuzla proved and leanSAT failed theorem 3 in file gexact_proof.lean
bitwuzla proved and leanSAT failed theorem 3 in file gdivhshift_proof.lean
bitwuzla proved and leanSAT failed theorem 5 in file gdivhshift_proof.lean
bitwuzla proved and leanSAT failed theorem 51 in file gdivhshift_proof.lean
bitwuzla proved and leanSAT failed theorem 53 in file gdivhshift_proof.lean
bitwuzla proved and leanSAT failed theorem 0 in file gsremhcanonicalize_proof.lean
bitwuzla proved and leanSAT failed theorem 3 in file gdistribute_proof.lean
bitwuzla proved and leanSAT failed theorem 4 in file gdistribute_proof.lean
bitwuzla proved and leanSAT failed theorem 9 in file gapinthsub_proof.lean
bitwuzla provided counterexample and leanSAT failed theorem 1 in file gapinthrem2_proof.lean
bitwuzla proved and leanSAT failed theorem 15 in file grem_proof.lean
bitwuzla proved and leanSAT failed theorem 2 in file gsdivhcanonicalize_proof.lean
bitwuzla proved and leanSAT failed theorem 1 in file gadd4_proof.lean
bitwuzla proved and leanSAT failed theorem 0 in file g2008h02h23hMulSub_proof.lean
bitwuzla proved and leanSAT failed theorem 0 in file g2010h11h23hDistributed_proof.lean
bitwuzla provided counterexample and leanSAT failed theorem 3 in file gapinthdiv2_proof.lean
bitwuzla proved and leanSAT failed theorem 14 in file gshlhfactor_proof.lean
bitwuzla proved and leanSAT failed theorem 21 in file greassociatehnuw_proof.lean
bitwuzla proved and leanSAT failed theorem 22 in file greassociatehnuw_proof.lean
bitwuzla proved and leanSAT failed theorem 23 in file greassociatehnuw_proof.lean
bitwuzla proved and leanSAT failed theorem 24 in file greassociatehnuw_proof.lean
bitwuzla proved and leanSAT failed theorem 13 in file gsubhxorhcmp_proof.lean
leanSAT and Bitwuzla solved: 7931
leanSAT and Bitwuzla provided 8 counterexamples
leanSAT and Bitwuzla both failed on 15 theorems
leanSAT failed and Bitwuzla succeeded on 20 theorems
leanSAT succeeded and Bitwuzla failed on 0 theorems
There were 0 inconsistencies
Errors raised: 77
ran rg 'Bitwuzla failed' | wc -l, expected 15, found 0, FAIL
ran rg 'LeanSAT failed' | wc -l, expected 35, found 0, FAIL
ran rg 'LeanSAT provided a counter' | wc -l, expected 8, found 0, FAIL
ran rg 'Bitwuzla provided a counter' | wc -l, expected 8, found 0, FAIL
ran rg 'LeanSAT proved' | wc -l, expected 7931, found 0, FAIL
ran rg 'Bitwuzla proved' | wc -l, expected 7951, found 0, FAIL
error (kernel) deep recursion detected was raised 25 times
error The SAT solver timed out while solving the problem. was raised 37 times
error The SMT solver timed out while solving the problem. was raised 15 times

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created_at: 2025-05-22T12:00:22Z
body: Alive Statistics: 90 / 93 (3 failed)
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created_at: 2025-05-22T12:04:49Z
body: bitwuzla proved and leanSAT failed theorem 3 in file gexact_proof.lean
bitwuzla proved and leanSAT failed theorem 3 in file gdivhshift_proof.lean
bitwuzla proved and leanSAT failed theorem 5 in file gdivhshift_proof.lean
bitwuzla proved and leanSAT failed theorem 51 in file gdivhshift_proof.lean
bitwuzla proved and leanSAT failed theorem 53 in file gdivhshift_proof.lean
bitwuzla proved and leanSAT failed theorem 0 in file gsremhcanonicalize_proof.lean
bitwuzla proved and leanSAT failed theorem 3 in file gdistribute_proof.lean
bitwuzla proved and leanSAT failed theorem 4 in file gdistribute_proof.lean
bitwuzla proved and leanSAT failed theorem 9 in file gapinthsub_proof.lean
bitwuzla provided counterexample and leanSAT failed theorem 1 in file gapinthrem2_proof.lean
bitwuzla proved and leanSAT failed theorem 15 in file grem_proof.lean
bitwuzla proved and leanSAT failed theorem 2 in file gsdivhcanonicalize_proof.lean
bitwuzla proved and leanSAT failed theorem 1 in file gadd4_proof.lean
bitwuzla proved and leanSAT failed theorem 0 in file g2008h02h23hMulSub_proof.lean
bitwuzla proved and leanSAT failed theorem 0 in file g2010h11h23hDistributed_proof.lean
bitwuzla provided counterexample and leanSAT failed theorem 3 in file gapinthdiv2_proof.lean
bitwuzla proved and leanSAT failed theorem 14 in file gshlhfactor_proof.lean
bitwuzla proved and leanSAT failed theorem 21 in file greassociatehnuw_proof.lean
bitwuzla proved and leanSAT failed theorem 22 in file greassociatehnuw_proof.lean
bitwuzla proved and leanSAT failed theorem 23 in file greassociatehnuw_proof.lean
bitwuzla proved and leanSAT failed theorem 24 in file greassociatehnuw_proof.lean
bitwuzla proved and leanSAT failed theorem 13 in file gsubhxorhcmp_proof.lean
leanSAT and Bitwuzla solved: 7931
leanSAT and Bitwuzla provided 8 counterexamples
leanSAT and Bitwuzla both failed on 15 theorems
leanSAT failed and Bitwuzla succeeded on 20 theorems
leanSAT succeeded and Bitwuzla failed on 0 theorems
There were 0 inconsistencies
Errors raised: 77
ran rg 'Bitwuzla failed' | wc -l, expected 15, found 0, FAIL
ran rg 'LeanSAT failed' | wc -l, expected 35, found 0, FAIL
ran rg 'LeanSAT provided a counter' | wc -l, expected 8, found 0, FAIL
ran rg 'Bitwuzla provided a counter' | wc -l, expected 8, found 0, FAIL
ran rg 'LeanSAT proved' | wc -l, expected 7931, found 0, FAIL
ran rg 'Bitwuzla proved' | wc -l, expected 7951, found 0, FAIL
error (kernel) deep recursion detected was raised 25 times
error The SAT solver timed out while solving the problem. was raised 37 times
error The SMT solver timed out while solving the problem. was raised 15 times

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created_at: 2025-05-22T12:32:12Z
body: Alive Statistics: 90 / 93 (3 failed)
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created_at: 2025-05-22T12:44:36Z
body: bitwuzla proved and leanSAT failed theorem 3 in file gexact_proof.lean
bitwuzla proved and leanSAT failed theorem 3 in file gdivhshift_proof.lean
bitwuzla proved and leanSAT failed theorem 5 in file gdivhshift_proof.lean
bitwuzla proved and leanSAT failed theorem 51 in file gdivhshift_proof.lean
bitwuzla proved and leanSAT failed theorem 53 in file gdivhshift_proof.lean
bitwuzla proved and leanSAT failed theorem 3 in file gdistribute_proof.lean
bitwuzla proved and leanSAT failed theorem 4 in file gdistribute_proof.lean
bitwuzla proved and leanSAT failed theorem 9 in file gapinthsub_proof.lean
bitwuzla provided counterexample and leanSAT failed theorem 1 in file gapinthrem2_proof.lean
bitwuzla proved and leanSAT failed theorem 15 in file grem_proof.lean
bitwuzla proved and leanSAT failed theorem 2 in file gsdivhcanonicalize_proof.lean
bitwuzla proved and leanSAT failed theorem 1 in file gadd4_proof.lean
bitwuzla proved and leanSAT failed theorem 0 in file g2008h02h23hMulSub_proof.lean
bitwuzla proved and leanSAT failed theorem 0 in file g2010h11h23hDistributed_proof.lean
bitwuzla provided counterexample and leanSAT failed theorem 3 in file gapinthdiv2_proof.lean
bitwuzla proved and leanSAT failed theorem 14 in file gshlhfactor_proof.lean
bitwuzla proved and leanSAT failed theorem 21 in file greassociatehnuw_proof.lean
bitwuzla proved and leanSAT failed theorem 22 in file greassociatehnuw_proof.lean
bitwuzla proved and leanSAT failed theorem 23 in file greassociatehnuw_proof.lean
bitwuzla proved and leanSAT failed theorem 24 in file greassociatehnuw_proof.lean
bitwuzla proved and leanSAT failed theorem 13 in file gsubhxorhcmp_proof.lean
leanSAT and Bitwuzla solved: 7932
leanSAT and Bitwuzla provided 8 counterexamples
leanSAT and Bitwuzla both failed on 15 theorems
leanSAT failed and Bitwuzla succeeded on 19 theorems
leanSAT succeeded and Bitwuzla failed on 0 theorems
There were 0 inconsistencies
Errors raised: 76
ran rg 'Bitwuzla failed' | wc -l, expected 15, found 0, FAIL
ran rg 'LeanSAT failed' | wc -l, expected 34, found 0, FAIL
ran rg 'LeanSAT provided a counter' | wc -l, expected 8, found 0, FAIL
ran rg 'Bitwuzla provided a counter' | wc -l, expected 8, found 0, FAIL
ran rg 'LeanSAT proved' | wc -l, expected 7932, found 0, FAIL
ran rg 'Bitwuzla proved' | wc -l, expected 7951, found 0, FAIL
error (kernel) deep recursion detected was raised 25 times
error The SAT solver timed out while solving the problem. was raised 36 times
error The SMT solver timed out while solving the problem. was raised 15 times

author_association: CONTRIBUTOR