Repository: tancheng/VectorCGRA
Pull request #141: 133 p0 deprecate systolic array
Author: login: yuqisun
Labels: name: cleanup
Created: 2025-04-23T17:26:47Z | Merged: 2025-05-06T05:52:27Z

Replace `addr/src_cgra/src_tile `of `load_request` with one NoC pkt to reduce the interfaces.

Will clean comments once all good. 
@tancheng , are we going to do same replacement for `store_request`?


Diff:
diff --git a/.github/workflows/python-package.yml b/.github/workflows/python-package.yml
index 55761adb..ee27a892 100644
--- a/.github/workflows/python-package.yml
+++ b/.github/workflows/python-package.yml
@@ -82,3 +82,5 @@ jobs:
         pytest ../multi_cgra/test/MeshMultiCgraRTL_test.py::test_verilog_homo_2x2_4x4 -xvs --test-verilog --dump-vtb --dump-vcd
         # Const Queue
         pytest ../mem/const/test/ConstQueueDynamicRTL_test.py -xvs
+        # Data Mem
+        pytest ../mem/data/test/DataMemWithCrossbarRTL_test.py -xvs --test-verilog --dump-vtb --dump-vcd
diff --git a/cgra/CgraRTL.py b/cgra/CgraRTL.py
index 70e95dc9..e52bfd8a 100644
--- a/cgra/CgraRTL.py
+++ b/cgra/CgraRTL.py
@@ -9,6 +9,7 @@
 from ..controller.ControllerRTL import ControllerRTL
 from ..lib.basic.val_rdy.ifcs import ValRdyRecvIfcRTL as RecvIfcRTL
 from ..lib.basic.val_rdy.ifcs import ValRdySendIfcRTL as SendIfcRTL
+from ..lib.basic.val_rdy.queues import BypassQueueRTL
 from ..lib.opt_type import *
 from ..lib.util.common import *
 from ..mem.data.DataMemWithCrossbarRTL import DataMemWithCrossbarRTL
@@ -26,7 +27,8 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
                 data_mem_size_per_bank, num_banks_per_cgra,
                 num_registers_per_reg_bank, num_ctrl,
                 total_steps, FunctionUnit, FuList, cgra_topology,
-                controller2addr_map, idTo2d_map, preload_data = None):
+                controller2addr_map, idTo2d_map, preload_data = None,
+                is_multi_cgra = True):
 
     # Other topology can simply modify the tiles connections, or
     # leverage the template for modeling.
@@ -38,6 +40,10 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
       s.num_mesh_ports = 8
 
     s.num_tiles = width * height
+    # The left and bottom tiles are connected to the data memory.
+    data_mem_num_rd_tiles = height + width - 1
+    data_mem_num_wr_tiles = height + width - 1
+
     num_cgras = multi_cgra_rows * multi_cgra_columns
     # An additional router for controller to receive CMD_COMPLETE signal from Ring to CPU.
     CtrlRingPos = mk_ring_pos(s.num_tiles + 1)
@@ -78,8 +84,8 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
                                         data_mem_size_global,
                                         data_mem_size_per_bank,
                                         num_banks_per_cgra,
-                                        height + width - 1, # left and bottom connecting to data mem
-                                        height + width - 1,
+                                        data_mem_num_rd_tiles,
+                                        data_mem_num_wr_tiles,
                                         multi_cgra_rows,
                                         multi_cgra_columns,
                                         s.num_tiles,
@@ -108,18 +114,20 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[height + width - 1] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[height + width - 1] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[height + width - 1] //= s.controller.send_to_mem_store_request_data
-    s.data_mem.recv_from_noc_rdata //= s.controller.send_to_tile_load_response_data
+    s.data_mem.recv_from_noc_load_request //= s.controller.send_to_mem_load_request
+    s.data_mem.recv_from_noc_store_request //= s.controller.send_to_mem_store_request
+    s.data_mem.recv_from_noc_load_response_pkt //= s.controller.send_to_tile_load_response
     s.data_mem.send_to_noc_load_request_pkt //= s.controller.recv_from_tile_load_request_pkt
     s.data_mem.send_to_noc_load_response_pkt //= s.controller.recv_from_tile_load_response_pkt
     s.data_mem.send_to_noc_store_pkt //= s.controller.recv_from_tile_store_request_pkt
 
-    s.recv_from_inter_cgra_noc //= s.controller.recv_from_inter_cgra_noc
-    s.send_to_inter_cgra_noc //= s.controller.send_to_inter_cgra_noc
+    if is_multi_cgra:
+      s.recv_from_inter_cgra_noc //= s.controller.recv_from_inter_cgra_noc
+      s.send_to_inter_cgra_noc //= s.controller.send_to_inter_cgra_noc
+    else:
+      s.bypass_queue = BypassQueueRTL(NocPktType, 1)
+      s.bypass_queue.send //= s.controller.recv_from_inter_cgra_noc
+      s.bypass_queue.recv //= s.controller.send_to_inter_cgra_noc
 
     # Connects the ctrl interface between CPU and controller.
     s.recv_from_cpu_pkt //= s.controller.recv_from_cpu_pkt
diff --git a/cgra/CgraTemplateRTL.py b/cgra/CgraTemplateRTL.py
index 6e2fc9db..23984c6a 100644
--- a/cgra/CgraTemplateRTL.py
+++ b/cgra/CgraTemplateRTL.py
@@ -6,17 +6,17 @@
 Author : Cheng Tan
   Date : Dec 30, 2024
 """
-
-from pymtl3 import *
 from ..controller.ControllerRTL import ControllerRTL
 from ..lib.basic.val_rdy.ifcs import ValRdyRecvIfcRTL as RecvIfcRTL
 from ..lib.basic.val_rdy.ifcs import ValRdySendIfcRTL as SendIfcRTL
+from ..lib.basic.val_rdy.queues import BypassQueueRTL
 from ..lib.opt_type import *
 from ..mem.data.DataMemWithCrossbarRTL import DataMemWithCrossbarRTL
 from ..noc.PyOCN.pymtl3_net.ocnlib.ifcs.positions import mk_ring_pos
 from ..noc.PyOCN.pymtl3_net.ringnet.RingNetworkRTL import RingNetworkRTL
 from ..tile.TileRTL import TileRTL
 
+
 class CgraTemplateRTL(Component):
 
   def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
@@ -26,7 +26,8 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
                 num_registers_per_reg_bank, num_ctrl,
                 total_steps, FunctionUnit, FuList, TileList, LinkList,
                 dataSPM, controller2addr_map, idTo2d_map,
-                preload_data = None):
+                preload_data = None,
+                is_multi_cgra = True):
 
     s.num_mesh_ports = 8
     s.num_tiles = len(TileList)
@@ -104,18 +105,20 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[dataSPM.getNumOfValidReadPorts()] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[dataSPM.getNumOfValidWritePorts()] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[dataSPM.getNumOfValidWritePorts()] //= s.controller.send_to_mem_store_request_data
-    s.data_mem.recv_from_noc_rdata //= s.controller.send_to_tile_load_response_data
+    s.data_mem.recv_from_noc_load_request //= s.controller.send_to_mem_load_request
+    s.data_mem.recv_from_noc_store_request //= s.controller.send_to_mem_store_request
+    s.data_mem.recv_from_noc_load_response_pkt //= s.controller.send_to_tile_load_response
     s.data_mem.send_to_noc_load_request_pkt //= s.controller.recv_from_tile_load_request_pkt
     s.data_mem.send_to_noc_load_response_pkt //= s.controller.recv_from_tile_load_response_pkt
     s.data_mem.send_to_noc_store_pkt //= s.controller.recv_from_tile_store_request_pkt
 
-    s.recv_from_inter_cgra_noc //= s.controller.recv_from_inter_cgra_noc
-    s.send_to_inter_cgra_noc //= s.controller.send_to_inter_cgra_noc
+    if is_multi_cgra:
+      s.recv_from_inter_cgra_noc //= s.controller.recv_from_inter_cgra_noc
+      s.send_to_inter_cgra_noc //= s.controller.send_to_inter_cgra_noc
+    else:
+      s.bypass_queue = BypassQueueRTL(NocPktType, 1)
+      s.bypass_queue.send //= s.controller.recv_from_inter_cgra_noc
+      s.bypass_queue.recv //= s.controller.send_to_inter_cgra_noc
 
     # Connects the ctrl interface between CPU and controller.
     s.recv_from_cpu_pkt //= s.controller.recv_from_cpu_pkt
diff --git a/cgra/test/CgraRTL_test.py b/cgra/test/CgraRTL_test.py
index 7ea0fec7..277df11f 100644
--- a/cgra/test/CgraRTL_test.py
+++ b/cgra/test/CgraRTL_test.py
@@ -32,7 +32,6 @@
 from ...fu.vector.VectorMulComboRTL import VectorMulComboRTL
 from ...lib.basic.val_rdy.SinkRTL import SinkRTL as TestSinkRTL
 from ...lib.basic.val_rdy.SourceRTL import SourceRTL as TestSrcRTL
-from ...lib.basic.val_rdy.queues import BypassQueueRTL
 from ...lib.messages import *
 from ...lib.opt_type import *
 
@@ -67,23 +66,14 @@ def construct(s, DUT, FunctionUnit, FuList, DataType, PredicateType,
                 data_mem_size_global, data_mem_size_per_bank,
                 num_banks_per_cgra, num_registers_per_reg_bank,
                 ctrl_steps, ctrl_steps, FunctionUnit,
-                FuList, topology, controller2addr_map, idTo2d_map)
+                FuList, topology, controller2addr_map, idTo2d_map,
+                is_multi_cgra = False)
 
-    # Uses a bypass queue here to enable the verilator simulation.
-    # Without bypass queue, the connection will not be translated and
-    # recognized.
-    s.bypass_queue = BypassQueueRTL(NocPktType, 1)
     cmp_fn = lambda a, b : a.payload.data == b.payload.data and a.payload.cmd == b.payload.cmd
     s.complete_signal_sink_out = TestSinkRTL(CtrlPktType, complete_signal_sink_out, cmp_fn = cmp_fn)
 
     # Connections
     s.dut.cgra_id //= cgra_id
-    # As we always first issue request pkt from CPU to NoC, 
-    # when there is no NoC for single CGRA test, 
-    # we have to connect from_noc and to_noc in testbench.
-    s.dut.send_to_inter_cgra_noc //= s.bypass_queue.recv
-    s.bypass_queue.send //= s.dut.recv_from_inter_cgra_noc
-
     s.complete_signal_sink_out.recv //= s.dut.send_to_cpu_pkt
 
     complete_count_value = \
diff --git a/cgra/test/CgraTemplateRTL_test.py b/cgra/test/CgraTemplateRTL_test.py
index 157896ff..ceec49fa 100644
--- a/cgra/test/CgraTemplateRTL_test.py
+++ b/cgra/test/CgraTemplateRTL_test.py
@@ -29,8 +29,6 @@
 from ...fu.single.ShifterRTL import ShifterRTL
 from ...lib.basic.val_rdy.SinkRTL import SinkRTL as TestSinkRTL
 from ...lib.basic.val_rdy.SourceRTL import SourceRTL as TestSrcRTL
-from ...lib.basic.val_rdy.queues import BypassQueueRTL
-from ...lib.cmd_type import *
 from ...lib.messages import *
 from ...lib.opt_type import *
 from ...lib.util.common import *
@@ -79,20 +77,11 @@ def construct(s, DUT, FunctionUnit, FuList, DataType, PredicateType,
                 num_registers_per_reg_bank,
                 ctrl_steps, ctrl_steps, FunctionUnit, FuList,
                 TileList, LinkList, dataSPM, controller2addr_map,
-                idTo2d_map)
+                idTo2d_map, is_multi_cgra = False)
 
-    # Uses a bypass queue here to enable the verilator simulation.
-    # Without bypass queue, the connection will not be translated and
-    # recognized.
-    s.bypass_queue = BypassQueueRTL(NocPktType, 1)
     # Connections
     s.dut.cgra_id //= cgra_id
     s.src_ctrl_pkt.send //= s.dut.recv_from_cpu_pkt
-    # As we always first issue request pkt from CPU to NoC,
-    # when there is no NoC for single CGRA test,
-    # we have to connect from_noc and to_noc in testbench.
-    s.dut.send_to_inter_cgra_noc //= s.bypass_queue.recv
-    s.bypass_queue.send //= s.dut.recv_from_inter_cgra_noc
     s.complete_signal_sink_out.recv //= s.dut.send_to_cpu_pkt
 
     # Connects memory address upper and lower bound for each CGRA.
diff --git a/controller/ControllerRTL.py b/controller/ControllerRTL.py
index 85acfba1..40cafea1 100644
--- a/controller/ControllerRTL.py
+++ b/controller/ControllerRTL.py
@@ -12,7 +12,6 @@
 from ..lib.basic.val_rdy.ifcs import RecvIfcRTL
 from ..lib.basic.val_rdy.ifcs import SendIfcRTL
 from ..lib.basic.val_rdy.queues import NormalQueueRTL
-from ..lib.cmd_type import *
 from ..lib.messages import *
 from ..lib.opt_type import *
 from ..lib.util.common import *
@@ -59,24 +58,18 @@ def construct(s,
     s.recv_from_tile_load_response_pkt = RecvIfcRTL(InterCgraPktType)
     s.recv_from_tile_store_request_pkt = RecvIfcRTL(InterCgraPktType)
 
-    s.send_to_mem_load_request_addr = SendIfcRTL(DataAddrType)
-    s.send_to_mem_load_request_src_cgra = SendIfcRTL(CgraIdType)
-    s.send_to_mem_load_request_src_tile = SendIfcRTL(TileIdType)
-    s.send_to_tile_load_response_data = SendIfcRTL(DataType)
-    s.send_to_mem_store_request_addr = SendIfcRTL(DataAddrType)
-    s.send_to_mem_store_request_data = SendIfcRTL(DataType)
+    s.send_to_mem_load_request = SendIfcRTL(InterCgraPktType)
+    s.send_to_tile_load_response = SendIfcRTL(InterCgraPktType)
+    s.send_to_mem_store_request = SendIfcRTL(InterCgraPktType)
 
     # Component
     s.recv_from_tile_load_request_pkt_queue = ChannelRTL(InterCgraPktType, latency = 1)
     s.recv_from_tile_load_response_pkt_queue = ChannelRTL(InterCgraPktType, latency = 1)
     s.recv_from_tile_store_request_pkt_queue = ChannelRTL(InterCgraPktType, latency = 1)
 
-    s.send_to_mem_load_request_addr_queue = ChannelRTL(DataAddrType, latency = 1)
-    s.send_to_mem_load_request_src_cgra_queue = ChannelRTL(CgraIdType, latency = 1)
-    s.send_to_mem_load_request_src_tile_queue = ChannelRTL(TileIdType, latency = 1)
-    s.send_to_tile_load_response_data_queue = ChannelRTL(DataType, latency = 1)
-    s.send_to_mem_store_request_addr_queue = ChannelRTL(DataAddrType, latency = 1)
-    s.send_to_mem_store_request_data_queue = ChannelRTL(DataType, latency = 1)
+    s.send_to_mem_load_request_queue = ChannelRTL(InterCgraPktType, latency = 1)
+    s.send_to_tile_load_response_queue = ChannelRTL(InterCgraPktType, latency = 1)
+    s.send_to_mem_store_request_queue = ChannelRTL(InterCgraPktType, latency = 1)
 
     # Crossbar with 4 inports (load and store requests towards remote
     # memory, load response from local memory, ctrl&data packet from cpu,
@@ -118,12 +111,9 @@ def construct(s,
     s.recv_from_tile_store_request_pkt_queue.recv //= s.recv_from_tile_store_request_pkt
 
     # Requests towards local from others, 1 cycle delay to improve timing.
-    s.send_to_mem_load_request_addr_queue.send //= s.send_to_mem_load_request_addr
-    s.send_to_mem_load_request_src_cgra_queue.send //= s.send_to_mem_load_request_src_cgra
-    s.send_to_mem_load_request_src_tile_queue.send //= s.send_to_mem_load_request_src_tile
-    s.send_to_tile_load_response_data_queue.send //= s.send_to_tile_load_response_data
-    s.send_to_mem_store_request_addr_queue.send //= s.send_to_mem_store_request_addr
-    s.send_to_mem_store_request_data_queue.send //= s.send_to_mem_store_request_data
+    s.send_to_mem_load_request_queue.send //= s.send_to_mem_load_request
+    s.send_to_tile_load_response_queue.send //= s.send_to_tile_load_response
+    s.send_to_mem_store_request_queue.send //= s.send_to_mem_store_request
 
     # For control signals delivery from CPU to tiles.
     s.recv_from_cpu_pkt //= s.recv_from_cpu_pkt_queue.recv
@@ -205,18 +195,14 @@ def update_received_msg():
     # def update_received_msg_from_noc():
 
       # Initiates the signals.
-      s.send_to_mem_load_request_addr_queue.recv.val @= 0
-      s.send_to_mem_load_request_src_cgra_queue.recv.val @= 0
-      s.send_to_mem_load_request_src_tile_queue.recv.val @= 0
-      s.send_to_mem_store_request_addr_queue.recv.val @= 0
-      s.send_to_mem_store_request_data_queue.recv.val @= 0
-      s.send_to_tile_load_response_data_queue.recv.val @= 0
-      s.send_to_mem_load_request_addr_queue.recv.msg @= DataAddrType()
-      s.send_to_mem_load_request_src_cgra_queue.recv.msg @= CgraIdType()
-      s.send_to_mem_load_request_src_tile_queue.recv.msg @= TileIdType()
-      s.send_to_mem_store_request_addr_queue.recv.msg @= DataAddrType()
-      s.send_to_mem_store_request_data_queue.recv.msg @= DataType()
-      s.send_to_tile_load_response_data_queue.recv.msg @= DataType()
+      s.send_to_mem_load_request_queue.recv.val @= 0
+      s.send_to_mem_store_request_queue.recv.val @= 0
+      s.send_to_tile_load_response_queue.recv.val @= 0
+
+      s.send_to_mem_load_request_queue.recv.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
+      s.send_to_mem_store_request_queue.recv.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
+      s.send_to_tile_load_response_queue.recv.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
+
       s.recv_from_inter_cgra_noc.rdy @= 0
       s.send_to_ctrl_ring_pkt.val @= 0
       s.send_to_ctrl_ring_pkt.msg @= IntraCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
@@ -225,26 +211,17 @@ def update_received_msg():
       received_pkt = s.recv_from_inter_cgra_noc.msg
       if s.recv_from_inter_cgra_noc.val:
         if s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_LOAD_REQUEST:
-          s.send_to_mem_load_request_addr_queue.recv.val @= 1
-          s.send_to_mem_load_request_src_cgra_queue.recv.val @= 1
-          s.send_to_mem_load_request_src_tile_queue.recv.val @= 1
+          s.send_to_mem_load_request_queue.recv.val @= 1
 
-          if s.send_to_mem_load_request_addr_queue.recv.rdy:
+          if s.send_to_mem_load_request_queue.recv.rdy:
             s.recv_from_inter_cgra_noc.rdy @= 1
-            s.send_to_mem_load_request_addr_queue.recv.msg @= DataAddrType(received_pkt.payload.data_addr)
-            s.send_to_mem_load_request_src_cgra_queue.recv.msg @= received_pkt.src
-            # FIXME: We can avoid this by sending the entire payload to data memory,
-            # https://github.com/tancheng/VectorCGRA/issues/117.
-            s.send_to_mem_load_request_src_tile_queue.recv.msg @= received_pkt.src_tile_id
+            s.send_to_mem_load_request_queue.recv.msg @= received_pkt
 
         elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_STORE_REQUEST:
-          s.send_to_mem_store_request_data_queue.recv.msg @= received_pkt.payload.data
-          s.send_to_mem_store_request_addr_queue.recv.msg @= received_pkt.payload.data_addr
-          s.send_to_mem_store_request_addr_queue.recv.val @= 1
-          s.send_to_mem_store_request_data_queue.recv.val @= 1
+          s.send_to_mem_store_request_queue.recv.msg @= received_pkt
+          s.send_to_mem_store_request_queue.recv.val @= 1
 
-          if s.send_to_mem_store_request_addr_queue.recv.rdy & \
-             s.send_to_mem_store_request_data_queue.recv.rdy:
+          if s.send_to_mem_store_request_queue.recv.rdy:
             s.recv_from_inter_cgra_noc.rdy @= 1
 
         elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_LOAD_RESPONSE:
@@ -269,9 +246,9 @@ def update_received_msg():
                                  s.recv_from_inter_cgra_noc.msg.payload)
 
           else:
-            s.recv_from_inter_cgra_noc.rdy @= s.send_to_tile_load_response_data_queue.recv.rdy
-            s.send_to_tile_load_response_data_queue.recv.msg @= received_pkt.payload.data
-            s.send_to_tile_load_response_data_queue.recv.val @= 1
+            s.recv_from_inter_cgra_noc.rdy @= s.send_to_tile_load_response_queue.recv.rdy
+            s.send_to_tile_load_response_queue.recv.msg @= received_pkt
+            s.send_to_tile_load_response_queue.recv.val @= 1
 
         elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_COMPLETE:
           s.recv_from_inter_cgra_noc.rdy @= s.send_to_cpu_pkt_queue.recv.rdy
@@ -337,9 +314,8 @@ def line_trace(s):
     recv_from_tile_load_response_pkt_str = "recv_from_tile_load_response_pkt: " + str(s.recv_from_tile_load_response_pkt.msg)
     recv_from_tile_store_request_pkt_str = "recv_from_tile_store_request_pkt: " + str(s.recv_from_tile_store_request_pkt.msg)
     crossbar_str = "crossbar: {" + s.crossbar.line_trace() + "}"
-    send_to_mem_load_request_addr_str = "send_to_mem_load_request_addr: " + str(s.send_to_mem_load_request_addr.msg)
-    send_to_mem_store_request_addr_str = "send_to_mem_store_request_addr: " + str(s.send_to_mem_store_request_addr.msg)
-    send_to_mem_store_request_data_str = "send_to_mem_store_request_data: " + str(s.send_to_mem_store_request_data.msg)
+    send_to_mem_load_request_str = "send_to_mem_load_request: " + str(s.send_to_mem_load_request.msg)
+    send_to_mem_store_request_str = "send_to_mem_store_request: " + str(s.send_to_mem_store_request.msg)
     recv_from_noc_str ="recv_from_noc_pkt.val: " + str(s.recv_from_inter_cgra_noc.val) + " recv_from_noc_pkt.msg: " + str(s.recv_from_inter_cgra_noc.msg) + " recv_from_noc_pkt.rdy: " + str(s.recv_from_inter_cgra_noc.rdy)
     send_to_noc_str = "send_to_noc_pkt: " + str(s.send_to_inter_cgra_noc.msg) + "; rdy: " + str(s.send_to_inter_cgra_noc.rdy) + "; val: " + str(s.send_to_inter_cgra_noc.val)
-    return f'{recv_from_cpu_pkt_str} || {recv_from_cpu_pkt_queue_str} || {crossbar_recv_str} ||  {send_to_ctrl_ring_pkt_str} || {recv_from_tile_load_request_pkt_str} || {recv_from_tile_load_response_pkt_str} || {recv_from_tile_store_request_pkt_str} || {crossbar_str} || {send_to_mem_load_request_addr_str} || {send_to_mem_store_request_addr_str} || {send_to_mem_store_request_data_str} || {recv_from_noc_str} || {send_to_noc_str}\n'
+    return f'{recv_from_cpu_pkt_str} || {recv_from_cpu_pkt_queue_str} || {crossbar_recv_str} ||  {send_to_ctrl_ring_pkt_str} || {recv_from_tile_load_request_pkt_str} || {recv_from_tile_load_response_pkt_str} || {recv_from_tile_store_request_pkt_str} || {crossbar_str} || {send_to_mem_load_request_str} || {send_to_mem_store_request_str} || {recv_from_noc_str} || {send_to_noc_str}\n'
diff --git a/controller/test/ControllerRTL_test.py b/controller/test/ControllerRTL_test.py
index 0b8bddd4..900bf71f 100644
--- a/controller/test/ControllerRTL_test.py
+++ b/controller/test/ControllerRTL_test.py
@@ -13,10 +13,9 @@
 from ..ControllerRTL import ControllerRTL
 from ...lib.basic.val_rdy.SinkRTL import SinkRTL as TestSinkRTL
 from ...lib.basic.val_rdy.SourceRTL import SourceRTL as TestSrcRTL
-from ...lib.cmd_type import *
 from ...lib.messages import *
 from ...lib.opt_type import *
-from ...noc.PyOCN.pymtl3_net.ocnlib.test.stream_sinks import NetSinkRTL as TestNetSinkRTL
+
 
 #-------------------------------------------------------------------------
 # TestHarness
@@ -34,10 +33,9 @@ def construct(s,
                 from_tile_load_request_pkt_msgs,
                 from_tile_load_response_pkt_msgs,
                 from_tile_store_request_pkt_msgs,
-                expected_to_mem_load_request_addr_msgs,
-                expected_to_mem_load_response_data_msgs,
-                expected_to_mem_store_request_addr_msgs,
-                expected_to_mem_store_request_data_msgs,
+                expected_to_mem_load_request_msgs,
+                expected_to_mem_load_response,
+                expected_to_mem_store_request_msgs,
                 from_noc_pkts,
                 expected_to_noc_pkts,
                 controller2addr_map,
@@ -45,17 +43,17 @@ def construct(s,
                 num_cgras,
                 num_tiles):
 
-    s.src_from_tile_load_request_pkt_en_rdy = TestSrcRTL(PktType, from_tile_load_request_pkt_msgs)
-    s.src_from_tile_load_response_pkt_en_rdy = TestSrcRTL(PktType, from_tile_load_response_pkt_msgs)
-    s.src_from_tile_store_request_pkt_en_rdy = TestSrcRTL(PktType, from_tile_store_request_pkt_msgs)
+    s.src_from_tile_load_request_pkt = TestSrcRTL(PktType, from_tile_load_request_pkt_msgs)
+    s.src_from_tile_load_response_pkt = TestSrcRTL(PktType, from_tile_load_response_pkt_msgs)
+    s.src_from_tile_store_request_pkt = TestSrcRTL(PktType, from_tile_store_request_pkt_msgs)
 
-    s.sink_to_mem_load_request_addr_en_rdy = TestSinkRTL(AddrType, expected_to_mem_load_request_addr_msgs)
-    s.sink_to_mem_load_response_data_en_rdy = TestSinkRTL(MsgType, expected_to_mem_load_response_data_msgs)
-    s.sink_to_mem_store_request_addr_en_rdy = TestSinkRTL(AddrType, expected_to_mem_store_request_addr_msgs)
-    s.sink_to_mem_store_request_data_en_rdy = TestSinkRTL(MsgType, expected_to_mem_store_request_data_msgs)
+    cmp_fn = lambda a, b : a.payload.data == b.payload.data and a.payload.cmd == b.payload.cmd
+    s.sink_to_mem_load_request = TestSinkRTL(PktType, expected_to_mem_load_request_msgs, cmp_fn = cmp_fn)
+    s.sink_to_mem_load_response = TestSinkRTL(PktType, expected_to_mem_load_response, cmp_fn = cmp_fn)
+    s.sink_to_mem_store_request = TestSinkRTL(PktType, expected_to_mem_store_request_msgs, cmp_fn = cmp_fn)
 
-    s.src_from_noc_val_rdy = TestSrcRTL(PktType, from_noc_pkts)
-    s.sink_to_noc_val_rdy = TestSinkRTL(PktType, expected_to_noc_pkts)
+    s.src_from_noc = TestSrcRTL(PktType, from_noc_pkts)
+    s.sink_to_noc = TestSinkRTL(PktType, expected_to_noc_pkts)
 
     s.dut = ControllerRTL(ControllerIdType,
                           CpuPktType,
@@ -70,19 +68,16 @@ def construct(s,
 
     # Connections
     s.dut.cgra_id //= cgra_id
-    s.src_from_tile_load_request_pkt_en_rdy.send //= s.dut.recv_from_tile_load_request_pkt
-    s.src_from_tile_load_response_pkt_en_rdy.send //= s.dut.recv_from_tile_load_response_pkt
-    s.src_from_tile_store_request_pkt_en_rdy.send //= s.dut.recv_from_tile_store_request_pkt
+    s.src_from_tile_load_request_pkt.send //= s.dut.recv_from_tile_load_request_pkt
+    s.src_from_tile_load_response_pkt.send //= s.dut.recv_from_tile_load_response_pkt
+    s.src_from_tile_store_request_pkt.send //= s.dut.recv_from_tile_store_request_pkt
 
-    s.dut.send_to_mem_store_request_addr //= s.sink_to_mem_store_request_addr_en_rdy.recv
-    s.dut.send_to_mem_store_request_data //= s.sink_to_mem_store_request_data_en_rdy.recv
-    s.dut.send_to_tile_load_response_data //= s.sink_to_mem_load_response_data_en_rdy.recv
-    s.dut.send_to_mem_load_request_addr  //= s.sink_to_mem_load_request_addr_en_rdy.recv
-    s.dut.send_to_mem_load_request_src_cgra.rdy //= 1
-    s.dut.send_to_mem_load_request_src_tile.rdy //= 1
+    s.dut.send_to_mem_store_request //= s.sink_to_mem_store_request.recv
+    s.dut.send_to_tile_load_response //= s.sink_to_mem_load_response.recv
+    s.dut.send_to_mem_load_request //= s.sink_to_mem_load_request.recv
 
-    s.src_from_noc_val_rdy.send //= s.dut.recv_from_inter_cgra_noc
-    s.dut.send_to_inter_cgra_noc //= s.sink_to_noc_val_rdy.recv
+    s.src_from_noc.send //= s.dut.recv_from_inter_cgra_noc
+    s.dut.send_to_inter_cgra_noc //= s.sink_to_noc.recv
 
     s.dut.recv_from_cpu_pkt.val //= 0
     s.dut.recv_from_cpu_pkt.msg //= CpuPktType()
@@ -92,15 +87,14 @@ def construct(s,
     s.dut.recv_from_ctrl_ring_pkt.msg //= CpuPktType()
 
   def done(s):
-    return s.src_from_tile_load_request_pkt_en_rdy.done()  and \
-           s.src_from_tile_load_response_pkt_en_rdy.done() and \
-           s.src_from_tile_store_request_pkt_en_rdy.done() and \
-           s.sink_to_mem_load_request_addr_en_rdy.done()  and \
-           s.sink_to_mem_load_response_data_en_rdy.done() and \
-           s.sink_to_mem_store_request_addr_en_rdy.done() and \
-           s.sink_to_mem_store_request_data_en_rdy.done() and \
-           s.src_from_noc_val_rdy.done() and \
-           s.sink_to_noc_val_rdy.done()
+    return s.src_from_tile_load_request_pkt.done()  and \
+           s.src_from_tile_load_response_pkt.done() and \
+           s.src_from_tile_store_request_pkt.done() and \
+           s.sink_to_mem_load_request.done()  and \
+           s.sink_to_mem_load_response.done() and \
+           s.sink_to_mem_store_request.done() and \
+           s.src_from_noc.done() and \
+           s.sink_to_noc.done()
 
   def line_trace(s):
     return s.dut.line_trace()
@@ -226,11 +220,14 @@ def mk_src_pkts(num_cgras, lst):
     InterCgraPktType(payload = CgraPayloadType(cmd = CMD_STORE_REQUEST, data = DataType(150, 1), data_addr = 15)),
 ]
 
-expected_to_mem_load_request_addr_msgs =  [DataAddrType(2)]
+expected_to_mem_load_request_msgs =  [InterCgraPktType(payload = CgraPayloadType(cmd = CMD_LOAD_REQUEST,  data = DataType(0,  1), data_addr = 2))]
+
 expected_to_mem_load_response_addr_msgs = [DataAddrType(8), DataAddrType(9)]
-expected_to_mem_load_response_data_msgs = [DataType(80, 1), DataType(90, 1)]
-expected_to_mem_store_request_addr_msgs = [DataAddrType(5)]
-expected_to_mem_store_request_data_msgs = [DataType(50, 1)]
+expected_to_mem_load_response = [
+    InterCgraPktType(0,   0,  0,    0,    0,    0,    0,       0,       0,  0, CgraPayloadType(CMD_LOAD_RESPONSE, DataType(80, 1), data_addr = 8)),
+    InterCgraPktType(0,   0,  0,    0,    0,    0,    0,       0,       0,  0, CgraPayloadType(CMD_LOAD_RESPONSE, DataType(90, 1), data_addr = 9))
+]
+expected_to_mem_store_request_msgs =  [InterCgraPktType(payload = CgraPayloadType(cmd = CMD_STORE_REQUEST,  data = DataType(50,  1), data_addr = 5))]
 
 from_noc_pkts = [
                    # src  dst src_x src_y dst_x dst_y src_tile dst_tile opq vc                 cmd
@@ -267,10 +264,9 @@ def test_simple(cmdline_opts):
                    from_tile_load_request_pkts,
                    from_tile_load_response_pkts,
                    from_tile_store_request_pkts,
-                   expected_to_mem_load_request_addr_msgs,
-                   expected_to_mem_load_response_data_msgs,
-                   expected_to_mem_store_request_addr_msgs,
-                   expected_to_mem_store_request_data_msgs,
+                   expected_to_mem_load_request_msgs,
+                   expected_to_mem_load_response,
+                   expected_to_mem_store_request_msgs,
                    from_noc_pkts,
                    expected_to_noc_pkts,
                    controller2addr_map,
diff --git a/mem/data/DataMemWithCrossbarRTL.py b/mem/data/DataMemWithCrossbarRTL.py
index 22c63fee..29660131 100644
--- a/mem/data/DataMemWithCrossbarRTL.py
+++ b/mem/data/DataMemWithCrossbarRTL.py
@@ -26,15 +26,14 @@
   Date : Dec 5, 2024
 """
 
-from pymtl3 import *
 from pymtl3.stdlib.primitive import RegisterFile
-from ...noc.PyOCN.pymtl3_net.xbar.XbarBypassQueueRTL import XbarBypassQueueRTL
+
 from ...lib.basic.val_rdy.ifcs import ValRdyRecvIfcRTL as RecvIfcRTL
 from ...lib.basic.val_rdy.ifcs import ValRdySendIfcRTL as SendIfcRTL
 from ...lib.basic.val_rdy.queues import BypassQueueRTL
-from ...lib.cmd_type import *
-from ...lib.opt_type import *
 from ...lib.messages import *
+from ...noc.PyOCN.pymtl3_net.xbar.XbarBypassQueueRTL import XbarBypassQueueRTL
+
 
 class DataMemWithCrossbarRTL(Component):
 
@@ -88,21 +87,24 @@ def construct(s,
                               num_cgras,
                               num_tiles)
 
+
     # Interface
+    # [num_rd_tiles] indicates the request from the NoC. ---> Add separate recv port for NoC.
+    s.recv_from_noc_load_request = RecvIfcRTL(NocPktType)
+    s.recv_from_noc_store_request = RecvIfcRTL(NocPktType)
+
     # [0, ..., num_rd_tiles - 1] indicate the requests from/to the tiles,
-    # [num_rd_tiles] indicates the request from the NoC.
-    s.recv_raddr = [RecvIfcRTL(AddrType) for _ in range(num_xbar_in_rd_ports)]
-    s.recv_waddr = [RecvIfcRTL(AddrType) for _ in range(num_xbar_in_wr_ports)]
-    s.recv_wdata = [RecvIfcRTL(DataType) for _ in range(num_xbar_in_wr_ports)]
-    s.send_rdata = [SendIfcRTL(DataType) for _ in range(num_rd_tiles)]
+    s.recv_raddr = [RecvIfcRTL(AddrType) for _ in range(num_rd_tiles)]
+    s.recv_waddr = [RecvIfcRTL(AddrType) for _ in range(num_wr_tiles)]
+    s.recv_wdata = [RecvIfcRTL(DataType) for _ in range(num_wr_tiles)]
 
-    s.recv_from_noc_load_src_cgra = RecvIfcRTL(mk_bits(max(1, clog2(num_cgras))))
-    s.recv_from_noc_load_src_tile = RecvIfcRTL(mk_bits(clog2(num_tiles + 1)))
+
+    s.send_rdata = [SendIfcRTL(DataType) for _ in range(num_rd_tiles)]
 
     s.send_to_noc_load_response_pkt = SendIfcRTL(NocPktType)
 
     # Response that is from a remote SRAM.
-    s.recv_from_noc_rdata = RecvIfcRTL(DataType)
+    s.recv_from_noc_load_response_pkt = RecvIfcRTL(NocPktType)
 
     # Requests that targets remote SRAMs.
     s.send_to_noc_load_request_pkt = SendIfcRTL(NocPktType)
@@ -173,30 +175,55 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
-          # Calculates the target bank index.
-          if (s.recv_raddr[i].msg >= s.address_lower) & (s.recv_raddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_raddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
-          else:
-            bank_index = XbarOutRdType(num_banks_per_cgra)
-          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, s.recv_raddr[i].msg, 0, 0)
         for i in range(num_rd_tiles):
-          s.rd_pkt[i].src_cgra @= s.cgra_id
+          recv_raddr = s.recv_raddr[i].msg
+          # Calculates the target bank index for load.
+          if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
+            bank_index_load_local = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+          else:
+            bank_index_load_local = XbarOutRdType(num_banks_per_cgra)
           # FIXME: change to exact tile id.
-          s.rd_pkt[i].src_tile @= 0 # i * (num_tiles // num_rd_tiles)
-        s.rd_pkt[num_rd_tiles].src_cgra @= s.recv_from_noc_load_src_cgra.msg
-        s.rd_pkt[num_rd_tiles].src_tile @= s.recv_from_noc_load_src_tile.msg
-
-
-        for i in range(num_xbar_in_wr_ports):
-          # Calculates the target bank index.
-          if (s.recv_waddr[i].msg >= s.address_lower) & (s.recv_waddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_waddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutWrType)
+          s.rd_pkt[i] @= TileSramXbarRdPktType(i,                       # src
+                                               bank_index_load_local,   # dst
+                                               recv_raddr,              # addr
+                                               s.cgra_id,               # src_cgra
+                                               0)                       # src_tile
+
+        recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr
+        # Calculates the target bank index.
+        if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper):
+          bank_index_load_from_noc = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+        else:
+          bank_index_load_from_noc = XbarOutRdType(num_banks_per_cgra)
+        s.rd_pkt[num_rd_tiles] @= TileSramXbarRdPktType(num_rd_tiles,                                   # src
+                                                        bank_index_load_from_noc,                       # dst
+                                                        recv_raddr_from_noc,                            # addr
+                                                        s.recv_from_noc_load_request.msg.src,           # src_cgra
+                                                        s.recv_from_noc_load_request.msg.src_tile_id)   # src_tile
+
+        for i in range(num_wr_tiles):
+          recv_waddr = s.recv_waddr[i].msg
+          # Calculates the target bank index for store.
+          if (recv_waddr >= s.address_lower) & (recv_waddr <= s.address_upper):
+            bank_index_store_local = trunc((recv_waddr - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType)
           else:
-            bank_index = XbarOutWrType(num_banks_per_cgra)
-          s.wr_pkt[i] @= TileSramXbarWrPktType(i, bank_index, s.recv_waddr[i].msg, 0, 0)
+            bank_index_store_local = XbarOutWrType(num_banks_per_cgra)
+          s.wr_pkt[i] @= TileSramXbarWrPktType(i,                       # src
+                                               bank_index_store_local,  # dst
+                                               recv_waddr,              # addr
+                                               0,                       # src_cgra
+                                               0)                       # src_tile
+
+        recv_waddr_from_noc = s.recv_from_noc_store_request.msg.payload.data_addr
+        if (recv_waddr_from_noc >= s.address_lower) & (recv_waddr_from_noc <= s.address_upper):
+          bank_index_store_from_noc = trunc((recv_waddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType)
+        else:
+          bank_index_store_from_noc = XbarOutWrType(num_banks_per_cgra)
+        s.wr_pkt[num_wr_tiles] @= TileSramXbarWrPktType(num_wr_tiles,               # src
+                                                        bank_index_store_from_noc,  # dst
+                                                        recv_waddr_from_noc,        # addr
+                                                        0,                          # src_cgra
+                                                        0)                          # src_tile
 
 
     # Connects xbar with the sram.
@@ -204,12 +231,15 @@ def assemble_xbar_pkt():
     def update_all():
 
       # Initializes the signals.
-      for i in range(num_xbar_in_rd_ports):
-        s.recv_raddr[i].rdy @= 0
-        s.recv_from_noc_load_src_cgra.rdy @= 0
-        s.recv_from_noc_load_src_tile.rdy @= 0
+      for i in range(num_rd_tiles):
+          s.recv_raddr[i].rdy @= 0
+      s.recv_from_noc_load_request.rdy @= 0
+
+      for i in range(num_wr_tiles):
         s.recv_waddr[i].rdy @= 0
         s.recv_wdata_bypass_q[i].send.rdy @= 0
+      s.recv_from_noc_store_request.rdy @= 0
+      s.recv_wdata_bypass_q[num_wr_tiles].send.rdy @= 0
 
       for i in range(num_rd_tiles):
         s.send_rdata[i].val @= 0
@@ -230,10 +260,12 @@ def update_all():
                      CgraPayloadType(0, 0, 0, 0, 0))
 
 
-      for i in range(num_xbar_in_wr_ports):
+      for i in range(num_wr_tiles):
         s.recv_wdata[i].rdy @= 0
         s.recv_wdata_bypass_q[i].recv.val @= 0
         s.recv_wdata_bypass_q[i].recv.msg @= DataType()
+      s.recv_wdata_bypass_q[num_wr_tiles].recv.val @= 0
+      s.recv_wdata_bypass_q[num_wr_tiles].recv.msg @= DataType()
 
       s.send_to_noc_store_pkt.msg @= \
           NocPktType(0, # src
@@ -254,7 +286,7 @@ def update_all():
         s.read_crossbar.recv[i].val @= 0
         s.read_crossbar.recv[i].msg @= TileSramXbarRdPktType(0, 0, 0, 0, 0)
 
-      s.recv_from_noc_rdata.rdy @= 0
+      s.recv_from_noc_load_response_pkt.rdy @= 0
 
       for i in range(num_xbar_in_wr_ports):
         s.write_crossbar.recv[i].val @= 0
@@ -291,22 +323,29 @@ def update_all():
           s.reg_file[b].wen[0] @= b1(1)
 
       else:
-        for i in range(num_xbar_in_wr_ports):
+        for i in range(num_wr_tiles):
           s.recv_wdata[i].rdy @= s.recv_wdata_bypass_q[i].recv.rdy
           s.recv_wdata_bypass_q[i].recv.val @= s.recv_wdata[i].val
           s.recv_wdata_bypass_q[i].recv.msg @= s.recv_wdata[i].msg
+        s.recv_from_noc_store_request.rdy @= s.recv_wdata_bypass_q[num_wr_tiles].recv.rdy
+        s.recv_wdata_bypass_q[num_wr_tiles].recv.val @= s.recv_from_noc_store_request.val
+        s.recv_wdata_bypass_q[num_wr_tiles].recv.msg @= s.recv_from_noc_store_request.msg.payload.data
 
-        for i in range(num_xbar_in_rd_ports):
-          s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
-          s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
-          s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
-        s.recv_from_noc_load_src_cgra.rdy @= s.read_crossbar.recv[-1].rdy
-        s.recv_from_noc_load_src_tile.rdy @= s.read_crossbar.recv[-1].rdy
-  
-        for i in range(num_xbar_in_wr_ports):
+        for i in range(num_rd_tiles):
+            s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
+            s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
+            s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
+        s.read_crossbar.recv[num_rd_tiles].val @= s.recv_from_noc_load_request.val
+        s.read_crossbar.recv[num_rd_tiles].msg @= s.rd_pkt[num_rd_tiles]
+        s.recv_from_noc_load_request.rdy @= s.read_crossbar.recv[num_rd_tiles].rdy
+
+        for i in range(num_wr_tiles):
           s.write_crossbar.recv[i].val @= s.recv_waddr[i].val
           s.write_crossbar.recv[i].msg @= s.wr_pkt[i]
           s.recv_waddr[i].rdy @= s.write_crossbar.recv[i].rdy
+        s.write_crossbar.recv[num_wr_tiles].val @= s.recv_from_noc_store_request.val
+        s.write_crossbar.recv[num_wr_tiles].msg @= s.wr_pkt[num_wr_tiles]
+        s.recv_from_noc_store_request.rdy @= s.write_crossbar.recv[num_wr_tiles].rdy
 
         # Connects the read ports towards SRAM and NoC from the xbar.
         for b in range(num_banks_per_cgra):
@@ -316,7 +355,7 @@ def update_all():
         for i in range(num_xbar_in_rd_ports):
           if (s.read_crossbar.send[s.read_crossbar.packet_on_input_units[i].dst].msg.src == i) & \
              (s.read_crossbar.packet_on_input_units[i].dst < num_banks_per_cgra):
-            if i < s.num_rd_tiles:
+            if i < num_rd_tiles:
               s.send_rdata[RdTileIdType(i)].msg @= s.reg_file[trunc(s.read_crossbar.packet_on_input_units[i].dst, LocalBankIndexType)].rdata[0]
               s.send_rdata[RdTileIdType(i)].val @= s.read_crossbar.send[s.read_crossbar.packet_on_input_units[i].dst].val
             # TODO: Check the translated Verilog to make sure the loop is flattened correctly with special out (NocPktType) towards NoC.
@@ -351,11 +390,11 @@ def update_all():
             # as the request can come from the NoC, it meant to access this local SRAM,
             # which should be guarded by the controller and NoC routers.
             # assert(i < num_banks_per_cgra)
-            s.send_rdata[RdTileIdType(i)].msg @= s.recv_from_noc_rdata.msg
+            s.send_rdata[RdTileIdType(i)].msg @= s.recv_from_noc_load_response_pkt.msg.payload.data
             # TODO: https://github.com/tancheng/VectorCGRA/issues/26 -- Modify this part for non-blocking access.
             s.send_rdata[RdTileIdType(i)].val @= \
                 s.read_crossbar.send[s.read_crossbar.packet_on_input_units[i].dst].val & \
-                s.recv_from_noc_rdata.val
+                s.recv_from_noc_load_response_pkt.val
                 # FIXME: The msg would come back one by one in order, so no
                 # need to check the src_tile, which can be improved.
                 # s.recv_from_noc_rdata.en & \
@@ -388,11 +427,11 @@ def update_all():
         # for a long time waiting for the response.
         # TODO: https://github.com/tancheng/VectorCGRA/issues/26 -- Modify this part for non-blocking access.
         # 'val` indicates the data is arbitrated successfully.
-        s.recv_from_noc_rdata.rdy @= s.read_crossbar.send[num_banks_per_cgra].val
+        s.recv_from_noc_load_response_pkt.rdy @= s.read_crossbar.send[num_banks_per_cgra].val
         # Only allows releasing the pending request until the required load data is back,
         # i.e., though the request already sent out to NoC (the port is still blocked until
         # response is back).
-        s.read_crossbar.send[num_banks_per_cgra].rdy @= s.recv_from_noc_rdata.val
+        s.read_crossbar.send[num_banks_per_cgra].rdy @= s.recv_from_noc_load_response_pkt.val
 
         # Connects the write ports towards SRAM and NoC from the xbar.
         for b in range(num_banks_per_cgra):
@@ -458,7 +497,7 @@ def update_remote_load_pending():
       if s.reset:
         s.send_to_noc_load_pending <<= 0
       else:
-        if s.recv_from_noc_rdata.val:
+        if s.recv_from_noc_load_response_pkt.val:
           s.send_to_noc_load_pending <<= 0
         elif s.send_to_noc_load_request_pkt.val & s.send_to_noc_load_request_pkt.rdy:
           s.send_to_noc_load_pending <<= 1
@@ -472,7 +511,7 @@ def line_trace(s):
 
     send_to_noc_load_request_pkt_str = "send_to_noc_load_request_pkt: {"
     send_to_noc_load_response_pkt_str = "send_to_noc_load_response_pkt: {"
-    recv_from_noc_rdata_str = "recv_from_noc_read_data: {"
+    recv_from_noc_load_response_pkt_str = "recv_from_noc_load_response_pkt: {"
     send_to_noc_store_pkt_str = "send_to_noc_store_pkt: {"
 
 
@@ -485,7 +524,7 @@ def line_trace(s):
 
     send_to_noc_load_request_pkt_str += str(s.send_to_noc_load_request_pkt.msg) + ";"
     send_to_noc_load_response_pkt_str += " " + str(s.send_to_noc_load_response_pkt.msg) + " "
-    recv_from_noc_rdata_str += str(s.recv_from_noc_rdata.msg) + ";"
+    recv_from_noc_load_response_pkt_str += str(s.recv_from_noc_load_response_pkt.msg) + ";"
     send_to_noc_store_pkt_str += str(s.send_to_noc_store_pkt.msg) + ", val: " + str(s.send_to_noc_store_pkt.val) + ";"
 
     recv_raddr_str += "}"
@@ -494,11 +533,11 @@ def line_trace(s):
     recv_wdata_str += "}"
     send_to_noc_load_request_pkt_str += "}"
     send_to_noc_load_response_pkt_str += "}"
-    recv_from_noc_rdata_str += "}"
+    recv_from_noc_load_response_pkt_str += "}"
     send_to_noc_store_pkt_str += "}"
     read_crossbar_str = "read_crossbar: " + s.read_crossbar.line_trace()
     write_crossbar_str = "write_crossbar: " + s.write_crossbar.line_trace()
     content_str += "}"
 
-    return f'{recv_raddr_str} || {recv_waddr_str} || {recv_wdata_str} || {send_rdata_str} || {send_to_noc_load_request_pkt_str} || {send_to_noc_load_response_pkt_str} || {recv_from_noc_rdata_str} || {send_to_noc_store_pkt_str} || {read_crossbar_str} || {write_crossbar_str} || [{content_str}]'
+    return f'{recv_raddr_str} || {recv_waddr_str} || {recv_wdata_str} || {send_rdata_str} || {send_to_noc_load_request_pkt_str} || {send_to_noc_load_response_pkt_str} || {recv_from_noc_load_response_pkt_str} || {send_to_noc_store_pkt_str} || {read_crossbar_str} || {write_crossbar_str} || [{content_str}]'
 
diff --git a/mem/data/test/DataMemWithCrossbarRTL_test.py b/mem/data/test/DataMemWithCrossbarRTL_test.py
index 8a8da7f7..78e05d7f 100644
--- a/mem/data/test/DataMemWithCrossbarRTL_test.py
+++ b/mem/data/test/DataMemWithCrossbarRTL_test.py
@@ -8,17 +8,16 @@
   Date : Dec 6, 2024
 """
 
-from pymtl3 import *
-from pymtl3.passes.backends.verilog import (VerilogTranslationPass,
-                                            VerilogVerilatorImportPass)
+from pymtl3.passes.backends.verilog import (VerilogTranslationPass)
 from pymtl3.stdlib.test_utils import config_model_with_cmdline_opts
+
 from ..DataMemWithCrossbarRTL import DataMemWithCrossbarRTL
-from ....lib.basic.val_rdy.SourceRTL import SourceRTL as TestSrcRTL
 from ....lib.basic.val_rdy.SinkRTL import SinkRTL as TestSinkRTL
-from ....lib.cmd_type import *
+from ....lib.basic.val_rdy.SourceRTL import SourceRTL as TestSrcRTL
 from ....lib.messages import *
 from ....lib.opt_type import *
 
+
 #-------------------------------------------------------------------------
 # Test harness
 #-------------------------------------------------------------------------
@@ -30,7 +29,7 @@ def construct(s, NocPktType, CgraPayloadType, DataType, DataAddrType,
                 rd_tiles, wr_tiles, num_cgra_rows, num_cgra_columns,
                 num_tiles,
                 read_addr, read_data, write_addr,
-                write_data, noc_recv_load_data,
+                write_data, noc_recv_load,
                 send_to_noc_load_request_pkt, send_to_noc_store_pkt,
                 preload_data_per_bank):
 
@@ -47,7 +46,7 @@ def construct(s, NocPktType, CgraPayloadType, DataType, DataAddrType,
     s.recv_wdata = [TestSrcRTL(DataType, write_data[i])
                     for i in range(wr_tiles)]
 
-    s.recv_from_noc_rdata = TestSrcRTL(DataType, noc_recv_load_data)
+    s.recv_from_noc = TestSrcRTL(NocPktType, noc_recv_load)
 
     s.send_to_noc_load_request_pkt = TestSinkRTL(NocPktType, send_to_noc_load_request_pkt)
     s.send_to_noc_store_pkt = TestSinkRTL(NocPktType, send_to_noc_store_pkt)
@@ -73,7 +72,7 @@ def construct(s, NocPktType, CgraPayloadType, DataType, DataAddrType,
       s.data_mem.recv_waddr[i] //= s.recv_waddr[i].send
       s.data_mem.recv_wdata[i] //= s.recv_wdata[i].send
 
-    s.data_mem.recv_from_noc_rdata //= s.recv_from_noc_rdata.send
+    s.data_mem.recv_from_noc_load_response_pkt //= s.recv_from_noc.send
     s.data_mem.send_to_noc_load_request_pkt //= s.send_to_noc_load_request_pkt.recv
     s.data_mem.send_to_noc_store_pkt //= s.send_to_noc_store_pkt.recv
 
@@ -93,7 +92,7 @@ def done(s):
 
     if not s.send_to_noc_load_request_pkt.done() or \
        not s.send_to_noc_store_pkt.done() or \
-       not s.recv_from_noc_rdata.done():
+       not s.recv_from_noc.done():
       return False
 
     return True
@@ -208,12 +207,12 @@ def test_const_queue(cmdline_opts):
                ]
 
   # Input data.
-  # noc_send_read_addr = [DataAddrType(42)]
   send_to_noc_load_request_pkt = [
                      # src  dst src_x src_y dst_x dst_y src_tile dst_tile opq vc
       InterCgraPktType(0,   0,  0,    0,    0,    0,    0,       0,       0,  0, CgraPayloadType(CMD_LOAD_REQUEST, data_addr = 42)),
   ]
-  noc_recv_load_data = [DataType(0xbbbb, 1)]
+
+  noc_recv_load = [InterCgraPktType(0,   0,  0,    0,    0,    0,    0,       0,       0,  0, CgraPayloadType(CMD_LOAD_RESPONSE, DataType(0xbbbb, 1)))]
 
   # Expected.
   send_to_noc_store_pkt = [
@@ -238,7 +237,7 @@ def test_const_queue(cmdline_opts):
                    read_data,
                    write_addr,
                    write_data,
-                   noc_recv_load_data,
+                   noc_recv_load,
                    send_to_noc_load_request_pkt,
                    send_to_noc_store_pkt,
                    preload_data_per_bank)


Reviews:
user: login: tancheng
state: COMMENTED
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submitted_at: 2025-04-23T21:28:16Z
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submitted_at: 2025-04-25T16:10:44Z
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submitted_at: 2025-04-25T16:17:25Z
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state: COMMENTED
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submitted_at: 2025-04-25T16:20:30Z
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state: COMMENTED
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submitted_at: 2025-04-25T16:21:02Z
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state: COMMENTED
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submitted_at: 2025-04-25T16:27:33Z
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submitted_at: 2025-04-25T16:40:20Z
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submitted_at: 2025-04-28T15:41:36Z
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submitted_at: 2025-04-28T15:45:46Z
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submitted_at: 2025-04-30T16:48:22Z
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submitted_at: 2025-04-30T17:36:28Z
user: login: tancheng
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submitted_at: 2025-04-30T17:37:16Z
user: login: yuqisun
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-05-01T06:15:48Z
user: login: tancheng
body: Can we still change the `CgraRTL_test.py`'s bypass_queue as I mentioned in this PR, i.e., moving it into `CgraRTL.py` conditionally.

The purpose is to facilitate the verification/test_bench for users who only want to translate a CGRA rather than multi-cgra. In such case, it is not good to have users write their own bypass queue.
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submitted_at: 2025-05-05T16:12:47Z
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submitted_at: 2025-05-05T16:14:06Z
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submitted_at: 2025-05-06T02:28:05Z
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user: login: tancheng
state: APPROVED
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submitted_at: 2025-05-06T03:43:24Z

Review comments:
diff_hunk: @@ -38,6 +38,10 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
       s.num_mesh_ports = 8
 
     s.num_tiles = width * height
+    # left and bottom connecting to data mem
path: cgra/CgraRTL.py
user: login: tancheng
body: `# left and bottom connecting to data mem` -> `# The left and bottom tiles are connected to the data memory.`.
created_at: 2025-04-23T21:10:31Z
author_association: OWNER
diff_hunk: @@ -108,11 +112,19 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[height + width - 1] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[height + width - 1] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[height + width - 1] //= s.controller.send_to_mem_store_request_data
+
+
+    # Replace below with one noc pkt port and decouple in DataMem itself.
+    # 1. can reduce number of recv_raddr to num_rd_tiles - 1
+    # 2. can also do with store request?
+    # s.data_mem.recv_raddr[s.data_mem_num_rd_tiles] //= s.controller.send_to_mem_load_request_addr
+    # s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
+    # s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
+    s.data_mem.recv_from_noc_load_request //= s.controller.send_to_mem_load_request
+
+    s.data_mem.recv_waddr[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_addr
+    s.data_mem.recv_wdata[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_data
path: cgra/CgraRTL.py
user: login: tancheng
body: Yes, let's change this as well.
created_at: 2025-04-23T21:15:10Z
author_association: OWNER
diff_hunk: @@ -108,11 +112,19 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[height + width - 1] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[height + width - 1] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[height + width - 1] //= s.controller.send_to_mem_store_request_data
+
+
+    # Replace below with one noc pkt port and decouple in DataMem itself.
+    # 1. can reduce number of recv_raddr to num_rd_tiles - 1
+    # 2. can also do with store request?
+    # s.data_mem.recv_raddr[s.data_mem_num_rd_tiles] //= s.controller.send_to_mem_load_request_addr
+    # s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
+    # s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
+    s.data_mem.recv_from_noc_load_request //= s.controller.send_to_mem_load_request
+
+    s.data_mem.recv_waddr[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_addr
+    s.data_mem.recv_wdata[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_data
+
     s.data_mem.recv_from_noc_rdata //= s.controller.send_to_tile_load_response_data
path: cgra/CgraRTL.py
user: login: tancheng
body: How about change this as well? i.e., `recv_from_noc_load_response`.
created_at: 2025-04-23T21:17:33Z
author_association: OWNER
diff_hunk: @@ -77,9 +80,11 @@ def construct(s,
     s.dut.send_to_mem_store_request_addr //= s.sink_to_mem_store_request_addr_en_rdy.recv
     s.dut.send_to_mem_store_request_data //= s.sink_to_mem_store_request_data_en_rdy.recv
     s.dut.send_to_tile_load_response_data //= s.sink_to_mem_load_response_data_en_rdy.recv
-    s.dut.send_to_mem_load_request_addr  //= s.sink_to_mem_load_request_addr_en_rdy.recv
-    s.dut.send_to_mem_load_request_src_cgra.rdy //= 1
-    s.dut.send_to_mem_load_request_src_tile.rdy //= 1
+
+    # s.dut.send_to_mem_load_request_addr  //= s.sink_to_mem_load_request_addr_en_rdy.recv
+    # s.dut.send_to_mem_load_request_src_cgra.rdy //= 1
+    # s.dut.send_to_mem_load_request_src_tile.rdy //= 1
+    s.dut.send_to_mem_load_request //= s.sink_to_mem_load_request_en_rdy.recv
path: controller/test/ControllerRTL_test.py
user: login: tancheng
body: Let's remove all the redundent `_en_rdy` and `_val_rdy`. They all should already be val/rdy based via import:
```
from ...lib.basic.val_rdy.SinkRTL import SinkRTL as TestSinkRTL
from ...lib.basic.val_rdy.SourceRTL import SourceRTL as TestSrcRTL
```
created_at: 2025-04-23T21:20:23Z
author_association: OWNER
diff_hunk: @@ -174,20 +180,30 @@ def assemble_xbar_pkt():
 
       if s.init_mem_done != b1(0):
         for i in range(num_xbar_in_rd_ports):
+
+          if i == num_xbar_in_rd_ports - 1:
+            recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
+            cgra_id = s.recv_from_noc_load_request.msg.src
+            tile_id = s.recv_from_noc_load_request.msg.src_tile_id
+          else:
+            recv_raddr = s.recv_raddr[i].msg
+            cgra_id = s.cgra_id
+            # FIXME: change to exact tile id.
+            tile_id = 0 # i * (num_tiles // num_rd_tiles)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Can these be initialized at beginning of the update_block but only be reset under certain condition?

And I feel they now have different behavior than previous logic for `s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, s.recv_raddr[i].msg, 0, 0)`, specifically, I cannot see `0, 0` be given.
created_at: 2025-04-23T21:23:50Z
author_association: OWNER
diff_hunk: @@ -296,12 +315,20 @@ def update_all():
           s.recv_wdata_bypass_q[i].recv.val @= s.recv_wdata[i].val
           s.recv_wdata_bypass_q[i].recv.msg @= s.recv_wdata[i].msg
 
-        for i in range(num_xbar_in_rd_ports):
-          s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
-          s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
-          s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
-        s.recv_from_noc_load_src_cgra.rdy @= s.read_crossbar.recv[-1].rdy
-        s.recv_from_noc_load_src_tile.rdy @= s.read_crossbar.recv[-1].rdy
+        for i in range(s.num_rd_tiles):
+            s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
+            s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
+            s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
+        s.read_crossbar.recv[-1].val @= s.recv_from_noc_load_request.val
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Add comments mentioning [-1] means `num_xbar_in_rd_ports - 1` and `s.num_rd_tiles`?
created_at: 2025-04-23T21:28:10Z
author_association: OWNER
diff_hunk: @@ -38,6 +38,10 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
       s.num_mesh_ports = 8
 
     s.num_tiles = width * height
+    # left and bottom connecting to data mem
path: cgra/CgraRTL.py
user: login: yuqisun
body: Done.
created_at: 2025-04-25T16:10:44Z
author_association: COLLABORATOR
diff_hunk: @@ -108,11 +112,19 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[height + width - 1] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[height + width - 1] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[height + width - 1] //= s.controller.send_to_mem_store_request_data
+
+
+    # Replace below with one noc pkt port and decouple in DataMem itself.
+    # 1. can reduce number of recv_raddr to num_rd_tiles - 1
+    # 2. can also do with store request?
+    # s.data_mem.recv_raddr[s.data_mem_num_rd_tiles] //= s.controller.send_to_mem_load_request_addr
+    # s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
+    # s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
+    s.data_mem.recv_from_noc_load_request //= s.controller.send_to_mem_load_request
+
+    s.data_mem.recv_waddr[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_addr
+    s.data_mem.recv_wdata[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_data
+
     s.data_mem.recv_from_noc_rdata //= s.controller.send_to_tile_load_response_data
path: cgra/CgraRTL.py
user: login: yuqisun
body: Want to change type from `DataType` to `NocPktType` for `s.data_mem.recv_from_noc_rdata //= s.controller.send_to_tile_load_response_data`?

`DataType` looks also good for now, but I'm good to change.
created_at: 2025-04-25T16:17:25Z
author_association: COLLABORATOR
diff_hunk: @@ -77,9 +80,11 @@ def construct(s,
     s.dut.send_to_mem_store_request_addr //= s.sink_to_mem_store_request_addr_en_rdy.recv
     s.dut.send_to_mem_store_request_data //= s.sink_to_mem_store_request_data_en_rdy.recv
     s.dut.send_to_tile_load_response_data //= s.sink_to_mem_load_response_data_en_rdy.recv
-    s.dut.send_to_mem_load_request_addr  //= s.sink_to_mem_load_request_addr_en_rdy.recv
-    s.dut.send_to_mem_load_request_src_cgra.rdy //= 1
-    s.dut.send_to_mem_load_request_src_tile.rdy //= 1
+
+    # s.dut.send_to_mem_load_request_addr  //= s.sink_to_mem_load_request_addr_en_rdy.recv
+    # s.dut.send_to_mem_load_request_src_cgra.rdy //= 1
+    # s.dut.send_to_mem_load_request_src_tile.rdy //= 1
+    s.dut.send_to_mem_load_request //= s.sink_to_mem_load_request_en_rdy.recv
path: controller/test/ControllerRTL_test.py
user: login: yuqisun
body: Done.
created_at: 2025-04-25T16:20:30Z
author_association: COLLABORATOR
diff_hunk: @@ -174,20 +180,30 @@ def assemble_xbar_pkt():
 
       if s.init_mem_done != b1(0):
         for i in range(num_xbar_in_rd_ports):
+
+          if i == num_xbar_in_rd_ports - 1:
+            recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
+            cgra_id = s.recv_from_noc_load_request.msg.src
+            tile_id = s.recv_from_noc_load_request.msg.src_tile_id
+          else:
+            recv_raddr = s.recv_raddr[i].msg
+            cgra_id = s.cgra_id
+            # FIXME: change to exact tile id.
+            tile_id = 0 # i * (num_tiles // num_rd_tiles)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: Checking ...
created_at: 2025-04-25T16:21:02Z
author_association: COLLABORATOR
diff_hunk: @@ -296,12 +315,20 @@ def update_all():
           s.recv_wdata_bypass_q[i].recv.val @= s.recv_wdata[i].val
           s.recv_wdata_bypass_q[i].recv.msg @= s.recv_wdata[i].msg
 
-        for i in range(num_xbar_in_rd_ports):
-          s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
-          s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
-          s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
-        s.recv_from_noc_load_src_cgra.rdy @= s.read_crossbar.recv[-1].rdy
-        s.recv_from_noc_load_src_tile.rdy @= s.read_crossbar.recv[-1].rdy
+        for i in range(s.num_rd_tiles):
+            s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
+            s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
+            s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
+        s.read_crossbar.recv[-1].val @= s.recv_from_noc_load_request.val
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: Added.
created_at: 2025-04-25T16:27:33Z
author_association: COLLABORATOR
diff_hunk: @@ -108,11 +112,19 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[height + width - 1] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[height + width - 1] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[height + width - 1] //= s.controller.send_to_mem_store_request_data
+
+
+    # Replace below with one noc pkt port and decouple in DataMem itself.
+    # 1. can reduce number of recv_raddr to num_rd_tiles - 1
+    # 2. can also do with store request?
+    # s.data_mem.recv_raddr[s.data_mem_num_rd_tiles] //= s.controller.send_to_mem_load_request_addr
+    # s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
+    # s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
+    s.data_mem.recv_from_noc_load_request //= s.controller.send_to_mem_load_request
+
+    s.data_mem.recv_waddr[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_addr
+    s.data_mem.recv_wdata[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_data
+
     s.data_mem.recv_from_noc_rdata //= s.controller.send_to_tile_load_response_data
path: cgra/CgraRTL.py
user: login: tancheng
body: Same to what u done for load request, i.e., InterCgraPktTyp. They all are for memory access. So we should do this for load request, load response, and store request.
created_at: 2025-04-25T16:40:20Z
author_association: OWNER
diff_hunk: @@ -296,12 +315,20 @@ def update_all():
           s.recv_wdata_bypass_q[i].recv.val @= s.recv_wdata[i].val
           s.recv_wdata_bypass_q[i].recv.msg @= s.recv_wdata[i].msg
 
-        for i in range(num_xbar_in_rd_ports):
-          s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
-          s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
-          s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
-        s.recv_from_noc_load_src_cgra.rdy @= s.read_crossbar.recv[-1].rdy
-        s.recv_from_noc_load_src_tile.rdy @= s.read_crossbar.recv[-1].rdy
+        for i in range(s.num_rd_tiles):
+            s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
+            s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
+            s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
+        s.read_crossbar.recv[-1].val @= s.recv_from_noc_load_request.val
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: Note: When run `MeshMultiCgraRTL_test.py::test_verilog_homo_2x2_4x4`, `-1` idx throws out of list exception, changed to `s.num_rd_tiles` fixed it, it's related with PyMTL?
created_at: 2025-04-28T15:41:36Z
author_association: COLLABORATOR
diff_hunk: @@ -296,12 +315,20 @@ def update_all():
           s.recv_wdata_bypass_q[i].recv.val @= s.recv_wdata[i].val
           s.recv_wdata_bypass_q[i].recv.msg @= s.recv_wdata[i].msg
 
-        for i in range(num_xbar_in_rd_ports):
-          s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
-          s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
-          s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
-        s.recv_from_noc_load_src_cgra.rdy @= s.read_crossbar.recv[-1].rdy
-        s.recv_from_noc_load_src_tile.rdy @= s.read_crossbar.recv[-1].rdy
+        for i in range(s.num_rd_tiles):
+            s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
+            s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
+            s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
+        s.read_crossbar.recv[-1].val @= s.recv_from_noc_load_request.val
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: @yo96 any comment on the `[-1]`?
created_at: 2025-04-28T15:45:46Z
author_association: OWNER
diff_hunk: @@ -184,41 +184,74 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
-          if i == num_xbar_in_rd_ports - 1:
-            recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
-            cgra_id = s.recv_from_noc_load_request.msg.src
-            tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
-          else:
-            recv_raddr = s.recv_raddr[i].msg
-
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
           if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
-            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
           s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, cgra_id, tile_id)
+
+        recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Can we change this `recv_raddr` to `recv_raddr_from_noc`, which will be more clear for this special port. Similar to `bank_index` -> `bank_index_from_noc`.

And what is the current blocker to enable pass the verification? Related to this?
created_at: 2025-04-29T14:13:26Z
author_association: OWNER
diff_hunk: @@ -184,41 +184,74 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
-          if i == num_xbar_in_rd_ports - 1:
-            recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
-            cgra_id = s.recv_from_noc_load_request.msg.src
-            tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
-          else:
-            recv_raddr = s.recv_raddr[i].msg
-
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
           if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
-            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
           s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, cgra_id, tile_id)
+
+        recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
+        # Calculates the target bank index.
+        if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
+          bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+        else:
+          bank_index = XbarOutRdType(num_banks_per_cgra)
+        cgra_id = s.recv_from_noc_load_request.msg.src
+        tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: change `cgra_id` to `src_cgra_id`, `tile_id` to `src_tile_id`?
created_at: 2025-04-29T14:14:39Z
author_association: OWNER
diff_hunk: @@ -184,41 +184,74 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
-          if i == num_xbar_in_rd_ports - 1:
-            recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
-            cgra_id = s.recv_from_noc_load_request.msg.src
-            tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
-          else:
-            recv_raddr = s.recv_raddr[i].msg
-
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
           if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
-            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
           s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, cgra_id, tile_id)
+
+        recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: Sure, currently blocking at `CgraRTL_test.py::test_systolic_3x3`, it passes pytest, but fails when `--test-verilog`. Looks nothing in data mem. (Log stopped in 77 cycles, while pytest process stopped in 86 steps, and not as many line_traces as pytest to investigate.)

```
E   VectorCGRA.lib.basic.val_rdy.SinkRTL.PyMTLTestSinkError: Test sink s.complete_signal_sink_out received WRONG message!
E   Expected : IntraCgraPkt: 0->0 || cgra_id:0(0, 0)->0(0, 0) || 00:0 || payload:MultiCgraNocPayload: cmd:a|data:0000000e.1.0.0|data_addr:04|ctrl:(opt)00|(fu_in)0-0-0-0|(predicate)0|(routing_xbar_out)0-0-0-0-0-0-0-0|(fu_xbar_out)0-0-0-0-0-0-0-0|(predicate_in)0-0-0-0|(vector_factor_power)0|(is_last_ctrl)0|(read_reg_from)0-0-0-0|(write_reg_from)0-0-0-0|(write_reg_idx)0-0-0-0|(read_reg_idx)0-0-0-0|ctrl_addr:0
E   
E   
E   Received : IntraCgraPkt: 0->9 || cgra_id:0(0, 0)->0(0, 0) || 00:0 || payload:MultiCgraNocPayload: cmd:a|data:00000000.0.0.0|data_addr:04|ctrl:(opt)00|(fu_in)0-0-0-0|(predicate)0|(routing_xbar_out)0-0-0-0-0-0-0-0|(fu_xbar_out)0-0-0-0-0-0-0-0|(predicate_in)0-0-0-0|(vector_factor_power)0|(is_last_ctrl)0|(read_reg_from)0-0-0-0|(write_reg_from)0-0-0-0|(write_reg_idx)0-0-0-0|(read_reg_idx)0-0-0-0|ctrl_addr:0
```
created_at: 2025-04-29T15:52:36Z
author_association: COLLABORATOR
diff_hunk: @@ -184,41 +184,74 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
-          if i == num_xbar_in_rd_ports - 1:
-            recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
-            cgra_id = s.recv_from_noc_load_request.msg.src
-            tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
-          else:
-            recv_raddr = s.recv_raddr[i].msg
-
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
           if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
-            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
           s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, cgra_id, tile_id)
+
+        recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
+        # Calculates the target bank index.
+        if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
+          bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+        else:
+          bank_index = XbarOutRdType(num_banks_per_cgra)
+        cgra_id = s.recv_from_noc_load_request.msg.src
+        tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: Done.
created_at: 2025-04-29T22:33:16Z
author_association: COLLABORATOR
diff_hunk: @@ -184,41 +184,74 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
-          if i == num_xbar_in_rd_ports - 1:
-            recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
-            cgra_id = s.recv_from_noc_load_request.msg.src
-            tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
-          else:
-            recv_raddr = s.recv_raddr[i].msg
-
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
           if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
-            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
           s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, cgra_id, tile_id)
+
+        recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: I believe this is related to https://github.com/tancheng/VectorCGRA/blob/da7c7164eb87f83f19d1d91edb23fd90c26893d3/cgra/test/CgraRTL_test.py#L75

Basically, the module/hardware inside the testbench but outside the `dut` won't be translated, which explains your pymtl simulation test passed, but translated verilog co-simulation failed.

I suggest you move that bypass queue inside the `dut`, i.e., `CgraRTL` (don't forget to include those [connections](https://github.com/tancheng/VectorCGRA/blob/da7c7164eb87f83f19d1d91edb23fd90c26893d3/cgra/test/CgraRTL_test.py#L84-L85)), and use a passed in argument (e.g., `is_multi_cgra = true` [here](https://github.com/tancheng/VectorCGRA/blob/da7c7164eb87f83f19d1d91edb23fd90c26893d3/cgra/CgraRTL.py#L29)). Then for `CgraRTL_test.py` ([this line](https://github.com/tancheng/VectorCGRA/blob/da7c7164eb87f83f19d1d91edb23fd90c26893d3/cgra/test/CgraRTL_test.py#L70)), you always provide that `is_multi_cgra` as `false`; while the multi-cgra tests, it is by default `true`.

Is this clear? And how does the solution sound to you?
created_at: 2025-04-29T22:59:57Z
author_association: OWNER
diff_hunk: @@ -184,41 +184,74 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
-          if i == num_xbar_in_rd_ports - 1:
-            recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
-            cgra_id = s.recv_from_noc_load_request.msg.src
-            tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
-          else:
-            recv_raddr = s.recv_raddr[i].msg
-
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
           if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
-            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
           s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, cgra_id, tile_id)
+
+        recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: As check, data is set in bypassQ, let me debug it in IDE for more information:
![Screenshot from 2025-04-30 12-05-02](https://github.com/user-attachments/assets/00e65563-7347-4f2f-a16e-de2f666574e3)

created_at: 2025-04-30T04:08:03Z
author_association: COLLABORATOR
diff_hunk: @@ -184,41 +184,74 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
-          if i == num_xbar_in_rd_ports - 1:
-            recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
-            cgra_id = s.recv_from_noc_load_request.msg.src
-            tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
-          else:
-            recv_raddr = s.recv_raddr[i].msg
-
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
           if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
-            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
           s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, cgra_id, tile_id)
+
+        recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: How about the dut's receiver connecting to bypass_queue's sender?
created_at: 2025-04-30T04:58:42Z
author_association: OWNER
diff_hunk: @@ -184,41 +184,74 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
-          if i == num_xbar_in_rd_ports - 1:
-            recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
-            cgra_id = s.recv_from_noc_load_request.msg.src
-            tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
-          else:
-            recv_raddr = s.recv_raddr[i].msg
-
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
           if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
-            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
           s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, cgra_id, tile_id)
+
+        recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: To clarify, 
> which explains your pymtl simulation test passed, but translated verilog co-simulation failed.

I think I was partially wrong. Bypass queue won't be translated as it is a part of test bench, but it still participates into co-simulation still as it is a part of test bench..
created_at: 2025-04-30T06:21:51Z
author_association: OWNER
diff_hunk: @@ -184,41 +184,74 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
-          if i == num_xbar_in_rd_ports - 1:
-            recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
-            cgra_id = s.recv_from_noc_load_request.msg.src
-            tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
-          else:
-            recv_raddr = s.recv_raddr[i].msg
-
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
           if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
-            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
           s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, cgra_id, tile_id)
+
+        recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: > How about the dut's receiver connecting to bypass_queue's sender?

Yes, can see data in it.
![Screenshot from 2025-05-01 00-47-03](https://github.com/user-attachments/assets/4ac156ad-8272-4670-bcd7-1033436fa0ed)

created_at: 2025-04-30T16:48:22Z
author_association: COLLABORATOR
diff_hunk: @@ -38,6 +38,10 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
       s.num_mesh_ports = 8
 
     s.num_tiles = width * height
+    # The left and bottom tiles are connected to the data memory.
+    s.data_mem_num_rd_tiles = height + width - 1
+    s.data_mem_num_wr_tiles = height + width - 1
path: cgra/CgraRTL.py
user: login: tancheng
body: These two could be python variables rather than pymtl HW module, i.e., remove `s.`?
created_at: 2025-04-30T16:52:05Z
author_association: OWNER
diff_hunk: @@ -296,12 +315,20 @@ def update_all():
           s.recv_wdata_bypass_q[i].recv.val @= s.recv_wdata[i].val
           s.recv_wdata_bypass_q[i].recv.msg @= s.recv_wdata[i].msg
 
-        for i in range(num_xbar_in_rd_ports):
-          s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
-          s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
-          s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
-        s.recv_from_noc_load_src_cgra.rdy @= s.read_crossbar.recv[-1].rdy
-        s.recv_from_noc_load_src_tile.rdy @= s.read_crossbar.recv[-1].rdy
+        for i in range(s.num_rd_tiles):
+            s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
+            s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
+            s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
+        s.read_crossbar.recv[-1].val @= s.recv_from_noc_load_request.val
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: Hi @tancheng ,

Could you help double review this part of [code.](https://github.com/yuqisun/VectorCGRA/blob/765dff945526ef08e74d218e6c4fa88083fd79de/mem/data/DataMemWithCrossbarRTL.py#L367-L369)
Is it possible to impact CgraRTL to test with verilog? 

Got some different behavior between `s.read_crossbar.recv[s.num_rd_tiles]` and `s.read_crossbar.recv[-1]`:

For `pytest ../cgra/test/CgraRTL_test.py::test_systolic_3x3 -xvs --tb=short --test-verilog`
1. If set s.read_crossbar.recv[-1] and s.rd_pkt[-1], error:
```
    raise PyMTLTypeError( s.blk, node.ast, 'array index out of range!' )
E   pymtl3.passes.rtlir.errors.PyMTLTypeError: 
E   In file /home/syq/cgra/VectorCGRA/mem/data/DataMemWithCrossbarRTL.py, Line 368, Col 39:
E     s.read_crossbar.recv[-1].msg @= s.rd_pkt[-1]
E                                    ^
E   - array index out of range!
```

2. If set 

```
s.read_crossbar.recv[s.num_rd_tiles].val @= s.recv_from_noc_load_request.val
        s.read_crossbar.recv[s.num_rd_tiles].msg @= s.rd_pkt[s.num_rd_tiles]
        s.recv_from_noc_load_request.rdy @= s.read_crossbar.recv[s.num_rd_tiles].rdy
```

error:

```
raise PyMTLTestSinkError( s.error_msg )
E   VectorCGRA.lib.basic.val_rdy.SinkRTL.PyMTLTestSinkError: Test sink s.complete_signal_sink_out received WRONG message!
E   Expected : IntraCgraPkt: 0->0 || cgra_id:0(0, 0)->0(0, 0) || 00:0 || payload:MultiCgraNocPayload: cmd:a|data:0000000e.1.0.0|data_addr:04|ctrl:(opt)00|(fu_in)0-0-0-0|(predicate)0|(routing_xbar_out)0-0-0-0-0-0-0-0|(fu_xbar_out)0-0-0-0-0-0-0-0|(predicate_in)0-0-0-0|(vector_factor_power)0|(is_last_ctrl)0|(read_reg_from)0-0-0-0|(write_reg_from)0-0-0-0|(write_reg_idx)0-0-0-0|(read_reg_idx)0-0-0-0|ctrl_addr:0
E   
E   
E   Received : IntraCgraPkt: 0->9 || cgra_id:0(0, 0)->0(0, 0) || 00:0 || payload:MultiCgraNocPayload: cmd:a|data:00000000.0.0.0|data_addr:04|ctrl:(opt)00|(fu_in)0-0-0-0|(predicate)0|(routing_xbar_out)0-0-0-0-0-0-0-0|(fu_xbar_out)0-0-0-0-0-0-0-0|(predicate_in)0-0-0-0|(vector_factor_power)0|(is_last_ctrl)0|(read_reg_from)0-0-0-0|(write_reg_from)0-0-0-0|(write_reg_idx)0-0-0-0|(read_reg_idx)0-0-0-0|ctrl_addr:0
```

4. If set

```
s.read_crossbar.recv[-1].val @= s.recv_from_noc_load_request.val
        s.read_crossbar.recv[-1].msg @= s.rd_pkt[s.num_rd_tiles]
        s.recv_from_noc_load_request.rdy @= s.read_crossbar.recv[-1].rdy
```
looks hang in [this signal](https://github.com/yuqisun/VectorCGRA/blob/765dff945526ef08e74d218e6c4fa88083fd79de/cgra/test/CgraRTL_test.py#L332), error:

```
../cgra/test/CgraRTL_test.py:683: in test_systolic_3x3
    run_sim(th)
../../../anaconda3/envs/py39/lib/python3.9/site-packages/pymtl3/stdlib/test_utils/test_helpers.py:236: in run_sim
    assert model.sim_cycle_count() < max_cycles
E   assert 10000 < 10000
E    +  where 10000 = <function PrepareSimPass.create_sim_cycle_count.<locals>.sim_cycle_count at 0x7f33ddf344c0>()
E    +    where <function PrepareSimPass.create_sim_cycle_count.<locals>.sim_cycle_count at 0x7f33ddf344c0> = s.sim_cycle_count
```
created_at: 2025-04-30T17:20:31Z
author_association: COLLABORATOR
diff_hunk: @@ -38,6 +38,10 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
       s.num_mesh_ports = 8
 
     s.num_tiles = width * height
+    # The left and bottom tiles are connected to the data memory.
+    s.data_mem_num_rd_tiles = height + width - 1
+    s.data_mem_num_wr_tiles = height + width - 1
path: cgra/CgraRTL.py
user: login: yuqisun
body: Updated.
created_at: 2025-04-30T17:21:45Z
author_association: COLLABORATOR
diff_hunk: @@ -166,50 +173,102 @@ def construct(s,
 
     @update
     def assemble_xbar_pkt():
+      cgra_id = s.cgra_id
+      # FIXME: change to exact tile id.
+      tile_id = TileIdType(0) # i * (num_tiles // num_rd_tiles)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Can we remove these temp python variables? Assemble the target pkt using the src pkt directly.
created_at: 2025-04-30T17:33:49Z
author_association: OWNER
diff_hunk: @@ -166,50 +173,102 @@ def construct(s,
 
     @update
     def assemble_xbar_pkt():
+      cgra_id = s.cgra_id
+      # FIXME: change to exact tile id.
+      tile_id = TileIdType(0) # i * (num_tiles // num_rd_tiles)
+
       for i in range(num_xbar_in_rd_ports):
         s.rd_pkt[i] @= TileSramXbarRdPktType(i, 0, 0, 0, 0)
 
       for i in range(num_xbar_in_wr_ports):
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
-          if (s.recv_raddr[i].msg >= s.address_lower) & (s.recv_raddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_raddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+          if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
-          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, s.recv_raddr[i].msg, 0, 0)
-        for i in range(num_rd_tiles):
-          s.rd_pkt[i].src_cgra @= s.cgra_id
-          # FIXME: change to exact tile id.
-          s.rd_pkt[i].src_tile @= 0 # i * (num_tiles // num_rd_tiles)
-        s.rd_pkt[num_rd_tiles].src_cgra @= s.recv_from_noc_load_src_cgra.msg
-        s.rd_pkt[num_rd_tiles].src_tile @= s.recv_from_noc_load_src_tile.msg
+          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, cgra_id, tile_id)
 
-
-        for i in range(num_xbar_in_wr_ports):
+        recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr
+        # Calculates the target bank index.
+        if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper):
+          bank_index = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+        else:
+          bank_index = XbarOutRdType(num_banks_per_cgra)
+        src_cgra_id = s.recv_from_noc_load_request.msg.src
+        src_tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
+        s.rd_pkt[num_rd_tiles] @= TileSramXbarRdPktType(num_rd_tiles, bank_index, recv_raddr_from_noc, src_cgra_id, src_tile_id)
+
+          # if i == num_xbar_in_rd_ports - 1:
+          #   recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
+          #   cgra_id = s.recv_from_noc_load_request.msg.src
+          #   tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
+          # else:
+          #   recv_raddr = s.recv_raddr[i].msg
+          #
+          # # Calculates the target bank index.
+          # if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
+          #   bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits,
+          #                      XbarOutRdType)
+          # else:
+          #   bank_index = XbarOutRdType(num_banks_per_cgra)
+          # s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, cgra_id, tile_id)
+        # for i in range(num_rd_tiles):
+        #   s.rd_pkt[i].src_cgra @= s.cgra_id
+        #   # FIXME: change to exact tile id.
+        #   s.rd_pkt[i].src_tile @= 0 # i * (num_tiles // num_rd_tiles)
+        # s.rd_pkt[num_rd_tiles].src_cgra @= s.recv_from_noc_load_src_cgra.msg
+        # s.rd_pkt[num_rd_tiles].src_tile @= s.recv_from_noc_load_src_tile.msg
+
+        for i in range(num_wr_tiles):
+          recv_waddr = s.recv_waddr[i].msg
           # Calculates the target bank index.
-          if (s.recv_waddr[i].msg >= s.address_lower) & (s.recv_waddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_waddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutWrType)
+          if (recv_waddr >= s.address_lower) & (recv_waddr <= s.address_upper):
+            bank_index = trunc((recv_waddr - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType)
           else:
             bank_index = XbarOutWrType(num_banks_per_cgra)
-          s.wr_pkt[i] @= TileSramXbarWrPktType(i, bank_index, s.recv_waddr[i].msg, 0, 0)
+          s.wr_pkt[i] @= TileSramXbarWrPktType(i, bank_index, recv_waddr, 0, 0)
+
+        recv_waddr_from_noc = s.recv_from_noc_store_request.msg.payload.data_addr
+        if (recv_waddr_from_noc >= s.address_lower) & (recv_waddr_from_noc <= s.address_upper):
+          bank_index = trunc((recv_waddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType)
+        else:
+          bank_index = XbarOutWrType(num_banks_per_cgra)
+        s.wr_pkt[num_wr_tiles] @= TileSramXbarWrPktType(num_wr_tiles, bank_index, recv_waddr_from_noc, 0, 0)
+
+          # if i == num_xbar_in_wr_ports - 1:
+          #   recv_waddr = s.recv_from_noc_store_request.msg.payload.data_addr
+          # else:
+          #   recv_waddr = s.recv_waddr[i].msg
+          # # Calculates the target bank index.
+          # if (recv_waddr >= s.address_lower) & (recv_waddr <= s.address_upper):
+          #   bank_index = trunc((recv_waddr - s.address_lower) >> per_bank_addr_nbits,
+          #                      XbarOutWrType)
+          # else:
+          #   bank_index = XbarOutWrType(num_banks_per_cgra)
+          # s.wr_pkt[i] @= TileSramXbarWrPktType(i, bank_index, recv_waddr, 0, 0)
 
 
     # Connects xbar with the sram.
     @update
     def update_all():
 
       # Initializes the signals.
-      for i in range(num_xbar_in_rd_ports):
-        s.recv_raddr[i].rdy @= 0
-        s.recv_from_noc_load_src_cgra.rdy @= 0
-        s.recv_from_noc_load_src_tile.rdy @= 0
+      for i in range(s.num_rd_tiles):
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Are we able to remove `s.`?
created_at: 2025-04-30T17:34:33Z
author_association: OWNER
diff_hunk: @@ -166,50 +173,102 @@ def construct(s,
 
     @update
     def assemble_xbar_pkt():
+      cgra_id = s.cgra_id
+      # FIXME: change to exact tile id.
+      tile_id = TileIdType(0) # i * (num_tiles // num_rd_tiles)
+
       for i in range(num_xbar_in_rd_ports):
         s.rd_pkt[i] @= TileSramXbarRdPktType(i, 0, 0, 0, 0)
 
       for i in range(num_xbar_in_wr_ports):
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
-          if (s.recv_raddr[i].msg >= s.address_lower) & (s.recv_raddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_raddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+          if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
-          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, s.recv_raddr[i].msg, 0, 0)
-        for i in range(num_rd_tiles):
-          s.rd_pkt[i].src_cgra @= s.cgra_id
-          # FIXME: change to exact tile id.
-          s.rd_pkt[i].src_tile @= 0 # i * (num_tiles // num_rd_tiles)
-        s.rd_pkt[num_rd_tiles].src_cgra @= s.recv_from_noc_load_src_cgra.msg
-        s.rd_pkt[num_rd_tiles].src_tile @= s.recv_from_noc_load_src_tile.msg
+          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, cgra_id, tile_id)
 
-
-        for i in range(num_xbar_in_wr_ports):
+        recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr
+        # Calculates the target bank index.
+        if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper):
+          bank_index = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+        else:
+          bank_index = XbarOutRdType(num_banks_per_cgra)
+        src_cgra_id = s.recv_from_noc_load_request.msg.src
+        src_tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
+        s.rd_pkt[num_rd_tiles] @= TileSramXbarRdPktType(num_rd_tiles, bank_index, recv_raddr_from_noc, src_cgra_id, src_tile_id)
+
+          # if i == num_xbar_in_rd_ports - 1:
+          #   recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
+          #   cgra_id = s.recv_from_noc_load_request.msg.src
+          #   tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
+          # else:
+          #   recv_raddr = s.recv_raddr[i].msg
+          #
+          # # Calculates the target bank index.
+          # if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
+          #   bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits,
+          #                      XbarOutRdType)
+          # else:
+          #   bank_index = XbarOutRdType(num_banks_per_cgra)
+          # s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, cgra_id, tile_id)
+        # for i in range(num_rd_tiles):
+        #   s.rd_pkt[i].src_cgra @= s.cgra_id
+        #   # FIXME: change to exact tile id.
+        #   s.rd_pkt[i].src_tile @= 0 # i * (num_tiles // num_rd_tiles)
+        # s.rd_pkt[num_rd_tiles].src_cgra @= s.recv_from_noc_load_src_cgra.msg
+        # s.rd_pkt[num_rd_tiles].src_tile @= s.recv_from_noc_load_src_tile.msg
+
+        for i in range(num_wr_tiles):
+          recv_waddr = s.recv_waddr[i].msg
           # Calculates the target bank index.
-          if (s.recv_waddr[i].msg >= s.address_lower) & (s.recv_waddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_waddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutWrType)
+          if (recv_waddr >= s.address_lower) & (recv_waddr <= s.address_upper):
+            bank_index = trunc((recv_waddr - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType)
           else:
             bank_index = XbarOutWrType(num_banks_per_cgra)
-          s.wr_pkt[i] @= TileSramXbarWrPktType(i, bank_index, s.recv_waddr[i].msg, 0, 0)
+          s.wr_pkt[i] @= TileSramXbarWrPktType(i, bank_index, recv_waddr, 0, 0)
+
+        recv_waddr_from_noc = s.recv_from_noc_store_request.msg.payload.data_addr
+        if (recv_waddr_from_noc >= s.address_lower) & (recv_waddr_from_noc <= s.address_upper):
+          bank_index = trunc((recv_waddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType)
+        else:
+          bank_index = XbarOutWrType(num_banks_per_cgra)
+        s.wr_pkt[num_wr_tiles] @= TileSramXbarWrPktType(num_wr_tiles, bank_index, recv_waddr_from_noc, 0, 0)
+
+          # if i == num_xbar_in_wr_ports - 1:
+          #   recv_waddr = s.recv_from_noc_store_request.msg.payload.data_addr
+          # else:
+          #   recv_waddr = s.recv_waddr[i].msg
+          # # Calculates the target bank index.
+          # if (recv_waddr >= s.address_lower) & (recv_waddr <= s.address_upper):
+          #   bank_index = trunc((recv_waddr - s.address_lower) >> per_bank_addr_nbits,
+          #                      XbarOutWrType)
+          # else:
+          #   bank_index = XbarOutWrType(num_banks_per_cgra)
+          # s.wr_pkt[i] @= TileSramXbarWrPktType(i, bank_index, recv_waddr, 0, 0)
 
 
     # Connects xbar with the sram.
     @update
     def update_all():
 
       # Initializes the signals.
-      for i in range(num_xbar_in_rd_ports):
-        s.recv_raddr[i].rdy @= 0
-        s.recv_from_noc_load_src_cgra.rdy @= 0
-        s.recv_from_noc_load_src_tile.rdy @= 0
+      for i in range(s.num_rd_tiles):
+          s.recv_raddr[i].rdy @= 0
+      s.recv_from_noc_load_request.rdy @= 0
+
+      for i in range(s.num_wr_tiles):
+        # s.recv_from_noc_load_src_cgra.rdy @= 0
+        # s.recv_from_noc_load_src_tile.rdy @= 0
         s.recv_waddr[i].rdy @= 0
         s.recv_wdata_bypass_q[i].send.rdy @= 0
+      s.recv_from_noc_store_request.rdy @= 0
+      s.recv_wdata_bypass_q[-1].send.rdy @= 0
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: `-1` doesn't work, plz use the const value.
created_at: 2025-04-30T17:34:58Z
author_association: OWNER
diff_hunk: @@ -230,10 +289,12 @@ def update_all():
                      CgraPayloadType(0, 0, 0, 0, 0))
 
 
-      for i in range(num_xbar_in_wr_ports):
+      for i in range(s.num_wr_tiles):
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: remove `s.`
created_at: 2025-04-30T17:35:04Z
author_association: OWNER
diff_hunk: @@ -230,10 +289,12 @@ def update_all():
                      CgraPayloadType(0, 0, 0, 0, 0))
 
 
-      for i in range(num_xbar_in_wr_ports):
+      for i in range(s.num_wr_tiles):
         s.recv_wdata[i].rdy @= 0
         s.recv_wdata_bypass_q[i].recv.val @= 0
         s.recv_wdata_bypass_q[i].recv.msg @= DataType()
+      s.recv_wdata_bypass_q[-1].recv.val @= 0
+      s.recv_wdata_bypass_q[-1].recv.msg @= DataType()
 
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: `-1` doesn't work.
created_at: 2025-04-30T17:35:16Z
author_association: OWNER
diff_hunk: @@ -291,22 +352,36 @@ def update_all():
           s.reg_file[b].wen[0] @= b1(1)
 
       else:
-        for i in range(num_xbar_in_wr_ports):
+        for i in range(s.num_wr_tiles):
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Remove `s.`
created_at: 2025-04-30T17:35:24Z
author_association: OWNER
diff_hunk: @@ -291,22 +352,36 @@ def update_all():
           s.reg_file[b].wen[0] @= b1(1)
 
       else:
-        for i in range(num_xbar_in_wr_ports):
+        for i in range(s.num_wr_tiles):
           s.recv_wdata[i].rdy @= s.recv_wdata_bypass_q[i].recv.rdy
           s.recv_wdata_bypass_q[i].recv.val @= s.recv_wdata[i].val
           s.recv_wdata_bypass_q[i].recv.msg @= s.recv_wdata[i].msg
-
-        for i in range(num_xbar_in_rd_ports):
-          s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
-          s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
-          s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
-        s.recv_from_noc_load_src_cgra.rdy @= s.read_crossbar.recv[-1].rdy
-        s.recv_from_noc_load_src_tile.rdy @= s.read_crossbar.recv[-1].rdy
+        s.recv_from_noc_store_request.rdy @= s.recv_wdata_bypass_q[-1].recv.rdy
+        s.recv_wdata_bypass_q[-1].recv.val @= s.recv_from_noc_store_request.val
+        s.recv_wdata_bypass_q[-1].recv.msg @= s.recv_from_noc_store_request.msg.payload.data
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: `-1` doesn't work.
created_at: 2025-04-30T17:35:35Z
author_association: OWNER
diff_hunk: @@ -291,22 +352,36 @@ def update_all():
           s.reg_file[b].wen[0] @= b1(1)
 
       else:
-        for i in range(num_xbar_in_wr_ports):
+        for i in range(s.num_wr_tiles):
           s.recv_wdata[i].rdy @= s.recv_wdata_bypass_q[i].recv.rdy
           s.recv_wdata_bypass_q[i].recv.val @= s.recv_wdata[i].val
           s.recv_wdata_bypass_q[i].recv.msg @= s.recv_wdata[i].msg
-
-        for i in range(num_xbar_in_rd_ports):
-          s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
-          s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
-          s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
-        s.recv_from_noc_load_src_cgra.rdy @= s.read_crossbar.recv[-1].rdy
-        s.recv_from_noc_load_src_tile.rdy @= s.read_crossbar.recv[-1].rdy
+        s.recv_from_noc_store_request.rdy @= s.recv_wdata_bypass_q[-1].recv.rdy
+        s.recv_wdata_bypass_q[-1].recv.val @= s.recv_from_noc_store_request.val
+        s.recv_wdata_bypass_q[-1].recv.msg @= s.recv_from_noc_store_request.msg.payload.data
+
+        for i in range(s.num_rd_tiles):
+            s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
+            s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
+            s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
+        s.read_crossbar.recv[-1].val @= s.recv_from_noc_load_request.val
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: `-1` doesn't work.
created_at: 2025-04-30T17:35:43Z
author_association: OWNER
diff_hunk: @@ -291,22 +352,36 @@ def update_all():
           s.reg_file[b].wen[0] @= b1(1)
 
       else:
-        for i in range(num_xbar_in_wr_ports):
+        for i in range(s.num_wr_tiles):
           s.recv_wdata[i].rdy @= s.recv_wdata_bypass_q[i].recv.rdy
           s.recv_wdata_bypass_q[i].recv.val @= s.recv_wdata[i].val
           s.recv_wdata_bypass_q[i].recv.msg @= s.recv_wdata[i].msg
-
-        for i in range(num_xbar_in_rd_ports):
-          s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
-          s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
-          s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
-        s.recv_from_noc_load_src_cgra.rdy @= s.read_crossbar.recv[-1].rdy
-        s.recv_from_noc_load_src_tile.rdy @= s.read_crossbar.recv[-1].rdy
+        s.recv_from_noc_store_request.rdy @= s.recv_wdata_bypass_q[-1].recv.rdy
+        s.recv_wdata_bypass_q[-1].recv.val @= s.recv_from_noc_store_request.val
+        s.recv_wdata_bypass_q[-1].recv.msg @= s.recv_from_noc_store_request.msg.payload.data
+
+        for i in range(s.num_rd_tiles):
+            s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
+            s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
+            s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
+        s.read_crossbar.recv[-1].val @= s.recv_from_noc_load_request.val
+        s.read_crossbar.recv[-1].msg @= s.rd_pkt[s.num_rd_tiles]
+        s.recv_from_noc_load_request.rdy @= s.read_crossbar.recv[-1].rdy
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Plz fix all `-1`.
created_at: 2025-04-30T17:36:02Z
author_association: OWNER
diff_hunk: @@ -291,22 +352,36 @@ def update_all():
           s.reg_file[b].wen[0] @= b1(1)
 
       else:
-        for i in range(num_xbar_in_wr_ports):
+        for i in range(s.num_wr_tiles):
           s.recv_wdata[i].rdy @= s.recv_wdata_bypass_q[i].recv.rdy
           s.recv_wdata_bypass_q[i].recv.val @= s.recv_wdata[i].val
           s.recv_wdata_bypass_q[i].recv.msg @= s.recv_wdata[i].msg
-
-        for i in range(num_xbar_in_rd_ports):
-          s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
-          s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
-          s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
-        s.recv_from_noc_load_src_cgra.rdy @= s.read_crossbar.recv[-1].rdy
-        s.recv_from_noc_load_src_tile.rdy @= s.read_crossbar.recv[-1].rdy
+        s.recv_from_noc_store_request.rdy @= s.recv_wdata_bypass_q[-1].recv.rdy
+        s.recv_wdata_bypass_q[-1].recv.val @= s.recv_from_noc_store_request.val
+        s.recv_wdata_bypass_q[-1].recv.msg @= s.recv_from_noc_store_request.msg.payload.data
+
+        for i in range(s.num_rd_tiles):
+            s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
+            s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
+            s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
+        s.read_crossbar.recv[-1].val @= s.recv_from_noc_load_request.val
+        s.read_crossbar.recv[-1].msg @= s.rd_pkt[s.num_rd_tiles]
+        s.recv_from_noc_load_request.rdy @= s.read_crossbar.recv[-1].rdy
+
+        # for i in range(num_xbar_in_rd_ports):
+        #   s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
+        #   s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
+        #   s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
+        # s.recv_from_noc_load_src_cgra.rdy @= s.read_crossbar.recv[-1].rdy
+        # s.recv_from_noc_load_src_tile.rdy @= s.read_crossbar.recv[-1].rdy
   
-        for i in range(num_xbar_in_wr_ports):
+        for i in range(s.num_wr_tiles):
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Remove `s.`
created_at: 2025-04-30T17:36:10Z
author_association: OWNER
diff_hunk: @@ -291,22 +352,36 @@ def update_all():
           s.reg_file[b].wen[0] @= b1(1)
 
       else:
-        for i in range(num_xbar_in_wr_ports):
+        for i in range(s.num_wr_tiles):
           s.recv_wdata[i].rdy @= s.recv_wdata_bypass_q[i].recv.rdy
           s.recv_wdata_bypass_q[i].recv.val @= s.recv_wdata[i].val
           s.recv_wdata_bypass_q[i].recv.msg @= s.recv_wdata[i].msg
-
-        for i in range(num_xbar_in_rd_ports):
-          s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
-          s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
-          s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
-        s.recv_from_noc_load_src_cgra.rdy @= s.read_crossbar.recv[-1].rdy
-        s.recv_from_noc_load_src_tile.rdy @= s.read_crossbar.recv[-1].rdy
+        s.recv_from_noc_store_request.rdy @= s.recv_wdata_bypass_q[-1].recv.rdy
+        s.recv_wdata_bypass_q[-1].recv.val @= s.recv_from_noc_store_request.val
+        s.recv_wdata_bypass_q[-1].recv.msg @= s.recv_from_noc_store_request.msg.payload.data
+
+        for i in range(s.num_rd_tiles):
+            s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
+            s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
+            s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
+        s.read_crossbar.recv[-1].val @= s.recv_from_noc_load_request.val
+        s.read_crossbar.recv[-1].msg @= s.rd_pkt[s.num_rd_tiles]
+        s.recv_from_noc_load_request.rdy @= s.read_crossbar.recv[-1].rdy
+
+        # for i in range(num_xbar_in_rd_ports):
+        #   s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
+        #   s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
+        #   s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
+        # s.recv_from_noc_load_src_cgra.rdy @= s.read_crossbar.recv[-1].rdy
+        # s.recv_from_noc_load_src_tile.rdy @= s.read_crossbar.recv[-1].rdy
   
-        for i in range(num_xbar_in_wr_ports):
+        for i in range(s.num_wr_tiles):
           s.write_crossbar.recv[i].val @= s.recv_waddr[i].val
           s.write_crossbar.recv[i].msg @= s.wr_pkt[i]
           s.recv_waddr[i].rdy @= s.write_crossbar.recv[i].rdy
+        s.write_crossbar.recv[-1].val @= s.recv_from_noc_store_request.val
+        s.write_crossbar.recv[-1].msg @= s.wr_pkt[s.num_wr_tiles]
+        s.recv_from_noc_store_request.rdy @= s.write_crossbar.recv[-1].rdy
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Fix `-1`
created_at: 2025-04-30T17:36:24Z
author_association: OWNER
diff_hunk: @@ -296,12 +315,20 @@ def update_all():
           s.recv_wdata_bypass_q[i].recv.val @= s.recv_wdata[i].val
           s.recv_wdata_bypass_q[i].recv.msg @= s.recv_wdata[i].msg
 
-        for i in range(num_xbar_in_rd_ports):
-          s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
-          s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
-          s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
-        s.recv_from_noc_load_src_cgra.rdy @= s.read_crossbar.recv[-1].rdy
-        s.recv_from_noc_load_src_tile.rdy @= s.read_crossbar.recv[-1].rdy
+        for i in range(s.num_rd_tiles):
+            s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
+            s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
+            s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
+        s.read_crossbar.recv[-1].val @= s.recv_from_noc_load_request.val
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Offline discussed with @yo96, `-1` doesn't work for translation (though works for python simulation), plz avoid using them.
created_at: 2025-04-30T17:37:16Z
author_association: OWNER
diff_hunk: @@ -296,12 +315,20 @@ def update_all():
           s.recv_wdata_bypass_q[i].recv.val @= s.recv_wdata[i].val
           s.recv_wdata_bypass_q[i].recv.msg @= s.recv_wdata[i].msg
 
-        for i in range(num_xbar_in_rd_ports):
-          s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
-          s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
-          s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
-        s.recv_from_noc_load_src_cgra.rdy @= s.read_crossbar.recv[-1].rdy
-        s.recv_from_noc_load_src_tile.rdy @= s.read_crossbar.recv[-1].rdy
+        for i in range(s.num_rd_tiles):
+            s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
+            s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
+            s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
+        s.read_crossbar.recv[-1].val @= s.recv_from_noc_load_request.val
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: Got it, thanks.
created_at: 2025-05-01T06:15:48Z
author_association: COLLABORATOR
diff_hunk: @@ -108,11 +112,20 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[height + width - 1] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[height + width - 1] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[height + width - 1] //= s.controller.send_to_mem_store_request_data
+
+
+    # Replace below with one noc pkt port and decouple in DataMem itself.
+    # 1. can reduce number of recv_raddr to num_rd_tiles - 1
+    # 2. can also do with store request?
+    # s.data_mem.recv_raddr[s.data_mem_num_rd_tiles] //= s.controller.send_to_mem_load_request_addr
+    # s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
+    # s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
path: cgra/CgraRTL.py
user: login: tancheng
body: Remove
created_at: 2025-05-01T07:27:02Z
author_association: OWNER
diff_hunk: @@ -108,11 +112,20 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[height + width - 1] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[height + width - 1] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[height + width - 1] //= s.controller.send_to_mem_store_request_data
+
+
+    # Replace below with one noc pkt port and decouple in DataMem itself.
+    # 1. can reduce number of recv_raddr to num_rd_tiles - 1
+    # 2. can also do with store request?
+    # s.data_mem.recv_raddr[s.data_mem_num_rd_tiles] //= s.controller.send_to_mem_load_request_addr
+    # s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
+    # s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
+    s.data_mem.recv_from_noc_load_request //= s.controller.send_to_mem_load_request
+
+    # s.data_mem.recv_waddr[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_addr
+    # s.data_mem.recv_wdata[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_data
path: cgra/CgraRTL.py
user: login: tancheng
body: Remove
created_at: 2025-05-01T07:27:12Z
author_association: OWNER
diff_hunk: @@ -108,11 +112,19 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[height + width - 1] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[height + width - 1] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[height + width - 1] //= s.controller.send_to_mem_store_request_data
+
+
+    # Replace below with one noc pkt port and decouple in DataMem itself.
+    # 1. can reduce number of recv_raddr to num_rd_tiles - 1
+    # 2. can also do with store request?
+    # s.data_mem.recv_raddr[s.data_mem_num_rd_tiles] //= s.controller.send_to_mem_load_request_addr
+    # s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
+    # s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
+    s.data_mem.recv_from_noc_load_request //= s.controller.send_to_mem_load_request
+
+    s.data_mem.recv_waddr[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_addr
+    s.data_mem.recv_wdata[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_data
+
     s.data_mem.recv_from_noc_rdata //= s.controller.send_to_tile_load_response_data
path: cgra/CgraRTL.py
user: login: tancheng
body: It seems all three are done?
created_at: 2025-05-01T07:28:54Z
author_association: OWNER
diff_hunk: @@ -104,11 +104,15 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[dataSPM.getNumOfValidReadPorts()] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[dataSPM.getNumOfValidWritePorts()] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[dataSPM.getNumOfValidWritePorts()] //= s.controller.send_to_mem_store_request_data
+    # s.data_mem.recv_raddr[dataSPM.getNumOfValidReadPorts()] //= s.controller.send_to_mem_load_request_addr
+    # s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
+    # s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
path: cgra/CgraTemplateRTL.py
user: login: tancheng
body: Remove all commented old code.
created_at: 2025-05-01T07:29:14Z
author_association: OWNER
diff_hunk: @@ -70,19 +72,23 @@ def construct(s,
 
     # Connections
     s.dut.cgra_id //= cgra_id
-    s.src_from_tile_load_request_pkt_en_rdy.send //= s.dut.recv_from_tile_load_request_pkt
-    s.src_from_tile_load_response_pkt_en_rdy.send //= s.dut.recv_from_tile_load_response_pkt
-    s.src_from_tile_store_request_pkt_en_rdy.send //= s.dut.recv_from_tile_store_request_pkt
+    s.src_from_tile_load_request_pkt.send //= s.dut.recv_from_tile_load_request_pkt
+    s.src_from_tile_load_response_pkt.send //= s.dut.recv_from_tile_load_response_pkt
+    s.src_from_tile_store_request_pkt.send //= s.dut.recv_from_tile_store_request_pkt
+
+    # s.dut.send_to_mem_store_request_addr //= s.sink_to_mem_store_request_addr.recv
path: controller/test/ControllerRTL_test.py
user: login: tancheng
body: Remove all commented old code
created_at: 2025-05-01T07:30:37Z
author_association: OWNER
diff_hunk: @@ -88,16 +89,22 @@ def construct(s,
                               num_cgras,
                               num_tiles)
 
+
     # Interface
+    # [num_rd_tiles] indicates the request from the NoC. ---> Add separate recv port for NoC.
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Remove?
created_at: 2025-05-01T07:31:17Z
author_association: OWNER
diff_hunk: @@ -166,50 +173,102 @@ def construct(s,
 
     @update
     def assemble_xbar_pkt():
+      # cgra_id = s.cgra_id
+      # FIXME: change to exact tile id.
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Let's keep this `FIXME` here
created_at: 2025-05-01T07:31:47Z
author_association: OWNER
diff_hunk: @@ -108,11 +112,19 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[height + width - 1] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[height + width - 1] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[height + width - 1] //= s.controller.send_to_mem_store_request_data
+
+
+    # Replace below with one noc pkt port and decouple in DataMem itself.
+    # 1. can reduce number of recv_raddr to num_rd_tiles - 1
+    # 2. can also do with store request?
+    # s.data_mem.recv_raddr[s.data_mem_num_rd_tiles] //= s.controller.send_to_mem_load_request_addr
+    # s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
+    # s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
+    s.data_mem.recv_from_noc_load_request //= s.controller.send_to_mem_load_request
+
+    s.data_mem.recv_waddr[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_addr
+    s.data_mem.recv_wdata[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_data
+
     s.data_mem.recv_from_noc_rdata //= s.controller.send_to_tile_load_response_data
path: cgra/CgraRTL.py
user: login: yuqisun
body: Pushed change for LOAD_RESPONSE just now, all three are done. Will move bypass_q to CgraRTL and clean unused comments.
created_at: 2025-05-02T16:13:44Z
author_association: COLLABORATOR
diff_hunk: @@ -184,41 +184,74 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
-          if i == num_xbar_in_rd_ports - 1:
-            recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
-            cgra_id = s.recv_from_noc_load_request.msg.src
-            tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
-          else:
-            recv_raddr = s.recv_raddr[i].msg
-
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
           if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
-            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
           s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, cgra_id, tile_id)
+
+        recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: Hi @tancheng ,

I moved `bypass_q` into `CgraRTL`, but got exception, `bypass_q` has already connected with interfaces via `//=`, still need set val/rdy? Code pushed in the latest [commit](https://github.com/tancheng/VectorCGRA/pull/141/commits/f6afd929c9858f1afe95b6d6090873886d7207dc), any idea?

```
   if not is_multi_cgra:
      s.bypass_queue = BypassQueueRTL(NocPktType, 1)
      s.send_to_inter_cgra_noc //= s.bypass_queue.recv
      s.recv_from_inter_cgra_noc //= s.bypass_queue.send
    else:
      s.recv_from_inter_cgra_noc //= s.controller.recv_from_inter_cgra_noc
      s.send_to_inter_cgra_noc //= s.controller.send_to_inter_cgra_noc
```
```
E   pymtl3.dsl.errors.NoWriterError: The following nets need drivers.
E   Net:
E    - s.dut.bypass_queue.recv.msg
E    - s.dut.send_to_inter_cgra_noc.msg
E    - s.dut.bypass_queue.q.recv.msg
E    - s.dut.bypass_queue.q.bypass_mux.in_[0]
E   Net:
E    - s.dut.send_to_inter_cgra_noc.val
E    - s.dut.bypass_queue.recv.val
E    - s.dut.bypass_queue.q.recv.val
E   Net:
E    - s.dut.bypass_queue.send.rdy
E    - s.dut.bypass_queue.q.send.rdy
E    - s.dut.recv_from_inter_cgra_noc.rdy
```


created_at: 2025-05-05T15:29:56Z
author_association: COLLABORATOR
diff_hunk: @@ -184,41 +184,74 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
-          if i == num_xbar_in_rd_ports - 1:
-            recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
-            cgra_id = s.recv_from_noc_load_request.msg.src
-            tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
-          else:
-            recv_raddr = s.recv_raddr[i].msg
-
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
           if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
-            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
           s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, cgra_id, tile_id)
+
+        recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: [updated] Plz change:
```
    if not is_multi_cgra:
      s.bypass_queue = BypassQueueRTL(NocPktType, 1)
      s.send_to_inter_cgra_noc //= s.bypass_queue.recv
      s.recv_from_inter_cgra_noc //= s.bypass_queue.send
    else:
      s.recv_from_inter_cgra_noc //= s.controller.recv_from_inter_cgra_noc
      s.send_to_inter_cgra_noc //= s.controller.send_to_inter_cgra_noc
```
to:
```
    if is_multi_cgra:
      s.recv_from_inter_cgra_noc //= s.controller.recv_from_inter_cgra_noc
      s.send_to_inter_cgra_noc //= s.controller.send_to_inter_cgra_noc
    else:
      s.bypass_queue = BypassQueueRTL(NocPktType, 1)
      s.bypass_queue.send //= s.controller.recv_from_inter_cgra_noc
      s.bypass_queue.recv //= s.controller.send_to_inter_cgra_noc
```
created_at: 2025-05-05T15:44:05Z
author_association: OWNER
diff_hunk: @@ -184,41 +184,74 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
-          if i == num_xbar_in_rd_ports - 1:
-            recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
-            cgra_id = s.recv_from_noc_load_request.msg.src
-            tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
-          else:
-            recv_raddr = s.recv_raddr[i].msg
-
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
           if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
-            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
           s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, cgra_id, tile_id)
+
+        recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: Ah, got it. pkt is from `controller` and current change write noting into `CgraRTL` recv/send interface yet, doesn't make sense to connect them with `bypass_q`. Sorry for the stupid question again ... Let me update it.
created_at: 2025-05-05T16:03:35Z
author_association: COLLABORATOR
diff_hunk: @@ -291,22 +352,36 @@ def update_all():
           s.reg_file[b].wen[0] @= b1(1)
 
       else:
-        for i in range(num_xbar_in_wr_ports):
+        for i in range(s.num_wr_tiles):
           s.recv_wdata[i].rdy @= s.recv_wdata_bypass_q[i].recv.rdy
           s.recv_wdata_bypass_q[i].recv.val @= s.recv_wdata[i].val
           s.recv_wdata_bypass_q[i].recv.msg @= s.recv_wdata[i].msg
-
-        for i in range(num_xbar_in_rd_ports):
-          s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
-          s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
-          s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
-        s.recv_from_noc_load_src_cgra.rdy @= s.read_crossbar.recv[-1].rdy
-        s.recv_from_noc_load_src_tile.rdy @= s.read_crossbar.recv[-1].rdy
+        s.recv_from_noc_store_request.rdy @= s.recv_wdata_bypass_q[-1].recv.rdy
+        s.recv_wdata_bypass_q[-1].recv.val @= s.recv_from_noc_store_request.val
+        s.recv_wdata_bypass_q[-1].recv.msg @= s.recv_from_noc_store_request.msg.payload.data
+
+        for i in range(s.num_rd_tiles):
+            s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
+            s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
+            s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
+        s.read_crossbar.recv[-1].val @= s.recv_from_noc_load_request.val
+        s.read_crossbar.recv[-1].msg @= s.rd_pkt[s.num_rd_tiles]
+        s.recv_from_noc_load_request.rdy @= s.read_crossbar.recv[-1].rdy
+
+        # for i in range(num_xbar_in_rd_ports):
+        #   s.read_crossbar.recv[i].val @= s.recv_raddr[i].val
+        #   s.read_crossbar.recv[i].msg @= s.rd_pkt[i]
+        #   s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy
+        # s.recv_from_noc_load_src_cgra.rdy @= s.read_crossbar.recv[-1].rdy
+        # s.recv_from_noc_load_src_tile.rdy @= s.read_crossbar.recv[-1].rdy
   
-        for i in range(num_xbar_in_wr_ports):
+        for i in range(s.num_wr_tiles):
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: Done.
created_at: 2025-05-05T16:10:26Z
author_association: COLLABORATOR
diff_hunk: @@ -104,11 +104,15 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[dataSPM.getNumOfValidReadPorts()] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[dataSPM.getNumOfValidWritePorts()] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[dataSPM.getNumOfValidWritePorts()] //= s.controller.send_to_mem_store_request_data
+    # s.data_mem.recv_raddr[dataSPM.getNumOfValidReadPorts()] //= s.controller.send_to_mem_load_request_addr
+    # s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
+    # s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
path: cgra/CgraTemplateRTL.py
user: login: yuqisun
body: Done.
created_at: 2025-05-05T16:10:51Z
author_association: COLLABORATOR
diff_hunk: @@ -166,50 +173,102 @@ def construct(s,
 
     @update
     def assemble_xbar_pkt():
+      # cgra_id = s.cgra_id
+      # FIXME: change to exact tile id.
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: Added back.
created_at: 2025-05-05T16:11:14Z
author_association: COLLABORATOR
diff_hunk: @@ -166,50 +173,102 @@ def construct(s,
 
     @update
     def assemble_xbar_pkt():
+      cgra_id = s.cgra_id
+      # FIXME: change to exact tile id.
+      tile_id = TileIdType(0) # i * (num_tiles // num_rd_tiles)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: Done.
created_at: 2025-05-05T16:11:55Z
author_association: COLLABORATOR
diff_hunk: @@ -108,11 +112,19 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[height + width - 1] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[height + width - 1] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[height + width - 1] //= s.controller.send_to_mem_store_request_data
+
+
+    # Replace below with one noc pkt port and decouple in DataMem itself.
+    # 1. can reduce number of recv_raddr to num_rd_tiles - 1
+    # 2. can also do with store request?
+    # s.data_mem.recv_raddr[s.data_mem_num_rd_tiles] //= s.controller.send_to_mem_load_request_addr
+    # s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
+    # s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
+    s.data_mem.recv_from_noc_load_request //= s.controller.send_to_mem_load_request
+
+    s.data_mem.recv_waddr[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_addr
+    s.data_mem.recv_wdata[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_data
path: cgra/CgraRTL.py
user: login: yuqisun
body: Done.
created_at: 2025-05-05T16:12:47Z
author_association: COLLABORATOR
diff_hunk: @@ -108,11 +112,19 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[height + width - 1] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[height + width - 1] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[height + width - 1] //= s.controller.send_to_mem_store_request_data
+
+
+    # Replace below with one noc pkt port and decouple in DataMem itself.
+    # 1. can reduce number of recv_raddr to num_rd_tiles - 1
+    # 2. can also do with store request?
+    # s.data_mem.recv_raddr[s.data_mem_num_rd_tiles] //= s.controller.send_to_mem_load_request_addr
+    # s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
+    # s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
+    s.data_mem.recv_from_noc_load_request //= s.controller.send_to_mem_load_request
+
+    s.data_mem.recv_waddr[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_addr
+    s.data_mem.recv_wdata[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_data
+
     s.data_mem.recv_from_noc_rdata //= s.controller.send_to_tile_load_response_data
path: cgra/CgraRTL.py
user: login: yuqisun
body: Done.
created_at: 2025-05-05T16:12:58Z
author_association: COLLABORATOR
diff_hunk: @@ -184,41 +184,74 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
-          if i == num_xbar_in_rd_ports - 1:
-            recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
-            cgra_id = s.recv_from_noc_load_request.msg.src
-            tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
-          else:
-            recv_raddr = s.recv_raddr[i].msg
-
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
           if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
-            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
           s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, cgra_id, tile_id)
+
+        recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: Updated.
created_at: 2025-05-05T16:14:06Z
author_association: COLLABORATOR
diff_hunk: @@ -108,11 +112,20 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[height + width - 1] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[height + width - 1] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[height + width - 1] //= s.controller.send_to_mem_store_request_data
+
+
+    # Replace below with one noc pkt port and decouple in DataMem itself.
+    # 1. can reduce number of recv_raddr to num_rd_tiles - 1
+    # 2. can also do with store request?
+    # s.data_mem.recv_raddr[s.data_mem_num_rd_tiles] //= s.controller.send_to_mem_load_request_addr
+    # s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
+    # s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
+    s.data_mem.recv_from_noc_load_request //= s.controller.send_to_mem_load_request
+
+    # s.data_mem.recv_waddr[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_addr
+    # s.data_mem.recv_wdata[s.data_mem_num_wr_tiles] //= s.controller.send_to_mem_store_request_data
path: cgra/CgraRTL.py
user: login: yuqisun
body: Done.
created_at: 2025-05-05T16:14:23Z
author_association: COLLABORATOR
diff_hunk: @@ -108,18 +114,22 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[height + width - 1] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[height + width - 1] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[height + width - 1] //= s.controller.send_to_mem_store_request_data
-    s.data_mem.recv_from_noc_rdata //= s.controller.send_to_tile_load_response_data
+    s.data_mem.recv_from_noc_load_request //= s.controller.send_to_mem_load_request
+
path: cgra/CgraRTL.py
user: login: tancheng
body: Remove empty lines.
created_at: 2025-05-05T17:12:22Z
author_association: OWNER
diff_hunk: @@ -108,18 +114,22 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[height + width - 1] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[height + width - 1] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[height + width - 1] //= s.controller.send_to_mem_store_request_data
-    s.data_mem.recv_from_noc_rdata //= s.controller.send_to_tile_load_response_data
+    s.data_mem.recv_from_noc_load_request //= s.controller.send_to_mem_load_request
+
+    s.data_mem.recv_from_noc_store_request //= s.controller.send_to_mem_store_request
+
path: cgra/CgraRTL.py
user: login: tancheng
body: ditto
created_at: 2025-05-05T17:12:30Z
author_association: OWNER
diff_hunk: @@ -104,18 +105,22 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[dataSPM.getNumOfValidReadPorts()] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[dataSPM.getNumOfValidWritePorts()] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[dataSPM.getNumOfValidWritePorts()] //= s.controller.send_to_mem_store_request_data
-    s.data_mem.recv_from_noc_rdata //= s.controller.send_to_tile_load_response_data
+    s.data_mem.recv_from_noc_load_request //= s.controller.send_to_mem_load_request
+
path: cgra/CgraTemplateRTL.py
user: login: tancheng
body: ditto
created_at: 2025-05-05T17:12:38Z
author_association: OWNER
diff_hunk: @@ -104,18 +105,22 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[dataSPM.getNumOfValidReadPorts()] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[dataSPM.getNumOfValidWritePorts()] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[dataSPM.getNumOfValidWritePorts()] //= s.controller.send_to_mem_store_request_data
-    s.data_mem.recv_from_noc_rdata //= s.controller.send_to_tile_load_response_data
+    s.data_mem.recv_from_noc_load_request //= s.controller.send_to_mem_load_request
+
+    s.data_mem.recv_from_noc_store_request //= s.controller.send_to_mem_store_request
+
path: cgra/CgraTemplateRTL.py
user: login: tancheng
body: ditto
created_at: 2025-05-05T17:12:43Z
author_association: OWNER
diff_hunk: @@ -173,43 +176,57 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
-          if (s.recv_raddr[i].msg >= s.address_lower) & (s.recv_raddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_raddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+          if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
-          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, s.recv_raddr[i].msg, 0, 0)
-        for i in range(num_rd_tiles):
-          s.rd_pkt[i].src_cgra @= s.cgra_id
           # FIXME: change to exact tile id.
-          s.rd_pkt[i].src_tile @= 0 # i * (num_tiles // num_rd_tiles)
-        s.rd_pkt[num_rd_tiles].src_cgra @= s.recv_from_noc_load_src_cgra.msg
-        s.rd_pkt[num_rd_tiles].src_tile @= s.recv_from_noc_load_src_tile.msg
+          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, s.cgra_id, 0)
 
+        recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr
+        # Calculates the target bank index.
+        if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper):
+          bank_index = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Change this `bank_index` to `bank_index_load_from_noc`?
created_at: 2025-05-05T17:14:31Z
author_association: OWNER
diff_hunk: @@ -173,43 +176,57 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
-          if (s.recv_raddr[i].msg >= s.address_lower) & (s.recv_raddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_raddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+          if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Change `bank_index` to `bank_index_load_local`?
created_at: 2025-05-05T17:14:54Z
author_association: OWNER
diff_hunk: @@ -173,43 +176,57 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
-          if (s.recv_raddr[i].msg >= s.address_lower) & (s.recv_raddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_raddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+          if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
-          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, s.recv_raddr[i].msg, 0, 0)
-        for i in range(num_rd_tiles):
-          s.rd_pkt[i].src_cgra @= s.cgra_id
           # FIXME: change to exact tile id.
-          s.rd_pkt[i].src_tile @= 0 # i * (num_tiles // num_rd_tiles)
-        s.rd_pkt[num_rd_tiles].src_cgra @= s.recv_from_noc_load_src_cgra.msg
-        s.rd_pkt[num_rd_tiles].src_tile @= s.recv_from_noc_load_src_tile.msg
+          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, s.cgra_id, 0)
 
+        recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr
+        # Calculates the target bank index.
+        if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper):
+          bank_index = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+        else:
+          bank_index = XbarOutRdType(num_banks_per_cgra)
+        src_cgra_id = s.recv_from_noc_load_request.msg.src
+        src_tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Why we need `TileIdType()` to cast?
created_at: 2025-05-05T17:15:27Z
author_association: OWNER
diff_hunk: @@ -173,43 +176,57 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
-          if (s.recv_raddr[i].msg >= s.address_lower) & (s.recv_raddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_raddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+          if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
-          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, s.recv_raddr[i].msg, 0, 0)
-        for i in range(num_rd_tiles):
-          s.rd_pkt[i].src_cgra @= s.cgra_id
           # FIXME: change to exact tile id.
-          s.rd_pkt[i].src_tile @= 0 # i * (num_tiles // num_rd_tiles)
-        s.rd_pkt[num_rd_tiles].src_cgra @= s.recv_from_noc_load_src_cgra.msg
-        s.rd_pkt[num_rd_tiles].src_tile @= s.recv_from_noc_load_src_tile.msg
+          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, s.cgra_id, 0)
 
+        recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr
+        # Calculates the target bank index.
+        if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper):
+          bank_index = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+        else:
+          bank_index = XbarOutRdType(num_banks_per_cgra)
+        src_cgra_id = s.recv_from_noc_load_request.msg.src
+        src_tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
+        s.rd_pkt[num_rd_tiles] @= TileSramXbarRdPktType(num_rd_tiles, bank_index, recv_raddr_from_noc, src_cgra_id, src_tile_id)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Can we avoid `src_cgra_id` and `src_tile_id`, but directly assembling the `TileSramXbarRdPktType` using `recv_from_noc_load_request.msg.xxx`?
created_at: 2025-05-05T17:16:22Z
author_association: OWNER
diff_hunk: @@ -173,43 +176,57 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
-          if (s.recv_raddr[i].msg >= s.address_lower) & (s.recv_raddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_raddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+          if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
-          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, s.recv_raddr[i].msg, 0, 0)
-        for i in range(num_rd_tiles):
-          s.rd_pkt[i].src_cgra @= s.cgra_id
           # FIXME: change to exact tile id.
-          s.rd_pkt[i].src_tile @= 0 # i * (num_tiles // num_rd_tiles)
-        s.rd_pkt[num_rd_tiles].src_cgra @= s.recv_from_noc_load_src_cgra.msg
-        s.rd_pkt[num_rd_tiles].src_tile @= s.recv_from_noc_load_src_tile.msg
+          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, s.cgra_id, 0)
 
+        recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr
+        # Calculates the target bank index.
+        if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper):
+          bank_index = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+        else:
+          bank_index = XbarOutRdType(num_banks_per_cgra)
+        src_cgra_id = s.recv_from_noc_load_request.msg.src
+        src_tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
+        s.rd_pkt[num_rd_tiles] @= TileSramXbarRdPktType(num_rd_tiles, bank_index, recv_raddr_from_noc, src_cgra_id, src_tile_id)
 
-        for i in range(num_xbar_in_wr_ports):
+        for i in range(num_wr_tiles):
+          recv_waddr = s.recv_waddr[i].msg
           # Calculates the target bank index.
-          if (s.recv_waddr[i].msg >= s.address_lower) & (s.recv_waddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_waddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutWrType)
+          if (recv_waddr >= s.address_lower) & (recv_waddr <= s.address_upper):
+            bank_index = trunc((recv_waddr - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Change to `bank_index_store_local`?
created_at: 2025-05-05T17:16:56Z
author_association: OWNER
diff_hunk: @@ -173,43 +176,57 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
-          if (s.recv_raddr[i].msg >= s.address_lower) & (s.recv_raddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_raddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+          if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
-          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, s.recv_raddr[i].msg, 0, 0)
-        for i in range(num_rd_tiles):
-          s.rd_pkt[i].src_cgra @= s.cgra_id
           # FIXME: change to exact tile id.
-          s.rd_pkt[i].src_tile @= 0 # i * (num_tiles // num_rd_tiles)
-        s.rd_pkt[num_rd_tiles].src_cgra @= s.recv_from_noc_load_src_cgra.msg
-        s.rd_pkt[num_rd_tiles].src_tile @= s.recv_from_noc_load_src_tile.msg
+          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, s.cgra_id, 0)
 
+        recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr
+        # Calculates the target bank index.
+        if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper):
+          bank_index = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+        else:
+          bank_index = XbarOutRdType(num_banks_per_cgra)
+        src_cgra_id = s.recv_from_noc_load_request.msg.src
+        src_tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
+        s.rd_pkt[num_rd_tiles] @= TileSramXbarRdPktType(num_rd_tiles, bank_index, recv_raddr_from_noc, src_cgra_id, src_tile_id)
 
-        for i in range(num_xbar_in_wr_ports):
+        for i in range(num_wr_tiles):
+          recv_waddr = s.recv_waddr[i].msg
           # Calculates the target bank index.
-          if (s.recv_waddr[i].msg >= s.address_lower) & (s.recv_waddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_waddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutWrType)
+          if (recv_waddr >= s.address_lower) & (recv_waddr <= s.address_upper):
+            bank_index = trunc((recv_waddr - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType)
           else:
             bank_index = XbarOutWrType(num_banks_per_cgra)
-          s.wr_pkt[i] @= TileSramXbarWrPktType(i, bank_index, s.recv_waddr[i].msg, 0, 0)
+          s.wr_pkt[i] @= TileSramXbarWrPktType(i, bank_index, recv_waddr, 0, 0)
+
+        recv_waddr_from_noc = s.recv_from_noc_store_request.msg.payload.data_addr
+        if (recv_waddr_from_noc >= s.address_lower) & (recv_waddr_from_noc <= s.address_upper):
+          bank_index = trunc((recv_waddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Change to `bank_index_store_from_noc`?
created_at: 2025-05-05T17:17:13Z
author_association: OWNER
diff_hunk: @@ -108,18 +114,22 @@ def construct(s, DataType, PredicateType, CtrlPktType, CgraPayloadType,
     s.data_mem.address_upper //= s.address_upper
 
     # Connects data memory with controller.
-    s.data_mem.recv_raddr[height + width - 1] //= s.controller.send_to_mem_load_request_addr
-    s.data_mem.recv_from_noc_load_src_cgra //= s.controller.send_to_mem_load_request_src_cgra
-    s.data_mem.recv_from_noc_load_src_tile //= s.controller.send_to_mem_load_request_src_tile
-    s.data_mem.recv_waddr[height + width - 1] //= s.controller.send_to_mem_store_request_addr
-    s.data_mem.recv_wdata[height + width - 1] //= s.controller.send_to_mem_store_request_data
-    s.data_mem.recv_from_noc_rdata //= s.controller.send_to_tile_load_response_data
+    s.data_mem.recv_from_noc_load_request //= s.controller.send_to_mem_load_request
+
path: cgra/CgraRTL.py
user: login: yuqisun
body: Removed.
created_at: 2025-05-06T02:26:17Z
author_association: COLLABORATOR
diff_hunk: @@ -173,43 +176,57 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
-          if (s.recv_raddr[i].msg >= s.address_lower) & (s.recv_raddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_raddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+          if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
-          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, s.recv_raddr[i].msg, 0, 0)
-        for i in range(num_rd_tiles):
-          s.rd_pkt[i].src_cgra @= s.cgra_id
           # FIXME: change to exact tile id.
-          s.rd_pkt[i].src_tile @= 0 # i * (num_tiles // num_rd_tiles)
-        s.rd_pkt[num_rd_tiles].src_cgra @= s.recv_from_noc_load_src_cgra.msg
-        s.rd_pkt[num_rd_tiles].src_tile @= s.recv_from_noc_load_src_tile.msg
+          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, s.cgra_id, 0)
 
+        recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr
+        # Calculates the target bank index.
+        if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper):
+          bank_index = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: Updated.
created_at: 2025-05-06T02:26:36Z
author_association: COLLABORATOR
diff_hunk: @@ -173,43 +176,57 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
-          if (s.recv_raddr[i].msg >= s.address_lower) & (s.recv_raddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_raddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+          if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
-          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, s.recv_raddr[i].msg, 0, 0)
-        for i in range(num_rd_tiles):
-          s.rd_pkt[i].src_cgra @= s.cgra_id
           # FIXME: change to exact tile id.
-          s.rd_pkt[i].src_tile @= 0 # i * (num_tiles // num_rd_tiles)
-        s.rd_pkt[num_rd_tiles].src_cgra @= s.recv_from_noc_load_src_cgra.msg
-        s.rd_pkt[num_rd_tiles].src_tile @= s.recv_from_noc_load_src_tile.msg
+          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, s.cgra_id, 0)
 
+        recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr
+        # Calculates the target bank index.
+        if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper):
+          bank_index = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+        else:
+          bank_index = XbarOutRdType(num_banks_per_cgra)
+        src_cgra_id = s.recv_from_noc_load_request.msg.src
+        src_tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: Removed. Added to fix [this](https://github.com/tancheng/VectorCGRA/pull/141#issuecomment-2839411203), but good now after remove `-1`.
created_at: 2025-05-06T02:27:38Z
author_association: COLLABORATOR
diff_hunk: @@ -173,43 +176,57 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
-          if (s.recv_raddr[i].msg >= s.address_lower) & (s.recv_raddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_raddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+          if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
-          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, s.recv_raddr[i].msg, 0, 0)
-        for i in range(num_rd_tiles):
-          s.rd_pkt[i].src_cgra @= s.cgra_id
           # FIXME: change to exact tile id.
-          s.rd_pkt[i].src_tile @= 0 # i * (num_tiles // num_rd_tiles)
-        s.rd_pkt[num_rd_tiles].src_cgra @= s.recv_from_noc_load_src_cgra.msg
-        s.rd_pkt[num_rd_tiles].src_tile @= s.recv_from_noc_load_src_tile.msg
+          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, s.cgra_id, 0)
 
+        recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr
+        # Calculates the target bank index.
+        if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper):
+          bank_index = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+        else:
+          bank_index = XbarOutRdType(num_banks_per_cgra)
+        src_cgra_id = s.recv_from_noc_load_request.msg.src
+        src_tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
+        s.rd_pkt[num_rd_tiles] @= TileSramXbarRdPktType(num_rd_tiles, bank_index, recv_raddr_from_noc, src_cgra_id, src_tile_id)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: Done.
created_at: 2025-05-06T02:27:51Z
author_association: COLLABORATOR
diff_hunk: @@ -173,43 +176,57 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
-          if (s.recv_raddr[i].msg >= s.address_lower) & (s.recv_raddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_raddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+          if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
-          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, s.recv_raddr[i].msg, 0, 0)
-        for i in range(num_rd_tiles):
-          s.rd_pkt[i].src_cgra @= s.cgra_id
           # FIXME: change to exact tile id.
-          s.rd_pkt[i].src_tile @= 0 # i * (num_tiles // num_rd_tiles)
-        s.rd_pkt[num_rd_tiles].src_cgra @= s.recv_from_noc_load_src_cgra.msg
-        s.rd_pkt[num_rd_tiles].src_tile @= s.recv_from_noc_load_src_tile.msg
+          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, s.cgra_id, 0)
 
+        recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr
+        # Calculates the target bank index.
+        if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper):
+          bank_index = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+        else:
+          bank_index = XbarOutRdType(num_banks_per_cgra)
+        src_cgra_id = s.recv_from_noc_load_request.msg.src
+        src_tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
+        s.rd_pkt[num_rd_tiles] @= TileSramXbarRdPktType(num_rd_tiles, bank_index, recv_raddr_from_noc, src_cgra_id, src_tile_id)
 
-        for i in range(num_xbar_in_wr_ports):
+        for i in range(num_wr_tiles):
+          recv_waddr = s.recv_waddr[i].msg
           # Calculates the target bank index.
-          if (s.recv_waddr[i].msg >= s.address_lower) & (s.recv_waddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_waddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutWrType)
+          if (recv_waddr >= s.address_lower) & (recv_waddr <= s.address_upper):
+            bank_index = trunc((recv_waddr - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: Done.
created_at: 2025-05-06T02:27:58Z
author_association: COLLABORATOR
diff_hunk: @@ -173,43 +176,57 @@ def assemble_xbar_pkt():
         s.wr_pkt[i] @= TileSramXbarWrPktType(i, 0, 0, 0, 0)
 
       if s.init_mem_done != b1(0):
-        for i in range(num_xbar_in_rd_ports):
+        for i in range(num_rd_tiles):
+          recv_raddr = s.recv_raddr[i].msg
           # Calculates the target bank index.
-          if (s.recv_raddr[i].msg >= s.address_lower) & (s.recv_raddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_raddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutRdType)
+          if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
+            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
             bank_index = XbarOutRdType(num_banks_per_cgra)
-          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, s.recv_raddr[i].msg, 0, 0)
-        for i in range(num_rd_tiles):
-          s.rd_pkt[i].src_cgra @= s.cgra_id
           # FIXME: change to exact tile id.
-          s.rd_pkt[i].src_tile @= 0 # i * (num_tiles // num_rd_tiles)
-        s.rd_pkt[num_rd_tiles].src_cgra @= s.recv_from_noc_load_src_cgra.msg
-        s.rd_pkt[num_rd_tiles].src_tile @= s.recv_from_noc_load_src_tile.msg
+          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, s.cgra_id, 0)
 
+        recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr
+        # Calculates the target bank index.
+        if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper):
+          bank_index = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+        else:
+          bank_index = XbarOutRdType(num_banks_per_cgra)
+        src_cgra_id = s.recv_from_noc_load_request.msg.src
+        src_tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
+        s.rd_pkt[num_rd_tiles] @= TileSramXbarRdPktType(num_rd_tiles, bank_index, recv_raddr_from_noc, src_cgra_id, src_tile_id)
 
-        for i in range(num_xbar_in_wr_ports):
+        for i in range(num_wr_tiles):
+          recv_waddr = s.recv_waddr[i].msg
           # Calculates the target bank index.
-          if (s.recv_waddr[i].msg >= s.address_lower) & (s.recv_waddr[i].msg <= s.address_upper):
-            bank_index = trunc((s.recv_waddr[i].msg - s.address_lower) >> per_bank_addr_nbits,
-                               XbarOutWrType)
+          if (recv_waddr >= s.address_lower) & (recv_waddr <= s.address_upper):
+            bank_index = trunc((recv_waddr - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType)
           else:
             bank_index = XbarOutWrType(num_banks_per_cgra)
-          s.wr_pkt[i] @= TileSramXbarWrPktType(i, bank_index, s.recv_waddr[i].msg, 0, 0)
+          s.wr_pkt[i] @= TileSramXbarWrPktType(i, bank_index, recv_waddr, 0, 0)
+
+        recv_waddr_from_noc = s.recv_from_noc_store_request.msg.payload.data_addr
+        if (recv_waddr_from_noc >= s.address_lower) & (recv_waddr_from_noc <= s.address_upper):
+          bank_index = trunc((recv_waddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: Done.
created_at: 2025-05-06T02:28:05Z
author_association: COLLABORATOR
diff_hunk: @@ -178,39 +177,37 @@ def assemble_xbar_pkt():
       if s.init_mem_done != b1(0):
         for i in range(num_rd_tiles):
           recv_raddr = s.recv_raddr[i].msg
-          # Calculates the target bank index.
+          # Calculates the target bank index for load.
           if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
-            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+            bank_index_load_local = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
-            bank_index = XbarOutRdType(num_banks_per_cgra)
+            bank_index_load_local = XbarOutRdType(num_banks_per_cgra)
           # FIXME: change to exact tile id.
-          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, s.cgra_id, 0)
+          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index_load_local, recv_raddr, s.cgra_id, 0)
 
         recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr
         # Calculates the target bank index.
         if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper):
-          bank_index = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+          bank_index_load_from_noc = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
         else:
-          bank_index = XbarOutRdType(num_banks_per_cgra)
-        src_cgra_id = s.recv_from_noc_load_request.msg.src
-        src_tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
-        s.rd_pkt[num_rd_tiles] @= TileSramXbarRdPktType(num_rd_tiles, bank_index, recv_raddr_from_noc, src_cgra_id, src_tile_id)
+          bank_index_load_from_noc = XbarOutRdType(num_banks_per_cgra)
+        s.rd_pkt[num_rd_tiles] @= TileSramXbarRdPktType(num_rd_tiles, bank_index_load_from_noc, recv_raddr_from_noc, s.recv_from_noc_load_request.msg.src, s.recv_from_noc_load_request.msg.src_tile_id)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Break this long line and align the fields.
created_at: 2025-05-06T02:28:49Z
author_association: OWNER
diff_hunk: @@ -178,39 +177,37 @@ def assemble_xbar_pkt():
       if s.init_mem_done != b1(0):
         for i in range(num_rd_tiles):
           recv_raddr = s.recv_raddr[i].msg
-          # Calculates the target bank index.
+          # Calculates the target bank index for load.
           if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
-            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+            bank_index_load_local = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
-            bank_index = XbarOutRdType(num_banks_per_cgra)
+            bank_index_load_local = XbarOutRdType(num_banks_per_cgra)
           # FIXME: change to exact tile id.
-          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, s.cgra_id, 0)
+          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index_load_local, recv_raddr, s.cgra_id, 0)
 
         recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr
         # Calculates the target bank index.
         if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper):
-          bank_index = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+          bank_index_load_from_noc = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
         else:
-          bank_index = XbarOutRdType(num_banks_per_cgra)
-        src_cgra_id = s.recv_from_noc_load_request.msg.src
-        src_tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
-        s.rd_pkt[num_rd_tiles] @= TileSramXbarRdPktType(num_rd_tiles, bank_index, recv_raddr_from_noc, src_cgra_id, src_tile_id)
+          bank_index_load_from_noc = XbarOutRdType(num_banks_per_cgra)
+        s.rd_pkt[num_rd_tiles] @= TileSramXbarRdPktType(num_rd_tiles, bank_index_load_from_noc, recv_raddr_from_noc, s.recv_from_noc_load_request.msg.src, s.recv_from_noc_load_request.msg.src_tile_id)
 
         for i in range(num_wr_tiles):
           recv_waddr = s.recv_waddr[i].msg
-          # Calculates the target bank index.
+          # Calculates the target bank index for store.
           if (recv_waddr >= s.address_lower) & (recv_waddr <= s.address_upper):
-            bank_index = trunc((recv_waddr - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType)
+            bank_index_store_local = trunc((recv_waddr - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType)
           else:
-            bank_index = XbarOutWrType(num_banks_per_cgra)
-          s.wr_pkt[i] @= TileSramXbarWrPktType(i, bank_index, recv_waddr, 0, 0)
+            bank_index_store_local = XbarOutWrType(num_banks_per_cgra)
+          s.wr_pkt[i] @= TileSramXbarWrPktType(i, bank_index_store_local, recv_waddr, 0, 0)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: ditto
created_at: 2025-05-06T02:29:14Z
author_association: OWNER
diff_hunk: @@ -178,39 +177,37 @@ def assemble_xbar_pkt():
       if s.init_mem_done != b1(0):
         for i in range(num_rd_tiles):
           recv_raddr = s.recv_raddr[i].msg
-          # Calculates the target bank index.
+          # Calculates the target bank index for load.
           if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
-            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+            bank_index_load_local = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
-            bank_index = XbarOutRdType(num_banks_per_cgra)
+            bank_index_load_local = XbarOutRdType(num_banks_per_cgra)
           # FIXME: change to exact tile id.
-          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, s.cgra_id, 0)
+          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index_load_local, recv_raddr, s.cgra_id, 0)
 
         recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr
         # Calculates the target bank index.
         if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper):
-          bank_index = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+          bank_index_load_from_noc = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
         else:
-          bank_index = XbarOutRdType(num_banks_per_cgra)
-        src_cgra_id = s.recv_from_noc_load_request.msg.src
-        src_tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
-        s.rd_pkt[num_rd_tiles] @= TileSramXbarRdPktType(num_rd_tiles, bank_index, recv_raddr_from_noc, src_cgra_id, src_tile_id)
+          bank_index_load_from_noc = XbarOutRdType(num_banks_per_cgra)
+        s.rd_pkt[num_rd_tiles] @= TileSramXbarRdPktType(num_rd_tiles, bank_index_load_from_noc, recv_raddr_from_noc, s.recv_from_noc_load_request.msg.src, s.recv_from_noc_load_request.msg.src_tile_id)
 
         for i in range(num_wr_tiles):
           recv_waddr = s.recv_waddr[i].msg
-          # Calculates the target bank index.
+          # Calculates the target bank index for store.
           if (recv_waddr >= s.address_lower) & (recv_waddr <= s.address_upper):
-            bank_index = trunc((recv_waddr - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType)
+            bank_index_store_local = trunc((recv_waddr - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType)
           else:
-            bank_index = XbarOutWrType(num_banks_per_cgra)
-          s.wr_pkt[i] @= TileSramXbarWrPktType(i, bank_index, recv_waddr, 0, 0)
+            bank_index_store_local = XbarOutWrType(num_banks_per_cgra)
+          s.wr_pkt[i] @= TileSramXbarWrPktType(i, bank_index_store_local, recv_waddr, 0, 0)
 
         recv_waddr_from_noc = s.recv_from_noc_store_request.msg.payload.data_addr
         if (recv_waddr_from_noc >= s.address_lower) & (recv_waddr_from_noc <= s.address_upper):
-          bank_index = trunc((recv_waddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType)
+          bank_index_store_from_noc = trunc((recv_waddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType)
         else:
-          bank_index = XbarOutWrType(num_banks_per_cgra)
-        s.wr_pkt[num_wr_tiles] @= TileSramXbarWrPktType(num_wr_tiles, bank_index, recv_waddr_from_noc, 0, 0)
+          bank_index_store_from_noc = XbarOutWrType(num_banks_per_cgra)
+        s.wr_pkt[num_wr_tiles] @= TileSramXbarWrPktType(num_wr_tiles, bank_index_store_from_noc, recv_waddr_from_noc, 0, 0)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: ditto
created_at: 2025-05-06T02:29:23Z
author_association: OWNER
diff_hunk: @@ -178,39 +177,37 @@ def assemble_xbar_pkt():
       if s.init_mem_done != b1(0):
         for i in range(num_rd_tiles):
           recv_raddr = s.recv_raddr[i].msg
-          # Calculates the target bank index.
+          # Calculates the target bank index for load.
           if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
-            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+            bank_index_load_local = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
-            bank_index = XbarOutRdType(num_banks_per_cgra)
+            bank_index_load_local = XbarOutRdType(num_banks_per_cgra)
           # FIXME: change to exact tile id.
-          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, s.cgra_id, 0)
+          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index_load_local, recv_raddr, s.cgra_id, 0)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: tancheng
body: Break this long line and align the fields.
created_at: 2025-05-06T02:29:35Z
author_association: OWNER
diff_hunk: @@ -178,39 +177,37 @@ def assemble_xbar_pkt():
       if s.init_mem_done != b1(0):
         for i in range(num_rd_tiles):
           recv_raddr = s.recv_raddr[i].msg
-          # Calculates the target bank index.
+          # Calculates the target bank index for load.
           if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper):
-            bank_index = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+            bank_index_load_local = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
           else:
-            bank_index = XbarOutRdType(num_banks_per_cgra)
+            bank_index_load_local = XbarOutRdType(num_banks_per_cgra)
           # FIXME: change to exact tile id.
-          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index, recv_raddr, s.cgra_id, 0)
+          s.rd_pkt[i] @= TileSramXbarRdPktType(i, bank_index_load_local, recv_raddr, s.cgra_id, 0)
 
         recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr
         # Calculates the target bank index.
         if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper):
-          bank_index = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
+          bank_index_load_from_noc = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType)
         else:
-          bank_index = XbarOutRdType(num_banks_per_cgra)
-        src_cgra_id = s.recv_from_noc_load_request.msg.src
-        src_tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
-        s.rd_pkt[num_rd_tiles] @= TileSramXbarRdPktType(num_rd_tiles, bank_index, recv_raddr_from_noc, src_cgra_id, src_tile_id)
+          bank_index_load_from_noc = XbarOutRdType(num_banks_per_cgra)
+        s.rd_pkt[num_rd_tiles] @= TileSramXbarRdPktType(num_rd_tiles, bank_index_load_from_noc, recv_raddr_from_noc, s.recv_from_noc_load_request.msg.src, s.recv_from_noc_load_request.msg.src_tile_id)
path: mem/data/DataMemWithCrossbarRTL.py
user: login: yuqisun
body: Done.
created_at: 2025-05-06T03:04:11Z
author_association: COLLABORATOR

PR comments:
user: login: tancheng
created_at: 2025-04-23T18:04:14Z
body: > Replace `addr/src_cgra/src_tile `of `load_request` with one NoC pkt to reduce the interfaces.
> 
> Will clean comments once all good. @tancheng , are we going to do same replacement for `store_request`?

Right. We should. Otherwise, misalighed and confusing.
author_association: OWNER
user: login: tancheng
created_at: 2025-04-27T15:21:20Z
body: Looks like the current commit fails due to lack of enough fields during initializing a data struct?
author_association: OWNER
user: login: yuqisun
created_at: 2025-04-27T15:27:34Z
body: > Looks like the current commit fails due to lack of enough fields during initializing a data struct?

Thanks for enlighten, let me check, how did you infer the root cause?
In log, it fails in `MeshMultiCgraRTL_test` with below, thought similar as before - some Type didn't put `0, 0 ...` in it.

```
    assert False, f"unrecognized datatype instance {instance}"
E   AssertionError: unrecognized datatype instance [Bits3(0x0), Bits3(0x0), Bits3(0x0), Bits3(0x0)]
```
author_association: COLLABORATOR
user: login: tancheng
created_at: 2025-04-27T15:30:05Z
body: > > Looks like the current commit fails due to lack of enough fields during initializing a data struct?
> 
> Thanks for enlighten, let me check, how did you infer the root cause? In log, it fails in `MeshMultiCgraRTL_test` with below, thought similar as before - some Type didn't put `0, 0 ...` in it.
> 
> ```
>     assert False, f"unrecognized datatype instance {instance}"
> E   AssertionError: unrecognized datatype instance [Bits3(0x0), Bits3(0x0), Bits3(0x0), Bits3(0x0)]
> ```

Yes, we are talking about the same thing. Plz check the data structs you used around the new interfaces, especially the data pkts related to the sram xbars.
author_association: OWNER
user: login: yuqisun
created_at: 2025-04-29T15:50:09Z
body: Hi @tancheng,

Got a question and could you help confirm. In PyMTL, actually all variables' bit width are pre-defined, right, even the index of the for loop.

i.e. For below code, `num_xbar_in_rd_ports = 3` and size of `s.recv_raddr` array is 2. It throws `E   - expects a 1-bit index but the given index has more (2) bits!`

So I repeat the find bank by addr code here, and I tried to create a function, but looks cannot use function in PyMTL in `--test-verilog`? Any better idea about such scenario?

```
for i in range(num_xbar_in_rd_ports):
  if i == num_xbar_in_rd_ports - 1:
    recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
    cgra_id = s.recv_from_noc_load_request.msg.src
    tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
  else:
    recv_raddr = s.recv_raddr[i].msg
```

Exception:
```
E   pymtl3.passes.rtlir.errors.PyMTLTypeError: 
E   In file /home/syq/cgra/VectorCGRA/mem/data/DataMemWithCrossbarRTL.py, Line 193, Col 25:
E     recv_raddr = s.recv_raddr[i].msg
E                  ^
E   - expects a 1-bit index but the given index has more (2) bits!
```

Function call exception:
```
E   pymtl3.passes.rtlir.errors.PyMTLSyntaxError: 
E   In file /home/syq/cgra/VectorCGRA/mem/data/DataMemWithCrossbarRTL.py, Line 189, Col 23:
E     bank_index = s.find_bank_index_by_addr(recv_raddr, s.address_lower, s.address_upper,
E                  ^
E   - <ast.Attribute object at 0x7f1f75d9fa90> function is not found!
```
author_association: COLLABORATOR
user: login: tancheng
created_at: 2025-04-29T16:21:27Z
body: > Hi @tancheng,
> 
> Got a question and could you help confirm. In PyMTL, actually all variables' bit width are pre-defined, right, even the index of the for loop.
> 
> i.e. For below code, `num_xbar_in_rd_ports = 3` and size of `s.recv_raddr` array is 2. It throws `E - expects a 1-bit index but the given index has more (2) bits!`
> 
> So I repeat the find bank by addr code here, and I tried to create a function, but looks cannot use function in PyMTL in `--test-verilog`? Any better idea about such scenario?
> 
> ```
> for i in range(num_xbar_in_rd_ports):
>   if i == num_xbar_in_rd_ports - 1:
>     recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
>     cgra_id = s.recv_from_noc_load_request.msg.src
>     tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
>   else:
>     recv_raddr = s.recv_raddr[i].msg
> ```
> 
> Exception:
> 
> ```
> E   pymtl3.passes.rtlir.errors.PyMTLTypeError: 
> E   In file /home/syq/cgra/VectorCGRA/mem/data/DataMemWithCrossbarRTL.py, Line 193, Col 25:
> E     recv_raddr = s.recv_raddr[i].msg
> E                  ^
> E   - expects a 1-bit index but the given index has more (2) bits!
> ```
> 
> Function call exception:
> 
> ```
> E   pymtl3.passes.rtlir.errors.PyMTLSyntaxError: 
> E   In file /home/syq/cgra/VectorCGRA/mem/data/DataMemWithCrossbarRTL.py, Line 189, Col 23:
> E     bank_index = s.find_bank_index_by_addr(recv_raddr, s.address_lower, s.address_upper,
> E                  ^
> E   - <ast.Attribute object at 0x7f1f75d9fa90> function is not found!
> ```

 - Function is not well supported I think (@yo96 for confirmation), especially for translation to Verilog.
 - Your current change (`for i in range(num_xbar_in_rd_ports)` -> `for i in range(num_rd_tiles)`) looks good to me. You can special handle the last `recv_raddr[-1]`, if there is bit-width issue, you can try to leverage extend? Can you update your code (remove `s. find_bank_index_by_addr()` and rename the variables as I mentioned) and clarify if there is still bitwidth mismatch?
author_association: OWNER
user: login: yuqisun
created_at: 2025-04-29T22:30:31Z
body: > > Hi @tancheng,
> > Got a question and could you help confirm. In PyMTL, actually all variables' bit width are pre-defined, right, even the index of the for loop.
> > i.e. For below code, `num_xbar_in_rd_ports = 3` and size of `s.recv_raddr` array is 2. It throws `E - expects a 1-bit index but the given index has more (2) bits!`
> > So I repeat the find bank by addr code here, and I tried to create a function, but looks cannot use function in PyMTL in `--test-verilog`? Any better idea about such scenario?
> > ```
> > for i in range(num_xbar_in_rd_ports):
> >   if i == num_xbar_in_rd_ports - 1:
> >     recv_raddr = s.recv_from_noc_load_request.msg.payload.data_addr
> >     cgra_id = s.recv_from_noc_load_request.msg.src
> >     tile_id = TileIdType(s.recv_from_noc_load_request.msg.src_tile_id)
> >   else:
> >     recv_raddr = s.recv_raddr[i].msg
> > ```
> > 
> > 
> >     
> >       
> >     
> > 
> >       
> >     
> > 
> >     
> >   
> > Exception:
> > ```
> > E   pymtl3.passes.rtlir.errors.PyMTLTypeError: 
> > E   In file /home/syq/cgra/VectorCGRA/mem/data/DataMemWithCrossbarRTL.py, Line 193, Col 25:
> > E     recv_raddr = s.recv_raddr[i].msg
> > E                  ^
> > E   - expects a 1-bit index but the given index has more (2) bits!
> > ```
> > 
> > 
> >     
> >       
> >     
> > 
> >       
> >     
> > 
> >     
> >   
> > Function call exception:
> > ```
> > E   pymtl3.passes.rtlir.errors.PyMTLSyntaxError: 
> > E   In file /home/syq/cgra/VectorCGRA/mem/data/DataMemWithCrossbarRTL.py, Line 189, Col 23:
> > E     bank_index = s.find_bank_index_by_addr(recv_raddr, s.address_lower, s.address_upper,
> > E                  ^
> > E   - <ast.Attribute object at 0x7f1f75d9fa90> function is not found!
> > ```
> 
>     * Function is not well supported I think (@yo96 for confirmation), especially for translation to Verilog.
> 
>     * Your current change (`for i in range(num_xbar_in_rd_ports)` -> `for i in range(num_rd_tiles)`) looks good to me. You can special handle the last `recv_raddr[-1]`, if there is bit-width issue, you can try to leverage extend? Can you update your code (remove `s. find_bank_index_by_addr()` and rename the variables as I mentioned) and clarify if there is still bitwidth mismatch?

Yes, the bitwidth mismatch issue can be fixed by change (`for i in range(num_xbar_in_rd_ports)` -> `for i in range(num_rd_tiles)`). Current issue is [this](https://github.com/tancheng/VectorCGRA/pull/141?notification_referrer_id=NT_kwDOAHY6MbMxNjAzMDA1MTQ5Mjo3NzQ4MTQ1#discussion_r2066873791)(pytest good, verilog test fail) even variables renamed.
author_association: COLLABORATOR
user: login: tancheng
created_at: 2025-04-30T17:42:35Z
body: Plz search all `-1` in the repo, and fix them all, thanks~!
author_association: OWNER
user: login: yuqisun
created_at: 2025-05-01T06:51:04Z
body: > Plz search all `-1` in the repo, and fix them all, thanks~!

Done and issue got fixed in my local test, building in Github. Some other `-1` are in pymtl3_net repo.
author_association: COLLABORATOR
user: login: tancheng
created_at: 2025-05-02T16:25:56Z
body: > > Plz search all `-1` in the repo, and fix them all, thanks~!
> 
> Done and issue got fixed in my local test, building in Github. Some other `-1` are in pymtl3_net repo.

So seems no other `-1` in our repo besides the files you touched in this PR.

Can you please copy the `Some other -1 are in pymtl3_net repo` here, @yo96 can help check whether they are okay.
author_association: OWNER
user: login: yuqisun
created_at: 2025-05-02T16:37:53Z
body: > > > Plz search all `-1` in the repo, and fix them all, thanks~!
> > 
> > 
> > Done and issue got fixed in my local test, building in Github. Some other `-1` are in pymtl3_net repo.
> 
> So seems no other `-1` in our repo besides the files you touched in this PR.
> 
> Can you please copy the `Some other -1 are in pymtl3_net repo` here, @yo96 can help check whether they are okay.

Yes, please help review below:

1. [ChannelCL.py#L48-L49](https://github.com/tancheng/PyOCN/blob/299d2d475d7dcaae18c9d5d5cc9428d3de443d64/pymtl3_net/channel/ChannelCL.py#L48-L49)

        if s.queues[-1].deq.rdy() and s.send.rdy():
          s.send( s.queues[-1].deq() )

2. [ChannelRTL.py#L50](https://github.com/tancheng/PyOCN/blob/299d2d475d7dcaae18c9d5d5cc9428d3de443d64/pymtl3_net/channel/ChannelRTL.py#L50)

      s.queues[-1].send //= s.send

3. [commons.py#L63](https://github.com/tancheng/PyOCN/blob/299d2d475d7dcaae18c9d5d5cc9428d3de443d64/pymtl3_net/ocnlib/utils/commons.py#L63)

    start = 0 if not slices else slices[-1].stop

4.1. [connects.py#L23](https://github.com/tancheng/PyOCN/blob/299d2d475d7dcaae18c9d5d5cc9428d3de443d64/pymtl3_net/ocnlib/utils/connects.py#L23)

    start = 0 if not slices else slices[-1].stop

4.2. [connects.py#L55](https://github.com/tancheng/PyOCN/blob/299d2d475d7dcaae18c9d5d5cc9428d3de443d64/pymtl3_net/ocnlib/utils/connects.py#L55)

    start     = 0 if not slices else slices[-1].stop


author_association: COLLABORATOR
user: login: tancheng
created_at: 2025-05-03T07:03:55Z
body: > > > > Plz search all `-1` in the repo, and fix them all, thanks~!
> > > 
> > > 
> > > Done and issue got fixed in my local test, building in Github. Some other `-1` are in pymtl3_net repo.
> > 
> > 
> > So seems no other `-1` in our repo besides the files you touched in this PR.
> > Can you please copy the `Some other -1 are in pymtl3_net repo` here, @yo96 can help check whether they are okay.
> 
> Yes, please help review below:
> 
> 1. [ChannelCL.py#L48-L49](https://github.com/tancheng/PyOCN/blob/299d2d475d7dcaae18c9d5d5cc9428d3de443d64/pymtl3_net/channel/ChannelCL.py#L48-L49)
>    ```
>     if s.queues[-1].deq.rdy() and s.send.rdy():
>       s.send( s.queues[-1].deq() )
>    ```
> 2. [ChannelRTL.py#L50](https://github.com/tancheng/PyOCN/blob/299d2d475d7dcaae18c9d5d5cc9428d3de443d64/pymtl3_net/channel/ChannelRTL.py#L50)
>    s.queues[-1].send //= s.send
> 3. [commons.py#L63](https://github.com/tancheng/PyOCN/blob/299d2d475d7dcaae18c9d5d5cc9428d3de443d64/pymtl3_net/ocnlib/utils/commons.py#L63)
>    start = 0 if not slices else slices[-1].stop
> 
> 4.1. [connects.py#L23](https://github.com/tancheng/PyOCN/blob/299d2d475d7dcaae18c9d5d5cc9428d3de443d64/pymtl3_net/ocnlib/utils/connects.py#L23)
> 
> ```
> start = 0 if not slices else slices[-1].stop
> ```
> 
> 4.2. [connects.py#L55](https://github.com/tancheng/PyOCN/blob/299d2d475d7dcaae18c9d5d5cc9428d3de443d64/pymtl3_net/ocnlib/utils/connects.py#L55)
> 
> ```
> start     = 0 if not slices else slices[-1].stop
> ```

Hi @yuqisun, confirmed with @yo96 that all these `-1` is python-related. They are used to index the instantiated instances but won't participate in the behavior logic inside the update block, so it is okay.
author_association: OWNER
user: login: tancheng
created_at: 2025-05-06T03:43:38Z
body: @yuqisun feel free to merge. Thanks~!
author_association: OWNER