Repository: xdslproject/xdsl
Pull request #4429: dialects: (x86) migrate operations to consistent mnemonic
Author: login: superlopuh
Labels: name: dialects
description: Changes on the dialects
Created: 2025-05-20T10:24:06Z | Merged: 2025-05-22T07:44:12Z

This proved to be too weird, and also still ambiguous, as `imm` in the op name mnemonic could mean `immediate` or `inout`, `memory`, `memory`. Having one-letter mnemonics seems better. I'll propose a new letter for inout registers.


Diff:
diff --git a/tests/dialects/test_x86.py b/tests/dialects/test_x86.py
index e5fcc429e2..4ddca84b4a 100644
--- a/tests/dialects/test_x86.py
+++ b/tests/dialects/test_x86.py
@@ -164,13 +164,13 @@ def test_sse_register(register: x86.register.SSERegisterType, name: str):
     "OpClass, dest, operand1, operand2",
     [
         (
-            x86.ops.RRR_Vfmadd231pdOp,
+            x86.ops.RSS_Vfmadd231pdOp,
             x86.register.YMM0,
             x86.register.YMM1,
             x86.register.YMM2,
         ),
         (
-            x86.ops.RRR_Vfmadd231psOp,
+            x86.ops.RSS_Vfmadd231psOp,
             x86.register.YMM0,
             x86.register.YMM1,
             x86.register.YMM2,
@@ -179,7 +179,7 @@ def test_sse_register(register: x86.register.SSERegisterType, name: str):
 )
 def test_rrr_vops(
     OpClass: type[
-        x86.ops.RRROperation[
+        x86.ops.RSS_Operation[
             x86.register.X86VectorRegisterType,
             x86.register.X86VectorRegisterType,
             x86.register.X86VectorRegisterType,
@@ -192,22 +192,27 @@ def test_rrr_vops(
     output = x86.ops.GetAVXRegisterOp(dest)
     param1 = x86.ops.GetAVXRegisterOp(operand1)
     param2 = x86.ops.GetAVXRegisterOp(operand2)
-    op = OpClass(r3=output.result, r1=param1.result, r2=param2.result, result=dest)
-    assert op.r1.type == operand1
-    assert op.r2.type == operand2
-    assert op.r3.type == dest
+    op = OpClass(
+        source2=output.result,
+        register_in=param1.result,
+        source1=param2.result,
+        register_out=dest,
+    )
+    assert op.register_in.type == operand1
+    assert op.source1.type == operand2
+    assert op.source2.type == dest
 
 
 @pytest.mark.parametrize(
     "OpClass, dest, src",
     [
         (
-            x86.ops.MR_VmovupsOp,
+            x86.ops.MS_VmovupsOp,
             x86.register.RCX,
             x86.register.YMM0,
         ),
         (
-            x86.ops.MR_VmovapdOp,
+            x86.ops.MS_VmovapdOp,
             x86.register.RCX,
             x86.register.YMM0,
         ),
@@ -215,7 +220,7 @@ def test_rrr_vops(
 )
 def test_mr_vops(
     OpClass: type[
-        x86.ops.M_MR_Operation[
+        x86.ops.MS_Operation[
             x86.register.GeneralRegisterType, x86.register.X86VectorRegisterType
         ]
     ],
@@ -224,26 +229,26 @@ def test_mr_vops(
 ):
     output = x86.ops.GetRegisterOp(dest)
     input = x86.ops.GetAVXRegisterOp(src)
-    op = OpClass(r1=output, r2=input, offset=IntegerAttr(0, 64))
-    assert op.r1.type == dest
-    assert op.r2.type == src
+    op = OpClass(memory=output, source=input, memory_offset=IntegerAttr(0, 64))
+    assert op.memory.type == dest
+    assert op.source.type == src
 
 
 @pytest.mark.parametrize(
     "OpClass, dest, src",
     [
         (
-            x86.ops.RM_VmovupsOp,
+            x86.ops.DM_VmovupsOp,
             x86.register.YMM0,
             x86.register.RCX,
         ),
         (
-            x86.ops.RM_VbroadcastsdOp,
+            x86.ops.DM_VbroadcastsdOp,
             x86.register.YMM0,
             x86.register.RCX,
         ),
         (
-            x86.ops.RM_VbroadcastssOp,
+            x86.ops.DM_VbroadcastssOp,
             x86.register.YMM0,
             x86.register.RCX,
         ),
@@ -251,14 +256,14 @@ def test_mr_vops(
 )
 def test_rm_vops(
     OpClass: type[
-        x86.ops.R_M_Operation[
-            x86.register.GeneralRegisterType, x86.register.X86VectorRegisterType
+        x86.ops.DM_Operation[
+            x86.register.X86VectorRegisterType, x86.register.GeneralRegisterType
         ]
     ],
     dest: x86.register.X86VectorRegisterType,
     src: x86.register.GeneralRegisterType,
 ):
     input = x86.ops.GetRegisterOp(src)
-    op = OpClass(r1=input, result=dest, offset=IntegerAttr(0, 64))
-    assert op.r1.type == src
-    assert op.result.type == dest
+    op = OpClass(memory=input, destination=dest, memory_offset=IntegerAttr(0, 64))
+    assert op.memory.type == src
+    assert op.destination.type == dest
diff --git a/tests/filecheck/backend/x86/convert_func_to_x86.mlir b/tests/filecheck/backend/x86/convert_func_to_x86.mlir
index e09f60c203..cb30c5638a 100644
--- a/tests/filecheck/backend/x86/convert_func_to_x86.mlir
+++ b/tests/filecheck/backend/x86/convert_func_to_x86.mlir
@@ -11,7 +11,7 @@ func.func @foo_const() -> i32 {
 // CHECK-NEXT:      %1 = "test.op"() : () -> i32
 // CHECK-NEXT:      %2 = builtin.unrealized_conversion_cast %1 : i32 to !x86.reg
 // CHECK-NEXT:      %3 = x86.get_register : () -> !x86.reg<rax>
-// CHECK-NEXT:      %4 = x86.rr.mov %2, %3 : (!x86.reg, !x86.reg<rax>) -> !x86.reg<rax>
+// CHECK-NEXT:      %4 = x86.rs.mov %2, %3 : (!x86.reg, !x86.reg<rax>) -> !x86.reg<rax>
 // CHECK-NEXT:      x86_func.ret
 // CHECK-NEXT:    }
 // CHECK-NEXT:  }
@@ -38,9 +38,9 @@ func.func public @foo_int(%0: i32, %1: i32, %2: i32, %3: i32, %4: i32, %5: i32,
 // CHECK-NEXT:      %10 = builtin.unrealized_conversion_cast %3 : !x86.reg<rcx> to i32
 // CHECK-NEXT:      %11 = builtin.unrealized_conversion_cast %4 : !x86.reg<r8> to i32
 // CHECK-NEXT:      %12 = builtin.unrealized_conversion_cast %5 : !x86.reg<r9> to i32
-// CHECK-NEXT:      %13 = x86.rm.mov %6, 8 {comment = "Load the 7th argument of the function"} : (!x86.reg<rsp>) -> !x86.reg
+// CHECK-NEXT:      %13 = x86.dm.mov %6, 8 {comment = "Load the 7th argument of the function"} : (!x86.reg<rsp>) -> !x86.reg
 // CHECK-NEXT:      %14 = builtin.unrealized_conversion_cast %13 : !x86.reg to i32
-// CHECK-NEXT:      %15 = x86.rm.mov %6, 16 {comment = "Load the 8th argument of the function"} : (!x86.reg<rsp>) -> !x86.reg
+// CHECK-NEXT:      %15 = x86.dm.mov %6, 16 {comment = "Load the 8th argument of the function"} : (!x86.reg<rsp>) -> !x86.reg
 // CHECK-NEXT:      %16 = builtin.unrealized_conversion_cast %15 : !x86.reg to i32
 // CHECK-NEXT:      %a = "test.op"(%7, %8) : (i32, i32) -> i32
 // CHECK-NEXT:      %b = "test.op"(%a, %9) : (i32, i32) -> i32
@@ -51,7 +51,7 @@ func.func public @foo_int(%0: i32, %1: i32, %2: i32, %3: i32, %4: i32, %5: i32,
 // CHECK-NEXT:      %g = "test.op"(%f, %16) : (i32, i32) -> i32
 // CHECK-NEXT:      %17 = builtin.unrealized_conversion_cast %g : i32 to !x86.reg
 // CHECK-NEXT:      %18 = x86.get_register : () -> !x86.reg<rax>
-// CHECK-NEXT:      %19 = x86.rr.mov %17, %18 : (!x86.reg, !x86.reg<rax>) -> !x86.reg<rax>
+// CHECK-NEXT:      %19 = x86.rs.mov %17, %18 : (!x86.reg, !x86.reg<rax>) -> !x86.reg<rax>
 // CHECK-NEXT:      x86_func.ret
 // CHECK-NEXT:    }
 // CHECK-NEXT:  }
diff --git a/tests/filecheck/backend/x86/convert_ptr_to_x86.mlir b/tests/filecheck/backend/x86/convert_ptr_to_x86.mlir
index b22fcce8e2..cadd6d1544 100644
--- a/tests/filecheck/backend/x86/convert_ptr_to_x86.mlir
+++ b/tests/filecheck/backend/x86/convert_ptr_to_x86.mlir
@@ -5,7 +5,7 @@
 // CHECK:       builtin.module {
 // CHECK-NEXT:    %ptr0 = "test.op"() : () -> !ptr_xdsl.ptr
 // CHECK-NEXT:    %v0 = builtin.unrealized_conversion_cast %ptr0 : !ptr_xdsl.ptr to !x86.reg
-// CHECK-NEXT:    %v0_1 = x86.rm.vmovups %v0, 0 : (!x86.reg) -> !x86.avx2reg
+// CHECK-NEXT:    %v0_1 = x86.dm.vmovups %v0, 0 : (!x86.reg) -> !x86.avx2reg
 // CHECK-NEXT:    %v0_2 = builtin.unrealized_conversion_cast %v0_1 : !x86.avx2reg to vector<8xf32>
 // CHECK-NEXT:  }
 
@@ -16,7 +16,7 @@
 // CHECK:       builtin.module {
 // CHECK-NEXT:    %ptr0b = "test.op"() : () -> !ptr_xdsl.ptr
 // CHECK-NEXT:    %v0b = builtin.unrealized_conversion_cast %ptr0b : !ptr_xdsl.ptr to !x86.reg
-// CHECK-NEXT:    %v0b_1 = x86.rm.vmovups %v0b, 0 : (!x86.reg) -> !x86.avx512reg
+// CHECK-NEXT:    %v0b_1 = x86.dm.vmovups %v0b, 0 : (!x86.reg) -> !x86.avx512reg
 // CHECK-NEXT:    %v0b_2 = builtin.unrealized_conversion_cast %v0b_1 : !x86.avx512reg to vector<16xf32>
 // CHECK-NEXT:  }
 
@@ -61,7 +61,7 @@ ptr_xdsl.store %v6, %ptr6 : vector<8xf32>, !ptr_xdsl.ptr
 // CHECK-NEXT:   %v6 = "test.op"() : () -> vector<8xf32>
 // CHECK-NEXT:   %0 = builtin.unrealized_conversion_cast %ptr6 : !ptr_xdsl.ptr to !x86.reg
 // CHECK-NEXT:   %1 = builtin.unrealized_conversion_cast %v6 : vector<8xf32> to !x86.avx2reg
-// CHECK-NEXT:   x86.mr.vmovups %0, %1, 0 : (!x86.reg, !x86.avx2reg) -> ()
+// CHECK-NEXT:   x86.ms.vmovups %0, %1, 0 : (!x86.reg, !x86.avx2reg) -> ()
 // CHECK-NEXT: }
 
 // -----
@@ -75,7 +75,7 @@ ptr_xdsl.store %v6b, %ptr6b : vector<16xf32>, !ptr_xdsl.ptr
 // CHECK-NEXT:   %v6b = "test.op"() : () -> vector<16xf32>
 // CHECK-NEXT:   %0 = builtin.unrealized_conversion_cast %ptr6b : !ptr_xdsl.ptr to !x86.reg
 // CHECK-NEXT:   %1 = builtin.unrealized_conversion_cast %v6b : vector<16xf32> to !x86.avx512reg
-// CHECK-NEXT:   x86.mr.vmovups %0, %1, 0 : (!x86.reg, !x86.avx512reg) -> ()
+// CHECK-NEXT:   x86.ms.vmovups %0, %1, 0 : (!x86.reg, !x86.avx512reg) -> ()
 // CHECK-NEXT: }
 
 // -----
@@ -89,7 +89,7 @@ ptr_xdsl.store %v6, %ptr6 : vector<4xf64>, !ptr_xdsl.ptr
 // CHECK-NEXT:   %v6 = "test.op"() : () -> vector<4xf64>
 // CHECK-NEXT:   %0 = builtin.unrealized_conversion_cast %ptr6 : !ptr_xdsl.ptr to !x86.reg
 // CHECK-NEXT:   %1 = builtin.unrealized_conversion_cast %v6 : vector<4xf64> to !x86.avx2reg
-// CHECK-NEXT:   x86.mr.vmovapd %0, %1, 0 : (!x86.reg, !x86.avx2reg) -> ()
+// CHECK-NEXT:   x86.ms.vmovapd %0, %1, 0 : (!x86.reg, !x86.avx2reg) -> ()
 // CHECK-NEXT: }
 
 // -----
@@ -124,6 +124,6 @@ ptr_xdsl.store %v6, %ptr6 : f32, !ptr_xdsl.ptr
 // CHECK-NEXT:   %idx = "test.op"() : () -> index
 // CHECK-NEXT:   %r0 = builtin.unrealized_conversion_cast %p : !ptr_xdsl.ptr to !x86.reg
 // CHECK-NEXT:   %r0_1 = builtin.unrealized_conversion_cast %idx : index to !x86.reg
-// CHECK-NEXT:   %r0_2 = x86.rr.add %r0, %r0_1 : (!x86.reg, !x86.reg) -> !x86.reg
+// CHECK-NEXT:   %r0_2 = x86.rs.add %r0, %r0_1 : (!x86.reg, !x86.reg) -> !x86.reg
 // CHECK-NEXT:   %r0_3 = builtin.unrealized_conversion_cast %r0_2 : !x86.reg to !ptr_xdsl.ptr
 // CHECK-NEXT: }
diff --git a/tests/filecheck/backend/x86/convert_vector_to_x86.mlir b/tests/filecheck/backend/x86/convert_vector_to_x86.mlir
index c16d9912a6..be16b64059 100644
--- a/tests/filecheck/backend/x86/convert_vector_to_x86.mlir
+++ b/tests/filecheck/backend/x86/convert_vector_to_x86.mlir
@@ -12,7 +12,7 @@
 // CHECK-NEXT:   %fma = builtin.unrealized_conversion_cast %lhs : vector<8xf32> to !x86.avx2reg
 // CHECK-NEXT:   %fma_1 = builtin.unrealized_conversion_cast %rhs : vector<8xf32> to !x86.avx2reg
 // CHECK-NEXT:   %fma_2 = builtin.unrealized_conversion_cast %acc : vector<8xf32> to !x86.avx2reg
-// CHECK-NEXT:   %fma_3 = x86.rrr.vfmadd231ps %fma_2, %fma, %fma_1 : (!x86.avx2reg, !x86.avx2reg, !x86.avx2reg) -> !x86.avx2reg
+// CHECK-NEXT:   %fma_3 = x86.rss.vfmadd231ps %fma_2, %fma, %fma_1 : (!x86.avx2reg, !x86.avx2reg, !x86.avx2reg) -> !x86.avx2reg
 // CHECK-NEXT:   %fma_4 = builtin.unrealized_conversion_cast %fma_3 : !x86.avx2reg to vector<8xf32>
 // CHECK-NEXT: }
 
@@ -30,7 +30,7 @@
 // CHECK-NEXT:   %fma = builtin.unrealized_conversion_cast %lhs : vector<4xf64> to !x86.avx2reg
 // CHECK-NEXT:   %fma_1 = builtin.unrealized_conversion_cast %rhs : vector<4xf64> to !x86.avx2reg
 // CHECK-NEXT:   %fma_2 = builtin.unrealized_conversion_cast %acc : vector<4xf64> to !x86.avx2reg
-// CHECK-NEXT:   %fma_3 = x86.rrr.vfmadd231pd %fma_2, %fma, %fma_1 : (!x86.avx2reg, !x86.avx2reg, !x86.avx2reg) -> !x86.avx2reg
+// CHECK-NEXT:   %fma_3 = x86.rss.vfmadd231pd %fma_2, %fma, %fma_1 : (!x86.avx2reg, !x86.avx2reg, !x86.avx2reg) -> !x86.avx2reg
 // CHECK-NEXT:   %fma_4 = builtin.unrealized_conversion_cast %fma_3 : !x86.avx2reg to vector<4xf64>
 // CHECK-NEXT: }
 
diff --git a/tests/filecheck/dialects/x86/x86_assembly_emission.mlir b/tests/filecheck/dialects/x86/x86_assembly_emission.mlir
index 990b4afcfd..03180e8940 100644
--- a/tests/filecheck/dialects/x86/x86_assembly_emission.mlir
+++ b/tests/filecheck/dialects/x86/x86_assembly_emission.mlir
@@ -5,25 +5,25 @@
 %2 = x86.get_register : () -> !x86.reg<rcx>
 %rsp = x86.get_register : () -> !x86.reg<rsp>
 
-%rr_add = x86.rr.add %0, %1 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.reg<rax>
+%rr_add = x86.rs.add %0, %1 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.reg<rax>
 // CHECK: add rax, rdx
-%rr_sub = x86.rr.sub %0, %1 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.reg<rax>
+%rr_sub = x86.rs.sub %0, %1 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.reg<rax>
 // CHECK-NEXT: sub rax, rdx
-%rr_imul = x86.rr.imul %0, %1 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.reg<rax>
+%rr_imul = x86.rs.imul %0, %1 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.reg<rax>
 // CHECK-NEXT: imul rax, rdx
-%rr_and = x86.rr.and %0, %1 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.reg<rax>
+%rr_and = x86.rs.and %0, %1 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.reg<rax>
 // CHECK-NEXT: and rax, rdx
-%rr_or = x86.rr.or %0, %1 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.reg<rax>
+%rr_or = x86.rs.or %0, %1 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.reg<rax>
 // CHECK-NEXT: or rax, rdx
-%rr_xor = x86.rr.xor %0, %1 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.reg<rax>
+%rr_xor = x86.rs.xor %0, %1 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.reg<rax>
 // CHECK-NEXT: xor rax, rdx
-%rr_mov = x86.rr.mov %0, %1 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.reg<rax>
+%rr_mov = x86.rs.mov %0, %1 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.reg<rax>
 // CHECK-NEXT: mov rax, rdx
-%rr_cmp = x86.rr.cmp %0, %1 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.rflags<rflags>
+%rr_cmp = x86.ss.cmp %0, %1 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.rflags<rflags>
 // CHECK-NEXT: cmp rax, rdx
-%r_pushrsp = x86.r.push %rsp, %0 : (!x86.reg<rsp>, !x86.reg<rax>) -> !x86.reg<rsp>
+%r_pushrsp = x86.s.push %rsp, %0 : (!x86.reg<rsp>, !x86.reg<rax>) -> !x86.reg<rsp>
 // CHECK-NEXT: push rax
-%r_pop, %r_poprsp = x86.r.pop %rsp : (!x86.reg<rsp>) -> (!x86.reg<rax>, !x86.reg<rsp>)
+%r_poprsp, %r_pop = x86.d.pop %rsp : (!x86.reg<rsp>) -> (!x86.reg<rsp>, !x86.reg<rax>)
 // CHECK-NEXT: pop rax
 %r_neg = x86.r.neg %0 : (!x86.reg<rax>) -> !x86.reg<rax>
 // CHECK-NEXT: neg rax
@@ -34,9 +34,9 @@
 %r_dec = x86.r.dec %0 : (!x86.reg<rax>) -> !x86.reg<rax>
 // CHECK-NEXT: dec rax
 
-%r_idiv_rdx, %r_idiv_rax = x86.r.idiv %2, %1, %0 : (!x86.reg<rcx>, !x86.reg<rdx>, !x86.reg<rax>) -> (!x86.reg<rdx>, !x86.reg<rax>)
+%r_idiv_rdx, %r_idiv_rax = x86.s.idiv %2, %1, %0 : (!x86.reg<rcx>, !x86.reg<rdx>, !x86.reg<rax>) -> (!x86.reg<rdx>, !x86.reg<rax>)
 // CHECK-NEXT: idiv rcx
-%r_imul_rdx, %r_imul_rax = x86.r.imul %2, %0 : (!x86.reg<rcx>, !x86.reg<rax>) -> (!x86.reg<rdx>, !x86.reg<rax>)
+%r_imul_rdx, %r_imul_rax = x86.s.imul %2, %0 : (!x86.reg<rcx>, !x86.reg<rax>) -> (!x86.reg<rdx>, !x86.reg<rax>)
 // CHECK-NEXT: imul rcx
 
 %rm_add_no_offset = x86.rm.add %0, %1 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.reg<rax>
@@ -55,72 +55,72 @@
 // CHECK-NEXT: or rax, [rdx+8]
 %rm_xor = x86.rm.xor %0, %1, 8 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.reg<rax>
 // CHECK-NEXT: xor rax, [rdx+8]
-%rm_mov = x86.rm.mov %1, 8 : (!x86.reg<rdx>) -> !x86.reg<rax>
+%rm_mov = x86.dm.mov %1, 8 : (!x86.reg<rdx>) -> !x86.reg<rax>
 // CHECK-NEXT: mov rax, [rdx+8]
-%rm_cmp = x86.rm.cmp %0, %1, 8 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.rflags<rflags>
+%rm_cmp = x86.sm.cmp %0, %1, 8 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.rflags<rflags>
 // CHECK-NEXT: cmp rax, [rdx+8]
-%rm_lea = x86.rm.lea %0, %1, 8 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.reg<rax>
+%rm_lea = x86.dm.lea %1, 8 : (!x86.reg<rdx>) -> !x86.reg<rax>
 // CHECK-NEXT: lea rax, [rdx+8]
 
-%ri_add = x86.rimm.add %0, 2 : (!x86.reg<rax>) -> !x86.reg<rax>
+%ri_add = x86.ri.add %0, 2 : (!x86.reg<rax>) -> !x86.reg<rax>
 // CHECK-NEXT: add rax, 2
-%ri_sub = x86.rimm.sub %0, 2 : (!x86.reg<rax>) -> !x86.reg<rax>
+%ri_sub = x86.ri.sub %0, 2 : (!x86.reg<rax>) -> !x86.reg<rax>
 // CHECK-NEXT: sub rax, 2
-%ri_and = x86.rimm.and %0, 2 : (!x86.reg<rax>) -> !x86.reg<rax>
+%ri_and = x86.ri.and %0, 2 : (!x86.reg<rax>) -> !x86.reg<rax>
 // CHECK-NEXT: and rax, 2
-%ri_or = x86.rimm.or %0, 2 : (!x86.reg<rax>) -> !x86.reg<rax>
+%ri_or = x86.ri.or %0, 2 : (!x86.reg<rax>) -> !x86.reg<rax>
 // CHECK-NEXT: or rax, 2
-%ri_xor = x86.rimm.xor %0, 2 : (!x86.reg<rax>) -> !x86.reg<rax>
+%ri_xor = x86.ri.xor %0, 2 : (!x86.reg<rax>) -> !x86.reg<rax>
 // CHECK-NEXT: xor rax, 2
-%ri_mov = x86.rimm.mov %0, 2 : (!x86.reg<rax>) -> !x86.reg<rax>
+%ri_mov = x86.ri.mov %0, 2 : (!x86.reg<rax>) -> !x86.reg<rax>
 // CHECK-NEXT: mov rax, 2
-%ri_cmp = x86.rimm.cmp %0, 2 : (!x86.reg<rax>) -> !x86.rflags<rflags>
+%ri_cmp = x86.si.cmp %0, 2 : (!x86.reg<rax>) -> !x86.rflags<rflags>
 // CHECK-NEXT: cmp rax, 2
 
-x86.mr.add %0, %1 : (!x86.reg<rax>, !x86.reg<rdx>) -> ()
+x86.ms.add %0, %1 : (!x86.reg<rax>, !x86.reg<rdx>) -> ()
 // CHECK-NEXT: add [rax], rdx
-x86.mr.add %0, %1, 8 : (!x86.reg<rax>, !x86.reg<rdx>) -> ()
+x86.ms.add %0, %1, 8 : (!x86.reg<rax>, !x86.reg<rdx>) -> ()
 // CHECK-NEXT: add [rax+8], rdx
-x86.mr.sub %0, %1, -8 : (!x86.reg<rax>, !x86.reg<rdx>) -> ()
+x86.ms.sub %0, %1, -8 : (!x86.reg<rax>, !x86.reg<rdx>) -> ()
 // CHECK-NEXT: sub [rax-8], rdx
-x86.mr.and %0, %1, 8 : (!x86.reg<rax>, !x86.reg<rdx>) -> ()
+x86.ms.and %0, %1, 8 : (!x86.reg<rax>, !x86.reg<rdx>) -> ()
 // CHECK-NEXT: and [rax+8], rdx
-x86.mr.or %0, %1, 8 : (!x86.reg<rax>, !x86.reg<rdx>) -> ()
+x86.ms.or %0, %1, 8 : (!x86.reg<rax>, !x86.reg<rdx>) -> ()
 // CHECK-NEXT: or [rax+8], rdx
-x86.mr.xor %0, %1, 8 : (!x86.reg<rax>, !x86.reg<rdx>) -> ()
+x86.ms.xor %0, %1, 8 : (!x86.reg<rax>, !x86.reg<rdx>) -> ()
 // CHECK-NEXT: xor [rax+8], rdx
-x86.mr.mov %0, %1, 8 : (!x86.reg<rax>, !x86.reg<rdx>) -> ()
+x86.ms.mov %0, %1, 8 : (!x86.reg<rax>, !x86.reg<rdx>) -> ()
 // CHECK-NEXT: mov [rax+8], rdx
-%mr_cmp = x86.mr.cmp %0, %1, 8 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.rflags<rflags>
+%mr_cmp = x86.ms.cmp %0, %1, 8 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.rflags<rflags>
 // CHECK-NEXT: cmp [rax+8], rdx
 
-x86.mimm.add %0, 2, 0 : (!x86.reg<rax>) -> ()
+x86.mi.add %0, 2, 0 : (!x86.reg<rax>) -> ()
 // CHECK-NEXT: add [rax], 2
-x86.mimm.add %0, 2 : (!x86.reg<rax>) -> ()
+x86.mi.add %0, 2 : (!x86.reg<rax>) -> ()
 // CHECK-NEXT: add [rax], 2
-x86.mimm.add %0, 2, 8 : (!x86.reg<rax>) -> ()
+x86.mi.add %0, 2, 8 : (!x86.reg<rax>) -> ()
 // CHECK-NEXT: add [rax+8], 2
-x86.mimm.sub %0, 2, -8 : (!x86.reg<rax>) -> ()
+x86.mi.sub %0, 2, -8 : (!x86.reg<rax>) -> ()
 // CHECK-NEXT: sub [rax-8], 2
-x86.mimm.and %0, 2, 8 : (!x86.reg<rax>) -> ()
+x86.mi.and %0, 2, 8 : (!x86.reg<rax>) -> ()
 // CHECK-NEXT: and [rax+8], 2
-x86.mimm.or %0, 2, 8 : (!x86.reg<rax>) -> ()
+x86.mi.or %0, 2, 8 : (!x86.reg<rax>) -> ()
 // CHECK-NEXT: or [rax+8], 2
-x86.mimm.xor %0, 2, 8 : (!x86.reg<rax>) -> ()
+x86.mi.xor %0, 2, 8 : (!x86.reg<rax>) -> ()
 // CHECK-NEXT: xor [rax+8], 2
-x86.mimm.mov %0, 2, 8 : (!x86.reg<rax>) -> ()
+x86.mi.mov %0, 2, 8 : (!x86.reg<rax>) -> ()
 // CHECK-NEXT: mov [rax+8], 2
-%mi_cmp = x86.mimm.cmp %0, 2, 8 : (!x86.reg<rax>) -> !x86.rflags<rflags>
+%mi_cmp = x86.mi.cmp %0, 2, 8 : (!x86.reg<rax>) -> !x86.rflags<rflags>
 // CHECK-NEXT: cmp [rax+8], 2
 
-%rri_imul = x86.rri.imul %1, 2 : (!x86.reg<rdx>) -> !x86.reg<rax>
+%rri_imul = x86.dsi.imul %1, 2 : (!x86.reg<rdx>) -> !x86.reg<rax>
 // CHECK-NEXT: imul rax, rdx, 2
 
-%rmi_imul_no_offset = x86.rmimm.imul %1, 2 : (!x86.reg<rdx>) -> !x86.reg<rax>
+%rmi_imul_no_offset = x86.dmi.imul %1, 2 : (!x86.reg<rdx>) -> !x86.reg<rax>
 // CHECK-NEXT: imul rax, [rdx], 2
-%rmi_imul_offset_zero = x86.rmimm.imul %1, 2, 0 : (!x86.reg<rdx>) -> !x86.reg<rax>
+%rmi_imul_offset_zero = x86.dmi.imul %1, 2, 0 : (!x86.reg<rdx>) -> !x86.reg<rax>
 // CHECK-NEXT: imul rax, [rdx], 2
-%rmi_imul = x86.rmimm.imul %1, 2, 8 : (!x86.reg<rdx>) -> !x86.reg<rax>
+%rmi_imul = x86.dmi.imul %1, 2, 8 : (!x86.reg<rdx>) -> !x86.reg<rax>
 // CHECK-NEXT: imul rax, [rdx+8], 2
 
 %m_push_rsp = x86.m.push %rsp, %0 : (!x86.reg<rsp>, !x86.reg<rax>) -> !x86.reg<rsp>
@@ -163,7 +163,7 @@ x86.label "label"
 x86_func.func @funcyasm() {
     %3 = x86.get_register : () -> !x86.reg<rax>
     %4 = x86.get_register : () -> !x86.reg<rdx>
-    %rflags = x86.rr.cmp %3, %4 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.rflags<rflags>
+    %rflags = x86.ss.cmp %3, %4 : (!x86.reg<rax>, !x86.reg<rdx>) -> !x86.rflags<rflags>
     // CHECK: cmp rax, rdx
 
     x86.c.jmp ^then(%arg : !x86.reg)
@@ -330,75 +330,75 @@ x86_func.func @funcyasm() {
 %xmm1 = x86.get_avx_register : () -> !x86.ssereg<xmm1>
 %xmm2 = x86.get_avx_register : () -> !x86.ssereg<xmm2>
 
-%rrr_vfmadd231pd_sse = x86.rrr.vfmadd231pd %xmm0, %xmm1, %xmm2 : (!x86.ssereg<xmm0>, !x86.ssereg<xmm1>, !x86.ssereg<xmm2>) -> !x86.ssereg<xmm0>
+%rrr_vfmadd231pd_sse = x86.rss.vfmadd231pd %xmm0, %xmm1, %xmm2 : (!x86.ssereg<xmm0>, !x86.ssereg<xmm1>, !x86.ssereg<xmm2>) -> !x86.ssereg<xmm0>
 // CHECK: vfmadd231pd xmm0, xmm1, xmm2
-%rr_vmovapd_sse = x86.rr.vmovapd %xmm0, %xmm1 : (!x86.ssereg<xmm0>, !x86.ssereg<xmm1>) -> !x86.ssereg<xmm0>
+%rr_vmovapd_sse = x86.rs.vmovapd %xmm0, %xmm1 : (!x86.ssereg<xmm0>, !x86.ssereg<xmm1>) -> !x86.ssereg<xmm0>
 // CHECK-NEXT: vmovapd xmm0, xmm1
-x86.mr.vmovapd %0, %xmm1, 0 : (!x86.reg<rax>, !x86.ssereg<xmm1>) -> ()
+x86.ms.vmovapd %0, %xmm1, 0 : (!x86.reg<rax>, !x86.ssereg<xmm1>) -> ()
 // CHECK-NEXT: vmovapd [rax], xmm1
-x86.mr.vmovapd %0, %xmm1, 8 : (!x86.reg<rax>, !x86.ssereg<xmm1>) -> ()
+x86.ms.vmovapd %0, %xmm1, 8 : (!x86.reg<rax>, !x86.ssereg<xmm1>) -> ()
 // CHECK-NEXT: vmovapd [rax+8], xmm1
-%rm_vbroadcastsd_sse0 = x86.rm.vbroadcastsd %1, 0 : (!x86.reg<rdx>) -> !x86.ssereg<xmm0>
+%rm_vbroadcastsd_sse0 = x86.dm.vbroadcastsd %1, 0 : (!x86.reg<rdx>) -> !x86.ssereg<xmm0>
 // CHECK-NEXT: vbroadcastsd xmm0, [rdx]
-%rm_vbroadcastsd_sse = x86.rm.vbroadcastsd %1, 8 : (!x86.reg<rdx>) -> !x86.ssereg<xmm0>
+%rm_vbroadcastsd_sse = x86.dm.vbroadcastsd %1, 8 : (!x86.reg<rdx>) -> !x86.ssereg<xmm0>
 // CHECK-NEXT: vbroadcastsd xmm0, [rdx+8]
 
 %ymm0 = x86.get_avx_register : () -> !x86.avx2reg<ymm0>
 %ymm1 = x86.get_avx_register : () -> !x86.avx2reg<ymm1>
 %ymm2 = x86.get_avx_register : () -> !x86.avx2reg<ymm2>
 
-%rrr_vfmadd231pd_avx2 = x86.rrr.vfmadd231pd %ymm0, %ymm1, %ymm2 : (!x86.avx2reg<ymm0>, !x86.avx2reg<ymm1>, !x86.avx2reg<ymm2>) -> !x86.avx2reg<ymm0>
+%rrr_vfmadd231pd_avx2 = x86.rss.vfmadd231pd %ymm0, %ymm1, %ymm2 : (!x86.avx2reg<ymm0>, !x86.avx2reg<ymm1>, !x86.avx2reg<ymm2>) -> !x86.avx2reg<ymm0>
 // CHECK: vfmadd231pd ymm0, ymm1, ymm2
-%rr_vmovapd_avx2 = x86.rr.vmovapd %ymm0, %ymm1 : (!x86.avx2reg<ymm0>, !x86.avx2reg<ymm1>) -> !x86.avx2reg<ymm0>
+%rr_vmovapd_avx2 = x86.rs.vmovapd %ymm0, %ymm1 : (!x86.avx2reg<ymm0>, !x86.avx2reg<ymm1>) -> !x86.avx2reg<ymm0>
 // CHECK-NEXT: vmovapd ymm0, ymm1
-x86.mr.vmovapd %0, %ymm1, 8 : (!x86.reg<rax>, !x86.avx2reg<ymm1>) -> ()
+x86.ms.vmovapd %0, %ymm1, 8 : (!x86.reg<rax>, !x86.avx2reg<ymm1>) -> ()
 // CHECK-NEXT: vmovapd [rax+8], ymm1
-%rm_vbroadcastsd_avx20 = x86.rm.vbroadcastsd %1, 0 : (!x86.reg<rdx>) -> !x86.avx2reg<ymm0>
+%rm_vbroadcastsd_avx20 = x86.dm.vbroadcastsd %1, 0 : (!x86.reg<rdx>) -> !x86.avx2reg<ymm0>
 // CHECK-NEXT: vbroadcastsd ymm0, [rdx]
-%rm_vbroadcastsd_avx2 = x86.rm.vbroadcastsd %1, 8 : (!x86.reg<rdx>) -> !x86.avx2reg<ymm0>
+%rm_vbroadcastsd_avx2 = x86.dm.vbroadcastsd %1, 8 : (!x86.reg<rdx>) -> !x86.avx2reg<ymm0>
 // CHECK-NEXT: vbroadcastsd ymm0, [rdx+8]
 
 %zmm0 = x86.get_avx_register : () -> !x86.avx512reg<zmm0>
 %zmm1 = x86.get_avx_register : () -> !x86.avx512reg<zmm1>
 %zmm2 = x86.get_avx_register : () -> !x86.avx512reg<zmm2>
 
-%rrr_vfmadd231pd_avx512 = x86.rrr.vfmadd231pd %zmm0, %zmm1, %zmm2 : (!x86.avx512reg<zmm0>, !x86.avx512reg<zmm1>, !x86.avx512reg<zmm2>) -> !x86.avx512reg<zmm0>
+%rrr_vfmadd231pd_avx512 = x86.rss.vfmadd231pd %zmm0, %zmm1, %zmm2 : (!x86.avx512reg<zmm0>, !x86.avx512reg<zmm1>, !x86.avx512reg<zmm2>) -> !x86.avx512reg<zmm0>
 // CHECK: vfmadd231pd zmm0, zmm1, zmm2
-%rr_vmovapd_avx512 = x86.rr.vmovapd %zmm0, %zmm1 : (!x86.avx512reg<zmm0>, !x86.avx512reg<zmm1>) -> !x86.avx512reg<zmm0>
+%rr_vmovapd_avx512 = x86.rs.vmovapd %zmm0, %zmm1 : (!x86.avx512reg<zmm0>, !x86.avx512reg<zmm1>) -> !x86.avx512reg<zmm0>
 // CHECK-NEXT: vmovapd zmm0, zmm1
-x86.mr.vmovapd %0, %zmm1, 0 : (!x86.reg<rax>, !x86.avx512reg<zmm1>) -> ()
+x86.ms.vmovapd %0, %zmm1, 0 : (!x86.reg<rax>, !x86.avx512reg<zmm1>) -> ()
 // CHECK-NEXT: vmovapd [rax], zmm1
-x86.mr.vmovapd %0, %zmm1, 8 : (!x86.reg<rax>, !x86.avx512reg<zmm1>) -> ()
+x86.ms.vmovapd %0, %zmm1, 8 : (!x86.reg<rax>, !x86.avx512reg<zmm1>) -> ()
 // CHECK-NEXT: vmovapd [rax+8], zmm1
-%rm_vbroadcastsd_avx5120 = x86.rm.vbroadcastsd %1, 0 : (!x86.reg<rdx>) -> !x86.avx512reg<zmm0>
+%rm_vbroadcastsd_avx5120 = x86.dm.vbroadcastsd %1, 0 : (!x86.reg<rdx>) -> !x86.avx512reg<zmm0>
 // CHECK-NEXT: vbroadcastsd zmm0, [rdx]
-%rm_vbroadcastsd_avx512 = x86.rm.vbroadcastsd %1, 8 : (!x86.reg<rdx>) -> !x86.avx512reg<zmm0>
+%rm_vbroadcastsd_avx512 = x86.dm.vbroadcastsd %1, 8 : (!x86.reg<rdx>) -> !x86.avx512reg<zmm0>
 // CHECK-NEXT: vbroadcastsd zmm0, [rdx+8]
 
-%rm_vmovups_avx512 = x86.rm.vmovups %1 : (!x86.reg<rdx>) -> (!x86.avx512reg<zmm0>)
+%rm_vmovups_avx512 = x86.dm.vmovups %1 : (!x86.reg<rdx>) -> (!x86.avx512reg<zmm0>)
 // CHECK: vmovups zmm0, [rdx]
-%rm_vmovups_avx2 = x86.rm.vmovups %1 : (!x86.reg<rdx>) -> (!x86.avx2reg<ymm0>)
+%rm_vmovups_avx2 = x86.dm.vmovups %1 : (!x86.reg<rdx>) -> (!x86.avx2reg<ymm0>)
 // CHECK-NEXT: vmovups ymm0, [rdx]
-%rm_vmovups_sse = x86.rm.vmovups %1 : (!x86.reg<rdx>) -> (!x86.ssereg<xmm0>)
+%rm_vmovups_sse = x86.dm.vmovups %1 : (!x86.reg<rdx>) -> (!x86.ssereg<xmm0>)
 // CHECK-NEXT: vmovups xmm0, [rdx]
 
-%rm_vbroadcastss_avx512 = x86.rm.vbroadcastss %1 : (!x86.reg<rdx>) -> (!x86.avx512reg<zmm0>)
+%rm_vbroadcastss_avx512 = x86.dm.vbroadcastss %1 : (!x86.reg<rdx>) -> (!x86.avx512reg<zmm0>)
 // CHECK: vbroadcastss zmm0, [rdx]
-%rm_vbroadcastss_avx2 = x86.rm.vbroadcastss %1 : (!x86.reg<rdx>) -> (!x86.avx2reg<ymm0>)
+%rm_vbroadcastss_avx2 = x86.dm.vbroadcastss %1 : (!x86.reg<rdx>) -> (!x86.avx2reg<ymm0>)
 // CHECK-NEXT: vbroadcastss ymm0, [rdx]
-%rm_vbroadcastss_sse = x86.rm.vbroadcastss %1 : (!x86.reg<rdx>) -> (!x86.ssereg<xmm0>)
+%rm_vbroadcastss_sse = x86.dm.vbroadcastss %1 : (!x86.reg<rdx>) -> (!x86.ssereg<xmm0>)
 // CHECK-NEXT: vbroadcastss xmm0, [rdx]
 
-x86.mr.vmovups %0, %zmm1, 0 : (!x86.reg<rax>, !x86.avx512reg<zmm1>) -> ()
+x86.ms.vmovups %0, %zmm1, 0 : (!x86.reg<rax>, !x86.avx512reg<zmm1>) -> ()
 // CHECK: vmovups [rax], zmm1
-x86.mr.vmovups %0, %ymm1, 0 : (!x86.reg<rax>, !x86.avx2reg<ymm1>) -> ()
+x86.ms.vmovups %0, %ymm1, 0 : (!x86.reg<rax>, !x86.avx2reg<ymm1>) -> ()
 // CHECK-NEXT: vmovups [rax], ymm1
-x86.mr.vmovups %0, %xmm1, 0 : (!x86.reg<rax>, !x86.ssereg<xmm1>) -> ()
+x86.ms.vmovups %0, %xmm1, 0 : (!x86.reg<rax>, !x86.ssereg<xmm1>) -> ()
 // CHECK-NEXT: vmovups [rax], xmm1
 
-%rrr_vfmadd231ps_sse = x86.rrr.vfmadd231ps %xmm0, %xmm1, %xmm2 : (!x86.ssereg<xmm0>, !x86.ssereg<xmm1>, !x86.ssereg<xmm2>) -> !x86.ssereg<xmm0>
+%rrr_vfmadd231ps_sse = x86.rss.vfmadd231ps %xmm0, %xmm1, %xmm2 : (!x86.ssereg<xmm0>, !x86.ssereg<xmm1>, !x86.ssereg<xmm2>) -> !x86.ssereg<xmm0>
 // CHECK: vfmadd231ps xmm0, xmm1, xmm2
-%rrr_vfmadd231ps_avx2 = x86.rrr.vfmadd231ps %ymm0, %ymm1, %ymm2 : (!x86.avx2reg<ymm0>, !x86.avx2reg<ymm1>, !x86.avx2reg<ymm2>) -> !x86.avx2reg<ymm0>
+%rrr_vfmadd231ps_avx2 = x86.rss.vfmadd231ps %ymm0, %ymm1, %ymm2 : (!x86.avx2reg<ymm0>, !x86.avx2reg<ymm1>, !x86.avx2reg<ymm2>) -> !x86.avx2reg<ymm0>
 // CHECK-NEXT: vfmadd231ps ymm0, ymm1, ymm2
-%rrr_vfmadd231ps_avx512 = x86.rrr.vfmadd231ps %zmm0, %zmm1, %zmm2 : (!x86.avx512reg<zmm0>, !x86.avx512reg<zmm1>, !x86.avx512reg<zmm2>) -> !x86.avx512reg<zmm0>
+%rrr_vfmadd231ps_avx512 = x86.rss.vfmadd231ps %zmm0, %zmm1, %zmm2 : (!x86.avx512reg<zmm0>, !x86.avx512reg<zmm1>, !x86.avx512reg<zmm2>) -> !x86.avx512reg<zmm0>
 // CHECK-NEXT: vfmadd231ps zmm0, zmm1, zmm2
diff --git a/tests/filecheck/dialects/x86/x86_ops.mlir b/tests/filecheck/dialects/x86/x86_ops.mlir
index bb7c6c8658..4e085be4b3 100644
--- a/tests/filecheck/dialects/x86/x86_ops.mlir
+++ b/tests/filecheck/dialects/x86/x86_ops.mlir
@@ -7,27 +7,27 @@
 %rax = "test.op"() : () -> !x86.reg<rax>
 %rdx = "test.op"() : () -> !x86.reg<rdx>
 
-%rr_add = x86.rr.add %0, %1 : (!x86.reg, !x86.reg) -> !x86.reg
-// CHECK: %{{.*}} = x86.rr.add %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> !x86.reg
-%rr_sub = x86.rr.sub %0, %1 : (!x86.reg, !x86.reg) -> !x86.reg
-// CHECK-NEXT: %{{.*}} = x86.rr.sub %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> !x86.reg
-%rr_mul = x86.rr.imul %0, %1 : (!x86.reg, !x86.reg) -> !x86.reg
-// CHECK-NEXT: %{{.*}} = x86.rr.imul %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> !x86.reg
-%rr_and = x86.rr.and %0, %1 : (!x86.reg, !x86.reg) -> !x86.reg
-// CHECK-NEXT: %{{.*}} = x86.rr.and %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> !x86.reg
-%rr_or = x86.rr.or %0, %1 : (!x86.reg, !x86.reg) -> !x86.reg
-// CHECK-NEXT: %{{.*}} = x86.rr.or %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> !x86.reg
-%rr_xor = x86.rr.xor %0, %1 : (!x86.reg, !x86.reg) -> !x86.reg
-// CHECK-NEXT: %{{.*}} = x86.rr.xor %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> !x86.reg
-%rr_mov = x86.rr.mov %0, %1 : (!x86.reg, !x86.reg) -> !x86.reg
-// CHECK-NEXT: %{{.*}} = x86.rr.mov %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> !x86.reg
-%rr_cmp = x86.rr.cmp %0, %1 : (!x86.reg, !x86.reg) -> !x86.rflags<rflags>
-// CHECK: %{{.*}} = x86.rr.cmp %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> !x86.rflags
+%rr_add = x86.rs.add %0, %1 : (!x86.reg, !x86.reg) -> !x86.reg
+// CHECK: %{{.*}} = x86.rs.add %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> !x86.reg
+%rr_sub = x86.rs.sub %0, %1 : (!x86.reg, !x86.reg) -> !x86.reg
+// CHECK-NEXT: %{{.*}} = x86.rs.sub %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> !x86.reg
+%rr_mul = x86.rs.imul %0, %1 : (!x86.reg, !x86.reg) -> !x86.reg
+// CHECK-NEXT: %{{.*}} = x86.rs.imul %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> !x86.reg
+%rr_and = x86.rs.and %0, %1 : (!x86.reg, !x86.reg) -> !x86.reg
+// CHECK-NEXT: %{{.*}} = x86.rs.and %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> !x86.reg
+%rr_or = x86.rs.or %0, %1 : (!x86.reg, !x86.reg) -> !x86.reg
+// CHECK-NEXT: %{{.*}} = x86.rs.or %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> !x86.reg
+%rr_xor = x86.rs.xor %0, %1 : (!x86.reg, !x86.reg) -> !x86.reg
+// CHECK-NEXT: %{{.*}} = x86.rs.xor %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> !x86.reg
+%rr_mov = x86.rs.mov %0, %1 : (!x86.reg, !x86.reg) -> !x86.reg
+// CHECK-NEXT: %{{.*}} = x86.rs.mov %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> !x86.reg
+%rr_cmp = x86.ss.cmp %0, %1 : (!x86.reg, !x86.reg) -> !x86.rflags<rflags>
+// CHECK: %{{.*}} = x86.ss.cmp %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> !x86.rflags
 
-%r_pushrsp = x86.r.push %rsp, %0 : (!x86.reg<rsp>, !x86.reg) -> !x86.reg<rsp>
-// CHECK-NEXT: %{{.*}} = x86.r.push %rsp, %{{.*}} : (!x86.reg<rsp>, !x86.reg) -> !x86.reg<rsp>
-%r_pop, %r_poprsp = x86.r.pop %rsp : (!x86.reg<rsp>) -> (!x86.reg, !x86.reg<rsp>)
-// CHECK-NEXT: %{{.*}}, %{{.*}} = x86.r.pop %{{.*}} : (!x86.reg<rsp>) -> (!x86.reg, !x86.reg<rsp>)
+%r_pushrsp = x86.s.push %rsp, %0 : (!x86.reg<rsp>, !x86.reg) -> !x86.reg<rsp>
+// CHECK-NEXT: %{{.*}} = x86.s.push %rsp, %{{.*}} : (!x86.reg<rsp>, !x86.reg) -> !x86.reg<rsp>
+%r_poprsp, %r_pop = x86.d.pop %rsp : (!x86.reg<rsp>) -> (!x86.reg<rsp>, !x86.reg)
+// CHECK-NEXT: %{{.*}}, %{{.*}} = x86.d.pop %{{.*}} : (!x86.reg<rsp>) -> (!x86.reg<rsp>, !x86.reg)
 %r_not = x86.r.not %0 : (!x86.reg) -> !x86.reg
 // CHECK-NEXT: %{{.*}} = x86.r.not %{{.*}} : (!x86.reg) -> !x86.reg
 %r_neg = x86.r.neg %0 : (!x86.reg) -> !x86.reg
@@ -37,10 +37,10 @@
 %r_dec = x86.r.dec %0 : (!x86.reg) -> !x86.reg
 // CHECK-NEXT: %{{.*}} = x86.r.dec %{{.*}} : (!x86.reg) -> !x86.reg
 
-%r_idiv_rdx, %r_idiv_rax = x86.r.idiv %0, %rdx, %rax : (!x86.reg, !x86.reg<rdx>, !x86.reg<rax>) -> (!x86.reg<rdx>, !x86.reg<rax>)
-// CHECK-NEXT: %{{.*}}, %{{.*}} = x86.r.idiv %{{.*}}, %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg<rdx>, !x86.reg<rax>) -> (!x86.reg<rdx>, !x86.reg<rax>)
-%r_imul_rdx, %r_imul_rax = x86.r.imul %0, %rax : (!x86.reg, !x86.reg<rax>) -> (!x86.reg<rdx>, !x86.reg<rax>)
-// CHECK-NEXT: %{{.*}}, %{{.*}} = x86.r.imul %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg<rax>) -> (!x86.reg<rdx>, !x86.reg<rax>)
+%r_idiv_rdx, %r_idiv_rax = x86.s.idiv %0, %rdx, %rax : (!x86.reg, !x86.reg<rdx>, !x86.reg<rax>) -> (!x86.reg<rdx>, !x86.reg<rax>)
+// CHECK-NEXT: %{{.*}}, %{{.*}} = x86.s.idiv %{{.*}}, %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg<rdx>, !x86.reg<rax>) -> (!x86.reg<rdx>, !x86.reg<rax>)
+%r_imul_rdx, %r_imul_rax = x86.s.imul %0, %rax : (!x86.reg, !x86.reg<rax>) -> (!x86.reg<rdx>, !x86.reg<rax>)
+// CHECK-NEXT: %{{.*}}, %{{.*}} = x86.s.imul %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg<rax>) -> (!x86.reg<rdx>, !x86.reg<rax>)
 
 %rm_add_no_offset  = x86.rm.add %0, %1 : (!x86.reg, !x86.reg) -> !x86.reg
 // CHECK-NEXT: %{{.*}} = x86.rm.add %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> !x86.reg
@@ -56,69 +56,69 @@
 // CHECK-NEXT: %{{.*}} = x86.rm.or %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.reg) -> !x86.reg
 %rm_xor = x86.rm.xor %0, %1, 8 : (!x86.reg, !x86.reg) -> !x86.reg
 // CHECK-NEXT: %{{.*}} = x86.rm.xor %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.reg) -> !x86.reg
-%rm_mov = x86.rm.mov %1, 8 : (!x86.reg) -> !x86.reg
-// CHECK-NEXT: %{{.*}} = x86.rm.mov %{{.*}}, 8 : (!x86.reg) -> !x86.reg
-%rm_cmp = x86.rm.cmp %0, %1, 8 : (!x86.reg, !x86.reg) -> !x86.rflags<rflags>
-// CHECK-NEXT: %{{.*}} = x86.rm.cmp %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.reg) -> !x86.rflags
-%rm_lea = x86.rm.lea %0, %1, 8 : (!x86.reg, !x86.reg) -> !x86.reg
-// CHECK-NEXT: %{{.*}} = x86.rm.lea %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.reg) -> !x86.reg
+%rm_mov = x86.dm.mov %1, 8 : (!x86.reg) -> !x86.reg
+// CHECK-NEXT: %{{.*}} = x86.dm.mov %{{.*}}, 8 : (!x86.reg) -> !x86.reg
+%rm_cmp = x86.sm.cmp %0, %1, 8 : (!x86.reg, !x86.reg) -> !x86.rflags<rflags>
+// CHECK-NEXT: %{{.*}} = x86.sm.cmp %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.reg) -> !x86.rflags
+%dm_lea = x86.dm.lea %0, 8 : (!x86.reg) -> !x86.reg
+// CHECK-NEXT: %{{.*}} = x86.dm.lea %{{.*}}, 8 : (!x86.reg) -> !x86.reg
 
-%ri_add = x86.rimm.add %0, 2 : (!x86.reg) -> !x86.reg
-// CHECK-NEXT: %{{.*}} = x86.rimm.add %{{.*}}, 2 : (!x86.reg) -> !x86.reg
-%ri_sub = x86.rimm.sub %0, 2 : (!x86.reg) -> !x86.reg
-// CHECK-NEXT: %{{.*}} = x86.rimm.sub %{{.*}}, 2 : (!x86.reg) -> !x86.reg
-%ri_and = x86.rimm.and %0, 2 : (!x86.reg) -> !x86.reg
-// CHECK-NEXT: %{{.*}} = x86.rimm.and %{{.*}}, 2 : (!x86.reg) -> !x86.reg
-%ri_or = x86.rimm.or %0, 2 : (!x86.reg) -> !x86.reg
-// CHECK-NEXT: %{{.*}} = x86.rimm.or %{{.*}}, 2 : (!x86.reg) -> !x86.reg
-%ri_xor = x86.rimm.xor %0, 2 : (!x86.reg) -> !x86.reg
-// CHECK-NEXT: %{{.*}} = x86.rimm.xor %{{.*}}, 2 : (!x86.reg) -> !x86.reg
-%ri_mov = x86.rimm.mov %0, 2 : (!x86.reg) -> !x86.reg
-// CHECK-NEXT: %{{.*}} = x86.rimm.mov %{{.*}}, 2 : (!x86.reg) -> !x86.reg
-%ri_cmp = x86.rimm.cmp %0, 2 : (!x86.reg) -> !x86.rflags<rflags>
-// CHECK-NEXT: %{{.*}} = x86.rimm.cmp %{{.*}}, 2 : (!x86.reg) -> !x86.rflags
+%ri_add = x86.ri.add %0, 2 : (!x86.reg) -> !x86.reg
+// CHECK-NEXT: %{{.*}} = x86.ri.add %{{.*}}, 2 : (!x86.reg) -> !x86.reg
+%ri_sub = x86.ri.sub %0, 2 : (!x86.reg) -> !x86.reg
+// CHECK-NEXT: %{{.*}} = x86.ri.sub %{{.*}}, 2 : (!x86.reg) -> !x86.reg
+%ri_and = x86.ri.and %0, 2 : (!x86.reg) -> !x86.reg
+// CHECK-NEXT: %{{.*}} = x86.ri.and %{{.*}}, 2 : (!x86.reg) -> !x86.reg
+%ri_or = x86.ri.or %0, 2 : (!x86.reg) -> !x86.reg
+// CHECK-NEXT: %{{.*}} = x86.ri.or %{{.*}}, 2 : (!x86.reg) -> !x86.reg
+%ri_xor = x86.ri.xor %0, 2 : (!x86.reg) -> !x86.reg
+// CHECK-NEXT: %{{.*}} = x86.ri.xor %{{.*}}, 2 : (!x86.reg) -> !x86.reg
+%ri_mov = x86.ri.mov %0, 2 : (!x86.reg) -> !x86.reg
+// CHECK-NEXT: %{{.*}} = x86.ri.mov %{{.*}}, 2 : (!x86.reg) -> !x86.reg
+%ri_cmp = x86.si.cmp %0, 2 : (!x86.reg) -> !x86.rflags<rflags>
+// CHECK-NEXT: %{{.*}} = x86.si.cmp %{{.*}}, 2 : (!x86.reg) -> !x86.rflags
 
-x86.mr.add %0, %1 : (!x86.reg, !x86.reg) -> ()
-// CHECK-NEXT: x86.mr.add %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> ()
-x86.mr.add %0, %1, 8 : (!x86.reg, !x86.reg) -> ()
-// CHECK-NEXT: x86.mr.add %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.reg) -> ()
-x86.mr.sub %0, %1, -8 : (!x86.reg, !x86.reg) -> ()
-// CHECK-NEXT: x86.mr.sub %{{.*}}, %{{.*}}, -8 : (!x86.reg, !x86.reg) -> ()
-x86.mr.and %0, %1, 8 : (!x86.reg, !x86.reg) -> ()
-// CHECK-NEXT: x86.mr.and %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.reg) -> ()
-x86.mr.or %0, %1, 8 : (!x86.reg, !x86.reg) -> ()
-// CHECK-NEXT: x86.mr.or %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.reg) -> ()
-x86.mr.xor %0, %1, 8 : (!x86.reg, !x86.reg) -> ()
-// CHECK-NEXT: x86.mr.xor %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.reg) -> ()
-x86.mr.mov %0, %1, 8 : (!x86.reg, !x86.reg) -> ()
-// CHECK-NEXT: x86.mr.mov %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.reg) -> ()
-%mr.cmp = x86.mr.cmp %0, %1, 8 : (!x86.reg, !x86.reg) -> !x86.rflags<rflags>
-// CHECK-NEXT: %{{.*}} = x86.mr.cmp %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.reg) -> !x86.rflags
+x86.ms.add %0, %1 : (!x86.reg, !x86.reg) -> ()
+// CHECK-NEXT: x86.ms.add %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> ()
+x86.ms.add %0, %1, 8 : (!x86.reg, !x86.reg) -> ()
+// CHECK-NEXT: x86.ms.add %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.reg) -> ()
+x86.ms.sub %0, %1, -8 : (!x86.reg, !x86.reg) -> ()
+// CHECK-NEXT: x86.ms.sub %{{.*}}, %{{.*}}, -8 : (!x86.reg, !x86.reg) -> ()
+x86.ms.and %0, %1, 8 : (!x86.reg, !x86.reg) -> ()
+// CHECK-NEXT: x86.ms.and %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.reg) -> ()
+x86.ms.or %0, %1, 8 : (!x86.reg, !x86.reg) -> ()
+// CHECK-NEXT: x86.ms.or %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.reg) -> ()
+x86.ms.xor %0, %1, 8 : (!x86.reg, !x86.reg) -> ()
+// CHECK-NEXT: x86.ms.xor %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.reg) -> ()
+x86.ms.mov %0, %1, 8 : (!x86.reg, !x86.reg) -> ()
+// CHECK-NEXT: x86.ms.mov %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.reg) -> ()
+%mr.cmp = x86.ms.cmp %0, %1, 8 : (!x86.reg, !x86.reg) -> !x86.rflags<rflags>
+// CHECK-NEXT: %{{.*}} = x86.ms.cmp %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.reg) -> !x86.rflags
 
-x86.mimm.add %0, 2 : (!x86.reg) -> ()
-// CHECK-NEXT: x86.mimm.add %{{.*}}, 2 : (!x86.reg) -> ()
-x86.mimm.add %0, 2, 8 : (!x86.reg) -> ()
-// CHECK-NEXT: x86.mimm.add %{{.*}}, 2, 8 : (!x86.reg) -> ()
-x86.mimm.sub %0, 2, -8 : (!x86.reg) -> ()
-// CHECK-NEXT: x86.mimm.sub %{{.*}}, 2, -8 : (!x86.reg) -> ()
-x86.mimm.and %0, 2, 8 : (!x86.reg) -> ()
-// CHECK-NEXT: x86.mimm.and %{{.*}}, 2, 8 : (!x86.reg) -> ()
-x86.mimm.or %0, 2, 8 : (!x86.reg) -> ()
-// CHECK-NEXT: x86.mimm.or %{{.*}}, 2, 8 : (!x86.reg) -> ()
-x86.mimm.xor %0, 2, 8 : (!x86.reg) -> ()
-// CHECK-NEXT: x86.mimm.xor %{{.*}}, 2, 8 : (!x86.reg) -> ()
-x86.mimm.mov %0, 2, 8 : (!x86.reg) -> ()
-// CHECK-NEXT: x86.mimm.mov %{{.*}}, 2, 8 : (!x86.reg) -> ()
-%mi_cmp = x86.mimm.cmp %0, 2, 8 : (!x86.reg) -> !x86.rflags<rflags>
-// CHECK-NEXT: %{{.*}} = x86.mimm.cmp %{{.*}}, 2, 8 : (!x86.reg) -> !x86.rflags
+x86.mi.add %0, 2 : (!x86.reg) -> ()
+// CHECK-NEXT: x86.mi.add %{{.*}}, 2 : (!x86.reg) -> ()
+x86.mi.add %0, 2, 8 : (!x86.reg) -> ()
+// CHECK-NEXT: x86.mi.add %{{.*}}, 2, 8 : (!x86.reg) -> ()
+x86.mi.sub %0, 2, -8 : (!x86.reg) -> ()
+// CHECK-NEXT: x86.mi.sub %{{.*}}, 2, -8 : (!x86.reg) -> ()
+x86.mi.and %0, 2, 8 : (!x86.reg) -> ()
+// CHECK-NEXT: x86.mi.and %{{.*}}, 2, 8 : (!x86.reg) -> ()
+x86.mi.or %0, 2, 8 : (!x86.reg) -> ()
+// CHECK-NEXT: x86.mi.or %{{.*}}, 2, 8 : (!x86.reg) -> ()
+x86.mi.xor %0, 2, 8 : (!x86.reg) -> ()
+// CHECK-NEXT: x86.mi.xor %{{.*}}, 2, 8 : (!x86.reg) -> ()
+x86.mi.mov %0, 2, 8 : (!x86.reg) -> ()
+// CHECK-NEXT: x86.mi.mov %{{.*}}, 2, 8 : (!x86.reg) -> ()
+%mi_cmp = x86.mi.cmp %0, 2, 8 : (!x86.reg) -> !x86.rflags<rflags>
+// CHECK-NEXT: %{{.*}} = x86.mi.cmp %{{.*}}, 2, 8 : (!x86.reg) -> !x86.rflags
 
-%rri_imul = x86.rri.imul %1, 2 : (!x86.reg) -> !x86.reg
-// CHECK-NEXT: %{{.*}} = x86.rri.imul %{{.*}}, 2 : (!x86.reg) -> !x86.reg
+%rri_imul = x86.dsi.imul %1, 2 : (!x86.reg) -> !x86.reg
+// CHECK-NEXT: %{{.*}} = x86.dsi.imul %{{.*}}, 2 : (!x86.reg) -> !x86.reg
 
-%rmi_imul_no_offset = x86.rmimm.imul %1, 2 : (!x86.reg) -> !x86.reg
-// CHECK-NEXT: %{{.*}} = x86.rmimm.imul %{{.*}}, 2 : (!x86.reg) -> !x86.reg
-%rmi_imul = x86.rmimm.imul %1, 2, 8 : (!x86.reg) ->  !x86.reg
-// CHECK-NEXT: %{{.*}} = x86.rmimm.imul %{{.*}}, 2, 8 : (!x86.reg) -> !x86.reg
+%rmi_imul_no_offset = x86.dmi.imul %1, 2 : (!x86.reg) -> !x86.reg
+// CHECK-NEXT: %{{.*}} = x86.dmi.imul %{{.*}}, 2 : (!x86.reg) -> !x86.reg
+%rmi_imul = x86.dmi.imul %1, 2, 8 : (!x86.reg) ->  !x86.reg
+// CHECK-NEXT: %{{.*}} = x86.dmi.imul %{{.*}}, 2, 8 : (!x86.reg) -> !x86.reg
 
 %m_push_rsp = x86.m.push %rsp, %0 : (!x86.reg<rsp>, !x86.reg) -> !x86.reg<rsp>
 // CHECK-NEXT: %{{.*}} = x86.m.push %rsp, %{{.*}} : (!x86.reg<rsp>, !x86.reg) -> !x86.reg<rsp>
@@ -153,8 +153,8 @@ x86.label "label"
 
 func.func @funcyasm() {
     %2, %3 = "test.op"() : () -> (!x86.reg, !x86.reg)
-    %rflags = x86.rr.cmp %2, %3 : (!x86.reg, !x86.reg) -> !x86.rflags<rflags>
-    // CHECK: %{{.*}} = x86.rr.cmp %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> !x86.rflags
+    %rflags = x86.ss.cmp %2, %3 : (!x86.reg, !x86.reg) -> !x86.rflags<rflags>
+    // CHECK: %{{.*}} = x86.ss.cmp %{{.*}}, %{{.*}} : (!x86.reg, !x86.reg) -> !x86.rflags
 
     x86.c.jmp ^then(%arg : !x86.reg)
     // CHECK-NEXT: x86.c.jmp ^{{.+}}(%arg : !x86.reg)
@@ -349,61 +349,61 @@ func.func @funcyasm() {
 
 %xmm0, %xmm1, %xmm2 = "test.op"() : () -> (!x86.ssereg, !x86.ssereg, !x86.ssereg)
 
-%rrr_vfmadd231pd_sse = x86.rrr.vfmadd231pd %xmm0, %xmm1, %xmm2 : (!x86.ssereg, !x86.ssereg, !x86.ssereg) -> !x86.ssereg
-// CHECK: %{{.*}} = x86.rrr.vfmadd231pd %{{.*}}, %{{.*}}, %{{.*}} : (!x86.ssereg, !x86.ssereg, !x86.ssereg) -> !x86.ssereg
-%rr_vmovapd_sse = x86.rr.vmovapd %xmm0, %xmm1 : (!x86.ssereg, !x86.ssereg) -> !x86.ssereg
-// CHECK-NEXT: x86.rr.vmovapd %{{.*}}, %{{.*}} : (!x86.ssereg, !x86.ssereg) -> !x86.ssereg
-x86.mr.vmovapd %0, %xmm1, 8 : (!x86.reg, !x86.ssereg) -> ()
-// CHECK-NEXT: x86.mr.vmovapd %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.ssereg) -> ()
-%rm_vbroadcastsd_sse = x86.rm.vbroadcastsd %0, 8 : (!x86.reg) -> !x86.ssereg
-// CHECK-NEXT: %{{.*}} = x86.rm.vbroadcastsd %{{.*}}, 8 : (!x86.reg) -> !x86.ssereg
+%rrr_vfmadd231pd_sse = x86.rss.vfmadd231pd %xmm0, %xmm1, %xmm2 : (!x86.ssereg, !x86.ssereg, !x86.ssereg) -> !x86.ssereg
+// CHECK: %{{.*}} = x86.rss.vfmadd231pd %{{.*}}, %{{.*}}, %{{.*}} : (!x86.ssereg, !x86.ssereg, !x86.ssereg) -> !x86.ssereg
+%rr_vmovapd_sse = x86.rs.vmovapd %xmm0, %xmm1 : (!x86.ssereg, !x86.ssereg) -> !x86.ssereg
+// CHECK-NEXT: x86.rs.vmovapd %{{.*}}, %{{.*}} : (!x86.ssereg, !x86.ssereg) -> !x86.ssereg
+x86.ms.vmovapd %0, %xmm1, 8 : (!x86.reg, !x86.ssereg) -> ()
+// CHECK-NEXT: x86.ms.vmovapd %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.ssereg) -> ()
+%rm_vbroadcastsd_sse = x86.dm.vbroadcastsd %0, 8 : (!x86.reg) -> !x86.ssereg
+// CHECK-NEXT: %{{.*}} = x86.dm.vbroadcastsd %{{.*}}, 8 : (!x86.reg) -> !x86.ssereg
 
 %ymm0, %ymm1, %ymm2 = "test.op"() : () -> (!x86.avx2reg, !x86.avx2reg, !x86.avx2reg)
 
-%rrr_vfmadd231pd_avx2 = x86.rrr.vfmadd231pd %ymm0, %ymm1, %ymm2 : (!x86.avx2reg, !x86.avx2reg, !x86.avx2reg) -> !x86.avx2reg
-// CHECK: %{{.*}} = x86.rrr.vfmadd231pd %{{.*}}, %{{.*}}, %{{.*}} : (!x86.avx2reg, !x86.avx2reg, !x86.avx2reg) -> !x86.avx2reg
-%rr_vmovapd_avx2 = x86.rr.vmovapd %ymm0, %ymm1 : (!x86.avx2reg, !x86.avx2reg) -> !x86.avx2reg
-// CHECK-NEXT: x86.rr.vmovapd %{{.*}}, %{{.*}} : (!x86.avx2reg, !x86.avx2reg) -> !x86.avx2reg
-x86.mr.vmovapd %0, %ymm1, 8 : (!x86.reg, !x86.avx2reg) -> ()
-// CHECK-NEXT: x86.mr.vmovapd %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.avx2reg) -> ()
-%rm_vbroadcastsd_avx2 = x86.rm.vbroadcastsd %0, 8 : (!x86.reg) -> !x86.avx2reg
-// CHECK-NEXT: %{{.*}} = x86.rm.vbroadcastsd %{{.*}}, 8 : (!x86.reg) -> !x86.avx2reg
+%rrr_vfmadd231pd_avx2 = x86.rss.vfmadd231pd %ymm0, %ymm1, %ymm2 : (!x86.avx2reg, !x86.avx2reg, !x86.avx2reg) -> !x86.avx2reg
+// CHECK: %{{.*}} = x86.rss.vfmadd231pd %{{.*}}, %{{.*}}, %{{.*}} : (!x86.avx2reg, !x86.avx2reg, !x86.avx2reg) -> !x86.avx2reg
+%rr_vmovapd_avx2 = x86.rs.vmovapd %ymm0, %ymm1 : (!x86.avx2reg, !x86.avx2reg) -> !x86.avx2reg
+// CHECK-NEXT: x86.rs.vmovapd %{{.*}}, %{{.*}} : (!x86.avx2reg, !x86.avx2reg) -> !x86.avx2reg
+x86.ms.vmovapd %0, %ymm1, 8 : (!x86.reg, !x86.avx2reg) -> ()
+// CHECK-NEXT: x86.ms.vmovapd %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.avx2reg) -> ()
+%rm_vbroadcastsd_avx2 = x86.dm.vbroadcastsd %0, 8 : (!x86.reg) -> !x86.avx2reg
+// CHECK-NEXT: %{{.*}} = x86.dm.vbroadcastsd %{{.*}}, 8 : (!x86.reg) -> !x86.avx2reg
 
 %zmm0, %zmm1, %zmm2 = "test.op"() : () -> (!x86.avx512reg, !x86.avx512reg, !x86.avx512reg)
 
-%rrr_vfmadd231pd_avx512 = x86.rrr.vfmadd231pd %zmm0, %zmm1, %zmm2 : (!x86.avx512reg, !x86.avx512reg, !x86.avx512reg) -> !x86.avx512reg
-// CHECK: %{{.*}} = x86.rrr.vfmadd231pd %{{.*}}, %{{.*}}, %{{.*}} : (!x86.avx512reg, !x86.avx512reg, !x86.avx512reg) -> !x86.avx512reg
-%rr_vmovapd_avx512 = x86.rr.vmovapd %zmm0, %zmm1 : (!x86.avx512reg, !x86.avx512reg) -> !x86.avx512reg
-// CHECK-NEXT: x86.rr.vmovapd %{{.*}}, %{{.*}} : (!x86.avx512reg, !x86.avx512reg) -> !x86.avx512reg
-x86.mr.vmovapd %0, %zmm1, 8 : (!x86.reg, !x86.avx512reg) -> ()
-// CHECK-NEXT: x86.mr.vmovapd %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.avx512reg) -> ()
-%rm_vbroadcastsd_avx512 = x86.rm.vbroadcastsd %0, 8 : (!x86.reg) -> !x86.avx512reg
-// CHECK-NEXT: %{{.*}} = x86.rm.vbroadcastsd %{{.*}}, 8 : (!x86.reg) -> !x86.avx512reg
+%rrr_vfmadd231pd_avx512 = x86.rss.vfmadd231pd %zmm0, %zmm1, %zmm2 : (!x86.avx512reg, !x86.avx512reg, !x86.avx512reg) -> !x86.avx512reg
+// CHECK: %{{.*}} = x86.rss.vfmadd231pd %{{.*}}, %{{.*}}, %{{.*}} : (!x86.avx512reg, !x86.avx512reg, !x86.avx512reg) -> !x86.avx512reg
+%rr_vmovapd_avx512 = x86.rs.vmovapd %zmm0, %zmm1 : (!x86.avx512reg, !x86.avx512reg) -> !x86.avx512reg
+// CHECK-NEXT: x86.rs.vmovapd %{{.*}}, %{{.*}} : (!x86.avx512reg, !x86.avx512reg) -> !x86.avx512reg
+x86.ms.vmovapd %0, %zmm1, 8 : (!x86.reg, !x86.avx512reg) -> ()
+// CHECK-NEXT: x86.ms.vmovapd %{{.*}}, %{{.*}}, 8 : (!x86.reg, !x86.avx512reg) -> ()
+%rm_vbroadcastsd_avx512 = x86.dm.vbroadcastsd %0, 8 : (!x86.reg) -> !x86.avx512reg
+// CHECK-NEXT: %{{.*}} = x86.dm.vbroadcastsd %{{.*}}, 8 : (!x86.reg) -> !x86.avx512reg
 
-%rm_vmovups_avx512 = x86.rm.vmovups %1, 8 : (!x86.reg) -> (!x86.avx512reg)
-// CHECK: %{{.*}} = x86.rm.vmovups %{{.*}}, 8 : (!x86.reg) -> !x86.avx512reg
-%rm_vmovups_avx2 = x86.rm.vmovups %1, 8 : (!x86.reg) -> (!x86.avx2reg)
-// CHECK-NEXT: %{{.*}} = x86.rm.vmovups %{{.*}}, 8 : (!x86.reg) -> !x86.avx2reg
-%rm_vmovups_sse = x86.rm.vmovups %1, 8 : (!x86.reg) -> (!x86.ssereg)
-// CHECK-NEXT: %{{.*}} = x86.rm.vmovups %{{.*}}, 8 : (!x86.reg) -> !x86.ssereg
+%rm_vmovups_avx512 = x86.dm.vmovups %1, 8 : (!x86.reg) -> (!x86.avx512reg)
+// CHECK: %{{.*}} = x86.dm.vmovups %{{.*}}, 8 : (!x86.reg) -> !x86.avx512reg
+%rm_vmovups_avx2 = x86.dm.vmovups %1, 8 : (!x86.reg) -> (!x86.avx2reg)
+// CHECK-NEXT: %{{.*}} = x86.dm.vmovups %{{.*}}, 8 : (!x86.reg) -> !x86.avx2reg
+%rm_vmovups_sse = x86.dm.vmovups %1, 8 : (!x86.reg) -> (!x86.ssereg)
+// CHECK-NEXT: %{{.*}} = x86.dm.vmovups %{{.*}}, 8 : (!x86.reg) -> !x86.ssereg
 
-%rm_vbroadcastss_avx512 = x86.rm.vbroadcastss %1, 8 : (!x86.reg) -> (!x86.avx512reg)
-// CHECK: %{{.*}} = x86.rm.vbroadcastss %{{.*}}, 8 : (!x86.reg) -> !x86.avx512reg
-%rm_vbroadcastss_avx2 = x86.rm.vbroadcastss %1, 8 : (!x86.reg) -> (!x86.avx2reg)
-// CHECK-NEXT: %{{.*}} = x86.rm.vbroadcastss %{{.*}}, 8 : (!x86.reg) -> !x86.avx2reg
-%rm_vbroadcastss_sse = x86.rm.vbroadcastss %1, 8 : (!x86.reg) -> (!x86.ssereg)
-// CHECK-NEXT: %{{.*}} = x86.rm.vbroadcastss %{{.*}}, 8 : (!x86.reg) -> !x86.ssereg
+%rm_vbroadcastss_avx512 = x86.dm.vbroadcastss %1, 8 : (!x86.reg) -> (!x86.avx512reg)
+// CHECK: %{{.*}} = x86.dm.vbroadcastss %{{.*}}, 8 : (!x86.reg) -> !x86.avx512reg
+%rm_vbroadcastss_avx2 = x86.dm.vbroadcastss %1, 8 : (!x86.reg) -> (!x86.avx2reg)
+// CHECK-NEXT: %{{.*}} = x86.dm.vbroadcastss %{{.*}}, 8 : (!x86.reg) -> !x86.avx2reg
+%rm_vbroadcastss_sse = x86.dm.vbroadcastss %1, 8 : (!x86.reg) -> (!x86.ssereg)
+// CHECK-NEXT: %{{.*}} = x86.dm.vbroadcastss %{{.*}}, 8 : (!x86.reg) -> !x86.ssereg
 
-x86.mr.vmovups %0, %zmm1, 0 : (!x86.reg, !x86.avx512reg) -> ()
-// CHECK: x86.mr.vmovups %{{.*}}, %{{.*}} : (!x86.reg, !x86.avx512reg) -> ()
-x86.mr.vmovups %0, %ymm1, 0 : (!x86.reg, !x86.avx2reg) -> ()
-// CHECK-NEXT: x86.mr.vmovups %{{.*}}, %{{.*}} : (!x86.reg, !x86.avx2reg) -> ()
-x86.mr.vmovups %0, %xmm1, 0 : (!x86.reg, !x86.ssereg) -> ()
-// CHECK-NEXT: x86.mr.vmovups %{{.*}}, %{{.*}} : (!x86.reg, !x86.ssereg) -> ()
+x86.ms.vmovups %0, %zmm1, 0 : (!x86.reg, !x86.avx512reg) -> ()
+// CHECK: x86.ms.vmovups %{{.*}}, %{{.*}} : (!x86.reg, !x86.avx512reg) -> ()
+x86.ms.vmovups %0, %ymm1, 0 : (!x86.reg, !x86.avx2reg) -> ()
+// CHECK-NEXT: x86.ms.vmovups %{{.*}}, %{{.*}} : (!x86.reg, !x86.avx2reg) -> ()
+x86.ms.vmovups %0, %xmm1, 0 : (!x86.reg, !x86.ssereg) -> ()
+// CHECK-NEXT: x86.ms.vmovups %{{.*}}, %{{.*}} : (!x86.reg, !x86.ssereg) -> ()
 
-%rrr_vfmadd231ps_sse = x86.rrr.vfmadd231ps %xmm0, %xmm1, %xmm2 : (!x86.ssereg, !x86.ssereg, !x86.ssereg) -> !x86.ssereg
-// CHECK: %{{.*}} = x86.rrr.vfmadd231ps %{{.*}}, %{{.*}}, %{{.*}} : (!x86.ssereg, !x86.ssereg, !x86.ssereg) -> !x86.ssereg
-%rrr_vfmadd231ps_avx2 = x86.rrr.vfmadd231ps %ymm0, %ymm1, %ymm2 : (!x86.avx2reg, !x86.avx2reg, !x86.avx2reg) -> !x86.avx2reg
-// CHECK: %{{.*}} = x86.rrr.vfmadd231ps %{{.*}}, %{{.*}}, %{{.*}} : (!x86.avx2reg, !x86.avx2reg, !x86.avx2reg) -> !x86.avx2reg
-%rrr_vfmadd231ps_avx512 = x86.rrr.vfmadd231ps %zmm0, %zmm1, %zmm2 : (!x86.avx512reg, !x86.avx512reg, !x86.avx512reg) -> !x86.avx512reg
-// CHECK: %{{.*}} = x86.rrr.vfmadd231ps %{{.*}}, %{{.*}}, %{{.*}} : (!x86.avx512reg, !x86.avx512reg, !x86.avx512reg) -> !x86.avx512reg
+%rrr_vfmadd231ps_sse = x86.rss.vfmadd231ps %xmm0, %xmm1, %xmm2 : (!x86.ssereg, !x86.ssereg, !x86.ssereg) -> !x86.ssereg
+// CHECK: %{{.*}} = x86.rss.vfmadd231ps %{{.*}}, %{{.*}}, %{{.*}} : (!x86.ssereg, !x86.ssereg, !x86.ssereg) -> !x86.ssereg
+%rrr_vfmadd231ps_avx2 = x86.rss.vfmadd231ps %ymm0, %ymm1, %ymm2 : (!x86.avx2reg, !x86.avx2reg, !x86.avx2reg) -> !x86.avx2reg
+// CHECK: %{{.*}} = x86.rss.vfmadd231ps %{{.*}}, %{{.*}}, %{{.*}} : (!x86.avx2reg, !x86.avx2reg, !x86.avx2reg) -> !x86.avx2reg
+%rrr_vfmadd231ps_avx512 = x86.rss.vfmadd231ps %zmm0, %zmm1, %zmm2 : (!x86.avx512reg, !x86.avx512reg, !x86.avx512reg) -> !x86.avx512reg
+// CHECK: %{{.*}} = x86.rss.vfmadd231ps %{{.*}}, %{{.*}}, %{{.*}} : (!x86.avx512reg, !x86.avx512reg, !x86.avx512reg) -> !x86.avx512reg
diff --git a/tests/filecheck/projects/libxsmm/x86_matmul_kernel.mlir b/tests/filecheck/projects/libxsmm/x86_matmul_kernel.mlir
index c2390538f9..9721100386 100644
--- a/tests/filecheck/projects/libxsmm/x86_matmul_kernel.mlir
+++ b/tests/filecheck/projects/libxsmm/x86_matmul_kernel.mlir
@@ -3,49 +3,49 @@
 // C: 4x4xf32 = A: 4x8xf32 * B: 8x4xf32
 x86_func.func @matmul(%rdi: !x86.reg<rdi>, %rsi: !x86.reg<rsi>, %rcx: !x86.reg<rcx>) {
     // Load rows of A
-    %a_row_0 = x86.rm.vmovups %rdi, 0 : (!x86.reg<rdi>) -> (!x86.avx2reg<ymm0>)
-    %a_row_1 = x86.rm.vmovups %rdi, 32 : (!x86.reg<rdi>) -> (!x86.avx2reg<ymm1>)
-    %a_row_2 = x86.rm.vmovups %rdi, 64 : (!x86.reg<rdi>) -> (!x86.avx2reg<ymm2>)
-    %a_row_3 = x86.rm.vmovups %rdi, 96 : (!x86.reg<rdi>) -> (!x86.avx2reg<ymm3>)
+    %a_row_0 = x86.dm.vmovups %rdi, 0 : (!x86.reg<rdi>) -> (!x86.avx2reg<ymm0>)
+    %a_row_1 = x86.dm.vmovups %rdi, 32 : (!x86.reg<rdi>) -> (!x86.avx2reg<ymm1>)
+    %a_row_2 = x86.dm.vmovups %rdi, 64 : (!x86.reg<rdi>) -> (!x86.avx2reg<ymm2>)
+    %a_row_3 = x86.dm.vmovups %rdi, 96 : (!x86.reg<rdi>) -> (!x86.avx2reg<ymm3>)
     // Initialize the accumulators (rows of C)
-    %c0_tmp0 = x86.rm.vmovups %rcx, 0 : (!x86.reg<rcx>) -> !x86.avx2reg<ymm4>
-    %c1_tmp0 = x86.rm.vmovups %rcx, 32 : (!x86.reg<rcx>) -> !x86.avx2reg<ymm5>
-    %c2_tmp0 = x86.rm.vmovups %rcx, 64 : (!x86.reg<rcx>) -> !x86.avx2reg<ymm6>
-    %c3_tmp0 = x86.rm.vmovups %rcx, 96 : (!x86.reg<rcx>) -> !x86.avx2reg<ymm7>
+    %c0_tmp0 = x86.dm.vmovups %rcx, 0 : (!x86.reg<rcx>) -> !x86.avx2reg<ymm4>
+    %c1_tmp0 = x86.dm.vmovups %rcx, 32 : (!x86.reg<rcx>) -> !x86.avx2reg<ymm5>
+    %c2_tmp0 = x86.dm.vmovups %rcx, 64 : (!x86.reg<rcx>) -> !x86.avx2reg<ymm6>
+    %c3_tmp0 = x86.dm.vmovups %rcx, 96 : (!x86.reg<rcx>) -> !x86.avx2reg<ymm7>
     // Load column 0 of B
-    %b_col_0 = x86.rm.vbroadcastss %rsi, 0 : (!x86.reg<rsi>) -> !x86.avx2reg<ymm8>
+    %b_col_0 = x86.dm.vbroadcastss %rsi, 0 : (!x86.reg<rsi>) -> !x86.avx2reg<ymm8>
     // Reduction
-    %c0_tmp1 = x86.rrr.vfmadd231ps %c0_tmp0, %b_col_0, %a_row_0 : (!x86.avx2reg<ymm4>, !x86.avx2reg<ymm8>, !x86.avx2reg<ymm0>) -> !x86.avx2reg<ymm4>
-    %c1_tmp1 = x86.rrr.vfmadd231ps %c1_tmp0, %b_col_0, %a_row_1 : (!x86.avx2reg<ymm5>, !x86.avx2reg<ymm8>, !x86.avx2reg<ymm1>) -> !x86.avx2reg<ymm5>
-    %c2_tmp1 = x86.rrr.vfmadd231ps %c2_tmp0, %b_col_0, %a_row_2 : (!x86.avx2reg<ymm6>, !x86.avx2reg<ymm8>, !x86.avx2reg<ymm2>) -> !x86.avx2reg<ymm6>
-    %c3_tmp1 = x86.rrr.vfmadd231ps %c3_tmp0, %b_col_0, %a_row_3 : (!x86.avx2reg<ymm7>, !x86.avx2reg<ymm8>, !x86.avx2reg<ymm3>) -> !x86.avx2reg<ymm7>
+    %c0_tmp1 = x86.rss.vfmadd231ps %c0_tmp0, %b_col_0, %a_row_0 : (!x86.avx2reg<ymm4>, !x86.avx2reg<ymm8>, !x86.avx2reg<ymm0>) -> !x86.avx2reg<ymm4>
+    %c1_tmp1 = x86.rss.vfmadd231ps %c1_tmp0, %b_col_0, %a_row_1 : (!x86.avx2reg<ymm5>, !x86.avx2reg<ymm8>, !x86.avx2reg<ymm1>) -> !x86.avx2reg<ymm5>
+    %c2_tmp1 = x86.rss.vfmadd231ps %c2_tmp0, %b_col_0, %a_row_2 : (!x86.avx2reg<ymm6>, !x86.avx2reg<ymm8>, !x86.avx2reg<ymm2>) -> !x86.avx2reg<ymm6>
+    %c3_tmp1 = x86.rss.vfmadd231ps %c3_tmp0, %b_col_0, %a_row_3 : (!x86.avx2reg<ymm7>, !x86.avx2reg<ymm8>, !x86.avx2reg<ymm3>) -> !x86.avx2reg<ymm7>
     // Load column 1 of B
-    %b_col_1 = x86.rm.vbroadcastss %rsi, 4 : (!x86.reg<rsi>) -> !x86.avx2reg<ymm9>
+    %b_col_1 = x86.dm.vbroadcastss %rsi, 4 : (!x86.reg<rsi>) -> !x86.avx2reg<ymm9>
     // Reduction
-    %c0_tmp2 = x86.rrr.vfmadd231ps %c0_tmp1, %b_col_1, %a_row_0 : (!x86.avx2reg<ymm4>, !x86.avx2reg<ymm9>, !x86.avx2reg<ymm0>) -> !x86.avx2reg<ymm4>
-    %c1_tmp2 = x86.rrr.vfmadd231ps %c1_tmp1, %b_col_1, %a_row_1 : (!x86.avx2reg<ymm5>, !x86.avx2reg<ymm9>, !x86.avx2reg<ymm1>) -> !x86.avx2reg<ymm5>
-    %c2_tmp2 = x86.rrr.vfmadd231ps %c2_tmp1, %b_col_1, %a_row_2 : (!x86.avx2reg<ymm6>, !x86.avx2reg<ymm9>, !x86.avx2reg<ymm2>) -> !x86.avx2reg<ymm6>
-    %c3_tmp2 = x86.rrr.vfmadd231ps %c3_tmp1, %b_col_1, %a_row_3 : (!x86.avx2reg<ymm7>, !x86.avx2reg<ymm9>, !x86.avx2reg<ymm3>) -> !x86.avx2reg<ymm7>
+    %c0_tmp2 = x86.rss.vfmadd231ps %c0_tmp1, %b_col_1, %a_row_0 : (!x86.avx2reg<ymm4>, !x86.avx2reg<ymm9>, !x86.avx2reg<ymm0>) -> !x86.avx2reg<ymm4>
+    %c1_tmp2 = x86.rss.vfmadd231ps %c1_tmp1, %b_col_1, %a_row_1 : (!x86.avx2reg<ymm5>, !x86.avx2reg<ymm9>, !x86.avx2reg<ymm1>) -> !x86.avx2reg<ymm5>
+    %c2_tmp2 = x86.rss.vfmadd231ps %c2_tmp1, %b_col_1, %a_row_2 : (!x86.avx2reg<ymm6>, !x86.avx2reg<ymm9>, !x86.avx2reg<ymm2>) -> !x86.avx2reg<ymm6>
+    %c3_tmp2 = x86.rss.vfmadd231ps %c3_tmp1, %b_col_1, %a_row_3 : (!x86.avx2reg<ymm7>, !x86.avx2reg<ymm9>, !x86.avx2reg<ymm3>) -> !x86.avx2reg<ymm7>
     // Load column 2 of B
-    %b_col_2 = x86.rm.vbroadcastss %rsi, 8 : (!x86.reg<rsi>) -> !x86.avx2reg<ymm10>
+    %b_col_2 = x86.dm.vbroadcastss %rsi, 8 : (!x86.reg<rsi>) -> !x86.avx2reg<ymm10>
     // Reduction
-    %c0_tmp3 = x86.rrr.vfmadd231ps %c0_tmp2, %b_col_2, %a_row_0 : (!x86.avx2reg<ymm4>, !x86.avx2reg<ymm10>, !x86.avx2reg<ymm0>) -> !x86.avx2reg<ymm4>
-    %c1_tmp3 = x86.rrr.vfmadd231ps %c1_tmp2, %b_col_2, %a_row_1 : (!x86.avx2reg<ymm5>, !x86.avx2reg<ymm10>, !x86.avx2reg<ymm1>) -> !x86.avx2reg<ymm5>
-    %c2_tmp3 = x86.rrr.vfmadd231ps %c2_tmp2, %b_col_2, %a_row_2 : (!x86.avx2reg<ymm6>, !x86.avx2reg<ymm10>, !x86.avx2reg<ymm2>) -> !x86.avx2reg<ymm6>
-    %c3_tmp3 = x86.rrr.vfmadd231ps %c3_tmp2, %b_col_2, %a_row_3 : (!x86.avx2reg<ymm7>, !x86.avx2reg<ymm10>, !x86.avx2reg<ymm3>) -> !x86.avx2reg<ymm7>
+    %c0_tmp3 = x86.rss.vfmadd231ps %c0_tmp2, %b_col_2, %a_row_0 : (!x86.avx2reg<ymm4>, !x86.avx2reg<ymm10>, !x86.avx2reg<ymm0>) -> !x86.avx2reg<ymm4>
+    %c1_tmp3 = x86.rss.vfmadd231ps %c1_tmp2, %b_col_2, %a_row_1 : (!x86.avx2reg<ymm5>, !x86.avx2reg<ymm10>, !x86.avx2reg<ymm1>) -> !x86.avx2reg<ymm5>
+    %c2_tmp3 = x86.rss.vfmadd231ps %c2_tmp2, %b_col_2, %a_row_2 : (!x86.avx2reg<ymm6>, !x86.avx2reg<ymm10>, !x86.avx2reg<ymm2>) -> !x86.avx2reg<ymm6>
+    %c3_tmp3 = x86.rss.vfmadd231ps %c3_tmp2, %b_col_2, %a_row_3 : (!x86.avx2reg<ymm7>, !x86.avx2reg<ymm10>, !x86.avx2reg<ymm3>) -> !x86.avx2reg<ymm7>
     // Load column 3 of B
-    %b_col_3 = x86.rm.vbroadcastss %rsi, 12 : (!x86.reg<rsi>) -> !x86.avx2reg<ymm11>
+    %b_col_3 = x86.dm.vbroadcastss %rsi, 12 : (!x86.reg<rsi>) -> !x86.avx2reg<ymm11>
     // Reduction
-    %c0 = x86.rrr.vfmadd231ps %c0_tmp3, %b_col_3, %a_row_0 : (!x86.avx2reg<ymm4>, !x86.avx2reg<ymm11>, !x86.avx2reg<ymm0>) -> !x86.avx2reg<ymm4>
-    %c1 = x86.rrr.vfmadd231ps %c1_tmp3, %b_col_3, %a_row_1 : (!x86.avx2reg<ymm5>, !x86.avx2reg<ymm11>, !x86.avx2reg<ymm1>) -> !x86.avx2reg<ymm5>
-    %c2 = x86.rrr.vfmadd231ps %c2_tmp3, %b_col_3, %a_row_2 : (!x86.avx2reg<ymm6>, !x86.avx2reg<ymm11>, !x86.avx2reg<ymm2>) -> !x86.avx2reg<ymm6>
-    %c3 = x86.rrr.vfmadd231ps %c3_tmp3, %b_col_3, %a_row_3 : (!x86.avx2reg<ymm7>, !x86.avx2reg<ymm11>, !x86.avx2reg<ymm3>) -> !x86.avx2reg<ymm7>
+    %c0 = x86.rss.vfmadd231ps %c0_tmp3, %b_col_3, %a_row_0 : (!x86.avx2reg<ymm4>, !x86.avx2reg<ymm11>, !x86.avx2reg<ymm0>) -> !x86.avx2reg<ymm4>
+    %c1 = x86.rss.vfmadd231ps %c1_tmp3, %b_col_3, %a_row_1 : (!x86.avx2reg<ymm5>, !x86.avx2reg<ymm11>, !x86.avx2reg<ymm1>) -> !x86.avx2reg<ymm5>
+    %c2 = x86.rss.vfmadd231ps %c2_tmp3, %b_col_3, %a_row_2 : (!x86.avx2reg<ymm6>, !x86.avx2reg<ymm11>, !x86.avx2reg<ymm2>) -> !x86.avx2reg<ymm6>
+    %c3 = x86.rss.vfmadd231ps %c3_tmp3, %b_col_3, %a_row_3 : (!x86.avx2reg<ymm7>, !x86.avx2reg<ymm11>, !x86.avx2reg<ymm3>) -> !x86.avx2reg<ymm7>
    // Store the results (rows of C)
-    x86.mr.vmovups %rcx, %c0, 0 : (!x86.reg<rcx>,!x86.avx2reg<ymm4>) -> ()
-    x86.mr.vmovups %rcx, %c1, 32 : (!x86.reg<rcx>,!x86.avx2reg<ymm5>) -> ()
-    x86.mr.vmovups %rcx,%c2,64 : (!x86.reg<rcx>,!x86.avx2reg<ymm6>) -> ()
-    x86.mr.vmovups %rcx,%c3,96 : (!x86.reg<rcx>,!x86.avx2reg<ymm7>) -> ()
-    
+    x86.ms.vmovups %rcx, %c0, 0 : (!x86.reg<rcx>,!x86.avx2reg<ymm4>) -> ()
+    x86.ms.vmovups %rcx, %c1, 32 : (!x86.reg<rcx>,!x86.avx2reg<ymm5>) -> ()
+    x86.ms.vmovups %rcx,%c2,64 : (!x86.reg<rcx>,!x86.avx2reg<ymm6>) -> ()
+    x86.ms.vmovups %rcx,%c3,96 : (!x86.reg<rcx>,!x86.avx2reg<ymm7>) -> ()
+
     x86_func.ret
 }
 
diff --git a/xdsl/backend/x86/lowering/convert_func_to_x86_func.py b/xdsl/backend/x86/lowering/convert_func_to_x86_func.py
index 5f50243238..659433aac9 100644
--- a/xdsl/backend/x86/lowering/convert_func_to_x86_func.py
+++ b/xdsl/backend/x86/lowering/convert_func_to_x86_func.py
@@ -91,14 +91,14 @@ def match_and_rewrite(self, op: func.FuncOp, rewriter: PatternRewriter):
         for i in range(num_inputs - MAX_REG_PASSING_INPUTS):
             arg = first_block.args[MAX_REG_PASSING_INPUTS + 1]
             assert sp != arg
-            mov_op = x86.RM_MovOp(
-                r1=sp,
-                offset=STACK_SLOT_SIZE_BYTES * (i + 1),
-                result=x86.register.UNALLOCATED_GENERAL,
+            mov_op = x86.DM_MovOp(
+                memory=sp,
+                memory_offset=STACK_SLOT_SIZE_BYTES * (i + 1),
+                destination=x86.register.UNALLOCATED_GENERAL,
                 comment=f"Load the {i + MAX_REG_PASSING_INPUTS + 1}th argument of the function",
             )
             cast_op = builtin.UnrealizedConversionCastOp.get(
-                (mov_op.result,), (arg.type,)
+                (mov_op.destination,), (arg.type,)
             )
             rewriter.insert_op([mov_op, cast_op], insertion_point)
             arg.replace_by(cast_op.results[0])
@@ -146,7 +146,9 @@ def match_and_rewrite(self, op: func.ReturnOp, rewriter: PatternRewriter):
             (return_value,), (x86.register.UNALLOCATED_GENERAL,)
         )
         get_reg_op = x86.ops.GetRegisterOp(return_passing_register)
-        mov_op = x86.ops.RR_MovOp(cast_op, get_reg_op, result=return_passing_register)
+        mov_op = x86.ops.RS_MovOp(
+            cast_op, get_reg_op, register_out=return_passing_register
+        )
         ret_op = x86_func.RetOp()
 
         rewriter.replace_matched_op([cast_op, get_reg_op, mov_op, ret_op])
diff --git a/xdsl/backend/x86/lowering/convert_ptr_to_x86.py b/xdsl/backend/x86/lowering/convert_ptr_to_x86.py
index 89b3ec7ce2..6cad63081e 100644
--- a/xdsl/backend/x86/lowering/convert_ptr_to_x86.py
+++ b/xdsl/backend/x86/lowering/convert_ptr_to_x86.py
@@ -28,8 +28,10 @@ def match_and_rewrite(self, op: ptr.PtrAddOp, rewriter: PatternRewriter):
         x86_reg_type = x86.register.UNALLOCATED_GENERAL
         ptr_cast_op = UnrealizedConversionCastOp.get((op.addr,), (x86_reg_type,))
         offset_cast_op = UnrealizedConversionCastOp.get((op.offset,), (x86_reg_type,))
-        add_op = x86.RR_AddOp(ptr_cast_op, offset_cast_op, result=x86_reg_type)
-        res_cast_op = UnrealizedConversionCastOp.get((add_op.result,), (ptr.PtrType(),))
+        add_op = x86.RS_AddOp(ptr_cast_op, offset_cast_op, register_out=x86_reg_type)
+        res_cast_op = UnrealizedConversionCastOp.get(
+            (add_op.register_out,), (ptr.PtrType(),)
+        )
         rewriter.replace_matched_op([ptr_cast_op, offset_cast_op, add_op, res_cast_op])
 
 
@@ -59,15 +61,15 @@ def match_and_rewrite(self, op: ptr.StoreOp, rewriter: PatternRewriter):
                     "Half-precision vector load is not implemented yet."
                 )
             case 32:
-                mov = x86.ops.MR_VmovupsOp
+                mov = x86.ops.MS_VmovupsOp
             case 64:
-                mov = x86.ops.MR_VmovapdOp
+                mov = x86.ops.MS_VmovapdOp
             case _:
                 raise DiagnosticException(
                     "Float precision must be half, single or double."
                 )
 
-        mov_op = mov(addr_cast_op, vect_cast_op, offset=0)
+        mov_op = mov(addr_cast_op, vect_cast_op, memory_offset=0)
         rewriter.replace_matched_op([addr_cast_op, vect_cast_op, mov_op])
 
 
@@ -95,7 +97,7 @@ def match_and_rewrite(self, op: ptr.LoadOp, rewriter: PatternRewriter):
                     "Half-precision vector load is not implemented yet."
                 )
             case 32:
-                mov = x86.ops.RM_VmovupsOp
+                mov = x86.ops.DM_VmovupsOp
             case 64:
                 raise DiagnosticException(
                     "Double precision vector load is not implemented yet."
@@ -107,8 +109,8 @@ def match_and_rewrite(self, op: ptr.LoadOp, rewriter: PatternRewriter):
 
         mov_op = mov(
             cast_op,
-            offset=0,
-            result=vector_type_to_register_type(value_type, self.arch),
+            memory_offset=0,
+            destination=vector_type_to_register_type(value_type, self.arch),
         )
         res_cast_op = UnrealizedConversionCastOp.get(mov_op.results, (value_type,))
         rewriter.replace_matched_op([cast_op, mov_op, res_cast_op])
diff --git a/xdsl/backend/x86/lowering/convert_vector_to_x86.py b/xdsl/backend/x86/lowering/convert_vector_to_x86.py
index 2bebbe2a44..3e0dd25c00 100644
--- a/xdsl/backend/x86/lowering/convert_vector_to_x86.py
+++ b/xdsl/backend/x86/lowering/convert_vector_to_x86.py
@@ -41,18 +41,18 @@ def match_and_rewrite(self, op: vector.FMAOp, rewriter: PatternRewriter):
                     "Half-precision vector load is not implemented yet."
                 )
             case 32:
-                fma = x86.ops.RRR_Vfmadd231psOp
+                fma = x86.ops.RSS_Vfmadd231psOp
             case 64:
-                fma = x86.ops.RRR_Vfmadd231pdOp
+                fma = x86.ops.RSS_Vfmadd231pdOp
             case _:
                 raise DiagnosticException(
                     "Float precision must be half, single or double."
                 )
-        fma_op = fma(
-            r1=acc_cast_op, r2=lhs_cast_op, r3=rhs_cast_op, result=x86_vect_type
-        )
+        fma_op = fma(acc_cast_op, lhs_cast_op, rhs_cast_op, register_out=x86_vect_type)
 
-        res_cast_op = UnrealizedConversionCastOp.get((fma_op.result,), (vect_type,))
+        res_cast_op = UnrealizedConversionCastOp.get(
+            (fma_op.register_out,), (vect_type,)
+        )
         rewriter.replace_matched_op(
             [lhs_cast_op, rhs_cast_op, acc_cast_op, fma_op, res_cast_op]
         )
diff --git a/xdsl/dialects/x86/__init__.py b/xdsl/dialects/x86/__init__.py
index 8508e82f4a..186e7a10bd 100644
--- a/xdsl/dialects/x86/__init__.py
+++ b/xdsl/dialects/x86/__init__.py
@@ -33,7 +33,15 @@
     C_JpOp,
     C_JsOp,
     C_JzOp,
+    D_PopOp,
     DirectiveOp,
+    DM_LeaOp,
+    DM_MovOp,
+    DM_VbroadcastsdOp,
+    DM_VbroadcastssOp,
+    DM_VmovupsOp,
+    DMI_ImulOp,
+    DSI_ImulOp,
     GetAVXRegisterOp,
     GetRegisterOp,
     LabelOp,
@@ -45,62 +53,54 @@
     M_NotOp,
     M_PopOp,
     M_PushOp,
-    MImm_AddOp,
-    MImm_AndOp,
-    MImm_CmpOp,
-    MImm_MovOp,
-    MImm_OrOp,
-    MImm_SubOp,
-    MImm_XorOp,
-    MR_AddOp,
-    MR_AndOp,
-    MR_CmpOp,
-    MR_MovOp,
-    MR_OrOp,
-    MR_SubOp,
-    MR_VmovapdOp,
-    MR_VmovupsOp,
-    MR_XorOp,
+    MI_AddOp,
+    MI_AndOp,
+    MI_CmpOp,
+    MI_MovOp,
+    MI_OrOp,
+    MI_SubOp,
+    MI_XorOp,
+    MS_AddOp,
+    MS_AndOp,
+    MS_CmpOp,
+    MS_MovOp,
+    MS_OrOp,
+    MS_SubOp,
+    MS_VmovapdOp,
+    MS_VmovupsOp,
+    MS_XorOp,
     R_DecOp,
-    R_IDivOp,
-    R_ImulOp,
     R_IncOp,
     R_NegOp,
     R_NotOp,
-    R_PopOp,
-    R_PushOp,
     RI_AddOp,
-    RImm_AndOp,
-    RImm_CmpOp,
-    RImm_MovOp,
-    RImm_OrOp,
-    RImm_SubOp,
-    RImm_XorOp,
+    RI_AndOp,
+    RI_MovOp,
+    RI_OrOp,
+    RI_SubOp,
+    RI_XorOp,
     RM_AddOp,
     RM_AndOp,
-    RM_CmpOp,
     RM_ImulOp,
-    RM_leaOp,
-    RM_MovOp,
     RM_OrOp,
     RM_SubOp,
-    RM_VbroadcastsdOp,
-    RM_VbroadcastssOp,
-    RM_VmovupsOp,
     RM_XorOp,
-    RMImm_ImulOp,
-    RR_AddOp,
-    RR_AndOp,
-    RR_CmpOp,
-    RR_ImulOp,
-    RR_MovOp,
-    RR_OrOp,
-    RR_SubOp,
-    RR_VmovapdOp,
-    RR_XorOp,
-    RRImm_ImulOp,
-    RRR_Vfmadd231pdOp,
-    RRR_Vfmadd231psOp,
+    RS_AddOp,
+    RS_AndOp,
+    RS_ImulOp,
+    RS_MovOp,
+    RS_OrOp,
+    RS_SubOp,
+    RS_VmovapdOp,
+    RS_XorOp,
+    RSS_Vfmadd231pdOp,
+    RSS_Vfmadd231psOp,
+    S_IDivOp,
+    S_ImulOp,
+    S_PushOp,
+    SI_CmpOp,
+    SM_CmpOp,
+    SS_CmpOp,
 )
 from .register import (
     AVX2RegisterType,
@@ -113,105 +113,105 @@
 X86 = Dialect(
     "x86",
     [
-        RR_AddOp,
-        RR_SubOp,
-        RR_ImulOp,
-        RR_AndOp,
-        RR_OrOp,
-        RR_XorOp,
-        RR_MovOp,
-        RR_CmpOp,
-        R_PushOp,
-        R_PopOp,
-        R_NotOp,
-        R_IDivOp,
-        R_ImulOp,
-        R_NegOp,
-        R_IncOp,
-        R_DecOp,
-        RM_AddOp,
-        RM_SubOp,
-        RM_ImulOp,
-        RM_AndOp,
-        RM_OrOp,
-        RM_XorOp,
-        RM_CmpOp,
-        RM_MovOp,
-        RM_leaOp,
-        RI_AddOp,
-        RImm_SubOp,
-        RImm_AndOp,
-        RImm_OrOp,
-        RImm_XorOp,
-        RImm_MovOp,
-        RImm_CmpOp,
-        MR_AddOp,
-        MR_SubOp,
-        MR_AndOp,
-        MR_OrOp,
-        MR_XorOp,
-        MR_MovOp,
-        MR_CmpOp,
-        MImm_AddOp,
-        MImm_SubOp,
-        MImm_AndOp,
-        MImm_OrOp,
-        MImm_XorOp,
-        MImm_MovOp,
-        MImm_CmpOp,
-        RRImm_ImulOp,
-        RMImm_ImulOp,
-        M_PushOp,
-        M_PopOp,
-        M_NegOp,
-        M_NotOp,
-        M_IDivOp,
-        M_ImulOp,
-        M_IncOp,
-        M_DecOp,
-        C_JmpOp,
-        C_JaOp,
         C_JaeOp,
-        C_JbOp,
+        C_JaOp,
         C_JbeOp,
+        C_JbOp,
         C_JcOp,
         C_JeOp,
-        C_JgOp,
         C_JgeOp,
-        C_JlOp,
+        C_JgOp,
         C_JleOp,
-        C_JnaOp,
+        C_JlOp,
+        C_JmpOp,
         C_JnaeOp,
-        C_JnbOp,
+        C_JnaOp,
         C_JnbeOp,
+        C_JnbOp,
         C_JncOp,
         C_JneOp,
-        C_JngOp,
         C_JngeOp,
-        C_JnlOp,
+        C_JngOp,
         C_JnleOp,
+        C_JnlOp,
         C_JnoOp,
         C_JnpOp,
         C_JnsOp,
         C_JnzOp,
         C_JoOp,
-        C_JpOp,
         C_JpeOp,
         C_JpoOp,
+        C_JpOp,
         C_JsOp,
         C_JzOp,
-        RRR_Vfmadd231pdOp,
-        RRR_Vfmadd231psOp,
-        RM_VmovupsOp,
-        MR_VmovupsOp,
-        RM_VbroadcastsdOp,
-        RM_VbroadcastssOp,
-        RR_VmovapdOp,
-        MR_VmovapdOp,
-        GetRegisterOp,
+        D_PopOp,
+        DirectiveOp,
+        DM_LeaOp,
+        DM_MovOp,
+        DM_VbroadcastsdOp,
+        DM_VbroadcastssOp,
+        DM_VmovupsOp,
+        DMI_ImulOp,
+        DSI_ImulOp,
         GetAVXRegisterOp,
+        GetRegisterOp,
         LabelOp,
-        DirectiveOp,
+        M_DecOp,
+        M_IDivOp,
+        M_ImulOp,
+        M_IncOp,
+        M_NegOp,
+        M_NotOp,
+        M_PopOp,
+        M_PushOp,
+        MI_AddOp,
+        MI_AndOp,
+        MI_CmpOp,
+        MI_MovOp,
+        MI_OrOp,
+        MI_SubOp,
+        MI_XorOp,
+        MS_AddOp,
+        MS_AndOp,
+        MS_CmpOp,
+        MS_MovOp,
+        MS_OrOp,
+        MS_SubOp,
+        MS_VmovapdOp,
+        MS_VmovupsOp,
+        MS_XorOp,
+        R_DecOp,
+        R_IncOp,
+        R_NegOp,
+        R_NotOp,
+        RI_AddOp,
+        RI_AndOp,
+        RI_MovOp,
+        RI_OrOp,
+        RI_SubOp,
+        RI_XorOp,
+        RM_AddOp,
+        RM_AndOp,
+        RM_ImulOp,
+        RM_OrOp,
+        RM_SubOp,
+        RM_XorOp,
+        RS_AddOp,
+        RS_AndOp,
+        RS_ImulOp,
+        RS_MovOp,
+        RS_OrOp,
+        RS_SubOp,
+        RS_VmovapdOp,
+        RS_XorOp,
+        RSS_Vfmadd231pdOp,
+        RSS_Vfmadd231psOp,
+        S_IDivOp,
+        S_ImulOp,
+        S_PushOp,
+        SI_CmpOp,
+        SM_CmpOp,
+        SS_CmpOp,
     ],
     [
         GeneralRegisterType,
diff --git a/xdsl/dialects/x86/ops.py b/xdsl/dialects/x86/ops.py
index 8d76a44ed1..0980682ee7 100644
--- a/xdsl/dialects/x86/ops.py
+++ b/xdsl/dialects/x86/ops.py
@@ -1,9 +1,36 @@
+"""
+The `x86` dialect contains operations that represent x86 assembly operations.
+
+In x86, the assembly operations may have different meaning depending on the types of
+arguments.
+For example, the [`mov` instruction](https://www.felixcloutier.com/x86/mov) can assign
+an immediate value to a register, or move the contents of another register.
+In order to disambiguate the two, we use a mnemonic in the operation name to communicate
+which operands are expected, for example `x86.ds.mov` is the version that moves the
+contents of one register to another, and `x86.di.mov` is the version that sets the
+immediate value passed in to the register.
+The mnemonic encodes the types of the assembly instruction arguments, in order.
+
+Here are the possible mnemonic values and what they stand for:
+
+
+- `s`: Source register
+- `d`: Destination register
+- `r`: Register used both as a source and destination
+- `i`: Immediate value
+- `m`: Memory
+- `c`: Condition
+
+This dialect is structured into abstract base classes, which are prefixed with the
+mnemonic that corresponds to the subclassing operations (e.g. `DS_Operation`).
+"""
+
 from __future__ import annotations
 
 from abc import ABC, abstractmethod
 from collections.abc import Sequence, Set
 from io import StringIO
-from typing import IO, Generic, TypeVar
+from typing import IO, Generic, TypeVar, cast
 
 from typing_extensions import Self
 
@@ -197,194 +224,197 @@ def assembly_line(self) -> str | None:
 # region: Operation Base Classes
 
 
-class R_RR_Operation(
+class RS_Operation(
     Generic[R1InvT, R2InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
-    A base class for x86 operations that have two registers.
+    A base class for x86 operations that have one register that is read and written to,
+    and one source register.
     """
 
-    r1 = operand_def(R1InvT)
-    r2 = operand_def(R2InvT)
+    register_in = operand_def(R1InvT)
+    register_out = result_def(R1InvT)
 
-    result = result_def(R1InvT)
+    source = operand_def(R2InvT)
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
-        r2: Operation | SSAValue,
+        register_in: Operation | SSAValue,
+        source: Operation | SSAValue,
         *,
         comment: str | StringAttr | None = None,
-        result: R1InvT,
+        register_out: R1InvT | None = None,
     ):
         if isinstance(comment, str):
             comment = StringAttr(comment)
+        register_in = SSAValue.get(register_in)
+        if register_out is None:
+            register_out = cast(R1InvT, register_in.type)
 
         super().__init__(
-            operands=[r1, r2],
+            operands=[register_in, source],
             attributes={
                 "comment": comment,
             },
-            result_types=[result],
+            result_types=[register_out],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        return self.r1, self.r2
+        return self.register_in, self.source
 
 
-class R_R_Operation(Generic[R1InvT], X86Instruction, X86CustomFormatOperation, ABC):
+class R_Operation(Generic[R1InvT], X86Instruction, X86CustomFormatOperation, ABC):
     """
-    A base class for x86 operations that have one register acting as both source and destination.
+    A base class for x86 operations that have one register that is read and written to.
     """
 
-    source = operand_def(R1InvT)
-    destination = result_def(R1InvT)
+    register_in = operand_def(R1InvT)
+    register_out = result_def(R1InvT)
 
     def __init__(
         self,
-        source: Operation | SSAValue | None = None,
+        register_in: Operation | SSAValue | None = None,
         *,
         comment: str | StringAttr | None = None,
-        destination: R1InvT | None = None,
+        register_out: R1InvT | None = None,
     ):
         if isinstance(comment, str):
             comment = StringAttr(comment)
-
         super().__init__(
-            operands=[source],
+            operands=[register_in],
             attributes={
                 "comment": comment,
             },
-            result_types=[destination],
+            result_types=[register_out],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        return (self.source,)
+        return (self.register_in,)
 
 
-class R_RM_Operation(
+class RM_Operation(
     Generic[R1InvT, R2InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
-    A base class for x86 operations that have one register and one memory access with an optional offset.
+    A base class for x86 operations that have one register read and written to and one
+    memory access with an optional offset.
     """
 
-    r1 = operand_def(R1InvT)
-    r2 = operand_def(R2InvT)
-    offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
+    register_in = operand_def(R1InvT)
+    register_out = result_def(R1InvT)
 
-    result = result_def(R1InvT)
+    memory = operand_def(R2InvT)
+    memory_offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
-        r2: Operation | SSAValue,
-        offset: int | IntegerAttr,
+        register_in: Operation | SSAValue,
+        memory: Operation | SSAValue,
+        memory_offset: int | IntegerAttr,
         *,
         comment: str | StringAttr | None = None,
-        result: R1InvT,
+        register_out: R1InvT,
     ):
-        if isinstance(offset, int):
-            offset = IntegerAttr(offset, 64)
+        if isinstance(memory_offset, int):
+            memory_offset = IntegerAttr(memory_offset, 64)
         if isinstance(comment, str):
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[r1, r2],
+            operands=[register_in, memory],
             attributes={
-                "offset": offset,
+                "memory_offset": memory_offset,
                 "comment": comment,
             },
-            result_types=[result],
+            result_types=[register_out],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        memory_access = memory_access_str(self.r2, self.offset)
-        destination = assembly_arg_str(self.r1)
+        memory_access = memory_access_str(self.memory, self.memory_offset)
+        destination = assembly_arg_str(self.register_in)
         return (destination, memory_access)
 
     @classmethod
     def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
         attributes = dict[str, Attribute]()
         if offset := cls.parse_optional_memory_access_offset(parser):
-            attributes["offset"] = offset
+            attributes["memory_offset"] = offset
         return attributes
 
     def custom_print_attributes(self, printer: Printer) -> Set[str]:
         printer.print(", ")
-        print_immediate_value(printer, self.offset)
-        return {"offset"}
+        print_immediate_value(printer, self.memory_offset)
+        return {"memory_offset"}
 
 
-class R_M_Operation(
+class DM_Operation(
     Generic[R1InvT, R2InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
-    A base class for x86 operations that have one register and one memory access with an optional offset.
+    A base class for x86 operations that load from memory into a destination register.
     """
 
-    r1 = operand_def(R1InvT)
-    offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
-
-    result = result_def(R2InvT)
+    destination = result_def(R1InvT)
+    memory = operand_def(R2InvT)
+    memory_offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
-        offset: int | IntegerAttr,
+        memory: Operation | SSAValue,
+        memory_offset: int | IntegerAttr,
         *,
         comment: str | StringAttr | None = None,
-        result: R2InvT,
+        destination: R1InvT,
     ):
-        if isinstance(offset, int):
-            offset = IntegerAttr(offset, 64)
+        if isinstance(memory_offset, int):
+            memory_offset = IntegerAttr(memory_offset, 64)
         if isinstance(comment, str):
             comment = StringAttr(comment)
-
         super().__init__(
-            operands=[r1],
+            operands=[memory],
             attributes={
-                "offset": offset,
+                "memory_offset": memory_offset,
                 "comment": comment,
             },
-            result_types=[result],
+            result_types=[destination],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        memory_access = memory_access_str(self.r1, self.offset)
-        destination = assembly_arg_str(self.result)
+        memory_access = memory_access_str(self.memory, self.memory_offset)
+        destination = assembly_arg_str(self.destination)
         return (destination, memory_access)
 
     @classmethod
     def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
         attributes = dict[str, Attribute]()
         if offset := cls.parse_optional_memory_access_offset(parser):
-            attributes["offset"] = offset
+            attributes["memory_offset"] = offset
         return attributes
 
     def custom_print_attributes(self, printer: Printer) -> Set[str]:
         printer.print(", ")
-        print_immediate_value(printer, self.offset)
-        return {"offset"}
+        print_immediate_value(printer, self.memory_offset)
+        return {"memory_offset"}
 
 
-class R_RImm_Operation(Generic[R1InvT], X86Instruction, X86CustomFormatOperation, ABC):
+class RI_Operation(Generic[R1InvT], X86Instruction, X86CustomFormatOperation, ABC):
     """
-    A base class for x86 operations that have one register and an immediate value.
+    A base class for x86 operations that have one register that is read and written to
+    and an immediate value.
     """
 
-    r1 = operand_def(R1InvT)
-    immediate = attr_def(IntegerAttr)
+    register_in = operand_def(R1InvT)
+    register_out = result_def(R1InvT)
 
-    result = result_def(R1InvT)
+    immediate = attr_def(IntegerAttr)
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
+        register_in: Operation | SSAValue,
         immediate: int | IntegerAttr,
         *,
         comment: str | StringAttr | None = None,
-        result: R1InvT,
+        register_out: R1InvT,
     ):
         if isinstance(immediate, int):
             immediate = IntegerAttr(
@@ -394,16 +424,16 @@ def __init__(
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[r1],
+            operands=[register_in],
             attributes={
                 "immediate": immediate,
                 "comment": comment,
             },
-            result_types=[result],
+            result_types=[register_out],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        return self.r1, self.immediate
+        return self.register_in, self.immediate
 
     @classmethod
     def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
@@ -421,69 +451,71 @@ def custom_print_attributes(self, printer: Printer) -> Set[str]:
         return {"immediate"}
 
 
-class M_MR_Operation(
+class MS_Operation(
     Generic[R1InvT, R2InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
-    A base class for x86 operations that have one memory reference and one register.
+    A base class for x86 operations that have one memory reference and one source
+    register.
     """
 
-    r1 = operand_def(R1InvT)
-    r2 = operand_def(R2InvT)
-    offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
+    memory = operand_def(R1InvT)
+    memory_offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
+    source = operand_def(R2InvT)
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
-        r2: Operation | SSAValue,
-        offset: int | IntegerAttr,
+        memory: Operation | SSAValue,
+        source: Operation | SSAValue,
+        memory_offset: int | IntegerAttr,
         *,
         comment: str | StringAttr | None = None,
     ):
-        if isinstance(offset, int):
-            offset = IntegerAttr(offset, 64)
+        if isinstance(memory_offset, int):
+            memory_offset = IntegerAttr(memory_offset, 64)
         if isinstance(comment, str):
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[r1, r2],
+            operands=[memory, source],
             attributes={
-                "offset": offset,
+                "memory_offset": memory_offset,
                 "comment": comment,
             },
             result_types=[],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        memory_access = memory_access_str(self.r1, self.offset)
-        return memory_access, self.r2
+        memory_access = memory_access_str(self.memory, self.memory_offset)
+        return memory_access, self.source
 
     @classmethod
     def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
         attributes = dict[str, Attribute]()
         if offset := cls.parse_optional_memory_access_offset(parser):
-            attributes["offset"] = offset
+            attributes["memory_offset"] = offset
         return attributes
 
     def custom_print_attributes(self, printer: Printer) -> Set[str]:
         printer.print(", ")
-        print_immediate_value(printer, self.offset)
-        return {"offset"}
+        print_immediate_value(printer, self.memory_offset)
+        return {"memory_offset"}
 
 
-class M_MImm_Operation(Generic[R1InvT], X86Instruction, X86CustomFormatOperation, ABC):
+class MI_Operation(Generic[R1InvT], X86Instruction, X86CustomFormatOperation, ABC):
     """
-    A base class for x86 operations that have one memory reference and an immediate value.
+    A base class for x86 operations that have one memory reference and an immediate
+    value.
     """
 
-    r1 = operand_def(R1InvT)
+    memory = operand_def(R1InvT)
+    memory_offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
     immediate = attr_def(IntegerAttr)
-    offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
-        offset: int | IntegerAttr,
+        memory: Operation | SSAValue,
+        memory_offset: int | IntegerAttr,
         immediate: int | IntegerAttr,
         *,
         comment: str | StringAttr | None = None,
@@ -492,16 +524,16 @@ def __init__(
             immediate = IntegerAttr(
                 immediate, 32
             )  # the default immediate size is 32 bits
-        if isinstance(offset, int):
-            offset = IntegerAttr(offset, 64)
+        if isinstance(memory_offset, int):
+            memory_offset = IntegerAttr(memory_offset, 64)
         if isinstance(comment, str):
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[r1],
+            operands=[memory],
             attributes={
                 "immediate": immediate,
-                "offset": offset,
+                "memory_offset": memory_offset,
                 "comment": comment,
             },
             result_types=[],
@@ -509,7 +541,7 @@ def __init__(
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
         immediate = assembly_arg_str(self.immediate)
-        memory_access = memory_access_str(self.r1, self.offset)
+        memory_access = memory_access_str(self.memory, self.memory_offset)
         return memory_access, immediate
 
     @classmethod
@@ -519,37 +551,37 @@ def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
         attributes["immediate"] = temp
         if parser.parse_optional_punctuation(",") is not None:
             if offset := cls.parse_optional_memory_access_offset(parser):
-                attributes["offset"] = offset
+                attributes["memory_offset"] = offset
         return attributes
 
     def custom_print_attributes(self, printer: Printer) -> Set[str]:
         printer.print(", ")
         print_immediate_value(printer, self.immediate)
-        if self.offset.value.data != 0:
+        if self.memory_offset.value.data != 0:
             printer.print(", ")
-            print_immediate_value(printer, self.offset)
-        return {"immediate", "offset"}
+            print_immediate_value(printer, self.memory_offset)
+        return {"immediate", "memory_offset"}
 
 
-class R_RRImm_Operation(
+class DSI_Operation(
     Generic[R1InvT, R2InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
-    A base class for x86 operations that have one destination register, one source register and an immediate value.
+    A base class for x86 operations that have one destination register, one source
+    register and an immediate value.
     """
 
-    r2 = operand_def(R2InvT)
+    destination = result_def(R1InvT)
+    source = operand_def(R2InvT)
     immediate = attr_def(IntegerAttr)
 
-    r1 = result_def(R1InvT)
-
     def __init__(
         self,
-        r2: Operation | SSAValue,
+        source: Operation | SSAValue,
         immediate: int | IntegerAttr,
         *,
         comment: str | StringAttr | None = None,
-        r1: R1InvT,
+        destination: R1InvT,
     ):
         if isinstance(immediate, int):
             immediate = IntegerAttr(
@@ -559,16 +591,16 @@ def __init__(
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[r2],
+            operands=[source],
             attributes={
                 "immediate": immediate,
                 "comment": comment,
             },
-            result_types=[r1],
+            result_types=[destination],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        return self.r1, self.r2, self.immediate
+        return self.destination, self.source, self.immediate
 
     @classmethod
     def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
@@ -583,51 +615,51 @@ def custom_print_attributes(self, printer: Printer) -> Set[str]:
         return {"immediate"}
 
 
-class R_RMImm_Operation(
+class DMI_Operation(
     Generic[R1InvT, R2InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
-    A base class for x86 operations that have one source register, one memory reference and an immediate value.
+    A base class for x86 operations that have one destination register, one memory
+    reference and an immediate value.
     """
 
-    r2 = operand_def(R2InvT)
+    destination = result_def(R1InvT)
+    memory = operand_def(R2InvT)
+    memory_offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
     immediate = attr_def(IntegerAttr)
-    offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
-
-    r1 = result_def(R1InvT)
 
     def __init__(
         self,
-        r2: Operation | SSAValue,
+        memory: Operation | SSAValue,
         immediate: int | IntegerAttr,
-        offset: int | IntegerAttr,
+        memory_offset: int | IntegerAttr,
         *,
         comment: str | StringAttr | None = None,
-        r1: R1InvT,
+        destination: R1InvT,
     ):
         if isinstance(immediate, int):
             immediate = IntegerAttr(
                 immediate, 32
             )  # the default immediate size is 32 bits
-        if isinstance(offset, int):
-            offset = IntegerAttr(offset, 64)
+        if isinstance(memory_offset, int):
+            memory_offset = IntegerAttr(memory_offset, 64)
         if isinstance(comment, str):
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[r2],
+            operands=[memory],
             attributes={
                 "immediate": immediate,
-                "offset": offset,
+                "memory_offset": memory_offset,
                 "comment": comment,
             },
-            result_types=[r1],
+            result_types=[destination],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        destination = assembly_arg_str(self.r1)
+        destination = assembly_arg_str(self.destination)
         immediate = assembly_arg_str(self.immediate)
-        memory_access = memory_access_str(self.r2, self.offset)
+        memory_access = memory_access_str(self.memory, self.memory_offset)
         return destination, memory_access, immediate
 
     @classmethod
@@ -637,63 +669,62 @@ def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
         attributes["immediate"] = temp
         if parser.parse_optional_punctuation(",") is not None:
             if offset := cls.parse_optional_memory_access_offset(parser):
-                attributes["offset"] = offset
+                attributes["memory_offset"] = offset
         return attributes
 
     def custom_print_attributes(self, printer: Printer) -> Set[str]:
         printer.print(", ")
         print_immediate_value(printer, self.immediate)
-        if self.offset.value.data != 0:
+        if self.memory_offset.value.data != 0:
             printer.print(", ")
-            print_immediate_value(printer, self.offset)
-        return {"immediate", "offset"}
+            print_immediate_value(printer, self.memory_offset)
+        return {"immediate", "memory_offset"}
 
 
-class M_M_Operation(Generic[R1InvT], X86Instruction, X86CustomFormatOperation, ABC):
+class M_Operation(Generic[R1InvT], X86Instruction, X86CustomFormatOperation, ABC):
     """
-    A base class for x86 operations with a memory reference that's both a source and a
-    destination
+    A base class for x86 operations with a memory reference.
     """
 
-    source = operand_def(R1InvT)
-    offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
+    memory = operand_def(R1InvT)
+    memory_offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
 
     def __init__(
         self,
-        source: Operation | SSAValue,
-        offset: int | IntegerAttr,
+        memory: Operation | SSAValue,
+        memory_offset: int | IntegerAttr,
         *,
         comment: str | StringAttr | None = None,
     ):
         if isinstance(comment, str):
             comment = StringAttr(comment)
-        if isinstance(offset, int):
-            offset = IntegerAttr(offset, 64)
+        if isinstance(memory_offset, int):
+            memory_offset = IntegerAttr(memory_offset, 64)
 
         super().__init__(
-            operands=[source],
+            operands=[memory],
             attributes={
-                "offset": offset,
+                "memory_offset": memory_offset,
                 "comment": comment,
             },
             result_types=[],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        memory_access = memory_access_str(self.source, self.offset)
+        memory_access = memory_access_str(self.memory, self.memory_offset)
         return (memory_access,)
 
     @classmethod
     def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
         attributes = dict[str, Attribute]()
         if offset := cls.parse_optional_memory_access_offset(parser):
-            attributes["offset"] = offset
+            attributes["memory_offset"] = offset
         return attributes
 
     def custom_print_attributes(self, printer: Printer) -> Set[str]:
         printer.print(", ")
-        print_immediate_value(printer, self.offset)
-        return {"offset"}
+        print_immediate_value(printer, self.memory_offset)
+        return {"memory_offset"}
 
 
 class ConditionalJumpOperation(X86Instruction, X86CustomFormatOperation, ABC):
@@ -815,175 +846,175 @@ def parse(cls, parser: Parser) -> Self:
         return op
 
 
-class RRROperation(
+class RSS_Operation(
     Generic[R1InvT, R2InvT, R3InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
-    A base class for x86 operations that have three registers.
+    A base class for x86 operations that have one register that is read and written to,
+    and two source registers.
     """
 
-    r1 = operand_def(R1InvT)
-    r2 = operand_def(R2InvT)
-    r3 = operand_def(R3InvT)
-
-    result = result_def(R1InvT)
+    register_in = operand_def(R1InvT)
+    register_out = result_def(R1InvT)
+    source1 = operand_def(R2InvT)
+    source2 = operand_def(R3InvT)
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
-        r2: Operation | SSAValue,
-        r3: Operation | SSAValue,
+        register_in: Operation | SSAValue,
+        source1: Operation | SSAValue,
+        source2: Operation | SSAValue,
         *,
         comment: str | StringAttr | None = None,
-        result: R1InvT,
+        register_out: R1InvT,
     ):
         if isinstance(comment, str):
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[r1, r2, r3],
+            operands=[register_in, source1, source2],
             attributes={
                 "comment": comment,
             },
-            result_types=[result],
+            result_types=[register_out],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        return self.r1, self.r2, self.r3
+        return self.register_in, self.source1, self.source2
 
 
 # endregion
 
 
 @irdl_op_definition
-class RR_AddOp(R_RR_Operation[GeneralRegisterType, GeneralRegisterType]):
+class RS_AddOp(RS_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    Adds the registers r1 and r2 and stores the result in r1.
+    Adds the registers r and s and stores the result in r.
     ```C
-    x[r1] = x[r1] + x[r2]
+    x[r] = x[r] + x[s]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/add).
     """
 
-    name = "x86.rr.add"
+    name = "x86.rs.add"
 
 
 @irdl_op_definition
-class RR_SubOp(R_RR_Operation[GeneralRegisterType, GeneralRegisterType]):
+class RS_SubOp(RS_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    subtracts r2 from r1 and stores the result in r1.
+    subtracts s from r and stores the result in r.
     ```C
-    x[r1] = x[r1] - x[r2]
+    x[r] = x[r] - x[s]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/sub).
     """
 
-    name = "x86.rr.sub"
+    name = "x86.rs.sub"
 
 
 @irdl_op_definition
-class RR_ImulOp(R_RR_Operation[GeneralRegisterType, GeneralRegisterType]):
+class RS_ImulOp(RS_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    Multiplies the registers r1 and r2 and stores the result in r1.
+    Multiplies the registers r and s and stores the result in r.
     ```C
-    x[r1] = x[r1] * x[r2]
+    x[r] = x[r] * x[s]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/imul).
     """
 
-    name = "x86.rr.imul"
+    name = "x86.rs.imul"
 
 
 @irdl_op_definition
-class RR_AndOp(R_RR_Operation[GeneralRegisterType, GeneralRegisterType]):
+class RS_AndOp(RS_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    bitwise and of r1 and r2, stored in r1
+    bitwise and of r and s, stored in r
     ```C
-    x[r1] = x[r1] & x[r2]
+    x[r] = x[r] & x[s]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/and).
     """
 
-    name = "x86.rr.and"
+    name = "x86.rs.and"
 
 
 @irdl_op_definition
-class RR_OrOp(R_RR_Operation[GeneralRegisterType, GeneralRegisterType]):
+class RS_OrOp(RS_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    bitwise or of r1 and r2, stored in r1
+    bitwise or of r and s, stored in r
     ```C
-    x[r1] = x[r1] | x[r2]
+    x[r] = x[r] | x[s]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/or).
     """
 
-    name = "x86.rr.or"
+    name = "x86.rs.or"
 
 
 @irdl_op_definition
-class RR_XorOp(R_RR_Operation[GeneralRegisterType, GeneralRegisterType]):
+class RS_XorOp(RS_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    bitwise xor of r1 and r2, stored in r1
+    bitwise xor of r and s, stored in r
     ```C
-    x[r1] = x[r1] ^ x[r2]
+    x[r] = x[r] ^ x[s]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/xor).
     """
 
-    name = "x86.rr.xor"
+    name = "x86.rs.xor"
 
 
 @irdl_op_definition
-class RR_MovOp(R_RR_Operation[GeneralRegisterType, GeneralRegisterType]):
+class RS_MovOp(RS_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    Copies the value of r1 into r2.
+    Copies the value of s into r.
     ```C
-    x[r1] = x[r2]
+    x[r] = x[s]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/mov).
     """
 
-    name = "x86.rr.mov"
+    name = "x86.rs.mov"
 
 
 @irdl_op_definition
-class R_PushOp(X86Instruction, X86CustomFormatOperation):
+class S_PushOp(X86Instruction, X86CustomFormatOperation):
     """
-    Decreases %rsp and places r1 at the new memory location pointed to by %rsp.
+    Decreases %rsp and places s at the new memory location pointed to by %rsp.
 
     See external [documentation](https://www.felixcloutier.com/x86/push).
     """
 
-    name = "x86.r.push"
+    name = "x86.s.push"
 
-    rsp_input = operand_def(RSP)
+    rsp_in = operand_def(RSP)
+    rsp_out = result_def(RSP)
     source = operand_def(R1InvT)
-    rsp_output = result_def(RSP)
 
     def __init__(
         self,
-        rsp_input: Operation | SSAValue,
+        resp_in: Operation | SSAValue,
         source: Operation | SSAValue,
         *,
         comment: str | StringAttr | None = None,
-        rsp_output: GeneralRegisterType,
+        rsp_out: GeneralRegisterType,
     ):
         if isinstance(comment, str):
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[rsp_input, source],
+            operands=[resp_in, source],
             attributes={
                 "comment": comment,
             },
-            result_types=[rsp_output],
+            result_types=[rsp_out],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
@@ -991,36 +1022,36 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
 
 
 @irdl_op_definition
-class R_PopOp(X86Instruction, X86CustomFormatOperation):
+class D_PopOp(X86Instruction, X86CustomFormatOperation):
     """
-    Copies the value at the top of the stack into r1 and increases %rsp.
+    Copies the value at the top of the stack into d and increases %rsp.
 
     See external [documentation](https://www.felixcloutier.com/x86/pop).
     """
 
-    name = "x86.r.pop"
+    name = "x86.d.pop"
 
-    rsp_input = operand_def(RSP)
+    rsp_in = operand_def(RSP)
+    rsp_out = result_def(RSP)
     destination = result_def(R1InvT)
-    rsp_output = result_def(RSP)
 
     def __init__(
         self,
-        rsp_input: Operation | SSAValue,
+        rsp_in: Operation | SSAValue,
         *,
         comment: str | StringAttr | None = None,
         destination: X86RegisterType,
-        rsp_output: GeneralRegisterType,
+        rsp_out: GeneralRegisterType,
     ):
         if isinstance(comment, str):
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[rsp_input],
+            operands=[rsp_in],
             attributes={
                 "comment": comment,
             },
-            result_types=[destination, rsp_output],
+            result_types=[destination, rsp_out],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
@@ -1028,11 +1059,11 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
 
 
 @irdl_op_definition
-class R_NegOp(R_R_Operation[GeneralRegisterType]):
+class R_NegOp(R_Operation[GeneralRegisterType]):
     """
-    Negates r1 and stores the result in r1.
+    Negates r and stores the result in r.
     ```C
-    x[r1] = -x[r1]
+    x[r] = -x[r]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/neg).
@@ -1042,11 +1073,11 @@ class R_NegOp(R_R_Operation[GeneralRegisterType]):
 
 
 @irdl_op_definition
-class R_NotOp(R_R_Operation[GeneralRegisterType]):
+class R_NotOp(R_Operation[GeneralRegisterType]):
     """
-    bitwise not of r1, stored in r1
+    bitwise not of r, stored in r
     ```C
-    x[r1] = ~x[r1]
+    x[r] = ~x[r]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/not).
@@ -1056,11 +1087,11 @@ class R_NotOp(R_R_Operation[GeneralRegisterType]):
 
 
 @irdl_op_definition
-class R_IncOp(R_R_Operation[GeneralRegisterType]):
+class R_IncOp(R_Operation[GeneralRegisterType]):
     """
-    Increments r1 by 1 and stores the result in r1.
+    Increments r by 1 and stores the result in r.
     ```C
-    x[r1] = x[r1] + 1
+    x[r] = x[r] + 1
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/inc).
@@ -1070,11 +1101,11 @@ class R_IncOp(R_R_Operation[GeneralRegisterType]):
 
 
 @irdl_op_definition
-class R_DecOp(R_R_Operation[GeneralRegisterType]):
+class R_DecOp(R_Operation[GeneralRegisterType]):
     """
-    Decrements r1 by 1 and stores the result in r1.
+    Decrements r by 1 and stores the result in r.
     ```C
-    x[r1] = x[r1] - 1
+    x[r] = x[r] - 1
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/dec).
@@ -1084,16 +1115,17 @@ class R_DecOp(R_R_Operation[GeneralRegisterType]):
 
 
 @irdl_op_definition
-class R_IDivOp(X86Instruction, X86CustomFormatOperation):
+class S_IDivOp(X86Instruction, X86CustomFormatOperation):
     """
-    Divides the value in RDX:RAX by r1 and stores the quotient in RAX and the remainder in RDX.
+    Divides the value in RDX:RAX by s and stores the quotient in RAX and the remainder
+    in RDX.
 
     See external [documentation](https://www.felixcloutier.com/x86/idiv).
     """
 
-    name = "x86.r.idiv"
+    name = "x86.s.idiv"
 
-    r1 = operand_def(R1InvT)
+    source = operand_def(R1InvT)
     rdx_input = operand_def(RDX)
     rax_input = operand_def(RAX)
 
@@ -1102,7 +1134,7 @@ class R_IDivOp(X86Instruction, X86CustomFormatOperation):
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
+        source: Operation | SSAValue,
         rdx_input: Operation | SSAValue,
         rax_input: Operation | SSAValue,
         *,
@@ -1114,7 +1146,7 @@ def __init__(
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[r1, rdx_input, rax_input],
+            operands=[source, rdx_input, rax_input],
             attributes={
                 "comment": comment,
             },
@@ -1122,23 +1154,24 @@ def __init__(
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        return (self.r1,)
+        return (self.source,)
 
 
 @irdl_op_definition
-class R_ImulOp(X86Instruction, X86CustomFormatOperation):
+class S_ImulOp(X86Instruction, X86CustomFormatOperation):
     """
-    The source operand is multiplied by the value in the RAX register and the product is stored in the RDX:RAX registers.
+    The source operand is multiplied by the value in the RAX register and the product is
+    stored in the RDX:RAX registers.
     ```C
-    x[RDX:RAX] = x[RAX] * r1
+    x[RDX:RAX] = x[RAX] * s
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/imul).
     """
 
-    name = "x86.r.imul"
+    name = "x86.s.imul"
 
-    r1 = operand_def(GeneralRegisterType)
+    source = operand_def(GeneralRegisterType)
     rax_input = operand_def(RAX)
 
     rdx_output = result_def(RDX)
@@ -1146,7 +1179,7 @@ class R_ImulOp(X86Instruction, X86CustomFormatOperation):
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
+        source: Operation | SSAValue,
         rax_input: Operation | SSAValue,
         *,
         comment: str | StringAttr | None = None,
@@ -1157,7 +1190,7 @@ def __init__(
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[r1, rax_input],
+            operands=[source, rax_input],
             attributes={
                 "comment": comment,
             },
@@ -1165,15 +1198,16 @@ def __init__(
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        return (self.r1,)
+        return (self.source,)
 
 
 @irdl_op_definition
-class RM_AddOp(R_RM_Operation[GeneralRegisterType, GeneralRegisterType]):
+class RM_AddOp(RM_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    Adds the value from the memory location pointed to by r2 to r1 and stores the result in r1.
+    Adds the value from the memory location pointed to by m to r and stores the result
+    in r.
     ```C
-    x[r1] = x[r1] + [x[r2]]
+    x[r] = x[r] + [x[m]]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/add).
@@ -1183,11 +1217,12 @@ class RM_AddOp(R_RM_Operation[GeneralRegisterType, GeneralRegisterType]):
 
 
 @irdl_op_definition
-class RM_SubOp(R_RM_Operation[GeneralRegisterType, GeneralRegisterType]):
+class RM_SubOp(RM_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    Subtracts the value from the memory location pointed to by r2 from r1 and stores the result in r1.
+    Subtracts the value from the memory location pointed to by m from r and stores the
+    result in r.
     ```C
-    x[r1] = x[r1] - [x[r2]]
+    x[r] = x[r] - [x[m]]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/sub).
@@ -1197,11 +1232,12 @@ class RM_SubOp(R_RM_Operation[GeneralRegisterType, GeneralRegisterType]):
 
 
 @irdl_op_definition
-class RM_ImulOp(R_RM_Operation[GeneralRegisterType, GeneralRegisterType]):
+class RM_ImulOp(RM_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    Multiplies the value from the memory location pointed to by r2 with r1 and stores the result in r1.
+    Multiplies the value from the memory location pointed to by m with r and stores the
+    result in r.
     ```C
-    x[r1] = x[r1] * [x[r2]]
+    x[r] = x[r] * [x[m]]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/imul).
@@ -1211,11 +1247,11 @@ class RM_ImulOp(R_RM_Operation[GeneralRegisterType, GeneralRegisterType]):
 
 
 @irdl_op_definition
-class RM_AndOp(R_RM_Operation[GeneralRegisterType, GeneralRegisterType]):
+class RM_AndOp(RM_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    bitwise and of r1 and [r2], stored in r1
+    bitwise and of r and [m], stored in r
     ```C
-    x[r1] = x[r1] & [x[r2]]
+    x[r] = x[r] & [x[m]]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/and).
@@ -1225,11 +1261,11 @@ class RM_AndOp(R_RM_Operation[GeneralRegisterType, GeneralRegisterType]):
 
 
 @irdl_op_definition
-class RM_OrOp(R_RM_Operation[GeneralRegisterType, GeneralRegisterType]):
+class RM_OrOp(RM_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    bitwise or of r1 and [r2], stored in r1
+    bitwise or of r and [m], stored in r
     ```C
-    x[r1] = x[r1] | [x[r2]]
+    x[r] = x[r] | [x[m]]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/or).
@@ -1239,11 +1275,11 @@ class RM_OrOp(R_RM_Operation[GeneralRegisterType, GeneralRegisterType]):
 
 
 @irdl_op_definition
-class RM_XorOp(R_RM_Operation[GeneralRegisterType, GeneralRegisterType]):
+class RM_XorOp(RM_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    bitwise xor of r1 and [r2], stored in r1
+    bitwise xor of r and [m], stored in r
     ```C
-    x[r1] = x[r1] ^ [x[r2]]
+    x[r] = x[r] ^ [x[m]]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/xor).
@@ -1253,354 +1289,354 @@ class RM_XorOp(R_RM_Operation[GeneralRegisterType, GeneralRegisterType]):
 
 
 @irdl_op_definition
-class RM_MovOp(R_M_Operation[GeneralRegisterType, GeneralRegisterType]):
+class DM_MovOp(DM_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    Copies the value from the memory location pointed to by source register r1 into destination register r2.
+    Copies the value from the memory location pointed to by source register m into destination register d.
     ```C
-    x[r2] = [x[r1]]
+    x[d] = [x[m]]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/mov).
     """
 
-    name = "x86.rm.mov"
+    name = "x86.dm.mov"
 
 
 @irdl_op_definition
-class RM_leaOp(R_RM_Operation[GeneralRegisterType, GeneralRegisterType]):
+class DM_LeaOp(DM_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    Loads the effective address of the memory location pointed to by r2 into r1.
+    Loads the effective address of the memory location pointed to by m into d.
     ```C
-    x[r1] = &x[r2]
+    x[d] = &x[m]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/lea).
     """
 
-    name = "x86.rm.lea"
+    name = "x86.dm.lea"
 
 
 @irdl_op_definition
-class RI_AddOp(R_RImm_Operation[GeneralRegisterType]):
+class RI_AddOp(RI_Operation[GeneralRegisterType]):
     """
-    Adds the immediate value to r1 and stores the result in r1.
+    Adds the immediate value to r and stores the result in r.
     ```C
-    x[r1] = x[r1] + immediate
+    x[r] = x[r] + immediate
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/add).
     """
 
-    name = "x86.rimm.add"
+    name = "x86.ri.add"
 
 
 @irdl_op_definition
-class RImm_SubOp(R_RImm_Operation[GeneralRegisterType]):
+class RI_SubOp(RI_Operation[GeneralRegisterType]):
     """
-    Subtracts the immediate value from r1 and stores the result in r1.
+    Subtracts the immediate value from r and stores the result in r.
     ```C
-    x[r1] = x[r1] - immediate
+    x[r] = x[r] - immediate
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/sub).
     """
 
-    name = "x86.rimm.sub"
+    name = "x86.ri.sub"
 
 
 @irdl_op_definition
-class RImm_AndOp(R_RImm_Operation[GeneralRegisterType]):
+class RI_AndOp(RI_Operation[GeneralRegisterType]):
     """
-    bitwise and of r1 and immediate, stored in r1
+    bitwise and of r and immediate, stored in r
     ```C
-    x[r1] = x[r1] & immediate
+    x[r] = x[r] & immediate
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/and).
     """
 
-    name = "x86.rimm.and"
+    name = "x86.ri.and"
 
 
 @irdl_op_definition
-class RImm_OrOp(R_RImm_Operation[GeneralRegisterType]):
+class RI_OrOp(RI_Operation[GeneralRegisterType]):
     """
-    bitwise or of r1 and immediate, stored in r1
+    bitwise or of r and immediate, stored in r
     ```C
-    x[r1] = x[r1] | immediate
+    x[r] = x[r] | immediate
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/or).
     """
 
-    name = "x86.rimm.or"
+    name = "x86.ri.or"
 
 
 @irdl_op_definition
-class RImm_XorOp(R_RImm_Operation[GeneralRegisterType]):
+class RI_XorOp(RI_Operation[GeneralRegisterType]):
     """
-    bitwise xor of r1 and immediate, stored in r1
+    bitwise xor of r and immediate, stored in r
     ```C
-    x[r1] = x[r1] ^ immediate
+    x[r] = x[r] ^ immediate
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/xor).
     """
 
-    name = "x86.rimm.xor"
+    name = "x86.ri.xor"
 
 
 @irdl_op_definition
-class RImm_MovOp(R_RImm_Operation[GeneralRegisterType]):
+class RI_MovOp(RI_Operation[GeneralRegisterType]):
     """
-    Copies the immediate value into r1.
+    Copies the immediate value into r.
     ```C
-    x[r1] = immediate
+    x[r] = immediate
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/mov).
     """
 
-    name = "x86.rimm.mov"
+    name = "x86.ri.mov"
 
 
 @irdl_op_definition
-class MR_AddOp(M_MR_Operation[GeneralRegisterType, GeneralRegisterType]):
+class MS_AddOp(MS_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    Adds the value from r2 to the memory location pointed to by r1.
+    Adds the value from s to the memory location pointed to by m.
     ```C
-    [x[r1]] = [x[r1]] + x[r2]
+    [x[m]] = [x[m]] + x[s]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/add).
     """
 
-    name = "x86.mr.add"
+    name = "x86.ms.add"
 
 
 @irdl_op_definition
-class MR_SubOp(M_MR_Operation[GeneralRegisterType, GeneralRegisterType]):
+class MS_SubOp(MS_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    Subtracts the value from r2 from the memory location pointed to by r1.
-    [x[r1]] = [x[r1]] - x[r2]
+    Subtracts the value from s from the memory location pointed to by m.
+    [x[m]] = [x[m]] - x[s]
 
     See external [documentation](https://www.felixcloutier.com/x86/sub).
     """
 
-    name = "x86.mr.sub"
+    name = "x86.ms.sub"
 
 
 @irdl_op_definition
-class MR_AndOp(M_MR_Operation[GeneralRegisterType, GeneralRegisterType]):
+class MS_AndOp(MS_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    bitwise and of [r1] and r2
-    [x[r1]] = [x[r1]] & x[r2]
+    bitwise and of [m] and s
+    [x[m]] = [x[m]] & x[s]
 
     See external [documentation](https://www.felixcloutier.com/x86/and).
     """
 
-    name = "x86.mr.and"
+    name = "x86.ms.and"
 
 
 @irdl_op_definition
-class MR_OrOp(M_MR_Operation[GeneralRegisterType, GeneralRegisterType]):
+class MS_OrOp(MS_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    bitwise or of [r1] and r2
-    [x[r1]] = [x[r1]] | x[r2]
+    bitwise or of [m] and s
+    [x[m]] = [x[m]] | x[s]
 
     See external [documentation](https://www.felixcloutier.com/x86/or).
     """
 
-    name = "x86.mr.or"
+    name = "x86.ms.or"
 
 
 @irdl_op_definition
-class MR_XorOp(M_MR_Operation[GeneralRegisterType, GeneralRegisterType]):
+class MS_XorOp(MS_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    bitwise xor of [r1] and r2
-    [x[r1]] = [x[r1]] ^ x[r2]
+    bitwise xor of [m] and s
+    [x[m]] = [x[m]] ^ x[s]
 
     See external [documentation](https://www.felixcloutier.com/x86/xor).
     """
 
-    name = "x86.mr.xor"
+    name = "x86.ms.xor"
 
 
 @irdl_op_definition
-class MR_MovOp(M_MR_Operation[GeneralRegisterType, GeneralRegisterType]):
+class MS_MovOp(MS_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    Copies the value from r2 into the memory location pointed to by r1.
-    [x[r1]] = x[r2]
+    Copies the value from s into the memory location pointed to by m.
+    [x[m]] = x[s]
 
     See external [documentation](https://www.felixcloutier.com/x86/mov).
     """
 
-    name = "x86.mr.mov"
+    name = "x86.ms.mov"
 
 
 @irdl_op_definition
-class MImm_AddOp(M_MImm_Operation[GeneralRegisterType]):
+class MI_AddOp(MI_Operation[GeneralRegisterType]):
     """
-    Adds the immediate value to the memory location pointed to by r1.
-    [x[r1]] = [x[r1]] + immediate
+    Adds the immediate value to the memory location pointed to by m.
+    [x[m]] = [x[m]] + immediate
 
     See external [documentation](https://www.felixcloutier.com/x86/add).
     """
 
-    name = "x86.mimm.add"
+    name = "x86.mi.add"
 
 
 @irdl_op_definition
-class MImm_SubOp(M_MImm_Operation[GeneralRegisterType]):
+class MI_SubOp(MI_Operation[GeneralRegisterType]):
     """
-    Subtracts the immediate value from the memory location pointed to by r1.
-    [x[r1]] = [x[r1]] - immediate
+    Subtracts the immediate value from the memory location pointed to by m.
+    [x[m]] = [x[m]] - immediate
 
     See external [documentation](https://www.felixcloutier.com/x86/sub).
     """
 
-    name = "x86.mimm.sub"
+    name = "x86.mi.sub"
 
 
 @irdl_op_definition
-class MImm_AndOp(M_MImm_Operation[GeneralRegisterType]):
+class MI_AndOp(MI_Operation[GeneralRegisterType]):
     """
-    bitwise and of immediate and [r1], stored in [r1]
+    bitwise and of immediate and [m], stored in [m]
     ```C
-    [x[r1]] = [x[r1]] & immediate
+    [x[m]] = [x[m]] & immediate
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/and).
     """
 
-    name = "x86.mimm.and"
+    name = "x86.mi.and"
 
 
 @irdl_op_definition
-class MImm_OrOp(M_MImm_Operation[GeneralRegisterType]):
+class MI_OrOp(MI_Operation[GeneralRegisterType]):
     """
-    bitwise or of immediate and [r1], stored in [r1]
+    bitwise or of immediate and [m], stored in [m]
     ```C
-    [x[r1]] = [x[r1]] | immediate
+    [x[m]] = [x[m]] | immediate
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/or).
     """
 
-    name = "x86.mimm.or"
+    name = "x86.mi.or"
 
 
 @irdl_op_definition
-class MImm_XorOp(M_MImm_Operation[GeneralRegisterType]):
+class MI_XorOp(MI_Operation[GeneralRegisterType]):
     """
-    bitwise xor of immediate and [r1], stored in [r1]
+    bitwise xor of immediate and [m], stored in [m]
     ```C
-    [x[r1]] = [x[r1]] ^ immediate
+    [x[m]] = [x[m]] ^ immediate
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/xor).
     """
 
-    name = "x86.mimm.xor"
+    name = "x86.mi.xor"
 
 
 @irdl_op_definition
-class MImm_MovOp(M_MImm_Operation[GeneralRegisterType]):
+class MI_MovOp(MI_Operation[GeneralRegisterType]):
     """
-    Copies the immediate value into the memory location pointed to by r1.
-    [x[r1]] = immediate
+    Copies the immediate value into the memory location pointed to by m.
+    [x[m]] = immediate
 
     See external [documentation](https://www.felixcloutier.com/x86/mov).
     """
 
-    name = "x86.mimm.mov"
+    name = "x86.mi.mov"
 
 
 @irdl_op_definition
-class RRImm_ImulOp(R_RRImm_Operation[GeneralRegisterType, GeneralRegisterType]):
+class DSI_ImulOp(DSI_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
     Multiplies the immediate value with the source register and stores the result in the destination register.
-    x[r1] = x[r2] * immediate
+    x[d] = x[s] * immediate
 
     See external [documentation](https://www.felixcloutier.com/x86/imul).
     """
 
-    name = "x86.rri.imul"
+    name = "x86.dsi.imul"
 
 
 @irdl_op_definition
-class RMImm_ImulOp(R_RMImm_Operation[GeneralRegisterType, GeneralRegisterType]):
+class DMI_ImulOp(DMI_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    Multiplies the immediate value with the memory location pointed to by r2 and stores the result in r1.
-    x[r1] = [x[r2]] * immediate
+    Multiplies the immediate value with the memory location pointed to by m and stores the result in d.
+    x[d] = [x[m]] * immediate
 
     See external [documentation](https://www.felixcloutier.com/x86/imul).
     """
 
-    name = "x86.rmimm.imul"
+    name = "x86.dmi.imul"
 
 
 @irdl_op_definition
 class M_PushOp(X86Instruction, X86CustomFormatOperation):
     """
-    Decreases %rsp and places [r1] at the new memory location pointed to by %rsp.
+    Decreases %rsp and places [m] at the new memory location pointed to by %rsp.
 
     See external [documentation](https://www.felixcloutier.com/x86/push).
     """
 
     name = "x86.m.push"
 
-    rsp_input = operand_def(RSP)
-    source = operand_def(R1InvT)
-    offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
+    rsp_in = operand_def(RSP)
+    rsp_out = result_def(RSP)
 
-    rsp_output = result_def(RSP)
+    memory = operand_def(R1InvT)
+    memory_offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
 
     def __init__(
         self,
-        rsp_input: Operation | SSAValue,
-        source: Operation | SSAValue,
+        rsp_in: Operation | SSAValue,
+        memory: Operation | SSAValue,
         *,
         comment: str | StringAttr | None = None,
-        offset: int | IntegerAttr,
-        rsp_output: GeneralRegisterType,
+        memory_offset: int | IntegerAttr,
+        rsp_out: GeneralRegisterType,
     ):
         if isinstance(comment, str):
             comment = StringAttr(comment)
-        if isinstance(offset, int):
-            offset = IntegerAttr(offset, 64)
+        if isinstance(memory_offset, int):
+            memory_offset = IntegerAttr(memory_offset, 64)
 
         super().__init__(
-            operands=[rsp_input, source],
+            operands=[rsp_in, memory],
             attributes={
-                "offset": offset,
+                "memory_offset": memory_offset,
                 "comment": comment,
             },
-            result_types=[rsp_output],
+            result_types=[rsp_out],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        memory_access = memory_access_str(self.source, self.offset)
+        memory_access = memory_access_str(self.memory, self.memory_offset)
         return (memory_access,)
 
     @classmethod
     def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
         attributes = dict[str, Attribute]()
         if offset := cls.parse_optional_memory_access_offset(parser):
-            attributes["offset"] = offset
+            attributes["memory_offset"] = offset
         return attributes
 
     def custom_print_attributes(self, printer: Printer) -> Set[str]:
         printer.print(", ")
-        print_immediate_value(printer, self.offset)
-        return {"offset"}
+        print_immediate_value(printer, self.memory_offset)
+        return {"memory_offset"}
 
 
 @irdl_op_definition
 class M_PopOp(X86Instruction, X86CustomFormatOperation):
     """
-    Copies the value at the top of the stack into [r1] and increases %rsp.
-    The value held by r1 is a pointer to the memory location where the value is stored.
+    Copies the value at the top of the stack into [m] and increases %rsp.
+    The value held by m is a pointer to the memory location where the value is stored.
     The only register modified by this operation is %rsp.
 
     See external [documentation](https://www.felixcloutier.com/x86/pop).
@@ -1608,37 +1644,35 @@ class M_PopOp(X86Instruction, X86CustomFormatOperation):
 
     name = "x86.m.pop"
 
-    rsp_input = operand_def(RSP)
-    destination = operand_def(
-        GeneralRegisterType
-    )  # the destination is a pointer to the memory location and the register itself is not modified
-    offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
-    rsp_output = result_def(RSP)
+    rsp_in = operand_def(RSP)
+    memory = operand_def(GeneralRegisterType)
+    memory_offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
+    rsp_out = result_def(RSP)
 
     def __init__(
         self,
-        rsp_input: Operation | SSAValue,
-        destination: Operation | SSAValue,
+        rsp_in: Operation | SSAValue,
+        memory: Operation | SSAValue,
         *,
         comment: str | StringAttr | None = None,
-        offset: int | IntegerAttr,
-        rsp_output: GeneralRegisterType,
+        memory_offset: int | IntegerAttr,
+        rsp_out: GeneralRegisterType,
     ):
-        if isinstance(offset, int):
-            offset = IntegerAttr(offset, 64)
+        if isinstance(memory_offset, int):
+            memory_offset = IntegerAttr(memory_offset, 64)
         if isinstance(comment, str):
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[rsp_input, destination],
+            operands=[rsp_in, memory],
             attributes={
                 "comment": comment,
             },
-            result_types=[rsp_output],
+            result_types=[rsp_out],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        memory_access = memory_access_str(self.destination, self.offset)
+        memory_access = memory_access_str(self.memory, self.memory_offset)
         return (memory_access,)
 
     @classmethod
@@ -1648,21 +1682,21 @@ def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
             parser, IntegerType(64, Signedness.SIGNED)
         )
         if temp is not None:
-            attributes["offset"] = temp
+            attributes["memory_offset"] = temp
         return attributes
 
     def custom_print_attributes(self, printer: Printer) -> Set[str]:
         printer.print(", ")
-        print_immediate_value(printer, self.offset)
-        return {"offset"}
+        print_immediate_value(printer, self.memory_offset)
+        return {"memory_offset"}
 
 
 @irdl_op_definition
-class M_NegOp(M_M_Operation[GeneralRegisterType]):
+class M_NegOp(M_Operation[GeneralRegisterType]):
     """
-    Negates the value at the memory location pointed to by r1.
+    Negates the value at the memory location pointed to by m.
     ```C
-    [x[r1]] = -[x[r1]]
+    [x[m]] = -[x[m]]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/neg).
@@ -1672,11 +1706,11 @@ class M_NegOp(M_M_Operation[GeneralRegisterType]):
 
 
 @irdl_op_definition
-class M_NotOp(M_M_Operation[GeneralRegisterType]):
+class M_NotOp(M_Operation[GeneralRegisterType]):
     """
-    bitwise not of [r1], stored in [r1]
+    bitwise not of [m], stored in [m]
     ```C
-    [x[r1]] = ~[x[r1]]
+    [x[m]] = ~[x[m]]
     ```
 
     See external [documentation](https://www.felixcloutier.com/x86/not).
@@ -1686,10 +1720,10 @@ class M_NotOp(M_M_Operation[GeneralRegisterType]):
 
 
 @irdl_op_definition
-class M_IncOp(M_M_Operation[GeneralRegisterType]):
+class M_IncOp(M_Operation[GeneralRegisterType]):
     """
-    Increments the value at the memory location pointed to by r1.
-    [x[r1]] = [x[r1]] + 1
+    Increments the value at the memory location pointed to by m.
+    [x[m]] = [x[m]] + 1
 
     See external [documentation](https://www.felixcloutier.com/x86/inc).
     """
@@ -1698,10 +1732,10 @@ class M_IncOp(M_M_Operation[GeneralRegisterType]):
 
 
 @irdl_op_definition
-class M_DecOp(M_M_Operation[GeneralRegisterType]):
+class M_DecOp(M_Operation[GeneralRegisterType]):
     """
-    Decrements the value at the memory location pointed to by r1.
-    [x[r1]] = [x[r1]] - 1
+    Decrements the value at the memory location pointed to by m.
+    [x[m]] = [x[m]] - 1
 
     See external [documentation](https://www.felixcloutier.com/x86/dec).
     """
@@ -1712,107 +1746,107 @@ class M_DecOp(M_M_Operation[GeneralRegisterType]):
 @irdl_op_definition
 class M_IDivOp(X86Instruction, X86CustomFormatOperation):
     """
-    Divides the value in RDX:RAX by [r1] and stores the quotient in RAX and the remainder in RDX.
+    Divides the value in RDX:RAX by [m] and stores the quotient in RAX and the remainder in RDX.
 
     See external [documentation](https://www.felixcloutier.com/x86/idiv).
     """
 
     name = "x86.m.idiv"
 
-    r1 = operand_def(R1InvT)
-    rdx_input = operand_def(RDX)
-    rax_input = operand_def(RAX)
-    offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
-
-    rdx_output = result_def(RDX)
-    rax_output = result_def(RAX)
+    memory = operand_def(R1InvT)
+    memory_offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
+    rdx_in = operand_def(RDX)
+    rdx_out = result_def(RDX)
+    rax_in = operand_def(RAX)
+    rax_out = result_def(RAX)
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
-        rdx_input: Operation | SSAValue,
-        rax_input: Operation | SSAValue,
-        offset: int | IntegerAttr,
+        memory: Operation | SSAValue,
+        rdx_in: Operation | SSAValue,
+        rax_in: Operation | SSAValue,
+        memory_offset: int | IntegerAttr,
         *,
         comment: str | StringAttr | None = None,
-        rdx_output: GeneralRegisterType,
-        rax_output: GeneralRegisterType,
+        rdx_out: GeneralRegisterType,
+        rax_out: GeneralRegisterType,
     ):
-        if isinstance(offset, int):
-            offset = IntegerAttr(offset, 64)
+        if isinstance(memory_offset, int):
+            memory_offset = IntegerAttr(memory_offset, 64)
         if isinstance(comment, str):
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[r1, rdx_input, rax_input],
+            operands=[memory, rdx_in, rax_in],
             attributes={
-                "offset": offset,
+                "memory_offset": memory_offset,
                 "comment": comment,
             },
-            result_types=[rdx_output, rax_output],
+            result_types=[rdx_out, rax_out],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        memory_access = memory_access_str(self.r1, self.offset)
+        memory_access = memory_access_str(self.memory, self.memory_offset)
         return (memory_access,)
 
     @classmethod
     def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
         attributes = dict[str, Attribute]()
         if offset := cls.parse_optional_memory_access_offset(parser):
-            attributes["offset"] = offset
+            attributes["memory_offset"] = offset
         return attributes
 
     def custom_print_attributes(self, printer: Printer) -> Set[str]:
         printer.print(", ")
-        print_immediate_value(printer, self.offset)
-        return {"offset"}
+        print_immediate_value(printer, self.memory_offset)
+        return {"memory_offset"}
 
 
 @irdl_op_definition
 class M_ImulOp(X86Instruction, X86CustomFormatOperation):
     """
     The source operand is multiplied by the value in the RAX register and the product is stored in the RDX:RAX registers.
-    x[RDX:RAX] = x[RAX] * [x[r1]]
+    x[RDX:RAX] = x[RAX] * [x[m]]
 
     See external [documentation](https://www.felixcloutier.com/x86/imul).
     """
 
     name = "x86.m.imul"
 
-    r1 = operand_def(GeneralRegisterType)
-    rax_input = operand_def(RAX)
-    offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
+    memory = operand_def(GeneralRegisterType)
+    memory_offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
 
-    rdx_output = result_def(RDX)
-    rax_output = result_def(RAX)
+    rdx_out = result_def(RDX)
+
+    rax_in = operand_def(RAX)
+    rax_out = result_def(RAX)
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
-        rax_input: Operation | SSAValue,
-        offset: int | IntegerAttr,
+        memory: Operation | SSAValue,
+        rax_in: Operation | SSAValue,
+        memory_offset: int | IntegerAttr,
         *,
         comment: str | StringAttr | None = None,
-        rdx_output: GeneralRegisterType,
-        rax_output: GeneralRegisterType,
+        rdx_out: GeneralRegisterType,
+        rax_out: GeneralRegisterType,
     ):
-        if isinstance(offset, int):
-            offset = IntegerAttr(offset, 64)
+        if isinstance(memory_offset, int):
+            memory_offset = IntegerAttr(memory_offset, 64)
         if isinstance(comment, str):
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[r1, rax_input],
+            operands=[memory, rax_in],
             attributes={
-                "offset": offset,
+                "memory_offset": memory_offset,
                 "comment": comment,
             },
-            result_types=[rdx_output, rax_output],
+            result_types=[rdx_out, rax_out],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        memory_access = memory_access_str(self.r1, self.offset)
+        memory_access = memory_access_str(self.memory, self.memory_offset)
         return (memory_access,)
 
     @classmethod
@@ -1822,13 +1856,13 @@ def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
             parser, IntegerType(64, Signedness.SIGNED)
         )
         if temp is not None:
-            attributes["offset"] = temp
+            attributes["memory_offset"] = temp
         return attributes
 
     def custom_print_attributes(self, printer: Printer) -> Set[str]:
         printer.print(", ")
-        print_immediate_value(printer, self.offset)
-        return {"offset"}
+        print_immediate_value(printer, self.memory_offset)
+        return {"memory_offset"}
 
 
 @irdl_op_definition
@@ -2027,7 +2061,7 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
 
 
 @irdl_op_definition
-class RR_CmpOp(X86Instruction, X86CustomFormatOperation):
+class SS_CmpOp(X86Instruction, X86CustomFormatOperation):
     """
     Compares the first source operand with the second source operand and sets the status
     flags in the EFLAGS register according to the results.
@@ -2035,17 +2069,17 @@ class RR_CmpOp(X86Instruction, X86CustomFormatOperation):
     See external [documentation](https://www.felixcloutier.com/x86/cmp).
     """
 
-    name = "x86.rr.cmp"
+    name = "x86.ss.cmp"
 
-    r1 = operand_def(R1InvT)
-    r2 = operand_def(R2InvT)
+    source1 = operand_def(R1InvT)
+    source2 = operand_def(R2InvT)
 
     result = result_def(RFLAGSRegisterType)
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
-        r2: Operation | SSAValue,
+        source1: Operation | SSAValue,
+        source2: Operation | SSAValue,
         *,
         comment: str | StringAttr | None = None,
         result: RFLAGSRegisterType,
@@ -2054,7 +2088,7 @@ def __init__(
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[r1, r2],
+            operands=[source1, source2],
             attributes={
                 "comment": comment,
             },
@@ -2062,11 +2096,11 @@ def __init__(
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        return self.r1, self.r2
+        return self.source1, self.source2
 
 
 @irdl_op_definition
-class RM_CmpOp(X86Instruction, X86CustomFormatOperation):
+class SM_CmpOp(X86Instruction, X86CustomFormatOperation):
     """
     Compares the first source operand with the second source operand and sets the status
     flags in the EFLAGS register according to the results.
@@ -2074,40 +2108,40 @@ class RM_CmpOp(X86Instruction, X86CustomFormatOperation):
     See external [documentation](https://www.felixcloutier.com/x86/cmp).
     """
 
-    name = "x86.rm.cmp"
+    name = "x86.sm.cmp"
 
-    r1 = operand_def(GeneralRegisterType)
-    r2 = operand_def(GeneralRegisterType)
-    offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
+    source = operand_def(GeneralRegisterType)
+    memory = operand_def(GeneralRegisterType)
+    memory_offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
 
     result = result_def(RFLAGSRegisterType)
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
-        r2: Operation | SSAValue,
-        offset: int | IntegerAttr,
+        source: Operation | SSAValue,
+        memory: Operation | SSAValue,
+        memory_offset: int | IntegerAttr,
         *,
         comment: str | StringAttr | None = None,
         result: RFLAGSRegisterType,
     ):
-        if isinstance(offset, int):
-            offset = IntegerAttr(offset, 64)
+        if isinstance(memory_offset, int):
+            memory_offset = IntegerAttr(memory_offset, 64)
         if isinstance(comment, str):
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[r1, r2],
+            operands=[source, memory],
             attributes={
-                "offset": offset,
+                "memory_offset": memory_offset,
                 "comment": comment,
             },
             result_types=[result],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        memory_access = memory_access_str(self.r2, self.offset)
-        return self.r1, memory_access
+        memory_access = memory_access_str(self.memory, self.memory_offset)
+        return self.source, memory_access
 
     @classmethod
     def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
@@ -2116,17 +2150,17 @@ def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
             parser, IntegerType(64, Signedness.SIGNED)
         )
         if temp is not None:
-            attributes["offset"] = temp
+            attributes["memory_offset"] = temp
         return attributes
 
     def custom_print_attributes(self, printer: Printer) -> Set[str]:
         printer.print(", ")
-        print_immediate_value(printer, self.offset)
-        return {"offset"}
+        print_immediate_value(printer, self.memory_offset)
+        return {"memory_offset"}
 
 
 @irdl_op_definition
-class RImm_CmpOp(X86Instruction, X86CustomFormatOperation):
+class SI_CmpOp(X86Instruction, X86CustomFormatOperation):
     """
     Compares the first source operand with the second source operand and sets the status
     flags in the EFLAGS register according to the results.
@@ -2134,16 +2168,16 @@ class RImm_CmpOp(X86Instruction, X86CustomFormatOperation):
     See external [documentation](https://www.felixcloutier.com/x86/cmp).
     """
 
-    name = "x86.rimm.cmp"
+    name = "x86.si.cmp"
 
-    r1 = operand_def(GeneralRegisterType)
+    source = operand_def(GeneralRegisterType)
     immediate = attr_def(IntegerAttr)
 
     result = result_def(RFLAGSRegisterType)
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
+        source: Operation | SSAValue,
         immediate: int | IntegerAttr,
         *,
         comment: str | StringAttr | None = None,
@@ -2155,7 +2189,7 @@ def __init__(
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[r1],
+            operands=[source],
             attributes={
                 "immediate": immediate,
                 "comment": comment,
@@ -2164,7 +2198,7 @@ def __init__(
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
-        return self.r1, self.immediate
+        return self.source, self.immediate
 
     @classmethod
     def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
@@ -2180,7 +2214,7 @@ def custom_print_attributes(self, printer: Printer) -> Set[str]:
 
 
 @irdl_op_definition
-class MR_CmpOp(X86Instruction, X86CustomFormatOperation):
+class MS_CmpOp(X86Instruction, X86CustomFormatOperation):
     """
     Compares the first source operand with the second source operand and sets the status
     flags in the EFLAGS register according to the results.
@@ -2188,40 +2222,40 @@ class MR_CmpOp(X86Instruction, X86CustomFormatOperation):
     See external [documentation](https://www.felixcloutier.com/x86/cmp).
     """
 
-    name = "x86.mr.cmp"
+    name = "x86.ms.cmp"
 
-    r1 = operand_def(GeneralRegisterType)
-    r2 = operand_def(GeneralRegisterType)
-    offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
+    memory = operand_def(GeneralRegisterType)
+    memory_offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
+    source = operand_def(GeneralRegisterType)
 
     result = result_def(RFLAGSRegisterType)
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
-        r2: Operation | SSAValue,
-        offset: int | IntegerAttr,
+        memory: Operation | SSAValue,
+        source: Operation | SSAValue,
+        memory_offset: int | IntegerAttr,
         *,
         comment: str | StringAttr | None = None,
         result: RFLAGSRegisterType,
     ):
-        if isinstance(offset, int):
-            offset = IntegerAttr(offset, 64)
+        if isinstance(memory_offset, int):
+            memory_offset = IntegerAttr(memory_offset, 64)
         if isinstance(comment, str):
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[r1, r2],
+            operands=[memory, source],
             attributes={
-                "offset": offset,
+                "memory_offset": memory_offset,
                 "comment": comment,
             },
             result_types=[result],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        memory_access = memory_access_str(self.r1, self.offset)
-        return memory_access, self.r2
+        memory_access = memory_access_str(self.memory, self.memory_offset)
+        return memory_access, self.source
 
     @classmethod
     def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
@@ -2230,17 +2264,17 @@ def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
             parser, IntegerType(64, Signedness.SIGNED)
         )
         if temp is not None:
-            attributes["offset"] = temp
+            attributes["memory_offset"] = temp
         return attributes
 
     def custom_print_attributes(self, printer: Printer) -> Set[str]:
         printer.print(", ")
-        print_immediate_value(printer, self.offset)
-        return {"offset"}
+        print_immediate_value(printer, self.memory_offset)
+        return {"memory_offset"}
 
 
 @irdl_op_definition
-class MImm_CmpOp(X86Instruction, X86CustomFormatOperation):
+class MI_CmpOp(X86Instruction, X86CustomFormatOperation):
     """
     Compares the first source operand with the second source operand and sets the status
     flags in the EFLAGS register according to the results.
@@ -2248,18 +2282,18 @@ class MImm_CmpOp(X86Instruction, X86CustomFormatOperation):
     See external [documentation](https://www.felixcloutier.com/x86/cmp).
     """
 
-    name = "x86.mimm.cmp"
+    name = "x86.mi.cmp"
 
-    r1 = operand_def(GeneralRegisterType)
+    memory = operand_def(GeneralRegisterType)
+    memory_offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
     immediate = attr_def(IntegerAttr)
-    offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
 
     result = result_def(RFLAGSRegisterType)
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
-        offset: int | IntegerAttr,
+        memory: Operation | SSAValue,
+        memory_offset: int | IntegerAttr,
         immediate: int | IntegerAttr,
         *,
         comment: str | StringAttr | None = None,
@@ -2269,16 +2303,16 @@ def __init__(
             immediate = IntegerAttr(
                 immediate, 32
             )  # the default immediate size is 32 bits
-        if isinstance(offset, int):
-            offset = IntegerAttr(offset, 64)
+        if isinstance(memory_offset, int):
+            memory_offset = IntegerAttr(memory_offset, 64)
         if isinstance(comment, str):
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[r1],
+            operands=[memory],
             attributes={
                 "immediate": immediate,
-                "offset": offset,
+                "memory_offset": memory_offset,
                 "comment": comment,
             },
             result_types=[result],
@@ -2286,7 +2320,7 @@ def __init__(
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
         immediate = assembly_arg_str(self.immediate)
-        memory_access = memory_access_str(self.r1, self.offset)
+        memory_access = memory_access_str(self.memory, self.memory_offset)
         return memory_access, immediate
 
     @classmethod
@@ -2299,15 +2333,15 @@ def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
                 parser, IntegerType(32, Signedness.SIGNED)
             )
             if temp2 is not None:
-                attributes["offset"] = temp2
+                attributes["memory_offset"] = temp2
         return attributes
 
     def custom_print_attributes(self, printer: Printer) -> Set[str]:
         printer.print(", ")
         print_immediate_value(printer, self.immediate)
         printer.print(", ")
-        print_immediate_value(printer, self.offset)
-        return {"immediate", "offset"}
+        print_immediate_value(printer, self.memory_offset)
+        return {"immediate", "memory_offset"}
 
 
 @irdl_op_definition
@@ -2641,35 +2675,35 @@ class C_JzOp(ConditionalJumpOperation):
 
 
 @irdl_op_definition
-class RRR_Vfmadd231pdOp(
-    RRROperation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]
+class RSS_Vfmadd231pdOp(
+    RSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]
 ):
     """
-    Multiply packed double-precision floating-point elements in r2 and r3, add the
-    intermediate result to r1, and store the final result in r1.
+    Multiply packed double-precision floating-point elements in s1 and s2, add the
+    intermediate result to r, and store the final result in r.
 
     See external [documentation](https://www.felixcloutier.com/x86/vfmadd132pd:vfmadd213pd:vfmadd231pd).
     """
 
-    name = "x86.rrr.vfmadd231pd"
+    name = "x86.rss.vfmadd231pd"
 
 
 @irdl_op_definition
-class RRR_Vfmadd231psOp(
-    RRROperation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]
+class RSS_Vfmadd231psOp(
+    RSS_Operation[X86VectorRegisterType, X86VectorRegisterType, X86VectorRegisterType]
 ):
     """
-    Multiply packed single-precision floating-point elements in r2 and r3, add the
-    intermediate result to r1, and store the final result in r1.
+    Multiply packed single-precision floating-point elements in s1 and s2, add the
+    intermediate result to r, and store the final result in r.
 
     See external [documentation](https://www.felixcloutier.com/x86/vfmadd132pd:vfmadd213pd:vfmadd231pd).
     """
 
-    name = "x86.rrr.vfmadd231ps"
+    name = "x86.rss.vfmadd231ps"
 
 
 @irdl_op_definition
-class RR_VmovapdOp(R_RR_Operation[X86VectorRegisterType, X86VectorRegisterType]):
+class RS_VmovapdOp(RS_Operation[X86VectorRegisterType, X86VectorRegisterType]):
     """
     Move aligned packed double precision floating-point values from zmm1 to zmm2 using
     writemask k1
@@ -2677,62 +2711,62 @@ class RR_VmovapdOp(R_RR_Operation[X86VectorRegisterType, X86VectorRegisterType])
     See external [documentation](https://www.felixcloutier.com/x86/movapd).
     """
 
-    name = "x86.rr.vmovapd"
+    name = "x86.rs.vmovapd"
 
 
 @irdl_op_definition
-class MR_VmovapdOp(M_MR_Operation[GeneralRegisterType, X86VectorRegisterType]):
+class MS_VmovapdOp(MS_Operation[GeneralRegisterType, X86VectorRegisterType]):
     """
     Move aligned packed double precision floating-point values from zmm1 to m512 using writemask k1
 
     See external [documentation](https://www.felixcloutier.com/x86/movapd).
     """
 
-    name = "x86.mr.vmovapd"
+    name = "x86.ms.vmovapd"
 
 
 @irdl_op_definition
-class MR_VmovupsOp(M_MR_Operation[GeneralRegisterType, X86VectorRegisterType]):
+class MS_VmovupsOp(MS_Operation[GeneralRegisterType, X86VectorRegisterType]):
     """
     Move aligned packed single precision floating-point values from vector register to memory
 
     See external [documentation](https://www.felixcloutier.com/x86/movups).
     """
 
-    name = "x86.mr.vmovups"
+    name = "x86.ms.vmovups"
 
 
 @irdl_op_definition
-class RM_VmovupsOp(R_M_Operation[GeneralRegisterType, X86VectorRegisterType]):
+class DM_VmovupsOp(DM_Operation[X86VectorRegisterType, GeneralRegisterType]):
     """
     Move aligned packed single precision floating-point values from memory to vector register
 
     See external [documentation](https://www.felixcloutier.com/x86/movups).
     """
 
-    name = "x86.rm.vmovups"
+    name = "x86.dm.vmovups"
 
 
 @irdl_op_definition
-class RM_VbroadcastsdOp(R_M_Operation[GeneralRegisterType, X86VectorRegisterType]):
+class DM_VbroadcastsdOp(DM_Operation[X86VectorRegisterType, GeneralRegisterType]):
     """
     Broadcast low double precision floating-point element in m64 to eight locations in zmm1 using writemask k1
 
     See external [documentation](https://www.felixcloutier.com/x86/vbroadcast).
     """
 
-    name = "x86.rm.vbroadcastsd"
+    name = "x86.dm.vbroadcastsd"
 
 
 @irdl_op_definition
-class RM_VbroadcastssOp(R_M_Operation[GeneralRegisterType, X86VectorRegisterType]):
+class DM_VbroadcastssOp(DM_Operation[X86VectorRegisterType, GeneralRegisterType]):
     """
     Broadcast single precision floating-point element to eight locations in memory
 
     See external [documentation](https://www.felixcloutier.com/x86/vbroadcast).
     """
 
-    name = "x86.rm.vbroadcastss"
+    name = "x86.dm.vbroadcastss"
 
 
 class GetAnyRegisterOperation(


Reviews:
user: login: qaco
state: APPROVED
author_association: COLLABORATOR
submitted_at: 2025-05-20T17:14:10Z
user: login: superlopuh
state: COMMENTED
author_association: MEMBER
submitted_at: 2025-05-21T09:32:18Z
user: login: alexarice
body: I started reviewing but think I have got confused and it's probably not worth putting the same comment on every op. Why don't the operands and results line up with the mnemonics, so that each `r` has a source and destination, a `d` appears only as an result, `s` appears only as operand etc. 
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-05-21T09:50:20Z
user: login: qaco
state: APPROVED
author_association: COLLABORATOR
submitted_at: 2025-05-21T12:10:08Z
user: login: alexarice
state: APPROVED
author_association: COLLABORATOR
submitted_at: 2025-05-21T14:43:47Z
user: login: superlopuh
state: COMMENTED
author_association: MEMBER
submitted_at: 2025-05-21T15:36:59Z
user: login: superlopuh
state: COMMENTED
author_association: MEMBER
submitted_at: 2025-05-21T15:37:14Z
user: login: superlopuh
state: COMMENTED
author_association: MEMBER
submitted_at: 2025-05-21T15:37:47Z
user: login: compor
body: post-merge review: I think this conveys the use clearly enough.

I just wanted to say that names like "register_in" (or "inout") and the like, in my head, imply scope (as in high-level languages), which is not the case in assembly (despite our structured approach within MLIR.
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-05-22T08:41:37Z

Review comments:
diff_hunk: @@ -316,43 +346,42 @@ def custom_print_attributes(self, printer: Printer) -> Set[str]:
         return {"offset"}
 
 
-class R_M_Operation(
+class DM_Operation(
     Generic[R1InvT, R2InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
-    A base class for x86 operations that have one register and one memory access with an optional offset.
+    A base class for x86 operations that load from memory (m, r2) into a destination
+    register (d, r1).
     """
 
-    r1 = operand_def(R1InvT)
+    r2 = operand_def(R2InvT)  # memory source
     offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
-
-    result = result_def(R2InvT)
+    r1 = result_def(R1InvT)  # destination register
path: xdsl/dialects/x86/ops.py
user: login: superlopuh
body: note the `assembly_line_args` function below, the destination register is passed first, making it `r1`. This is the only major functional change in this file, the rest is just renaming.
created_at: 2025-05-21T09:32:18Z
author_association: MEMBER
diff_hunk: @@ -197,83 +224,86 @@ def assembly_line(self) -> str | None:
 # region: Operation Base Classes
 
 
-class R_RR_Operation(
+class RS_Operation(
     Generic[R1InvT, R2InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
     A base class for x86 operations that have two registers.
     """
 
-    r1 = operand_def(R1InvT)
+    r1_source = operand_def(R1InvT)
     r2 = operand_def(R2InvT)
path: xdsl/dialects/x86/ops.py
user: login: alexarice
body: Should this be `s`?
created_at: 2025-05-21T09:46:17Z
author_association: COLLABORATOR
diff_hunk: @@ -197,83 +224,86 @@ def assembly_line(self) -> str | None:
 # region: Operation Base Classes
 
 
-class R_RR_Operation(
+class RS_Operation(
     Generic[R1InvT, R2InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
     A base class for x86 operations that have two registers.
     """
 
-    r1 = operand_def(R1InvT)
+    r1_source = operand_def(R1InvT)
     r2 = operand_def(R2InvT)
 
-    result = result_def(R1InvT)
+    r1_destination = result_def(R1InvT)
 
     def __init__(
         self,
         r1: Operation | SSAValue,
         r2: Operation | SSAValue,
         *,
         comment: str | StringAttr | None = None,
-        result: R1InvT,
+        r1_destination: R1InvT | None = None,
     ):
         if isinstance(comment, str):
             comment = StringAttr(comment)
+        r1 = SSAValue.get(r1)
+        if r1_destination is None:
+            r1_destination = cast(R1InvT, r1.type)
 
         super().__init__(
             operands=[r1, r2],
             attributes={
                 "comment": comment,
             },
-            result_types=[result],
+            result_types=[r1_destination],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        return self.r1, self.r2
+        return self.r1_source, self.r2
 
 
-class R_R_Operation(Generic[R1InvT], X86Instruction, X86CustomFormatOperation, ABC):
+class R_Operation(Generic[R1InvT], X86Instruction, X86CustomFormatOperation, ABC):
     """
     A base class for x86 operations that have one register acting as both source and destination.
     """
 
-    source = operand_def(R1InvT)
-    destination = result_def(R1InvT)
+    r1_source = operand_def(R1InvT)
+    r1_destination = result_def(R1InvT)
 
     def __init__(
         self,
-        source: Operation | SSAValue | None = None,
+        r1_source: Operation | SSAValue | None = None,
         *,
         comment: str | StringAttr | None = None,
-        destination: R1InvT | None = None,
+        r1_destination: R1InvT | None = None,
     ):
         if isinstance(comment, str):
             comment = StringAttr(comment)
-
         super().__init__(
-            operands=[source],
+            operands=[r1_source],
             attributes={
                 "comment": comment,
             },
-            result_types=[destination],
+            result_types=[r1_destination],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        return (self.source,)
+        return (self.r1_source,)
 
 
-class R_RM_Operation(
+class RM_Operation(
     Generic[R1InvT, R2InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
-    A base class for x86 operations that have one register and one memory access with an optional offset.
+    A base class for x86 operations that have one inout register and one memory access
+    with an optional offset.
     """
 
-    r1 = operand_def(R1InvT)
+    r1_source = operand_def(R1InvT)
     r2 = operand_def(R2InvT)
path: xdsl/dialects/x86/ops.py
user: login: alexarice
body: m?
created_at: 2025-05-21T09:47:13Z
author_association: COLLABORATOR
diff_hunk: @@ -86,12 +113,15 @@ def parse(cls, parser: Parser) -> Self:
         pos = parser.pos
         operand_types, result_types = cls.parse_op_type(parser)
         operands = parser.resolve_operands(args, operand_types, pos)
-        return cls.build(
-            operands=operands,
-            result_types=result_types,
-            attributes=attributes,
-            regions=regions,
-        )
+        try:
+            return cls.build(
+                operands=operands,
+                result_types=result_types,
+                attributes=attributes,
+                regions=regions,
+            )
+        except ValueError:
+            raise parser.raise_error(f"{cls}", pos)
path: xdsl/dialects/x86/ops.py
user: login: alexarice
body: Is this meant to be in this PR? 
created_at: 2025-05-21T14:31:39Z
author_association: COLLABORATOR
diff_hunk: @@ -197,194 +227,198 @@ def assembly_line(self) -> str | None:
 # region: Operation Base Classes
 
 
-class R_RR_Operation(
+class RS_Operation(
     Generic[R1InvT, R2InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
-    A base class for x86 operations that have two registers.
+    A base class for x86 operations that have two registers, where the contents of the
path: xdsl/dialects/x86/ops.py
user: login: alexarice
body: Nit, feel free to ignore: "Inout" registers are referred to by a few different things in the docstrings (here it's "updated in-place", below it's "used as source and target"). Wonder if it's worth being consistent.
created_at: 2025-05-21T14:35:05Z
author_association: COLLABORATOR
diff_hunk: @@ -197,194 +227,198 @@ def assembly_line(self) -> str | None:
 # region: Operation Base Classes
 
 
-class R_RR_Operation(
+class RS_Operation(
     Generic[R1InvT, R2InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
-    A base class for x86 operations that have two registers.
+    A base class for x86 operations that have two registers, where the contents of the
+    first one are updated in-place, and the second only read.
     """
 
-    r1 = operand_def(R1InvT)
-    r2 = operand_def(R2InvT)
+    register_in = operand_def(R1InvT)
+    register_out = result_def(R1InvT)
 
-    result = result_def(R1InvT)
+    source = operand_def(R2InvT)
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
-        r2: Operation | SSAValue,
+        register_in: Operation | SSAValue,
+        source: Operation | SSAValue,
         *,
         comment: str | StringAttr | None = None,
-        result: R1InvT,
+        register_out: R1InvT | None = None,
     ):
         if isinstance(comment, str):
             comment = StringAttr(comment)
+        register_in = SSAValue.get(register_in)
+        if register_out is None:
+            register_out = cast(R1InvT, register_in.type)
 
         super().__init__(
-            operands=[r1, r2],
+            operands=[register_in, source],
             attributes={
                 "comment": comment,
             },
-            result_types=[result],
+            result_types=[register_out],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        return self.r1, self.r2
+        return self.register_in, self.source
 
 
-class R_R_Operation(Generic[R1InvT], X86Instruction, X86CustomFormatOperation, ABC):
+class R_Operation(Generic[R1InvT], X86Instruction, X86CustomFormatOperation, ABC):
     """
-    A base class for x86 operations that have one register acting as both source and destination.
+    A base class for x86 operations that have one register acting as both source and
+    destination.
     """
 
-    source = operand_def(R1InvT)
-    destination = result_def(R1InvT)
+    register_in = operand_def(R1InvT)
+    register_out = result_def(R1InvT)
 
     def __init__(
         self,
-        source: Operation | SSAValue | None = None,
+        register_in: Operation | SSAValue | None = None,
         *,
         comment: str | StringAttr | None = None,
-        destination: R1InvT | None = None,
+        register_out: R1InvT | None = None,
     ):
         if isinstance(comment, str):
             comment = StringAttr(comment)
-
         super().__init__(
-            operands=[source],
+            operands=[register_in],
             attributes={
                 "comment": comment,
             },
-            result_types=[destination],
+            result_types=[register_out],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        return (self.source,)
+        return (self.register_in,)
 
 
-class R_RM_Operation(
+class RM_Operation(
     Generic[R1InvT, R2InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
-    A base class for x86 operations that have one register and one memory access with an optional offset.
+    A base class for x86 operations that have one inout register and one memory access
+    with an optional offset.
     """
 
-    r1 = operand_def(R1InvT)
-    r2 = operand_def(R2InvT)
-    offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
+    register_in = operand_def(R1InvT)
+    register_out = result_def(R1InvT)
 
-    result = result_def(R1InvT)
+    memory = operand_def(R2InvT)
+    memory_offset = attr_def(IntegerAttr, default_value=IntegerAttr(0, 64))
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
-        r2: Operation | SSAValue,
-        offset: int | IntegerAttr,
+        register_in: Operation | SSAValue,
+        memory: Operation | SSAValue,
+        memory_offset: int | IntegerAttr,
         *,
         comment: str | StringAttr | None = None,
-        result: R1InvT,
+        register_out: R1InvT,
     ):
-        if isinstance(offset, int):
-            offset = IntegerAttr(offset, 64)
+        if isinstance(memory_offset, int):
+            memory_offset = IntegerAttr(memory_offset, 64)
         if isinstance(comment, str):
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[r1, r2],
+            operands=[register_in, memory],
             attributes={
-                "offset": offset,
+                "memory_offset": memory_offset,
                 "comment": comment,
             },
-            result_types=[result],
+            result_types=[register_out],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        memory_access = memory_access_str(self.r2, self.offset)
-        destination = assembly_arg_str(self.r1)
+        memory_access = memory_access_str(self.memory, self.memory_offset)
+        destination = assembly_arg_str(self.register_in)
         return (destination, memory_access)
 
     @classmethod
     def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
         attributes = dict[str, Attribute]()
         if offset := cls.parse_optional_memory_access_offset(parser):
-            attributes["offset"] = offset
+            attributes["memory_offset"] = offset
         return attributes
 
     def custom_print_attributes(self, printer: Printer) -> Set[str]:
         printer.print(", ")
-        print_immediate_value(printer, self.offset)
-        return {"offset"}
+        print_immediate_value(printer, self.memory_offset)
+        return {"memory_offset"}
 
 
-class R_M_Operation(
+class DM_Operation(
     Generic[R1InvT, R2InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
-    A base class for x86 operations that have one register and one memory access with an optional offset.
+    A base class for x86 operations that load from memory m into a destination register
path: xdsl/dialects/x86/ops.py
user: login: alexarice
body: This docstring mentioning the mnemonics feels weird when the others don't
created_at: 2025-05-21T14:36:14Z
author_association: COLLABORATOR
diff_hunk: @@ -421,69 +455,69 @@ def custom_print_attributes(self, printer: Printer) -> Set[str]:
         return {"immediate"}
 
 
-class M_MR_Operation(
+class MS_Operation(
     Generic[R1InvT, R2InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
     A base class for x86 operations that have one memory reference and one register.
path: xdsl/dialects/x86/ops.py
user: login: alexarice
body: ```suggestion
    A base class for x86 operations that have one memory reference and one source register.
```
created_at: 2025-05-21T14:37:03Z
author_association: COLLABORATOR
diff_hunk: @@ -421,69 +455,69 @@ def custom_print_attributes(self, printer: Printer) -> Set[str]:
         return {"immediate"}
 
 
-class M_MR_Operation(
+class MS_Operation(
     Generic[R1InvT, R2InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
     A base class for x86 operations that have one memory reference and one register.
path: xdsl/dialects/x86/ops.py
user: login: alexarice
body: or something similar?
created_at: 2025-05-21T14:37:38Z
author_association: COLLABORATOR
diff_hunk: @@ -637,63 +670,63 @@ def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
         attributes["immediate"] = temp
         if parser.parse_optional_punctuation(",") is not None:
             if offset := cls.parse_optional_memory_access_offset(parser):
-                attributes["offset"] = offset
+                attributes["memory_offset"] = offset
         return attributes
 
     def custom_print_attributes(self, printer: Printer) -> Set[str]:
         printer.print(", ")
         print_immediate_value(printer, self.immediate)
-        if self.offset.value.data != 0:
+        if self.memory_offset.value.data != 0:
             printer.print(", ")
-            print_immediate_value(printer, self.offset)
-        return {"immediate", "offset"}
+            print_immediate_value(printer, self.memory_offset)
+        return {"immediate", "memory_offset"}
 
 
-class M_M_Operation(Generic[R1InvT], X86Instruction, X86CustomFormatOperation, ABC):
+class M_Operation(Generic[R1InvT], X86Instruction, X86CustomFormatOperation, ABC):
     """
     A base class for x86 operations with a memory reference that's both a source and a
     destination
path: xdsl/dialects/x86/ops.py
user: login: alexarice
body: ```suggestion
    A base class for x86 operations with a memory reference.
```
created_at: 2025-05-21T14:40:22Z
author_association: COLLABORATOR
diff_hunk: @@ -815,224 +848,223 @@ def parse(cls, parser: Parser) -> Self:
         return op
 
 
-class RRROperation(
+class RSS_Operation(
     Generic[R1InvT, R2InvT, R3InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
     A base class for x86 operations that have three registers.
path: xdsl/dialects/x86/ops.py
user: login: alexarice
body: ```suggestion
    A base class for x86 operations that have one inout and two source registers.
```
created_at: 2025-05-21T14:40:49Z
author_association: COLLABORATOR
diff_hunk: @@ -815,224 +848,223 @@ def parse(cls, parser: Parser) -> Self:
         return op
 
 
-class RRROperation(
+class RSS_Operation(
     Generic[R1InvT, R2InvT, R3InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
     A base class for x86 operations that have three registers.
     """
 
-    r1 = operand_def(R1InvT)
-    r2 = operand_def(R2InvT)
-    r3 = operand_def(R3InvT)
-
-    result = result_def(R1InvT)
+    register_in = operand_def(R1InvT)
+    register_out = result_def(R1InvT)
+    source1 = operand_def(R2InvT)
+    source2 = operand_def(R3InvT)
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
-        r2: Operation | SSAValue,
-        r3: Operation | SSAValue,
+        register_in: Operation | SSAValue,
+        source1: Operation | SSAValue,
+        source2: Operation | SSAValue,
         *,
         comment: str | StringAttr | None = None,
-        result: R1InvT,
+        register_out: R1InvT,
     ):
         if isinstance(comment, str):
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[r1, r2, r3],
+            operands=[register_in, source1, source2],
             attributes={
                 "comment": comment,
             },
-            result_types=[result],
+            result_types=[register_out],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        return self.r1, self.r2, self.r3
+        return self.register_in, self.source1, self.source2
 
 
 # endregion
 
 
 @irdl_op_definition
-class RR_AddOp(R_RR_Operation[GeneralRegisterType, GeneralRegisterType]):
+class RS_AddOp(RS_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    Adds the registers r1 and r2 and stores the result in r1.
+    Adds the registers r and s and stores the result in r.
path: xdsl/dialects/x86/ops.py
user: login: alexarice
body: You're going to hate me but this would make more sense if the operands/results were called `r` and `s`
created_at: 2025-05-21T14:41:57Z
author_association: COLLABORATOR
diff_hunk: @@ -86,12 +113,15 @@ def parse(cls, parser: Parser) -> Self:
         pos = parser.pos
         operand_types, result_types = cls.parse_op_type(parser)
         operands = parser.resolve_operands(args, operand_types, pos)
-        return cls.build(
-            operands=operands,
-            result_types=result_types,
-            attributes=attributes,
-            regions=regions,
-        )
+        try:
+            return cls.build(
+                operands=operands,
+                result_types=result_types,
+                attributes=attributes,
+                regions=regions,
+            )
+        except ValueError:
+            raise parser.raise_error(f"{cls}", pos)
path: xdsl/dialects/x86/ops.py
user: login: superlopuh
body: Ah no sorry good catch it was my debugging
created_at: 2025-05-21T15:36:59Z
author_association: MEMBER
diff_hunk: @@ -197,194 +227,198 @@ def assembly_line(self) -> str | None:
 # region: Operation Base Classes
 
 
-class R_RR_Operation(
+class RS_Operation(
     Generic[R1InvT, R2InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
-    A base class for x86 operations that have two registers.
+    A base class for x86 operations that have two registers, where the contents of the
path: xdsl/dialects/x86/ops.py
user: login: superlopuh
body: Definitely worth being consistent, I'll do a pass
created_at: 2025-05-21T15:37:14Z
author_association: MEMBER
diff_hunk: @@ -815,224 +848,223 @@ def parse(cls, parser: Parser) -> Self:
         return op
 
 
-class RRROperation(
+class RSS_Operation(
     Generic[R1InvT, R2InvT, R3InvT], X86Instruction, X86CustomFormatOperation, ABC
 ):
     """
     A base class for x86 operations that have three registers.
     """
 
-    r1 = operand_def(R1InvT)
-    r2 = operand_def(R2InvT)
-    r3 = operand_def(R3InvT)
-
-    result = result_def(R1InvT)
+    register_in = operand_def(R1InvT)
+    register_out = result_def(R1InvT)
+    source1 = operand_def(R2InvT)
+    source2 = operand_def(R3InvT)
 
     def __init__(
         self,
-        r1: Operation | SSAValue,
-        r2: Operation | SSAValue,
-        r3: Operation | SSAValue,
+        register_in: Operation | SSAValue,
+        source1: Operation | SSAValue,
+        source2: Operation | SSAValue,
         *,
         comment: str | StringAttr | None = None,
-        result: R1InvT,
+        register_out: R1InvT,
     ):
         if isinstance(comment, str):
             comment = StringAttr(comment)
 
         super().__init__(
-            operands=[r1, r2, r3],
+            operands=[register_in, source1, source2],
             attributes={
                 "comment": comment,
             },
-            result_types=[result],
+            result_types=[register_out],
         )
 
     def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
-        return self.r1, self.r2, self.r3
+        return self.register_in, self.source1, self.source2
 
 
 # endregion
 
 
 @irdl_op_definition
-class RR_AddOp(R_RR_Operation[GeneralRegisterType, GeneralRegisterType]):
+class RS_AddOp(RS_Operation[GeneralRegisterType, GeneralRegisterType]):
     """
-    Adds the registers r1 and r2 and stores the result in r1.
+    Adds the registers r and s and stores the result in r.
path: xdsl/dialects/x86/ops.py
user: login: superlopuh
body: Train has left the station
created_at: 2025-05-21T15:37:47Z
author_association: MEMBER

PR comments:
user: login: superlopuh
created_at: 2025-05-20T10:25:51Z
body: Basically a revert of #4382
author_association: MEMBER
user: login: codecov[bot]
created_at: 2025-05-20T10:30:54Z
body: ## [Codecov](https://app.codecov.io/gh/xdslproject/xdsl/pull/4429?dropdown=coverage&src=pr&el=h1&utm_medium=referral&utm_source=github&utm_content=comment&utm_campaign=pr+comments&utm_term=xdslproject) Report
:x: Patch coverage is `91.86441%` with `24 lines` in your changes missing coverage. Please review.
:white_check_mark: Project coverage is 89.17%. Comparing base ([`5c2d6c3`](https://app.codecov.io/gh/xdslproject/xdsl/commit/5c2d6c341438cf1b07c30d04e996ff59e0948047?dropdown=coverage&el=desc&utm_medium=referral&utm_source=github&utm_content=comment&utm_campaign=pr+comments&utm_term=xdslproject)) to head ([`fb36883`](https://app.codecov.io/gh/xdslproject/xdsl/commit/fb36883970aeb609ac351b0105d93fddb7bc5406?dropdown=coverage&el=desc&utm_medium=referral&utm_source=github&utm_content=comment&utm_campaign=pr+comments&utm_term=xdslproject)).
:warning: Report is 573 commits behind head on main.

| [Files with missing lines](https://app.codecov.io/gh/xdslproject/xdsl/pull/4429?dropdown=coverage&src=pr&el=tree&utm_medium=referral&utm_source=github&utm_content=comment&utm_campaign=pr+comments&utm_term=xdslproject) | Patch % | Lines |
|---|---|---|
| [xdsl/dialects/x86/ops.py](https://app.codecov.io/gh/xdslproject/xdsl/pull/4429?src=pr&el=tree&filepath=xdsl%2Fdialects%2Fx86%2Fops.py&utm_medium=referral&utm_source=github&utm_content=comment&utm_campaign=pr+comments&utm_term=xdslproject#diff-eGRzbC9kaWFsZWN0cy94ODYvb3BzLnB5) | 91.51% | [23 Missing and 1 partial :warning: ](https://app.codecov.io/gh/xdslproject/xdsl/pull/4429?src=pr&el=tree&utm_medium=referral&utm_source=github&utm_content=comment&utm_campaign=pr+comments&utm_term=xdslproject) |

<details><summary>Additional details and impacted files</summary>



```diff
@@            Coverage Diff             @@
##             main    #4429      +/-   ##
==========================================
- Coverage   89.18%   89.17%   -0.01%     
==========================================
  Files         339      339              
  Lines       45844    45859      +15     
  Branches     5622     5623       +1     
==========================================
+ Hits        40884    40897      +13     
+ Misses       3566     3565       -1     
- Partials     1394     1397       +3     
```
</details>

[:umbrella: View full report in Codecov by Sentry](https://app.codecov.io/gh/xdslproject/xdsl/pull/4429?dropdown=coverage&src=pr&el=continue&utm_medium=referral&utm_source=github&utm_content=comment&utm_campaign=pr+comments&utm_term=xdslproject).   
:loudspeaker: Have feedback on the report? [Share it here](https://about.codecov.io/codecov-pr-comment-feedback/?utm_medium=referral&utm_source=github&utm_content=comment&utm_campaign=pr+comments&utm_term=xdslproject).
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</details>
author_association: NONE
user: login: alexarice
created_at: 2025-05-20T13:06:26Z
body: I think it'd help to see the full naming scheme before changing/reverting separate parts of it
author_association: COLLABORATOR
user: login: superlopuh
created_at: 2025-05-20T13:28:02Z
body: Fine I'll do it all in this PR
author_association: MEMBER
user: login: superlopuh
created_at: 2025-05-22T08:59:17Z
body: Yeah that is definitely my least favourite part of this naming scheme, I guess we can change it later if we come up with something better.
author_association: MEMBER