Repository: r-abishek/rpp
Pull request #431: RPP F32 QA : Review Comments Resolution
Author: login: HazarathKumarM
Labels: name: enhancement
description: New feature or request
Created: 2025-05-07T15:19:00Z | Merged: 2025-05-14T15:31:31Z

- Resolved review comments added by Rajy
- Modified SIMD print functions to use union which help us eliminating an extra storeu_ps instruction


Diff:
diff --git a/src/include/common/cpu/rpp_cpu_simd_load_store.hpp b/src/include/common/cpu/rpp_cpu_simd_load_store.hpp
index daa669d174..fb5e44479b 100644
--- a/src/include/common/cpu/rpp_cpu_simd_load_store.hpp
+++ b/src/include/common/cpu/rpp_cpu_simd_load_store.hpp
@@ -167,17 +167,37 @@ const __m256i avx_pxMaskR = _mm256_setr_epi8(0, 0x80, 0x80, 3, 0x80, 0x80, 6, 0x
 const __m256i avx_pxMaskG = _mm256_setr_epi8(0x80, 1, 0x80, 0x80, 4, 0x80, 0x80, 7, 0x80, 0x80, 10, 0x80, 0x80, 13, 0x80, 0x80, 16, 0x80, 0x80, 19, 0x80, 0x80, 22, 0x80, 0x80, 25, 0x80, 0x80, 28, 0x80, 0x80, 0x80);
 const __m256i avx_pxMaskB = _mm256_setr_epi8(0x80, 0x80, 2, 0x80, 0x80, 5, 0x80, 0x80, 8, 0x80, 0x80, 11, 0x80, 0x80, 14, 0x80, 0x80, 17, 0x80, 0x80, 20, 0x80, 0x80, 23, 0x80, 0x80, 26, 0x80, 0x80, 29, 0x80, 0x80);
 
+// Union for handling 128-bit SIMD data (SSE).
+union RppSIMD128
+{
+    __m128i  m128iVal;
+    __m128   m128Val;
+    char     i8[16];
+    short    i16[8];
+    int      i32[4];
+    float    f32[4];
+};
+
+// Union for handling 256-bit SIMD data (AVX).
+union RppSIMD256
+{
+    __m256i  m256iVal;
+    __m256   m256Val;
+    unsigned char u8[32];
+    short    i16[16];
+    int      i32[8];
+    float    f32[8];
+};
+
 // Print helpers
 
-inline void rpp_mm_print_epi8(__m128i vPrintArray)
+inline void rpp_mm_print_epi8(__m128i *v)
 {
-    char printArray[16];
-    _mm_storeu_si128((__m128i *)printArray, vPrintArray);
+    RppSIMD128 u;
+    u.m128iVal = v[0];
     printf("\n");
-    for (int ct = 0; ct < 16; ct++)
-    {
-        printf("%d ", printArray[ct]);
-    }
+    for (int i = 0; i < 16; ++i)
+        printf("%d ", u.i8[i]);
 }
 
 inline void rpp_storeu_si32(void *__p,
@@ -196,81 +216,68 @@ inline void rpp_storeu_si64(void *__p,
   ((struct __storeu_si64 *)__p)->__v = ((__v2di)__b)[0];
 }
 
-inline void rpp_mm_print_epi32(__m128i vPrintArray)
+inline void rpp_mm_print_epi16(__m128i *v)
 {
-    int printArray[4];
-    _mm_storeu_si128((__m128i *)printArray, vPrintArray);
+    RppSIMD128 u;
+    u.m128iVal = v[0];
     printf("\n");
-    for (int ct = 0; ct < 4; ct++)
-    {
-        printf("%d ", printArray[ct]);
-    }
+    for (int i = 0; i < 8; ++i)
+        printf("%hd ", u.i16[i]);
 }
 
-inline void rpp_mm_print_epi16(__m128i vPrintArray)
+inline void rpp_mm_print_epi32(__m128i *v)
 {
-    unsigned short int printArray[8];
-    _mm_storeu_si128((__m128i *)printArray, vPrintArray);
+    RppSIMD128 u;
+    u.m128iVal = v[0];
     printf("\n");
-    for (int ct = 0; ct < 8; ct++)
-    {
-        printf("%hu ", printArray[ct]);
-    }
+    for (int i = 0; i < 4; ++i)
+        printf("%d ", u.i32[i]);
 }
 
-inline void rpp_mm_print_ps(__m128 vPrintArray)
+inline void rpp_mm_print_ps(__m128 *v)
 {
-    float printArray[4];
-    _mm_storeu_ps(printArray, vPrintArray);
+    RppSIMD128 u;
+    u.m128Val = v[0];
     printf("\n");
-    for (int ct = 0; ct < 4; ct++)
-    {
-        printf("%0.6f ", printArray[ct]);
-    }
+    for (int i = 0; i < 4; ++i)
+        printf("%0.6f ", u.f32[i]);
 }
 
-inline void rpp_mm256_print_epi8(__m256i vPrintArray)
+
+inline void rpp_mm256_print_epi8(__m256i *v)
 {
-    unsigned char printArray[32];
-    _mm256_storeu_si256((__m256i *)printArray, vPrintArray);
+    RppSIMD256 u;
+    u.m256iVal = v[0];
     printf("\n");
-    for (int ct = 0; ct < 32; ct++)
-    {
-        printf("%d ", (unsigned char)printArray[ct]);
-    }
+    for (int i = 0; i < 32; ++i)
+        printf("%u ", u.u8[i]);
 }
 
-inline void rpp_mm256_print_epi32(__m256i vPrintArray)
+inline void rpp_mm256_print_epi16(__m256i *v)
 {
-    int printArray[8];
-    _mm256_storeu_si256((__m256i *)printArray, vPrintArray);
+    RppSIMD256 u;
+    u.m256iVal = v[0];
     printf("\n");
-    for (int ct = 0; ct < 8; ct++)
-    {
-        printf("%d ", printArray[ct]);
-    }
+    for (int i = 0; i < 16; ++i)
+        printf("%hd ", u.i16[i]);
 }
 
-inline void rpp_mm256_print_epi16(__m256i vPrintArray)
+inline void rpp_mm256_print_epi32(__m256i *v)
 {
-    unsigned short int printArray[8];
-    _mm256_storeu_si256((__m256i *)printArray, vPrintArray);
+    RppSIMD256 u;
+    u.m256iVal = v[0];
     printf("\n");
-    for (int ct = 0; ct < 16; ct++)
-    {
-        printf("%hu ", printArray[ct]);
-    }
+    for (int i = 0; i < 8; ++i)
+        printf("%d ", u.i32[i]);
 }
 
-inline void rpp_mm256_print_ps(__m256 vPrintArray)
+inline void rpp_mm256_print_ps(__m256 *v)
 {
-    float printArray[8];
-    _mm256_storeu_ps(printArray, vPrintArray);
+    RppSIMD256 u;
+    u.m256Val = v[0];
     printf("\n");
-    for (int ct = 0; ct < 8; ct++)
-    {
-        printf("%0.6f ", printArray[ct]);
-    }
+    for (int i = 0; i < 8; ++i)
+        printf("%0.6f ", u.f32[i]);
 }
 
 inline void rpp_pixel_check_0to1(__m256 *p, Rpp32s numVectors)
diff --git a/src/modules/tensor/cpu/kernel/blend.cpp b/src/modules/tensor/cpu/kernel/blend.cpp
index 865d68405c..6d0c67bdde 100644
--- a/src/modules/tensor/cpu/kernel/blend.cpp
+++ b/src/modules/tensor/cpu/kernel/blend.cpp
@@ -339,8 +339,6 @@ RppStatus blend_f32_f32_host_tensor(Rpp32f *srcPtr1,
                     p1[0] = _mm_fmadd_ps(_mm_sub_ps(p1[0], p2[0]), pMul, p2[0]);    // alpha-blending adjustment
                     p1[1] = _mm_fmadd_ps(_mm_sub_ps(p1[1], p2[1]), pMul, p2[1]);    // alpha-blending adjustment
                     p1[2] = _mm_fmadd_ps(_mm_sub_ps(p1[2], p2[2]), pMul, p2[2]);    // alpha-blending adjustment
-                    //boundary checks for f32
-                    rpp_pixel_check_0to1(p1, 3);
                     rpp_simd_store(rpp_store12_f32pln3_to_f32pln3, dstPtrTempR, dstPtrTempG, dstPtrTempB, p1);    // simd stores
 
                     srcPtr1Temp += 12;
@@ -405,8 +403,6 @@ RppStatus blend_f32_f32_host_tensor(Rpp32f *srcPtr1,
                     p1[0] = _mm_fmadd_ps(_mm_sub_ps(p1[0], p2[0]), pMul, p2[0]);    // alpha-blending adjustment
                     p1[1] = _mm_fmadd_ps(_mm_sub_ps(p1[1], p2[1]), pMul, p2[1]);    // alpha-blending adjustment
                     p1[2] = _mm_fmadd_ps(_mm_sub_ps(p1[2], p2[2]), pMul, p2[2]);    // alpha-blending adjustment
-                    //boundary checks for f32
-                    rpp_pixel_check_0to1(p1, 3);
                     rpp_simd_store(rpp_store12_f32pln3_to_f32pkd3, dstPtrTemp, p1);    // simd stores
 
                     srcPtr1TempR += 4;
@@ -469,8 +465,6 @@ RppStatus blend_f32_f32_host_tensor(Rpp32f *srcPtr1,
                         rpp_simd_load(rpp_load4_f32_to_f32, srcPtr1Temp, p1);    // simd loads
                         rpp_simd_load(rpp_load4_f32_to_f32, srcPtr2Temp, p2);    // simd loads
                         p1[0] = _mm_fmadd_ps(_mm_sub_ps(p1[0], p2[0]), pMul, p2[0]);    // alpha-blending adjustment
-                        //boundary checks for f32
-                        rpp_pixel_check_0to1(p1, 1);
                         rpp_simd_store(rpp_store4_f32_to_f32, dstPtrTemp, p1);    // simd stores
 
                         srcPtr1Temp += 4;
diff --git a/src/modules/tensor/cpu/kernel/brightness.cpp b/src/modules/tensor/cpu/kernel/brightness.cpp
index 704d024d43..723ef11525 100644
--- a/src/modules/tensor/cpu/kernel/brightness.cpp
+++ b/src/modules/tensor/cpu/kernel/brightness.cpp
@@ -396,7 +396,7 @@ RppStatus brightness_f32_f32_host_tensor(Rpp32f *srcPtr,
                     rpp_simd_load(rpp_load24_f32pkd3_to_f32pln3_avx, srcPtrTemp, p);    // simd loads
                     compute_brightness_24_host(p, pBrightnessParams);  // brightness adjustment
                     //Boundary check for f32
-                    rpp_pixel_check_0to1(p, 1);
+                    rpp_pixel_check_0to1(p, 3);
                     rpp_simd_store(rpp_store24_f32pln3_to_f32pln3_avx, dstPtrTempR, dstPtrTempG, dstPtrTempB, p);    // simd stores
 #else
                     __m128 p[3];
@@ -453,7 +453,7 @@ RppStatus brightness_f32_f32_host_tensor(Rpp32f *srcPtr,
                     rpp_simd_load(rpp_load24_f32pln3_to_f32pln3_avx, srcPtrTempR, srcPtrTempG, srcPtrTempB, p);    // simd loads
                     compute_brightness_24_host(p, pBrightnessParams);  // brightness adjustment
                     //Boundary check for f32
-                    rpp_pixel_check_0to1(p, 1);
+                    rpp_pixel_check_0to1(p, 3);
                     rpp_simd_store(rpp_store24_f32pln3_to_f32pkd3_avx, dstPtrTemp, p);    // simd stores
 #else
                     __m128 p[4];
@@ -628,7 +628,7 @@ RppStatus brightness_f16_f16_host_tensor(Rpp16f *srcPtr,
                     rpp_simd_load(rpp_load24_f32pkd3_to_f32pln3_avx, srcPtrTemp_ps, p);    // simd loads
                     compute_brightness_24_host(p, pBrightnessParams);  // brightness adjustment
                     //Boundary check for f16
-                    rpp_pixel_check_0to1(p, 1);
+                    rpp_pixel_check_0to1(p, 3);
                     rpp_simd_store(rpp_store24_f32pln3_to_f32pln3_avx, dstPtrTempR_ps, dstPtrTempG_ps, dstPtrTempB_ps, p);    // simd stores
 #else
                     __m128 p[3];
@@ -701,7 +701,7 @@ RppStatus brightness_f16_f16_host_tensor(Rpp16f *srcPtr,
                     rpp_simd_load(rpp_load24_f32pln3_to_f32pln3_avx, srcPtrTempR_ps, srcPtrTempG_ps, srcPtrTempB_ps, p);    // simd loads
                     compute_brightness_24_host(p, pBrightnessParams);  // brightness adjustment
                     //Boundary check for f16
-                    rpp_pixel_check_0to1(p, 1);
+                    rpp_pixel_check_0to1(p, 3);
                     rpp_simd_store(rpp_store24_f32pln3_to_f32pkd3_avx, dstPtrTemp_ps, p);    // simd stores
 #else
                     __m128 p[4];
diff --git a/src/modules/tensor/cpu/kernel/crop.cpp b/src/modules/tensor/cpu/kernel/crop.cpp
index 3038034364..d405cee6f5 100644
--- a/src/modules/tensor/cpu/kernel/crop.cpp
+++ b/src/modules/tensor/cpu/kernel/crop.cpp
@@ -229,8 +229,6 @@ RppStatus crop_f32_f32_host_tensor(Rpp32f *srcPtr,
                 {
                     __m128 p[4];
                     rpp_simd_load(rpp_load12_f32pkd3_to_f32pln3, srcPtrTemp, p);    // simd loads
-                    //boundary checks for f32
-                    rpp_pixel_check_0to1(p, 3);
                     rpp_simd_store(rpp_store12_f32pln3_to_f32pln3, dstPtrTempR, dstPtrTempG, dstPtrTempB, p);    // simd stores
                     srcPtrTemp += 12;
                     dstPtrTempR += 4;
@@ -279,8 +277,6 @@ RppStatus crop_f32_f32_host_tensor(Rpp32f *srcPtr,
                 {
                     __m128 p[4];
                     rpp_simd_load(rpp_load12_f32pln3_to_f32pln3, srcPtrTempR, srcPtrTempG, srcPtrTempB, p);    // simd loads
-                    //boundary checks for f32
-                    rpp_pixel_check_0to1(p, 3);
                     rpp_simd_store(rpp_store12_f32pln3_to_f32pkd3, dstPtrTemp, p);    // simd stores
                     srcPtrTempR += 4;
                     srcPtrTempG += 4;
@@ -394,8 +390,6 @@ RppStatus crop_f16_f16_host_tensor(Rpp16f *srcPtr,
                     __m128 p[4];
 
                     rpp_simd_load(rpp_load12_f32pkd3_to_f32pln3, srcPtrTemp_ps, p);    // simd loads
-                    //boundary checks for f16
-                    rpp_pixel_check_0to1(p, 3);
                     rpp_simd_store(rpp_store12_f32pln3_to_f32pln3, dstPtrTemp_ps, dstPtrTemp_ps + 4, dstPtrTemp_ps + 8, p);    // simd stores
 
                     for(int cnt = 0; cnt < 4; cnt++)
@@ -462,8 +456,6 @@ RppStatus crop_f16_f16_host_tensor(Rpp16f *srcPtr,
                     __m128 p[4];
 
                     rpp_simd_load(rpp_load12_f32pln3_to_f32pln3, srcPtrTemp_ps, srcPtrTemp_ps + 4, srcPtrTemp_ps + 8, p);    // simd loads
-                    //boundary checks for f16
-                    rpp_pixel_check_0to1(p, 3);
                     rpp_simd_store(rpp_store12_f32pln3_to_f32pkd3, dstPtrTemp_ps, p);    // simd stores
 
                     for(int cnt = 0; cnt < 12; cnt++)
diff --git a/src/modules/tensor/cpu/kernel/crop_and_patch.cpp b/src/modules/tensor/cpu/kernel/crop_and_patch.cpp
index bda568087f..e3cceca0e8 100644
--- a/src/modules/tensor/cpu/kernel/crop_and_patch.cpp
+++ b/src/modules/tensor/cpu/kernel/crop_and_patch.cpp
@@ -446,8 +446,6 @@ RppStatus crop_and_patch_f32_f32_host_tensor(Rpp32f *srcPtr1,
                     {
                         __m128 p[4];
                         rpp_simd_load(rpp_load12_f32pkd3_to_f32pln3, srcPtr2Temp, p);    // simd loads
-                        //Boundary checks for f32
-                        rpp_pixel_check_0to1(p, 3);
                         rpp_simd_store(rpp_store12_f32pln3_to_f32pln3, dstPtrTempR, dstPtrTempG, dstPtrTempB, p);    // simd stores
                         srcPtr2Temp += vectorIncrement;
                         dstPtrTempR += vectorIncrementPerChannel;
@@ -470,8 +468,6 @@ RppStatus crop_and_patch_f32_f32_host_tensor(Rpp32f *srcPtr1,
                     {
                         __m128 p[4];
                         rpp_simd_load(rpp_load12_f32pkd3_to_f32pln3, srcPtr1Temp, p);    // simd loads
-                        //Boundary checks for f32
-                        rpp_pixel_check_0to1(p, 3);
                         rpp_simd_store(rpp_store12_f32pln3_to_f32pln3, dstPtrTempR, dstPtrTempG, dstPtrTempB, p);    // simd stores
                         srcPtr1Temp += vectorIncrement;
                         dstPtrTempR += vectorIncrementPerChannel;
@@ -494,8 +490,6 @@ RppStatus crop_and_patch_f32_f32_host_tensor(Rpp32f *srcPtr1,
                     {
                         __m128 p[4];
                         rpp_simd_load(rpp_load12_f32pkd3_to_f32pln3, srcPtr2Temp, p);    // simd loads
-                        //Boundary checks for f32
-                        rpp_pixel_check_0to1(p, 3);
                         rpp_simd_store(rpp_store12_f32pln3_to_f32pln3, dstPtrTempR, dstPtrTempG, dstPtrTempB, p);    // simd stores
                         srcPtr2Temp += vectorIncrement;
                         dstPtrTempR += vectorIncrementPerChannel;
@@ -519,8 +513,6 @@ RppStatus crop_and_patch_f32_f32_host_tensor(Rpp32f *srcPtr1,
                     {
                         __m128 p[4];
                         rpp_simd_load(rpp_load12_f32pkd3_to_f32pln3, srcPtr2Temp, p);    // simd loads
-                        //Boundary checks for f32
-                        rpp_pixel_check_0to1(p, 3);
                         rpp_simd_store(rpp_store12_f32pln3_to_f32pln3, dstPtrTempR, dstPtrTempG, dstPtrTempB, p);    // simd stores
                         srcPtr2Temp += vectorIncrement;
                         dstPtrTempR += vectorIncrementPerChannel;
@@ -572,8 +564,6 @@ RppStatus crop_and_patch_f32_f32_host_tensor(Rpp32f *srcPtr1,
                     {
                         __m128 p[4];
                         rpp_simd_load(rpp_load12_f32pln3_to_f32pln3, srcPtr2TempR, srcPtr2TempG, srcPtr2TempB, p);    // simd loads
-                        //Boundary checks for f32
-                        rpp_pixel_check_0to1(p, 3);
                         rpp_simd_store(rpp_store12_f32pln3_to_f32pkd3, dstPtrTemp, p);    // simd stores
                         srcPtr2TempR += vectorIncrementPerChannel;
                         srcPtr2TempG += vectorIncrementPerChannel;
@@ -598,8 +588,6 @@ RppStatus crop_and_patch_f32_f32_host_tensor(Rpp32f *srcPtr1,
                     {
                         __m128 p[4];
                         rpp_simd_load(rpp_load12_f32pln3_to_f32pln3, srcPtr1TempR, srcPtr1TempG, srcPtr1TempB, p);    // simd loads
-                        //Boundary checks for f32
-                        rpp_pixel_check_0to1(p, 3);
                         rpp_simd_store(rpp_store12_f32pln3_to_f32pkd3, dstPtrTemp, p);    // simd stores
                         srcPtr1TempR += vectorIncrementPerChannel;
                         srcPtr1TempG += vectorIncrementPerChannel;
@@ -624,8 +612,6 @@ RppStatus crop_and_patch_f32_f32_host_tensor(Rpp32f *srcPtr1,
                     {
                         __m128 p[4];
                         rpp_simd_load(rpp_load12_f32pln3_to_f32pln3, srcPtr2TempR, srcPtr2TempG, srcPtr2TempB, p);    // simd loads
-                        //Boundary checks for f32
-                        rpp_pixel_check_0to1(p, 3);
                         rpp_simd_store(rpp_store12_f32pln3_to_f32pkd3, dstPtrTemp, p);    // simd stores
                         srcPtr2TempR += vectorIncrementPerChannel;
                         srcPtr2TempG += vectorIncrementPerChannel;
@@ -651,8 +637,6 @@ RppStatus crop_and_patch_f32_f32_host_tensor(Rpp32f *srcPtr1,
                     {
                         __m128 p[4];
                         rpp_simd_load(rpp_load12_f32pln3_to_f32pln3, srcPtr2TempR, srcPtr2TempG, srcPtr2TempB, p);    // simd loads
-                        //Boundary checks for f32
-                        rpp_pixel_check_0to1(p, 3);
                         rpp_simd_store(rpp_store12_f32pln3_to_f32pkd3, dstPtrTemp, p);    // simd stores
                         srcPtr2TempR += vectorIncrementPerChannel;
                         srcPtr2TempG += vectorIncrementPerChannel;
@@ -827,8 +811,6 @@ RppStatus crop_and_patch_f16_f16_host_tensor(Rpp16f *srcPtr1,
 
                         __m128 p[4];
                         rpp_simd_load(rpp_load12_f32pkd3_to_f32pln3, srcPtrTemp_ps, p);    // simd loads
-                        //Boundary checks for f16
-                        rpp_pixel_check_0to1(p, 3);
                         rpp_simd_store(rpp_store12_f32pln3_to_f32pln3, dstPtrTemp_ps, dstPtrTemp_ps + 4, dstPtrTemp_ps + 8, p);    // simd stores
                         for(int cnt = 0; cnt < 4; cnt++)
                         {
@@ -860,8 +842,6 @@ RppStatus crop_and_patch_f16_f16_host_tensor(Rpp16f *srcPtr1,
 
                         __m128 p[4];
                         rpp_simd_load(rpp_load12_f32pkd3_to_f32pln3, srcPtrTemp_ps, p);    // simd loads
-                        //Boundary checks for f16
-                        rpp_pixel_check_0to1(p, 3);
                         rpp_simd_store(rpp_store12_f32pln3_to_f32pln3, dstPtrTemp_ps, dstPtrTemp_ps + 4, dstPtrTemp_ps + 8, p);    // simd stores
                         for(int cnt = 0; cnt < 4; cnt++)
                         {
@@ -894,8 +874,6 @@ RppStatus crop_and_patch_f16_f16_host_tensor(Rpp16f *srcPtr1,
 
                         __m128 p[4];
                         rpp_simd_load(rpp_load12_f32pkd3_to_f32pln3, srcPtrTemp_ps, p);    // simd loads
-                        //Boundary checks for f16
-                        rpp_pixel_check_0to1(p, 3);
                         rpp_simd_store(rpp_store12_f32pln3_to_f32pln3, dstPtrTemp_ps, dstPtrTemp_ps + 4, dstPtrTemp_ps + 8, p);    // simd stores
                         for(int cnt = 0; cnt < 4; cnt++)
                         {
@@ -929,8 +907,6 @@ RppStatus crop_and_patch_f16_f16_host_tensor(Rpp16f *srcPtr1,
 
                         __m128 p[4];
                         rpp_simd_load(rpp_load12_f32pkd3_to_f32pln3, srcPtrTemp_ps, p);    // simd loads
-                        //Boundary checks for f16
-                        rpp_pixel_check_0to1(p, 3);
                         rpp_simd_store(rpp_store12_f32pln3_to_f32pln3, dstPtrTemp_ps, dstPtrTemp_ps + 4, dstPtrTemp_ps + 8, p);    // simd stores
                         for(int cnt = 0; cnt < 4; cnt++)
                         {
@@ -997,8 +973,6 @@ RppStatus crop_and_patch_f16_f16_host_tensor(Rpp16f *srcPtr1,
                         }
                         __m128 p[4];
                         rpp_simd_load(rpp_load12_f32pln3_to_f32pln3, srcPtrTemp_ps, srcPtrTemp_ps + 4, srcPtrTemp_ps + 4, p);    // simd loads
-                        //Boundary checks for f16
-                        rpp_pixel_check_0to1(p, 3);
                         rpp_simd_store(rpp_store12_f32pln3_to_f32pkd3, dstPtrTemp_ps, p);    // simd stores
                         for(int cnt = 0; cnt < 12; cnt++)
                             *(dstPtrTemp + cnt) = (Rpp16f) *(dstPtrTemp_ps + cnt);
@@ -1032,8 +1006,6 @@ RppStatus crop_and_patch_f16_f16_host_tensor(Rpp16f *srcPtr1,
                         }
                         __m128 p[4];
                         rpp_simd_load(rpp_load12_f32pln3_to_f32pln3, srcPtrTemp_ps, srcPtrTemp_ps + 4, srcPtrTemp_ps + 8, p);    // simd loads
-                        //Boundary checks for f16
-                        rpp_pixel_check_0to1(p, 3);
                         rpp_simd_store(rpp_store12_f32pln3_to_f32pkd3, dstPtrTemp_ps, p);    // simd stores
                         for(int cnt = 0; cnt < 12; cnt++)
                             *(dstPtrTemp + cnt) = (Rpp16f) *(dstPtrTemp_ps + cnt);
@@ -1068,8 +1040,6 @@ RppStatus crop_and_patch_f16_f16_host_tensor(Rpp16f *srcPtr1,
                         }
                         __m128 p[4];
                         rpp_simd_load(rpp_load12_f32pln3_to_f32pln3, srcPtrTemp_ps, srcPtrTemp_ps + 4, srcPtrTemp_ps + 8, p);    // simd loads
-                        //Boundary checks for f16
-                        rpp_pixel_check_0to1(p, 3);
                         rpp_simd_store(rpp_store12_f32pln3_to_f32pkd3, dstPtrTemp_ps, p);    // simd stores
                         for(int cnt = 0; cnt < 12; cnt++)
                             *(dstPtrTemp + cnt) = (Rpp16f) *(dstPtrTemp_ps + cnt);
@@ -1105,8 +1075,6 @@ RppStatus crop_and_patch_f16_f16_host_tensor(Rpp16f *srcPtr1,
                         }
                         __m128 p[4];
                         rpp_simd_load(rpp_load12_f32pln3_to_f32pln3, srcPtrTemp_ps, srcPtrTemp_ps + 4, srcPtrTemp_ps + 8, p);    // simd loads
-                        //Boundary checks for f16
-                        rpp_pixel_check_0to1(p, 3);
                         rpp_simd_store(rpp_store12_f32pln3_to_f32pkd3, dstPtrTemp_ps, p);    // simd stores
                         for(int cnt = 0; cnt < 12; cnt++)
                             *(dstPtrTemp + cnt) = (Rpp16f) *(dstPtrTemp_ps + cnt);
diff --git a/src/modules/tensor/cpu/kernel/threshold.cpp b/src/modules/tensor/cpu/kernel/threshold.cpp
index 57828cd585..806ea2b39a 100644
--- a/src/modules/tensor/cpu/kernel/threshold.cpp
+++ b/src/modules/tensor/cpu/kernel/threshold.cpp
@@ -432,8 +432,6 @@ RppStatus threshold_f32_f32_host_tensor(Rpp32f *srcPtr,
                     __m256 p[3];
                     rpp_simd_load(rpp_load24_f32pkd3_to_f32pln3_avx, srcPtrTemp, p);                               // simd loads
                     compute_threshold_24_host(p, pThresholdParams); 	                                           // threshold adjustment
-                    //Boundary check for f32
-                    rpp_pixel_check_0to1(p, 1);
                     rpp_simd_store(rpp_store24_f32pln3_to_f32pln3_avx, dstPtrTempR, dstPtrTempG, dstPtrTempB, p);  // simd stores
                     srcPtrTemp += 24;
                     dstPtrTempR += 8;
@@ -487,8 +485,6 @@ RppStatus threshold_f32_f32_host_tensor(Rpp32f *srcPtr,
                     __m256 p[3];
                     rpp_simd_load(rpp_load24_f32pln3_to_f32pln3_avx, srcPtrTempR, srcPtrTempG, srcPtrTempB, p);  // simd loads
                     compute_threshold_24_host(p, pThresholdParams); 	                                         // threshold adjustment
-                    //Boundary check for f32
-                    rpp_pixel_check_0to1(p, 1);
                     rpp_simd_store(rpp_store24_f32pln3_to_f32pkd3_avx, dstPtrTemp, p);                           // simd stores
                     srcPtrTempR += 8;
                     srcPtrTempG += 8;
@@ -537,8 +533,6 @@ RppStatus threshold_f32_f32_host_tensor(Rpp32f *srcPtr,
                     __m256 p[3];
                     rpp_simd_load(rpp_load24_f32pkd3_to_f32pln3_avx, srcPtrTemp, p);         // simd loads
                     compute_threshold_24_host(p, pThresholdParams); 	                     // threshold adjustment
-                    //Boundary check for f32
-                    rpp_pixel_check_0to1(p, 1);
                     rpp_simd_store(rpp_store24_f32pln3_to_f32pkd3_avx, dstPtrTemp, p);       // simd stores
                     srcPtrTemp += vectorIncrement;
                     dstPtrTemp += vectorIncrement;
@@ -594,8 +588,6 @@ RppStatus threshold_f32_f32_host_tensor(Rpp32f *srcPtr,
                     __m256 p[3];
                     rpp_simd_load(rpp_load24_f32pln3_to_f32pln3_avx, srcPtrTempR, srcPtrTempG, srcPtrTempB, p);   // simd loads
                     compute_threshold_24_host(p, pThresholdParams);                                               // threshold adjustment
-                    //Boundary check for f32
-                    rpp_pixel_check_0to1(p, 1);
                     rpp_simd_store(rpp_store24_f32pln3_to_f32pln3_avx, dstPtrTempR, dstPtrTempG, dstPtrTempB, p); // simd stores                                  // simd stores
                     srcPtrTempR += vectorIncrementPerChannel;
                     srcPtrTempG += vectorIncrementPerChannel;
@@ -647,8 +639,6 @@ RppStatus threshold_f32_f32_host_tensor(Rpp32f *srcPtr,
                     __m256 p[1];
                     rpp_simd_load(rpp_load8_f32_to_f32_avx, srcPtrTemp, p);      // simd loads
                     compute_threshold_8_host(p, pThresholdParams);              // threshold adjustment
-                    //Boundary check for f32
-                    rpp_pixel_check_0to1(p, 1);
                     rpp_simd_store(rpp_store8_f32_to_f32_avx, dstPtrTemp, p);    // simd stores
                     srcPtrTemp += vectorIncrementPerChannel;
                     dstPtrTemp += vectorIncrementPerChannel;
@@ -1040,8 +1030,6 @@ RppStatus threshold_f16_f16_host_tensor(Rpp16f *srcPtr,
                     __m256 p[3];
                     rpp_simd_load(rpp_load24_f16pkd3_to_f32pln3_avx, srcPtrTemp, p);                               // simd loads
                     compute_threshold_24_host(p, pThresholdParams); 	                                           // threshold adjustment
-                    //Boundary check for f16
-                    rpp_pixel_check_0to1(p, 1);
                     rpp_simd_store(rpp_store24_f32pln3_to_f16pln3_avx, dstPtrTempR, dstPtrTempG, dstPtrTempB, p);  // simd stores
                     srcPtrTemp += 24;
                     dstPtrTempR += 8;
@@ -1095,8 +1083,6 @@ RppStatus threshold_f16_f16_host_tensor(Rpp16f *srcPtr,
                     __m256 p[3];
                     rpp_simd_load(rpp_load24_f16pln3_to_f32pln3_avx, srcPtrTempR, srcPtrTempG, srcPtrTempB, p);  // simd loads
                     compute_threshold_24_host(p, pThresholdParams); 	                                         // threshold adjustment
-                    //Boundary check for f16
-                    rpp_pixel_check_0to1(p, 1);
                     rpp_simd_store(rpp_store24_f32pln3_to_f16pkd3_avx, dstPtrTemp, p);                           // simd stores
                     srcPtrTempR += 8;
                     srcPtrTempG += 8;
@@ -1145,8 +1131,6 @@ RppStatus threshold_f16_f16_host_tensor(Rpp16f *srcPtr,
                     __m256 p[3];
                     rpp_simd_load(rpp_load24_f16pkd3_to_f32pln3_avx, srcPtrTemp, p);         // simd loads
                     compute_threshold_24_host(p, pThresholdParams); 	                     // threshold adjustment
-                    //Boundary check for f16
-                    rpp_pixel_check_0to1(p, 1);
                     rpp_simd_store(rpp_store24_f32pln3_to_f16pkd3_avx, dstPtrTemp, p);       // simd stores
                     srcPtrTemp += vectorIncrement;
                     dstPtrTemp += vectorIncrement;
@@ -1202,8 +1186,6 @@ RppStatus threshold_f16_f16_host_tensor(Rpp16f *srcPtr,
                     __m256 p[3];
                     rpp_simd_load(rpp_load24_f16pln3_to_f32pln3_avx, srcPtrTempR, srcPtrTempG, srcPtrTempB, p);   // simd loads
                     compute_threshold_24_host(p, pThresholdParams);                                               // threshold adjustment
-                    //Boundary check for f16
-                    rpp_pixel_check_0to1(p, 1);
                     rpp_simd_store(rpp_store24_f32pln3_to_f16pln3_avx, dstPtrTempR, dstPtrTempG, dstPtrTempB, p); // simd stores                                  // simd stores
                     srcPtrTempR += vectorIncrementPerChannel;
                     srcPtrTempG += vectorIncrementPerChannel;
@@ -1255,7 +1237,6 @@ RppStatus threshold_f16_f16_host_tensor(Rpp16f *srcPtr,
                     __m256 p[1];
                     rpp_simd_load(rpp_load8_f16_to_f32_avx, srcPtrTemp, p);      // simd loads
                     compute_threshold_8_host(p, pThresholdParams);              // threshold adjustment
-                    rpp_pixel_check_0to1(p, 1);
                     rpp_simd_store(rpp_store8_f32_to_f16_avx, dstPtrTemp, p);    // simd stores
                     srcPtrTemp += vectorIncrementPerChannel;
                     dstPtrTemp += vectorIncrementPerChannel;


Reviews:
user: login: copilot-pull-request-reviewer[bot]
body: ## Pull Request Overview

This PR resolves review comments by modifying SIMD print functions to use union-based conversions, eliminating an extra storeu_ps instruction.  
- Replaced temporary arrays with unions for SIMD print functions  
- Consolidated and standardized the conversions across various data types


<details>
<summary>Comments suppressed due to low confidence (1)</summary>

**src/include/common/cpu/rpp_cpu_simd_load_store.hpp:295**
* [nitpick] Consider using the loop variable name 'ct' instead of 'i' for consistency with the other print functions.
```
for (int i = 0; i < 8; ++i)
```
</details>


state: COMMENTED
author_association: NONE
submitted_at: 2025-05-08T01:38:22Z
user: login: r-abishek
body: @HazarathKumarM Pls address comments
state: CHANGES_REQUESTED
author_association: OWNER
submitted_at: 2025-05-08T04:00:43Z
user: login: r-abishek
state: COMMENTED
author_association: OWNER
submitted_at: 2025-05-14T04:47:00Z
user: login: r-abishek
state: COMMENTED
author_association: OWNER
submitted_at: 2025-05-14T04:47:17Z
user: login: r-abishek
state: COMMENTED
author_association: OWNER
submitted_at: 2025-05-14T04:50:55Z
user: login: r-abishek
body: @HazarathKumarM Please address comments on following similar rpp standards
state: CHANGES_REQUESTED
author_association: OWNER
submitted_at: 2025-05-14T04:52:18Z
user: login: copilot-pull-request-reviewer[bot]
body: ## Pull Request Overview

This PR resolves review comments from Rajy and refines SIMD print functions by introducing union-based types, while removing explicit boundary check calls in several tensor processing kernels.  
- Removed calls to rpp_pixel_check_0to1 in threshold, crop, crop_and_patch, and blend kernels  
- Revised SIMD print helper functions to use union-based data for improved performance and clarity

### Reviewed Changes

Copilot reviewed 5 out of 5 changed files in this pull request and generated 1 comment.

<details>
<summary>Show a summary per file</summary>

| File                                                         | Description                                                 |
| ------------------------------------------------------------ | ----------------------------------------------------------- |
| src/modules/tensor/cpu/kernel/threshold.cpp                  | Removed boundary check calls; relies on compute_threshold logic |
| src/modules/tensor/cpu/kernel/crop_and_patch.cpp               | Removed boundary check calls in pixel processing            |
| src/modules/tensor/cpu/kernel/crop.cpp                         | Removed boundary check calls in pixel processing            |
| src/modules/tensor/cpu/kernel/blend.cpp                        | Removed boundary check calls during alpha-blending           |
| src/include/common/cpu/rpp_cpu_simd_load_store.hpp             | Introduced union types and refactored SIMD print helpers      |
</details>



<details>
<summary>Comments suppressed due to low confidence (4)</summary>

**src/modules/tensor/cpu/kernel/threshold.cpp:434**
* Removal of boundary checks in threshold functions should be validated; ensure that compute_threshold_* functions or another mechanism guarantees valid pixel ranges. Consider adding a clarifying comment about how boundary conditions are now enforced.
```
rpp_pixel_check_0to1(p, 1);
```
**src/modules/tensor/cpu/kernel/crop_and_patch.cpp:448**
* With the boundary check removed, verify that pixel values remain within valid ranges as expected downstream. A brief comment explaining this design decision might improve code clarity.
```
rpp_pixel_check_0to1(p, 3);
```
**src/modules/tensor/cpu/kernel/crop.cpp:231**
* Ensure that the removal of this boundary check does not lead to invalid pixel values in subsequent processing; document the alternative validation mechanism if one exists.
```
rpp_pixel_check_0to1(p, 3);
```
**src/modules/tensor/cpu/kernel/blend.cpp:341**
* Verify that eliminating the boundary check in the blend function is safe and that the blending operation correctly constrains the pixel values. Consider documenting this behavior for future maintainers.
```
rpp_pixel_check_0to1(p1, 3);
```
</details>


state: COMMENTED
author_association: NONE
submitted_at: 2025-05-14T04:54:18Z
user: login: HazarathKumarM
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-05-14T15:28:04Z
user: login: HazarathKumarM
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-05-14T15:28:10Z
user: login: HazarathKumarM
state: COMMENTED
author_association: COLLABORATOR
submitted_at: 2025-05-14T15:28:26Z
user: login: r-abishek
state: APPROVED
author_association: OWNER
submitted_at: 2025-05-14T15:30:24Z

Review comments:
diff_hunk: @@ -171,12 +171,17 @@ const __m256i avx_pxMaskB = _mm256_setr_epi8(0x80, 0x80, 2, 0x80, 0x80, 5, 0x80,
 
 inline void rpp_mm_print_epi8(__m128i vPrintArray)
 {
-    char printArray[16];
-    _mm_storeu_si128((__m128i *)printArray, vPrintArray);
+    union {
+        __m128i vec;
+        char arr[16];
+    } u;
path: src/include/common/cpu/rpp_cpu_simd_load_store.hpp
user: login: r-abishek
body: Please don't do the union initialization inside every function. Take it out globally.
Next, we should ideally pass pointer to __m128i (call by reference). So receive it in __m128i* vPrintArrayPtr.
A global u is already defined, so we just use that here next
```
u.vec = *(vPrintArrayPtr);
```
This way, two copies are avoided:
1. The call by value copy when you call `rpp_mm_print_epi8(__m128i vPrintArray)`
2. The copy at `u.vec = vPrintArray;`

Pls check u.arr should also be accessible after that.
created_at: 2025-05-08T02:44:52Z
author_association: OWNER
diff_hunk: @@ -167,17 +167,34 @@ const __m256i avx_pxMaskR = _mm256_setr_epi8(0, 0x80, 0x80, 3, 0x80, 0x80, 6, 0x
 const __m256i avx_pxMaskG = _mm256_setr_epi8(0x80, 1, 0x80, 0x80, 4, 0x80, 0x80, 7, 0x80, 0x80, 10, 0x80, 0x80, 13, 0x80, 0x80, 16, 0x80, 0x80, 19, 0x80, 0x80, 22, 0x80, 0x80, 25, 0x80, 0x80, 28, 0x80, 0x80, 0x80);
 const __m256i avx_pxMaskB = _mm256_setr_epi8(0x80, 0x80, 2, 0x80, 0x80, 5, 0x80, 0x80, 8, 0x80, 0x80, 11, 0x80, 0x80, 14, 0x80, 0x80, 17, 0x80, 0x80, 20, 0x80, 0x80, 23, 0x80, 0x80, 26, 0x80, 0x80, 29, 0x80, 0x80);
 
+// Union for handling 128-bit SIMD data (SSE).
+union RppSIMD128 {
+    __m128i  m128i_val;
path: src/include/common/cpu/rpp_cpu_simd_load_store.hpp
user: login: r-abishek
body: Open braces in next line as per RPP standard everywhere
created_at: 2025-05-14T04:47:00Z
author_association: OWNER
diff_hunk: @@ -167,17 +167,34 @@ const __m256i avx_pxMaskR = _mm256_setr_epi8(0, 0x80, 0x80, 3, 0x80, 0x80, 6, 0x
 const __m256i avx_pxMaskG = _mm256_setr_epi8(0x80, 1, 0x80, 0x80, 4, 0x80, 0x80, 7, 0x80, 0x80, 10, 0x80, 0x80, 13, 0x80, 0x80, 16, 0x80, 0x80, 19, 0x80, 0x80, 22, 0x80, 0x80, 25, 0x80, 0x80, 28, 0x80, 0x80, 0x80);
 const __m256i avx_pxMaskB = _mm256_setr_epi8(0x80, 0x80, 2, 0x80, 0x80, 5, 0x80, 0x80, 8, 0x80, 0x80, 11, 0x80, 0x80, 14, 0x80, 0x80, 17, 0x80, 0x80, 20, 0x80, 0x80, 23, 0x80, 0x80, 26, 0x80, 0x80, 29, 0x80, 0x80);
 
+// Union for handling 128-bit SIMD data (SSE).
+union RppSIMD128 {
+    __m128i  m128i_val;
+    __m128   m128_val;
+    char     i8[16];
+    short    i16[8];
+    int      i32[4];
+    float    f32[4];
+};
+
+// Union for handling 256-bit SIMD data (AVX).
+union RppSIMD256 {
+    __m256i  m256i_val;
+    __m256   m256_val;
+    unsigned char u8[32];
+    short    i16[16];
+    int      i32[8];
+    float    f32[8];
+};
+
 // Print helpers
 
-inline void rpp_mm_print_epi8(__m128i vPrintArray)
-{
-    char printArray[16];
-    _mm_storeu_si128((__m128i *)printArray, vPrintArray);
+inline void rpp_mm_print_epi8(__m128i *v) {
+    RppSIMD128 u;
path: src/include/common/cpu/rpp_cpu_simd_load_store.hpp
user: login: r-abishek
body: Same comment. Open braces in next line as per RPP standard everywhere
created_at: 2025-05-14T04:47:17Z
author_association: OWNER
diff_hunk: @@ -167,17 +167,34 @@ const __m256i avx_pxMaskR = _mm256_setr_epi8(0, 0x80, 0x80, 3, 0x80, 0x80, 6, 0x
 const __m256i avx_pxMaskG = _mm256_setr_epi8(0x80, 1, 0x80, 0x80, 4, 0x80, 0x80, 7, 0x80, 0x80, 10, 0x80, 0x80, 13, 0x80, 0x80, 16, 0x80, 0x80, 19, 0x80, 0x80, 22, 0x80, 0x80, 25, 0x80, 0x80, 28, 0x80, 0x80, 0x80);
 const __m256i avx_pxMaskB = _mm256_setr_epi8(0x80, 0x80, 2, 0x80, 0x80, 5, 0x80, 0x80, 8, 0x80, 0x80, 11, 0x80, 0x80, 14, 0x80, 0x80, 17, 0x80, 0x80, 20, 0x80, 0x80, 23, 0x80, 0x80, 26, 0x80, 0x80, 29, 0x80, 0x80);
 
+// Union for handling 128-bit SIMD data (SSE).
+union RppSIMD128 {
+    __m128i  m128i_val;
+    __m128   m128_val;
path: src/include/common/cpu/rpp_cpu_simd_load_store.hpp
user: login: r-abishek
body: Please dont use snake_case here too, call it m128iVal and m128Val
created_at: 2025-05-14T04:50:55Z
author_association: OWNER
diff_hunk: @@ -167,17 +167,34 @@ const __m256i avx_pxMaskR = _mm256_setr_epi8(0, 0x80, 0x80, 3, 0x80, 0x80, 6, 0x
 const __m256i avx_pxMaskG = _mm256_setr_epi8(0x80, 1, 0x80, 0x80, 4, 0x80, 0x80, 7, 0x80, 0x80, 10, 0x80, 0x80, 13, 0x80, 0x80, 16, 0x80, 0x80, 19, 0x80, 0x80, 22, 0x80, 0x80, 25, 0x80, 0x80, 28, 0x80, 0x80, 0x80);
 const __m256i avx_pxMaskB = _mm256_setr_epi8(0x80, 0x80, 2, 0x80, 0x80, 5, 0x80, 0x80, 8, 0x80, 0x80, 11, 0x80, 0x80, 14, 0x80, 0x80, 17, 0x80, 0x80, 20, 0x80, 0x80, 23, 0x80, 0x80, 26, 0x80, 0x80, 29, 0x80, 0x80);
 
+// Union for handling 128-bit SIMD data (SSE).
path: src/include/common/cpu/rpp_cpu_simd_load_store.hpp
user: login: Copilot
body: [nitpick] It may be helpful to add a brief explanation on why the union-based SIMD structures were introduced and how they contribute to eliminating extra store instructions, to aid future maintenance.
created_at: 2025-05-14T04:54:18Z
author_association: NONE
diff_hunk: @@ -167,17 +167,34 @@ const __m256i avx_pxMaskR = _mm256_setr_epi8(0, 0x80, 0x80, 3, 0x80, 0x80, 6, 0x
 const __m256i avx_pxMaskG = _mm256_setr_epi8(0x80, 1, 0x80, 0x80, 4, 0x80, 0x80, 7, 0x80, 0x80, 10, 0x80, 0x80, 13, 0x80, 0x80, 16, 0x80, 0x80, 19, 0x80, 0x80, 22, 0x80, 0x80, 25, 0x80, 0x80, 28, 0x80, 0x80, 0x80);
 const __m256i avx_pxMaskB = _mm256_setr_epi8(0x80, 0x80, 2, 0x80, 0x80, 5, 0x80, 0x80, 8, 0x80, 0x80, 11, 0x80, 0x80, 14, 0x80, 0x80, 17, 0x80, 0x80, 20, 0x80, 0x80, 23, 0x80, 0x80, 26, 0x80, 0x80, 29, 0x80, 0x80);
 
+// Union for handling 128-bit SIMD data (SSE).
+union RppSIMD128 {
+    __m128i  m128i_val;
path: src/include/common/cpu/rpp_cpu_simd_load_store.hpp
user: login: HazarathKumarM
body: Done

created_at: 2025-05-14T15:28:04Z
author_association: COLLABORATOR
diff_hunk: @@ -167,17 +167,34 @@ const __m256i avx_pxMaskR = _mm256_setr_epi8(0, 0x80, 0x80, 3, 0x80, 0x80, 6, 0x
 const __m256i avx_pxMaskG = _mm256_setr_epi8(0x80, 1, 0x80, 0x80, 4, 0x80, 0x80, 7, 0x80, 0x80, 10, 0x80, 0x80, 13, 0x80, 0x80, 16, 0x80, 0x80, 19, 0x80, 0x80, 22, 0x80, 0x80, 25, 0x80, 0x80, 28, 0x80, 0x80, 0x80);
 const __m256i avx_pxMaskB = _mm256_setr_epi8(0x80, 0x80, 2, 0x80, 0x80, 5, 0x80, 0x80, 8, 0x80, 0x80, 11, 0x80, 0x80, 14, 0x80, 0x80, 17, 0x80, 0x80, 20, 0x80, 0x80, 23, 0x80, 0x80, 26, 0x80, 0x80, 29, 0x80, 0x80);
 
+// Union for handling 128-bit SIMD data (SSE).
+union RppSIMD128 {
+    __m128i  m128i_val;
+    __m128   m128_val;
+    char     i8[16];
+    short    i16[8];
+    int      i32[4];
+    float    f32[4];
+};
+
+// Union for handling 256-bit SIMD data (AVX).
+union RppSIMD256 {
+    __m256i  m256i_val;
+    __m256   m256_val;
+    unsigned char u8[32];
+    short    i16[16];
+    int      i32[8];
+    float    f32[8];
+};
+
 // Print helpers
 
-inline void rpp_mm_print_epi8(__m128i vPrintArray)
-{
-    char printArray[16];
-    _mm_storeu_si128((__m128i *)printArray, vPrintArray);
+inline void rpp_mm_print_epi8(__m128i *v) {
+    RppSIMD128 u;
path: src/include/common/cpu/rpp_cpu_simd_load_store.hpp
user: login: HazarathKumarM
body: Done
created_at: 2025-05-14T15:28:10Z
author_association: COLLABORATOR
diff_hunk: @@ -167,17 +167,34 @@ const __m256i avx_pxMaskR = _mm256_setr_epi8(0, 0x80, 0x80, 3, 0x80, 0x80, 6, 0x
 const __m256i avx_pxMaskG = _mm256_setr_epi8(0x80, 1, 0x80, 0x80, 4, 0x80, 0x80, 7, 0x80, 0x80, 10, 0x80, 0x80, 13, 0x80, 0x80, 16, 0x80, 0x80, 19, 0x80, 0x80, 22, 0x80, 0x80, 25, 0x80, 0x80, 28, 0x80, 0x80, 0x80);
 const __m256i avx_pxMaskB = _mm256_setr_epi8(0x80, 0x80, 2, 0x80, 0x80, 5, 0x80, 0x80, 8, 0x80, 0x80, 11, 0x80, 0x80, 14, 0x80, 0x80, 17, 0x80, 0x80, 20, 0x80, 0x80, 23, 0x80, 0x80, 26, 0x80, 0x80, 29, 0x80, 0x80);
 
+// Union for handling 128-bit SIMD data (SSE).
+union RppSIMD128 {
+    __m128i  m128i_val;
+    __m128   m128_val;
path: src/include/common/cpu/rpp_cpu_simd_load_store.hpp
user: login: HazarathKumarM
body: Done
created_at: 2025-05-14T15:28:26Z
author_association: COLLABORATOR

PR comments:
user: login: HazarathKumarM
created_at: 2025-05-09T18:37:15Z
body: - pixel check changes are pending on this PR
author_association: COLLABORATOR
user: login: HazarathKumarM
created_at: 2025-05-14T03:57:34Z
body: <img width="365" alt="image" src="https://github.com/user-attachments/assets/0ae2dbca-f058-4b91-9a7a-cc25a21cc776" />

author_association: COLLABORATOR
user: login: HazarathKumarM
created_at: 2025-05-14T15:29:04Z
body: > @HazarathKumarM Please address comments on following similar rpp standards

all review comments are addressed now

author_association: COLLABORATOR