Repository: openhwgroup/cve2
Pull request #284: add X-IF 1.0
Author: login: davideschiavone
Created: 2025-02-27T13:37:47Z | Merged: 2025-04-10T12:06:34Z

- [x] @FrancescoDeMalde-synthara checks XInterface=1

- [x] @cairo-caplan checks SEC

- [x] @davideschiavone checks Verilator


Diff:
diff --git a/rtl/cve2_core.sv b/rtl/cve2_core.sv
index 440cc36818..c62eb44806 100644
--- a/rtl/cve2_core.sv
+++ b/rtl/cve2_core.sv
@@ -22,7 +22,8 @@ module cve2_core import cve2_pkg::*; #(
   parameter rv32m_e      RV32M             = RV32MFast,
   parameter rv32b_e      RV32B             = RV32BNone,
   parameter bit          DbgTriggerEn      = 1'b0,
-  parameter int unsigned DbgHwBreakNum     = 1
+  parameter int unsigned DbgHwBreakNum     = 1,
+  parameter bit          XInterface        = 1'b0
 ) (
   // Clock and Reset
   input  logic                         clk_i,
@@ -52,6 +53,25 @@ module cve2_core import cve2_pkg::*; #(
   input  logic [31:0]                  data_rdata_i,
   input  logic                         data_err_i,
 
+  // Core-V Extension Interface (CV-X-IF)
+  // Issue Interface
+  output logic                         x_issue_valid_o,
+  input  logic                         x_issue_ready_i,
+  output x_issue_req_t                 x_issue_req_o,
+  input  x_issue_resp_t                x_issue_resp_i,
+
+  // Register Interface
+  output x_register_t                  x_register_o,
+
+  // Commit Interface
+  output logic                         x_commit_valid_o,
+  output x_commit_t                    x_commit_o,
+
+  // Result Interface
+  input  logic                         x_result_valid_i,
+  output logic                         x_result_ready_o,
+  input  x_result_t                    x_result_i,
+
   // Interrupt inputs
   input  logic                         irq_software_i,
   input  logic                         irq_timer_i,
@@ -355,7 +375,8 @@ module cve2_core import cve2_pkg::*; #(
   cve2_id_stage #(
     .RV32E          (RV32E),
     .RV32M          (RV32M),
-    .RV32B          (RV32B)
+    .RV32B          (RV32B),
+    .XInterface     (XInterface)
   ) id_stage_i (
     .clk_i (clk_i),
     .rst_ni(rst_ni),
@@ -439,6 +460,25 @@ module cve2_core import cve2_pkg::*; #(
     .lsu_load_err_i (lsu_load_err),
     .lsu_store_err_i(lsu_store_err),
 
+    // Core-V Extension Interface (CV-X-IF)
+    // Issue Interface
+    .x_issue_valid_o(x_issue_valid_o),
+    .x_issue_ready_i(x_issue_ready_i),
+    .x_issue_req_o(x_issue_req_o),
+    .x_issue_resp_i(x_issue_resp_i),
+
+    // Register Interface
+    .x_register_o(x_register_o),
+
+    // Commit Interface
+    .x_commit_valid_o(x_commit_valid_o),
+    .x_commit_o(x_commit_o),
+
+    // Result Interface
+    .x_result_valid_i(x_result_valid_i),
+    .x_result_ready_o(x_result_ready_o),
+    .x_result_i(x_result_i),
+
     // Interrupt Signals
     .csr_mstatus_mie_i(csr_mstatus_mie),
     .irq_pending_i    (irq_pending_o),
diff --git a/rtl/cve2_decoder.sv b/rtl/cve2_decoder.sv
index 5b9cbca148..3d4ed8c716 100644
--- a/rtl/cve2_decoder.sv
+++ b/rtl/cve2_decoder.sv
@@ -16,7 +16,8 @@
 module cve2_decoder #(
   parameter bit RV32E               = 0,
   parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast,
-  parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone
+  parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone,
+  parameter bit               XInterface    = 1'b0
 ) (
   input  logic                 clk_i,
   input  logic                 rst_ni,
@@ -50,46 +51,50 @@ module cve2_decoder #(
   output logic [31:0]           zimm_rs1_type_o,
 
   // register file
-  output cve2_pkg::rf_wd_sel_e rf_wdata_sel_o,   // RF write data selection
-  output logic                 rf_we_o,          // write enable for regfile
-  output logic [4:0]           rf_raddr_a_o,
-  output logic [4:0]           rf_raddr_b_o,
-  output logic [4:0]           rf_waddr_o,
-  output logic                 rf_ren_a_o,          // Instruction reads from RF addr A
-  output logic                 rf_ren_b_o,          // Instruction reads from RF addr B
+  output logic [XInterface:0]      rf_wdata_sel_o,   // RF write data selection
+  output logic                     rf_we_o,          // write enable for regfile
+  output logic [4:0]               rf_raddr_a_o,
+  output logic [4:0]               rf_raddr_b_o,
+  output logic [4:0]               rf_waddr_o,
+  output logic                     rf_ren_a_o,          // Instruction reads from RF addr A
+  output logic                     rf_ren_b_o,          // Instruction reads from RF addr B
 
   // ALU
-  output cve2_pkg::alu_op_e    alu_operator_o,        // ALU operation selection
-  output cve2_pkg::op_a_sel_e  alu_op_a_mux_sel_o,    // operand a selection: reg value, PC,
-                                                      // immediate or zero
-  output cve2_pkg::op_b_sel_e  alu_op_b_mux_sel_o,    // operand b selection: reg value or
-                                                      // immediate
-  output logic                 alu_multicycle_o,      // ternary bitmanip instruction
+  output cve2_pkg::alu_op_e        alu_operator_o,        // ALU operation selection
+  output cve2_pkg::op_a_sel_e      alu_op_a_mux_sel_o,    // operand a selection: reg value, PC,
+                                                          // immediate or zero
+  output cve2_pkg::op_b_sel_e      alu_op_b_mux_sel_o,    // operand b selection: reg value or
+                                                          // immediate
+  output logic                     alu_multicycle_o,      // ternary bitmanip instruction
 
   // MULT & DIV
-  output logic                 mult_en_o,             // perform integer multiplication
-  output logic                 div_en_o,              // perform integer division or remainder
-  output logic                 mult_sel_o,            // as above but static, for data muxes
-  output logic                 div_sel_o,             // as above but static, for data muxes
+  output logic                     mult_en_o,             // perform integer multiplication
+  output logic                     div_en_o,              // perform integer division or remainder
+  output logic                     mult_sel_o,            // as above but static, for data muxes
+  output logic                     div_sel_o,             // as above but static, for data muxes
 
-  output cve2_pkg::md_op_e     multdiv_operator_o,
-  output logic [1:0]           multdiv_signed_mode_o,
+  output cve2_pkg::md_op_e         multdiv_operator_o,
+  output logic [1:0]               multdiv_signed_mode_o,
 
   // CSRs
-  output logic                 csr_access_o,          // access to CSR
-  output cve2_pkg::csr_op_e    csr_op_o,              // operation to perform on CSR
+  output logic                     csr_access_o,          // access to CSR
+  output cve2_pkg::csr_op_e        csr_op_o,              // operation to perform on CSR
 
   // LSU
-  output logic                 data_req_o,            // start transaction to data memory
-  output logic                 data_we_o,             // write enable
-  output logic [1:0]           data_type_o,           // size of transaction: byte, half
-                                                      // word or word
-  output logic                 data_sign_extension_o, // sign extension for data read from
+  output logic                     data_req_o,            // start transaction to data memory
+  output logic                     data_we_o,             // write enable
+  output logic [1:0]               data_type_o,           // size of transaction: byte, half
+                                                          // word or word
+  output logic                     data_sign_extension_o, // sign extension for data read from
                                                       // memory
 
+  // Core-V eXtension interface (CV-X-IF)
+  input  cve2_pkg::readregflags_t  x_issue_resp_register_read_i,
+  input  cve2_pkg::writeregflags_t x_issue_resp_writeback_i,
+
   // jump/branches
-  output logic                 jump_in_dec_o,         // jump is being calculated in ALU
-  output logic                 branch_in_dec_o
+  output logic                     jump_in_dec_o,         // jump is being calculated in ALU
+  output logic                     branch_in_dec_o
 );
 
   import cve2_pkg::*;
@@ -205,7 +210,7 @@ module cve2_decoder #(
     multdiv_operator_o    = MD_OP_MULL;
     multdiv_signed_mode_o = 2'b00;
 
-    rf_wdata_sel_o        = RF_WD_EX;
+    rf_wdata_sel_o        = $bits(rf_wdata_sel_o)'({RF_WD_EX});
     rf_we                 = 1'b0;
     rf_ren_a_o            = 1'b0;
     rf_ren_b_o            = 1'b0;
@@ -612,7 +617,7 @@ module cve2_decoder #(
         end else begin
           // instruction to read/modify CSR
           csr_access_o     = 1'b1;
-          rf_wdata_sel_o   = RF_WD_CSR;
+          rf_wdata_sel_o   = $bits(rf_wdata_sel_o)'({RF_WD_CSR});
           rf_we            = 1'b1;
 
           if (~instr[14]) begin
@@ -653,6 +658,13 @@ module cve2_decoder #(
       jump_set_o      = 1'b0;
       branch_in_dec_o = 1'b0;
       csr_access_o    = 1'b0;
+      // CV-X-IF
+      if(XInterface) begin
+        rf_ren_a_o       = x_issue_resp_register_read_i[0];
+        rf_ren_b_o       = x_issue_resp_register_read_i[1];
+        rf_we            = x_issue_resp_writeback_i;
+        rf_wdata_sel_o   = $bits(rf_wdata_sel_o)'({RF_WD_COPROC});
+      end 
     end
   end
 
diff --git a/rtl/cve2_id_stage.sv b/rtl/cve2_id_stage.sv
index e7ebf52c25..6f4d727f31 100644
--- a/rtl/cve2_id_stage.sv
+++ b/rtl/cve2_id_stage.sv
@@ -20,7 +20,8 @@
 module cve2_id_stage #(
   parameter bit               RV32E           = 0,
   parameter cve2_pkg::rv32m_e RV32M           = cve2_pkg::RV32MFast,
-  parameter cve2_pkg::rv32b_e RV32B           = cve2_pkg::RV32BNone
+  parameter cve2_pkg::rv32b_e RV32B           = cve2_pkg::RV32BNone,
+  parameter bit               XInterface      = 1'b0
 ) (
   input  logic                      clk_i,
   input  logic                      rst_ni,
@@ -102,6 +103,25 @@ module cve2_id_stage #(
   input  logic                      lsu_addr_incr_req_i,
   input  logic [31:0]               lsu_addr_last_i,
 
+  //  Core-V eXtension Interface (CV-X-IF)
+  //  Issue Interface
+  output logic                      x_issue_valid_o,
+  input  logic                      x_issue_ready_i,
+  output cve2_pkg::x_issue_req_t    x_issue_req_o,
+  input  cve2_pkg::x_issue_resp_t   x_issue_resp_i,
+
+  // Register Interface
+  output  cve2_pkg::x_register_t    x_register_o,
+
+  // Commit Interface
+  output logic                      x_commit_valid_o,
+  output cve2_pkg::x_commit_t       x_commit_o,
+
+  // Result Interface
+  input  logic                      x_result_valid_i,
+  output logic                      x_result_ready_o,
+  input   cve2_pkg::x_result_t      x_result_i,
+
   // Interrupt signals
   input  logic                      csr_mstatus_mie_i,
   input  logic                      irq_pending_i,
@@ -196,10 +216,10 @@ module cve2_id_stage #(
 
   // Register file interface
 
-  rf_wd_sel_e  rf_wdata_sel;
-  logic        rf_we_dec, rf_we_raw;
-  logic        rf_ren_a, rf_ren_b;
-  logic        rf_ren_a_dec, rf_ren_b_dec;
+  logic [XInterface:0] rf_wdata_sel;
+  logic                rf_we_dec, rf_we_raw;
+  logic                rf_ren_a, rf_ren_b;
+  logic                rf_ren_a_dec, rf_ren_b_dec;
 
   // Read enables should only be asserted for valid and legal instructions
   assign rf_ren_a = instr_valid_i & ~instr_fetch_err_i & ~illegal_insn_o & rf_ren_a_dec;
@@ -243,6 +263,81 @@ module cve2_id_stage #(
   logic [31:0] alu_operand_a;
   logic [31:0] alu_operand_b;
 
+  // CV-X-IF
+  logic stall_coproc;
+
+  ///////////////
+  // ID-EX FSM //
+  ///////////////
+
+  typedef enum logic { FIRST_CYCLE, MULTI_CYCLE } id_fsm_e;
+  id_fsm_e id_fsm_q, id_fsm_d;
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin : id_pipeline_reg
+    if (!rst_ni) begin
+      id_fsm_q <= FIRST_CYCLE;
+    end else if (instr_executing) begin
+      id_fsm_q <= id_fsm_d;
+    end
+  end
+
+  // CV-X-IF
+  if (XInterface) begin: gen_xif
+
+    logic coproc_done;
+    assign multicycle_done = lsu_req_dec ? lsu_resp_valid_i : (illegal_insn_dec ? coproc_done : ex_valid_i);
+
+    assign coproc_done = (x_issue_valid_o & x_issue_ready_i & ~x_issue_resp_i.writeback) | (x_result_valid_i & x_result_i.we);
+
+    // Issue Interface
+    assign x_issue_valid_o     = instr_executing & illegal_insn_dec & (id_fsm_q == FIRST_CYCLE);
+    assign x_issue_req_o.instr = instr_rdata_i;
+
+    // Register Interface
+    assign x_register_o.rs[0]    = rf_rdata_a_fwd;
+    assign x_register_o.rs[1]    = rf_rdata_b_fwd;
+    assign x_register_o.rs_valid = '1;
+
+    // Commit Interface
+    assign x_commit_valid_o       = 1'b1;
+    assign x_commit_o.commit_kill = 1'b0;
+
+    // Result Interface
+    assign x_result_ready_o = 1'b1;
+
+    assign illegal_insn_o = instr_valid_i & (illegal_csr_insn_i | (x_issue_valid_o & x_issue_ready_i & ~x_issue_resp_i.accept));
+  end
+
+  else begin: no_gen_xif
+    logic          unused_x_issue_ready;
+    x_issue_resp_t unused_x_issue_resp;
+    logic          unused_x_result_valid;
+    x_result_t     unused_x_result;
+
+
+    assign multicycle_done = lsu_req_dec ? lsu_resp_valid_i : ex_valid_i;
+
+    // Issue Interface
+    assign x_issue_valid_o      = 1'b0;
+    assign unused_x_issue_ready = x_issue_ready_i;
+    assign x_issue_req_o        = '0;
+    assign unused_x_issue_resp  = x_issue_resp_i;
+
+    // Register Interface
+    assign x_register_o = '0;
+
+    // Commit Interface
+    assign x_commit_valid_o = 1'b0;
+    assign x_commit_o       = '0;
+
+    // Result Interface
+    assign x_result_ready_o      = 1'b0;
+    assign unused_x_result_valid = x_result_valid_i;
+    assign unused_x_result       = x_result_i;
+
+    assign illegal_insn_o = instr_valid_i & (illegal_csr_insn_i | illegal_insn_dec);
+  end
+
   /////////////
   // LSU Mux //
   /////////////
@@ -323,10 +418,11 @@ module cve2_id_stage #(
 
   // Register file write data mux
   always_comb begin : rf_wdata_id_mux
-    unique case (rf_wdata_sel)
-      RF_WD_EX:  rf_wdata_id_o = result_ex_i;
-      RF_WD_CSR: rf_wdata_id_o = csr_rdata_i;
-      default:   rf_wdata_id_o = result_ex_i;
+    unique case ($bits(rf_wd_sel_e)'({rf_wdata_sel}))
+      RF_WD_EX:     rf_wdata_id_o   = result_ex_i;
+      RF_WD_CSR:    rf_wdata_id_o   = csr_rdata_i;
+      RF_WD_COPROC: rf_wdata_id_o   = XInterface? x_result_i.data : result_ex_i;
+      default:      rf_wdata_id_o   = result_ex_i;
     endcase
   end
 
@@ -337,7 +433,8 @@ module cve2_id_stage #(
   cve2_decoder #(
     .RV32E          (RV32E),
     .RV32M          (RV32M),
-    .RV32B          (RV32B)
+    .RV32B          (RV32B),
+    .XInterface     (XInterface)
   ) decoder_i (
     .clk_i (clk_i),
     .rst_ni(rst_ni),
@@ -402,6 +499,10 @@ module cve2_id_stage #(
     .data_type_o          (lsu_type),
     .data_sign_extension_o(lsu_sign_ext),
 
+    // Core-V eXtension Interface (CV-X-IF)
+    .x_issue_resp_register_read_i(x_issue_resp_i.register_read),
+    .x_issue_resp_writeback_i(x_issue_resp_i.writeback),
+
     // jump/branches
     .jump_in_dec_o  (jump_in_dec),
     .branch_in_dec_o(branch_in_dec)
@@ -442,8 +543,6 @@ module cve2_id_stage #(
   // Controller //
   ////////////////
 
-  assign illegal_insn_o = instr_valid_i & (illegal_insn_dec | illegal_csr_insn_i);
-
   cve2_controller #(
   ) controller_i (
     .clk_i (clk_i),
@@ -599,21 +698,6 @@ module cve2_id_stage #(
   assign jump_set        = jump_set_raw        & ~branch_jump_set_done_q;
   assign branch_set      = branch_set_raw      & ~branch_jump_set_done_q;
 
-  ///////////////
-  // ID-EX FSM //
-  ///////////////
-
-  typedef enum logic { FIRST_CYCLE, MULTI_CYCLE } id_fsm_e;
-  id_fsm_e id_fsm_q, id_fsm_d;
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin : id_pipeline_reg
-    if (!rst_ni) begin
-      id_fsm_q <= FIRST_CYCLE;
-    end else if (instr_executing) begin
-      id_fsm_q <= id_fsm_d;
-    end
-  end
-
   // ID/EX stage can be in two states, FIRST_CYCLE and MULTI_CYCLE. An instruction enters
   // MULTI_CYCLE if it requires multiple cycles to complete regardless of stalls and other
   // considerations. An instruction may be held in FIRST_CYCLE if it's unable to begin executing
@@ -626,6 +710,7 @@ module cve2_id_stage #(
     stall_jump              = 1'b0;
     stall_branch            = 1'b0;
     stall_alu               = 1'b0;
+    stall_coproc            = 1'b0;
     branch_set_raw_d        = 1'b0;
     jump_set_raw            = 1'b0;
     perf_branch_o           = 1'b0;
@@ -673,6 +758,30 @@ module cve2_id_stage #(
               id_fsm_d      = MULTI_CYCLE;
               rf_we_raw     = 1'b0;
             end
+            illegal_insn_dec: begin
+
+              // CV-X-IF
+              if(XInterface) begin
+                if(x_issue_valid_o && x_issue_ready_i) begin
+                  if(x_issue_resp_i.accept && x_issue_resp_i.writeback) begin
+                      id_fsm_d = MULTI_CYCLE;
+                      stall_coproc = 1'b1;
+                  end
+                  else begin
+                    id_fsm_d = FIRST_CYCLE;
+                  end
+                end
+                else begin
+                  stall_coproc = 1'b1;
+                  id_fsm_d = FIRST_CYCLE;
+                end
+              end
+              else begin
+                id_fsm_d = FIRST_CYCLE;
+              end
+
+            end
+
             default: begin
               id_fsm_d      = FIRST_CYCLE;
             end
@@ -690,6 +799,7 @@ module cve2_id_stage #(
             stall_multdiv   = multdiv_en_dec;
             stall_branch    = branch_in_dec;
             stall_jump      = jump_in_dec;
+            stall_coproc    = XInterface & illegal_insn_dec;
           end
         end
 
@@ -700,13 +810,16 @@ module cve2_id_stage #(
     end
   end
 
+
+
+
   `ASSERT(StallIDIfMulticycle, (id_fsm_q == FIRST_CYCLE) & (id_fsm_d == MULTI_CYCLE) |-> stall_id)
 
 
   // Stall ID/EX stage for reason that relates to instruction in ID/EX, update assertion below if
   // modifying this.
   assign stall_id = stall_mem | stall_multdiv | stall_jump | stall_branch |
-                      stall_alu;
+                      stall_alu | (XInterface & stall_coproc);
 
   // Generally illegal instructions have no reason to stall, however they must still stall waiting
   // for outstanding memory requests so exceptions related to them take priority over the illegal
@@ -723,34 +836,32 @@ module cve2_id_stage #(
   // Used by ALU to access RS3 if ternary instruction.
   assign instr_first_cycle_id_o = instr_first_cycle;
 
-    assign multicycle_done = lsu_req_dec ? lsu_resp_valid_i : ex_valid_i;
-
-    assign data_req_allowed = instr_first_cycle;
+  assign data_req_allowed = instr_first_cycle;
 
-    // Without Writeback Stage always stall the first cycle of a load/store.
-    // Then stall until it is complete
-    assign stall_mem = instr_valid_i & (lsu_req_dec & (~lsu_resp_valid_i | instr_first_cycle));
+  // Without Writeback Stage always stall the first cycle of a load/store.
+  // Then stall until it is complete
+  assign stall_mem = instr_valid_i & (lsu_req_dec & (~lsu_resp_valid_i | instr_first_cycle));
 
-    // Without writeback stage any valid instruction that hasn't seen an error will execute
-    assign instr_executing_spec = instr_valid_i & ~instr_fetch_err_i & controller_run;
-    assign instr_executing = instr_executing_spec;
+  // Without writeback stage any valid instruction that hasn't seen an error will execute
+  assign instr_executing_spec = instr_valid_i & ~instr_fetch_err_i & controller_run;
+  assign instr_executing = instr_executing_spec;
 
-    `ASSERT(IbexStallIfValidInstrNotExecuting,
-      instr_valid_i & ~instr_fetch_err_i & ~instr_executing & controller_run |-> stall_id)
+  `ASSERT(IbexStallIfValidInstrNotExecuting,
+    instr_valid_i & ~instr_fetch_err_i & ~instr_executing & controller_run |-> stall_id)
 
-    // No data forwarding without writeback stage so always take source register data direct from
-    // register file
-    assign rf_rdata_a_fwd = rf_rdata_a_i;
-    assign rf_rdata_b_fwd = rf_rdata_b_i;
+  // No data forwarding without writeback stage so always take source register data direct from
+  // register file
+  assign rf_rdata_a_fwd = rf_rdata_a_i;
+  assign rf_rdata_b_fwd = rf_rdata_b_i;
 
-    // Unused Writeback stage only IO & wiring
-    // Assign inputs and internal wiring to unused signals to satisfy lint checks
-    // Tie-off outputs to constant values
-    logic unused_data_req_done_ex;
+  // Unused Writeback stage only IO & wiring
+  // Assign inputs and internal wiring to unused signals to satisfy lint checks
+  // Tie-off outputs to constant values
+  logic unused_data_req_done_ex;
 
-    assign perf_dside_wait_o = instr_executing & lsu_req_dec & ~lsu_resp_valid_i;
+  assign perf_dside_wait_o = instr_executing & lsu_req_dec & ~lsu_resp_valid_i;
 
-    assign instr_id_done_o = instr_done;
+  assign instr_id_done_o = instr_done;
 
   // Signal which instructions to count as retired in minstret, all traps along with ebrk and
   // ecall instructions are not counted.
@@ -784,9 +895,17 @@ module cve2_id_stage #(
       OP_A_FWD,
       OP_A_CURRPC,
       OP_A_IMM})
-  `ASSERT(IbexRegfileWdataSelValid, instr_valid_i |-> rf_wdata_sel inside {
-      RF_WD_EX,
-      RF_WD_CSR})
+  if (XInterface) begin: gen_asserts_xif
+    `ASSERT(IbexRegfileWdataSelValid, instr_valid_i |-> rf_wdata_sel inside {
+        RF_WD_EX,
+        RF_WD_CSR,
+        RF_WD_COPROC})
+  end 
+  else begin : no_gen_asserts_xif
+    `ASSERT(IbexRegfileWdataSelValid, instr_valid_i |-> rf_wdata_sel inside {
+        RF_WD_EX,
+        RF_WD_CSR})
+  end
   `ASSERT_KNOWN(IbexWbStateKnown, id_fsm_q)
 
   // Branch decision must be valid when jumping.
@@ -803,7 +922,7 @@ module cve2_id_stage #(
 
   // Multicycle enable signals must be unique.
   `ASSERT(IbexMulticycleEnableUnique,
-      $onehot0({lsu_req_dec, multdiv_en_dec, branch_in_dec, jump_in_dec}))
+      $onehot0({lsu_req_dec, multdiv_en_dec, branch_in_dec, jump_in_dec, illegal_insn_dec}))
 
   // Duplicated instruction flops must match
   // === as DV environment can produce instructions with Xs in, so must use precise match that
diff --git a/rtl/cve2_pkg.sv b/rtl/cve2_pkg.sv
index 2e5b35352e..37c08c0312 100644
--- a/rtl/cve2_pkg.sv
+++ b/rtl/cve2_pkg.sv
@@ -260,9 +260,10 @@ package cve2_pkg;
   } imm_b_sel_e;
 
   // Regfile write data selection
-  typedef enum logic {
+  typedef enum {
     RF_WD_EX,
-    RF_WD_CSR
+    RF_WD_CSR,
+    RF_WD_COPROC // Only used when XInterface = 1
   } rf_wd_sel_e;
 
   //////////////
@@ -654,5 +655,57 @@ package cve2_pkg;
     rvfi_csr_elmt_t pmpaddr15;
   } rvfi_csr_t;
 
+  // CV-X-IF
+  parameter int unsigned X_NUM_RS       = 2;
+  parameter int unsigned X_ID_WIDTH     = 4;
+  parameter int unsigned X_RFR_WIDTH    = 32;
+  parameter int unsigned X_RFW_WIDTH    = 32;
+  parameter int unsigned X_HARTID_WIDTH = 1;
+  parameter int unsigned X_DUAL_READ    = 0;
+  parameter int unsigned X_DUAL_WRITE   = 0;
+
+  typedef logic [X_NUM_RS+X_DUAL_READ-1:0] readregflags_t;
+  typedef logic [X_DUAL_WRITE:0]           writeregflags_t;
+  typedef logic [X_ID_WIDTH-1:0]           id_t;
+  typedef logic [X_HARTID_WIDTH-1:0]       hartid_t;
+
+  // Issue Interface
+  typedef struct packed {
+    logic [31:0] instr;
+    hartid_t     hartid;
+    id_t         id;
+  } x_issue_req_t;
+
+  typedef struct packed {
+    logic           accept;
+    writeregflags_t writeback;
+    readregflags_t  register_read;
+  } x_issue_resp_t;
+
+  // Register Interface
+  typedef struct packed {
+    hartid_t                              hartid;
+    id_t                                  id;
+    logic [X_NUM_RS-1:0][X_RFR_WIDTH-1:0] rs;
+    readregflags_t                        rs_valid;
+  } x_register_t;
+
+  // Commit Interface
+  typedef struct packed {
+    hartid_t hartid;
+    id_t     id;
+    logic    commit_kill;
+  } x_commit_t;
+
+  // Result Interface
+  typedef struct packed {
+    hartid_t                hartid;
+    id_t                    id;
+    logic [X_RFW_WIDTH-1:0] data;
+    logic [4:0]             rd;
+    writeregflags_t         we;
+  } x_result_t;
+
+
 endpackage
 
diff --git a/rtl/cve2_top.sv b/rtl/cve2_top.sv
index d8c9b5983f..5f240695c8 100644
--- a/rtl/cve2_top.sv
+++ b/rtl/cve2_top.sv
@@ -17,7 +17,8 @@ module cve2_top import cve2_pkg::*; #(
   parameter int unsigned MHPMCounterNum   = 10,
   parameter int unsigned MHPMCounterWidth = 40,
   parameter bit          RV32E            = 1'b0,
-  parameter rv32m_e      RV32M            = RV32MFast
+  parameter rv32m_e      RV32M            = RV32MFast,
+  parameter bit          XInterface       = 1'b0
 ) (
   // Clock and Reset
   input  logic                         clk_i,
@@ -48,6 +49,25 @@ module cve2_top import cve2_pkg::*; #(
   input  logic [31:0]                  data_rdata_i,
   input  logic                         data_err_i,
 
+  // Core-V Extension Interface (CV-X-IF)
+  // Issue Interface
+  output logic                         x_issue_valid_o,
+  input  logic                         x_issue_ready_i,
+  output x_issue_req_t                 x_issue_req_o,
+  input  x_issue_resp_t                x_issue_resp_i,
+
+  // Register Interface
+  output x_register_t                  x_register_o,
+
+  // Commit Interface
+  output logic                         x_commit_valid_o,
+  output x_commit_t                    x_commit_o,
+
+  // Result Interface
+  input  logic                         x_result_valid_i,
+  output logic                         x_result_ready_o,
+  input  x_result_t                    x_result_i,
+
   // Interrupt inputs
   input  logic                         irq_software_i,
   input  logic                         irq_timer_i,
@@ -161,7 +181,8 @@ module cve2_top import cve2_pkg::*; #(
     .RV32M            (RV32M),
     .RV32B            (RV32B),
     .DbgTriggerEn     (DbgTriggerEn),
-    .DbgHwBreakNum    (DbgHwBreakNum)
+    .DbgHwBreakNum    (DbgHwBreakNum),
+    .XInterface       (XInterface)
   ) u_cve2_core (
     .clk_i(clk),
     .rst_ni,
@@ -187,6 +208,25 @@ module cve2_top import cve2_pkg::*; #(
     .data_rdata_i,
     .data_err_i,
 
+    // Core-V Extension Interface (CV-X-IF)
+    // Issue Interface
+    .x_issue_valid_o,
+    .x_issue_ready_i,
+    .x_issue_req_o,
+    .x_issue_resp_i,
+
+    // Register Interface
+    .x_register_o,
+
+    // Commit Interface
+    .x_commit_valid_o,
+    .x_commit_o,
+
+    // Result Interface
+    .x_result_valid_i,
+    .x_result_ready_o,
+    .x_result_i,
+
     .irq_software_i,
     .irq_timer_i,
     .irq_external_i,
@@ -268,7 +308,6 @@ module cve2_top import cve2_pkg::*; #(
 
   `ASSERT_KNOWN(IbexDataGntX, data_gnt_i)
   `ASSERT_KNOWN(IbexDataRValidX, data_rvalid_i)
-  `ASSERT_KNOWN_IF(IbexDataRPayloadX, {data_rdata_i, data_err_i}, data_rvalid_i)
 
   `ASSERT_KNOWN(IbexIrqX, {irq_software_i, irq_timer_i, irq_external_i, irq_fast_i, irq_nm_i})
 
diff --git a/rtl/cve2_top_tracing.sv b/rtl/cve2_top_tracing.sv
index 1f7ca6de43..f0015c9884 100644
--- a/rtl/cve2_top_tracing.sv
+++ b/rtl/cve2_top_tracing.sv
@@ -43,6 +43,25 @@ module cve2_top_tracing import cve2_pkg::*; #(
   input  logic [31:0]                  data_rdata_i,
   input  logic                         data_err_i,
 
+  // Core-V Extension Interface (CV-X-IF)
+  // Issue Interface
+  output logic                         x_issue_valid_o,
+  input  logic                         x_issue_ready_i,
+  output x_issue_req_t                 x_issue_req_o,
+  input  x_issue_resp_t                x_issue_resp_i,
+
+  // Register Interface
+  output x_register_t                  x_register_o,
+
+  // Commit Interface
+  output logic                         x_commit_valid_o,
+  output x_commit_t                    x_commit_o,
+
+  // Result Interface
+  input  logic                         x_result_valid_i,
+  output logic                         x_result_ready_o,
+  input  x_result_t                    x_result_i,
+
   // Interrupt inputs
   input  logic                         irq_software_i,
   input  logic                         irq_timer_i,
@@ -140,6 +159,25 @@ module cve2_top_tracing import cve2_pkg::*; #(
     .data_rdata_i,
     .data_err_i,
 
+    // Core-V Extension Interface (CV-X-IF)
+    // Issue Interface
+    .x_issue_valid_o,
+    .x_issue_ready_i,
+    .x_issue_req_o,
+    .x_issue_resp_i,
+
+    // Register Interface
+    .x_register_o,
+
+    // Commit Interface
+    .x_commit_valid_o,
+    .x_commit_o,
+
+    // Result Interface
+    .x_result_valid_i,
+    .x_result_ready_o,
+    .x_result_i,
+
     .irq_software_i,
     .irq_timer_i,
     .irq_external_i,
diff --git a/scripts/sec/sec.sh b/scripts/sec/sec.sh
index 51ff834cbe..9c2ce8d4e4 100755
--- a/scripts/sec/sec.sh
+++ b/scripts/sec/sec.sh
@@ -100,13 +100,21 @@ elif [[ "${target_tool}" == "mentor" ]]; then
 
 elif [[ "${target_tool}" == "yosys" ]]; then
     echo "Using Yosys EQY"
-    eqy -f yosys/sec.eqy -j $(($(nproc)/2)) -d ${report_dir} &> ${report_dir}/output.yosys.log
+
+    if ! [ -x "$(command -v eqy)" ]; then
+        echo "Yosys EQY (eqy) could not be found"
+        exit 1
+    fi
+
+    eqy -f yosys/sec.eqy -j $(($(nproc)/2)) -d ${report_dir} &> /dev/null
+    mv ${report_dir}/logfile.txt ${report_dir}/output.yosys.log
     rm yosys/golden_io.txt
 
     if [ -f "${report_dir}/PASS" ]; then 
         RESULT=0
     elif [ -f "${report_dir}/FAIL" ]; then 
         RESULT=1
+        echo "Check ${report_dir}/output.yosys.log"
     else
         echo "Failed to run Yosys EQY"
         exit 1


Reviews:
user: login: cairo-caplan
body: I'm glad for the addition of the eXtension Interface to the CVE2 :) 

Also, sorry for the delay on the review.

I added some comments basically regarding changes that should be necessary to keep the CVE2 behave the same way when the X-IF is not used, after @davideschiavone suggestion to run a Logical Equivalence Checking tool.

I used [Yosys EQY](https://github.com/YosysHQ/eqy) for it, you can run the same test applying the patch in attachment and running it with `cd scripts/sec && ./sec.sh -t yosys`

[patch_review_X-IF_cve2.zip](https://github.com/user-attachments/files/19111681/patch_review_X-IF_cve2.zip)

state: CHANGES_REQUESTED
author_association: NONE
submitted_at: 2025-03-06T16:19:03Z
user: login: cairo-caplan
state: COMMENTED
author_association: NONE
submitted_at: 2025-03-17T10:48:18Z
user: login: FrancescoDeMalde-synthara
state: COMMENTED
author_association: NONE
submitted_at: 2025-03-17T11:50:03Z
user: login: cairo-caplan
state: APPROVED
author_association: NONE
submitted_at: 2025-03-25T08:55:36Z
user: login: davideschiavone
state: COMMENTED
author_association: NONE
submitted_at: 2025-04-09T06:14:12Z
user: login: cairo-caplan
body: @davideschiavone, @FrancescoDeMalde-synthara: my opinion is that the code is still mergeable, as it would not affect the behaviour of the RTL without X-IF, but the X-IF would still need to be verified and fixed for this due to the invalid case on [line 649/663](https://github.com/openhwgroup/cve2/pull/284#discussion_r2035123905)


state: CHANGES_REQUESTED
author_association: NONE
submitted_at: 2025-04-09T11:01:35Z
user: login: cairo-caplan
state: COMMENTED
author_association: NONE
submitted_at: 2025-04-09T11:34:53Z

Review comments:
diff_hunk: @@ -646,7 +660,6 @@ module cve2_decoder #(
     // insufficient privileges), or when accessing non-available registers in RV32E,
     // these cases are not handled here
     if (illegal_insn) begin
-      rf_we           = 1'b0;
path: rtl/cve2_decoder.sv
user: login: cairo-caplan
body: Is the removal of this line necessary? If yes, is it due to a bug or it is needed to allow the eXtension Interface to work?
created_at: 2025-03-06T14:28:49Z
author_association: NONE
diff_hunk: @@ -690,6 +800,7 @@ module cve2_id_stage #(
             stall_multdiv   = multdiv_en_dec;
             stall_branch    = branch_in_dec;
             stall_jump      = jump_in_dec;
+            stall_coproc    = illegal_insn_dec;
path: rtl/cve2_id_stage.sv
user: login: cairo-caplan
body: I would add the condition of when the XInterface parameter is activated, so that it is fully compatible with the original design with the X-IF.
created_at: 2025-03-06T14:33:23Z
author_association: NONE
diff_hunk: @@ -626,6 +710,8 @@ module cve2_id_stage #(
     stall_jump              = 1'b0;
     stall_branch            = 1'b0;
     stall_alu               = 1'b0;
+    stall_coproc            = 1'b0;
+    stall_coproc            = 1'b0;
path: rtl/cve2_id_stage.sv
user: login: cairo-caplan
body: Duplicate line
created_at: 2025-03-06T15:54:26Z
author_association: NONE
diff_hunk: @@ -324,9 +419,10 @@ module cve2_id_stage #(
   // Register file write data mux
   always_comb begin : rf_wdata_id_mux
     unique case (rf_wdata_sel)
-      RF_WD_EX:  rf_wdata_id_o = result_ex_i;
-      RF_WD_CSR: rf_wdata_id_o = csr_rdata_i;
-      default:   rf_wdata_id_o = result_ex_i;
+      RF_WD_EX:     rf_wdata_id_o   = result_ex_i;
+      RF_WD_CSR:    rf_wdata_id_o   = csr_rdata_i;
+      RF_WD_COPROC: rf_wdata_id_o   = x_result_i.data;
path: rtl/cve2_id_stage.sv
user: login: cairo-caplan
body: It would be better to limit the case `RF_WD_COPROC: rf_wdata_id_o   = x_result_i.data;` to only when X-IF is used, i.e. when `XInterface` is enabled.
created_at: 2025-03-06T16:02:21Z
author_association: NONE
diff_hunk: @@ -646,7 +660,6 @@ module cve2_decoder #(
     // insufficient privileges), or when accessing non-available registers in RV32E,
     // these cases are not handled here
     if (illegal_insn) begin
-      rf_we           = 1'b0;
path: rtl/cve2_decoder.sv
user: login: cairo-caplan
body: @FrancescoDeMalde-synthara, could you please take a look on it?
created_at: 2025-03-17T10:48:17Z
author_association: NONE
diff_hunk: @@ -646,7 +660,6 @@ module cve2_decoder #(
     // insufficient privileges), or when accessing non-available registers in RV32E,
     // these cases are not handled here
     if (illegal_insn) begin
-      rf_we           = 1'b0;
path: rtl/cve2_decoder.sv
user: login: FrancescoDeMalde-synthara
body: Based on my understanding, when the interface is enabled, the write enable signal of the register file is determined by the writeback signal from the issue interface response packet. If I had not removed that line, when an illegal instruction is detected and XInterface is set to 1, the illegal_insn signal would be asserted, causing execution to enter the subsequent if statement, where the write enable signal was explicitly set to 0.

If XInterface is set to 0 and an illegal instruction is encountered, I believed this would not cause an issue, even though rf_we is not explicitly set to 0, as it should retain its default value of 0.
created_at: 2025-03-17T11:50:03Z
author_association: NONE
diff_hunk: @@ -646,7 +660,7 @@ module cve2_decoder #(
     // insufficient privileges), or when accessing non-available registers in RV32E,
     // these cases are not handled here
     if (illegal_insn) begin
-      rf_we           = 1'b0;
+      rf_we           &= XInterface;
path: rtl/cve2_decoder.sv
user: login: davideschiavone
body: @cairo-caplan - why do we have the `&=` operator?
created_at: 2025-04-09T06:14:01Z
author_association: NONE
diff_hunk: @@ -646,7 +660,6 @@ module cve2_decoder #(
     // insufficient privileges), or when accessing non-available registers in RV32E,
     // these cases are not handled here
     if (illegal_insn) begin
-      rf_we           = 1'b0;
path: rtl/cve2_decoder.sv
user: login: cairo-caplan
body: Hi @FrancescoDeMalde-synthara. Thank you for the explanation, and sorry for having to come back to this issue.

I had overlooked this by also assuming `rf_we` would keep its default value of 0, so that this line could eventually be removed. However, it does the following illegal instruction situation that can lead to the registers file being written if it is removed:

0. Starting on  `unique case (opcode)` of line 236, where `opcode` is `instr[6:0]`
1.  When **`opcode` == `OPCODE_SYSTEM`,** entering the case of line 588.
2. **`instr[14:12]`** is not equal to `3'b000`, taking an example of **`3'b100`**, entering the else of line 617 and setting `rf_we` to 1 at line 621.
3. `instr[13:12]`, goes into the default case because of the example where `[13:12]` is `2'b00` at line 631, then it sets `csr_illegal`  to 1 at the same line. It causes `illegal_insn` to also set its value to 1 at line 634  (btw the only purpose of `csr_illegal` in the code).
4. When it enters the subsequent `if (illegal_insn) begin` at line 662, it is known it is an illegal instruction as `illegal_insn` is 1, but the `rf_we` is also kept a 1 when it should not.

Previously, I had proposed to reset `rf_we` only when `XInterface` is disabled (to make SEC pass), as in [line 663 and the comment below](https://github.com/openhwgroup/cve2/pull/284/files#r2034519122), but that would make this invalid situation possible when `XInterface` is enabled.


created_at: 2025-04-09T10:58:44Z
author_association: NONE
diff_hunk: @@ -646,7 +660,7 @@ module cve2_decoder #(
     // insufficient privileges), or when accessing non-available registers in RV32E,
     // these cases are not handled here
     if (illegal_insn) begin
-      rf_we           = 1'b0;
+      rf_we           &= XInterface;
path: rtl/cve2_decoder.sv
user: login: cairo-caplan
body: I answered you on the chat, but just to let it registered :)
It is the same as writing `rf_we = rf_we & XInterface;`, which means:
-  `rf_we` is reset if `XInterface` is 0 (same behaviour as on original core without X-IF)
- otherwise it keeps its value for `XInterface` is 1, but that can still lead to the issue I described [here](https://github.com/openhwgroup/cve2/pull/284#discussion_r2035123905)

created_at: 2025-04-09T11:34:52Z
author_association: NONE

PR comments:
user: login: MikeOpenHWGroup
created_at: 2025-03-25T13:08:11Z
body: Hi @FrancescoDeMalde-synthara. Before we can merge in this PR, you will need to be covered by the Eclipse Contributor Agreement.  It is painless, we promise!  Please check out [CONTRIBUTING](https://github.com/openhwgroup/cve2/blob/main/CONTRIBUTING.md) for information about how to do that.
author_association: MEMBER
user: login: FrancescoDeMalde-synthara
created_at: 2025-04-01T12:10:31Z
body: Hi,
Looking at the agreement, it seems that it is meant to be between the
Eclipse Foundation and Synthara. However, in the “Member” section, my
signature is expected, which creates a bit of confusion. Since I cannot
sign on behalf of Synthara, if the agreement is indeed between Eclipse and
the company, then I believe someone with signing authority, like the CTO,
should be the one to sign.

Could you please confirm if I understood this correctly and if it’s ok for
the CTO to sign instead?

Best regards,
Francesco

On Tue, 25 Mar 2025 at 14:08, Mike Thompson ***@***.***>
wrote:

> Hi @FrancescoDeMalde-synthara
> <https://github.com/FrancescoDeMalde-synthara>. Before we can merge in
> this PR, you will need to be covered by the Eclipse Contributor Agreement.
> It is painless, we promise! Please check out CONTRIBUTING
> <https://github.com/openhwgroup/cve2/blob/main/CONTRIBUTING.md> for
> information about how to do that.
>
> —
> Reply to this email directly, view it on GitHub
> <https://github.com/openhwgroup/cve2/pull/284#issuecomment-2751207927>,
> or unsubscribe
> <https://github.com/notifications/unsubscribe-auth/BIBQFICRLHZMEOOIMER3WH32WFINDAVCNFSM6AAAAABX73JFMWVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDONJRGIYDOOJSG4>
> .
> You are receiving this because you were mentioned.Message ID:
> ***@***.***>
> [image: MikeOpenHWGroup]*MikeOpenHWGroup* left a comment
> (openhwgroup/cve2#284)
> <https://github.com/openhwgroup/cve2/pull/284#issuecomment-2751207927>
>
> Hi @FrancescoDeMalde-synthara
> <https://github.com/FrancescoDeMalde-synthara>. Before we can merge in
> this PR, you will need to be covered by the Eclipse Contributor Agreement.
> It is painless, we promise! Please check out CONTRIBUTING
> <https://github.com/openhwgroup/cve2/blob/main/CONTRIBUTING.md> for
> information about how to do that.
>
> —
> Reply to this email directly, view it on GitHub
> <https://github.com/openhwgroup/cve2/pull/284#issuecomment-2751207927>,
> or unsubscribe
> <https://github.com/notifications/unsubscribe-auth/BIBQFICRLHZMEOOIMER3WH32WFINDAVCNFSM6AAAAABX73JFMWVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDONJRGIYDOOJSG4>
> .
> You are receiving this because you were mentioned.Message ID:
> ***@***.***>
>

author_association: NONE
user: login: MikeOpenHWGroup
created_at: 2025-04-01T12:43:32Z
body: For the [ECA](https://www.eclipse.org/legal/eca/), this is an agreement between Eclipse and an individual.  It has been a long time since I signed it, but as I recall, you can sign this electronically.

As you say, the [MCCA](https://www.eclipse.org/legal/committer-process/eclipse-member-committer-agreement.pdf) is an agreement between Eclipse and a Member company.

If you are contributing on behalf of Synthara, it is recommended that Synthara signs the MCCA and this will automatically cover you.  If you are contributing on behalf of yourself, the ECA is sufficient.
author_association: MEMBER
user: login: FrancescoDeMalde-synthara
created_at: 2025-04-07T15:26:15Z
body: Hi,
I have just signed the ECA agreement electronically. Please let me know if
everything is in order.

Best regards,
Francesco

On Tue, 1 Apr 2025 at 14:43, Mike Thompson ***@***.***> wrote:

> For the ECA <https://www.eclipse.org/legal/eca/>, this is an agreement
> between Eclipse and an individual. It has been a long time since I signed
> it, but as I recall, you can sign this electronically.
>
> As you say, the MCCA
> <https://www.eclipse.org/legal/committer-process/eclipse-member-committer-agreement.pdf>
> is an agreement between Eclipse and a Member company.
>
> If you are contributing on behalf of Synthara, it is recommended that
> Synthara signs the MCCA and this will automatically cover you. If you are
> contributing on behalf of yourself, the ECA is sufficient.
>
> —
> Reply to this email directly, view it on GitHub
> <https://github.com/openhwgroup/cve2/pull/284#issuecomment-2769236336>,
> or unsubscribe
> <https://github.com/notifications/unsubscribe-auth/BIBQFIDYCDL5N4BE3OP6THD2XKCYVAVCNFSM6AAAAABX73JFMWVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDONRZGIZTMMZTGY>
> .
> You are receiving this because you were mentioned.Message ID:
> ***@***.***>
> [image: MikeOpenHWGroup]*MikeOpenHWGroup* left a comment
> (openhwgroup/cve2#284)
> <https://github.com/openhwgroup/cve2/pull/284#issuecomment-2769236336>
>
> For the ECA <https://www.eclipse.org/legal/eca/>, this is an agreement
> between Eclipse and an individual. It has been a long time since I signed
> it, but as I recall, you can sign this electronically.
>
> As you say, the MCCA
> <https://www.eclipse.org/legal/committer-process/eclipse-member-committer-agreement.pdf>
> is an agreement between Eclipse and a Member company.
>
> If you are contributing on behalf of Synthara, it is recommended that
> Synthara signs the MCCA and this will automatically cover you. If you are
> contributing on behalf of yourself, the ECA is sufficient.
>
> —
> Reply to this email directly, view it on GitHub
> <https://github.com/openhwgroup/cve2/pull/284#issuecomment-2769236336>,
> or unsubscribe
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author_association: NONE
user: login: MikeOpenHWGroup
created_at: 2025-04-07T22:00:39Z
body: Hi @FrancescoDeMalde-synthara.  The Eclipse ECA check seems to believe the email used to submit this PR follows the form:

`167969440+FrancescoDeMalde-synthara@us*rs DOT noreply DOT github DOT com`.
author_association: MEMBER
user: login: FrancescoDeMalde-synthara
created_at: 2025-04-09T10:15:33Z
body: Hi,
I’ve linked my GitHub account to my Eclipse account, so I think that should take care of the email issue with the ECA check. @MikeOpenHWGroup 

About the XIF implementation, I ran into something while porting it to our design, which already includes other custom instructions. What I noticed is that some instructions that can be offloaded to the XIF and others that cannot offload still use the same opcode. Because of this, an offloadable instruction might enter an opcode case meant for a different instruction and eventually hit the default case. This means the logic added in the default block has to be repeated in multiple places.

In my opinion, it would be cleaner to move the offloading logic directly into the "if (illegal_insn)" block, where the issue with the rf_we signal also shows up. This would make the offload handling clearer and more consistent, and it might also solve the rf_we issue. @davideschiavone 
author_association: NONE
user: login: davideschiavone
created_at: 2025-04-09T11:19:52Z
body: > @davideschiavone, @FrancescoDeMalde-synthara: my opinion is that the code is still mergeable, as it would not affect the behaviour of the RTL without X-IF, but the X-IF would still need to be verified and fixed for this due to the invalid case on [line 649/663](https://github.com/openhwgroup/cve2/pull/284#discussion_r2035123905)

hi @FrancescoDeMalde-synthara - I agree with @cairo-caplan to first merge this PR, then fix the X-IF interface by moving the logic so that - this way we can close this PR and add another one on top - would you be ok with this @FrancescoDeMalde-synthara ?
author_association: NONE
user: login: MikeOpenHWGroup
created_at: 2025-04-09T19:01:57Z
body: > I’ve linked my GitHub account to my Eclipse account, so I think that should take care of the email issue with the ECA check. @MikeOpenHWGroup

Yep, the ECA check is fixed now.  Thanks.
author_association: MEMBER
user: login: cairo-caplan
created_at: 2025-04-10T09:00:08Z
body: All good on my side.

- [x] checks SEC
author_association: NONE
user: login: davideschiavone
created_at: 2025-04-10T09:06:44Z
body: > All good on my side.
> 
> * [x]  checks SEC

all good from my side too - @FrancescoDeMalde-synthara - @cairo-caplan and I are good to merge - let's us know 
author_association: NONE
user: login: FrancescoDeMalde-synthara
created_at: 2025-04-10T09:12:14Z
body: All good also for me.

On Thu, 10 Apr 2025 at 11:07, Davide Schiavone ***@***.***>
wrote:

> All good on my side.
>
>    - checks SEC
>
> all good from my side too - @FrancescoDeMalde-synthara
> <https://github.com/FrancescoDeMalde-synthara> - @cairo-caplan
> <https://github.com/cairo-caplan> and I are good to merge - let's us know
>
> —
> Reply to this email directly, view it on GitHub
> <https://github.com/openhwgroup/cve2/pull/284#issuecomment-2792076039>,
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> *davideschiavone* left a comment (openhwgroup/cve2#284)
> <https://github.com/openhwgroup/cve2/pull/284#issuecomment-2792076039>
>
> All good on my side.
>
>    - checks SEC
>
> all good from my side too - @FrancescoDeMalde-synthara
> <https://github.com/FrancescoDeMalde-synthara> - @cairo-caplan
> <https://github.com/cairo-caplan> and I are good to merge - let's us know
>
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author_association: NONE