Repository: zephyrproject-rtos/zephyr
Pull request #89909: soc: nxp: mcx: MCXN947: add NVS subsystem support with flash_k4 driver
Author: login: DerekSnell
Labels: name: area: Samples
description: Samples
name: area: Flash
name: platform: NXP
description: NXP
name: manifest
name: manifest-hal_nxp
Created: 2025-05-13T21:27:34Z | Merged: 2025-05-31T09:57:40Z

- updates this SOC to use flash_k4 driver.  Uses flash_k4 driver for internal flash instead of ROM API driver.  One
benefit is the flash program phrase size decreases from 128 Bytes to 16 Bytes.  16 Byte phrases enables this SOC to leverage the Zephyr NVS subsystem, and the MCUboot swap mode.
- adds testcase for MCXN947 internal flash in samples/subsys/nvs.  For boards frdm_mcxn947 and mcx_n9xx_evks test NVS in internal flash in addition to external QSPI flash.  Also enable the NVS subsystem on these boards for Twister.



Diff:
diff --git a/boards/nxp/frdm_mcxn947/board.c b/boards/nxp/frdm_mcxn947/board.c
index c1384e6c183ae..9e6195fd74692 100644
--- a/boards/nxp/frdm_mcxn947/board.c
+++ b/boards/nxp/frdm_mcxn947/board.c
@@ -99,6 +99,11 @@ void board_early_init_hook(void)
 	/* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */
 	FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U));
 
+#ifdef CONFIG_FLASH
+	/* Enable clock for internal FMU flash */
+	CLOCK_SetupClockCtrl(SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK);
+#endif
+
 	/* Enable FRO HF(48MHz) output */
 	CLOCK_SetupFROHFClocking(48000000U);
 
diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml
index 057162bca2642..1648313dc3d37 100644
--- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml
+++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml
@@ -24,6 +24,7 @@ supported:
   - i2c
   - i2s
   - i3c
+  - nvs
   - pwm
   - regulator
   - rtc
diff --git a/boards/nxp/mcx_n9xx_evk/board.c b/boards/nxp/mcx_n9xx_evk/board.c
index 4d6c1f6d69495..5b5a13c1ae990 100644
--- a/boards/nxp/mcx_n9xx_evk/board.c
+++ b/boards/nxp/mcx_n9xx_evk/board.c
@@ -99,6 +99,11 @@ void board_early_init_hook(void)
 	/* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */
 	FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U));
 
+#ifdef CONFIG_FLASH
+	/* Enable clock for internal FMU flash */
+	CLOCK_SetupClockCtrl(SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK);
+#endif
+
 	/* Enable FRO HF(48MHz) output */
 	CLOCK_SetupFROHFClocking(48000000U);
 
diff --git a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.yaml b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.yaml
index b7f1b052e2e1d..dd0b5d2e7732c 100644
--- a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.yaml
+++ b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.yaml
@@ -24,6 +24,7 @@ supported:
   - i2c
   - i2s
   - i3c
+  - nvs
   - pwm
   - regulator
   - rtc
diff --git a/dts/arm/nxp/nxp_mcxnx4x_common.dtsi b/dts/arm/nxp/nxp_mcxnx4x_common.dtsi
index 33330aa72bfb9..7505d44aaaad1 100644
--- a/dts/arm/nxp/nxp_mcxnx4x_common.dtsi
+++ b/dts/arm/nxp/nxp_mcxnx4x_common.dtsi
@@ -629,8 +629,7 @@
 			compatible = "soc-nv-flash";
 			reg = <0 DT_SIZE_M(2)>;
 			erase-block-size = <8192>;
-			/* MCXN54x ROM Flash API supports writing of 128B pages. */
-			write-block-size = <128>;
+			write-block-size = <16>;
 		};
 
 		uuid: uuid@1100000 {
diff --git a/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake b/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake
index 9c6ae45585b57..14af317323b57 100644
--- a/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake
+++ b/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake
@@ -197,7 +197,7 @@ if(CONFIG_SOC_MK82F25615 OR CONFIG_SOC_MK64F12 OR CONFIG_SOC_MK66F18 OR
   set(CONFIG_MCUX_COMPONENT_driver.sysmpu ON)
 endif()
 
-if(CONFIG_SOC_SERIES_MCXW)
+if(CONFIG_SOC_SERIES_MCXW OR CONFIG_SOC_MCXN947 OR CONFIG_SOC_MCXN547)
   set_variable_ifdef(CONFIG_SOC_FLASH_MCUX CONFIG_MCUX_COMPONENT_driver.flash_k4)
 endif()
 
@@ -262,7 +262,7 @@ if(CONFIG_SOC_SERIES_MCXA)
   set(CONFIG_MCUX_COMPONENT_driver.romapi ON)
 endif()
 
-if(CONFIG_SOC_SERIES_MCXN)
+if(CONFIG_SOC_SERIES_MCXN AND !CONFIG_SOC_MCXN947 AND !CONFIG_SOC_MCXN547)
   set_variable_ifdef(CONFIG_SOC_FLASH_MCUX CONFIG_MCUX_COMPONENT_driver.romapi_flashiap)
 endif()
 
diff --git a/samples/subsys/nvs/nxp/mcxn947_internal_flash.overlay b/samples/subsys/nvs/nxp/mcxn947_internal_flash.overlay
new file mode 100644
index 0000000000000..2644340913243
--- /dev/null
+++ b/samples/subsys/nvs/nxp/mcxn947_internal_flash.overlay
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* The MCXN947 boards place the storage_partition in external flash.  For this
+ * testcase, move the storage_partition to internal flash
+ */
+
+/delete-node/ &storage_partition;
+
+&flash {
+	partitions {
+		storage_partition: partition@100000 {
+			label = "storage";
+			reg = <0x100000 DT_SIZE_M(1)>;
+		};
+	};
+};
diff --git a/samples/subsys/nvs/sample.yaml b/samples/subsys/nvs/sample.yaml
index 051edc635f9d8..c3a454cb80745 100644
--- a/samples/subsys/nvs/sample.yaml
+++ b/samples/subsys/nvs/sample.yaml
@@ -21,3 +21,27 @@ tests:
            39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 \
            56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 \
            73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f"
+  sample.nvs.internal_flash:
+    tags: nvs
+    depends_on: nvs
+    integration_platforms:
+      - frdm_mcxn947/mcxn947/cpu0
+    platform_allow:
+      - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
+    extra_args:
+      - platform:frdm_mcxn947/mcxn947/cpu0:"DTC_OVERLAY_FILE=nxp/mcxn947_internal_flash.overlay"
+      - platform:mcx_n9xx_evk/mcxn947/cpu0:"DTC_OVERLAY_FILE=nxp/mcxn947_internal_flash.overlay"
+    harness: console
+    harness_config:
+      type: multi_line
+      regex:
+        - "Id: 1, Address: 192.168.1.1"
+        - "Id: 2, Key: ff fe fd fc fb fa f9 f8"
+        - "Id: 3, Reboot_counter: (.*)"
+        - "Id: 4, Data: DATA"
+        - "Id: 5, Longarray: 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12 13 14 15 16 17 18 19 1a 1b \
+           1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 \
+           39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 \
+           56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 \
+           73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f"
diff --git a/soc/nxp/mcx/mcxn/Kconfig.defconfig b/soc/nxp/mcx/mcxn/Kconfig.defconfig
index 50d7ba40eb6dd..2d70ffa351040 100644
--- a/soc/nxp/mcx/mcxn/Kconfig.defconfig
+++ b/soc/nxp/mcx/mcxn/Kconfig.defconfig
@@ -24,8 +24,12 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 16000 if MCUX_LPTMR_TIMER
 	default 150000000 if CORTEX_M_SYSTICK
 
+config MCUX_FLASH_K4_API
+	default y if (SOC_MCXN947 || SOC_MCXN547) # Initially, only Nx4x uses the k4 driver
+
 # Set to the minimal size of data which can be written.
 config FLASH_FILL_BUFFER_SIZE
+	default 16 if (SOC_MCXN947 || SOC_MCXN547) # Initially, only Nx4x uses the k4 driver
 	default 128
 
 # The existing SAI diver cannot initialize the PLL on the board,
diff --git a/west.yml b/west.yml
index c666805fe1214..b21198ed0cd01 100644
--- a/west.yml
+++ b/west.yml
@@ -210,7 +210,7 @@ manifest:
       groups:
         - hal
     - name: hal_nxp
-      revision: cea5006f1829520e40db1b550a9f49cc69ceba7d
+      revision: 2fe4ab6cd0d5586d12cc396197d956493575a0dd
       path: modules/hal/nxp
       groups:
         - hal


Reviews:
user: login: hakehuang
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-05-14T04:51:03Z
user: login: butok
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-05-14T06:27:14Z
user: login: DerekSnell
state: COMMENTED
author_association: NONE
submitted_at: 2025-05-15T16:35:36Z
user: login: DerekSnell
state: COMMENTED
author_association: NONE
submitted_at: 2025-05-15T16:38:41Z
user: login: butok
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-05-16T06:20:53Z
user: login: hakehuang
state: COMMENTED
author_association: CONTRIBUTOR
submitted_at: 2025-05-16T07:44:36Z
user: login: hakehuang
state: DISMISSED
author_association: CONTRIBUTOR
submitted_at: 2025-05-26T05:35:35Z
user: login: hakehuang
state: DISMISSED
author_association: CONTRIBUTOR
submitted_at: 2025-05-30T04:19:33Z
user: login: decsny
state: DISMISSED
author_association: MEMBER
submitted_at: 2025-05-30T17:34:36Z
user: login: dleach02
state: APPROVED
author_association: MEMBER
submitted_at: 2025-05-30T18:27:17Z
user: login: decsny
state: APPROVED
author_association: MEMBER
submitted_at: 2025-05-30T18:30:46Z

Review comments:
diff_hunk: @@ -21,3 +21,27 @@ tests:
            39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 \
            56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 \
            73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f"
+  sample.nvs.internal_flash:
+    tags: nvs
+    depends_on: nvs
path: samples/subsys/nvs/sample.yaml
user: login: hakehuang
body: we need add nvs in the <board>.yaml support list, otherwise this application will be filtered out.
created_at: 2025-05-14T04:51:02Z
author_association: CONTRIBUTOR
diff_hunk: @@ -24,6 +24,7 @@ supported:
   - i2c
   - i2s
   - i3c
+  - nvs
path: boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml
user: login: butok
body: I am personally OK with using SW features, but Zephyr considers it as a mistake.
Please read the comment of @nashif:
https://github.com/zephyrproject-rtos/zephyr/pull/79924#issuecomment-2422424335
created_at: 2025-05-14T06:27:14Z
author_association: CONTRIBUTOR
diff_hunk: @@ -24,6 +24,7 @@ supported:
   - i2c
   - i2s
   - i3c
+  - nvs
path: boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml
user: login: DerekSnell
body: Thanks @butok .  But the NVS support does depend on the hardware.  NVS does not support flash with program phrase sizes over 32 Bytes.  This is the major reason this PR moves this SOC to the other driver, to enable NVS.  I feel we do need to filter the NVS tests and samples based on the HW platform.  NXP still has other platforms that are not compatible with NVS, like the LPC5500 family.
created_at: 2025-05-15T16:35:36Z
author_association: NONE
diff_hunk: @@ -21,3 +21,27 @@ tests:
            39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 \
            56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 \
            73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f"
+  sample.nvs.internal_flash:
+    tags: nvs
+    depends_on: nvs
path: samples/subsys/nvs/sample.yaml
user: login: DerekSnell
body: Thanks @hakehuang ,
I already have `nvs` added to frdm_mcxn947_mcxn947_cpu0.yaml.  And I confirmed Twister will run this sample on these 2 boards.  Or are you referring to something else?
created_at: 2025-05-15T16:38:41Z
author_association: NONE
diff_hunk: @@ -24,6 +24,7 @@ supported:
   - i2c
   - i2s
   - i3c
+  - nvs
path: boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml
user: login: butok
body: > But the NVS support does depend on the hardware.

Nice. I will use this argument in future discussions. ;)
created_at: 2025-05-16T06:20:53Z
author_association: CONTRIBUTOR
diff_hunk: @@ -21,3 +21,27 @@ tests:
            39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 \
            56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 \
            73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f"
+  sample.nvs.internal_flash:
+    tags: nvs
+    depends_on: nvs
path: samples/subsys/nvs/sample.yaml
user: login: hakehuang
body: Thanks. So only test on frdm board is enough.
created_at: 2025-05-16T07:44:36Z
author_association: CONTRIBUTOR

PR comments:
user: login: github-actions[bot]
created_at: 2025-05-13T21:29:02Z
body: The following west manifest projects have changed revision in this Pull Request:

| Name | Old Revision | New Revision | Diff |
| ---- | ------------ | ------------ |------|
| hal_nxp | https://github.com/zephyrproject-rtos/hal_nxp/commit/cea5006f1829520e40db1b550a9f49cc69ceba7d | https://github.com/zephyrproject-rtos/hal_nxp/commit/2fe4ab6cd0d5586d12cc396197d956493575a0dd| [zephyrproject-rtos/hal_nxp@cea5006f..2fe4ab6c](https://github.com/zephyrproject-rtos/hal_nxp/compare/cea5006f1829520e40db1b550a9f49cc69ceba7d..2fe4ab6cd0d5586d12cc396197d956493575a0dd) |

✅ **All manifest checks OK**

*Note: This message is automatically posted and updated by the Manifest GitHub Action.* 
author_association: NONE
user: login: DerekSnell
created_at: 2025-05-13T21:29:58Z
body: @hakehuang , can you help test this?  This changes the driver used for internal flash.  Only the MCXN947 and MCXW devices use this flash_k4 driver currently.  The other MCXN and MCXA devices use the existing ROM API driver (for now).
author_association: NONE
user: login: hakehuang
created_at: 2025-05-14T04:20:35Z
body: > @hakehuang , can you help test this? This changes the driver used for internal flash. Only the MCXN947 and MCXW devices use this flash_k4 driver currently. The other MCXN and MCXA devices use the existing ROM API driver (for now).

@DerekSnell , but this will cause the tests/drivers/flash cases failure on those board
```
2025-05-14 11:44:36,353 - twister - DEBUG - DEVICE: ===================================================================
2025-05-14 11:44:36,356 - twister - DEBUG - DEVICE: TESTSUITE flash_driver failed.
2025-05-14 11:44:36,360 - twister - DEBUG - DEVICE: ------ TESTSUITE SUMMARY START ------
2025-05-14 11:44:36,369 - twister - DEBUG - DEVICE: SUITE FAIL -  50.00% [flash_driver]: pass = 3, fail = 3, skip = 1, total = 7 duration = 2.213 seconds
2025-05-14 11:44:36,375 - twister - DEBUG - DEVICE: - PASS - [flash_driver.test_flash_copy] duration = 0.129 seconds
2025-05-14 11:44:36,381 - twister - DEBUG - DEVICE: - FAIL - [flash_driver.test_flash_erase] duration = 1.705 seconds
2025-05-14 11:44:36,386 - twister - DEBUG - DEVICE: - FAIL - [flash_driver.test_flash_fill] duration = 0.105 seconds
2025-05-14 11:44:36,392 - twister - DEBUG - DEVICE: - FAIL - [flash_driver.test_flash_flatten] duration = 0.104 seconds
2025-05-14 11:44:36,399 - twister - DEBUG - DEVICE: - PASS - [flash_driver.test_flash_page_layout] duration = 0.045 seconds
2025-05-14 11:44:36,404 - twister - DEBUG - DEVICE: - SKIP - [flash_driver.test_get_size] duration = 0.043 seconds
2025-05-14 11:44:36,411 - twister - DEBUG - DEVICE: - PASS - [flash_driver.test_read_unaligned_address] duration = 0.082 seconds
2025-05-14 11:44:36,415 - twister - DEBUG - DEVICE: ------ TESTSUITE SUMMARY END ------
2025-05-14 11:44:36,421 - twister - DEBUG - DEVICE: ===================================================================
2025-05-14 11:44:36,424 - twister - DEBUG - DEVICE: RunID: ff28e480f2713a77f8f07bd24c2121e6
2025-05-14 11:44:36,427 - twister - DEBUG - DEVICE: PROJECT EXECUTION FAILED
```
author_association: CONTRIBUTOR
user: login: DerekSnell
created_at: 2025-05-15T17:39:04Z
body: > @DerekSnell , but this will cause the tests/drivers/flash cases failure on those board

@hakehuang , that test case fails from this known issue https://github.com/zephyrproject-rtos/zephyr/issues/88080.  And that test case tests the external QSPI flash, not the internal flash used with this PR.
author_association: NONE
user: login: hakehuang
created_at: 2025-05-16T07:46:51Z
body: > @hakehuang , that test case fails from this known issue #88080. And that test case tests the external QSPI flash, not the internal flash used with this PR.

board testing for system/subsys/nvs pass on v4.1.0-3814-g72ab204c80ac
author_association: CONTRIBUTOR
user: login: dleach02
created_at: 2025-05-21T18:34:53Z
body: @DerekSnell can you address the merge conflicts
author_association: MEMBER
user: login: DerekSnell
created_at: 2025-05-23T16:54:07Z
body: rebased to resolve merge conflicts.  Also added the MCXN547 SOC derivative from https://github.com/zephyrproject-rtos/zephyr/pull/89712 
author_association: NONE
user: login: DerekSnell
created_at: 2025-05-28T17:21:58Z
body: rebased to resolve CI test failures
author_association: NONE
user: login: hakehuang
created_at: 2025-05-30T04:19:13Z
body: board testing pass for 
•	board_list :['frdm_mcxn947/mcxn947/cpu0', 'mcx_n9xx_evk/mcxn947/cpu0']
•	commit_id :96a637c2aad472a8eaca077674b9a4b35e59335e
•	pull_id :89909
•	version :v4.1.0-4937-g96a637c2aad4

author_association: CONTRIBUTOR
user: login: dleach02
created_at: 2025-05-30T18:26:45Z
body: @DerekSnell your HAL PR was merged so I updated this one to have the new SHA
author_association: MEMBER
user: login: sonarqubecloud[bot]
created_at: 2025-05-30T19:19:33Z
body: ## [![Quality Gate Passed](https://sonarsource.github.io/sonarcloud-github-static-resources/v2/checks/QualityGateBadge/qg-passed-20px.png 'Quality Gate Passed')](https://sonarcloud.io/dashboard?id=zephyrproject-rtos_zephyr&pullRequest=89909) **Quality Gate passed**  
Issues  
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Measures  
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author_association: NONE