Repository: zephyrproject-rtos/zephyr
Pull request #86759: boards: intel: btl: Adds Bartlett Lake board 
Author: login: akanisetti
Labels: name: area: Watchdog
description: Watchdog
name: platform: X86
description: x86 and x86-64
Created: 2025-03-07T09:56:18Z | Merged: 2025-03-29T11:44:22Z

Added support for Bartlett lake board with
Raptorlake SOC

Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>


Diff:
diff --git a/boards/intel/btl/CMakeLists.txt b/boards/intel/btl/CMakeLists.txt
new file mode 100644
index 0000000000000..ee5e7343e8377
--- /dev/null
+++ b/boards/intel/btl/CMakeLists.txt
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Create an EFI image
+if(CONFIG_BUILD_OUTPUT_EFI)
+  set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+    COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/arch/x86/zefi/zefi.py
+    -c ${CMAKE_C_COMPILER}
+    -o ${CMAKE_OBJCOPY}
+    -i ${ZEPHYR_BASE}/include ${PROJECT_BINARY_DIR}/include/generated
+    -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf
+    $<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--verbose>
+    WORKING_DIRECTORY ${PROJECT_BINARY_DIR}
+  )
+endif()
diff --git a/boards/intel/btl/Kconfig.defconfig b/boards/intel/btl/Kconfig.defconfig
new file mode 100644
index 0000000000000..177c7c1f0d2ba
--- /dev/null
+++ b/boards/intel/btl/Kconfig.defconfig
@@ -0,0 +1,71 @@
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+
+config BUILD_OUTPUT_STRIPPED
+	default y
+
+config MP_MAX_NUM_CPUS
+	default 2
+
+# TSC on this board is 2.9 GHz, HPET is 19.2 MHz
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 2900000000 if APIC_TSC_DEADLINE_TIMER
+	default 2900000000 if APIC_TIMER_TSC
+	default 19200000
+
+if APIC_TIMER
+
+config APIC_TIMER_IRQ
+	default 24
+
+endif
+
+if APIC_TIMER_TSC
+
+config APIC_TIMER_TSC_M
+	default 3
+
+config APIC_TIMER_TSC_N
+	default 249
+
+endif
+
+config ACPI
+	default y
+
+if ACPI
+
+config HEAP_MEM_POOL_ADD_SIZE_ACPI
+	default 64000000
+
+config MAIN_STACK_SIZE
+	default 320000
+
+if SHELL
+
+config SHELL_STACK_SIZE
+	default 320000
+
+endif # SHELL
+
+endif # ACPI
+
+if DMA
+
+config DMA_64BIT
+	default y
+
+config DMA_DW_HW_LLI
+	default n
+
+config DMA_DW_CHANNEL_COUNT
+	default 2
+
+endif
+
+config UART_NS16550_INTEL_LPSS_DMA
+	default y if BOARD_INTEL_BTL_S_CRB
+
+config HAS_COVERAGE_SUPPORT
+	default y
diff --git a/boards/intel/btl/Kconfig.intel_btl_s_crb b/boards/intel/btl/Kconfig.intel_btl_s_crb
new file mode 100644
index 0000000000000..19f802f0c31cc
--- /dev/null
+++ b/boards/intel/btl/Kconfig.intel_btl_s_crb
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_INTEL_BTL_S_CRB
+	select SOC_RAPTOR_LAKE
diff --git a/boards/intel/btl/board.cmake b/boards/intel/btl/board.cmake
new file mode 100644
index 0000000000000..6b01bab2aeea8
--- /dev/null
+++ b/boards/intel/btl/board.cmake
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_set_flasher_ifnset(misc-flasher)
+board_finalize_runner_args(misc-flasher)
diff --git a/boards/intel/btl/board.yml b/boards/intel/btl/board.yml
new file mode 100644
index 0000000000000..f3b6dd2e2f81a
--- /dev/null
+++ b/boards/intel/btl/board.yml
@@ -0,0 +1,6 @@
+boards:
+  - name: intel_btl_s_crb
+    full_name: Bartlett Lake P CRB
+    vendor: intel
+    socs:
+      - name: raptor_lake
diff --git a/boards/intel/btl/doc/index.rst b/boards/intel/btl/doc/index.rst
new file mode 100644
index 0000000000000..dfe360e2bde01
--- /dev/null
+++ b/boards/intel/btl/doc/index.rst
@@ -0,0 +1,58 @@
+.. _intel_btl_s:
+
+Bartlett Lake S
+###############
+
+Overview
+********
+Bartlett Lake processor is a 64-bit multi-core processor built on Intel 7 process
+Technology. Bartlett Lake is based on a Hybrid architecture, utilizing
+P-cores for performance and E-Cores for efficiency.
+
+The S-Processor line is a 2-Chip Platform that includes the Processor Die and
+Platform Controller Hub (PCH-S) Die in the Package.
+
+For more information about Raptor Lake Processor lines, P-cores, and E-cores
+please refer to `BTL`_.
+
+This board configuration enables kernel support for the Bartlett Lake S boards.
+
+Hardware
+********
+
+General information about the board can be found at the `BTL`_ website.
+
+Connections and IOs
+===================
+
+Refer to the `BTL`_ website for more information.
+
+Programming and Debugging
+*************************
+Use the following procedures for booting an image for an Bartlett Lake S CRB board.
+
+.. contents::
+   :depth: 1
+   :local:
+   :backlinks: top
+
+Build Zephyr application
+========================
+
+#. Build a Zephyr application; for instance, to build the ``hello_world``
+   application for Bartlett Lake S CRB:
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/hello_world
+      :board: intel_btl_s_crb
+      :goals: build
+
+   .. note::
+
+      A Zephyr EFI image file named :file:`zephyr.efi` is automatically
+      created in the build directory after the application is built.
+
+.. include:: ../../../intel/common/efi_boot.rst
+   :start-after: start_include_here
+
+.. _BTL: https://www.intel.com/content/www/us/en/secure/content-details/839635/bartlett-lake-s-processor-external-design-specification-eds-for-edge-platforms.html?DocID=839635
diff --git a/boards/intel/btl/intel_btl_s_crb.dts b/boards/intel/btl/intel_btl_s_crb.dts
new file mode 100644
index 0000000000000..3ae2d4592c8df
--- /dev/null
+++ b/boards/intel/btl/intel_btl_s_crb.dts
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 Intel Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <mem.h>
+
+#define DT_DRAM_SIZE		DT_SIZE_M(2048)
+
+#include <intel/bartlett_lake_s.dtsi>
+
+/ {
+	model = "intel_btl_s_crb";
+	compatible = "intel,bartlett-lake-crb";
+
+	chosen {
+		zephyr,sram = &dram0;
+		zephyr,console = &uart_ec_0;
+		zephyr,shell-uart = &uart_ec_0;
+	};
+
+	aliases {
+		watchdog0 = &tco_wdt;
+		rtc = &rtc;
+	};
+};
+
+&uart_ec_0 {
+	status = "okay";
+};
+
+&rtc {
+	status = "okay";
+};
diff --git a/boards/intel/btl/intel_btl_s_crb.yaml b/boards/intel/btl/intel_btl_s_crb.yaml
new file mode 100644
index 0000000000000..a569213d394ae
--- /dev/null
+++ b/boards/intel/btl/intel_btl_s_crb.yaml
@@ -0,0 +1,15 @@
+identifier: intel_btl_s_crb
+name: Bartlett Lake S CRB
+type: mcu
+arch: x86
+toolchain:
+  - zephyr
+ram: 2048
+supported:
+  - acpi
+  - smp
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+vendor: intel
diff --git a/boards/intel/btl/intel_btl_s_crb_defconfig b/boards/intel/btl/intel_btl_s_crb_defconfig
new file mode 100644
index 0000000000000..853850deb12c5
--- /dev/null
+++ b/boards/intel/btl/intel_btl_s_crb_defconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_PIC_DISABLE=y
+CONFIG_LOAPIC=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_NS16550=y
+CONFIG_UART_NS16550_VARIANT_NS16750=y
+CONFIG_UART_CONSOLE=y
+CONFIG_X2APIC=y
+CONFIG_SMP=y
+CONFIG_BUILD_OUTPUT_EFI=y
diff --git a/dts/bindings/cpu/intel,bartlett-lake.yaml b/dts/bindings/cpu/intel,bartlett-lake.yaml
new file mode 100644
index 0000000000000..1e1c1880e5b39
--- /dev/null
+++ b/dts/bindings/cpu/intel,bartlett-lake.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel Bartlett Lake CPU
+
+compatible: "intel,bartlett-lake"
+
+include: cpu.yaml
diff --git a/dts/x86/intel/bartlett_lake_s.dtsi b/dts/x86/intel/bartlett_lake_s.dtsi
new file mode 100644
index 0000000000000..70f4df31e28c8
--- /dev/null
+++ b/dts/x86/intel/bartlett_lake_s.dtsi
@@ -0,0 +1,598 @@
+/*
+ * Copyright (c) 2025 Intel Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/pcie/pcie.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,bartlett-lake";
+			d-cache-line-size = <64>;
+			reg = <0>;
+		};
+	};
+
+	dram0: memory@0 {
+		device_type = "memory";
+		reg = <0x0 DT_DRAM_SIZE>;
+	};
+
+	intc: ioapic@fec00000  {
+		compatible = "intel,ioapic";
+		#address-cells = <1>;
+		#interrupt-cells = <3>;
+		reg = <0xfec00000 0x1000>;
+		interrupt-controller;
+	};
+
+	intc_loapic: loapic@fee00000  {
+		compatible = "intel,loapic";
+		reg = <0xfee00000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+	};
+
+	pcie0: pcie0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "pcie-controller";
+		acpi-hid = "PNP0A08";
+		ranges;
+
+		smbus0: smbus0 {
+			compatible = "intel,pch-smbus";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7aa3>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+
+			status = "disabled";
+		};
+
+		i2c0_dma: i2c0_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		i2c0: i2c0 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7acc>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c0_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c1_dma: i2c1_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		i2c1: i2c1 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7acd>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c1_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c2_dma: i2c2_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		i2c2: i2c2 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7ace>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c2_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c3_dma: i2c3_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		i2c3: i2c3 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7acf>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c3_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c4_dma: i2c4_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		i2c4: i2c4 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7afc>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c4_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c5_dma: i2c5_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		i2c5: i2c5 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7afd>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c5_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c6_dma: i2c6_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		i2c6: i2c6 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7ada>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c6_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c7_dma: i2c7_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		i2c7: i2c7 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7adb>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c7_dma 0>;
+
+			status = "disabled";
+		};
+
+		spi0: spi0 {
+			compatible = "intel,penwell-spi";
+			vendor-id = <0x8086>;
+			device-id = <0x7aaa>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pw,cs-mode = <0>;
+			pw,cs-output = <0>;
+			pw,fifo-depth = <64>;
+			cs-gpios = <&gpio_0_i 15 GPIO_ACTIVE_LOW>;
+			clock-frequency = <100000000>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+
+			status = "disabled";
+		};
+
+		spi1: spi1 {
+			compatible = "intel,penwell-spi";
+			vendor-id = <0x8086>;
+			device-id = <0x7aab>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pw,cs-mode = <0>;
+			pw,cs-output = <0>;
+			pw,fifo-depth = <64>;
+			cs-gpios = <&gpio_0_i 19 GPIO_ACTIVE_LOW>;
+			clock-frequency = <100000000>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+
+			status = "disabled";
+		};
+
+		spi2: spi2 {
+			compatible = "intel,penwell-spi";
+			vendor-id = <0x8086>;
+			device-id = <0x7afb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pw,cs-mode = <0>;
+			pw,cs-output = <0>;
+			pw,fifo-depth = <64>;
+			cs-gpios = <&gpio_0_r 12 GPIO_ACTIVE_LOW>;
+			clock-frequency = <100000000>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+
+			status = "disabled";
+		};
+
+		uart0_dma: uart0_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		uart0: uart0 {
+			compatible = "ns16550";
+			vendor-id = <0x8086>;
+			device-id = <0x7aa8>;
+			reg-shift = <2>;
+			clock-frequency = <1843200>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			current-speed = <115200>;
+			dmas = <&uart0_dma 0>, <&uart0_dma 1>;
+			dma-names = "tx", "rx";
+
+			status = "disabled";
+		};
+
+		uart1_dma: uart1_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		uart1: uart1 {
+			compatible = "ns16550";
+			vendor-id = <0x8086>;
+			device-id = <0x7aa9>;
+			reg-shift = <2>;
+			clock-frequency = <1843200>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			current-speed = <115200>;
+			dmas = <&uart1_dma 0>, <&uart1_dma 1>;
+			dma-names = "tx", "rx";
+
+			status = "disabled";
+		};
+
+		uart2: uart2 {
+			compatible = "ns16550";
+			vendor-id = <0x8086>;
+			device-id = <0x7afe>;
+			reg-shift = <2>;
+			clock-frequency = <1843200>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			current-speed = <115200>;
+
+			status = "disabled";
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		vtd: vtd@fed91000 {
+			compatible = "intel,vt-d";
+			reg = <0xfed91000 0x1000>;
+
+			status = "okay";
+		};
+
+		uart_ec_0: uart@3f8 {
+			compatible = "ns16550";
+			reg = <0x000003f8 0x100>;
+			io-mapped;
+			clock-frequency = <1843200>;
+			interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
+			interrupt-parent = <&intc>;
+			reg-shift = <0>;
+			io-mapped;
+
+			status = "disabled";
+		};
+
+		gpio_0_i: gpio@e06e0700 {
+			compatible = "intel,gpio";
+			reg = <0xe06e0700 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <23>;
+			pin-offset = <0>;
+
+			status = "disabled";
+		};
+
+		gpio_0_r: gpio@e06e0890 {
+			compatible = "intel,gpio";
+			reg = <0xe06e0890 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <22>;
+			pin-offset = <26>;
+
+			status = "disabled";
+		};
+
+		gpio_0_j: gpio@e06e0a00 {
+			compatible = "intel,gpio";
+			reg = <0xe06e0a00 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <12>;
+			pin-offset = <49>;
+
+			status = "disabled";
+		};
+
+		gpio_1_b: gpio@e06d0700 {
+			compatible = "intel,gpio";
+			reg = <0xe06d0700 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <24>;
+			pin-offset = <0>;
+
+			status = "disabled";
+		};
+
+		gpio_1_g: gpio@e06d0880 {
+			compatible = "intel,gpio";
+			reg = <0xe06d0880 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin-offset = <24>;
+
+			status = "disabled";
+		};
+
+		gpio_1_h: gpio@e06d0900 {
+			compatible = "intel,gpio";
+			reg = <0xe06d0900 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <24>;
+			pin-offset = <32>;
+
+			status = "disabled";
+		};
+
+		gpio_3_a: gpio@e06b0790 {
+			compatible = "intel,gpio";
+			reg = <0xe06b0790 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <15>;
+			pin-offset = <9>;
+
+			status = "disabled";
+		};
+
+		gpio_3_c: gpio@e06b0890 {
+			compatible = "intel,gpio";
+			reg = <0xe06b0890 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <24>;
+			pin-offset = <25>;
+
+			status = "disabled";
+		};
+
+		gpio_4_s: gpio@e06a0700 {
+			compatible = "intel,gpio";
+			reg = <0xe06a0700 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin-offset = <0>;
+
+			status = "disabled";
+		};
+
+		gpio_4_e: gpio@e06a0780 {
+			compatible = "intel,gpio";
+			reg = <0xe06a0780 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <22>;
+			pin-offset = <8>;
+
+			status = "disabled";
+		};
+
+		gpio_4_k: gpio@e06a08f0 {
+			compatible = "intel,gpio";
+			reg = <0xe06a08f0 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <12>;
+			pin-offset = <25>;
+
+			status = "disabled";
+		};
+
+		gpio_4_f: gpio@e06a09e0 {
+			compatible = "intel,gpio";
+			reg = <0xe06a09e0 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x3>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <24>;
+			pin-offset = <41>;
+
+			status = "disabled";
+		};
+
+		gpio_5_d: gpio@e0690700 {
+			compatible = "intel,gpio";
+			reg = <0xe0690700 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <24>;
+			pin-offset = <0>;
+
+			status = "disabled";
+		};
+
+		pwm0: pwm@e06a0000 {
+			compatible = "intel,blinky-pwm";
+			reg = <0xe06a0000 0x400>;
+			reg-offset = <0x304>;
+			clock-frequency = <32768>;
+			max-pins = <1>;
+			#pwm-cells = <2>;
+
+			status = "disabled";
+		};
+
+		rtc: counter: rtc@70 {
+			compatible = "motorola,mc146818";
+			reg = <0x70 0x0D 0x71 0x0D>;
+			interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
+			interrupt-parent = <&intc>;
+			alarms-count = <1>;
+
+			status = "disabled";
+		};
+
+		tgpio: tgpio@fe001200 {
+			compatible = "intel,timeaware-gpio";
+			reg = <0xfe001200 0x100>;
+			timer-clock = <19200000>;
+			max-pins = <2>;
+
+			status = "disabled";
+		};
+
+		hpet: hpet@fed00000 {
+			compatible = "intel,hpet";
+			reg = <0xfed00000 0x400>;
+			interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
+			interrupt-parent = <&intc>;
+
+			status = "disabled";
+		};
+
+		tco_wdt: tco_wdt@400 {
+			compatible = "intel,tco-wdt";
+			reg = <0x0400 0x20>;
+
+			status = "disabled";
+		};
+	};
+};
diff --git a/soc/intel/raptor_lake/soc_gpio.h b/soc/intel/raptor_lake/soc_gpio.h
index 6901cab92211f..79db43a7e7d2d 100644
--- a/soc/intel/raptor_lake/soc_gpio.h
+++ b/soc/intel/raptor_lake/soc_gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, Intel Corporation
+ * Copyright (c) 2023-2025, Intel Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,7 +15,7 @@
 #ifndef __SOC_GPIO_H_
 #define __SOC_GPIO_H_
 
-#if defined(CONFIG_BOARD_INTEL_RPL_S_CRB)
+#if defined(CONFIG_BOARD_INTEL_RPL_S_CRB) || defined(CONFIG_BOARD_INTEL_BTL_S_CRB)
 #define GPIO_INTEL_NR_SUBDEVS		13
 #define REG_PAD_OWNER_BASE		0x00A0
 #define REG_GPI_INT_STS_BASE		0x0200


Reviews:
user: login: nordicjm
state: CHANGES_REQUESTED
author_association: CONTRIBUTOR
submitted_at: 2025-03-07T10:22:24Z
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submitted_at: 2025-03-07T11:07:54Z
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submitted_at: 2025-03-07T11:08:41Z
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submitted_at: 2025-03-07T11:40:29Z
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submitted_at: 2025-03-07T12:02:36Z
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submitted_at: 2025-03-25T17:27:39Z

Review comments:
diff_hunk: @@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+
path: boards/intel/btl/CMakeLists.txt
user: login: nordicjm
body: soc commit before board commit
created_at: 2025-03-07T10:16:15Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Create an EFI image
+if(CONFIG_BUILD_OUTPUT_EFI)
+set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+  COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py
path: boards/intel/btl/CMakeLists.txt
user: login: nordicjm
body: ZEPHYR_BASE?
created_at: 2025-03-07T10:17:07Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Create an EFI image
+if(CONFIG_BUILD_OUTPUT_EFI)
+set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
path: boards/intel/btl/CMakeLists.txt
user: login: nordicjm
body: indent
created_at: 2025-03-07T10:17:12Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,56 @@
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+
+config BUILD_OUTPUT_STRIPPED
+	default y
+
+config MP_MAX_NUM_CPUS
+	default 2
+
+# TSC on this board is 2.9 GHz, HPET is 19.2 MHz
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 2900000000 if APIC_TSC_DEADLINE_TIMER
+	default 2900000000 if APIC_TIMER_TSC
+	default 19200000
+
+if APIC_TIMER
+config APIC_TIMER_IRQ
+	default 24
+endif
path: boards/intel/btl/Kconfig.defconfig
user: login: nordicjm
body: ```suggestion
if APIC_TIMER

config APIC_TIMER_IRQ
	default 24

endif
```
fix styling throughout
created_at: 2025-03-07T10:18:18Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,580 @@
+/*
+ * Copyright (c) 2025 Intel Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/pcie/pcie.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,bartlett-lake";
+			d-cache-line-size = <64>;
+			reg = <0>;
+		};
+
path: dts/x86/intel/bartlett_lake_s.dtsi
user: login: nordicjm
body: ```suggestion
```
created_at: 2025-03-07T10:19:44Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,580 @@
+/*
+ * Copyright (c) 2025 Intel Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/pcie/pcie.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,bartlett-lake";
+			d-cache-line-size = <64>;
+			reg = <0>;
+		};
+
+	};
+
+	dram0: memory@0 {
+		device_type = "memory";
+		reg = <0x0 DT_DRAM_SIZE>;
+	};
+
+	intc: ioapic@fec00000  {
+		compatible = "intel,ioapic";
+		#address-cells = <1>;
+		#interrupt-cells = <3>;
+		reg = <0xfec00000 0x1000>;
+		interrupt-controller;
+	};
+
+	intc_loapic: loapic@fee00000  {
+		compatible = "intel,loapic";
+		reg = <0xfee00000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+	};
+
+	pcie0: pcie0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "pcie-controller";
+		acpi-hid = "PNP0A08";
+		ranges;
+
+		smbus0: smbus0 {
+			compatible = "intel,pch-smbus";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7aa3>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+
+			status = "okay";
path: dts/x86/intel/bartlett_lake_s.dtsi
user: login: nordicjm
body: disabled
created_at: 2025-03-07T10:20:19Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,580 @@
+/*
+ * Copyright (c) 2025 Intel Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/pcie/pcie.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,bartlett-lake";
+			d-cache-line-size = <64>;
+			reg = <0>;
+		};
+
+	};
+
+	dram0: memory@0 {
+		device_type = "memory";
+		reg = <0x0 DT_DRAM_SIZE>;
+	};
+
+	intc: ioapic@fec00000  {
+		compatible = "intel,ioapic";
+		#address-cells = <1>;
+		#interrupt-cells = <3>;
+		reg = <0xfec00000 0x1000>;
+		interrupt-controller;
+	};
+
+	intc_loapic: loapic@fee00000  {
+		compatible = "intel,loapic";
+		reg = <0xfee00000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+	};
+
+	pcie0: pcie0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "pcie-controller";
path: dts/x86/intel/bartlett_lake_s.dtsi
user: login: nordicjm
body: disabled
created_at: 2025-03-07T10:20:23Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,580 @@
+/*
+ * Copyright (c) 2025 Intel Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/pcie/pcie.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,bartlett-lake";
+			d-cache-line-size = <64>;
+			reg = <0>;
+		};
+
+	};
+
+	dram0: memory@0 {
+		device_type = "memory";
+		reg = <0x0 DT_DRAM_SIZE>;
+	};
+
+	intc: ioapic@fec00000  {
+		compatible = "intel,ioapic";
+		#address-cells = <1>;
+		#interrupt-cells = <3>;
+		reg = <0xfec00000 0x1000>;
+		interrupt-controller;
+	};
+
+	intc_loapic: loapic@fee00000  {
+		compatible = "intel,loapic";
+		reg = <0xfee00000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+	};
+
+	pcie0: pcie0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "pcie-controller";
+		acpi-hid = "PNP0A08";
+		ranges;
+
+		smbus0: smbus0 {
+			compatible = "intel,pch-smbus";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7aa3>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+
+			status = "okay";
+		};
+
+		i2c0_dma: i2c0_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "okay";
path: dts/x86/intel/bartlett_lake_s.dtsi
user: login: nordicjm
body: disabled
created_at: 2025-03-07T10:20:29Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,580 @@
+/*
+ * Copyright (c) 2025 Intel Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/pcie/pcie.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,bartlett-lake";
+			d-cache-line-size = <64>;
+			reg = <0>;
+		};
+
+	};
+
+	dram0: memory@0 {
+		device_type = "memory";
+		reg = <0x0 DT_DRAM_SIZE>;
+	};
+
+	intc: ioapic@fec00000  {
+		compatible = "intel,ioapic";
+		#address-cells = <1>;
+		#interrupt-cells = <3>;
+		reg = <0xfec00000 0x1000>;
+		interrupt-controller;
+	};
+
+	intc_loapic: loapic@fee00000  {
+		compatible = "intel,loapic";
+		reg = <0xfee00000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+	};
+
+	pcie0: pcie0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "pcie-controller";
+		acpi-hid = "PNP0A08";
+		ranges;
+
+		smbus0: smbus0 {
+			compatible = "intel,pch-smbus";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7aa3>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+
+			status = "okay";
+		};
+
+		i2c0_dma: i2c0_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "okay";
+		};
+
+		i2c0: i2c0 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7acc>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c0_dma 0>;
+
+			status = "okay";
path: dts/x86/intel/bartlett_lake_s.dtsi
user: login: nordicjm
body: disabled
created_at: 2025-03-07T10:20:34Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,580 @@
+/*
+ * Copyright (c) 2025 Intel Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/pcie/pcie.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,bartlett-lake";
+			d-cache-line-size = <64>;
+			reg = <0>;
+		};
+
+	};
+
+	dram0: memory@0 {
+		device_type = "memory";
+		reg = <0x0 DT_DRAM_SIZE>;
+	};
+
+	intc: ioapic@fec00000  {
+		compatible = "intel,ioapic";
+		#address-cells = <1>;
+		#interrupt-cells = <3>;
+		reg = <0xfec00000 0x1000>;
+		interrupt-controller;
+	};
+
+	intc_loapic: loapic@fee00000  {
+		compatible = "intel,loapic";
+		reg = <0xfee00000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+	};
+
+	pcie0: pcie0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "pcie-controller";
+		acpi-hid = "PNP0A08";
+		ranges;
+
+		smbus0: smbus0 {
+			compatible = "intel,pch-smbus";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7aa3>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+
+			status = "okay";
+		};
+
+		i2c0_dma: i2c0_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "okay";
+		};
+
+		i2c0: i2c0 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7acc>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c0_dma 0>;
+
+			status = "okay";
+		};
+
+		i2c1_dma: i2c1_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c1: i2c1 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7acd>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c1_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c2_dma: i2c2_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c2: i2c2 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7ace>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c2_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c3_dma: i2c3_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c3: i2c3 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7acf>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c3_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c4_dma: i2c4_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c4: i2c4 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7afc>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c4_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c5_dma: i2c5_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c5: i2c5 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7afd>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c5_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c6_dma: i2c6_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c6: i2c6 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7ada>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c6_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c7_dma: i2c7_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c7: i2c7 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7adb>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c7_dma 0>;
+
+			status = "disabled";
+		};
+
+		spi0: spi0 {
+			compatible = "intel,penwell-spi";
+			vendor-id = <0x8086>;
+			device-id = <0x7aaa>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pw,cs-mode = <0>;
+			pw,cs-output = <0>;
+			pw,fifo-depth = <64>;
+			cs-gpios = <&gpio_0_i 15 GPIO_ACTIVE_LOW>;
+			clock-frequency = <100000000>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			status = "okay";
path: dts/x86/intel/bartlett_lake_s.dtsi
user: login: nordicjm
body: disabled
created_at: 2025-03-07T10:20:40Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,580 @@
+/*
+ * Copyright (c) 2025 Intel Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/pcie/pcie.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,bartlett-lake";
+			d-cache-line-size = <64>;
+			reg = <0>;
+		};
+
+	};
+
+	dram0: memory@0 {
+		device_type = "memory";
+		reg = <0x0 DT_DRAM_SIZE>;
+	};
+
+	intc: ioapic@fec00000  {
+		compatible = "intel,ioapic";
+		#address-cells = <1>;
+		#interrupt-cells = <3>;
+		reg = <0xfec00000 0x1000>;
+		interrupt-controller;
+	};
+
+	intc_loapic: loapic@fee00000  {
+		compatible = "intel,loapic";
+		reg = <0xfee00000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+	};
+
+	pcie0: pcie0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "pcie-controller";
+		acpi-hid = "PNP0A08";
+		ranges;
+
+		smbus0: smbus0 {
+			compatible = "intel,pch-smbus";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7aa3>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+
+			status = "okay";
+		};
+
+		i2c0_dma: i2c0_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "okay";
+		};
+
+		i2c0: i2c0 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7acc>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c0_dma 0>;
+
+			status = "okay";
+		};
+
+		i2c1_dma: i2c1_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c1: i2c1 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7acd>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c1_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c2_dma: i2c2_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c2: i2c2 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7ace>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c2_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c3_dma: i2c3_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c3: i2c3 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7acf>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c3_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c4_dma: i2c4_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c4: i2c4 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7afc>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c4_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c5_dma: i2c5_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c5: i2c5 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7afd>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c5_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c6_dma: i2c6_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c6: i2c6 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7ada>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c6_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c7_dma: i2c7_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c7: i2c7 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7adb>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c7_dma 0>;
+
+			status = "disabled";
+		};
+
+		spi0: spi0 {
+			compatible = "intel,penwell-spi";
+			vendor-id = <0x8086>;
+			device-id = <0x7aaa>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pw,cs-mode = <0>;
+			pw,cs-output = <0>;
+			pw,fifo-depth = <64>;
+			cs-gpios = <&gpio_0_i 15 GPIO_ACTIVE_LOW>;
+			clock-frequency = <100000000>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			status = "okay";
+		};
+
+		spi1: spi1 {
+			compatible = "intel,penwell-spi";
+			vendor-id = <0x8086>;
+			device-id = <0x7aab>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pw,cs-mode = <0>;
+			pw,cs-output = <0>;
+			pw,fifo-depth = <64>;
+			cs-gpios = <&gpio_0_i 19 GPIO_ACTIVE_LOW>;
+			clock-frequency = <100000000>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			status = "disabled";
+		};
+
+		spi2: spi2 {
+			compatible = "intel,penwell-spi";
+			vendor-id = <0x8086>;
+			device-id = <0x7afb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pw,cs-mode = <0>;
+			pw,cs-output = <0>;
+			pw,fifo-depth = <64>;
+			cs-gpios = <&gpio_0_r 12 GPIO_ACTIVE_LOW>;
+			clock-frequency = <100000000>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			status = "disabled";
+		};
+
+		uart0_dma: uart0_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		uart0: uart0 {
+			compatible = "ns16550";
+			vendor-id = <0x8086>;
+			device-id = <0x7aa8>;
+			reg-shift = <2>;
+			clock-frequency = <1843200>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			current-speed = <115200>;
+			dmas = <&uart0_dma 0>, <&uart0_dma 1>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		uart1_dma: uart1_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		uart1: uart1 {
+			compatible = "ns16550";
+			vendor-id = <0x8086>;
+			device-id = <0x7aa9>;
+			reg-shift = <2>;
+			clock-frequency = <1843200>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			current-speed = <115200>;
+			dmas = <&uart1_dma 0>, <&uart1_dma 1>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		uart2: uart2 {
+			compatible = "ns16550";
+			vendor-id = <0x8086>;
+			device-id = <0x7afe>;
+			reg-shift = <2>;
+			clock-frequency = <1843200>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			current-speed = <115200>;
+			status = "disabled";
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		vtd: vtd@fed91000 {
+			compatible = "intel,vt-d";
+			reg = <0xfed91000 0x1000>;
+
+			status = "okay";
+		};
+
+		uart_ec_0: uart@3f8 {
+			compatible = "ns16550";
+			reg = <0x000003f8 0x100>;
+			io-mapped;
+			clock-frequency = <1843200>;
+			interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
+			interrupt-parent = <&intc>;
+			reg-shift = <0>;
+			io-mapped;
+			status = "okay";
path: dts/x86/intel/bartlett_lake_s.dtsi
user: login: nordicjm
body: disabled
created_at: 2025-03-07T10:20:49Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,580 @@
+/*
+ * Copyright (c) 2025 Intel Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/pcie/pcie.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,bartlett-lake";
+			d-cache-line-size = <64>;
+			reg = <0>;
+		};
+
+	};
+
+	dram0: memory@0 {
+		device_type = "memory";
+		reg = <0x0 DT_DRAM_SIZE>;
+	};
+
+	intc: ioapic@fec00000  {
+		compatible = "intel,ioapic";
+		#address-cells = <1>;
+		#interrupt-cells = <3>;
+		reg = <0xfec00000 0x1000>;
+		interrupt-controller;
+	};
+
+	intc_loapic: loapic@fee00000  {
+		compatible = "intel,loapic";
+		reg = <0xfee00000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+	};
+
+	pcie0: pcie0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "pcie-controller";
+		acpi-hid = "PNP0A08";
+		ranges;
+
+		smbus0: smbus0 {
+			compatible = "intel,pch-smbus";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7aa3>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+
+			status = "okay";
+		};
+
+		i2c0_dma: i2c0_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "okay";
+		};
+
+		i2c0: i2c0 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7acc>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c0_dma 0>;
+
+			status = "okay";
+		};
+
+		i2c1_dma: i2c1_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c1: i2c1 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7acd>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c1_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c2_dma: i2c2_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c2: i2c2 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7ace>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c2_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c3_dma: i2c3_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c3: i2c3 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7acf>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c3_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c4_dma: i2c4_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c4: i2c4 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7afc>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c4_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c5_dma: i2c5_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c5: i2c5 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7afd>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c5_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c6_dma: i2c6_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c6: i2c6 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7ada>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c6_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c7_dma: i2c7_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		i2c7: i2c7 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7adb>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c7_dma 0>;
+
+			status = "disabled";
+		};
+
+		spi0: spi0 {
+			compatible = "intel,penwell-spi";
+			vendor-id = <0x8086>;
+			device-id = <0x7aaa>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pw,cs-mode = <0>;
+			pw,cs-output = <0>;
+			pw,fifo-depth = <64>;
+			cs-gpios = <&gpio_0_i 15 GPIO_ACTIVE_LOW>;
+			clock-frequency = <100000000>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			status = "okay";
+		};
+
+		spi1: spi1 {
+			compatible = "intel,penwell-spi";
+			vendor-id = <0x8086>;
+			device-id = <0x7aab>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pw,cs-mode = <0>;
+			pw,cs-output = <0>;
+			pw,fifo-depth = <64>;
+			cs-gpios = <&gpio_0_i 19 GPIO_ACTIVE_LOW>;
+			clock-frequency = <100000000>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			status = "disabled";
+		};
+
+		spi2: spi2 {
+			compatible = "intel,penwell-spi";
+			vendor-id = <0x8086>;
+			device-id = <0x7afb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pw,cs-mode = <0>;
+			pw,cs-output = <0>;
+			pw,fifo-depth = <64>;
+			cs-gpios = <&gpio_0_r 12 GPIO_ACTIVE_LOW>;
+			clock-frequency = <100000000>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			status = "disabled";
+		};
+
+		uart0_dma: uart0_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		uart0: uart0 {
+			compatible = "ns16550";
+			vendor-id = <0x8086>;
+			device-id = <0x7aa8>;
+			reg-shift = <2>;
+			clock-frequency = <1843200>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			current-speed = <115200>;
+			dmas = <&uart0_dma 0>, <&uart0_dma 1>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		uart1_dma: uart1_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		uart1: uart1 {
+			compatible = "ns16550";
+			vendor-id = <0x8086>;
+			device-id = <0x7aa9>;
+			reg-shift = <2>;
+			clock-frequency = <1843200>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			current-speed = <115200>;
+			dmas = <&uart1_dma 0>, <&uart1_dma 1>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		uart2: uart2 {
+			compatible = "ns16550";
+			vendor-id = <0x8086>;
+			device-id = <0x7afe>;
+			reg-shift = <2>;
+			clock-frequency = <1843200>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			current-speed = <115200>;
+			status = "disabled";
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		vtd: vtd@fed91000 {
+			compatible = "intel,vt-d";
+			reg = <0xfed91000 0x1000>;
+
+			status = "okay";
+		};
+
+		uart_ec_0: uart@3f8 {
+			compatible = "ns16550";
+			reg = <0x000003f8 0x100>;
+			io-mapped;
+			clock-frequency = <1843200>;
+			interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
+			interrupt-parent = <&intc>;
+			reg-shift = <0>;
+			io-mapped;
+			status = "okay";
+		};
+
+		gpio_0_i: gpio@e06e0700 {
+			compatible = "intel,gpio";
+			reg = <0xe06e0700 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <23>;
+			pin-offset = <0>;
+
+			status = "okay";
path: dts/x86/intel/bartlett_lake_s.dtsi
user: login: nordicjm
body: instead of commenting them all, all peripherals should be disabled in base dts file 
created_at: 2025-03-07T10:22:21Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+
path: boards/intel/btl/CMakeLists.txt
user: login: akanisetti
body: Board Config used in soc commit is from board definition, so I added board first and then added soc changes for the board.
created_at: 2025-03-07T11:07:54Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Create an EFI image
+if(CONFIG_BUILD_OUTPUT_EFI)
+set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+  COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py
path: boards/intel/btl/CMakeLists.txt
user: login: akanisetti
body: Explanation please
created_at: 2025-03-07T11:08:41Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Create an EFI image
+if(CONFIG_BUILD_OUTPUT_EFI)
+set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+  COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py
path: boards/intel/btl/CMakeLists.txt
user: login: nordicjm
body: `PROJECT_SOURCE_DIR` is the path from `project()`, it should be `ZEPHYR_BASE` since this is a zephyr file
created_at: 2025-03-07T11:40:29Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Create an EFI image
+if(CONFIG_BUILD_OUTPUT_EFI)
+set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+  COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py
path: boards/intel/btl/CMakeLists.txt
user: login: nashif
body: @nordicjm 

> ZEPHYR_BASE?

This type of feedback is very unhelpful, please spend some time explaining what you are asking for. Not everyone understands what you mean and why this might be a problem. 

https://docs.zephyrproject.org/latest/contribute/reviewer_expectations.html#:~:text=Reviewers%20shall%20be,request%20for%20changes.
created_at: 2025-03-07T12:02:36Z
author_association: MEMBER
diff_hunk: @@ -0,0 +1,580 @@
+/*
+ * Copyright (c) 2025 Intel Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/pcie/pcie.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,bartlett-lake";
+			d-cache-line-size = <64>;
+			reg = <0>;
+		};
+
+	};
+
+	dram0: memory@0 {
+		device_type = "memory";
+		reg = <0x0 DT_DRAM_SIZE>;
+	};
+
+	intc: ioapic@fec00000  {
+		compatible = "intel,ioapic";
+		#address-cells = <1>;
+		#interrupt-cells = <3>;
+		reg = <0xfec00000 0x1000>;
+		interrupt-controller;
+	};
+
+	intc_loapic: loapic@fee00000  {
+		compatible = "intel,loapic";
+		reg = <0xfee00000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+	};
+
+	pcie0: pcie0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "pcie-controller";
+		acpi-hid = "PNP0A08";
+		ranges;
+
+		smbus0: smbus0 {
+			compatible = "intel,pch-smbus";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7aa3>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+
+			status = "okay";
+		};
+
+		i2c0_dma: i2c0_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+			status = "okay";
path: dts/x86/intel/bartlett_lake_s.dtsi
user: login: nashif
body: @nordicjm 

> disabled

This type of feedback is very unhelpful, please spend some time explaining what you are asking for. Not everyone understands what you mean and why this might be a problem. 

https://docs.zephyrproject.org/latest/contribute/reviewer_expectations.html#:~:text=Reviewers%20shall%20be,request%20for%20changes.
created_at: 2025-03-07T12:03:11Z
author_association: MEMBER
diff_hunk: @@ -0,0 +1,580 @@
+/*
+ * Copyright (c) 2025 Intel Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/pcie/pcie.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,bartlett-lake";
+			d-cache-line-size = <64>;
+			reg = <0>;
+		};
+
+	};
+
+	dram0: memory@0 {
+		device_type = "memory";
+		reg = <0x0 DT_DRAM_SIZE>;
+	};
+
+	intc: ioapic@fec00000  {
+		compatible = "intel,ioapic";
+		#address-cells = <1>;
+		#interrupt-cells = <3>;
+		reg = <0xfec00000 0x1000>;
+		interrupt-controller;
+	};
+
+	intc_loapic: loapic@fee00000  {
+		compatible = "intel,loapic";
+		reg = <0xfee00000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+	};
+
+	pcie0: pcie0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "pcie-controller";
+		acpi-hid = "PNP0A08";
+		ranges;
+
+		smbus0: smbus0 {
+			compatible = "intel,pch-smbus";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7aa3>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+
+			status = "okay";
path: dts/x86/intel/bartlett_lake_s.dtsi
user: login: nashif
body: @nordicjm  why does this need to be disabled?
created_at: 2025-03-07T12:21:08Z
author_association: MEMBER
diff_hunk: @@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Create an EFI image
+if(CONFIG_BUILD_OUTPUT_EFI)
+set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
path: boards/intel/btl/CMakeLists.txt
user: login: nordicjm
body: not addressed
created_at: 2025-03-11T07:48:06Z
author_association: CONTRIBUTOR
diff_hunk: @@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Create an EFI image
+if(CONFIG_BUILD_OUTPUT_EFI)
+set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
path: boards/intel/btl/CMakeLists.txt
user: login: akanisetti
body: missed it, now addressed.
created_at: 2025-03-11T08:01:00Z
author_association: CONTRIBUTOR

PR comments:
user: login: edersondisouza
created_at: 2025-03-21T00:35:49Z
body: @akanisetti guess this needs rebase, right?
author_association: CONTRIBUTOR
user: login: edersondisouza
created_at: 2025-03-25T17:30:21Z
body: Hmmm...it seems still need to solve the `%d` issue.
author_association: CONTRIBUTOR
user: login: akanisetti
created_at: 2025-03-26T03:07:44Z
body: > Hmmm...it seems still need to solve the `%d` issue.

Yes, I am trying to solve it by using unsigned int for frequency in the following PR (#87553 87553). It is almost ready, once it gets approved this issue will be resolved. 
author_association: CONTRIBUTOR