bluuebunny/crossref_metadata_2025_split huggingface dataset:
Burn-in-Testing (BIT) Challenge: to BIT or not to BIT?
Authors: Suhir E. 
Published: February 2022

Abstract
Burn-in testing (BIT) is a costly undertaking. Predictive modeling enables shading useful light on what and how should be tested, if at all. Three analytical (“mathematical”) predictive models recently suggested by the author are addressed in this mini-review: 1) A model based on the analysis of the infant mortality portion (IMP) of the bathtub curve (BTC) suggests that the non-random time derivative of the expected “statistical” failure rate (SFR) at the beginning of the IMP could be viewed as a suitable criterion (“figure of merit”) to answer the basic question of the BIT undertaking: “to BIT or not to BIT?” 2) A model based on the analysis of the random failure rate (RFR) of the mass-produced components that the manufactured product of interest is comprised of suggests that the above derivative is, in effect, the RFR variance of these components. 3) A model based on the use of the kinetic multi-parametric Boltzmann-Arrhenius-Zhurkov (BAZ) constitutive equation is employed to establish the BIT's adequate duration and level, if this kind of failure-oriented-accelerated-testing (FOAT) is found to be necessary. The theoretical findings are illustrated by calculated data. It is concluded that predictive modeling should always precede the actual BIT, that analytical modeling should always complement computer simulations and that future work should address the experimental validation and possible extension of the obtained results and recommendations.
State-of-the-Art and Outlooks of Chiplets Heterogeneous Integration and Hybrid Bonding
Authors: Lau John H 
Published: February 2022

Abstract
In this study, the recent advances and trends of chiplet design and heterogeneous integration packaging will be investigated. Emphasis is placed on the definition, kinds, advantages and disadvantages, lateral interconnects, and examples of chiplet design and heterogeneous integration packaging. Also, emphasis is placed on the fundamental and examples of hybrid bonding.
High-Accuracy Pick-and-Place of Multiple Dies in Parallel Assisted by Capillary Self-Alignment
Authors: Brandstätter Birgit , Auer Benedikt , Klingler Hannes , Scherbaum Sabine 
Published: February 2022

Abstract
Self-assembly of components driven by liquid surface tension is an attractive complement and even alternative to traditional high-accuracy pick-and-place as it offers high accuracy despite inaccurate robotic part placement. While capillary self-alignment through liquid solder is the standard technology for flip-chip processes, this work presents self-alignment of dies on wetted receptors on a temporary carrier: Low-viscosity liquid is jetted on each receptor where the liquid is contained through generation of hydrophilic and hydrophobic sections on the temporary carrier by plasma treatment. Deterministic die feeding by low-accuracy pick-and-place is conducted for single dies, as well as for batches of three dies and nine dies optimizing the equipment for best throughput to achieve both high accuracy and high productivity. The industry-ready and fully automated chip-to-wafer pick-and-place process is implemented into a fan-out wafer-level packaging production flow proving that self-alignment is capable of easing the stringent requirement for robotic alignment capability for pick-and-place systems in fan-out packaging for the single die-level step in this production chain. The self-alignment process is optimized, and failure modes such as poor liquid confinement, surface contamination, or excess force are identified and eliminated. Post-bond accuracy of &lt;3 μm @ 3 σ at each point of the die is reached for dies of 3.1 mm x 3.1 mm in size. Using parallel die handling, high speeds of around 10 000 units per hour are made possible.
Advanced Protected Fan-In WLCSP
Authors: Hackler Doug , Prack Ed 
Published: February 2022

ABSTRACT
With the advent of bumped die new IC packages evolved: for low IO WLCSP (wafer level chip scale package), for high IO FC (flip chip) CBGA (ceramic ball grid array) and PBGA (plastic ball grid array). For low IO, protected CSP is an emerging and rapidly growing market. In 2020 the market exceeded $2B and is ramping to a forecast $2.5B by 2025.1 Initially WLCSP, also known as FI (fan in), packages were built on the wafer with no active side protection evolving to single sided protection from a package built on the wafer2 which transition to redistribution PSB (passivation stress buffer)3, PSBs were used on FC wafers for high IO BGA packages. These provided acceptable performance initially, however as devices became more complex and reliability requirements increased, these processes no longer provided the required reliability. To attain higher IO capability and better reliability performance evolved to CSP4 (non-WL) which allowed larger area for bump distribution and additional protection to the rest of the exposed die surfaces. Fully protected die CSP (without substrates or leadframes) was initially implemented with processes such as M-series utilizing a FO (fan out) process.5 To obtain higher reliability 6-sided die protection afforded by M-series type processes require die reconstitution, expensive tapes, molding, and other operations generally required in a FO process which can feasibly be eliminated in a WLCSP protected FI process. American Semiconductor's Semiconductor-on-Polymer™ (SoP™) 300mm FleX-TM WLCSP is an advanced packaging process optimized for protected fan-in. FleX-TM produces the thinnest and lowest cost protected FI the industry today. Protected FI process innovations can improve performance in power devices, RF switches, die stacking and thin board applications. This article includes background on the evolution of CSP and the comparison of SOTA (state of the art) FI processes including FleX-TM.
Structured glass substrates in wafer- and panel level packaging: Status and recent achievements.
Authors: Letz M. , Gotschke T. , Wagner F. , Heiss-Chouquet M. , Müller L. , Peuchert U. , Vanderpool D. 
Published: February 2022

Abstract
Glasses can be used as core substrate for panel- and/or wafer-level packaging to achieve heterogeneous integration of chiplets and integrated passives in increasingly complex packages. Glass has a large number of advantages: The stiffness of glass (i) allows manufacturing of highly accurate buildup layers. These buildup layers can have manufacturing precision of 1μm and below on large dies with sizes of 50mm x 50mm and more, needed for antenna in package (AiP) applications and high performance computing (HPC). Special glasses can be made with adjusted thermal expansion (CTE) (ii), either adjusted to silicon or with larger thermal expansion to allow packages with buildup layers of epoxy molds and metallization that see high thermal loads either during manufacturing or during operation. Glasses can also be optimized with very good dielectric properties (iii) and can be utilized in antenna-in-package applications. But most of all, economic glass structuring techniques (iv) which can provide millions of vias and thousands of cut-outs in a glass panel are important and are being developed. SCHOTTs Structured Glass Portfolio FLEXINITY® and related technologies provide an excellent starting point for highly sophisticated structured glass substrates required for Advanced Packaging. The biggest hurdle for a large-scale commercialization of glass panel packaging is industrial readiness along the whole process chain. This is needed, to bring glass panel packaging in applications like IC-packaging, RF-MEMS packaging and medical diagnostics or, in combination with cutouts for fan-out, embedding of active and passive components. In addition, metallization processes with good adhesion, excellent electrical properties and high geometric accuracy for glasses are an important step. In the current manuscript, we review the status and discuss our contribution towards achieving industrial readiness for glass in panel- and wafer-level packaging.
Reliability of Chiplets Heterogeneous Integration on 2.3D Hybrid Substrate Using Solder Joint and Underfill
Authors: Chou Ricky Tsun-Sheng , Lau John H , Chen Gary Chang-Fu , Huang Jones Yu-Cheng , Yang Channing Cheng-Lin , Liu Hsing-Ning , Tseng Tzyy-Jang 
Published: February 2022

Abstract
In this study, the reliability of chiplets heterogeneous integration on a 2.3D hybrid substrate using solder joint and underfill is investigated. Emphasis is placed on the thermal cycling test and drop test of the structure. The test results are plotted into Weibull distributions, where the Weibull slope and characteristic life at median rank are presented. At 90% confidence, the true Weibull slope interval and the true characteristic life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the chip/package assembly of the heterogeneous integration package are provided and discussed.
The Pivotal Role of Uniformity of Electrolytic Deposition Processes to Improve the Reliability of Advanced Packaging
Authors: Schmidt Ralf , Palm Jens , Knaup Jan M. 
Published: February 2022

Abstract
Heterogeneous integration is considered as the key technology to create large, complex System in Package (SiP) assemblies of separately manufactured, smaller components. Proper control of the uniformity of each process step constitutes one of the main challenges during integration of the different components into a higher-level assembly. In this context, processes that create thick layers by electrochemical deposition are especially susceptible to variations across the substrate. Such processes include copper pillar and bump as well as tin-silver applications. Insufficient coplanarity of electrolytic copper would result in significant reliability issues or evolution of stress in the package. Upcoming hybrid bump designs with features of different dimensions pose additional challenges to the electrolytic copper and tin-silver processes. Purposeful adjustment of differences between the heights of pillars of different diameters may be required after the copper process step in order to obtain the best uniformity for the complete stack with tin-silver on top. In addition to coplanarity, the electrolytic process should allow modification shape of the individual pillar or bump. In this context, a versatile copper electrodeposition process will be discussed that allows adjustment to a broad variety of uniformity parameters and combinations thereof. In combination with suitable tin-silver deposition processes, this process is expected to significantly improve the reliability of copper pillars and bumps for advanced packaging applications.
Thin film flexible circuits with embedded ASICs–Enabling technology for sophisticated medical applications
Authors: Kaiser A. , Matej P. , Hanka K. , Abel M. , Herbort C. , Lang R. , Pursche O. , Ruess K. , Keim U. 
Published: February 2022

Abstract
The requirements for thin film substrates have increased over the last years, as new materials, ongoing miniaturization and higher connectivity and complexity of circuit designs are arising. Especially the medical field, with its various application areas, drives the development of new technologies and new material combinations. Specifically, components for catheter or endoscope equipment are often difficult to realize, as limited space/cross section compete with the demand for higher functionality in the tip, and thus, requiring a higher number of connections to be routed out. One possibility to overcome this problem, is a local digitalization of the signals of the various sensors in the tip and doing a serial data transmission to the outside, reducing the required number of leads. To maintain a very small form factor, we have developed a technology that allows the direct integration of thinned ASIC chips into thin film flexible circuits. An example application, for the readout of catheter shape and positioning, was realized.
Our contribution will give an overview of the target application and describe the integration technology for the thinned dies together with the build-up of the thin film flexible circuits.
An Investigation into Thermomigration Failure of Flip Chip Solder Joint Interconnects used in High Reliability Applications
Authors: Morey Aimee M , Popelar Scott , Hook Julie 
Published: February 2022

Abstract
The experimental study described herein investigates thermomigration of both eutectic Sn/Pb and lead free Sn/Ag/Cu solder joints, with the additional focus on the development of an Arrhenius failure model of time-to- failure as a function of temperature. Flip chip test vehicles were assembled with daisy chain die, with and without underfill, attached to ceramic and organic package substrates, using standard reflow processes. Three different under bump metallurgy technologies were investigated: sputtered thin film Al/NiV/Cu, thick electroplated nickel, and thick electroplated copper (i.e., copper pillars). The test vehicles were subjected to unbiased high temperature storage (HTS) testing with temperatures ranging from 125°C to 200°C. Failure was determined from continuity testing at regular intervals until an open circuit or high resistivity was detected. The results demonstrate the robustness of Al/NiV/Cu UBM at temperatures less than 130°C, and of the thick electroplated UBM at temperatures of 150°C. Based on the HTS test results, and corresponding analyses, a thermomigration failure model was generated for eutectic Sn/Pb and lead free Sn/Ag/Cu solder alloys using an Arrhenius-like fit to the failure data.
Enhancing the Paste Release on 55μm pads with Water-Soluble Type 7 SAC305 Solder Paste for High Density SIP Application
Authors: Senthil Kumar B. , Rui Fen Zhang , Yam  , Huei Lip , HanWen Zhang , Sungsig Kang , Li-San Chan 
Published: February 2022

Abstract
The ultra-fine SAC305 solder is widely used as the lead-free solder composition for interconnection in advanced packaging based on its advantages such as good joint strength, thermo-mechanical fatigue behavior and creep resistance. Stencil printing remains the technology of choice for system-in-package (SiP) assembly because of its benefits such as economy of usage, ease of process control, flexibility of usage and fast and wide range of process window.
SiP involves the high-level integration of different components, Copper (Cu) pillar flip-chip dies and chips in one package to achieve multiple functions in one system. The need to accommodate ever increasing demand for reduced footprints requires the technology to constantly invent a range of Cu pillar 55μm diameter and smaller components. Many mobile communications SiP consist of 6 or more flip chips in a single package. Conventional flip-chip attach uses flux & Cu pillar solder cap for solder joint formation as it is challenging for solder paste to be printed on fine geometries below 70μm. Additional benefits of solder paste printing help eliminate non-wet Cu pillar defect rates and improve yield over conventional flux printing. Heraeus solder paste (AP series T7) makes use of ultra-fine spherical shape of solder powder to create strong metal coalesce for bonding during reflow process of Cu pillars mounting to substrates.
For example, the smallest passive component in use today is 008004 and Cu pillar diameter of 70um, which has a stencil opening of 125μm and 70μm respectively. Further reduction in Cu pillar flip-chip diameter of 55μm will require further reduction in stencil opening to 55μm, thus testing the limits of current type 7 pastes. Current solder pastes (AP series T7) can meet the consistency of printability when the stencil opening is 70μm or more. With smaller stencil opening, down to 55μm, the printing performance is less than desired. In this paper we describe the stencil printing application on the enhanced version of type 7 paste with a reinvented flux. The application tests were carried out using 55μm stencil opening. This paper will report the results of this application test.
Ultrasonic Wire Bond Outlier Classification
Authors: Seppänen Henri , Chua Siang Tat , Martinez Joel Elizondo , Villa Pedro 
Published: February 2022

Abstract
K&S developed and tested the Advanced Process Diagnostics (APD) algorithm to classify bonding outliers in ultrasonic wire bond production. APD is a software feature, part of Kulicke & Soffa wedge bonders to measure and analyze process signals and detect and classify bond outliers. APD helps bonder operators, production supervisors and process engineers to detect process deviations and fix the underlying root causes. APD measures bond signals, such as deformation, ultrasonic current and ultrasonic frequency. Bonds are automatically divided into subgroups based on bond order and process parameters and the signals within a subgroup are then normalized. For outlier classification, the features are extracted from the normalized signals and combined into failure class values. The failure classes, such as contamination, misaligned wire and unstable substrate, are calculated independently. Within the APD feature, a user can define limits for the failure class values and define bonder actions based on the severity of the detected outlier. We measured the detection rates for large wire Al bond failure classes and demonstrate how APD calculates failure class values from the signals. Additionally, we show how new signal features and failure classes can be defined to detect production specific or rare failure classes. Finally, we present outlier classification performance metrics against large production data sets.
Comprehensive Characterization of All Inorganic and Organic Components in Neutral Tin Plating Bath for Electronics Applications
Authors: Shalyt Eugene , Wang Jingjing , Parekh Vishal , Bai Chuannan , Liang Guang 
Published: February 2022

Abstract
Tin plating at neutral and near-neutral pH is the preferable process in the application of electronic components such as capacitors and resistors, where the chemically sensitive ceramic and glass portions can be damaged by highly acidic solutions (often used in semiconductor packaging processes). Stannous ions are not as stable at elevated pH due to oxidation and hydrolysis, and plating demands the use of a large number of additives making the process control very challenging. Various analytical techniques are developed for automatic and comprehensive characterization of all inorganic and organic bath components including simultaneous detection of conductive salt, anti-whisker and chelator by near-infrared (NIR) spectroscopy, brightener by potentiometric titration, stannous ions by electrochemical method, and the breakdown stannic ions by spectro-titration.
Copper Crystal Structures in Plated Microvias. Their Recrystallisation and a Means to Identify Joints at Risk of Premature Failure
Authors: Bernhard T. , Massey R. , Klaeden K. , Zarwell S. , Kempa S. , Steinhaeuser E. , Dieter S. , Brüning F. 
Published: February 2022

Abstract
Plated microvias are widely used within todays PCB industry as a means of achieving the high-density designs that are required in modern mobile devices, however, there has been growing concern regarding their long term reliability performance when stacked directly on top of each other.
Blind microvias (BMV) have a potentially complex metallurgical structure, with several interfaces located around the target pad - electroless Copper - electrolytic Copper joint. While field experience as shown that there are typically two major types of crystal structures formed across the BMV base, there has been little reported work investigating how or why such structures develop. In this paper, we review these two commonly observed microstructures within filled BMVs and offer proposals on how such structures are created. We subsequently describe a novel means to indicate if the microstructure of a BMV is likely to have a tendency for an early onset of failure.
Emergence of Glass Solutions for 5G and Heterogeneous Integration
Authors: Shorey Aric B. , Nelson Shelby F. , Levy David , Ballentine Paul 
Published: February 2022

Abstract
Glass has been of great interest for advanced packaging and RF applications for many years. Since glass is an insulator, it provides low loss performance particularly at high frequencies in the mmWave. The low roughness and ability to form in thin and large area formats provide opportunities for fine line spacing to enable miniaturization and cost-effectiveness. The challenge to glass adoption has been to establish high volume manufacturing operations. Leveraging the Viaffirm® temporary bond process provides many advantages to enable use of existing processes to fabricate thin glass substrates. Here we describe the process and examples of how it has been used to enable manufacture of devices on thin glass substrates.
Verification of Compartmental Electromagnetic Interference Shielding Effect with imprint-Through Mold Via (i-TMV) for RF modules
Authors: Negishi Motohiro , Shibata Tomoaki , Li Xinrong , Suzuki Naoya 
Published: February 2022

Abstract
In order to form a compartmental EMI shielding structure for radio frequency (RF) modules, we have proposed the new process named ”imprint-Through Mold Via (i-TMV)”, which could be fabricated by imprinting with a silicon master and filling with conductive paste. In this work, a test coupon was fabricated and EMI shielding effect of the i-TMV was actually evaluated by measurement of the electric field strength that leaked through from via array. As a result, it was found that the shielding effect was 23.6 dB at 4 GHz, which was close to the completely shielded value with a metal cap (25.6 dB). This result indicated that the i-TMV was significantly effective as a compartmental EMI shielding for the Sub-6 band application.
Assessment of Solder Flux Corrosivity and Flux Residue Level in Clip Bonding Assembly
Authors: Le Fred Fuliang , Chen Haibin , Guan Zunyu , Fajardo Francis Louise 
Published: February 2022

Abstract
Most fluxes and their flux residue are corrosive, and their presence on the surface of assemblies may cause reliability concerns due to electrochemical migration. This study firstly refers to the test method IPC-TM-650 2.3.32D and 2.6.15C and the requirements in J-STD-004A to evaluate flux-induced corrosion and the corrosivity of their flux residue. Then thermogravimetric analysis is used to evaluate the flux residue level after soldering under identical conditions. These comparison data can be utilized to compare flux performance of solder pastes. For the cleanliness evaluation after flux cleaning, the qualitative analysis refers to IPC-A-610G and adopts optical inspection to observe the flux cleaning effect. The quantitative analysis refers to IPC-TM-650 2.3.28B ion chromatography test method to analyze the level of ionic species after flux cleaning. In addition to IPC-TM-650 2.3.28B ion chromatography method, the effectiveness of other methods has been well demonstrated to characterize the fluxes and their flux residue in clip bonding assembly.
Distribution of Coated Metal Layer on Free Air Ball (FAB) Surface
Authors: Murali Sarangapani , Wan Lo Miew , Mariyappan Dhayalan , Weon Evonne Lim Yee , Sungsig SS Kang 
Published: February 2022

Abstract
Developments in bonding wire focus on coated silver wire for stacked devices in memory sectors revealing near equivalent performances to 4N Au wire. In addition to stacked device applications, the wire is also examined for other conventional applications. The innovative wire exhibits excellent performance on biased Highly Accelerated Stress Test (bHAST) passing 192h and 504h at 130°C, 85%RH for +3.3V and +20V, respectively. Thus, the wire satisfied one of the important criteria required to pass automotive reliability test (2X stress test, AEC Q100 Rev-H, with limited test samples). The test is conducted using 0.8mil coated silver wire and molded with green epoxy molding compound. Another benefit of the wire is stitch bond bondability with high MTBA of greater than 2h.