bluuebunny/crossref_metadata_2025_split huggingface dataset:
Effect of Novel SAC-Bi Solder Joints on Electromigration Reliability for Wafer Level Chip Scale Packages
Authors: Tsai Min-Yan , Lin Yung-Sheng , Kao Chin-Li , Wang Shan-Bo , Lin Ting-Chun , Hung Yun-Ching 
Published: February 2022

Abstract
The Sn-4Ag-0.5Cu base solder adding 3 wt.% bismuth (SAC-3Bi) solder has better drop and thermal cycling performance than Sn-4Ag-0.5Cu solder due the excellent mechanical properties in previous study. Therefore, SAC-3Bi has applied in solder joints of wafer level chip scale packaging (WLCSP) in recent year. In this study, SAC-3Bi solder was used on WLCSP device to evaluate electromigration reliability. A specially designed test vehicle for SAC-3Bi solder balls with 200μm diameter Ti/Cu/Cu UBM have been investigated experimentally. The electromigration behavior of solder balls was investigated in terms of the electrical resistance change, and the mechanism was also explored by the microstructure evolutions. The electromigration experiment of the SAC-3Bi solder balls was conducted continuously at 1.2 A to 1.6 A under 170 °C to 185 °C condition. The resistance of solder balls was monitored according to Kelvin structure. An EM prediction model of SAC-3Bi solder balls was built based on Black-type electromigration time to failure equation, followed the JEDEC with five test conditions. The activation energy of SAC-3Bi solder is 0.80 eV ± 0.02 eV, coinciding the activation energy of SAC based solder alloy (0.72 eV ~ 0.89 eV). The microstructure of the solder balls was investigated using a scanning electron microscope (SEM) accompanying energy-dispersive X-ray spectroscopy (EDS) and electron backscatter diffraction (EBSD) for the failure behaviors and phase characterization. There were intermetallic compounds of Cu3Sn and Cu6Sn5 at the interface of copper and solder. We observed two failure modes of SAC-3Bi solder balls during current stressing, the fracture occurred at the UBM/solder ball interface and Cu redistribution layer (RDL), respectively. The failure mechanisms have been investigated in detail from microstructure analysis.
High Frequency, Low Loss, Additively Manufactured Hermetic Package
Authors: Smith Tim , Rhyne Bill , Reid Robert , Hatfield Christopher 
Published: February 2022

Abstract
This paper presents the development of a new type of hermetic cavity package for mmWave RF MMICs. The package features an all copper additively manufactured construction for optimal thermal performance as well as low loss air coax RF signal routing with a critical ceramic feedthrough to isolate the internals of the package from the external environment. With a simulated thermal resistance of 1 C/W, from die backside to package lid, and RF insertion loss of less than 0.5dB from 0–80Ghz, this package can support high power as well as high frequency MMICS. With no polymers in the construction of the package true hermetic performance is expected, making this package a high reliability option as well.
For this paper two die were selected for demo packages. These die do not have surface mountable packages offered on the market. The die selected are the CMD247 30–40GHz Low Phase Noise Amplifier from Qorvo and the CHA2080-98F 71–86GHz Low Noise Amplifier from United Monolithic Semiconductors. RF insertion loss as well as environmental reliability will be demonstrated with these devices. The additive manufacturing process used is the proprietary PolyStrata® process developed by Nuvotronics. With the development of 14” panel substrate manufacturing line utilizing a mask-less process, fabrication process can support both high-volume, and high-customization without incurring prohibitive tooling costs.
New approach for High Reliable & Cost-Effective Solder alloys for Automotive Applications
Authors: Fritzsche Sebastian , Vaidya Manu Noe , Prenosil Peter , Stenger Katja , Trodler Jörg , Jörger Michael 
Published: February 2022

Abstract
Commercially known as Innolot, the highly reliable lead-free alloy, allowing for high operating temperatures, is a Tin-Silver-Copper (SAC) metallurgical system with additional elements to harden the alloy and to improve its creep strength in order to significantly improve the reliability of solder joints. Compared to traditional SAC alloys, the characteristic lifetime can be enhanced on the base of temperature cycle tests (TCT) from −40°C to +125°C or even extended to 150°C.
Assemblies in the automotive industry increasingly require higher reliability for safety relevant and emerging applications such as Advanced Driver Assistance Systems (ADAS). Cost-reduction requirements demand a new approach for optimized soldering processes and materials. As the current reflow process prefers Nitrogen atmosphere for low defects in high reliability soldering, our research focuses around the partial and/or complete change to air soldering processes. Furthermore, we investigate the influence of different surface finishes such as Chemical Sn, NiAu, and Cu OSP, and modified alloy compositions in the soldering performance. Apart from initial characterizations for various assemblies, reliability tests on Heraeus Reliability1 printed circuit boards as well as temperature cycle tests from −40 to +150°C for up to 2500 cycles are reported and resulting failure modes are discussed.
This paper furthermore describes the potential for cost reductions via process and/or material optimizations without diminishing the high reliability performance for such automotive applications.
Ultra wide-band, low Loss RF substrate with high-density DC routing supporting 5G/6G flip-chip RFICs
Authors: Smith Tim , Rhyne Bill , Hatfield Christopher 
Published: February 2022

Abstract
This paper presents the development of a substrate/interposer technology that is capable of supporting DC signal line routing down to &lt;1mil trace and space densities, but also supports wideband, high-frequency and industry leading low loss RF routing from to beyond 175GHz. Building off of the proven performance and reliability of the PolyStrata® technology enabled air-coax routing, this paper discusses the development and addition of a redistribution technology that enables multilayer, high density DC signal routing at any point during the PolyStrata® process. This enhances the Polystrata® offering to a truly integrated substrate manufacturing process supporting high density interconnect requirement of flip-chip RF ICs as well as low loss high performance RF routing.
The paper describes the design and fabrication of a demonstration part designed to accept a D-Band Flip-Chip RFIC. The chip side interconnects are 50um diameter copper pillar with solder cap, at 100um pitch with over 200 interconnects on a die. Multiple connections were required from 10Ghz to 175GHz as well has 30+ DC signal lines. The design can support this level of interconnect density and act as an interposer for next level interconnect to a printed circuit board. DC lines were routed out to a 400um pitch while RF interconnects can support transitions to micro-strip or strip-line PCB routing technology or waveguide, for easy and low loss interconnect to the next level system. An added benefit of being integrated into the PolyStrata® process is that high-performance passive components can be monolithically integrated into the interposer, and the demonstration vehicle implements a mmWave pass-band filter as well.
Memory Packaging Challenges for a Growing Market
Authors: Olmstead Knowlton , Zwenger Curtis , Strode Richard 
Published: February 2022

Abstract
Increasing demands for storage and high-performance memory in applications such as artificial intelligence (AI), machine learning and processing storage are driving long-term growth in the market. This paper will highlight the key challenges encountered in packaging next-generation memory devices and discuss some of the technological developments required to address them while considering performance, cost, and yield. An evaluation is highlighted of a remote microwave plasma process to remove damage caused by laser ablation during the wafer dicing process that shows an improvement in die strength using this process.
Warpage Simulation Study by Trace Mapping Method for FCCSP with ETS Substrate
Authors: Zhang Ken , Kao Nicholas , Lai David , Wang Yu-Po 
Published: February 2022

Abstract
ETS (Embedded trace substrate) has become as the mainstream substrate for FCCSP since it has fine trace, better trace dimension control and low cost advantages which compared to normal substrate. But it usually encountered more serious warpage issue for bare substrate and complete package which may influence D/B (die bonding) and SMT yield rate due to its coreless characteristic. Especially for ETS substrate with special trace pattern design (ex. larger Copper area), bare substrate may appear peculiar warpage contour and led to serious non-wetting issue at specific location during D/B process. Thus, if it can predict warpage value and contour accurately for bare substrate and package is an important topic.
In this paper, a FCCSP package with ETS substrate was chosen to study trace impact. Bare substrate and package warpage simulation models w/ and w/o considering trace pattern by trace mapping method were performed and compared to shadow moiré results. Analysis results showed that simulation w/ considering trace pattern could get more accurate warpage value and more similar warpage contour for bare substrate and package warpage.
Optimization of Thermal Design and Mold Flow Process for 3D SiP Structure
Authors: Chang Yu-Hsiang , Huang Bing-Yuan , Huang Hung-Hsien , Chen Dao-Long , Tarng David , Hung CP 
Published: February 2022

Abstract
With the advent of the 5G era, major package and testing plants have been taking frequent action recently. Obviously, with higher and higher performance requirements, SiP is a functional package integrated multiple functional chips, including processor, memory into one package. However, thermal design is an important issue to be addressed at this time. This paper mainly presents a 3D SiP structure based on the combination of two substrates, integrating 4 components in a single package, total power consumption is 30 Watt. To address thermal management difficulties of this 3D SiP, a method is designed to increase the thermal path between the two boards. The Effects of the structure, number of via, and changing location of components aspects of the thermal performance are studied. The thermal vias was designed in between the two boards provide are direct heat dissipation, connecting the metal studs above passive components to improve thermal performance. Thermal performance with 240 vias is improved by 0.4%, while the number of vias increases from 240 to 912, the temperature decreases only 1.0%, 0.6% respectively. The difference of thermal resistance (θJB) comparison is 1.9%, 1.5% and 1.0%. There are limits to the improvement of vias, the effect of increasing the number of via is not as good as expected. However, increasing the thermal conduction path may have an effect on the void of mold flow. s
3D mold flow modeling of the transfer molding process with molded underfill (MUF) using Moldex3D is applied to optimize design and process parameters that can reduce device defects. There is one important challenge that faced air voids entrapment in molding area. Generally, the experiments involve a lot of design of experiment (DOE) matrixes which spend a lot of time to solve air void issue. As above reasons, the mold flow simulation can be used to apply molding parameters to find out optimum solutions for air void risk free of SiP, which can reduce development cycle time before mass production. From the mold flow simulation results, when the number of plunger segments increases and the tail flow rate decreases, the void issues can be effectively improved.
High Density Package Design Platform and Assembly Design Kit
Authors: Huang Chih-Yi , Cao Lihong , Chang Keng-Tuan , Wang Chen-Chao 
Published: February 2022

Abstract
With the miniaturization of integrated circuit technology and process, chips are getting smaller and smaller, and thus it results in fan-out packaging with RDL process was derived to extend the ball grid array design space. The applicable range of RDL now includes products in the fields of Networking, HPC, AI and even SiPh. And the new package types comprised of the RDL process include e-WLB, chip first FOCoS, chip last FOCoS, FO-PoP and 2.5D IC etc.
The total pin count in FOCoS packaging can be more than ten times than that the pin counts in a large FCBGA packaging; the FOCoS package layout density can reach tens or even hundreds of times than FCBGA. High density and complex connectivity in FOCoS cause more difficult using traditional EDA tool for packaging design. In addition, the RDL process manufacturing equipment is different from that for traditional packaging substrate and it is more like the foundry process, so it is required to consider design rule check and LVS check flow compatible to IC design flow except for the package layout. It is necessary to have different methods and tools from that in the past to complete a reliable design.
In this paper, there is an introduction about the new design flow and platform for high density package design and it describes the new design platform could overcome the difficulties of layout on high-density packages such as FOCoS. And then talking about FOCoS Assembly Design Kit (ADK) to provide to the IC or system designers, especially the new design rule checking tools and procedure, as well as example about how DRC tools plays an important role in RDL process improvement and design. In addition to checking the design rule for the layout, verifying the interconnections between the components in the package after design is very important to FOCoS packaging which is generally used in multiple dice integration such as homogeneous and heterogeneous integration design.
Contamination Troubleshooting for Microelectronics Packaging
Authors: Chia Victor K.F. , Wilkus Tiffany , Huerta Laarni , Rivello Wendy , Jew Jennifer , Li Fuhe , Gotts Hugh , Hsu I-Hsiang , Anderson Scott 
Published: February 2022

Abstract
A goal of advanced packaging design performance is to reduce power and to achieve better control of heat and electromagnetic interference. Materials to achieve efficient packaging include the use of gold (Au) wire, copper (Cu) alloy, gold/silver (Au/Ag) plating, solder, low-k epoxy and dry-film polymers, silicones and polyimides. Material purity verification and contamination control during the production process is a prerequisite to ensure high yields in packaging because getting this wrong means throwing away multiple chips. This paper describes an Analytical Decision Tree to guide methodology selection, reviews contamination troubleshooting methodologies, and case studies to resolve process issues.
A Novel Design of High-Temperature Lead-Free Solders for Die-Attachment in Power Discrete Applications
Authors: Zhang Hongwen , Lytwynec Samuel , Wang Huaguang , Geng Jie , Mutuku Francis , Lee Ning-Cheng 
Published: February 2022

Abstract
Development of high-temperature lead-free (HTLF) solders to replace high-lead solders for die-attachment in power device applications is driven by (1) the harmful effects of lead to human health and the environment, and (2) the demand of the improved bonding materials serving under high-power density and high-junction temperatures, especially for wide-band-gap power devices. A novel design, based on a mixed solder powder paste technology—Durafuse™—has been developed to deliver a Sn-rich HTLF paste, presenting the merits of both constituent powders. The combination of the rigid, high-melting SnSbCuAgX and the ductile, low-temperature Sn-rich solder in one paste enables reflow at a relatively low temperature (barely above the liquidus temperature of the final joint composition) and maintains the joint strength above 15MPa in the temperature range between 270°C and 295°C. The sufficient high-temperature strength has demonstrated the capability of maintaining the joint integrity during subsequent multiple SMT reflows below the 270°C peak temperature, regardless of the existence of a partial melting phase. Both X-ray inspection and cross-section microstructure have not shown any damage in the Si die or any noticeable cracks in the bonding joint, even after 3000 cycles of TCT (−40 to 150°C). In summary, Durafuse™ HT, the novel design of the high-temperature lead-free pastes, has shown the feasibility as a drop-in solution to replace high-lead solders for die-attachment in power discrete applications.
Challenges and novel approaches for the development of hardware-related trustworthy electronics
Authors: Middendorf A. , Böttcher M. , Jung E. , Pötter H. , Ndip I. , Töpper M. , Schneider-Ramelow M. , Steller W. 
Published: February 2022

Abstract
Emerging and future electronic components and systems must not only meet cost, performance, reliability, miniaturization and environmental requirements, they must also be trustworthy. In the near future, we have to trust even more electronic components and systems in everyday life, such as those used in self-driving cars or service robots.
In this contribution, we present the challenges and novel approaches for the development of hardware-related trustworthy electronics. Our proposed solutions cover all aspects of the value chain starting with the confidentiality of secure production chains, the security against manipulation as well as technological sovereignty. These novel approaches are extensively investigated with partners from academia and industry in R&D projects within the framework of the German Flagship initiative “Trustworthy Electronics”. The German Federal Ministry of Education and Research (BMBF) as a contribution to research and innovation for technological sovereignty fund this initiative.
In this paper, we will report on the latest research results of the implementation of our approaches at four key levels, namely wafer, board, system and platform levels.
In the area of wafer level packaging, the focus is on developing solutions for the implementation of trustworthy heterogeneous systems using high-frequency chips in combination with complex signal processing.
At board-level, the goal is to develop a universal electro-optical interposer, particularly taking into account security features (e.g. key generation and encryption / decryption, design of photonic expandable RISC-V peripheral components).
At system-level, we focus on the development of processes and multi-sensor systems that protect important microelectronic circuits from criminal attacks. The entire system has to be protected by hierarchically graded monitoring, by embedded sensors and its corresponding microcontrollers. The development of the packaging and interconnection technology is supplemented by non-destructive testing methods that monitor the integrity of the protective mechanisms. The approach pursued here does not require any modification of the structure of the circuits to be protected and can be combined with all safety-critical application circuits. With this cost-effective solution, small series production is also economically feasible.
Finally, at the platform-level, overreaching issues are investigated within the three pillars, namely design, production and analysis of the microelectronic value chain. The platform concentrates predominantly on contributions to the necessary standardization. This enables companies effectively to support the supply of trustworthy electronics, especially with regard to small series.
Highly accelerated lifetime testing in power electronics
Authors: Czerny Bernhard , Khatibi Golta 
Published: February 2022

Abstract
This paper presents case studies on application of accelerated mechanical fatigue testing for evaluation of wire bond interconnects and interfaces in electronic devices. A dedicated experimental set-up is designed to induce fatigue failure in the weak sites of the devices by reproducing the failure modes occurring during operation. Acceleration is achieved by increasing the mechanical testing frequency enabling determination of lifetime curves in a very short time. Exemplary studies on the degradation and fatigue failure of heavy wire bonds typically used in power electronics are presented and advantages and some restrictions of the proposed method are briefly discussed.
Plantas devonianas do Brasil e seu significado bioestratigráfico
Authors: Matsumura Willian Mikio Kurita , Iannuzzi Roberto 
Published: February 2022

O registro paleobotânico do Devoniano brasileiro tem sido recentemente resgatado da literatura e reinvestigado por meio de novos depósitos fitofossilíferos, principalmente nas bacias do Paraná e do Parnaíba. Estas ocorrências têm possibilitado estudos de caráter taxonômico, tafonômico e fitoestratigráfico. O presente estudo objetiva caracterizar a flora devoniana brasileira a partir de algumas descrições de plantas fósseis provenientes das três bacias sedimentares brasileiras (Amazonas, Paraná e Parnaíba) e ilustrar o posicionamento estratigráfico e o significado bioestratigráfico das ocorrências fitofossilíferas. As unidades litoestratigráficas contendo plantas fósseis foram compiladas e correlacionadas. No total, foram levantados 19 gêneros de plantas fósseis, distribuídas ao longo do intervalo Lochkoviano-Famenniano. A partir da amplitude dos gêneros levantados, foram identificados três intervalos estratigráficos e dois estágios florísticos distintos, denominados Cooksonia-Hostinella e Haplostigma-Spongiophyton, para o intervalo analisado.
Brioflora do Parque Estadual Intervales, São Paulo, Brasil: uma importante área para conservação da biodiversidade da Mata Atlântica do Sudeste brasileiro
Authors: Visnadi Sandra Regina 
Published: February 2022

O Parque Estadual Intervales (PEI) forma, com outras unidades de conservação, o Continuum Ecológico de Paranapiacaba, que é uma das sete maiores áreas contínuas de Mata Atlântica do país. O trabalho tem por objetivo evidenciar a riqueza da brioflora, pois lista 199 espécies (90%), além das 21 já citadas na literatura para o PEI, totalizando 220 espécies para a Mata Atlântica de encosta (floresta ombrófila densa) desse parque. O material totaliza 767 exsicatas, que se encontram depositadas no Herbário Maria Eneyda Pacheco Kauffmann Fidalgo, do Instituto de Botânica de São Paulo (SP). A brioflora do PEI é rica e característica da Mata Atlântica de encosta do estado de São Paulo, mas com algumas espécies restritas ao parque, não ocorrendo nesse ecossistema de outras localidades paulistas; inclui duas citações novas para o Brasil (Chryso-hypnum squarrosulum, Leskeodon andicola) e cinco para São Paulo (Fissidens dendrophilus, Macromitrium longifolium, Orthostichopsis praetermissa, Pelekium scabrosulum e Thamniopsis cruegeriana), além de possuir 13 espécies endêmicas do Brasil e uma espécie que, no Brasil, restringe-se ao estado paulista. Esses dados demonstram a importância do PEI para a conservação e proteção da diversidade da brioflora local, do estado de São Paulo e do Brasil.