(G02 Best Paper Award Winner) Development Of High Resistivity FD-SOI Substrates for mmWave Applications
Authors: Bertrand Isabelle , Flatresse Philippe , Besnard Guillaume , Bethoux Jean-Marc , Chalupa Zdenek , Plantier Christophe , Rack Martin , Nabet Massinissa , Raskin Jean-Pierre , Allibert Frederic 
Published: July 2022

The mmWave era opens up the door to revolutionary applications in the fields of communication, radar, imager, security, etc. FD-SOI CMOS technology is entering the mmW realm providing undeniable benefits in terms of data-rates, bandwidth, latency and power consumption improvements. The high resistivity substrate option is seen as a major booster to reach ultimate mmW performances. The engineering challenges related to this new wafer generation are addressed in this paper.
In the different options for highly resistive silicon, low and high interstitial oxygen (Oi) materials are the most common ones, typically used to reach resistivity performance on SOI handles. Those materials are less compatible with FD-SOI technology, as they can be very sensitive to slip-line issues or wafer deformation, in specific SOI processing and customer’s line, possibly leading to overlay error. In addition, we can encounter inspectability and co-integration issues due to Crystal Originated Particules (COPs) presence for high Oi substrates. For the targeted technologies with FD-SOI, equal or below 28 nm, the handle properties will be key, as deformation and inspectability considerations are even more critical.
One of the main challenges was to develop specific materials and processes to get both good resistivity and stability towards fabrication processes (SOI line and customer processing), and good mechanical behavior towards slip-line and potential deformation leading to error, together with low COPs handle material.
In this paper, we will show how substrates were engineered specifically, to reach the appropriate resistivity targets around 1000 Ω.cm, and to be stable in depth with different additional anneals, in order to control compatibility with customer processes. In addition, we managed to achieve good performances in terms of mechanical behavior, such as slip-line generation during fabrication processes. We also had no overlay issues usually linked with slip-lines or excessive Bulk Micro Defects (BMD) presence in depth, generating dislocations and plastic deformation.
We will review the material and process steps requirements to reach the best performances.
The initial material requirements will be the oxygen content, together with the resistivity. The process requirements will be the final oxygen precipitation status, affected by specific thermal treatments and presence of sites for BMD nucleation and growth.
A specific precipitation range will lead to good robustness towards both slip-lines sensitivity and overlay risks, by creating enough BMDs but not in excess. Besides, this specific precipitation state also helps to decrease the amount of residual interstitial oxygen left inside the High Resistivity substrate, and then decreases the oxygen thermal donor generation during back-end treatments in the 375-425°C range, improving resistivity stability.
We will present all the characterizations performed on final SOI wafers, and after additional treatments, to highlight both handle substrate resistivity stability and mechanical robustness.
Specific measurements were carried out to ensure that going from standard to high resistivity substrates did not adversely impact the behavior of logic devices. Test structures were implemented with 28 nm design rules on FD-SOI substrates with either 10 Ω.cm or 5 kΩ.cm handle resistivity. Compared figures of merit included transistors’ VTH and minimum gate length devices Ion/Ioff tradeoff as well as several devices built in the bulk of the wafer such as bipolar devices, diodes and capacitors. Obtained results will be shown to be within the natural process dispersion.
Those substrates being destined to RF and mmWave applications, their performance was measured in terms of linearity and attenuation using coplanar waveguides built directly on top of the 20 nm buried oxide. Second harmonics measurements up to 28 GHz of fundamental frequency will be shown. The small signal measurements results will be compared to simulations including a thicker dielectric mimicking the very thick back-end of line available in advanced nodes.
In conclusion, we will summarize how specific material for eSoC.1-HR handle was developed, showing performances in agreement with expectations on resistivity stability and mechanical robustness. Those substrates are leading to improved RF parameters compared to standard FD-SOI substrates, without degrading logic devices parameters.