Beol-Compatible Ingazno-Based Devices for 3D Integrated Circuits
Authors: Gong Xiao , Han Kaizhen , Sun Chen , Zheng Zijie , Kong Qiwen , Kang Yuye , Wang Chengkuan , Kumar Annie , Zhou Zuopu , Jiao Leming , Liu Long 
Published: November 2022

Due to its attractive materials and electrical properties, indium-gallium-zinc-oxide (IGZO) has been extensively researched in many emerging technologies, especially for three-dimensional (3D) monolithic integration and back-end-of-line (BEOL) compatible applications [1]. On the pathway toward the realization of high-performance 3D monolithic integrated chips (ICs), a wide range of building blocks with different functionalities are required. 3D monolithic ICs also demand optimization in device performance and circuit architecture design.
In this paper, we discuss our recent research development in IGZO-based techniques at both device and circuit levels. This includes nanowire structure for IGZO-based transistors, as well as the BEOL-compatible ferroelectric ternary content-addressable memory (TCAM) and embedded dynamic random-access-memory (eDRAM) for compute-in-memory (CiM) using IGZO-based transistors.
A novel digital etch technique for amorphous IGZO (α-IGZO) material as well as the formation of α-IGZO nanowires were realized, enabling high performance α-IGZO nanowire field-effect transistors (NWFETs) with ultra-scaled nanowire width (W
NW) [2]. The scanning electron microscopy (SEM) images of α-IGZO nanowire before and after the digital etch show that the nanowire structure as well as W
NW reduction after digital etch can be clearly observed. The smallest α-IGZO nanowire after digital etch has a W
NW of ~20 nm. By leveraging the ultra-scaled nanowire structure, the NWFET with the smallest W
NW achieves decent subthreshold swing of 80 mV/decade as well as high peak extrinsic transconductance (G
m,ext) of 612 μS/μm at a drain to source voltage (V
DS) = 2 V (456 μS/μm at V
DS = 1 V). As compared with previous works in literature, our IGZO NWFET achieves one of the highest peak G
m among all IGZO-based FETs.

α-IGZO ferroelectric FETs (Fe-FETs) with a metal-ferroelectric-metal-oxide-semiconductor (MFMIS) structure were further realized based on the α-IGZO transistor process modules. The smallest L
CH is as small as 40 nm. The cross-sectional transmission electron microscopy (TEM) image of the device shows sharp interface. The α-IGZO Fe-FETs achieve a large memory window of 2.9 V, high endurance of 108 cycles, high conductance ratio, and small cycle-to-cycle variation. By leveraging the low temperature processed α-IGZO Fe-FETs with good electrical characteristics, a BEOL-compatible ferroelectric TCAM circuit with 2 Fe-FETs connected in parallel was realized [3], showing an extremely large sensing margin. In addition, such α-IGZO Fe-FET TCAM reduces the transistor number from 16 to 2 as compared to traditional SRAM-based TCAM. Smaller cell size and higher energy efficiency can also be obtained.
IGZO transistors can play an important role in in-memory computing as well. SEM image of the eDRAM CiM cell shows utilization of IGZO transistors. The smallest device has L
CH of 45 nm [4]. The IGZO transistor-based eDRAM CiM with differential cell structure achieves low leakage current, low variation, low charge loss sensitivity, and the control-friendly charge-domain computing without DC power. By evaluating the key figure-of-merits, including precision, power efficiency, computing density, retention time, and robustness, it can be concluded that our IGZO transistor-based eDRAM CiM is promising for low-power and scalable compute-in-eDRAM design.

Acknowledgments: This work is supported by Singapore Ministry of Education (Tier 2: MOE2018-T2-2-154, Tier 1: R-263-000-D65-114).

References: [1] K. Normura et al., Nature, 432 (7016), 488-492, 2004. [2] K. Han et al., VLSI, 2021, p. T10-1. [3] C. Sun et al., VLSI, 2021, p. T7-4. [4] J. Liu et al., IEDM, 2021, p. 462.