(Digital Presentation) Properties of Selectively Grown Si:P Layers below 500°C for Use in Stacked Nanosheet Devices
Authors: Rosseel Erik , Porret Clement , Hikavyy Andriy Yakovitch , Loo Roger , Richard Olivier , Martinez Gerardo Tadeo , Batuk Dmitry , Mertens Hans , Dentoni Litta Eugenio , Horiguchi Naoto 
Published: November 2022

With the introduction of novel stacked CMOS transistor integration schemes such as sequential 3D and CFETs [1,2], there is an increasing need for highly active source/drain layers with a low overall thermal budget. For some integration schemes, processing temperatures below ~ 525°C are desired [3] and in most cases, the contacts need to be formed on the {110} surfaces of exposed Si nanosheets. In this paper, we report on selectively grown Si:P layers below 500°C targeting application in stacked nanosheet-based devices. In contrast to conventional approaches where selectivity is obtained at low temperatures using Cyclic-Deposition and Etch (CDE) with HCl/GeH4 as an etchant [4,5], we rely for this work on Cl2-based etching in combination with Si3H8 as a high-order Si precursor [6]. The Si:P layers were grown in a 300 mm ASM Intrepid® ES reduced pressure chemical vapor deposition reactor on Si (001) substrates.
Figure 1 shows some typical characteristics for the Si:P layers without etching (“Dep-only”) and CDE Si:P layers below 500°C. As the temperature is lowered, the growth rate and P incorporation for a given PH3 flow decreases substantially, while the active concentration increases. For both the “Dep-only” and CDE layers, a minimum develops in the resistivity which corresponds to a maximum in active concentration as derived from micro-Hall measurements. Due to the etching during CDE, a P-enrichment takes place and the P concentration in the layers is enhanced compared to the “Dep-only” case. A minimum resistivity of 0.28 mOhm.cm (Pact ~ 6e20/cm3) is obtained for CDE at 480°C which is slightly larger than the minimum resistivity of 0.24 mOhm.cm (Pact ~ 1e21/cm3) for the “Dep-only” case at the corresponding temperature.
Figure 2 shows the application of the CDE process on wafers with fins. By lowering the deposition time at a constant etching time per cycle, a (wafer-scale) selective regime can be reached. For the “Dep-only” case, quite some defects and nuclei are present on the sidewalls of the Si-fins and the oxide dielectric, respectively, which are finally removed by sufficient Cl2 etching.
Figure 3 compares the corresponding X-TEMs of the above fins after “Dep-only” and selective CDE conditions. For the “Dep-only” case we can only observe a mono-crystalline growth in the <100> direction. For other growth directions like <110>, epitaxial breakdown-down occurs resulting in a substantially reduced crystalline thickness. With the use of Cl2 based CDE, a selective growth can be reached as well as a clear structural improvement in the <110> growth direction, which is very important for the application in nanosheet devices. Finally, once a (111) facet is formed, twin defects occur as expected for low temperature Si:P and Si:C:P [7].
The growth behavior of the CDE processes in relevant nanosheet geometries is currently under investigation.

References

[1] W. Rachmady et al. in Proc. IEDM 2019.
[2] C.-Y. Huang et al. in Proc. IEDM 2020.
[3] A. Vandooren et al. in Proc. VLSI 2018.
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[6] M. Bauer, ECS Trans.
50(9), pp. 499–506 (2012).
[7] J. Tolle et al., ECS Trans.
50(9), pp. 491-497 (2012).
[8] E. Rosseel et al., ECS Trans. 75(8), pp.347-359 (2016).

Figure 1