Airborne Molecular Contamination: Mechanism and Consequences on Devices
Authors: Garnier Philippe , Borde Yannick , Sevilla Gines 
Published: July 2022

Keywords: Airborne molecular contamination, condensation defects, threshold voltage, high k metal gate, corrosion.
Introduction
During dies manufacturing, silicon surfaces cleaning continues to be challenged to reduce materials consumption. There’s a trade-off between such reduction and keeping a good enough cleaning efficiency to avoid defects creation. This paper gives a few examples of chemical traces deposited on various surfaces, degrading the dies quality such as corrosion concerns, device electrical properties shifts.
Experimental and characterizations
In this work, a 28nm node is considered in a high k metal gate, gate first integration. The metal gate is a stack of a HfSiON and TiN films, on FD-SOI wafers [1].
Various chemicals are hereby discussed, all dispensed on spin dry single wafer platforms from SCREEN.
Contamination has been measured thanks to LPE-IC (Liquid phase extraction – ionic chromatography).
Results and discussion
Airborne molecular contamination can lead to various concerns. Such contamination can be divided in 4 categories: acids, bases, condensables, and dopants.
Halogen based gas and liquids are widely used in the semiconductor industry: plasma etching (CF4, HBr, ...) [2], deposition and wet processes.
First and foremost, halogen gas can adsorb on substrates during plasma, or deposition processes. If the gas is not properly purged away from the process chamber, this can lead to a significant surface contamination. First example consists in volatile salts left on a silicon nitride film after a LPCVD furnace deposition. The film surface is contaminated by salts due to inefficient dichlorosilane gas chamber purge. Although the salts are quite volatile, they can generate further patterning defects, blocking plasma etching processes (figure 1).
Similar kind of defects, with an order of 20µm size are also observed after selective silicon epitaxy, that uses HCl gas. Such salts are analyzed by LPE-IC (table 1), revealing their nature: ammonium chloride, from adsorbed HCl having reacted with ammonia and humidity from air cleanroom. If unremoved, severe silicon corrosion is found few hours after the epitaxy process. Fortunately, a very mild SC1 (Standard Clean 1) wet or plasma process can either dissolve or degas such salts.
Eventually, wet processes can also meet airborne molecular contamination concerns [3], especially when using concentrated acids (sulfuric [4], or phosphoric acid [5]). They can leave a significant amount of anions on the substrate surface, if not properly cleaned, forming ammonium based salts. Photo lithography patterning quality can be degraded (figure 2) but also thermal oxide growth kinetics [6].
As a last straw, single wafer cleaning platforms can deliver different processes between wafer frontside and backside. This is convenient to clean only the wafer backside without touching its frontside. Although the wafer is protected by a nitrogen curtain at few millimeters from the wafer surface, a device degradation is found when a wafer backside clean is operated after the high k film deposition. Indeed, the NMOS threshold voltage is shifted up to 40mV. A perfect correlation is drawn with a fluorine contamination measured on the high k surface, thanks to XPS (figure 3). This correlation is relevant towards some observations in the literature where fluorine can affect the device [7] [8]. This fluorine airborne contamination is finally confirmed thanks to a Picarro analyzer that confirms the chamber ambiance can be contaminated to levels of 0.6 ppbv.
Conclusions
Airborne molecular contamination can be linked with poor gas line purges, leaving adsorbed molecules reacting with cleanroom atmosphere. This can lead to severe yield degradation. Moreover, although cleaning tend to be milder and milder, concentrated acids still needs a relevant cleaning to avoid salts growth. Finally, a deeper attention is required to control the ambiance of single wafer cleaning platforms.
References
[1] J. Hartmann et al., Planar FD-SOI technology at 28nm and below for extremely power efficient SoCs, Las Vegas show (2012)
[2] A. Kabansky, Solid State Phenomena Vols. 103-104, p 59-62 (2005)
[3] J.M. Oh et al., Solid State Phenomena, vol. 145–146, Trans Tech Publications, p. 151–154 (2009)
[4] P.J Clews et al., ECS, Vol. 97-35, p. 23-30
[5] P. Garnier et al., ECS, 80 (2), p. 101-109
[6]. W. Scott et al., ECS, 151 (1), G8-G12 (2004)
[7] S. Lee et al., Solid State Technology 56(4), p. 22-24 (2013)
[8] W. Xiong, IEEE international SOI conference (2007)

Figure 1