(Invited) Optoelectronic and 3D Applications with Die to Wafer Direct Bonding: From Mechanisms to Applications
Authors: Fournel Frank , Sanchez Loic , Montmayeul Brigitte , Mauguen Gaëlle , Bally Laurent , Larrey Vincent , Morales Christophe , Bourjot Emilie , Ladner Carine , Bond Alice , Moreau Stephane , Szelag Bertrand 
Published: November 2022

Abstract—Wafer direct bonding is now a widely spread technique in microelectronics. However in many interesting applications, wafer bonding is not adapted due to size, material or technological node differences. Die to wafer bonding could then lead to innovative devices. After explaining some specific fundamental mechanisms, III/V die to wafer bonding and copper hybrid bonding will be presented for photonic and 3D applications.
Introduction
SOI or backside image sensors’ fabrication in mass production, for instance, calls upon direct wafer bonding that has become a standard technology available in many industrial microelectronic factories. Direct bonding of 200 mm or 300 mm silicon wafers are nowadays well mastered. For many innovative applications, it could be interesting to introduce new materials like InP, AsGa, GaN on a silicon platform. Heterostructure bonding then needs to be developed. This could be done with wafer-to-wafer bonding. However, wafers made of these new materials usually have diameters much smaller than that of silicon wafers, especially if CMOS are required on the silicon wafers. Indeed, advanced CMOS devices are nowadays only available on 200/300 mm silicon wafers. Even if the bonding of a small wafer on a bigger one is easily feasible, the silicon surface lost will be detrimental to the cost of the device. Moreover, usually, a very small surface of the new material is needed on the silicon wafer. With a wafer-to-wafer bonding (W2W), the new material surface loss will be quite important. Die-to-wafer (D2W) bonding is thus the solution to both issues in order to put only a small amount of new material where it is needed and populate all the active area on silicon wafers.
D2W is also interesting in hybrid bonding with silicon wafers. Indeed, D2W enlarges design rules to mix different technologies (material, dies size) on the same bottom wafer while enabling high density of copper interconnects.. Hybrid D2W is then foreseen as being the next step for hybrid bonding in order to widen its application field.
Results
Starting with the well know fundamental mechanisms of silicon dioxide bonding [1] as well as copper and hybrid surface bonding [2], D2W bonding behavior will be discussed. Some specific features indeed have to be taken into account for die bonding. For instance, all the edge effects, during and after the bonding or the annealing, have a great impact on the bonding energy as well as on the interface defectivity. Moreover, specific bonding techniques using for instance liquid water films can be used only in D2W bonding. If these specific features are under control, very innovative structures can be obtained. It is possible for instance to bond small 3mm*3mm InP dies onto 200mm silicon photonic wafers as shown in Fig.1a [3]. Moreover, hybrid bonding interfaces can also be obtained between 6mm*4mm dies and a 300mm wafer as shown in Fig.1b. Obviously, alignment in mandatory during hybrid bonding. This can be obtained thanks to a die to wafer bonder. However, innovative technologies such as capillary assisted self-assembly can also be really interesting [4
-7]. The electrical characterization of the D2W hybrid bonding connection will be also discussed, showing roughly the same good results as for W2W hybrid bonding.
Acknowledgment
This work was funded thanks to the French National program “Programme d’Investissement d’Avenir IRT Nanoelec” ANR-10-AIRT-05.
References

1 F. Fournel, et al., ECS J. Solid State Sci. Technol. 4, P124 (2015).

2 L.D. Cioccio, et al., J. Electrochem. Soc. 158, P81 (2011).

3 B. Szelag et al., Hybrid III-V/Silicon technology for laser integration on a 200 mm fully CMOS-compatible silicon photonics platform, IEEE J. Sel. Top. Quantum Electron., In Press (2019).

4 A. Jouve, et al., ECTC (2019).

5 T. Fukushima, et al., in 2011 IEEE 61st Electron. Compon. Technol. Conf. ECTC (2011), pp. 2050–2055.

6 E. Bourjot, et al., ECTC(2021)

Figure 1