(Invited) Addressing Key Process and Material Challenges to Enable 2D Transition Metal Dichalcogenide Channels in Advanced Logic Devices
Authors: Morin Pierre , Groven Benjamin , Medina Henry , Shi Yuanyuan , Voronenkov Vladislav , Kandybka Iryna , Delabie Annelies , Vranckx Dries , De Vos Brecht , Nijs Sebastiaan , Maurice Thibaut , Cott Daire , Banerjee Sreetama , Smets Quentin , Schram Tom , Wu Xiangyu , Lin Dennis , Asselberghs Inge 
Published: November 2022

Two dimensional ultrathin layers are considered promising materials to bring new functionalities in nanotechnologies and candidate to replace 3D materials in existing applications. Among this last category, transition metal dichalcogenides (TMDC) like WS2, MoS2, WSe2 are viewed as interesting alternative channels for ultra-scaled CMOS technologies, as silicon is approaching its physical limits. These semiconductor 2D monolayers could bring a decisive advantage in terms of electrostatic control at very low gate length, while maintaining decent carrier transport properties as compared to 3D materials at same dimension. In addition, TMDC should provide improved off current performance as compared to silicon, an important factor to improve the static power efficiency in multibillion transistor chips. Obviously, replacing the channel material of the main device in microelectronics, from silicon to TMDC, comes with a very long list of scientific and technological challenges to be addressed. In this paper we limit our scope to the growth of TMDC, one of the main pillar in this global effort, and share how we addressed some of the challenges related to the formation of 2D semiconductor channels, to enable the fabrication of functioning devices on lab and 300 mm flows.
TMDCs thin films grown with metal oxide CVD on substrates with, in some case, the presence of NaCl salts, are demonstrating the largest grain size and the best electrical performance but these processes are hardly compatible with industrial CVD reactors. In contrast we use chemistries more compatible with manufacturing, with the target of growing TMDC on 300 mm substrates. We report on MoS2 and WS2 formed with chemistries using metal organic precursors such as Mo(CO)6 or W(CO)6 and di-hydrogen sulfide grown in customized epitaxial cross flow 200 and 300 mm reactors [1]. We report basic nucleation and growth studies over a large process domain which show the possibility to control the density of nuclei and the subsequent lateral crystal growth while minimizing secondary nucleation and metal particle defectivity.
We study the deposition of MoS2 an WS2 on two basic types of substrates defining fundamentally the integration schemes. On one route, dedicated to device performance demonstration, TMDC monolayers are grown on templated substrates like sapphire following a van der Waals epitaxy mode which enables regular orientation of the crystallites and formation of large and oriented domains after grain ripening with reduced defect concentration. The 2D layer is then transferred onto the final substrate for the device formation. With this technique, average mobilities above 30 cm2/Vs have been achieved regularly on MoS2 backgated devices, and the best devices exhibit currents at transfer curve up to 420 mA/mm [2,3]. On the other flow, recent efforts have aimed at growing WS2 directly on various types of amorphous substrate layer typically deposited on 300mm wafer, acting either as bottom gate dielectric or sacrificial layer. This scheme doesn’t require subsequent transfer step. However, after integration, these materials demonstrate performance still substantially lower than with material grown on sapphire [4,5].
As the device dimensions has scaled down over the last 20 years, improving the variability at different scales has emerged as major topic in microelectronics. TMDC channels are no exception to this trend despite intrinsic advantage in terms of thickness control. We will share on specific work done on sapphire surface specification and preparation. We have demonstrated that depositing MoS2 on 1° off-A axis C-plane sapphire substrate reduced the dispersion in mobility as compared to similar materials obtained on C-plane oriented on-axis substrates [6]. We have also worked-out in-situ Cl2 etch process to remove the superficial islands grown on top of the first layer MoS2 crystals as this first layer is being closed. The process enables full lateral etching of the secondary layer crystals selectively to the closed first layer. With this process, we observed substantial improvement in the electrostatic control of MoS2 scaled transistors, including threshold voltage variability and improved subthreshold swing control [7].
We continue to work out the TMDC growth process to improve the material quality, impacted by the presence of defects at the grain boundaries or intra-grain, aiming to close the gap with advanced logic requirements.
1-Caymax & al., SSDM, D-1-03, 2019
2-D Lin & al., Symposium on VLSI Technology, 1-2, 2021
3- Wu & al., IEDM, 7.4.1-7.4.4, 2021
4- Asselberghs & al., IEDM, 40.2.1- 40.2.4, 2020
5- Smets & al., IEDM, 34.2.1-34.2.4, 2021
6- Shi & al., ACS nano 15 (6), 9482-9494, 2021
7- Shi & al., IEDM, 37.1.1-37.1.4, 2021