(Invited, Digital Presentation) Improved Reliability of 4H-SiC Metal-Oxide-Semiconductor Devices Utilising Atomic Layer Deposited Layers with Enhanced Interface Quality
Authors: Renz Arne Benjamin Benjamin , Vavasour Oliver J , Gammon Peter Michael , Li Fan , Dai Tianxiang , Baker Guy W C , Grant Nicholas E , Murphy John D , Mawby P. A. , Shah Vishal Ajit , Gott James 
Published: July 2022

A major component of reliability of Silicon Carbide (4H-SiC) power electronics are due to the gate dielectric. Specific aspects such as hysteresis, insulator lifetime, threshold voltage (VTH) instability and high leakage currents, remain an issue of paramount importance which hamper the uptake of 4H-SiC power MOSFETs.1 The oxide understood to have the most importance is coincidently the native oxide, SiO2, due to the suitable band offset to 4H-SiC. However, most of the SiO2/SiC interface problems, such as carbon clusters, H content and O vacancies, are directly related to the thermal oxidation process.2 Here, we show these issues can partially be avoided by using dielectric deposition instead.
Atomic layer deposition (ALD) offers specific advantages such as very low deposition temperature, excellent process control and suitability for conformal deposition of gate oxides in trench structures.3 Deposited oxides still require a post-deposition anneal (PDA) in a nitrogen-containing ambient4 such as nitrous oxide (N2O) or nitric oxide (NO) [2] to passivate the defects within the stack and improve the as-deposited layer’s poor electrical quality. We present the excellent reliability performance of ALD-deposited SiO2 layers on SiC through fabrication of metal-oxide-semiconductor capacitors (MOSCAPs) and then using time-dependent dielectric breakdown (TDDB) characterisation. The distribution of interface parameters, as well as the results from TDDB, have been investigated as metrics of improvement following the N2O PDA process. For benchmarking, processes will be compared to thermally grown oxides4 and LPCVD-deposited dielectric layers to demonstrate the superior process quality.
An active 10 µm thick epitaxial layer of 4 × 1015 cm-3 n-type doping is used in this study and grown on 100 mm diameter, 4° off-axis (0001) 4H-SiC wafers. Growth was performed using a 30 μm/hr growth and N2 as a dopant in an LPE ACiS M8 chemical vapour deposition (CVD) reactor. After an initial clean, a 1 µm thick field oxide was deposited and a window was opened via photolithography and reactive ion etching (RIE). Then, quarter wafers underwent one of the three oxidation routines: 1. SiO2 plasma deposition at 200 °C using bis(diethylamino)silane (BDEAS) and O2 plasma precursors in an Ultratech Fiji G2 Plasma-Enhanced ALD System. 2. SiO2 deposition at 750 °C using tetraethyl orthosilicate (TEOS) as a precursor in a Thermco LPCVD system. 3. direct thermal growth of SiO2 in a HiTech furnace at 1300 °C for 5 hrs in N2O ambient. Samples that had undergone one of the first two routines then underwent a PDA in N2O, in the HiTech furnace at 1300°C for 2 hrs. All oxidation measurements resulted in oxide thicknesses between 50 and 60 nm, which were verified using step-height AFM measurements and optical interferometry. To create the vertical MOSCAP structure samples had a 500 nm aluminium (Al) backside contact deposited, before a 1 μm Al layer was deposited on the topside of the samples by means of a liftoff process. A cross-sectional diagram of the fabricated final device structure is shown in Fig. 1 (a). Table I shows the key electrical parameters which were extracted using room temperature C-V measurements, combined with I-V and constant field TDDB measurements at 175 °C. Fig. 1 (b) shows the improvement brought about by the N2O anneal, which also results in the average flatband voltage being reduced by more than 10 V to the lowest value of the dataset (1.44 V) and frequency dispersion mostly removed, with all but the ALD as-deposited samples reaching average breakdown oxide fields of about 10 MV/cm. The most promising improvement of the ALD-deposited SiO2 can be seen observing the breakdown distribution of MOSCAPs when stressed at constant high electric field (9 MV/cm), which can be seen in Fig. 2 (a) and (b). Here, these samples reach a TDDB, 63% value of 4786 s, which represents an average increase of 28% when compared to LPCVD samples and 58% when comparing this to a purely thermal process.
Further evidence will be presented that high-quality, high-reliability SiO2 layers, formed by ALD and PDA have been formed. Flatband voltage and hysteresis are reduced, compared to thermally grown oxide, and frequency dispersion in accumulation is negligible. The ALD oxide with PDA has higher reliability than LPCVD and thermal oxides in TDDB tests, offering 29% to 345% improvement. The degradation mechanisms of the ALD oxide are different to that the LPCVD and thermal oxides and will be discussed in this talk.
[1] P. Moens et al, ISPSD 32, 78-71 (2020).
[2] P. Fiorenza et al, Appl. Surf. Sci., 149752 (2021).
[3] A. Renz et al, MSSP 122, 105527 (2021).
[4] K. Tachiki et al, Appl. Phy. Expr. 13.12, 121002(2020).

Figure 1