(Invited) Cryogenic Electronics for Quantum Computing ICs: What Can Bring FDSOI
Authors: Casse Mikael , Cardoso Paz Bruna , Bergamaschi Flavio , Ghibaudo Gérard , Balestra Francis , Vinet Maud 
Published: September 2023

To design efficient quantum computers, conventional electronics is required as close as possible to the quantum bit (qubit) devices, considering either superconducting or Si-spin qubits, for the read-out and control, thus reducing the need for wiring toward room temperature [1]. This need highlights the broad importance of exploring and developing low-temperature CMOS technologies, with operation temperatures ranging from 4.2K down to well below 1K. Moreover, the Si-spin qubit process is also compatible with the CMOS process, allowing both of them, in principle, to be monolithically integrated on a single chip [2], [3]. This could provide an essential building block for any large-scale quantum processors, by enabling the design of scalable close-to-qubit cryogenic electronics for massive qubit matrix indexation and, ultimately, development of fault-tolerant universal gate-based quantum computers [4].
In this approach, FDSOI technologies appear as a valuable solution, with their unique property of being able to adjust its threshold voltage (Vth) as a function of the temperature by the mean of a back bias VB. FDSOI thus enables high performance and low-power electronics. However, there is currently no process design kit to design CMOS circuits at cryogenic temperature, whatever the technology node considered. Therefore, extensive electrical characterization is required, with the aim of building a future cryogenic compact model, or at least of providing analytical and physics based models to designers in order to help them to optimize their circuits [5].
In this work, we present an overview of the performances of FDSOI CMOS technology down to deep cryogenic temperature, with specific attention to devices electrostatics, variability or thermal effects. Because these aspects are essential for the development of compact models and robust design tools, we present recent progresses in electrical characterization and analysis of FDSOI MOSFETs down to 100mK, and the underlying physics, highlighting the effect of the back bias VB.
We show that transistors can fully operate down to 100mK, keeping the same efficiency of the back bias on the threshold voltage [6]. Overall performances are mostly improved at low temperature, with e.g. a high reduction of the subthreshold slope and of the off current, or a higher transconductance maximum value due to higher carrier mobility. The tunability of the threshold voltage on a wide range through the back-bias offers a great advantage to the FDSOI technology, allowing improved performances [7] and the optimization of circuit in cryogenic environment [8], [9]. Other important electrical characteristics have also been investigated down to very low temperature, such as variability and mismatch properties [7], [10], or low frequency noise [11]. As a result, we show that FDSOI technology can outperform other CMOS technologies in cryogenic operation.
Thermal effects, which play a fundamental role in cryogenic electronics – operating at various temperature stages, with limited cooling power. The study of self-heating effects at cryogenic temperature in this regard provides valuable information on how to manage thermal effects, and is discussed [7], [15].
Finally, modeling issues are also addressed. Besides serious numerical difficulties due to singularities appearing at low temperature when solving model equations, the change of important physical parameters (like carrier mobility, thermal conductivity,...) needs to be correctly taken into account in future compact or analytical models. In addition, new physical effects evidenced at low temperature also need to be understood, analytically modeled and included as well. In particular, transport exhibits evidence of strong intersubband scattering in the channel of thin film FDSOI transistors [12]. The equations describing the sub-threshold regime are also strongly modified [13], [14].
[1] E. Charbon et al., IEDM, 2016.
[2] P. Galy et al., IEEE J. Electron Devices Soc., 2018.
[3] L. Le Guevel et al., Appl. Phys. Rev., 2020.
[4] X. Xue et al., Nature, 2021.
[5] C. Enz et al.,
EDM, 2020
[6] B. Cardoso Paz et al., EUROSOI-ULIS, 2020.
[7] M. Cassé et al., to be published in IEDM, 2022.
[8] H. Bohuslavskyi et al., IEEE Trans. Electron Devices, 2018.
[9] L. Le Guevel et al., ISSCC, 2020.
[10] B. Cardoso Paz et al., VLSI, 2020.
[11] B. Cardoso Paz et al., IEEE Trans. Electron Devices, 2020.
[12] M. Cassé et al., Appl. Phys. Lett., 2020.
[13] H. Bohuslavskyi et al., IEEE Electron Device Lett., 2019.
[14] G. Ghibaudo et al., Solid. State. Electron., 2020.
[15] K. Triantopoulos et al., IEEE Trans. Electron Devices, 2019.