Enabling Fine Line RDL and High Aspect Ratios for CU Pillars for Heterogeneous Integration
Authors: Benthaus Fabian , Hichri Habib , Arendt Markus , Gingerella Matthew 
Published: January 2025

Next generation devices demand for higher bandwidths and increasing functionalities which requires integration technologies to overcome limitations in Moore’s Law. Approaches for enhancing device capabilities, in particular power consumption, form factor, performance and functionality, drive integration in the third dimension. One popular example for 3D Integration is Package-on-Package (PoP), where memory stacks are mounted above the processor. Heterogeneous Integration (HI) through System in Package (SiP) is one of the key technologies to enable high density system integration for next generation fan-out (FO) application standards, using higher bandwidth and higher chip-to-chip interconnection density. High IO density applications have started to use packages with fan-out solutions. Future applications will be more complex including FPGA, high level processors and high demanding CPU/GPU and the memories associated. High performance heterogeneous systems, especially those with embedded large dies will require very large package sizes, greater than 50x50mm². This creates performance pressure on materials and equipment, to overcome challenges and provide solutions to eliminate design rules while maintaining fine resolution, large depth of focus (DOF) and high overlay accuracy. New and future device packaging technologies demand for low cost of ownership lithography applications, providing fundamental requirements in advanced packaging for next generation fan-out application. Future devices require high resolution for fine line redistribution layers (RDL), enabling high density heterogeneous packages, as well as large depth of focus (DOF) for process stability. To reduce production cost for larger packages, lithography systems need to provide large die scalability and production of non-repeated, heterogeneous patterns without stitching. The elimination of stitching will reduce the production process and related yield loss. Furthermore, lithography tools need to support the trend of fan-out wafer-level packaging and provide new features for die shift compensation which occurs during pic and place of the die to the carrier wafer and during the reconstitution by molding. Therefore, die shift compensation is essential for fan-out wafer-level packaging applications allowing high accuracy overlay. This paper presents technical challenges and provides solutions for future high density heterogeneous fan-out applications, using a full-field UV projection scanning system for large package integration. Furthermore, high resolution for fine line RDL down to 1.5/1.5μm line and space is demonstrated. Aspect ratios as high as 10:1 are shown for square vias with 1:1 pitch for tall copper pillars in thick resist applications. Full process window for 2/2μm L/S RDL is determined. Solutions to enable limitless design for large heterogeneous packages without the need of stitching as well as alignment for high overlay accuracy is presented. In addition, unique capabilities and features of the UV projection scanning technology as well for production as R&D purpose is demonstrated. The extendibility to large panel packaging integration is discussed.