bluuebunny/crossref_metadata_2025_split huggingface dataset:
Open-Cavity Plastic Packages: A Robust IC Packaging Solution for High-Reliability Applications
Authors: Sadri Sam , Tammen Tom 
Published: May 2023

Fast-turn prototype package assembly is frequently employed for rapid IC design verification. Open-cavity plastic packages (OCPP) are an attractive assembly option when commercial off-the-shelf (COTS) prototype packages are not available. Any existing IC plastic packages, whether dummies, electrical test rejects or excess inventory, can be quickly converted into robust open-cavity packages, ready to be assembled with new die, creating new packages that will fit an established footprint. This allows them to be easily inserted into test sockets and boards, so that no retooling or redesign is required. OCPP is also a practical option for production when no onshore sources exist for a company’s required plastic package assembly. This paper will delve into a case study example that details the process by which QP Technologies’ OCPPs were selected and qualified for avionics ASIC provider DEI when its prior package/assembly provider went out of business. The resulting packages passed MSL-3 solder stress tests with results equivalent to factory-fresh parts.
Heterogeneous Integration of III-V Lasers in a 300 mm CMOS Manufacturing Line
Authors: Baranowski Sarah , Nguyen Anh , Hossain Mohammad Jobayer , Kruger Seth , Carpenter Lewis G , Dikshit Amit , McDonough Colin , Harame David L. 
Published: May 2023

AIM Photonics has developed a high precision laser attach process using an ultra-precise ASM Amicra NANO 300 mm die-to-wafer flip-chip bonder and integrated solder stamping system. Laser die are placed with high accuracy (<1 µm) and soldered to form a AuSn eutectic bond. This photonic platform has low optical losses, with SiN waveguides measuring on the order of 0.4 dB/cm and a calculated laser-to-waveguide coupling loss of 1.86 dB.
The Study of Highest Thickness Photo Resist for Cu Post of Fan-Out Wafer Level Packaging
Authors: Heo Yuseon , Lee Jiyoung , Park Jieun , Park Junhyeong , Shim Jihye , Kim Sueryeon 
Published: May 2023

The mobile device’s limited thermal budget hardly allows the use of a high-performance application (AP) at its full speed. However, as artificial intelligence technologies has been rapidly applied for mobile devices, the demand like high-speed and large-capacity signal processing is continuously increasing. Therefore, controlling the heat generation of AP chip is becoming a key factor, and it is necessary to develop a Re-Distribution Layer (RDL) based Fan-Out Package (FOPKG) structure that does not increase the thickness of the package while maximizing the die thickness for heat dissipation. The height of Cu post is getting higher for the production of FOPKG that can apply thick die, and in this study, the world’s thickest photoresist material (>350um thickness) was developed for the production of Cu post (>300um thickness). The effect of light transmittance of the photoresist and the effect of solubility depending on the molecular structure of the main polymer were studied for lithography process of thick photoresist. Based on the understanding of this thick photoresist behavior, the optimal liquid type photoresist composition was developed. Through lithography evaluation based on thick photoresist characteristics, deep-hole via implementation and Cu electro-plating were performed to obtain a yield of Cpk 1.27 in the AP product design applied wafer. Depending on this in-depth understanding and experimentation on thick photoresist, it is possible to build an advanced research foundation of increasing the photoresist thickness and finer Cu post pitch to secure heat dissipation characteristics and improve the degree of freedom of architecture.
Modeling the effect of hatched grounds on the radio-frequency performance of microstrip lines on flexible substrate
Authors: Abdelatty Mohamed Y. , Umar Ashraf , Obeidat Abdullah S. , Enakerakpo Emuobosan , Alhendi Mohammed , Poliks Mark. D. 
Published: May 2023

Cross-hatching of PCB grounds refers to a process in which certain ground planes appear as copper lattices; regular openings are placed at regular intervals. Nowadays, the efficacy of ground hatching on rigid PCBs is minimal. However, it is becoming essential for flexible hybrid electronics. Utilizing hatched grounds for flexible applications could offer some benefits. Hatched grounds can perform dual roles, act as ground surfaces, and offer structural support. Hatched grounds are more durable for bending and stretching applications. Also, hatched grounds are desirable in terms of material conservation. In this paper, we focus on studying how hatched grounds affect the RF performance of a straight microstrip line. Simulations show that cross-hatched grounds with more than 50% filling produces good radio-frequency performance. We will study the effect hatching pattern as well as the density of the hatching on the RF performance of the microstrips. The theoretical modeling is considered in this work and fabricating aerosol jet silver ink microstrip lines on PET substrates will be considered as an extension of this work.
Additive Packaging for Bare Die and Additively Integrated Antenna
Authors: Areias Christopher , Lamport Emily , Piro Yuri , Cason Michael , Armiento Craig , Akyurtlu Alkim 
Published: May 2023

This paper presents the use of Additive Manufacturing (AM) in packaging applications. Specifically, the design, fabrication, and test of an AM packaged receiver phased array front-end will be shown. As part of this work, an LNA and phase shifter bare die will be directly integrated on board with the antenna array. The bare die integration is conducted through attaching the die to a pocket milled into the dielectric of a copper laminate. Filet bridges between the chip and board are then applied using a photocurable dielectric ink, and aerosol-jet silver conductors are printed overtop. Rigorous modeling of the phase shifter and LNA die are conducted and compared to measured data. The two-element array will be printed alone with spacing and amplitude/phase excitation for broadside radiation and the measured results for the antenna will be compared with simulated results from Ansys HFSS modeling tool. Finally, the fully integrated system will be assembled on a single substrate and tested
Finding a Happy Medium for Heterogeneous Cache Integration using M-Series Fan-out Technology
Authors: San Jose Benedict , Davis Robin , Bishop Craig , Olson Tim 
Published: May 2023

For high performance computing, it is desirable to disintegrate the cache memory from the monolithic SoC and reintegrate it through heterogenous integration technologies. Relocating the cache out of the monolithic SoC leads to the reduction of the advanced silicon die size leading to higher yield and lower cost. In this study, we evaluate ways to bridge the gap between high-end 3D silicon interconnect solutions and low-end substrate solutions with Deca’s molded M-Series™ embedded cache fan-out solutions. Deca’s M-Series Chips First Face up FOWLP planarized structure is an ideal platform to build an embedded interposer for the heterogenous integration of the processor chiplets, cache memory, and deep trench capacitors. Deca’s Adaptive Patterning® allows for scaling to high density interconnect between the processor chiplet and the cache memory. Three different configurations of the embedded cache interposer are considered. The vertically stacked face-to-face configurations minimize the interconnect length between the processor and the cache, while the lateral configuration provides a copper to copper build up interconnect between the chiplet and cache enabling further scaling down of the interconnect pitch. Both configurations have their specific benefits and disadvantages which are described in detail in this work.
Fabrication of Panel-Level Glass Substrates with Complete Design Freedom using LIDE
Authors: Santos Rafael , Anspach Nils , Ambrosius Norbert , Schmidt Stephan , Ostholt Roman 
Published: May 2023

In this work, we present examples of highly reproducible, accurate and extremely cost-effective wafer- and panel-level fabrication of glass interposers, free of any process-dependent design limitations where any distribution and density of Through-Glass Vias (TGV) with any cross-section geometries and aspect-ratios, is possible. Glass has recently garnered significant interest for its many applications in the semiconductor packaging industry, particularly as a core substrate material for interposer applications. Glass has a unique set of material properties with great relevance for this industry, such as very high electrical resistivity, low loss tangent and low dielectric constant. Glass also exhibits low warpage due to its relatively low Young‘s Modulus while still being compatible with Silicon in terms of CTE and, when processed using a technology that doesn’t induce the generation of any defects such as microcracks or thermally-induced stress, it is highly reliable during processing and operation. Laser Induced Deep Etching (LIDE®) technology is a 2.5D glass processing technology with complete design freedom purposedly developed for cost-effective, high-volume fabrication of defect-free glass components. Despite its many advantages as an interposer material in relation to Si, its application has been hindered by the lack of reliable, precise, and cost-effective processing technologies. LIDE® consists of a two-step process: i) a very fast maskless and direct-write laser process induces subtle and very localized modification in the glass substrate, requiring a single laser pulse to modify the whole glass thickness; and 1. ii) a wet-etching process done in batch, where the whole glass substrate is subjected to the action of an etchant and where the removal of glass occurs at an accelerated rate in the laser-modified regions. This process flow allows LIDE to fabricate several thousands of TGV per second, completely free of any defects, with a sub-micron point-to-point accuracy and ± 5 µm accuracy (cumulative) across a 510 mm x 515 mm glass panel (Cp > 1.33), in any glass type, with aspect-ratios from 1:10 to 1:50 (diameter:depth).
Study on CPI behaviors of X Dimension Fan-Out Integration (XDFOI) packages
Authors: Chen Haijie , Hu Zhen , Wang Chen , He Ming , Xie Jielei , Lin Yaojian , Lee Choon Heung 
Published: May 2023

XDFOITM (X Dimension Fan Out Integration) is a package family designed for fan out packages and heterogeneous integration, as XDFOI offers great flexibility to let single die or multi-functional chips, such as logic, memory, power management, RF and passive components, to be packaged by technology evolutions. Based on the approaches of “chip first” and “chip last” processes, XDFOI is designed with the high density I/O and multi-layer metals, polyimide and encapsulation materials like ABF, underfill or molding compound. Various materials applied in the full process flow brings lots of combination of CTE (coefficient of thermal expansion) and meanwhile the CTE mismatch may generate stress on the dielectric materials to influence the performance requirements. It is widely known that manufacturing procedures of heterogeneous integration make the boundaries of foundry backend process of line (BEOL) and bumping process fuzzy. In this paper, three package members in XDFOI family are introduced and the respective process flows are illustrated detailed in order to exhibit the differences between the solutions. Finite-element analysis is integrated along with package building process to predict the stress performances. The simulation results of XDFOI packages divided by packages provide a guideline for estimating maximum stress on the dielectric materials. In order to provide proper guideline to chip packages, data from theoretical calculation are collected, analyzed and merged into design rules for further process optimization and new product introduction. It is considered that the study can greatly improve the overall innovation level and process capabilities.
Thermal Performance of Liquid Metal Pastes Containing low Content of Metal Particles for Thermal Interface Materials in IC Module Electronics
Authors: Fan Guangyu , Kurish Jeff , Tagliaferri Sofia , Green Kyle , LaBarbera Christine 
Published: May 2023

In recent years, considerable attention has been paid to gallium-based liquid metal alloys in their use as thermal interface materials for GPU, APU, and HPC in PC and super computers due to its considerably high thermal conductivity and low contact thermal resistance. Gallium-based Liquid metal paste containing low content of metal particles (LMP-MPs) to enhance thermal performance and controllable BLT of the prepared liquid metal composites for thermal interface materials (TIMs) prepared by in-situ introducing gallium oxide into the liquid metal alloys will be reported in our recent research. In this paper, we will report effect of the composition, particle size/types, and bond line thickness on thermal properties of the LMP-MPs. Thermal properties of the LMP-MPs were measured at 50o C using a thermal tester, TIMA5, based on ASTM-D5470 test methodology. It was found in the present study that the composition and types of metal particles, and BLT have significant influence on thermal conductivity, and the conductivity values increase with an increase of the content of metal particles and BLT. However, thermal resistance varies with the change of composition and BLT of LMP-MPs. Scanning electron microscope (SEM) was used to characterize microstructure of LMP-MPs with different metal particles and sizes. Micrographic morphology of the LMPs-MPs shows continuous frame structure observed with SEM, which could keep liquid metals from spreading out and stabilize the phase. We eventually found the LMP-MPs have the better wetting and adhesion properties on bare Cu, glass and bare Si surface than liquid metal alloys that endows good printability to the LMP-MPs. Continuous monitoring of thermal resistance of LMP-MPs at 45o C and 89o C using a house-made thermal tester shows stable thermal resistance after a few months, which indicates LMP-MPs have excellent thermal reliability in ambient atmosphere.
Smaller than MLCC: CCW (Ceramic Capacitor Wire)
Authors: Park Soojae , Lee Jonghyun , Cho Chulhyung , Kim Namhoon , Kim Jaehoon , Park Soomoon 
Published: May 2023

The world’s smallest discrete capacitor was invented in a cylindrical form factor for high-frequency power delivery, contrary to a planar capacitor such as MLCC. A dielectric layer of Al2O3 (5~50nm ALD) was deposited on conventional Au metal wires (18~40µm), and subsequently, a 2nd electrode metal (0.5~1µm) was sputtered on the Al2O3 layer. Advanced wire bonding was used to assemble CCW to PCB pads for electrical connections required capacitors. Electrical simulations were used to characterize CCW in terms of electrical performances. The capacitance measurements were compared between CCW & MLCC in conjunction with electrical simulation at high frequencies for RF & HPC applications. CCW can also be embedded into PCB and integrated into package chips.
Printed Microstrip Interconnects for Improved RF Performance in mm-Wave Packaging
Authors: Christenson Kurt , Bourassa Justin , Hamre John , Dean Mike 
Published: May 2023

Printed microstrip interconnects are gaining attention as designers seek a more-compact, lower-loss scheme to replace wire bonds. Aerosol Jet® printed interconnects have the potential to lower insertion losses by creating conductors with arbitrary geometries and zero loop height. Printed dielectric and conductor materials typically have inferior electrical properties compared to bulk-deposited materials. There is a question whether these properties will produce unacceptable S21 losses in printed interconnects. This work presents calculations of the effect of the printed material’s properties on S21. HFSS modeling from 0.1 to 100 GHz was conducted on two representative interconnect structures. A trench in an RF substrate filled with dielectric and a dielectric ramp from a substrate up to a GaAs die. The microstrip (or transmission) line over a filled trench represents the filled region around a die that sits down in a “pocket” in the dielectric and contacts the ground plane. Conductors modeled include a pure copper reference along with conductors with four and ten times the resistivity of bulk silver. The dielectric constant of the insulator varied from 2.8 to 4.3 and the loss tangent varied from 0.004 to 0.04. For simplicity, an unpatterned GaAs die was used in place of an RF IC. The work focuses on estimating any degradations in performance of an ideal reference circuit caused by the material properties of real printed materials. Also presented are the dielectric properties of our current materials along with properties of candidate materials that have better thermo-mechanical properties (shrink, CTE, Tg…).
Simple Solution to Estimating and Predicting Transient Current in Small Signal AC Circuits
Authors: Ganescu, PhD Virgil C. 
Published: May 2023

Transient current through a small signal RLC series ac circuit is investigated. The current is calculated analytically from the governing differential equation of the circuit. Furthermore, the analytical solution is compared and validated, for the steady state, against the numerical solution generated by Multisim. Lastly, results and discussions are focused on the transient analysis (t —> 0s), when currents peak.
Assembly Solutions for Cost-Effective Heterogeneous Integration with Disparate Die Types
Authors: Farris Glenn 
Published: May 2023

The semiconductor industry is driving to enable high volume integration of disparate die types via Heterogeneous Integration. These die can come from a range of wafer sizes fabricated in different technology nodes. This emerging package type creates new challenges regarding assembly efficiency and yield. Traditionally, flip-chip assembly process flows have utilized a single placement tool for the placement of the single die type onto the target substrate. For applications with multiple die types, a series of placement tools have been configured in a production line, with each tool dedicated to the placement of a specific die type. This paper and presentation explore the implications of this type of solution in the era of Heterogeneous Integration. Impacts on product yield, throughput, manufacturing efficiency, and overall cost of assembly will be explored for a broad range of Heterogeneous Integration die configurations. Based on a sensitivity analysis for the range of die types expected in these applications, a novel approach to optimization of overall assembly economics will be proposed. Appropriateness of this novel approach will be explored for a range of packaging solutions, including Flip-Chip, 2.5D, 3D, and Fan-Out.
Inspection Solution for 2μm RDL from Wafer-Level to Panel-Level Fan-out Process
Authors: Lin Leon , Liu Anderson , Chen Jay , Wu Maruko , Kim Cheolkyu , Liu Zhuan 
Published: May 2023

In the advanced packaging industry, both fan-out wafer-level packaging (FOWLP) and fan-out panel-level packaging (FOPLP) have grown quickly in recent years since they are compatible with largescale, low-cost manufacturing and are key enablers for ultra-thin and high-density packages. However, the commercialization of the fan-out process continues to face technical challenges with the rapid adoption of finer pitch and width of the Cu redistribution layer (RDL) in die-first or die-last integration approaches. AOI has been widely used in the advanced packaging industry as a major tool for defect inspection during various process steps. The conventional bright field and dark field imaging techniques suffer from a high nuisance rate for RDL inspection; in many cases, the RDL metal grain size could be larger than the defect of interest, and the interferences from underneath the pattern, such as bottom RDL layers or molding compounds, can increase the difficulties of defect detection. In this paper, we present Onto Innovation’s innovative fluorescence technology to enhance contrasts between organic material, such as polyimide, or photoresists and metals that enable fine-pitch RDL inspection with increased accuracy by eliminating nuisance defects. By using powerful fluorescence technology, in conjunction with higher resolution, high-definition inspection (HDI) technology, fine-pitch RDL defect inspections on both wafer-level and panel-level packaging were studied and shown to enable accelerated development cycles in the R&D stage, as well enable rapid yield enhancements in the HVM environment.
Influence of Rigid Carrier Substrate and its Release Layer on Warpage of Fan-out chip last WLPs & PLPs
Authors: Matsuura Yoshinori , Yoshida Tatsuya , Komiya Yukiko , Nakamura Toshimi , Yanai Takenori , Okuyama Kazuhiro , Kitabatake Yukiko , Ishii Rintaro , Hayashi Katsuyuki , Kubota Takashi , Fujii Joji 
Published: May 2023

In recent years, the need for ultra-high density chip packaging devices and heterogenous integration devices require strategic placement of various components for high-performance computing (HPC), artificial intelligence (AI), etc. The fan-out chip last process with redistribution layer (RDL) first is expected as a solution to assemble these modules in advanced packages, which is essential for avoiding the risk of known good die (KGD) loss. During the assembly of the fan-out chip last WLP, elimination or minimizing warpage is an inherent challenge. It is caused by a thermal mismatch between various organic-inorganic – metallic – non-metallic – composite materials used in different layers of the package. If not controlled, then warpage from stresses induces alignment mismatch impacting package yield loss and reliability related issues. Warpage is minimized by using a rigid carrier substrate to build the RDL layers. The selection of this rigid carrier and its release layer influence the package warpage during the fan-out chip last WLP fabrication process. This paper focuses on the influence of rigid carrier substrate and its release layer on the warpage of fan-out chip last WLPs. Further, a solution towards controlling warpage has been provided using a novel material set referred to as HRDP® (High Resolution Debondable Panel). This is a drop-in approach compatible with the existing assembly flow. One of the important features of the HRDP® carrier is that it is offered in various dimensions and thicknesses. The HRDP® carrier is available for round wafers as well as for square/rectangular panel shapes in glass or silicon substrates to match the coefficient of thermal expansion (CTE) of the metal RDL, dielectric material, and Epoxy molding compound (EMC). This contributes to optimizing CTE related interfacial stresses and minimizes assembly warpage. Another key attribute of the HRDP® is its ease of debonding. Contrary to conventional debonding/release polymer layers, the HRDP® structure is composed of 100% inorganic material. It improves processing capability during RDL manufacturing, showing better chemical resistance and heat resistance than alternate technologies such as laser lift-off (LLO) type carrier