Glass Panel Embedding (GPE) for High-Frequency Applications
Authors: Ravichandran Siddharth , Watanabe Atom , Ogura Nobuo , Swaminathan Madhavan , Tummala Rao 
Published: January 2025

Embedded Wafer Level Fan Out (WLFO) packages have disrupted the entire semiconductor industry due to its benefits in size, cost, electrical and thermal performance, reliability and potential for heterogeneous integration when compared to traditional flip- chip and wire bond packages. Although it was initially designed to extend package I/O counts beyond fan-in Wafer Level Packages (WLP), the scope of WLFO technology has expanded significantly in recent years to include multi-die SiP modules with high-density RDL, as well as high I/O logic and memory integration. Most WLFO packaging technologies today use epoxy-based mold compounds as the carrier [1]. 3D integration in WFLO, today, is primarily pursued by means of a Through Encapsulant Via (TEV) which is a vertical interconnect through the mold compound in the fan-out area. However, the use of mold compounds limits the scope of current WLFP packages in a number of ways: (i) mold compounds have a huge CTE mismatch with silicon affecting reliability (ii) It is difficult to populate high-density fine RDL on mold compounds and also achieve good layer to layer registration (iii) mold compounds suffer from large area warpage that hinder panel-scale processing which may reduce cost by up to 2-4x, depending on the package and panel sizes, the number of die per package, and the number of RDL layers. In order to address these limitations, Georgia Tech has been developing the key technologies necessary for Glass based panel fan-out technology. Glass, when used as a substrate for die embedding, not only outperforms other organic solutions, but also provides many other benefits not found in existing WLFO technologies. The smooth surface (<5 nm) and high-dimensional stability (~1 um panel registration) of glass enables high-density silicon-like RDL wiring and BEOL-like I/Os even on large panels, thus increasing productivity and lowering cost, bringing an unparalleled combination of high I/Os and low cost. The CTE of glass can be tailored between 3 and 11 ppm/K, thus, improving reliability and enabling the direct surface mounting onto the board unlike some high-density fan-out packages that require an organic package to connect to the board for large body sizes. Glass also excellent moisture resistance that becomes an important consideration over mold compounds. Glass fanout packages can be fabricated either with or without a carrier. In the first case, cavities are formed in glass and dies are placed inside them. Following this, polymer RDL layers are built on either side of the substrate and interconnected through Through-Glass-Vias (TGVs) [2]. In the second case, through cavities are cut on a glass panel with TGVs and mounted on to a 1mm-thick glass carrier [3]. Dies are placed in the cavities and epoxy polymers are laminated on either side using a double carrier process following with RDL metal layers are built using a semi-additive process. Both these processes have their advantages and disadvantages in terms of ease of manufacturability, thermal limits and also package thickness. In this paper, we discuss in the detail the advantages and limits of these process flows and provide design guidelines for panel scalability from warpage modeling. The electrical performance of both these package structures are also compared considering an ultra-thin packaging topology and low-loss RF chain interconnected from a chip to antenna array, which consists of transmission lines, through-package vias, and microvias. Conductor-backed co-planar waveguides and striplines are formed in high-density interconnect layers with low-loss (Df=0.0025 @ 28GHz) dielectric build-up thin films. Through-glass vias and microvias are employed for vertical interconnects in the proposed packaging architecture. In summary, this paper presents the different process technology options for glass-based panel fanout packaging addressing electrical and thermal performance and panel scalability through warpage modeling. The paper also presents design guidelines for Glass fanout packages for high-frequency applications.