Die Crack Prevention and Detection in Advanced Packaging
Authors: Han Woo Young 
Published: January 2025

Semiconductor manufacturers are continuously driving efforts to put more computing power and speed into less volume. At the same time, consumers are demanding devices with more functionality that integrate a variety of interconnected circuit types. The result has been an increasing reliance on advanced packaging technologies that use fab-like processes to integrate multiple chips and to provide the increased I/O capability required. The demand for higher performance electronics in smaller packages has led to the development of wafer level packaging (WLP), panel level packaging (PLP) and fan-out level packaging. The need for low cost, smaller packages with high density interconnects for cell phones and wearable devices has been leading the development of advanced packaging. All of these advanced packaging techniques involve stacking multiple chips in vertical directions. In DRAM memory packaging, there are as many as eight dies integrated vertically and the manufacturers are trying to keep the thickness of the die as minimal as possible to keep an overall thin package profile. Backside thinning of fully processed wafers has become a widely used technique in the industry. Typical final wafer thickness in the early 1990s was around 450µm but current wafers are usually thinner than 50µm. As the final wafer thickness is getting thinner, they are becoming more fragile and susceptible to cracks and chips. Chipping and cracks can cause near-term yield and long-term reliability problems. If a chip or crack is discovered during the final processes of advanced packaging, the overall final yield will be lower. If it is not discovered, the end device may not be reliable in the real world and fail for the consumer, a more costly consequence. As wafers became thinner, the industry started seeing sidewall cracks, inner cracks and micro cracks starting from the kerf or street area initiated from wafer sawing. These types of cracks can cause air bubbles around the cracks during the molding process in fan-out packaging and eventually lead to mold cracking which can lead to lower yields. It would be very beneficial if these types of cracks are detected early and the affected die removed. However, these types of cracks are happening underneath the die surface and are difficult to see with traditional bright field and dark field illuminations because they are underneath the top surface. Consumer tolerance for device failure is at an all-time low, as they demand more functionality and more convenience from their electronic devices. Wafer level packaging (WLP), panel level packaging (PLP) and fan-out level packaging advanced packaging techniques all involve extensive use of bumps and die thinning to establish electrical connections in vertical directions. Packaging these vertically integrated die requires the need to provide interlayer connections that are as small and reliable as the multilayer interconnect technologies used within the chip. This need for vertical connections has created a whole new class of technologies; advanced packaging; with a whole new lexicon of terms and acronyms: through-silicon vias (TSVs), redistribution layers (RDLs), bumps, pillars, nails, under bump metallization (UBM), wafer-level packaging (WLP), fan-in, fan-out, and many more. All of these technologies serve the purpose of providing reliable, electrically isolated, vertical connections, and most, at some point, involve the creation of a conductive; ump; protruding through an insulating layer to carry the signal to the next layer above or below. As more chips are integrated vertically, overall package thickness increased as well and the common ways to reduce the overall package thickness are by thinning chips or die and reducing bump sizes. As die or chips are getting thinner, they become more fragile and susceptible to cracks or chippings. Cracks or chips can reduce the final package yields or cause long term reliability issues in the consumer devices. This paper describes inspection challenges for cracks underneath the die surface and possible solutions to overcome the challenges.