(Gordon E. Moore Medal for Outstanding Achievement in SSS&T) Moore’s Law Sustained by Non-Lithographic Technologies
Authors: Roozeboom Fred 
Published: September 2023

Since G. Moore’s historical observation [1] that the functionality per chip (bits, transistors) as well as MPU performance (clock frequency in MHz × instructions per clock = millions of instructions per second) doubles every 1.5 to 2 years, the semiconductor industry has continued to grow to over 600 G$ in 2022 [2].
The IRDS 2022 Roadmap [3] catches the scaling challenges faced for the upcoming decades by the term ‘3D Power Scaling’. This period is the third in a sequence of eras that started early on with straightforward geometrical scaling by continuous shortening of the wavelengths (from regular UV to deep UV/immersion) used in the lithographic patterning of planar transistor structures (Fig. 1a). In the second, almost past ‘equivalent scaling’ era, new superior material properties and critical dimensions nearing single-digit nanometer values could still be realized by cost-effective technology solutions, often in spite of the delay in (EUV) lithography solutions. Ever more complex device architectures requiring extreme edge placement accuracy, layer conformality and shape fidelity in all processing steps (deposition, etching) could be fully 3D-integrated into vertical intra- and inter-chip concepts (Fig. 1b) thus alleviating the need for new capital-intensive lithography tools capable of higher resolution (~ 40% of total tool costs).
Figure 2 illustrates the development in the past 65 years of the non-lithographic technologies that have sustained Moore’s Law, as driven by continuous downscaling of CMOS devices. Two extra trends have set in half way (~1993): single-wafer processing and heterogeneous device integration. The latter development, often coined as More than Moore, a term that was introduced in the 2005 ITRS Roadmap, and refers to the silicon-compatible integration of devices with functionalities that do not necessarily scale according to Moore's Law, but provide additional value in different ways. The More-than-Moore approach allows for the incorporation of non-digital functionalities (e.g., RF communication, passive components, power control, sensors, actuators) that can flexibly move from the system board-level into the package (SiP) or onto the chip (SoC).
We will discuss a kaleidoscopic view of the author’s activities in Rapid Thermal Processing, RIE etching for TSVs, RF-SIP integration of passives, and Atomic Layer Processing (deposition, etch, and cleaning). In sub-10 nm scaling and fabrication of 3D architectures, especially the techniques of ALD and ALE have manifested to cost-effectively bridge the record incubation time needed to bring EUV technology from prototype to commercial use. More importantly, these unique techniques can be used to create advanced devices in dedicated isotropic (thermal and radical-enhanced) and anisotropic (directional and ion-enhanced) processing modes. Here, energetic species (radicals and/or ions in a plasma) are used in one or two steps, with the ions yielding anisotropic profiles (used in FinFET logic and 3D NAND memory), and neutrals and radicals yielding isotropic profiles used to deposit or etch the features in horizontal nanowires, nanosheets and ‘forksheets’ in GAA-FETs.
1. G. Moore, Cramming more components onto integrated circuits, Electronics 38(8), (1965) 114-118.
2. https://www.semiconductors.org/global-semiconductor-sales-increase-24-year-to-year-in-october-annual-sales-projected-to-increase-26-in-2021-exceed-600-billion-in-2022/
3. International Roadmap for Devices and Systems (IRDS™) 2022 Edition - IEEE IRDS™.

Fig. 1. a) Different scaling ages for device manufacturing; b) the planar-to-GAA transition; after [3].

Fig. 2. Historic and future perspectives of non-lithographic key technologies in IC scaling.

Figure 1