Through Silicon Via Undercut Profile Optimisation for 3D Packaging Applications
Authors: Gray Paul 
Published: January 2025

In recent years through silicon via (TSV) has become a key enabling technology in the production of 3D integrated circuits, these features allow components to be stacked vertically [1], dramatically increasing the device performance while minimising power consumption and overall package size [2]. This study investigated the effects of process parameter changes on the overhang feature dimensions and across wafer non-uniformity in a positive profile TSV using a silicon substrate. Positive profile features are commonly used for TSV applications as no part of the sidewall overshadows any other point on its internal surface, these features frequently require a second process [3] to remove the ‘overhang’ or ‘undercut’ feature which commonly forms at the top of the profile due to a lateral etching effect [4] which will prevent a continuous metal barrier layer being applied to the TSV, it is critical to the function of the final device [5] that the layer is continuous, as voids in the film will cause defects in the filler material [6]. This research focused on the outcome of the interactions between various process parameters on the across wafer non-uniformity and final profile dimensions of the etched features. The goal of the programme was to determine the process parameter effects that allow the magnitude of the overhang feature to be manipulated in order to prevent its formation or limit its growth. The removal of the undercut feature would eliminate the need for any secondary processes required to remove the feature after the completion of the etch [7], which adds cost and time to the manufacturing cycle [8]. The process trials were completed using an SPTS Technologies Ltd Pegasus™ deep silicon etch system using 150mm TSV structure test wafers with a 3.28% open area. The etch reactor was cleaned using a 30-minute O2 plasma to remove any contamination from previous processes runs. After completion of the clean the process chamber was conditioned for 30 minutes using an SF6/O2/C4F8 switched process to passivate the internal chamber walls. An L16 (4^5) Taguchi Array [11] design of experiments (DoE) was used to understand the role of parameter changes on the etch profile. The values of the five chosen process parameters (chamber pressure, bias power, coil power, platen temperature and total gas flow) were centred around the process of record to determine the effect on the etch profile. Each parameter had four data points that were equally divided across the range, the ratio between the process gasses was fixed for the purposes of this test. The completed etched profiles were measured at three locations across the wafer surface Centre (C), Main Flat (MF), and Opposite Main Flat (OMF) to gain information about the uniformity and depth of the profile across the substrate surface. To define the shape of the etched profile, the TSV is measured in four locations, depth (D), top width (TW), maximum width (MW), bottom width (BW). The results from the sample process runs were measured using a Carl Zeiss Sigma scanning electron microscope (SEM). The full set of results obtained from the 17 sample runs were collected and analysed by the JMP Statistical Discovery™ software [12] for predictable interactions between process parameters and profile dimensions. The results and software model clearly show that there were no encompassing predictable interactions between the tested process parameters and the final dimensions of the positive profile etched features. Interactions between the parameters and final dimensions were present and often predictable, but a desirable effect in one area was usually accompanied by an undesirable affect within the same feature. One of the most critical dimensions for manufacturing processes is the across wafer non-uniformity of the features, the homogeneity of the devices is desirable for subsequent manufacturing steps. The software model shows that there is a good correlation (p-value <0.007) between decreasing non-uniformity and increasing platen temperature, but crucially the temperature increase has little to no effect on the other dimensions. The improvement on across wafer non-uniformity was approximately 1% for every 5°C increase of wafer platform temperature for the range tested. Passivation of the substrate surface is strongly dependent upon temperature, as it is raised the deposition rate of the passivation layer reduces, increasing the isotropic and anisotropic etch rates. As the volume of the silicon being etched increases, more of the etch species will be consumed from the reactor environment and this slows down the overall etch rate. The results of this effect were successfully modelled in the software model results; decreased passivation should show as increased etch rate, but counterintuitively the results are showing either very small increases or actual decreases in etch rate. This slowing of the etch rate is the likely cause of the decrease in feature non- uniformity across the wafer. As the etch rate decreases it reduces the effect of variations in plasma density across the whole surface, which homogenises the etch rate thus making the across wafer features more uniform. The initial purpose of this research was to identify and quantify the dominant process parameter changes needed to predictably eliminate the undercut/overhang feature that normally develops at the top of a positive profile TSV feature during etching. This research identified that a clear framework of adjustments was not discernible from the results, however there was a predictable interaction between raising the bias platen temperature and improvements in across wafer non-uniformity.