bluuebunny/crossref_metadata_2025_split huggingface dataset:
Social appearance anxiety and oral health-related quality of life in middle-aged adults with implant therapy
Authors: Kalyoncuoğlu Ülkü Tuğba , Samur Ergüven Sara 
Published: May 2023

Introduction: The success of implant therapy is strongly related to the perceptions and expectations of the patients.
Aim:&nbsp;This study aimed to assess the level of social appearance anxiety and oral health-related quality of life in middle-aged adults with implant-supported fixed prostheses and compare with individuals who have tooth loss without any prosthetic rehabilitation or who have natural teeth.
Materials and methods:&nbsp;The participants (n=292) were divided into three groups: group 1, individuals with implant-supported fixed dental prostheses; group 2, individuals with tooth loss; and group 3, individuals with totally natural teeth. A questionnaire form including basic questions, Social Appearance Anxiety Scale (SAAS), and Oral Health Impact Profile-14 (OHIP-14) was distributed among patients.
Results: Group 2 showed a significantly higher level of SAAS and OHIP-14 scores compared with groups 1 and 3 (p<0.001). The SAAS scores were similar between groups 1 and 3, with no significant differences. The median OHIP-14 score was the lowest in group 3. For all groups, education was related to SAAS and OHIP-14 scores (p=0.037 and 0.002, respectively). The SAAS and OHIP-14 scores were significantly and positively related (p<0.001, r=0.501).
Conclusions: It was concluded that patients with tooth loss had higher levels of SAAS and OHIP-14 scores. Besides, the SAAS scores were similar for patients with implant-supported fixed prostheses and those with natural teeth. Middle-aged adults with higher educational levels tended to present better oral health-related quality of life and lower social appearance anxiety.
L’adolescent : un temps d’« enfouissement »…
Authors: Bidaud Éric 
Published: May 2023

Cet article propose de montrer les enjeux de l’adolescent qui se confine et fabrique avec méthode un lieu de réclusion volontaire, jusqu’à offrir la figure d’un enfouissement au limite de l’angoisse d’un en-terrement , le lieu d’une ascèse. Ce que ce texte tente de suivre ici est moins la description d’une courbe ascétique : les privations, l’isolement et les attaques du corps, que là où ça se passe, le lieu de l’ascèse, là où la maison familiale se défait, recouverte par un nouvel espace.
Contribución al conocimiento de la subfamilia Polistinae (Hymenoptera: Vespidae) en la Reserva de la Biosfera del Manu, Madre de Dios, Perú
Authors: Amaru-Castelo Javier , Marquina-Montesinos Edgar , Bautista-Challco Benita , Quispe-Saenz Criss , Herrera-Huayhua Carolina Milagros , Colan-Rodríguez Renato 
Published: May 2023

La subfamilia Polistinae (Hymenoptera: Vespidae) es un grupo común de la fauna neotropical, caracterizados en su mayoría por su comportamiento social. En Manu Learning Centre, dentro de la Reserva de Biosfera del Manu, se han colectado dichos organismos empleando trampas Malaise, de caída y bandejas amarillas durante los meses de mayo a diciembre del 2021. Se encontraron diecisiete especies de la subfamilia Polistinae, de las cuales catorce se reportan por primera vez para el departamento de Madre de Dios (Perú). El género mejor representado es Polybia Lepeletier, 1836, con 7 especies.
Mixed reaction gold as versatile plating solution for ENIG, ENEPIG and EPAG plating
Authors: Schafsteller Britta , Rosin Mario , Schlosser Timo , Ramos Gustavo 
Published: May 2023

The surface finish on a printed circuit board (PCB) or substrate serves as surface protection and at the same time enables a variety of assembly techniques. Depending on which final finish is selected it allows for e.g. soldering connections or wire bonding by Al, Au or even Cu-wires. Surface finishes are typically characterized by different metal layers, including tin, nickel, palladium or gold. In this context the electroless or immersion plating of gold has a long history in the electronics industry. The gold plating represents a key step in different finish systems such as electroless nickel/immersion gold (ENIG), electroless nickel/electroless palladium/immersion gold (ENEPIG) and electroless palladium/autocatalytic gold (EPAG). ENIG, ENEPIG and EPAG finishes are characterized by their capabilities to be used as solderable and wire-bondable finish with specific benefits for ENEPIG and EPAG such as enhanced solder joint reliability and gold-wire bondability. In this paper an overview is given on the different types of electroless gold plating electrolytes from fully immersion type and autocatalytic type to mixed reaction type gold electrolytes. The details of the various plating mechanisms are presented, and the different properties and capabilities of these electrolytes are compared and explained based on the respective mechanisms. The presented study investigates the performance of a gold electrolyte of a mixed reaction type looking into the layer properties as well as the soldering and bonding capabilities. The results show that a mixed reaction gold electrolyte can be capable for versatile application- ENIG, ENEPIG and EPAG. The capability of the process was tested with respect to the solder wetting performance, solder joint reliability, wire bonding performance, corrosive attack to the nickel and thickness distribution. It can be shown that this gold process passes or exceeds all related industry standards and target requirements for ENIG, ENEPIG and EPAG final finishes.
Innovations in Soldering Materials and Optimization of Solder Paste Printing and Inspection Parameters for System-in-Package Assembly
Authors: Griffith Evan , Rowland Casey , Sbiroli David , Sjoberg Jonas 
Published: May 2023

System-in-Package (SiP) assembly has become a popular solution for the challenges of continued miniaturization in the semiconductor industry. The continued and expected growth of the semiconductor industry in the coming years is driving more advanced assembly methods within System-in-Package and advanced packaging in general, and more advanced semiconductor assembly materials are required to meet those challenges such as solder paste specifically designed for SiP assembly, with fine solder powder and specifically formulated flux vehicles. Fine feature solder paste printing as an assembly method continues to be a challenge for SiP assembly. Small stencil aperture designs have necessitated fine-powder solder pastes, with type 5, type 6, and type 7 being common, as well as there being a need for type 8 for future, more advanced designs. Additionally, as more components are being packed into a SiP, solder paste rheology becomes an important characteristic to consider. Printing transfer efficiency, stencil life, and resistance to slump, are other important paste attributes to consider when evaluating solder paste for SiP assembly. While material properties are important to consider, proper equipment setup for a certain paste formulation is also necessary to maximize throughput and minimize assembly defects. The effects of solder paste printer parameters on fine-feature printing performance will be discussed, such as print speed, separation speed, separation distance, and stencil material. This paper will first focus on common failure modes in SiP assembly, and the technology advancements in both solder paste formulation and substrate design which help eliminate those failure modes. Then, this paper will discuss how proper stencil printer setup can reduce assembly defects, and will highlight designs-of-experiment outlining which stencil printer parameters are statistically significant in improving process yields of SiP assemblies with fine powder solder pastes, both with respect to pre-reflow inspection and post-reflow component placement. This paper will also discuss the importance of solder paste inspection with respect to assembly defects, and will highlight important parameters to optimize to accurately inspect solder paste deposits below 90 microns.
Direct-Write Printed Wearable Metasurfaces
Authors: Kajenski Adria , Strack Guinevere , Khushrushahi Shahriar , Akyurtlu Alkim 
Published: May 2023

Direct-write printing was utilized in fabricating a wearable metasurface for frequency filtering at 6 GHz. Using radio frequency (RF) performance and sheet resistance, Rs as performance metrics, the printed metasurfaces were subjected to wash cycle and longevity testing. The metasurface was printed on two woven nylon industrial fabrics (70D (EX) and 200D (BW) thread masses) featuring a polyurethane (PU) coating on one side. Two conductive inks, CM127-48 (Creative Materials) and PE876 (Dupont) were printed on the fabrics and tested for Rs , RF performance, wash cycle stability, and longevity. Rs values for CM127-48 on EX and BW were similar (0.083±0.013 and 0.088±0.031 ohm/sq, respectively), while PE876 had higher Rs , on BW than EX (0.080±0.015 and 0.35±0.06 ohm/s). RF performance revealed that S21 magnitudes were at least −30 dB for all four ink–fabric combinations, in agreement with simulations. Wash cycle testing of PE876 on EX and BW revealed a comparable decrease in S21 magnitude for both fabrics. However, BW samples exhibited minimal shifts in peak frequency. Longevity tests on the four ink–fabric combinations demonstrated that S21 magnitudes were at least −29.5 dB, with the smallest change in magnitude for the CM127-48–EX sample. Materials selection may be tailored for various design goals in wearable electronics.
A Novel Analytical Method of Thallium Determination in Gold Electrodeposition
Authors: Saitta Patrick , Wang Jingjing , Shalyt Eugene 
Published: May 2023

Thallium is used in both cyanide and sulfite-based gold plating bath solutions as an additive that modulates how gold deposits on the target substrate. The level of Tl in the plating solutions has a large effect on the properties of the gold being deposited, including its microstructure and hardness. Thus, especially in commercial process applications, it is critical to be able to measure the Tl content of plating solutions accurately, quickly, and facilely in order to ensure proper quality of the products being manufactured. The cyclic voltametric behavior of Tl-containing gold plating bath solutions has been investigated, but quantification of its Tl content is unsatisfactory, either expensive and time consuming, or not accurate in complexed matrices. Here, we present a proprietary, electroanalytical method of Tl measurement that is fast and gives excellent accuracy and sensitivity, even in the presence of common bath breakdown products.
State-of-the-Art and Outlooks for 2.3D IC Integration
Authors: Lau John H 
Published: May 2023

The state-of-the-art and outlooks for 2.3D IC integration will be investigated in this study. Emphasis is placed on the design, materials, process, advantages and disadvantages, challenges (opportunities), and examples of 2.3D IC integration for chiplet design and heterogeneous integration packaging. Also, some recommendations of 2.3D IC integration will be presented.
A Hybrid Pressure-less Silver Sintering Technology for High-power Density Electronics
Authors: Zhao Yuan , Tolla Bruno , Katze Doug , Castaneda Glenda , Wood John , Wilson Jo-Anne , Brand David 
Published: May 2023

Integration of smaller, higher-functioning devices and use of advanced high thermal chip structures present thermal management challenges in the aerospace sector where reliability is the top priority and fail-safe processes/materials are the standard. As power density increases rapidly, traditional die attaching technology is becoming an increasingly limiting factor in microelectronics packaging for the next generation aerospace and defense systems. This paper introduces an advanced hybrid silver sintering technology, which incorporates ultra-high thermal and electrical performance of silver sintering with high reliability and process friendly of epoxy-based die attach technology. Unlike traditional silver sintering that requires high temperature and pressure, this hybrid sintering paste can be processed without applying any pressures in temperature ranges that are normal in microelectronics packaging processes. This paper presents results of an application study aimed at developing this unique technology in the field of high-power density devices for aerospace applications.
An Organic Package Designer’s Guide to Transitioning to FOWLP and 2.5D Design
Authors: Acito Bill 
Published: May 2023

Many package designers have many years of hands-on experience designing organic FR4/HDI build-up BGA/LGA substrates. We’ve memorized the design guidelines and the substrate fabrication is well understood. We know how to wield our design tools like precision scalpels to get the design completed on-time, on-specification and on budget. Whether it’s flipchip attach, wire bond or a stacked die combo the design methodology is well understood. Then management mentions that the next generation of designs are going to be “heterogeneously integrated”, utilizing new integration platforms such as RDL-based fan-out wafer level and/or interposers. Suddenly, people start mentioning things like “Assembly Design Kits”, “Stream-out”, “sign-off using PDK’s”, multi-pass degassing, seal rings, assembly LVS and HBM stack routing. The suggestion is made that new design tools might be needed – semiconductor P&R tools that only work on Linux and are all TCL/TK script driven. We start doing some research online and attend a conference or two and listen to some of the EDA tool vendors and you could easily arrive at a point where you start to think, “Am I obsolete? Do I really need to learn to use silicon P&R tools? What is “assembly LVS”, multiple-pass degassing and why do my metal planes need to be hatched and offset?” For many of us, the shift in technology can be overwhelming. Do not despair; yes, there is new terminology to understand and many new design techniques to be understood and mastered, as well as a completely new design process and flow. The good news is that this can all be overcome without having to learn silicon P&R design tools. This paper will discuss real-world experiences of organic package substrate designers who have transitioned and mastered RDL-based FOWLP and 2.5D silicon and organic interposer design, while still using (and preserving) the majority of their existing packaged design tools and skills.
A Novel Lead-Free Low-Temperature Solder Paste for Wafer-Level Package Application
Authors: Zhang Hongwen , Richmond Tyler , Harter Tybarius , Prado Diego , Geng Jie , Wang Huaguang 
Published: May 2023

An In-containing low-temperature solder paste (DFLT) has been developed and successfully used in mobile phone board-stacking application. It is now being tried for main-board application, targeting at using lower-temperature reflow profiles but delivering at least the comparable reliability to the mainstream SAC305. The customized drop-shock packages and the daisy-chained WLP256 assemblies were reflowed under a variety of reflow profiles, in which peak temperatures ranged from 200o C up to 240o C. SAC305 has been used as the control leg reflowed under a traditional 240o C peak temperature lead-free reflow profile. The joint morphology changed with the reflow profiles. Under the 200o C peak reflow, hybrid joints were formed in which the mixing zone, dominated by DFLT, was present at the PCB side while the SAC305 ball at the chip side maintained the original morphology. Increasing the reflow peak temperature led to the fully-merged SAC305 ball with DFLT and, finally the formation of the homogeneous joint. Based on the reflow profile, DFLT has shown the drop-shock performance (g-force>6000g) comparable to or substantially better than SAC305, in which 220o C peak reflow allows DFLT having the drop-shock performance more than 90% better than SAC305. Temperature cycling test (TCT) has been done with the profile of -40 to 125o C and 20 minutes dwelling time. Similar to drop-shock, depending on the reflow profiles DFLT has the TCT performance outperforming SAC305. Reflow under a peak temperature of 210o C results in best TCT performance among all profiles. Although the reflow profiles impacts the performance ranking, the failure modes remain the similar for all the assemblies in drop-shock and TCT, respectively.
Modeling the effect of bend radius on the performance of a conformal dual-band mm-wave patch antenna array
Authors: Umar Ashraf , Abdelatty Mohamed Y. , Obeidat Abdullah , Enakerakpo Emuobosan , Alhendi Mohammed , Poliks Mark. D. 
Published: May 2023

There is growing interest in the use of additive manufacturing for the fabrication of RF devices due to fast prototyping capabilities and the use of less material as opposed to traditional fabrication techniques. In addition to the previously mentioned advantages, the aerosol jet printing method in particular allows for the conformal printing of RF components. This work models the effect of the bend radius on the return loss and radiation pattern of a dual-band (28 GHz and 39 GHz) mm wave patch antenna array design that will be aerosol jet printed. The antenna is modeled on a 5-mil thick flexible substrate (PET) and the simulation is run from 27 GHz to 40 GHz using HFSS. The return loss and radiation pattern results of the antenna are compared for various bend radii (0.25 in to 2 in) of the conformal surface the antenna is to be printed upon. Simulation results show a maximum frequency deviation of about 400 MHz on the return loss for the low (28 GHz) frequency band of the antenna when it is bent from a bend radius of 0 in to 2 in.
Development of all new structure of Dicing Die Attach Film (DDAF) for Stealth Dicing and Cool Expansion processes
Authors: Iwaya Wataru , Sato Yosuke , Sakamoto Misaki , Yamagishi Masanori , Saiki Naoya 
Published: May 2023

Mobile devices, including smart phones and tablets, are increasing in complexity and require ever greater amounts of memory storage. In the past the challenge of higher memory densities and increase functionality has been met through miniaturization of device features, but as we reach the physical limits of feature size, packaging is being relied on more and more to achieve the necessary higher densities in memory and additional device functionality. Thin dies reduce overall package height, however, to achieve high memory densities in low profile packages the die attach material must have an even, thin bond line thickness. DAF (Die Attach Film) is an excellent solution. LINTEC developed an all new DDAF (Dicing Die Attach Film) with thinner DAF for CE (Cool Expansion) process. Conventional tape has a large area of exposed DAF surface which creates the risk of wafer and / or equipment contamination if DAF flies off during the CE process. We developed an all-new tape structure which is compatible with the SD (Stealth Dicing) and CE processes. The structure consists of DAF, IB (Intermediate Basefilm), and dicing tape. The diameter of the DAF and IB is close to the wafer diameter size to significantly reduce the risk of DAF separation and ejection during CE. We considered IB to improve DAF separation and it was found that a thinner IB layer is a good approach to separate DAF effectively. We can adjust adhesion between the DAF and the IB by changing the material properties of the IB, as an effective means to control die-fly and pick-up.
Microstructural Characterization of Sn57Bi1Ag Solder Alloy Joints
Authors: Murali Sarangapani , Evonne Lim Yee Weon , Wan Lo Miew , Danila Bayaras Abito , Keong Loke Chee , Ting Lo Yee , Kumar Balasubramanian Senthil , Sungsig SS Kang 
Published: May 2023

Sn57Bi1Ag alloy system meets the basic solderability requirements while reliability of solder is less known. The presence of intermetallics that form at the solder-joint interface and in the bulk solder is the primary reason to cause joint failure on simple loading. Furthermore, dissolution of soldered surface (copper, gold, silver, nickel, etc.) into the solder during reflow alters the composition of the interface leading to the formation of intermetallic phases. The present paper addresses the characterization of low temperature Sn57Bi1Ag solder alloy, its joint interface metallurgy and integrity. Generally, formation of intermetallic phases (Cu3Sn, Cu6Sn5, Ag3Sn, AuSn2, Ni3Sn4, etc.) at the solder-pad interface is in the range of 0.3 to 1.0µm. On thermal ageing at 75°C (0.55Tm), the intermetallic phases grow further up to 2.3µm, particularly CuSn and AuSn phases. In addition, to distributed eutectic tin (Sn) and bismuth (Bi) phases, fine eutectic tin and bismuth phases and primary tin (β-Sn) are also observed. Coarsening of Bi and Sn phases is noticed on thermal ageing (75°C and 100°C). The rate of coarsening increases with the supply of thermal energy promoting Sn/Bi atomic diffusion and movement of eutectic boundaries (grain boundaries). However, the Sn-Bi interface is stable without any significant changes in eutectic structures and its morphologies. The mechanical drop test of the Sn57Bi1Ag solder joint passed 120 drops, characteristic life corresponds to the number of drops for a failure of 63.2%. Evaluated as per JESD22-B111 specification to a maximum peak acceleration of 1500G and half-sine shock pulse duration of 0.5 milliseconds, soldered the alloy to copper OSP surface. The solder joint also passed 1200cycles evaluated at -40 to +125°C. Electrical connectivity of the solder joints soldered to ENIG plated test boards is recorded continuously. Crystallographic orientation of Sn and Bi second phases is observed using electron back scattered diffraction (EBSD) of thermal aged solder joints and are also presented in this paper.
A New Look at Silicon Carbide
Authors: Muscolino Frank 
Published: May 2023

Silicon Carbide, SiC is one of the most widely used materials that plays a critical role in industries such as: aerospace, electronics, industrial furnaces and wear-resistant mechanical parts among others. Although SiC is widely used in electronics and other high technology applications, the metallurgical, abrasive, and refractory industries are dominate by volume. It is only in the last five or six years that SiC has gained a new and important role in the semiconductor industry. SiC has become a key material in the drive towards electrification. It’s unique physical properties, wide band gap, especially, high temperature performance and “ease of manufacturability makes it a key material going forward. The physical properties that make SiC so unique also represent some serious problems to large scale manufacturing of SiC diodes, transistors and modules. SiC is a very tough material, it has a Mohs hardness rating of 9.5 approaching that of diamond. Just as the semiconductor industry needed high quality defect free silicon wafers to move forward, so did the SiC industry. High quality defect free wafers have just come into the market. They are 4 and six wafers that will allow SiC. These boules can be “sliced” in wafers and run on a standard CMOS fabrication process. Next comes the dicing of the wafers into devices. A diamond saw has to be run at a very slow rate to a material almost as hard as the diamond itself. Die attach brings an interesting problem the devices are generally rate at 200+ deg C and voltages >1000W. Standard epoxy and even Au/Si eutectic die attach has issues has issues at these extreme operating conditions. Lastly, the epoxy molding compound has to be capable of withstanding the harsh conditions and not breakdown. These are all challenges that are being met today. This is a continuing story of how the semiconductor industry adapts to ever changing requirements