bluuebunny/crossref_metadata_2025_split huggingface dataset:
An Evaluation of Bath Life Effects on Photoresist Removal for Wafer Level Packaging
Authors: Bahena Joel A. , Tyler Phillip , Taddei John , Sankarapandian Muthumanickam , Prudhomme Jamie , Pillai Karthikeyan , Said Abdullahi , Carr Christopher , Goldfarb Dario , Waskiewicz Chris , Chen Qianwen 
Published: May 2023

With the emergence of 3D integration and wafer level packaging, the pillar bumping process has become a critical processing step. As the process has matured, significant efforts have been made for optimization in terms of both production and cost. This is especially true for photoresist stripping, since thick photoresists are needed to pattern high aspect ratios and must be removed in subsequent steps to expose underlying metal films. In this study, the removal of a thick negative tone photoresist with solder pillar plated wafers were investigated using a dimethyl sulfoxide blend with a quaternary ammonium hydroxide. Emphasis was placed on exploring the feasibility of an extended bath life beyond 7 days. Coupon level beaker tests were used to provide insight into the swelling and dissolution mechanisms with fresh and aged chemistry. Additionally, several chemistries were compared to examine the effect of the quaternary ammonium hydroxide. Based on these findings, chemical aging studies were performed on 300 mm wafers using a highly customizable single wafer processing tool that combined soaking and a high-pressure spray processing to potentially prolong the bath age even further. In addition to stripping efficiency at extended bath life, the compatibly with pillar structures and seed layers is investigated. Results from the study highlight potential methods to extend bath life while maintaining photoresist stripping efficiency.
Development of a Photopolymer-Based Dielectric Nanocomposite for High Resolution Direct-Write Processes
Authors: Piro Yuri , Aerias Christopher , Luce Andrew , Lamport Emily , Li Yibo , Trulli Susan , Akyurtlu Alkim 
Published: May 2023

A UV curable dielectric ink composition, which enables adaptable and high-resolution direct ink writing, is presented. The UV curable dielectric ink composition is designed using non-hazardous, low cost, commercially available ingredients. The ink manufacturing procedure was devised to require only fundamental lab equipment, without the need for complex reaction conditions or harmful processes. The UV dielectric ink composition was engineered to meet a range of direct ink writing application specific needs. These needs include a tailored rheology, cured film rigidity, dielectric performance, and adhesive ability. The versatility of this ink composition is demonstrated through the fabrication of dielectric bridges for printed coplanar waveguides, bare die chip integration, and interconnects between printed circuit board regions.
Advancements, Versatility, and Flexibility of Dual-Layer Material System for Advanced Packaging Applications
Authors: Jones Andy , Bai Dongshun , Koch Matt , Prenger Luke 
Published: May 2023

Integrated circuits (IC) have seen a major shift in development within the past 10-20 years with traditional lithography methods showing a drastic increase in development time for more advanced nodes, as well as an exponential increase in cost to achieve the same performance gains as before. The increase in cost and the decline in development in lithography have resulted in looking at advanced packaging technologies to achieve the same performance gains by changing the way IC design is approached. The look towards advanced packaging technologies for the future in terms of increasing performance for a substantially lower cost has resulted in considering the IC as a system of components working intertwined with each other rather than as individual components. This shift in mindset has resulted in technologies such as system in package (SiP), package on package (PoP), and fan-out wafer-level packaging (FOWLP). One advanced packaging technology that plays a critical role enabling these aforementioned technologies is temporary bond and debond (TB/DB). TB/DB’s crucial role in advanced packaging is due to the enablement of backside processing such as wafer thinning, bumping of the wafer, die stacking, and chemical vapor deposition/physical vapor deposition (CVD/PVD)–type processes by the use of a support carrier wafer. The support carrier wafer also allows for the use of highly warp-prone materials such as epoxy mold compound (EMC), which are critical in FOWLP applications, by reducing the overall warpage of the entire wafer stack. To utilize the support carrier wafer, a robust material solution is required to allow for the wafers to be bonded together and subsequently released after backside processing by one of the primary separation methods of thermal slide, mechanical, or laser debond. Brewer Science has designed and developed a dual-layer temporary bonding system. This system consists of two materials, a thermoplastic layer that is typically coated on the device, and a thermoset layer which is typically coated on the carrier. The materials developed for the dual-layer system demonstrate very good performance in very high temperature applications, EMC wafer handling, and device thinning to sub-20 µm. In this paper, we will summarize their capabilities and introduce how adhesion between the two temporary layers can be adjusted by material design. We will also cover a new feature of the thermoset layer that can be patterned to allow for the use of a patterned bonding material for TB/DB-type applications.
A Novel Printed Circuit Board Laminate for High Frequency Electronics
Authors: Lin James , Owen Geraint , Orsley Tim 
Published: May 2023

A novel PCB material that is advantaged at the 10-100+ GHz range has been developed. It consists of a 3 layer laminate, nominally with a total thickness of 140 microns, and individual laminates can be stacked to make multilayer boards. The outer two layers of the laminate consist of the polymer Topas, 50 microns thick and the middle layer is Corning’s ribbon alumina, 40 microns thick. For brevity, the laminate is called “TAT”. The permittivities of the Topas and alumina are 2.5 and 10 respectively, and that of the 50/40/50 TAT laminate is 3.2 in a direction transverse to the plane of the laminate. The individual loss tangents are about 0.0002, and the loss tangent of the TAT laminate has about the same value. Thus, TAT has significantly lower loss with a lower effective permittivity than other PCB materials currently available. These dielectric properties have been measured experimentally at 10 and 15 GHz. The permittivity and loss tangents can also be predicted accurately using extremely simple analytical formulae. This makes predicting the properties of TAT structures with different dimensions very easy. A TAT strip line has been modeled and found to have an effective permittivity of 2.3. The machining of TAT is somewhat incompatible with conventional PCB shop practice. However, laser drilling and cutting are perfectly practicable. In-house processes have been successfully developed, and an external vendor has also developed these capabilities. Copper sheet adheres strongly to the TAT, and the conductivity of the resulting traces is high. Boards for a 77 GHz radar demonstrate the manufacturability of TAT. Mechanical testing of TAT has been carried out, and the measured flexural modulus and stress at failure compare well with calculations. Environmental tests at 80 °C and 80% humidity indicate that TAT is quite robust. Moreover, it is quite possible that TAT itself may satisfy the UL94 criteria, since the alumina may act as a flame retardant. The feasibility of loading Topas with ceramic or fluoropolymer powders to reduce flammability has been investigated, and it has been found that the addition of these powders causes negligible dielectric loss. In summary, laminates of this type are plausible extreme low loss candidates for PCBs for very advanced applications such as 5G and 6G devices.
Maskless direct write lithography for 3D wafer-level-system-integration
Authors: Windrich Frank , Preuß Sven , Jehle Achim 
Published: May 2023

This publication presents lithography results for 3D wafer-level system integration applications using a reticle free maskless lithography system VPG+ 400 from Heidelberg Instruments. The focus is on high density Cu redistribution layer (RDL) formation with <2µm L/S used in polymer RDL stacks, overlay accuracy determination better than ±150nm and hybrid bond interconnect formation for 2µm interconnects, all processed on 300mm wafer size substrates.
Electromigration Risk Assessment and Circuit Optimization using Innovative Multiphysics Modeling
Authors: Cai Chongyang , Yang Zhi , Li Yuan , Jain Padam , Kang Terry , Mellachervu Krishna 
Published: May 2023

With smaller and denser transistors, the physical flow of electrons may inhibit the performance of the device over time by forming voids and cracks at interconnects due to Electro-Migration (EM). Circuit designs that fail to meet EM specifications may lead to catastrophic failures and SI/PI performance degradation. One way of mitigating EM is to use multiple vias between layers of copper traces to reduce the current crowding effect. However, the quantities of vias may affect the current density and current redistribution inside critical joints. Current studies mainly focus on predicting the EM time-to-failure (TTF) based on the empirical Black’s equation. However, this method may not give enough insights about void formation and crack propagation and reflects the current redistribution that could impact the TTF. In this study, we compared the EM lifetime of Ball Grid Array (BGA) test vehicles with different structural designs and developed a methodology to consider the diffusion of atoms in solder joints based on Multiphysics field migration to study the current redistribution influence of vias. Moreover, crack propagation was also simulated to understand the failure mechanism. BGA traces without vias and with 8 vias are stressed under 5A, 7A, and 9A at 150C to compare the EM performance. Moreover, each test structure is manufactured with two different surface finishes: A and B. Based on the experimental results, Finite Element Analysis (FEA) simulations based on Atom Flux Divergence (AFD) were performed to compare with the experiment results. It was found that the current crowding effect could be significantly reduced by 8 vias compared to daisy chained traces. The study shows better EM resistance with 8 and 4 vias than no-via traces and helps predict the EM life of different structures to provide guidance for design optimization
On Excess CO2 within a Hermetically Sealed 14-Pin Butterfly Package: Solubility of CO2 within Fluorocarbon Liquids
Authors: De Luna Mark M. , Uramoto Todd 
Published: May 2023

In this paper, we examine the presence of excess CO2 found within a hermetically sealed 14-pin butterfly package. Excess CO2 within a hermetically sealed package can suggest that the internal structures of the package have degraded significantly over the lifetime of the package. The level of CO2 discovered within the butterfly package was inconsistent with the controlled sealing gas environmental composition, and the gas composition of concurrently sealed packages. A literature review of industry technical papers and academic studies show that fluorocarbon liquids preferentially absorb CO2 at levels 4-5 times greater than other gasses such as oxygen and nitrogen. Previous experimental and computational methods found that fluorocarbon liquids can absorb CO2 at levels of 1.5-1.6 mol%, which is greater than the calculated maximum amount of absorbed CO2 (0.91 mol%) found within the butterfly package. The Internal Gas Analysis (IGA) of the butterfly package confirmed that it is highly likely that when butterfly package ingested the fluorocarbon liquid, the CO2 was absorbed in solution and thus ingested into the device. Given that the butterfly package was initially filled with 12% ppmv of helium and it retained the helium at a significant level, the phenomenon of a one-way leaker preserved the evidence of CO2 absorbed in the fluorocarbon liquid.
Simulation and Experimental Study on Edge Bonding Shape for Reliable BGA Packages
Authors: Kato Yasuhiko , Hamagami Hiroyuki , Shibata Tomoaki , Seki Kohei , Sato Ryota 
Published: May 2023

In order to ensure thermal reliability including temperature cycling, semiconductor chips and packages mounted on a BGA substrate need a reinforced structure with adhesive resin. In this study, the relationship between reliability and the applied shape of the edge bond (EB) material was verified based on thermal stress simulation and actual experimental results. In consequence, the test vehicle with the cross-sectional area of 0.62 mm2 showed higher reliability than the one of 1.04 mm2 , and maintained the electrical continuity over 3100 cycles. This result showed that there was an optimal cross-sectional area of EB material to obtain high reliability.
A high-uniformity, high-purity copper pillar ECP process with limited acid concentration
Authors: Ye Pingping , Letize Adam , Han Jianwen , Braye Stephan , Kuppersmith Ashley , Whitten Kyle , Richardson Thomas , Najjar Elie 
Published: May 2023

The requirements for wafer-level packaging (WLP) are becoming more and more stringent both from a sustainability perspective and process performance. For instance, there is a demand for continuous process improvement for within die uniformity (WID) and operating in a low acid environment for copper pillar plating. Antagonistic these requests are; however, we must devise novel ECP techniques and additive designs to meet such ambitious targets. The additives consist of an accelerator, suppressor, and leveler. The systematic use of Linear Sweep Voltammetry (LSV) aided the study of the electrochemical response to screen the additives and determine the Wagner number (Wa) in the current density region of interest. In addition, the rigorous use of the Design of Experiment (DOE) enabled us to determine the concentrations for combining this new leveler and suppressor with the accelerator. Owing to designing the right leveler and suppressor, we controlled the free acid concentration at 10% (100 g/L) while maintaining the WID below 2.5% and controlling the within-feature (WIF) less than 1µm (~2.0%), using a deposition rate of approximately 2.0 µm/min, to various wafer patterns with various aspect ratios and layouts. Lastly, the resulting film properties are as crucial as ECP performance. SIMS studies support a deficient level of inclusion in the copper film with a total impurity of 3.1 ppm, including C, O, N, S, and Cl. Therefore, when studied with a solder cap, the Kirkendall void performance was outstanding based on minimal voids post 10X reflow cycles and high-temperature storage. The shear stress test measuring the bonding between the copper and its pad on the wafer is 18.4 gf/mil2.
Board Level Reliability of Flipchip Package
Authors: Lakhera Nishant , Benson Mollie , Mawer Andrew 
Published: May 2023

In the world of electronic materials, solder is a critical material that plays an important role in the first level (silicon to package substrate) and second level (package to printed circuit board) interconnection. As a joining material in electronic assemblies, solder provides electrical and mechanical connections. The increasing need for reliable electronic devices for harsh environment triggers the need for reliable solder joints. This study focuses on reliability of second level interconnections between package and printed circuit boards. Board level temperature cycling and mechanical drop performance of a 15 mm x 15 mm FCBGA test vehicle were evaluated with different package construction (lidded vs non-lidded), and BGA solder alloys (SA1, SA2, and SA3). Daisy chain packages were assembled on 1.0 mm thick PCB. Mounted units were thermally cycled between from -40C to 125C. Additional samples were evaluated in mechanical drop test conditions following JEDEC standards. Results showed that packages with SA2, and SA3 BGA had significantly higher board-level thermal cycling life compared to SA1. The best drop performance was achieved with SA1 solder. The performance trend among different solder alloys was found to be similar between lidded vs non lidded package. However, lidded package showed improved board-level reliability performance compared to a non-lidded package.
Die-embedded packaging using Corning® multi-layered glass
Authors: Kim Choon-Kon , Xiao Yu , Yook Jong-Min , Chang Hyun-Je , Moon Hyung-Soo 
Published: May 2023

Die-embedded (DE) packaging technologies in recent years have ventured into advanced packaging structures, such as fan-out wafer level packages (FOWLPs) or package-on-packages (PoPs). They offer higher density at lower costs, despite many challenges, such as the die-shift and warpage problems often observed during the molding process, caused by the high shrinkage and high coefficients of thermal expansion (CTEs) of the molding materials. This in turn makes it difficult to accurately mount the high-density fine-pitch bumps and adversely affects the overall yield, especially in processes using large-size substrates. Glass, known for its superior dimensional and thermal stability and its low or tunable CTEs, can be advantageous in reducing die-shift and warpages as opposed to other alternative material solutions for the molding process. In this paper, we propose a packaging solution based on a glass substrate incorporating a plurality of precisely dimensioned cavities, with a chip positioned in each cavity to prevent them from shifting during processing. Corning® Adaptive Formed Glass (AFG), a laminate glass with a unique clad/core/clad structure, allows for effectively forming cavities with high dimensional precision and positional accuracies as well as surface flatness through a wet etch process. Using a 0.5mm thick laminate Corning® AFG glass, we successfully designed and fabricated three types of DE packages with lab scale tools at Korea Electronics Technology Institute (KETI): single- and double-sided DE packages, and package-on-packages (POPs). High etching selectivity over 20:1, which was achieved by carefully designing the core and clad glass compositions, enabled a wet-etch cavity forming process with accurate cavity depths and flat bottom surfaces (< ± 2.5μm) with relative ease. A double-sided DE package with a total thickness of 600μm was fabricated with two 125μm-thick IC chips, one embedded on each side of the substrate, and connected by metallized through glass vias (TGVs). A POP measured at 5.1×5.1×1.27 mm3 was also successfully demonstrated by using two built-in double-sided DE packages joined by flip-chip bonding, equivalent to stacking four layers of conventional single-sided DE packages. The double-sided DE packages and POPs presented in this paper are believed to be the world’s first demonstration on glass. The work also manifests the immense potential of Corning® AFG glass in enabling higher density IC packaging and large-size panel-level (or wafer-level) packaging.
Glass Substrate for Co-Packaged Optics
Authors: Brusberg Lars , Zakharian Aramais R. , Grenier Jason R. , Paddock Barry J. , Levesque Daniel W. , Sutton Cliff G. , Force Robin M. , Yeary Lucas W. , Bellman Robert A. , Terwilliger Chad C. , Johnson Betsy J. 
Published: May 2023

Co-packaged optics leads to significant power reduction by placing the electronic and photonic chiplets in a single package. An integrated electro-optical substrate made of glass with optical waveguides, through vias and electrical redistribution layers inside a single-sided cavity enables fine-line electrical routing and low-cost assembly. Existing glass and thin film technologies were evaluated and combined into a single process stream including photonic assembly. Photonic chips with silicon nitride waveguides were optically coupled to integrated low-loss (<0.1 dB/cm) glass waveguides with minimum loss of 0.65 dB achieved by fiducial alignment and pick-and-place assembly.
Development of high performance flip chip ball grid array (FCBGA) packages for automotive application processors
Authors: Sharma Gaurav , Lakhera Nishant , Shantaram Sandeep , Huang Willy 
Published: May 2023

Automobiles have witnessed rapid proliferation of infotainment, driver assistance and autonomous driving features which have led to significant increase in semiconductor content per car. However, this has also required increased integration of device functionality to meet the new automotive requirements for in-vehicle networking, autonomous driving, infotainment, and sensor integration. Advance technology/packages are needed to provide ideal solutions for automotive grade reliability, high electrical performance, and multi-function integration for automotive application processors. To address these requirements, innovative packages including Flip Chip Ball Grid Array (FCBGA) are the potential solutions. In this study FCBGA packages are developed for automotive processor application and qualified for AEC2 qualification tier. To achieve higher performance and reliability, different package substrate materials such as core dielectric and build-up dielectric were evaluated. Mechanical modelling and simulation of package reliability and influence of key material properties such as coefficient of thermal expansion (CTE), modulus of elasticity (E) and glass transition temperature (Tg) was used to provide guidance for the selection of substrate and assembly materials. Developed packages met all the product performance requirements and passed package qual conditions of high temperature storage life (150°C, 500 hours), temperature cycling (-55 °C to 125 °C, 1000 cycles), temperature humidity bias (85 °C, 85% RH, 1000 hours) and board level temperature cycling (-40 °C to 125 °C, 1000 cycles).
Impact of FCBGA substrate stack-up on BLR performance
Authors: Williamson Jaimal , Suzuki Yutaka , Eller Ron 
Published: May 2023

Board level reliability (BLR) temperature cycling is a metric for FCBGA field performance, where it is imperative to understand process variation holistically covering both substrate and / or assembly manufacturing process and its impact to product margin. This study focuses on technical reasoning a common FCBGA design manufactured with an identical substrate material set (i.e. core, dielectric, solder mask), assembly bill-of-materials (i.e. underfill, lid, etc.) and assembly site demonstrated different cycles to first failure during BLR testing. Although results far exceeded JESD22-A104 condition G requirements, BLR performance based on identical substrate designs (manufactured at different points in time) proved TV1 (test vehicle 1) performed ~2x better than its TV2 (test vehicle 2) counterpart. To elucidate the primary factor of the disparity in BLR performance, supplier feedback as well as a detailed package construction analysis ensued to compare build-up substrate layer thickness dimensions between TV1 and TV2. Discovery demonstrated a slightly larger volume of a specific layer in the build-up stack within TV2 that generated a higher degree of out-of-plane displacement as compared to TV1. Reproducing the cycles to first failure with the superior TV1 device via the TV1a and impact of substrate warpage was investigated as a factor in the BLR findings driving root cause.