(Invited) III-V Integration on Silicon for Resource-Efficient Sensor-Technology
Authors: Quay Ruediger , Leuther Arnulf , Chartier Sebastien , John Laurenz , Tessmann Axel 
Published: September 2023

This work deals with the wafer-level integration of advanced group III-V devices and integrated circuits on silicon substrate for RF-sensor integration, such as radar functions a very high frequencies beyond 300 GHz [1]. The aim is to achieve both performance improvements on device level, co-integration with digital functions, and advanced integration to achieve a greener usage of material critical to the environment. Submillimeter-Wave frequency bands beyond 300 GHz allow for broadband transmit and receive windows, serviceable to both communications and radar-based applications—increasing data rates and imaging resolutions, respectively. On the other hand, CMOS co-integration is called for by the data acquisition- and other mixed-mode- and fast digital functions. As examples of the integration schemes Terahertz Monolithic Integrated Circuit amplifiers (TMICs) are implemented in an advanced transferred-substrate InGaAs-channel HEMT technology with 20-nm gate length on silicon. The inverted III-V HEMT heterostructure is grown by molecular beam epitaxy (MBE) on 100-mm semi-isolating GaAs wafers and transferred to silicon substrates by using a SiO2-based wafer bond process with subsequent wafer thinning and removal of the GaAs substrate. Thus, only a 100-nm-thick III-V heterostructure layer is remaining on the Si substrate. This advanced transferred-substrate technology also offers the implementation of HEMT devices with backside gate [2,3] to achieve better sub-threshold slope, or field plates to increase both channel confinement and higher breakdown voltages. The 20-nm InGaAs-OI HEMT technology features typical values for the OFF-state breakdown voltage of 5 V and and maximum drain-current density of 1200 mA/mm, respectively. A maximum transconductance of 2400 mS/mm is achieved. The expected cutoff frequency values fT and fmax are above 500 GHz and 1 THz, respectively [4]. A fully passivated back-end-of-line (BEOL) process is used, including three metal layers (MET1–MET3). A NiCr 50 Ohm sq thin-film-resistor layer, as well as an SiN layer for the implementation of MIM capacitors between MET2 andMET3. S-parameter characteristics of a six-stage and nine-stage TMIC amplifiers in the frequency band from 620 to 730 GHz are given as examples. During the on-wafer characterization, the HEMT devices in cascode configuration have been biased at VD= 2 V (1 V drain–source voltage per device) and a current of 350 mA/mm. The measured small-signal gain of the six-stage cascode TMIC amplifier is in the range of 22–25 dB over the frequency range from 670 to above 700 GHz. This corresponds to 4 dB of gain per cascode stage around the 670-GHz frequency range. A nine-stage TMIC amplifier, on the other hand, achieves at least 30 dB of measured gain from 660 to about 700 GHz. This again corresponds to a gain per stage below 4 dB. Such results prove both the advancements in integration as well as state-of-the-art circuit performance co-integrated on silicon.
References:
[1] B. Gashi et al., "Broadband 400 GHz On-Chip Antenna With a Metastructured Ground Plane and Dielectric Resonator," in IEEE Transactions on Antennas and Propagation, vol. 70, no. 10, pp. 9025-9038, Oct. 2022, doi: 10.1109/TAP.2022.3177527.
[2] A. Tessmann et al., "20-nm In0.8Ga0.2As MOSHEMT MMIC Technology on Silicon," in IEEE Journal of Solid-State Circuits, vol. 54, no. 9, pp. 2411-2418, Sept. 2019, doi: 10.1109/JSSC.2019.2915161.
[3] A. Leuther et al., "InGaAs HEMT MMIC Technology on Silicon Substrate with Backside Field-Plate," 2020 50th European Microwave Conference (EuMC), 2021, pp. 187-190, doi: 10.23919/EuMC48046.2021.9337957.
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